drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54 #include <rte_tailq.h>
  55 #include <rte_hash_crc.h>
  56
  57 #include "i40e_logs.h"
  58 #include "base/i40e_prototype.h"
  59 #include "base/i40e_adminq_cmd.h"
  60 #include "base/i40e_type.h"
  61 #include "base/i40e_register.h"
  62 #include "base/i40e_dcb.h"
  63 #include "i40e_ethdev.h"
  64 #include "i40e_rxtx.h"
  65 #include "i40e_pf.h"
  66 #include "i40e_regs.h"
  67 #include "rte_pmd_i40e.h"
  68
  69 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  70 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  71
  72 #define I40E_CLEAR_PXE_WAIT_MS     200
  73
  74 /* Maximun number of capability elements */
  75 #define I40E_MAX_CAP_ELE_NUM       128
  76
  77 /* Wait count and inteval */
  78 #define I40E_CHK_Q_ENA_COUNT       1000
  79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  80
  81 /* Maximun number of VSI */
  82 #define I40E_MAX_NUM_VSIS          (384UL)
  83
  84 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  85
  86 /* Flow control default timer */
  87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  88
  89 /* Flow control default high water */
  90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  91
  92 /* Flow control default low water */
  93 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  94
  95 /* Flow control enable fwd bit */
  96 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  97
  98 /* Receive Packet Buffer size */
  99 #define I40E_RXPBSIZE (968 * 1024)
 100
 101 /* Kilobytes shift */
 102 #define I40E_KILOSHIFT 10
 103
 104 /* Receive Average Packet Size in Byte*/
 105 #define I40E_PACKET_AVERAGE_SIZE 128
 106
 107 /* Mask of PF interrupt causes */
 108 #define I40E_PFINT_ICR0_ENA_MASK ( \
 109                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 113                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 /* Additional timesync values. */
 133 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 134 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 135 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 136 #define I40E_PRTTSYN_TSYNENA     0x80000000
 137 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 138 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 139
 140 #define I40E_MAX_PERCENT            100
 141 #define I40E_DEFAULT_DCB_APP_NUM    1
 142 #define I40E_DEFAULT_DCB_APP_PRIO   3
 143
 144 /**
 145  * Below are values for writing un-exposed registers suggested
 146  * by silicon experts
 147  */
 148 /* Destination MAC address */
 149 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 150 /* Source MAC address */
 151 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 155 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 156 /* Single VLAN tag in the inner L2 header */
 157 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 158 /* Source IPv4 address */
 159 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 160 /* Destination IPv4 address */
 161 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 162 /* Source IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 164 /* Destination IPv4 address for X722 */
 165 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 166 /* IPv4 Protocol for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 168 /* IPv4 Time to Live for X722 */
 169 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 170 /* IPv4 Type of Service (TOS) */
 171 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 172 /* IPv4 Protocol */
 173 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 174 /* IPv4 Time to Live */
 175 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 176 /* Source IPv6 address */
 177 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 178 /* Destination IPv6 address */
 179 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 180 /* IPv6 Traffic Class (TC) */
 181 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 182 /* IPv6 Next Header */
 183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 184 /* IPv6 Hop Limit */
 185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 186 /* Source L4 port */
 187 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 188 /* Destination L4 port */
 189 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 190 /* SCTP verification tag */
 191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 194 /* Source port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 196 /* Destination port of tunneling UDP */
 197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 198 /* UDP Tunneling ID, NVGRE/GRE key */
 199 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 200 /* Last ether type */
 201 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 202 /* Tunneling outer destination IPv4 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 204 /* Tunneling outer destination IPv6 address */
 205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 206 /* 1st word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 208 /* 2nd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 210 /* 3rd word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 212 /* 4th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 214 /* 5th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 216 /* 6th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 218 /* 7th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 220 /* 8th word of flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 222 /* all 8 words flex payload */
 223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 224 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 225
 226 #define I40E_TRANSLATE_INSET 0
 227 #define I40E_TRANSLATE_REG   1
 228
 229 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 230 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 231 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 232 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 234 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 235
 236 /* PCI offset for querying capability */
 237 #define PCI_DEV_CAP_REG            0xA4
 238 /* PCI offset for enabling/disabling Extended Tag */
 239 #define PCI_DEV_CTRL_REG           0xA8
 240 /* Bit mask of Extended Tag capability */
 241 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 242 /* Bit shift of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 244 /* Bit mask of Extended Tag enable/disable */
 245 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 246
 247 /* The max bandwidth of i40e is 40Gbps. */
 248 #define I40E_QOS_BW_MAX 40000
 249 /* The bandwidth should be the multiple of 50Mbps. */
 250 #define I40E_QOS_BW_GRANULARITY 50
 251 /* The min bandwidth weight is 1. */
 252 #define I40E_QOS_BW_WEIGHT_MIN 1
 253 /* The max bandwidth weight is 127. */
 254 #define I40E_QOS_BW_WEIGHT_MAX 127
 255
 256 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 257 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 258 static int i40e_dev_configure(struct rte_eth_dev *dev);
 259 static int i40e_dev_start(struct rte_eth_dev *dev);
 260 static void i40e_dev_stop(struct rte_eth_dev *dev);
 261 static void i40e_dev_close(struct rte_eth_dev *dev);
 262 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 263 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 264 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 265 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 266 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 267 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 268 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 269                                struct rte_eth_stats *stats);
 270 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 271                                struct rte_eth_xstat *xstats, unsigned n);
 272 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 273                                      struct rte_eth_xstat_name *xstats_names,
 274                                      unsigned limit);
 275 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 276 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 277                                             uint16_t queue_id,
 278                                             uint8_t stat_idx,
 279                                             uint8_t is_rx);
 280 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 281                                 char *fw_version, size_t fw_size);
 282 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 283                               struct rte_eth_dev_info *dev_info);
 284 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 285                                 uint16_t vlan_id,
 286                                 int on);
 287 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 288                               enum rte_vlan_type vlan_type,
 289                               uint16_t tpid);
 290 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 291 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 292                                       uint16_t queue,
 293                                       int on);
 294 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 295 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 296 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 297 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 298                               struct rte_eth_fc_conf *fc_conf);
 299 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 300                               struct rte_eth_fc_conf *fc_conf);
 301 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 302                                        struct rte_eth_pfc_conf *pfc_conf);
 303 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 304                           struct ether_addr *mac_addr,
 305                           uint32_t index,
 306                           uint32_t pool);
 307 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 308 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 309                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 310                                     uint16_t reta_size);
 311 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 312                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 313                                    uint16_t reta_size);
 314
 315 static int i40e_get_cap(struct i40e_hw *hw);
 316 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 317 static int i40e_pf_setup(struct i40e_pf *pf);
 318 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 319 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 320 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 321 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 322 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 323                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 324 static void i40e_stat_update_48(struct i40e_hw *hw,
 325                                uint32_t hireg,
 326                                uint32_t loreg,
 327                                bool offset_loaded,
 328                                uint64_t *offset,
 329                                uint64_t *stat);
 330 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 331 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 332                                        void *param);
 333 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 334                                 uint32_t base, uint32_t num);
 335 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 336 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 337                         uint32_t base);
 338 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 339                         uint16_t num);
 340 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 341 static int i40e_veb_release(struct i40e_veb *veb);
 342 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 343                                                 struct i40e_vsi *vsi);
 344 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 345 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 346 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 347                                              struct i40e_macvlan_filter *mv_f,
 348                                              int num,
 349                                              struct ether_addr *addr);
 350 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 351                                              struct i40e_macvlan_filter *mv_f,
 352                                              int num,
 353                                              uint16_t vlan);
 354 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 355 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 356                                     struct rte_eth_rss_conf *rss_conf);
 357 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 358                                       struct rte_eth_rss_conf *rss_conf);
 359 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 360                                         struct rte_eth_udp_tunnel *udp_tunnel);
 361 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 362                                         struct rte_eth_udp_tunnel *udp_tunnel);
 363 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 364 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 365                                 enum rte_filter_op filter_op,
 366                                 void *arg);
 367 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 368                                 enum rte_filter_type filter_type,
 369                                 enum rte_filter_op filter_op,
 370                                 void *arg);
 371 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 372                                   struct rte_eth_dcb_info *dcb_info);
 373 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 374 static void i40e_configure_registers(struct i40e_hw *hw);
 375 static void i40e_hw_init(struct rte_eth_dev *dev);
 376 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 377 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 378                         struct rte_eth_mirror_conf *mirror_conf,
 379                         uint8_t sw_id, uint8_t on);
 380 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 381
 382 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 383 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 384 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 385                                            struct timespec *timestamp,
 386                                            uint32_t flags);
 387 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 388                                            struct timespec *timestamp);
 389 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 390
 391 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 392
 393 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 394                                    struct timespec *timestamp);
 395 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 396                                     const struct timespec *timestamp);
 397
 398 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 399                                          uint16_t queue_id);
 400 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 401                                           uint16_t queue_id);
 402
 403 static int i40e_get_regs(struct rte_eth_dev *dev,
 404                          struct rte_dev_reg_info *regs);
 405
 406 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 407
 408 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 409                            struct rte_dev_eeprom_info *eeprom);
 410
 411 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 412                                       struct ether_addr *mac_addr);
 413
 414 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 415
 416 static int i40e_ethertype_filter_convert(
 417         const struct rte_eth_ethertype_filter *input,
 418         struct i40e_ethertype_filter *filter);
 419 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 420                                    struct i40e_ethertype_filter *filter);
 421
 422 static int i40e_tunnel_filter_convert(
 423         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 424         struct i40e_tunnel_filter *tunnel_filter);
 425 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 426                                 struct i40e_tunnel_filter *tunnel_filter);
 427 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 428
 429 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 430 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 431 static void i40e_filter_restore(struct i40e_pf *pf);
 432
 433 int i40e_logtype_init;
 434 int i40e_logtype_driver;
 435
 436 static const struct rte_pci_id pci_id_i40e_map[] = {
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 447         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 448         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 449         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 450         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 451         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 452         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 453         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 454         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 455         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 456         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 457         { .vendor_id = 0, /* sentinel */ },
 458 };
 459
 460 static const struct eth_dev_ops i40e_eth_dev_ops = {
 461         .dev_configure                = i40e_dev_configure,
 462         .dev_start                    = i40e_dev_start,
 463         .dev_stop                     = i40e_dev_stop,
 464         .dev_close                    = i40e_dev_close,
 465         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 466         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 467         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 468         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 469         .dev_set_link_up              = i40e_dev_set_link_up,
 470         .dev_set_link_down            = i40e_dev_set_link_down,
 471         .link_update                  = i40e_dev_link_update,
 472         .stats_get                    = i40e_dev_stats_get,
 473         .xstats_get                   = i40e_dev_xstats_get,
 474         .xstats_get_names             = i40e_dev_xstats_get_names,
 475         .stats_reset                  = i40e_dev_stats_reset,
 476         .xstats_reset                 = i40e_dev_stats_reset,
 477         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 478         .fw_version_get               = i40e_fw_version_get,
 479         .dev_infos_get                = i40e_dev_info_get,
 480         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 481         .vlan_filter_set              = i40e_vlan_filter_set,
 482         .vlan_tpid_set                = i40e_vlan_tpid_set,
 483         .vlan_offload_set             = i40e_vlan_offload_set,
 484         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 485         .vlan_pvid_set                = i40e_vlan_pvid_set,
 486         .rx_queue_start               = i40e_dev_rx_queue_start,
 487         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 488         .tx_queue_start               = i40e_dev_tx_queue_start,
 489         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 490         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 491         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 492         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 493         .rx_queue_release             = i40e_dev_rx_queue_release,
 494         .rx_queue_count               = i40e_dev_rx_queue_count,
 495         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 496         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 497         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 498         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 499         .tx_queue_release             = i40e_dev_tx_queue_release,
 500         .dev_led_on                   = i40e_dev_led_on,
 501         .dev_led_off                  = i40e_dev_led_off,
 502         .flow_ctrl_get                = i40e_flow_ctrl_get,
 503         .flow_ctrl_set                = i40e_flow_ctrl_set,
 504         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 505         .mac_addr_add                 = i40e_macaddr_add,
 506         .mac_addr_remove              = i40e_macaddr_remove,
 507         .reta_update                  = i40e_dev_rss_reta_update,
 508         .reta_query                   = i40e_dev_rss_reta_query,
 509         .rss_hash_update              = i40e_dev_rss_hash_update,
 510         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 511         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 512         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 513         .filter_ctrl                  = i40e_dev_filter_ctrl,
 514         .rxq_info_get                 = i40e_rxq_info_get,
 515         .txq_info_get                 = i40e_txq_info_get,
 516         .mirror_rule_set              = i40e_mirror_rule_set,
 517         .mirror_rule_reset            = i40e_mirror_rule_reset,
 518         .timesync_enable              = i40e_timesync_enable,
 519         .timesync_disable             = i40e_timesync_disable,
 520         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 521         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 522         .get_dcb_info                 = i40e_dev_get_dcb_info,
 523         .timesync_adjust_time         = i40e_timesync_adjust_time,
 524         .timesync_read_time           = i40e_timesync_read_time,
 525         .timesync_write_time          = i40e_timesync_write_time,
 526         .get_reg                      = i40e_get_regs,
 527         .get_eeprom_length            = i40e_get_eeprom_length,
 528         .get_eeprom                   = i40e_get_eeprom,
 529         .mac_addr_set                 = i40e_set_default_mac_addr,
 530         .mtu_set                      = i40e_dev_mtu_set,
 531 };
 532
 533 /* store statistics names and its offset in stats structure */
 534 struct rte_i40e_xstats_name_off {
 535         char name[RTE_ETH_XSTATS_NAME_SIZE];
 536         unsigned offset;
 537 };
 538
 539 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 540         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 541         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 542         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 543         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 544         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 545                 rx_unknown_protocol)},
 546         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 547         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 548         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 549         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 550 };
 551
 552 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 553                 sizeof(rte_i40e_stats_strings[0]))
 554
 555 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 556         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 557                 tx_dropped_link_down)},
 558         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 559         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 560                 illegal_bytes)},
 561         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 562         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 563                 mac_local_faults)},
 564         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 565                 mac_remote_faults)},
 566         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 567                 rx_length_errors)},
 568         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 569         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 570         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 571         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 572         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 573         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_127)},
 575         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 576                 rx_size_255)},
 577         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 578                 rx_size_511)},
 579         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 580                 rx_size_1023)},
 581         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 582                 rx_size_1522)},
 583         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 584                 rx_size_big)},
 585         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 586                 rx_undersize)},
 587         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 588                 rx_oversize)},
 589         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 590                 mac_short_packet_dropped)},
 591         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 592                 rx_fragments)},
 593         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 594         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 595         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_127)},
 597         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 598                 tx_size_255)},
 599         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 600                 tx_size_511)},
 601         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 602                 tx_size_1023)},
 603         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 604                 tx_size_1522)},
 605         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 606                 tx_size_big)},
 607         {"rx_flow_director_atr_match_packets",
 608                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 609         {"rx_flow_director_sb_match_packets",
 610                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 611         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 612                 tx_lpi_status)},
 613         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 614                 rx_lpi_status)},
 615         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 616                 tx_lpi_count)},
 617         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 618                 rx_lpi_count)},
 619 };
 620
 621 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 622                 sizeof(rte_i40e_hw_port_strings[0]))
 623
 624 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 625         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_rx)},
 627         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xoff_rx)},
 629 };
 630
 631 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 632                 sizeof(rte_i40e_rxq_prio_strings[0]))
 633
 634 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 635         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 636                 priority_xon_tx)},
 637         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 638                 priority_xoff_tx)},
 639         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 640                 priority_xon_2_xoff)},
 641 };
 642
 643 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 644                 sizeof(rte_i40e_txq_prio_strings[0]))
 645
 646 static struct eth_driver rte_i40e_pmd = {
 647         .pci_drv = {
 648                 .id_table = pci_id_i40e_map,
 649                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 650                 .probe = rte_eth_dev_pci_probe,
 651                 .remove = rte_eth_dev_pci_remove,
 652         },
 653         .eth_dev_init = eth_i40e_dev_init,
 654         .eth_dev_uninit = eth_i40e_dev_uninit,
 655         .dev_private_size = sizeof(struct i40e_adapter),
 656 };
 657
 658 static inline int
 659 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 660                                      struct rte_eth_link *link)
 661 {
 662         struct rte_eth_link *dst = link;
 663         struct rte_eth_link *src = &(dev->data->dev_link);
 664
 665         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 666                                         *(uint64_t *)src) == 0)
 667                 return -1;
 668
 669         return 0;
 670 }
 671
 672 static inline int
 673 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 674                                       struct rte_eth_link *link)
 675 {
 676         struct rte_eth_link *dst = &(dev->data->dev_link);
 677         struct rte_eth_link *src = link;
 678
 679         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 680                                         *(uint64_t *)src) == 0)
 681                 return -1;
 682
 683         return 0;
 684 }
 685
 686 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 687 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 688 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 689
 690 #ifndef I40E_GLQF_ORT
 691 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 692 #endif
 693 #ifndef I40E_GLQF_PIT
 694 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 695 #endif
 696 #ifndef I40E_GLQF_L3_MAP
 697 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 698 #endif
 699
 700 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 701 {
 702         /*
 703          * Initialize registers for flexible payload, which should be set by NVM.
 704          * This should be removed from code once it is fixed in NVM.
 705          */
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 711         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 712         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 713         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 714         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 715         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 716         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 717         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 718
 719         /* Initialize registers for parsing packet type of QinQ */
 720         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 721         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 722 }
 723
 724 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 725
 726 /*
 727  * Add a ethertype filter to drop all flow control frames transmitted
 728  * from VSIs.
 729 */
 730 static void
 731 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 732 {
 733         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 734         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 735                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 736                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 737         int ret;
 738
 739         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 740                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 741                                 pf->main_vsi_seid, 0,
 742                                 TRUE, NULL, NULL);
 743         if (ret)
 744                 PMD_INIT_LOG(ERR,
 745                         "Failed to add filter to drop flow control frames from VSIs.");
 746 }
 747
 748 static int
 749 floating_veb_list_handler(__rte_unused const char *key,
 750                           const char *floating_veb_value,
 751                           void *opaque)
 752 {
 753         int idx = 0;
 754         unsigned int count = 0;
 755         char *end = NULL;
 756         int min, max;
 757         bool *vf_floating_veb = opaque;
 758
 759         while (isblank(*floating_veb_value))
 760                 floating_veb_value++;
 761
 762         /* Reset floating VEB configuration for VFs */
 763         for (idx = 0; idx < I40E_MAX_VF; idx++)
 764                 vf_floating_veb[idx] = false;
 765
 766         min = I40E_MAX_VF;
 767         do {
 768                 while (isblank(*floating_veb_value))
 769                         floating_veb_value++;
 770                 if (*floating_veb_value == '\0')
 771                         return -1;
 772                 errno = 0;
 773                 idx = strtoul(floating_veb_value, &end, 10);
 774                 if (errno || end == NULL)
 775                         return -1;
 776                 while (isblank(*end))
 777                         end++;
 778                 if (*end == '-') {
 779                         min = idx;
 780                 } else if ((*end == ';') || (*end == '\0')) {
 781                         max = idx;
 782                         if (min == I40E_MAX_VF)
 783                                 min = idx;
 784                         if (max >= I40E_MAX_VF)
 785                                 max = I40E_MAX_VF - 1;
 786                         for (idx = min; idx <= max; idx++) {
 787                                 vf_floating_veb[idx] = true;
 788                                 count++;
 789                         }
 790                         min = I40E_MAX_VF;
 791                 } else {
 792                         return -1;
 793                 }
 794                 floating_veb_value = end + 1;
 795         } while (*end != '\0');
 796
 797         if (count == 0)
 798                 return -1;
 799
 800         return 0;
 801 }
 802
 803 static void
 804 config_vf_floating_veb(struct rte_devargs *devargs,
 805                        uint16_t floating_veb,
 806                        bool *vf_floating_veb)
 807 {
 808         struct rte_kvargs *kvlist;
 809         int i;
 810         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 811
 812         if (!floating_veb)
 813                 return;
 814         /* All the VFs attach to the floating VEB by default
 815          * when the floating VEB is enabled.
 816          */
 817         for (i = 0; i < I40E_MAX_VF; i++)
 818                 vf_floating_veb[i] = true;
 819
 820         if (devargs == NULL)
 821                 return;
 822
 823         kvlist = rte_kvargs_parse(devargs->args, NULL);
 824         if (kvlist == NULL)
 825                 return;
 826
 827         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 828                 rte_kvargs_free(kvlist);
 829                 return;
 830         }
 831         /* When the floating_veb_list parameter exists, all the VFs
 832          * will attach to the legacy VEB firstly, then configure VFs
 833          * to the floating VEB according to the floating_veb_list.
 834          */
 835         if (rte_kvargs_process(kvlist, floating_veb_list,
 836                                floating_veb_list_handler,
 837                                vf_floating_veb) < 0) {
 838                 rte_kvargs_free(kvlist);
 839                 return;
 840         }
 841         rte_kvargs_free(kvlist);
 842 }
 843
 844 static int
 845 i40e_check_floating_handler(__rte_unused const char *key,
 846                             const char *value,
 847                             __rte_unused void *opaque)
 848 {
 849         if (strcmp(value, "1"))
 850                 return -1;
 851
 852         return 0;
 853 }
 854
 855 static int
 856 is_floating_veb_supported(struct rte_devargs *devargs)
 857 {
 858         struct rte_kvargs *kvlist;
 859         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 860
 861         if (devargs == NULL)
 862                 return 0;
 863
 864         kvlist = rte_kvargs_parse(devargs->args, NULL);
 865         if (kvlist == NULL)
 866                 return 0;
 867
 868         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 869                 rte_kvargs_free(kvlist);
 870                 return 0;
 871         }
 872         /* Floating VEB is enabled when there's key-value:
 873          * enable_floating_veb=1
 874          */
 875         if (rte_kvargs_process(kvlist, floating_veb_key,
 876                                i40e_check_floating_handler, NULL) < 0) {
 877                 rte_kvargs_free(kvlist);
 878                 return 0;
 879         }
 880         rte_kvargs_free(kvlist);
 881
 882         return 1;
 883 }
 884
 885 static void
 886 config_floating_veb(struct rte_eth_dev *dev)
 887 {
 888         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 889         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 890         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 891
 892         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 893
 894         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 895                 pf->floating_veb =
 896                         is_floating_veb_supported(pci_dev->device.devargs);
 897                 config_vf_floating_veb(pci_dev->device.devargs,
 898                                        pf->floating_veb,
 899                                        pf->floating_veb_list);
 900         } else {
 901                 pf->floating_veb = false;
 902         }
 903 }
 904
 905 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 906 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 907
 908 static int
 909 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 910 {
 911         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 912         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 913         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 914         int ret;
 915
 916         struct rte_hash_parameters ethertype_hash_params = {
 917                 .name = ethertype_hash_name,
 918                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 919                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 920                 .hash_func = rte_hash_crc,
 921                 .hash_func_init_val = 0,
 922                 .socket_id = rte_socket_id(),
 923         };
 924
 925         /* Initialize ethertype filter rule list and hash */
 926         TAILQ_INIT(&ethertype_rule->ethertype_list);
 927         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 928                  "ethertype_%s", dev->data->name);
 929         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 930         if (!ethertype_rule->hash_table) {
 931                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 932                 return -EINVAL;
 933         }
 934         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 935                                        sizeof(struct i40e_ethertype_filter *) *
 936                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 937                                        0);
 938         if (!ethertype_rule->hash_map) {
 939                 PMD_INIT_LOG(ERR,
 940                              "Failed to allocate memory for ethertype hash map!");
 941                 ret = -ENOMEM;
 942                 goto err_ethertype_hash_map_alloc;
 943         }
 944
 945         return 0;
 946
 947 err_ethertype_hash_map_alloc:
 948         rte_hash_free(ethertype_rule->hash_table);
 949
 950         return ret;
 951 }
 952
 953 static int
 954 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 955 {
 956         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 957         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 958         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 959         int ret;
 960
 961         struct rte_hash_parameters tunnel_hash_params = {
 962                 .name = tunnel_hash_name,
 963                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 964                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 965                 .hash_func = rte_hash_crc,
 966                 .hash_func_init_val = 0,
 967                 .socket_id = rte_socket_id(),
 968         };
 969
 970         /* Initialize tunnel filter rule list and hash */
 971         TAILQ_INIT(&tunnel_rule->tunnel_list);
 972         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 973                  "tunnel_%s", dev->data->name);
 974         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 975         if (!tunnel_rule->hash_table) {
 976                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 977                 return -EINVAL;
 978         }
 979         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 980                                     sizeof(struct i40e_tunnel_filter *) *
 981                                     I40E_MAX_TUNNEL_FILTER_NUM,
 982                                     0);
 983         if (!tunnel_rule->hash_map) {
 984                 PMD_INIT_LOG(ERR,
 985                              "Failed to allocate memory for tunnel hash map!");
 986                 ret = -ENOMEM;
 987                 goto err_tunnel_hash_map_alloc;
 988         }
 989
 990         return 0;
 991
 992 err_tunnel_hash_map_alloc:
 993         rte_hash_free(tunnel_rule->hash_table);
 994
 995         return ret;
 996 }
 997
 998 static int
 999 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1000 {
1001         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1002         struct i40e_fdir_info *fdir_info = &pf->fdir;
1003         char fdir_hash_name[RTE_HASH_NAMESIZE];
1004         int ret;
1005
1006         struct rte_hash_parameters fdir_hash_params = {
1007                 .name = fdir_hash_name,
1008                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1009                 .key_len = sizeof(struct rte_eth_fdir_input),
1010                 .hash_func = rte_hash_crc,
1011                 .hash_func_init_val = 0,
1012                 .socket_id = rte_socket_id(),
1013         };
1014
1015         /* Initialize flow director filter rule list and hash */
1016         TAILQ_INIT(&fdir_info->fdir_list);
1017         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1018                  "fdir_%s", dev->data->name);
1019         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1020         if (!fdir_info->hash_table) {
1021                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1022                 return -EINVAL;
1023         }
1024         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1025                                           sizeof(struct i40e_fdir_filter *) *
1026                                           I40E_MAX_FDIR_FILTER_NUM,
1027                                           0);
1028         if (!fdir_info->hash_map) {
1029                 PMD_INIT_LOG(ERR,
1030                              "Failed to allocate memory for fdir hash map!");
1031                 ret = -ENOMEM;
1032                 goto err_fdir_hash_map_alloc;
1033         }
1034         return 0;
1035
1036 err_fdir_hash_map_alloc:
1037         rte_hash_free(fdir_info->hash_table);
1038
1039         return ret;
1040 }
1041
1042 static int
1043 eth_i40e_dev_init(struct rte_eth_dev *dev)
1044 {
1045         struct rte_pci_device *pci_dev;
1046         struct rte_intr_handle *intr_handle;
1047         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1048         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1049         struct i40e_vsi *vsi;
1050         int ret;
1051         uint32_t len;
1052         uint8_t aq_fail = 0;
1053
1054         PMD_INIT_FUNC_TRACE();
1055
1056         dev->dev_ops = &i40e_eth_dev_ops;
1057         dev->rx_pkt_burst = i40e_recv_pkts;
1058         dev->tx_pkt_burst = i40e_xmit_pkts;
1059         dev->tx_pkt_prepare = i40e_prep_pkts;
1060
1061         /* for secondary processes, we don't initialise any further as primary
1062          * has already done this work. Only check we don't need a different
1063          * RX function */
1064         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1065                 i40e_set_rx_function(dev);
1066                 i40e_set_tx_function(dev);
1067                 return 0;
1068         }
1069         pci_dev = I40E_DEV_TO_PCI(dev);
1070         intr_handle = &pci_dev->intr_handle;
1071
1072         rte_eth_copy_pci_info(dev, pci_dev);
1073         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1074
1075         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1076         pf->adapter->eth_dev = dev;
1077         pf->dev_data = dev->data;
1078
1079         hw->back = I40E_PF_TO_ADAPTER(pf);
1080         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1081         if (!hw->hw_addr) {
1082                 PMD_INIT_LOG(ERR,
1083                         "Hardware is not available, as address is NULL");
1084                 return -ENODEV;
1085         }
1086
1087         hw->vendor_id = pci_dev->id.vendor_id;
1088         hw->device_id = pci_dev->id.device_id;
1089         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1090         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1091         hw->bus.device = pci_dev->addr.devid;
1092         hw->bus.func = pci_dev->addr.function;
1093         hw->adapter_stopped = 0;
1094
1095         /* Make sure all is clean before doing PF reset */
1096         i40e_clear_hw(hw);
1097
1098         /* Initialize the hardware */
1099         i40e_hw_init(dev);
1100
1101         /* Reset here to make sure all is clean for each PF */
1102         ret = i40e_pf_reset(hw);
1103         if (ret) {
1104                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1105                 return ret;
1106         }
1107
1108         /* Initialize the shared code (base driver) */
1109         ret = i40e_init_shared_code(hw);
1110         if (ret) {
1111                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1112                 return ret;
1113         }
1114
1115         /*
1116          * To work around the NVM issue, initialize registers
1117          * for flexible payload and packet type of QinQ by
1118          * software. It should be removed once issues are fixed
1119          * in NVM.
1120          */
1121         i40e_GLQF_reg_init(hw);
1122
1123         /* Initialize the input set for filters (hash and fd) to default value */
1124         i40e_filter_input_set_init(pf);
1125
1126         /* Initialize the parameters for adminq */
1127         i40e_init_adminq_parameter(hw);
1128         ret = i40e_init_adminq(hw);
1129         if (ret != I40E_SUCCESS) {
1130                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1131                 return -EIO;
1132         }
1133         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1134                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1135                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1136                      ((hw->nvm.version >> 12) & 0xf),
1137                      ((hw->nvm.version >> 4) & 0xff),
1138                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1139
1140         /* initialise the L3_MAP register */
1141         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1142                                    0x00000028,  NULL);
1143         if (ret)
1144                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1145
1146         /* Need the special FW version to support floating VEB */
1147         config_floating_veb(dev);
1148         /* Clear PXE mode */
1149         i40e_clear_pxe_mode(hw);
1150         ret = i40e_dev_sync_phy_type(hw);
1151         if (ret) {
1152                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1153                 goto err_sync_phy_type;
1154         }
1155         /*
1156          * On X710, performance number is far from the expectation on recent
1157          * firmware versions. The fix for this issue may not be integrated in
1158          * the following firmware version. So the workaround in software driver
1159          * is needed. It needs to modify the initial values of 3 internal only
1160          * registers. Note that the workaround can be removed when it is fixed
1161          * in firmware in the future.
1162          */
1163         i40e_configure_registers(hw);
1164
1165         /* Get hw capabilities */
1166         ret = i40e_get_cap(hw);
1167         if (ret != I40E_SUCCESS) {
1168                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1169                 goto err_get_capabilities;
1170         }
1171
1172         /* Initialize parameters for PF */
1173         ret = i40e_pf_parameter_init(dev);
1174         if (ret != 0) {
1175                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1176                 goto err_parameter_init;
1177         }
1178
1179         /* Initialize the queue management */
1180         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1181         if (ret < 0) {
1182                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1183                 goto err_qp_pool_init;
1184         }
1185         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1186                                 hw->func_caps.num_msix_vectors - 1);
1187         if (ret < 0) {
1188                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1189                 goto err_msix_pool_init;
1190         }
1191
1192         /* Initialize lan hmc */
1193         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1194                                 hw->func_caps.num_rx_qp, 0, 0);
1195         if (ret != I40E_SUCCESS) {
1196                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1197                 goto err_init_lan_hmc;
1198         }
1199
1200         /* Configure lan hmc */
1201         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1202         if (ret != I40E_SUCCESS) {
1203                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1204                 goto err_configure_lan_hmc;
1205         }
1206
1207         /* Get and check the mac address */
1208         i40e_get_mac_addr(hw, hw->mac.addr);
1209         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1210                 PMD_INIT_LOG(ERR, "mac address is not valid");
1211                 ret = -EIO;
1212                 goto err_get_mac_addr;
1213         }
1214         /* Copy the permanent MAC address */
1215         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1216                         (struct ether_addr *) hw->mac.perm_addr);
1217
1218         /* Disable flow control */
1219         hw->fc.requested_mode = I40E_FC_NONE;
1220         i40e_set_fc(hw, &aq_fail, TRUE);
1221
1222         /* Set the global registers with default ether type value */
1223         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1224         if (ret != I40E_SUCCESS) {
1225                 PMD_INIT_LOG(ERR,
1226                         "Failed to set the default outer VLAN ether type");
1227                 goto err_setup_pf_switch;
1228         }
1229
1230         /* PF setup, which includes VSI setup */
1231         ret = i40e_pf_setup(pf);
1232         if (ret) {
1233                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1234                 goto err_setup_pf_switch;
1235         }
1236
1237         /* reset all stats of the device, including pf and main vsi */
1238         i40e_dev_stats_reset(dev);
1239
1240         vsi = pf->main_vsi;
1241
1242         /* Disable double vlan by default */
1243         i40e_vsi_config_double_vlan(vsi, FALSE);
1244
1245         /* Disable S-TAG identification when floating_veb is disabled */
1246         if (!pf->floating_veb) {
1247                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1248                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1249                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1250                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1251                 }
1252         }
1253
1254         if (!vsi->max_macaddrs)
1255                 len = ETHER_ADDR_LEN;
1256         else
1257                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1258
1259         /* Should be after VSI initialized */
1260         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1261         if (!dev->data->mac_addrs) {
1262                 PMD_INIT_LOG(ERR,
1263                         "Failed to allocated memory for storing mac address");
1264                 goto err_mac_alloc;
1265         }
1266         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1267                                         &dev->data->mac_addrs[0]);
1268
1269         /* Init dcb to sw mode by default */
1270         ret = i40e_dcb_init_configure(dev, TRUE);
1271         if (ret != I40E_SUCCESS) {
1272                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1273                 pf->flags &= ~I40E_FLAG_DCB;
1274         }
1275         /* Update HW struct after DCB configuration */
1276         i40e_get_cap(hw);
1277
1278         /* initialize pf host driver to setup SRIOV resource if applicable */
1279         i40e_pf_host_init(dev);
1280
1281         /* register callback func to eal lib */
1282         rte_intr_callback_register(intr_handle,
1283                                    i40e_dev_interrupt_handler, dev);
1284
1285         /* configure and enable device interrupt */
1286         i40e_pf_config_irq0(hw, TRUE);
1287         i40e_pf_enable_irq0(hw);
1288
1289         /* enable uio intr after callback register */
1290         rte_intr_enable(intr_handle);
1291         /*
1292          * Add an ethertype filter to drop all flow control frames transmitted
1293          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1294          * frames to wire.
1295          */
1296         i40e_add_tx_flow_control_drop_filter(pf);
1297
1298         /* Set the max frame size to 0x2600 by default,
1299          * in case other drivers changed the default value.
1300          */
1301         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1302
1303         /* initialize mirror rule list */
1304         TAILQ_INIT(&pf->mirror_list);
1305
1306         ret = i40e_init_ethtype_filter_list(dev);
1307         if (ret < 0)
1308                 goto err_init_ethtype_filter_list;
1309         ret = i40e_init_tunnel_filter_list(dev);
1310         if (ret < 0)
1311                 goto err_init_tunnel_filter_list;
1312         ret = i40e_init_fdir_filter_list(dev);
1313         if (ret < 0)
1314                 goto err_init_fdir_filter_list;
1315
1316         return 0;
1317
1318 err_init_fdir_filter_list:
1319         rte_free(pf->tunnel.hash_table);
1320         rte_free(pf->tunnel.hash_map);
1321 err_init_tunnel_filter_list:
1322         rte_free(pf->ethertype.hash_table);
1323         rte_free(pf->ethertype.hash_map);
1324 err_init_ethtype_filter_list:
1325         rte_free(dev->data->mac_addrs);
1326 err_mac_alloc:
1327         i40e_vsi_release(pf->main_vsi);
1328 err_setup_pf_switch:
1329 err_get_mac_addr:
1330 err_configure_lan_hmc:
1331         (void)i40e_shutdown_lan_hmc(hw);
1332 err_init_lan_hmc:
1333         i40e_res_pool_destroy(&pf->msix_pool);
1334 err_msix_pool_init:
1335         i40e_res_pool_destroy(&pf->qp_pool);
1336 err_qp_pool_init:
1337 err_parameter_init:
1338 err_get_capabilities:
1339 err_sync_phy_type:
1340         (void)i40e_shutdown_adminq(hw);
1341
1342         return ret;
1343 }
1344
1345 static void
1346 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1347 {
1348         struct i40e_ethertype_filter *p_ethertype;
1349         struct i40e_ethertype_rule *ethertype_rule;
1350
1351         ethertype_rule = &pf->ethertype;
1352         /* Remove all ethertype filter rules and hash */
1353         if (ethertype_rule->hash_map)
1354                 rte_free(ethertype_rule->hash_map);
1355         if (ethertype_rule->hash_table)
1356                 rte_hash_free(ethertype_rule->hash_table);
1357
1358         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1359                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1360                              p_ethertype, rules);
1361                 rte_free(p_ethertype);
1362         }
1363 }
1364
1365 static void
1366 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1367 {
1368         struct i40e_tunnel_filter *p_tunnel;
1369         struct i40e_tunnel_rule *tunnel_rule;
1370
1371         tunnel_rule = &pf->tunnel;
1372         /* Remove all tunnel director rules and hash */
1373         if (tunnel_rule->hash_map)
1374                 rte_free(tunnel_rule->hash_map);
1375         if (tunnel_rule->hash_table)
1376                 rte_hash_free(tunnel_rule->hash_table);
1377
1378         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1379                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1380                 rte_free(p_tunnel);
1381         }
1382 }
1383
1384 static void
1385 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1386 {
1387         struct i40e_fdir_filter *p_fdir;
1388         struct i40e_fdir_info *fdir_info;
1389
1390         fdir_info = &pf->fdir;
1391         /* Remove all flow director rules and hash */
1392         if (fdir_info->hash_map)
1393                 rte_free(fdir_info->hash_map);
1394         if (fdir_info->hash_table)
1395                 rte_hash_free(fdir_info->hash_table);
1396
1397         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1398                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1399                 rte_free(p_fdir);
1400         }
1401 }
1402
1403 static int
1404 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1405 {
1406         struct i40e_pf *pf;
1407         struct rte_pci_device *pci_dev;
1408         struct rte_intr_handle *intr_handle;
1409         struct i40e_hw *hw;
1410         struct i40e_filter_control_settings settings;
1411         struct rte_flow *p_flow;
1412         int ret;
1413         uint8_t aq_fail = 0;
1414
1415         PMD_INIT_FUNC_TRACE();
1416
1417         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1418                 return 0;
1419
1420         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1421         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1422         pci_dev = I40E_DEV_TO_PCI(dev);
1423         intr_handle = &pci_dev->intr_handle;
1424
1425         if (hw->adapter_stopped == 0)
1426                 i40e_dev_close(dev);
1427
1428         dev->dev_ops = NULL;
1429         dev->rx_pkt_burst = NULL;
1430         dev->tx_pkt_burst = NULL;
1431
1432         /* Clear PXE mode */
1433         i40e_clear_pxe_mode(hw);
1434
1435         /* Unconfigure filter control */
1436         memset(&settings, 0, sizeof(settings));
1437         ret = i40e_set_filter_control(hw, &settings);
1438         if (ret)
1439                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1440                                         ret);
1441
1442         /* Disable flow control */
1443         hw->fc.requested_mode = I40E_FC_NONE;
1444         i40e_set_fc(hw, &aq_fail, TRUE);
1445
1446         /* uninitialize pf host driver */
1447         i40e_pf_host_uninit(dev);
1448
1449         rte_free(dev->data->mac_addrs);
1450         dev->data->mac_addrs = NULL;
1451
1452         /* disable uio intr before callback unregister */
1453         rte_intr_disable(intr_handle);
1454
1455         /* register callback func to eal lib */
1456         rte_intr_callback_unregister(intr_handle,
1457                                      i40e_dev_interrupt_handler, dev);
1458
1459         i40e_rm_ethtype_filter_list(pf);
1460         i40e_rm_tunnel_filter_list(pf);
1461         i40e_rm_fdir_filter_list(pf);
1462
1463         /* Remove all flows */
1464         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1465                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1466                 rte_free(p_flow);
1467         }
1468
1469         return 0;
1470 }
1471
1472 static int
1473 i40e_dev_configure(struct rte_eth_dev *dev)
1474 {
1475         struct i40e_adapter *ad =
1476                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1477         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1478         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1479         int i, ret;
1480
1481         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1482          * bulk allocation or vector Rx preconditions we will reset it.
1483          */
1484         ad->rx_bulk_alloc_allowed = true;
1485         ad->rx_vec_allowed = true;
1486         ad->tx_simple_allowed = true;
1487         ad->tx_vec_allowed = true;
1488
1489         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1490                 ret = i40e_fdir_setup(pf);
1491                 if (ret != I40E_SUCCESS) {
1492                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1493                         return -ENOTSUP;
1494                 }
1495                 ret = i40e_fdir_configure(dev);
1496                 if (ret < 0) {
1497                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1498                         goto err;
1499                 }
1500         } else
1501                 i40e_fdir_teardown(pf);
1502
1503         ret = i40e_dev_init_vlan(dev);
1504         if (ret < 0)
1505                 goto err;
1506
1507         /* VMDQ setup.
1508          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1509          *  RSS setting have different requirements.
1510          *  General PMD driver call sequence are NIC init, configure,
1511          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1512          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1513          *  applicable. So, VMDQ setting has to be done before
1514          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1515          *  For RSS setting, it will try to calculate actual configured RX queue
1516          *  number, which will be available after rx_queue_setup(). dev_start()
1517          *  function is good to place RSS setup.
1518          */
1519         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1520                 ret = i40e_vmdq_setup(dev);
1521                 if (ret)
1522                         goto err;
1523         }
1524
1525         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1526                 ret = i40e_dcb_setup(dev);
1527                 if (ret) {
1528                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1529                         goto err_dcb;
1530                 }
1531         }
1532
1533         TAILQ_INIT(&pf->flow_list);
1534
1535         return 0;
1536
1537 err_dcb:
1538         /* need to release vmdq resource if exists */
1539         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1540                 i40e_vsi_release(pf->vmdq[i].vsi);
1541                 pf->vmdq[i].vsi = NULL;
1542         }
1543         rte_free(pf->vmdq);
1544         pf->vmdq = NULL;
1545 err:
1546         /* need to release fdir resource if exists */
1547         i40e_fdir_teardown(pf);
1548         return ret;
1549 }
1550
1551 void
1552 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1553 {
1554         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1555         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1556         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1557         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1558         uint16_t msix_vect = vsi->msix_intr;
1559         uint16_t i;
1560
1561         for (i = 0; i < vsi->nb_qps; i++) {
1562                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1563                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1564                 rte_wmb();
1565         }
1566
1567         if (vsi->type != I40E_VSI_SRIOV) {
1568                 if (!rte_intr_allow_others(intr_handle)) {
1569                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1570                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1571                         I40E_WRITE_REG(hw,
1572                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1573                                        0);
1574                 } else {
1575                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1576                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1577                         I40E_WRITE_REG(hw,
1578                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1579                                                        msix_vect - 1), 0);
1580                 }
1581         } else {
1582                 uint32_t reg;
1583                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1584                         vsi->user_param + (msix_vect - 1);
1585
1586                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1587                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1588         }
1589         I40E_WRITE_FLUSH(hw);
1590 }
1591
1592 static void
1593 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1594                        int base_queue, int nb_queue)
1595 {
1596         int i;
1597         uint32_t val;
1598         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1599
1600         /* Bind all RX queues to allocated MSIX interrupt */
1601         for (i = 0; i < nb_queue; i++) {
1602                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1603                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1604                         ((base_queue + i + 1) <<
1605                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1606                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1607                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1608
1609                 if (i == nb_queue - 1)
1610                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1611                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1612         }
1613
1614         /* Write first RX queue to Link list register as the head element */
1615         if (vsi->type != I40E_VSI_SRIOV) {
1616                 uint16_t interval =
1617                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1618
1619                 if (msix_vect == I40E_MISC_VEC_ID) {
1620                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1621                                        (base_queue <<
1622                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1623                                        (0x0 <<
1624                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1625                         I40E_WRITE_REG(hw,
1626                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1627                                        interval);
1628                 } else {
1629                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1630                                        (base_queue <<
1631                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1632                                        (0x0 <<
1633                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1634                         I40E_WRITE_REG(hw,
1635                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1636                                                        msix_vect - 1),
1637                                        interval);
1638                 }
1639         } else {
1640                 uint32_t reg;
1641
1642                 if (msix_vect == I40E_MISC_VEC_ID) {
1643                         I40E_WRITE_REG(hw,
1644                                        I40E_VPINT_LNKLST0(vsi->user_param),
1645                                        (base_queue <<
1646                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1647                                        (0x0 <<
1648                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1649                 } else {
1650                         /* num_msix_vectors_vf needs to minus irq0 */
1651                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1652                                 vsi->user_param + (msix_vect - 1);
1653
1654                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1655                                        (base_queue <<
1656                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1657                                        (0x0 <<
1658                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1659                 }
1660         }
1661
1662         I40E_WRITE_FLUSH(hw);
1663 }
1664
1665 void
1666 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1667 {
1668         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1669         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1670         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1671         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1672         uint16_t msix_vect = vsi->msix_intr;
1673         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1674         uint16_t queue_idx = 0;
1675         int record = 0;
1676         uint32_t val;
1677         int i;
1678
1679         for (i = 0; i < vsi->nb_qps; i++) {
1680                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1681                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1682         }
1683
1684         /* INTENA flag is not auto-cleared for interrupt */
1685         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1686         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1687                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1688                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1689         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1690
1691         /* VF bind interrupt */
1692         if (vsi->type == I40E_VSI_SRIOV) {
1693                 __vsi_queues_bind_intr(vsi, msix_vect,
1694                                        vsi->base_queue, vsi->nb_qps);
1695                 return;
1696         }
1697
1698         /* PF & VMDq bind interrupt */
1699         if (rte_intr_dp_is_en(intr_handle)) {
1700                 if (vsi->type == I40E_VSI_MAIN) {
1701                         queue_idx = 0;
1702                         record = 1;
1703                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1704                         struct i40e_vsi *main_vsi =
1705                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1706                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1707                         record = 1;
1708                 }
1709         }
1710
1711         for (i = 0; i < vsi->nb_used_qps; i++) {
1712                 if (nb_msix <= 1) {
1713                         if (!rte_intr_allow_others(intr_handle))
1714                                 /* allow to share MISC_VEC_ID */
1715                                 msix_vect = I40E_MISC_VEC_ID;
1716
1717                         /* no enough msix_vect, map all to one */
1718                         __vsi_queues_bind_intr(vsi, msix_vect,
1719                                                vsi->base_queue + i,
1720                                                vsi->nb_used_qps - i);
1721                         for (; !!record && i < vsi->nb_used_qps; i++)
1722                                 intr_handle->intr_vec[queue_idx + i] =
1723                                         msix_vect;
1724                         break;
1725                 }
1726                 /* 1:1 queue/msix_vect mapping */
1727                 __vsi_queues_bind_intr(vsi, msix_vect,
1728                                        vsi->base_queue + i, 1);
1729                 if (!!record)
1730                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1731
1732                 msix_vect++;
1733                 nb_msix--;
1734         }
1735 }
1736
1737 static void
1738 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1739 {
1740         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1741         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1742         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1743         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1744         uint16_t interval = i40e_calc_itr_interval(\
1745                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1746         uint16_t msix_intr, i;
1747
1748         if (rte_intr_allow_others(intr_handle))
1749                 for (i = 0; i < vsi->nb_msix; i++) {
1750                         msix_intr = vsi->msix_intr + i;
1751                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1752                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1753                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1754                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1755                                 (interval <<
1756                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1757                 }
1758         else
1759                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1760                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1761                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1762                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1763                                (interval <<
1764                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1765
1766         I40E_WRITE_FLUSH(hw);
1767 }
1768
1769 static void
1770 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1771 {
1772         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1773         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1774         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1775         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1776         uint16_t msix_intr, i;
1777
1778         if (rte_intr_allow_others(intr_handle))
1779                 for (i = 0; i < vsi->nb_msix; i++) {
1780                         msix_intr = vsi->msix_intr + i;
1781                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1782                                        0);
1783                 }
1784         else
1785                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1786
1787         I40E_WRITE_FLUSH(hw);
1788 }
1789
1790 static inline uint8_t
1791 i40e_parse_link_speeds(uint16_t link_speeds)
1792 {
1793         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1794
1795         if (link_speeds & ETH_LINK_SPEED_40G)
1796                 link_speed |= I40E_LINK_SPEED_40GB;
1797         if (link_speeds & ETH_LINK_SPEED_25G)
1798                 link_speed |= I40E_LINK_SPEED_25GB;
1799         if (link_speeds & ETH_LINK_SPEED_20G)
1800                 link_speed |= I40E_LINK_SPEED_20GB;
1801         if (link_speeds & ETH_LINK_SPEED_10G)
1802                 link_speed |= I40E_LINK_SPEED_10GB;
1803         if (link_speeds & ETH_LINK_SPEED_1G)
1804                 link_speed |= I40E_LINK_SPEED_1GB;
1805         if (link_speeds & ETH_LINK_SPEED_100M)
1806                 link_speed |= I40E_LINK_SPEED_100MB;
1807
1808         return link_speed;
1809 }
1810
1811 static int
1812 i40e_phy_conf_link(struct i40e_hw *hw,
1813                    uint8_t abilities,
1814                    uint8_t force_speed)
1815 {
1816         enum i40e_status_code status;
1817         struct i40e_aq_get_phy_abilities_resp phy_ab;
1818         struct i40e_aq_set_phy_config phy_conf;
1819         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1820                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1821                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1822                         I40E_AQ_PHY_FLAG_LOW_POWER;
1823         const uint8_t advt = I40E_LINK_SPEED_40GB |
1824                         I40E_LINK_SPEED_25GB |
1825                         I40E_LINK_SPEED_10GB |
1826                         I40E_LINK_SPEED_1GB |
1827                         I40E_LINK_SPEED_100MB;
1828         int ret = -ENOTSUP;
1829
1830
1831         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1832                                               NULL);
1833         if (status)
1834                 return ret;
1835
1836         memset(&phy_conf, 0, sizeof(phy_conf));
1837
1838         /* bits 0-2 use the values from get_phy_abilities_resp */
1839         abilities &= ~mask;
1840         abilities |= phy_ab.abilities & mask;
1841
1842         /* update ablities and speed */
1843         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1844                 phy_conf.link_speed = advt;
1845         else
1846                 phy_conf.link_speed = force_speed;
1847
1848         phy_conf.abilities = abilities;
1849
1850         /* use get_phy_abilities_resp value for the rest */
1851         phy_conf.phy_type = phy_ab.phy_type;
1852         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1853         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1854         phy_conf.eee_capability = phy_ab.eee_capability;
1855         phy_conf.eeer = phy_ab.eeer_val;
1856         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1857
1858         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1859                     phy_ab.abilities, phy_ab.link_speed);
1860         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1861                     phy_conf.abilities, phy_conf.link_speed);
1862
1863         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1864         if (status)
1865                 return ret;
1866
1867         return I40E_SUCCESS;
1868 }
1869
1870 static int
1871 i40e_apply_link_speed(struct rte_eth_dev *dev)
1872 {
1873         uint8_t speed;
1874         uint8_t abilities = 0;
1875         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1876         struct rte_eth_conf *conf = &dev->data->dev_conf;
1877
1878         speed = i40e_parse_link_speeds(conf->link_speeds);
1879         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1880         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1881                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1882         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1883
1884         /* Skip changing speed on 40G interfaces, FW does not support */
1885         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1886                 speed =  I40E_LINK_SPEED_UNKNOWN;
1887                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1888         }
1889
1890         return i40e_phy_conf_link(hw, abilities, speed);
1891 }
1892
1893 static int
1894 i40e_dev_start(struct rte_eth_dev *dev)
1895 {
1896         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1897         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1898         struct i40e_vsi *main_vsi = pf->main_vsi;
1899         int ret, i;
1900         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1901         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1902         uint32_t intr_vector = 0;
1903         struct i40e_vsi *vsi;
1904
1905         hw->adapter_stopped = 0;
1906
1907         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1908                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1909                              dev->data->port_id);
1910                 return -EINVAL;
1911         }
1912
1913         rte_intr_disable(intr_handle);
1914
1915         if ((rte_intr_cap_multiple(intr_handle) ||
1916              !RTE_ETH_DEV_SRIOV(dev).active) &&
1917             dev->data->dev_conf.intr_conf.rxq != 0) {
1918                 intr_vector = dev->data->nb_rx_queues;
1919                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1920                 if (ret)
1921                         return ret;
1922         }
1923
1924         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1925                 intr_handle->intr_vec =
1926                         rte_zmalloc("intr_vec",
1927                                     dev->data->nb_rx_queues * sizeof(int),
1928                                     0);
1929                 if (!intr_handle->intr_vec) {
1930                         PMD_INIT_LOG(ERR,
1931                                 "Failed to allocate %d rx_queues intr_vec",
1932                                 dev->data->nb_rx_queues);
1933                         return -ENOMEM;
1934                 }
1935         }
1936
1937         /* Initialize VSI */
1938         ret = i40e_dev_rxtx_init(pf);
1939         if (ret != I40E_SUCCESS) {
1940                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1941                 goto err_up;
1942         }
1943
1944         /* Map queues with MSIX interrupt */
1945         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1946                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1947         i40e_vsi_queues_bind_intr(main_vsi);
1948         i40e_vsi_enable_queues_intr(main_vsi);
1949
1950         /* Map VMDQ VSI queues with MSIX interrupt */
1951         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1952                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1953                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1954                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1955         }
1956
1957         /* enable FDIR MSIX interrupt */
1958         if (pf->fdir.fdir_vsi) {
1959                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1960                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1961         }
1962
1963         /* Enable all queues which have been configured */
1964         ret = i40e_dev_switch_queues(pf, TRUE);
1965         if (ret != I40E_SUCCESS) {
1966                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1967                 goto err_up;
1968         }
1969
1970         /* Enable receiving broadcast packets */
1971         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1972         if (ret != I40E_SUCCESS)
1973                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1974
1975         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1976                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1977                                                 true, NULL);
1978                 if (ret != I40E_SUCCESS)
1979                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1980         }
1981
1982         /* Enable the VLAN promiscuous mode. */
1983         if (pf->vfs) {
1984                 for (i = 0; i < pf->vf_num; i++) {
1985                         vsi = pf->vfs[i].vsi;
1986                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1987                                                      true, NULL);
1988                 }
1989         }
1990
1991         /* Apply link configure */
1992         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1993                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1994                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1995                                 ETH_LINK_SPEED_40G)) {
1996                 PMD_DRV_LOG(ERR, "Invalid link setting");
1997                 goto err_up;
1998         }
1999         ret = i40e_apply_link_speed(dev);
2000         if (I40E_SUCCESS != ret) {
2001                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2002                 goto err_up;
2003         }
2004
2005         if (!rte_intr_allow_others(intr_handle)) {
2006                 rte_intr_callback_unregister(intr_handle,
2007                                              i40e_dev_interrupt_handler,
2008                                              (void *)dev);
2009                 /* configure and enable device interrupt */
2010                 i40e_pf_config_irq0(hw, FALSE);
2011                 i40e_pf_enable_irq0(hw);
2012
2013                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2014                         PMD_INIT_LOG(INFO,
2015                                 "lsc won't enable because of no intr multiplex");
2016         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2017                 ret = i40e_aq_set_phy_int_mask(hw,
2018                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2019                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2020                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2021                 if (ret != I40E_SUCCESS)
2022                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2023
2024                 /* Call get_link_info aq commond to enable LSE */
2025                 i40e_dev_link_update(dev, 0);
2026         }
2027
2028         /* enable uio intr after callback register */
2029         rte_intr_enable(intr_handle);
2030
2031         i40e_filter_restore(pf);
2032
2033         return I40E_SUCCESS;
2034
2035 err_up:
2036         i40e_dev_switch_queues(pf, FALSE);
2037         i40e_dev_clear_queues(dev);
2038
2039         return ret;
2040 }
2041
2042 static void
2043 i40e_dev_stop(struct rte_eth_dev *dev)
2044 {
2045         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2046         struct i40e_vsi *main_vsi = pf->main_vsi;
2047         struct i40e_mirror_rule *p_mirror;
2048         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2049         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2050         int i;
2051
2052         /* Disable all queues */
2053         i40e_dev_switch_queues(pf, FALSE);
2054
2055         /* un-map queues with interrupt registers */
2056         i40e_vsi_disable_queues_intr(main_vsi);
2057         i40e_vsi_queues_unbind_intr(main_vsi);
2058
2059         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2060                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2061                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2062         }
2063
2064         if (pf->fdir.fdir_vsi) {
2065                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2066                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2067         }
2068         /* Clear all queues and release memory */
2069         i40e_dev_clear_queues(dev);
2070
2071         /* Set link down */
2072         i40e_dev_set_link_down(dev);
2073
2074         /* Remove all mirror rules */
2075         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2076                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2077                 rte_free(p_mirror);
2078         }
2079         pf->nb_mirror_rule = 0;
2080
2081         if (!rte_intr_allow_others(intr_handle))
2082                 /* resume to the default handler */
2083                 rte_intr_callback_register(intr_handle,
2084                                            i40e_dev_interrupt_handler,
2085                                            (void *)dev);
2086
2087         /* Clean datapath event and queue/vec mapping */
2088         rte_intr_efd_disable(intr_handle);
2089         if (intr_handle->intr_vec) {
2090                 rte_free(intr_handle->intr_vec);
2091                 intr_handle->intr_vec = NULL;
2092         }
2093 }
2094
2095 static void
2096 i40e_dev_close(struct rte_eth_dev *dev)
2097 {
2098         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2099         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2101         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2102         uint32_t reg;
2103         int i;
2104
2105         PMD_INIT_FUNC_TRACE();
2106
2107         i40e_dev_stop(dev);
2108         hw->adapter_stopped = 1;
2109         i40e_dev_free_queues(dev);
2110
2111         /* Disable interrupt */
2112         i40e_pf_disable_irq0(hw);
2113         rte_intr_disable(intr_handle);
2114
2115         /* shutdown and destroy the HMC */
2116         i40e_shutdown_lan_hmc(hw);
2117
2118         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2119                 i40e_vsi_release(pf->vmdq[i].vsi);
2120                 pf->vmdq[i].vsi = NULL;
2121         }
2122         rte_free(pf->vmdq);
2123         pf->vmdq = NULL;
2124
2125         /* release all the existing VSIs and VEBs */
2126         i40e_fdir_teardown(pf);
2127         i40e_vsi_release(pf->main_vsi);
2128
2129         /* shutdown the adminq */
2130         i40e_aq_queue_shutdown(hw, true);
2131         i40e_shutdown_adminq(hw);
2132
2133         i40e_res_pool_destroy(&pf->qp_pool);
2134         i40e_res_pool_destroy(&pf->msix_pool);
2135
2136         /* force a PF reset to clean anything leftover */
2137         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2138         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2139                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2140         I40E_WRITE_FLUSH(hw);
2141 }
2142
2143 static void
2144 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2145 {
2146         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2147         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148         struct i40e_vsi *vsi = pf->main_vsi;
2149         int status;
2150
2151         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2152                                                      true, NULL, true);
2153         if (status != I40E_SUCCESS)
2154                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2155
2156         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2157                                                         TRUE, NULL);
2158         if (status != I40E_SUCCESS)
2159                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2160
2161 }
2162
2163 static void
2164 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2165 {
2166         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2167         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2168         struct i40e_vsi *vsi = pf->main_vsi;
2169         int status;
2170
2171         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2172                                                      false, NULL, true);
2173         if (status != I40E_SUCCESS)
2174                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2175
2176         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2177                                                         false, NULL);
2178         if (status != I40E_SUCCESS)
2179                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2180 }
2181
2182 static void
2183 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2184 {
2185         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2186         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2187         struct i40e_vsi *vsi = pf->main_vsi;
2188         int ret;
2189
2190         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2191         if (ret != I40E_SUCCESS)
2192                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2193 }
2194
2195 static void
2196 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2197 {
2198         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2199         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200         struct i40e_vsi *vsi = pf->main_vsi;
2201         int ret;
2202
2203         if (dev->data->promiscuous == 1)
2204                 return; /* must remain in all_multicast mode */
2205
2206         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2207                                 vsi->seid, FALSE, NULL);
2208         if (ret != I40E_SUCCESS)
2209                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2210 }
2211
2212 /*
2213  * Set device link up.
2214  */
2215 static int
2216 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2217 {
2218         /* re-apply link speed setting */
2219         return i40e_apply_link_speed(dev);
2220 }
2221
2222 /*
2223  * Set device link down.
2224  */
2225 static int
2226 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2227 {
2228         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2229         uint8_t abilities = 0;
2230         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2231
2232         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2233         return i40e_phy_conf_link(hw, abilities, speed);
2234 }
2235
2236 int
2237 i40e_dev_link_update(struct rte_eth_dev *dev,
2238                      int wait_to_complete)
2239 {
2240 #define CHECK_INTERVAL 100  /* 100ms */
2241 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2242         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2243         struct i40e_link_status link_status;
2244         struct rte_eth_link link, old;
2245         int status;
2246         unsigned rep_cnt = MAX_REPEAT_TIME;
2247         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2248
2249         memset(&link, 0, sizeof(link));
2250         memset(&old, 0, sizeof(old));
2251         memset(&link_status, 0, sizeof(link_status));
2252         rte_i40e_dev_atomic_read_link_status(dev, &old);
2253
2254         do {
2255                 /* Get link status information from hardware */
2256                 status = i40e_aq_get_link_info(hw, enable_lse,
2257                                                 &link_status, NULL);
2258                 if (status != I40E_SUCCESS) {
2259                         link.link_speed = ETH_SPEED_NUM_100M;
2260                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2261                         PMD_DRV_LOG(ERR, "Failed to get link info");
2262                         goto out;
2263                 }
2264
2265                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2266                 if (!wait_to_complete || link.link_status)
2267                         break;
2268
2269                 rte_delay_ms(CHECK_INTERVAL);
2270         } while (--rep_cnt);
2271
2272         if (!link.link_status)
2273                 goto out;
2274
2275         /* i40e uses full duplex only */
2276         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2277
2278         /* Parse the link status */
2279         switch (link_status.link_speed) {
2280         case I40E_LINK_SPEED_100MB:
2281                 link.link_speed = ETH_SPEED_NUM_100M;
2282                 break;
2283         case I40E_LINK_SPEED_1GB:
2284                 link.link_speed = ETH_SPEED_NUM_1G;
2285                 break;
2286         case I40E_LINK_SPEED_10GB:
2287                 link.link_speed = ETH_SPEED_NUM_10G;
2288                 break;
2289         case I40E_LINK_SPEED_20GB:
2290                 link.link_speed = ETH_SPEED_NUM_20G;
2291                 break;
2292         case I40E_LINK_SPEED_25GB:
2293                 link.link_speed = ETH_SPEED_NUM_25G;
2294                 break;
2295         case I40E_LINK_SPEED_40GB:
2296                 link.link_speed = ETH_SPEED_NUM_40G;
2297                 break;
2298         default:
2299                 link.link_speed = ETH_SPEED_NUM_100M;
2300                 break;
2301         }
2302
2303         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2304                         ETH_LINK_SPEED_FIXED);
2305
2306 out:
2307         rte_i40e_dev_atomic_write_link_status(dev, &link);
2308         if (link.link_status == old.link_status)
2309                 return -1;
2310
2311         return 0;
2312 }
2313
2314 /* Get all the statistics of a VSI */
2315 void
2316 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2317 {
2318         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2319         struct i40e_eth_stats *nes = &vsi->eth_stats;
2320         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2321         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2322
2323         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2324                             vsi->offset_loaded, &oes->rx_bytes,
2325                             &nes->rx_bytes);
2326         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2327                             vsi->offset_loaded, &oes->rx_unicast,
2328                             &nes->rx_unicast);
2329         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2330                             vsi->offset_loaded, &oes->rx_multicast,
2331                             &nes->rx_multicast);
2332         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2333                             vsi->offset_loaded, &oes->rx_broadcast,
2334                             &nes->rx_broadcast);
2335         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2336                             &oes->rx_discards, &nes->rx_discards);
2337         /* GLV_REPC not supported */
2338         /* GLV_RMPC not supported */
2339         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2340                             &oes->rx_unknown_protocol,
2341                             &nes->rx_unknown_protocol);
2342         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2343                             vsi->offset_loaded, &oes->tx_bytes,
2344                             &nes->tx_bytes);
2345         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2346                             vsi->offset_loaded, &oes->tx_unicast,
2347                             &nes->tx_unicast);
2348         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2349                             vsi->offset_loaded, &oes->tx_multicast,
2350                             &nes->tx_multicast);
2351         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2352                             vsi->offset_loaded,  &oes->tx_broadcast,
2353                             &nes->tx_broadcast);
2354         /* GLV_TDPC not supported */
2355         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2356                             &oes->tx_errors, &nes->tx_errors);
2357         vsi->offset_loaded = true;
2358
2359         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2360                     vsi->vsi_id);
2361         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2362         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2363         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2364         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2365         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2366         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2367                     nes->rx_unknown_protocol);
2368         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2369         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2370         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2371         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2372         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2373         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2374         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2375                     vsi->vsi_id);
2376 }
2377
2378 static void
2379 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2380 {
2381         unsigned int i;
2382         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2383         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2384
2385         /* Get statistics of struct i40e_eth_stats */
2386         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2387                             I40E_GLPRT_GORCL(hw->port),
2388                             pf->offset_loaded, &os->eth.rx_bytes,
2389                             &ns->eth.rx_bytes);
2390         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2391                             I40E_GLPRT_UPRCL(hw->port),
2392                             pf->offset_loaded, &os->eth.rx_unicast,
2393                             &ns->eth.rx_unicast);
2394         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2395                             I40E_GLPRT_MPRCL(hw->port),
2396                             pf->offset_loaded, &os->eth.rx_multicast,
2397                             &ns->eth.rx_multicast);
2398         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2399                             I40E_GLPRT_BPRCL(hw->port),
2400                             pf->offset_loaded, &os->eth.rx_broadcast,
2401                             &ns->eth.rx_broadcast);
2402         /* Workaround: CRC size should not be included in byte statistics,
2403          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2404          */
2405         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2406                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2407
2408         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2409                             pf->offset_loaded, &os->eth.rx_discards,
2410                             &ns->eth.rx_discards);
2411         /* GLPRT_REPC not supported */
2412         /* GLPRT_RMPC not supported */
2413         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2414                             pf->offset_loaded,
2415                             &os->eth.rx_unknown_protocol,
2416                             &ns->eth.rx_unknown_protocol);
2417         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2418                             I40E_GLPRT_GOTCL(hw->port),
2419                             pf->offset_loaded, &os->eth.tx_bytes,
2420                             &ns->eth.tx_bytes);
2421         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2422                             I40E_GLPRT_UPTCL(hw->port),
2423                             pf->offset_loaded, &os->eth.tx_unicast,
2424                             &ns->eth.tx_unicast);
2425         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2426                             I40E_GLPRT_MPTCL(hw->port),
2427                             pf->offset_loaded, &os->eth.tx_multicast,
2428                             &ns->eth.tx_multicast);
2429         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2430                             I40E_GLPRT_BPTCL(hw->port),
2431                             pf->offset_loaded, &os->eth.tx_broadcast,
2432                             &ns->eth.tx_broadcast);
2433         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2434                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2435         /* GLPRT_TEPC not supported */
2436
2437         /* additional port specific stats */
2438         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2439                             pf->offset_loaded, &os->tx_dropped_link_down,
2440                             &ns->tx_dropped_link_down);
2441         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2442                             pf->offset_loaded, &os->crc_errors,
2443                             &ns->crc_errors);
2444         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2445                             pf->offset_loaded, &os->illegal_bytes,
2446                             &ns->illegal_bytes);
2447         /* GLPRT_ERRBC not supported */
2448         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2449                             pf->offset_loaded, &os->mac_local_faults,
2450                             &ns->mac_local_faults);
2451         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2452                             pf->offset_loaded, &os->mac_remote_faults,
2453                             &ns->mac_remote_faults);
2454         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2455                             pf->offset_loaded, &os->rx_length_errors,
2456                             &ns->rx_length_errors);
2457         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2458                             pf->offset_loaded, &os->link_xon_rx,
2459                             &ns->link_xon_rx);
2460         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2461                             pf->offset_loaded, &os->link_xoff_rx,
2462                             &ns->link_xoff_rx);
2463         for (i = 0; i < 8; i++) {
2464                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2465                                     pf->offset_loaded,
2466                                     &os->priority_xon_rx[i],
2467                                     &ns->priority_xon_rx[i]);
2468                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2469                                     pf->offset_loaded,
2470                                     &os->priority_xoff_rx[i],
2471                                     &ns->priority_xoff_rx[i]);
2472         }
2473         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2474                             pf->offset_loaded, &os->link_xon_tx,
2475                             &ns->link_xon_tx);
2476         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2477                             pf->offset_loaded, &os->link_xoff_tx,
2478                             &ns->link_xoff_tx);
2479         for (i = 0; i < 8; i++) {
2480                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2481                                     pf->offset_loaded,
2482                                     &os->priority_xon_tx[i],
2483                                     &ns->priority_xon_tx[i]);
2484                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2485                                     pf->offset_loaded,
2486                                     &os->priority_xoff_tx[i],
2487                                     &ns->priority_xoff_tx[i]);
2488                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2489                                     pf->offset_loaded,
2490                                     &os->priority_xon_2_xoff[i],
2491                                     &ns->priority_xon_2_xoff[i]);
2492         }
2493         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2494                             I40E_GLPRT_PRC64L(hw->port),
2495                             pf->offset_loaded, &os->rx_size_64,
2496                             &ns->rx_size_64);
2497         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2498                             I40E_GLPRT_PRC127L(hw->port),
2499                             pf->offset_loaded, &os->rx_size_127,
2500                             &ns->rx_size_127);
2501         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2502                             I40E_GLPRT_PRC255L(hw->port),
2503                             pf->offset_loaded, &os->rx_size_255,
2504                             &ns->rx_size_255);
2505         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2506                             I40E_GLPRT_PRC511L(hw->port),
2507                             pf->offset_loaded, &os->rx_size_511,
2508                             &ns->rx_size_511);
2509         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2510                             I40E_GLPRT_PRC1023L(hw->port),
2511                             pf->offset_loaded, &os->rx_size_1023,
2512                             &ns->rx_size_1023);
2513         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2514                             I40E_GLPRT_PRC1522L(hw->port),
2515                             pf->offset_loaded, &os->rx_size_1522,
2516                             &ns->rx_size_1522);
2517         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2518                             I40E_GLPRT_PRC9522L(hw->port),
2519                             pf->offset_loaded, &os->rx_size_big,
2520                             &ns->rx_size_big);
2521         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2522                             pf->offset_loaded, &os->rx_undersize,
2523                             &ns->rx_undersize);
2524         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2525                             pf->offset_loaded, &os->rx_fragments,
2526                             &ns->rx_fragments);
2527         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2528                             pf->offset_loaded, &os->rx_oversize,
2529                             &ns->rx_oversize);
2530         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2531                             pf->offset_loaded, &os->rx_jabber,
2532                             &ns->rx_jabber);
2533         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2534                             I40E_GLPRT_PTC64L(hw->port),
2535                             pf->offset_loaded, &os->tx_size_64,
2536                             &ns->tx_size_64);
2537         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2538                             I40E_GLPRT_PTC127L(hw->port),
2539                             pf->offset_loaded, &os->tx_size_127,
2540                             &ns->tx_size_127);
2541         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2542                             I40E_GLPRT_PTC255L(hw->port),
2543                             pf->offset_loaded, &os->tx_size_255,
2544                             &ns->tx_size_255);
2545         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2546                             I40E_GLPRT_PTC511L(hw->port),
2547                             pf->offset_loaded, &os->tx_size_511,
2548                             &ns->tx_size_511);
2549         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2550                             I40E_GLPRT_PTC1023L(hw->port),
2551                             pf->offset_loaded, &os->tx_size_1023,
2552                             &ns->tx_size_1023);
2553         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2554                             I40E_GLPRT_PTC1522L(hw->port),
2555                             pf->offset_loaded, &os->tx_size_1522,
2556                             &ns->tx_size_1522);
2557         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2558                             I40E_GLPRT_PTC9522L(hw->port),
2559                             pf->offset_loaded, &os->tx_size_big,
2560                             &ns->tx_size_big);
2561         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2562                            pf->offset_loaded,
2563                            &os->fd_sb_match, &ns->fd_sb_match);
2564         /* GLPRT_MSPDC not supported */
2565         /* GLPRT_XEC not supported */
2566
2567         pf->offset_loaded = true;
2568
2569         if (pf->main_vsi)
2570                 i40e_update_vsi_stats(pf->main_vsi);
2571 }
2572
2573 /* Get all statistics of a port */
2574 static void
2575 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2576 {
2577         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2578         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2579         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2580         unsigned i;
2581
2582         /* call read registers - updates values, now write them to struct */
2583         i40e_read_stats_registers(pf, hw);
2584
2585         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2586                         pf->main_vsi->eth_stats.rx_multicast +
2587                         pf->main_vsi->eth_stats.rx_broadcast -
2588                         pf->main_vsi->eth_stats.rx_discards;
2589         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2590                         pf->main_vsi->eth_stats.tx_multicast +
2591                         pf->main_vsi->eth_stats.tx_broadcast;
2592         stats->ibytes   = ns->eth.rx_bytes;
2593         stats->obytes   = ns->eth.tx_bytes;
2594         stats->oerrors  = ns->eth.tx_errors +
2595                         pf->main_vsi->eth_stats.tx_errors;
2596
2597         /* Rx Errors */
2598         stats->imissed  = ns->eth.rx_discards +
2599                         pf->main_vsi->eth_stats.rx_discards;
2600         stats->ierrors  = ns->crc_errors +
2601                         ns->rx_length_errors + ns->rx_undersize +
2602                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2603
2604         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2605         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2606         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2607         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2608         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2609         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2610         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2611                     ns->eth.rx_unknown_protocol);
2612         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2613         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2614         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2615         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2616         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2617         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2618
2619         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2620                     ns->tx_dropped_link_down);
2621         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2622         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2623                     ns->illegal_bytes);
2624         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2625         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2626                     ns->mac_local_faults);
2627         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2628                     ns->mac_remote_faults);
2629         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2630                     ns->rx_length_errors);
2631         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2632         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2633         for (i = 0; i < 8; i++) {
2634                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2635                                 i, ns->priority_xon_rx[i]);
2636                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2637                                 i, ns->priority_xoff_rx[i]);
2638         }
2639         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2640         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2641         for (i = 0; i < 8; i++) {
2642                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2643                                 i, ns->priority_xon_tx[i]);
2644                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2645                                 i, ns->priority_xoff_tx[i]);
2646                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2647                                 i, ns->priority_xon_2_xoff[i]);
2648         }
2649         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2650         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2651         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2652         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2653         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2654         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2655         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2656         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2657         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2658         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2659         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2660         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2661         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2662         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2663         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2664         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2665         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2666         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2667         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2668                         ns->mac_short_packet_dropped);
2669         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2670                     ns->checksum_error);
2671         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2672         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2673 }
2674
2675 /* Reset the statistics */
2676 static void
2677 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2678 {
2679         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2680         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681
2682         /* Mark PF and VSI stats to update the offset, aka "reset" */
2683         pf->offset_loaded = false;
2684         if (pf->main_vsi)
2685                 pf->main_vsi->offset_loaded = false;
2686
2687         /* read the stats, reading current register values into offset */
2688         i40e_read_stats_registers(pf, hw);
2689 }
2690
2691 static uint32_t
2692 i40e_xstats_calc_num(void)
2693 {
2694         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2695                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2696                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2697 }
2698
2699 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2700                                      struct rte_eth_xstat_name *xstats_names,
2701                                      __rte_unused unsigned limit)
2702 {
2703         unsigned count = 0;
2704         unsigned i, prio;
2705
2706         if (xstats_names == NULL)
2707                 return i40e_xstats_calc_num();
2708
2709         /* Note: limit checked in rte_eth_xstats_names() */
2710
2711         /* Get stats from i40e_eth_stats struct */
2712         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2713                 snprintf(xstats_names[count].name,
2714                          sizeof(xstats_names[count].name),
2715                          "%s", rte_i40e_stats_strings[i].name);
2716                 count++;
2717         }
2718
2719         /* Get individiual stats from i40e_hw_port struct */
2720         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2721                 snprintf(xstats_names[count].name,
2722                         sizeof(xstats_names[count].name),
2723                          "%s", rte_i40e_hw_port_strings[i].name);
2724                 count++;
2725         }
2726
2727         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2728                 for (prio = 0; prio < 8; prio++) {
2729                         snprintf(xstats_names[count].name,
2730                                  sizeof(xstats_names[count].name),
2731                                  "rx_priority%u_%s", prio,
2732                                  rte_i40e_rxq_prio_strings[i].name);
2733                         count++;
2734                 }
2735         }
2736
2737         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2738                 for (prio = 0; prio < 8; prio++) {
2739                         snprintf(xstats_names[count].name,
2740                                  sizeof(xstats_names[count].name),
2741                                  "tx_priority%u_%s", prio,
2742                                  rte_i40e_txq_prio_strings[i].name);
2743                         count++;
2744                 }
2745         }
2746         return count;
2747 }
2748
2749 static int
2750 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2751                     unsigned n)
2752 {
2753         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2754         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2755         unsigned i, count, prio;
2756         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2757
2758         count = i40e_xstats_calc_num();
2759         if (n < count)
2760                 return count;
2761
2762         i40e_read_stats_registers(pf, hw);
2763
2764         if (xstats == NULL)
2765                 return 0;
2766
2767         count = 0;
2768
2769         /* Get stats from i40e_eth_stats struct */
2770         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2771                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2772                         rte_i40e_stats_strings[i].offset);
2773                 xstats[count].id = count;
2774                 count++;
2775         }
2776
2777         /* Get individiual stats from i40e_hw_port struct */
2778         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2779                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2780                         rte_i40e_hw_port_strings[i].offset);
2781                 xstats[count].id = count;
2782                 count++;
2783         }
2784
2785         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2786                 for (prio = 0; prio < 8; prio++) {
2787                         xstats[count].value =
2788                                 *(uint64_t *)(((char *)hw_stats) +
2789                                 rte_i40e_rxq_prio_strings[i].offset +
2790                                 (sizeof(uint64_t) * prio));
2791                         xstats[count].id = count;
2792                         count++;
2793                 }
2794         }
2795
2796         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2797                 for (prio = 0; prio < 8; prio++) {
2798                         xstats[count].value =
2799                                 *(uint64_t *)(((char *)hw_stats) +
2800                                 rte_i40e_txq_prio_strings[i].offset +
2801                                 (sizeof(uint64_t) * prio));
2802                         xstats[count].id = count;
2803                         count++;
2804                 }
2805         }
2806
2807         return count;
2808 }
2809
2810 static int
2811 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2812                                  __rte_unused uint16_t queue_id,
2813                                  __rte_unused uint8_t stat_idx,
2814                                  __rte_unused uint8_t is_rx)
2815 {
2816         PMD_INIT_FUNC_TRACE();
2817
2818         return -ENOSYS;
2819 }
2820
2821 static int
2822 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2823 {
2824         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2825         u32 full_ver;
2826         u8 ver, patch;
2827         u16 build;
2828         int ret;
2829
2830         full_ver = hw->nvm.oem_ver;
2831         ver = (u8)(full_ver >> 24);
2832         build = (u16)((full_ver >> 8) & 0xffff);
2833         patch = (u8)(full_ver & 0xff);
2834
2835         ret = snprintf(fw_version, fw_size,
2836                  "%d.%d%d 0x%08x %d.%d.%d",
2837                  ((hw->nvm.version >> 12) & 0xf),
2838                  ((hw->nvm.version >> 4) & 0xff),
2839                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2840                  ver, build, patch);
2841
2842         ret += 1; /* add the size of '\0' */
2843         if (fw_size < (u32)ret)
2844                 return ret;
2845         else
2846                 return 0;
2847 }
2848
2849 static void
2850 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2851 {
2852         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2853         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2854         struct i40e_vsi *vsi = pf->main_vsi;
2855         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2856
2857         dev_info->pci_dev = pci_dev;
2858         dev_info->max_rx_queues = vsi->nb_qps;
2859         dev_info->max_tx_queues = vsi->nb_qps;
2860         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2861         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2862         dev_info->max_mac_addrs = vsi->max_macaddrs;
2863         dev_info->max_vfs = pci_dev->max_vfs;
2864         dev_info->rx_offload_capa =
2865                 DEV_RX_OFFLOAD_VLAN_STRIP |
2866                 DEV_RX_OFFLOAD_QINQ_STRIP |
2867                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2868                 DEV_RX_OFFLOAD_UDP_CKSUM |
2869                 DEV_RX_OFFLOAD_TCP_CKSUM;
2870         dev_info->tx_offload_capa =
2871                 DEV_TX_OFFLOAD_VLAN_INSERT |
2872                 DEV_TX_OFFLOAD_QINQ_INSERT |
2873                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2874                 DEV_TX_OFFLOAD_UDP_CKSUM |
2875                 DEV_TX_OFFLOAD_TCP_CKSUM |
2876                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2877                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2878                 DEV_TX_OFFLOAD_TCP_TSO |
2879                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2880                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2881                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2882                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2883         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2884                                                 sizeof(uint32_t);
2885         dev_info->reta_size = pf->hash_lut_size;
2886         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2887
2888         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2889                 .rx_thresh = {
2890                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2891                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2892                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2893                 },
2894                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2895                 .rx_drop_en = 0,
2896         };
2897
2898         dev_info->default_txconf = (struct rte_eth_txconf) {
2899                 .tx_thresh = {
2900                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2901                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2902                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2903                 },
2904                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2905                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2906                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2907                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2908         };
2909
2910         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2911                 .nb_max = I40E_MAX_RING_DESC,
2912                 .nb_min = I40E_MIN_RING_DESC,
2913                 .nb_align = I40E_ALIGN_RING_DESC,
2914         };
2915
2916         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2917                 .nb_max = I40E_MAX_RING_DESC,
2918                 .nb_min = I40E_MIN_RING_DESC,
2919                 .nb_align = I40E_ALIGN_RING_DESC,
2920                 .nb_seg_max = I40E_TX_MAX_SEG,
2921                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2922         };
2923
2924         if (pf->flags & I40E_FLAG_VMDQ) {
2925                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2926                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2927                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2928                                                 pf->max_nb_vmdq_vsi;
2929                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2930                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2931                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2932         }
2933
2934         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2935                 /* For XL710 */
2936                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2937         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2938                 /* For XXV710 */
2939                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2940         else
2941                 /* For X710 */
2942                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2943 }
2944
2945 static int
2946 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2947 {
2948         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2949         struct i40e_vsi *vsi = pf->main_vsi;
2950         PMD_INIT_FUNC_TRACE();
2951
2952         if (on)
2953                 return i40e_vsi_add_vlan(vsi, vlan_id);
2954         else
2955                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2956 }
2957
2958 static int
2959 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2960                    enum rte_vlan_type vlan_type,
2961                    uint16_t tpid)
2962 {
2963         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2964         uint64_t reg_r = 0, reg_w = 0;
2965         uint16_t reg_id = 0;
2966         int ret = 0;
2967         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2968
2969         switch (vlan_type) {
2970         case ETH_VLAN_TYPE_OUTER:
2971                 if (qinq)
2972                         reg_id = 2;
2973                 else
2974                         reg_id = 3;
2975                 break;
2976         case ETH_VLAN_TYPE_INNER:
2977                 if (qinq)
2978                         reg_id = 3;
2979                 else {
2980                         ret = -EINVAL;
2981                         PMD_DRV_LOG(ERR,
2982                                 "Unsupported vlan type in single vlan.");
2983                         return ret;
2984                 }
2985                 break;
2986         default:
2987                 ret = -EINVAL;
2988                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2989                 return ret;
2990         }
2991         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2992                                           &reg_r, NULL);
2993         if (ret != I40E_SUCCESS) {
2994                 PMD_DRV_LOG(ERR,
2995                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2996                            reg_id);
2997                 ret = -EIO;
2998                 return ret;
2999         }
3000         PMD_DRV_LOG(DEBUG,
3001                 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3002                 reg_id, reg_r);
3003
3004         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3005         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3006         if (reg_r == reg_w) {
3007                 ret = 0;
3008                 PMD_DRV_LOG(DEBUG, "No need to write");
3009                 return ret;
3010         }
3011
3012         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3013                                            reg_w, NULL);
3014         if (ret != I40E_SUCCESS) {
3015                 ret = -EIO;
3016                 PMD_DRV_LOG(ERR,
3017                         "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3018                         reg_id);
3019                 return ret;
3020         }
3021         PMD_DRV_LOG(DEBUG,
3022                 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3023                 reg_w, reg_id);
3024
3025         return ret;
3026 }
3027
3028 static void
3029 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3030 {
3031         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3032         struct i40e_vsi *vsi = pf->main_vsi;
3033
3034         if (mask & ETH_VLAN_FILTER_MASK) {
3035                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3036                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3037                 else
3038                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3039         }
3040
3041         if (mask & ETH_VLAN_STRIP_MASK) {
3042                 /* Enable or disable VLAN stripping */
3043                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3044                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3045                 else
3046                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3047         }
3048
3049         if (mask & ETH_VLAN_EXTEND_MASK) {
3050                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3051                         i40e_vsi_config_double_vlan(vsi, TRUE);
3052                         /* Set global registers with default ether type value */
3053                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3054                                            ETHER_TYPE_VLAN);
3055                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3056                                            ETHER_TYPE_VLAN);
3057                 }
3058                 else
3059                         i40e_vsi_config_double_vlan(vsi, FALSE);
3060         }
3061 }
3062
3063 static void
3064 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3065                           __rte_unused uint16_t queue,
3066                           __rte_unused int on)
3067 {
3068         PMD_INIT_FUNC_TRACE();
3069 }
3070
3071 static int
3072 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3073 {
3074         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3075         struct i40e_vsi *vsi = pf->main_vsi;
3076         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3077         struct i40e_vsi_vlan_pvid_info info;
3078
3079         memset(&info, 0, sizeof(info));
3080         info.on = on;
3081         if (info.on)
3082                 info.config.pvid = pvid;
3083         else {
3084                 info.config.reject.tagged =
3085                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3086                 info.config.reject.untagged =
3087                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3088         }
3089
3090         return i40e_vsi_vlan_pvid_set(vsi, &info);
3091 }
3092
3093 static int
3094 i40e_dev_led_on(struct rte_eth_dev *dev)
3095 {
3096         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3097         uint32_t mode = i40e_led_get(hw);
3098
3099         if (mode == 0)
3100                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3101
3102         return 0;
3103 }
3104
3105 static int
3106 i40e_dev_led_off(struct rte_eth_dev *dev)
3107 {
3108         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3109         uint32_t mode = i40e_led_get(hw);
3110
3111         if (mode != 0)
3112                 i40e_led_set(hw, 0, false);
3113
3114         return 0;
3115 }
3116
3117 static int
3118 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3119 {
3120         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3121         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3122
3123         fc_conf->pause_time = pf->fc_conf.pause_time;
3124         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3125         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3126
3127          /* Return current mode according to actual setting*/
3128         switch (hw->fc.current_mode) {
3129         case I40E_FC_FULL:
3130                 fc_conf->mode = RTE_FC_FULL;
3131                 break;
3132         case I40E_FC_TX_PAUSE:
3133                 fc_conf->mode = RTE_FC_TX_PAUSE;
3134                 break;
3135         case I40E_FC_RX_PAUSE:
3136                 fc_conf->mode = RTE_FC_RX_PAUSE;
3137                 break;
3138         case I40E_FC_NONE:
3139         default:
3140                 fc_conf->mode = RTE_FC_NONE;
3141         };
3142
3143         return 0;
3144 }
3145
3146 static int
3147 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3148 {
3149         uint32_t mflcn_reg, fctrl_reg, reg;
3150         uint32_t max_high_water;
3151         uint8_t i, aq_failure;
3152         int err;
3153         struct i40e_hw *hw;
3154         struct i40e_pf *pf;
3155         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3156                 [RTE_FC_NONE] = I40E_FC_NONE,
3157                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3158                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3159                 [RTE_FC_FULL] = I40E_FC_FULL
3160         };
3161
3162         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3163
3164         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3165         if ((fc_conf->high_water > max_high_water) ||
3166                         (fc_conf->high_water < fc_conf->low_water)) {
3167                 PMD_INIT_LOG(ERR,
3168                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3169                         max_high_water);
3170                 return -EINVAL;
3171         }
3172
3173         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3174         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3175         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3176
3177         pf->fc_conf.pause_time = fc_conf->pause_time;
3178         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3179         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3180
3181         PMD_INIT_FUNC_TRACE();
3182
3183         /* All the link flow control related enable/disable register
3184          * configuration is handle by the F/W
3185          */
3186         err = i40e_set_fc(hw, &aq_failure, true);
3187         if (err < 0)
3188                 return -ENOSYS;
3189
3190         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3191                 /* Configure flow control refresh threshold,
3192                  * the value for stat_tx_pause_refresh_timer[8]
3193                  * is used for global pause operation.
3194                  */
3195
3196                 I40E_WRITE_REG(hw,
3197                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3198                                pf->fc_conf.pause_time);
3199
3200                 /* configure the timer value included in transmitted pause
3201                  * frame,
3202                  * the value for stat_tx_pause_quanta[8] is used for global
3203                  * pause operation
3204                  */
3205                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3206                                pf->fc_conf.pause_time);
3207
3208                 fctrl_reg = I40E_READ_REG(hw,
3209                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3210
3211                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3212                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3213                 else
3214                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3215
3216                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3217                                fctrl_reg);
3218         } else {
3219                 /* Configure pause time (2 TCs per register) */
3220                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3221                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3222                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3223
3224                 /* Configure flow control refresh threshold value */
3225                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3226                                pf->fc_conf.pause_time / 2);
3227
3228                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3229
3230                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3231                  *depending on configuration
3232                  */
3233                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3234                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3235                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3236                 } else {
3237                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3238                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3239                 }
3240
3241                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3242         }
3243
3244         /* config the water marker both based on the packets and bytes */
3245         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3246                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3247                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3248         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3249                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3250                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3251         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3252                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3253                        << I40E_KILOSHIFT);
3254         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3255                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3256                        << I40E_KILOSHIFT);
3257
3258         I40E_WRITE_FLUSH(hw);
3259
3260         return 0;
3261 }
3262
3263 static int
3264 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3265                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3266 {
3267         PMD_INIT_FUNC_TRACE();
3268
3269         return -ENOSYS;
3270 }
3271
3272 /* Add a MAC address, and update filters */
3273 static void
3274 i40e_macaddr_add(struct rte_eth_dev *dev,
3275                  struct ether_addr *mac_addr,
3276                  __rte_unused uint32_t index,
3277                  uint32_t pool)
3278 {
3279         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3280         struct i40e_mac_filter_info mac_filter;
3281         struct i40e_vsi *vsi;
3282         int ret;
3283
3284         /* If VMDQ not enabled or configured, return */
3285         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3286                           !pf->nb_cfg_vmdq_vsi)) {
3287                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3288                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3289                         pool);
3290                 return;
3291         }
3292
3293         if (pool > pf->nb_cfg_vmdq_vsi) {
3294                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3295                                 pool, pf->nb_cfg_vmdq_vsi);
3296                 return;
3297         }
3298
3299         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3300         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3301                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3302         else
3303                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3304
3305         if (pool == 0)
3306                 vsi = pf->main_vsi;
3307         else
3308                 vsi = pf->vmdq[pool - 1].vsi;
3309
3310         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3311         if (ret != I40E_SUCCESS) {
3312                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3313                 return;
3314         }
3315 }
3316
3317 /* Remove a MAC address, and update filters */
3318 static void
3319 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3320 {
3321         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3322         struct i40e_vsi *vsi;
3323         struct rte_eth_dev_data *data = dev->data;
3324         struct ether_addr *macaddr;
3325         int ret;
3326         uint32_t i;
3327         uint64_t pool_sel;
3328
3329         macaddr = &(data->mac_addrs[index]);
3330
3331         pool_sel = dev->data->mac_pool_sel[index];
3332
3333         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3334                 if (pool_sel & (1ULL << i)) {
3335                         if (i == 0)
3336                                 vsi = pf->main_vsi;
3337                         else {
3338                                 /* No VMDQ pool enabled or configured */
3339                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3340                                         (i > pf->nb_cfg_vmdq_vsi)) {
3341                                         PMD_DRV_LOG(ERR,
3342                                                 "No VMDQ pool enabled/configured");
3343                                         return;
3344                                 }
3345                                 vsi = pf->vmdq[i - 1].vsi;
3346                         }
3347                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3348
3349                         if (ret) {
3350                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3351                                 return;
3352                         }
3353                 }
3354         }
3355 }
3356
3357 /* Set perfect match or hash match of MAC and VLAN for a VF */
3358 static int
3359 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3360                  struct rte_eth_mac_filter *filter,
3361                  bool add)
3362 {
3363         struct i40e_hw *hw;
3364         struct i40e_mac_filter_info mac_filter;
3365         struct ether_addr old_mac;
3366         struct ether_addr *new_mac;
3367         struct i40e_pf_vf *vf = NULL;
3368         uint16_t vf_id;
3369         int ret;
3370
3371         if (pf == NULL) {
3372                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3373                 return -EINVAL;
3374         }
3375         hw = I40E_PF_TO_HW(pf);
3376
3377         if (filter == NULL) {
3378                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3379                 return -EINVAL;
3380         }
3381
3382         new_mac = &filter->mac_addr;
3383
3384         if (is_zero_ether_addr(new_mac)) {
3385                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3386                 return -EINVAL;
3387         }
3388
3389         vf_id = filter->dst_id;
3390
3391         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3392                 PMD_DRV_LOG(ERR, "Invalid argument.");
3393                 return -EINVAL;
3394         }
3395         vf = &pf->vfs[vf_id];
3396
3397         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3398                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3399                 return -EINVAL;
3400         }
3401
3402         if (add) {
3403                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3404                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3405                                 ETHER_ADDR_LEN);
3406                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3407                                  ETHER_ADDR_LEN);
3408
3409                 mac_filter.filter_type = filter->filter_type;
3410                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3411                 if (ret != I40E_SUCCESS) {
3412                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3413                         return -1;
3414                 }
3415                 ether_addr_copy(new_mac, &pf->dev_addr);
3416         } else {
3417                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3418                                 ETHER_ADDR_LEN);
3419                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3420                 if (ret != I40E_SUCCESS) {
3421                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3422                         return -1;
3423                 }
3424
3425                 /* Clear device address as it has been removed */
3426                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3427                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3428         }
3429
3430         return 0;
3431 }
3432
3433 /* MAC filter handle */
3434 static int
3435 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3436                 void *arg)
3437 {
3438         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3439         struct rte_eth_mac_filter *filter;
3440         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3441         int ret = I40E_NOT_SUPPORTED;
3442
3443         filter = (struct rte_eth_mac_filter *)(arg);
3444
3445         switch (filter_op) {
3446         case RTE_ETH_FILTER_NOP:
3447                 ret = I40E_SUCCESS;
3448                 break;
3449         case RTE_ETH_FILTER_ADD:
3450                 i40e_pf_disable_irq0(hw);
3451                 if (filter->is_vf)
3452                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3453                 i40e_pf_enable_irq0(hw);
3454                 break;
3455         case RTE_ETH_FILTER_DELETE:
3456                 i40e_pf_disable_irq0(hw);
3457                 if (filter->is_vf)
3458                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3459                 i40e_pf_enable_irq0(hw);
3460                 break;
3461         default:
3462                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3463                 ret = I40E_ERR_PARAM;
3464                 break;
3465         }
3466
3467         return ret;
3468 }
3469
3470 static int
3471 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3472 {
3473         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3474         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3475         int ret;
3476
3477         if (!lut)
3478                 return -EINVAL;
3479
3480         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3481                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3482                                           lut, lut_size);
3483                 if (ret) {
3484                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3485                         return ret;
3486                 }
3487         } else {
3488                 uint32_t *lut_dw = (uint32_t *)lut;
3489                 uint16_t i, lut_size_dw = lut_size / 4;
3490
3491                 for (i = 0; i < lut_size_dw; i++)
3492                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3493         }
3494
3495         return 0;
3496 }
3497
3498 static int
3499 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3500 {
3501         struct i40e_pf *pf;
3502         struct i40e_hw *hw;
3503         int ret;
3504
3505         if (!vsi || !lut)
3506                 return -EINVAL;
3507
3508         pf = I40E_VSI_TO_PF(vsi);
3509         hw = I40E_VSI_TO_HW(vsi);
3510
3511         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3512                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3513                                           lut, lut_size);
3514                 if (ret) {
3515                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3516                         return ret;
3517                 }
3518         } else {
3519                 uint32_t *lut_dw = (uint32_t *)lut;
3520                 uint16_t i, lut_size_dw = lut_size / 4;
3521
3522                 for (i = 0; i < lut_size_dw; i++)
3523                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3524                 I40E_WRITE_FLUSH(hw);
3525         }
3526
3527         return 0;
3528 }
3529
3530 static int
3531 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3532                          struct rte_eth_rss_reta_entry64 *reta_conf,
3533                          uint16_t reta_size)
3534 {
3535         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3536         uint16_t i, lut_size = pf->hash_lut_size;
3537         uint16_t idx, shift;
3538         uint8_t *lut;
3539         int ret;
3540
3541         if (reta_size != lut_size ||
3542                 reta_size > ETH_RSS_RETA_SIZE_512) {
3543                 PMD_DRV_LOG(ERR,
3544                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3545                         reta_size, lut_size);
3546                 return -EINVAL;
3547         }
3548
3549         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3550         if (!lut) {
3551                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3552                 return -ENOMEM;
3553         }
3554         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3555         if (ret)
3556                 goto out;
3557         for (i = 0; i < reta_size; i++) {
3558                 idx = i / RTE_RETA_GROUP_SIZE;
3559                 shift = i % RTE_RETA_GROUP_SIZE;
3560                 if (reta_conf[idx].mask & (1ULL << shift))
3561                         lut[i] = reta_conf[idx].reta[shift];
3562         }
3563         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3564
3565 out:
3566         rte_free(lut);
3567
3568         return ret;
3569 }
3570
3571 static int
3572 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3573                         struct rte_eth_rss_reta_entry64 *reta_conf,
3574                         uint16_t reta_size)
3575 {
3576         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3577         uint16_t i, lut_size = pf->hash_lut_size;
3578         uint16_t idx, shift;
3579         uint8_t *lut;
3580         int ret;
3581
3582         if (reta_size != lut_size ||
3583                 reta_size > ETH_RSS_RETA_SIZE_512) {
3584                 PMD_DRV_LOG(ERR,
3585                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3586                         reta_size, lut_size);
3587                 return -EINVAL;
3588         }
3589
3590         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3591         if (!lut) {
3592                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3593                 return -ENOMEM;
3594         }
3595
3596         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3597         if (ret)
3598                 goto out;
3599         for (i = 0; i < reta_size; i++) {
3600                 idx = i / RTE_RETA_GROUP_SIZE;
3601                 shift = i % RTE_RETA_GROUP_SIZE;
3602                 if (reta_conf[idx].mask & (1ULL << shift))
3603                         reta_conf[idx].reta[shift] = lut[i];
3604         }
3605
3606 out:
3607         rte_free(lut);
3608
3609         return ret;
3610 }
3611
3612 /**
3613  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3614  * @hw:   pointer to the HW structure
3615  * @mem:  pointer to mem struct to fill out
3616  * @size: size of memory requested
3617  * @alignment: what to align the allocation to
3618  **/
3619 enum i40e_status_code
3620 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3621                         struct i40e_dma_mem *mem,
3622                         u64 size,
3623                         u32 alignment)
3624 {
3625         const struct rte_memzone *mz = NULL;
3626         char z_name[RTE_MEMZONE_NAMESIZE];
3627
3628         if (!mem)
3629                 return I40E_ERR_PARAM;
3630
3631         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3632         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3633                                          alignment, RTE_PGSIZE_2M);
3634         if (!mz)
3635                 return I40E_ERR_NO_MEMORY;
3636
3637         mem->size = size;
3638         mem->va = mz->addr;
3639         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3640         mem->zone = (const void *)mz;
3641         PMD_DRV_LOG(DEBUG,
3642                 "memzone %s allocated with physical address: %"PRIu64,
3643                 mz->name, mem->pa);
3644
3645         return I40E_SUCCESS;
3646 }
3647
3648 /**
3649  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3650  * @hw:   pointer to the HW structure
3651  * @mem:  ptr to mem struct to free
3652  **/
3653 enum i40e_status_code
3654 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3655                     struct i40e_dma_mem *mem)
3656 {
3657         if (!mem)
3658                 return I40E_ERR_PARAM;
3659
3660         PMD_DRV_LOG(DEBUG,
3661                 "memzone %s to be freed with physical address: %"PRIu64,
3662                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3663         rte_memzone_free((const struct rte_memzone *)mem->zone);
3664         mem->zone = NULL;
3665         mem->va = NULL;
3666         mem->pa = (u64)0;
3667
3668         return I40E_SUCCESS;
3669 }
3670
3671 /**
3672  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3673  * @hw:   pointer to the HW structure
3674  * @mem:  pointer to mem struct to fill out
3675  * @size: size of memory requested
3676  **/
3677 enum i40e_status_code
3678 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3679                          struct i40e_virt_mem *mem,
3680                          u32 size)
3681 {
3682         if (!mem)
3683                 return I40E_ERR_PARAM;
3684
3685         mem->size = size;
3686         mem->va = rte_zmalloc("i40e", size, 0);
3687
3688         if (mem->va)
3689                 return I40E_SUCCESS;
3690         else
3691                 return I40E_ERR_NO_MEMORY;
3692 }
3693
3694 /**
3695  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3696  * @hw:   pointer to the HW structure
3697  * @mem:  pointer to mem struct to free
3698  **/
3699 enum i40e_status_code
3700 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3701                      struct i40e_virt_mem *mem)
3702 {
3703         if (!mem)
3704                 return I40E_ERR_PARAM;
3705
3706         rte_free(mem->va);
3707         mem->va = NULL;
3708
3709         return I40E_SUCCESS;
3710 }
3711
3712 void
3713 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3714 {
3715         rte_spinlock_init(&sp->spinlock);
3716 }
3717
3718 void
3719 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3720 {
3721         rte_spinlock_lock(&sp->spinlock);
3722 }
3723
3724 void
3725 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3726 {
3727         rte_spinlock_unlock(&sp->spinlock);
3728 }
3729
3730 void
3731 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3732 {
3733         return;
3734 }
3735
3736 /**
3737  * Get the hardware capabilities, which will be parsed
3738  * and saved into struct i40e_hw.
3739  */
3740 static int
3741 i40e_get_cap(struct i40e_hw *hw)
3742 {
3743         struct i40e_aqc_list_capabilities_element_resp *buf;
3744         uint16_t len, size = 0;
3745         int ret;
3746
3747         /* Calculate a huge enough buff for saving response data temporarily */
3748         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3749                                                 I40E_MAX_CAP_ELE_NUM;
3750         buf = rte_zmalloc("i40e", len, 0);
3751         if (!buf) {
3752                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3753                 return I40E_ERR_NO_MEMORY;
3754         }
3755
3756         /* Get, parse the capabilities and save it to hw */
3757         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3758                         i40e_aqc_opc_list_func_capabilities, NULL);
3759         if (ret != I40E_SUCCESS)
3760                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3761
3762         /* Free the temporary buffer after being used */
3763         rte_free(buf);
3764
3765         return ret;
3766 }
3767
3768 static int
3769 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3770 {
3771         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3772         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3773         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3774         uint16_t qp_count = 0, vsi_count = 0;
3775
3776         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3777                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3778                 return -EINVAL;
3779         }
3780         /* Add the parameter init for LFC */
3781         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3782         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3783         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3784
3785         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3786         pf->max_num_vsi = hw->func_caps.num_vsis;
3787         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3788         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3789         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3790
3791         /* FDir queue/VSI allocation */
3792         pf->fdir_qp_offset = 0;
3793         if (hw->func_caps.fd) {
3794                 pf->flags |= I40E_FLAG_FDIR;
3795                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3796         } else {
3797                 pf->fdir_nb_qps = 0;
3798         }
3799         qp_count += pf->fdir_nb_qps;
3800         vsi_count += 1;
3801
3802         /* LAN queue/VSI allocation */
3803         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3804         if (!hw->func_caps.rss) {
3805                 pf->lan_nb_qps = 1;
3806         } else {
3807                 pf->flags |= I40E_FLAG_RSS;
3808                 if (hw->mac.type == I40E_MAC_X722)
3809                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3810                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3811         }
3812         qp_count += pf->lan_nb_qps;
3813         vsi_count += 1;
3814
3815         /* VF queue/VSI allocation */
3816         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3817         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3818                 pf->flags |= I40E_FLAG_SRIOV;
3819                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3820                 pf->vf_num = pci_dev->max_vfs;
3821                 PMD_DRV_LOG(DEBUG,
3822                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3823                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3824         } else {
3825                 pf->vf_nb_qps = 0;
3826                 pf->vf_num = 0;
3827         }
3828         qp_count += pf->vf_nb_qps * pf->vf_num;
3829         vsi_count += pf->vf_num;
3830
3831         /* VMDq queue/VSI allocation */
3832         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3833         pf->vmdq_nb_qps = 0;
3834         pf->max_nb_vmdq_vsi = 0;
3835         if (hw->func_caps.vmdq) {
3836                 if (qp_count < hw->func_caps.num_tx_qp &&
3837                         vsi_count < hw->func_caps.num_vsis) {
3838                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3839                                 qp_count) / pf->vmdq_nb_qp_max;
3840
3841                         /* Limit the maximum number of VMDq vsi to the maximum
3842                          * ethdev can support
3843                          */
3844                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3845                                 hw->func_caps.num_vsis - vsi_count);
3846                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3847                                 ETH_64_POOLS);
3848                         if (pf->max_nb_vmdq_vsi) {
3849                                 pf->flags |= I40E_FLAG_VMDQ;
3850                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3851                                 PMD_DRV_LOG(DEBUG,
3852                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3853                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3854                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3855                         } else {
3856                                 PMD_DRV_LOG(INFO,
3857                                         "No enough queues left for VMDq");
3858                         }
3859                 } else {
3860                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3861                 }
3862         }
3863         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3864         vsi_count += pf->max_nb_vmdq_vsi;
3865
3866         if (hw->func_caps.dcb)
3867                 pf->flags |= I40E_FLAG_DCB;
3868
3869         if (qp_count > hw->func_caps.num_tx_qp) {
3870                 PMD_DRV_LOG(ERR,
3871                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3872                         qp_count, hw->func_caps.num_tx_qp);
3873                 return -EINVAL;
3874         }
3875         if (vsi_count > hw->func_caps.num_vsis) {
3876                 PMD_DRV_LOG(ERR,
3877                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3878                         vsi_count, hw->func_caps.num_vsis);
3879                 return -EINVAL;
3880         }
3881
3882         return 0;
3883 }
3884
3885 static int
3886 i40e_pf_get_switch_config(struct i40e_pf *pf)
3887 {
3888         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3889         struct i40e_aqc_get_switch_config_resp *switch_config;
3890         struct i40e_aqc_switch_config_element_resp *element;
3891         uint16_t start_seid = 0, num_reported;
3892         int ret;
3893
3894         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3895                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3896         if (!switch_config) {
3897                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3898                 return -ENOMEM;
3899         }
3900
3901         /* Get the switch configurations */
3902         ret = i40e_aq_get_switch_config(hw, switch_config,
3903                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3904         if (ret != I40E_SUCCESS) {
3905                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3906                 goto fail;
3907         }
3908         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3909         if (num_reported != 1) { /* The number should be 1 */
3910                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3911                 goto fail;
3912         }
3913
3914         /* Parse the switch configuration elements */
3915         element = &(switch_config->element[0]);
3916         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3917                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3918                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3919         } else
3920                 PMD_DRV_LOG(INFO, "Unknown element type");
3921
3922 fail:
3923         rte_free(switch_config);
3924
3925         return ret;
3926 }
3927
3928 static int
3929 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3930                         uint32_t num)
3931 {
3932         struct pool_entry *entry;
3933
3934         if (pool == NULL || num == 0)
3935                 return -EINVAL;
3936
3937         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3938         if (entry == NULL) {
3939                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3940                 return -ENOMEM;
3941         }
3942
3943         /* queue heap initialize */
3944         pool->num_free = num;
3945         pool->num_alloc = 0;
3946         pool->base = base;
3947         LIST_INIT(&pool->alloc_list);
3948         LIST_INIT(&pool->free_list);
3949
3950         /* Initialize element  */
3951         entry->base = 0;
3952         entry->len = num;
3953
3954         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3955         return 0;
3956 }
3957
3958 static void
3959 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3960 {
3961         struct pool_entry *entry, *next_entry;
3962
3963         if (pool == NULL)
3964                 return;
3965
3966         for (entry = LIST_FIRST(&pool->alloc_list);
3967                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3968                         entry = next_entry) {
3969                 LIST_REMOVE(entry, next);
3970                 rte_free(entry);
3971         }
3972
3973         for (entry = LIST_FIRST(&pool->free_list);
3974                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3975                         entry = next_entry) {
3976                 LIST_REMOVE(entry, next);
3977                 rte_free(entry);
3978         }
3979
3980         pool->num_free = 0;
3981         pool->num_alloc = 0;
3982         pool->base = 0;
3983         LIST_INIT(&pool->alloc_list);
3984         LIST_INIT(&pool->free_list);
3985 }
3986
3987 static int
3988 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3989                        uint32_t base)
3990 {
3991         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3992         uint32_t pool_offset;
3993         int insert;
3994
3995         if (pool == NULL) {
3996                 PMD_DRV_LOG(ERR, "Invalid parameter");
3997                 return -EINVAL;
3998         }
3999
4000         pool_offset = base - pool->base;
4001         /* Lookup in alloc list */
4002         LIST_FOREACH(entry, &pool->alloc_list, next) {
4003                 if (entry->base == pool_offset) {
4004                         valid_entry = entry;
4005                         LIST_REMOVE(entry, next);
4006                         break;
4007                 }
4008         }
4009
4010         /* Not find, return */
4011         if (valid_entry == NULL) {
4012                 PMD_DRV_LOG(ERR, "Failed to find entry");
4013                 return -EINVAL;
4014         }
4015
4016         /**
4017          * Found it, move it to free list  and try to merge.
4018          * In order to make merge easier, always sort it by qbase.
4019          * Find adjacent prev and last entries.
4020          */
4021         prev = next = NULL;
4022         LIST_FOREACH(entry, &pool->free_list, next) {
4023                 if (entry->base > valid_entry->base) {
4024                         next = entry;
4025                         break;
4026                 }
4027                 prev = entry;
4028         }
4029
4030         insert = 0;
4031         /* Try to merge with next one*/
4032         if (next != NULL) {
4033                 /* Merge with next one */
4034                 if (valid_entry->base + valid_entry->len == next->base) {
4035                         next->base = valid_entry->base;
4036                         next->len += valid_entry->len;
4037                         rte_free(valid_entry);
4038                         valid_entry = next;
4039                         insert = 1;
4040                 }
4041         }
4042
4043         if (prev != NULL) {
4044                 /* Merge with previous one */
4045                 if (prev->base + prev->len == valid_entry->base) {
4046                         prev->len += valid_entry->len;
4047                         /* If it merge with next one, remove next node */
4048                         if (insert == 1) {
4049                                 LIST_REMOVE(valid_entry, next);
4050                                 rte_free(valid_entry);
4051                         } else {
4052                                 rte_free(valid_entry);
4053                                 insert = 1;
4054                         }
4055                 }
4056         }
4057
4058         /* Not find any entry to merge, insert */
4059         if (insert == 0) {
4060                 if (prev != NULL)
4061                         LIST_INSERT_AFTER(prev, valid_entry, next);
4062                 else if (next != NULL)
4063                         LIST_INSERT_BEFORE(next, valid_entry, next);
4064                 else /* It's empty list, insert to head */
4065                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4066         }
4067
4068         pool->num_free += valid_entry->len;
4069         pool->num_alloc -= valid_entry->len;
4070
4071         return 0;
4072 }
4073
4074 static int
4075 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4076                        uint16_t num)
4077 {
4078         struct pool_entry *entry, *valid_entry;
4079
4080         if (pool == NULL || num == 0) {
4081                 PMD_DRV_LOG(ERR, "Invalid parameter");
4082                 return -EINVAL;
4083         }
4084
4085         if (pool->num_free < num) {
4086                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4087                             num, pool->num_free);
4088                 return -ENOMEM;
4089         }
4090
4091         valid_entry = NULL;
4092         /* Lookup  in free list and find most fit one */
4093         LIST_FOREACH(entry, &pool->free_list, next) {
4094                 if (entry->len >= num) {
4095                         /* Find best one */
4096                         if (entry->len == num) {
4097                                 valid_entry = entry;
4098                                 break;
4099                         }
4100                         if (valid_entry == NULL || valid_entry->len > entry->len)
4101                                 valid_entry = entry;
4102                 }
4103         }
4104
4105         /* Not find one to satisfy the request, return */
4106         if (valid_entry == NULL) {
4107                 PMD_DRV_LOG(ERR, "No valid entry found");
4108                 return -ENOMEM;
4109         }
4110         /**
4111          * The entry have equal queue number as requested,
4112          * remove it from alloc_list.
4113          */
4114         if (valid_entry->len == num) {
4115                 LIST_REMOVE(valid_entry, next);
4116         } else {
4117                 /**
4118                  * The entry have more numbers than requested,
4119                  * create a new entry for alloc_list and minus its
4120                  * queue base and number in free_list.
4121                  */
4122                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4123                 if (entry == NULL) {
4124                         PMD_DRV_LOG(ERR,
4125                                 "Failed to allocate memory for resource pool");
4126                         return -ENOMEM;
4127                 }
4128                 entry->base = valid_entry->base;
4129                 entry->len = num;
4130                 valid_entry->base += num;
4131                 valid_entry->len -= num;
4132                 valid_entry = entry;
4133         }
4134
4135         /* Insert it into alloc list, not sorted */
4136         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4137
4138         pool->num_free -= valid_entry->len;
4139         pool->num_alloc += valid_entry->len;
4140
4141         return valid_entry->base + pool->base;
4142 }
4143
4144 /**
4145  * bitmap_is_subset - Check whether src2 is subset of src1
4146  **/
4147 static inline int
4148 bitmap_is_subset(uint8_t src1, uint8_t src2)
4149 {
4150         return !((src1 ^ src2) & src2);
4151 }
4152
4153 static enum i40e_status_code
4154 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4155 {
4156         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4157
4158         /* If DCB is not supported, only default TC is supported */
4159         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4160                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4161                 return I40E_NOT_SUPPORTED;
4162         }
4163
4164         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4165                 PMD_DRV_LOG(ERR,
4166                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4167                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4168                 return I40E_NOT_SUPPORTED;
4169         }
4170         return I40E_SUCCESS;
4171 }
4172
4173 int
4174 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4175                                 struct i40e_vsi_vlan_pvid_info *info)
4176 {
4177         struct i40e_hw *hw;
4178         struct i40e_vsi_context ctxt;
4179         uint8_t vlan_flags = 0;
4180         int ret;
4181
4182         if (vsi == NULL || info == NULL) {
4183                 PMD_DRV_LOG(ERR, "invalid parameters");
4184                 return I40E_ERR_PARAM;
4185         }
4186
4187         if (info->on) {
4188                 vsi->info.pvid = info->config.pvid;
4189                 /**
4190                  * If insert pvid is enabled, only tagged pkts are
4191                  * allowed to be sent out.
4192                  */
4193                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4194                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4195         } else {
4196                 vsi->info.pvid = 0;
4197                 if (info->config.reject.tagged == 0)
4198                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4199
4200                 if (info->config.reject.untagged == 0)
4201                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4202         }
4203         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4204                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4205         vsi->info.port_vlan_flags |= vlan_flags;
4206         vsi->info.valid_sections =
4207                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4208         memset(&ctxt, 0, sizeof(ctxt));
4209         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4210         ctxt.seid = vsi->seid;
4211
4212         hw = I40E_VSI_TO_HW(vsi);
4213         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4214         if (ret != I40E_SUCCESS)
4215                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4216
4217         return ret;
4218 }
4219
4220 static int
4221 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4222 {
4223         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4224         int i, ret;
4225         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4226
4227         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4228         if (ret != I40E_SUCCESS)
4229                 return ret;
4230
4231         if (!vsi->seid) {
4232                 PMD_DRV_LOG(ERR, "seid not valid");
4233                 return -EINVAL;
4234         }
4235
4236         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4237         tc_bw_data.tc_valid_bits = enabled_tcmap;
4238         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4239                 tc_bw_data.tc_bw_credits[i] =
4240                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4241
4242         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4243         if (ret != I40E_SUCCESS) {
4244                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4245                 return ret;
4246         }
4247
4248         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4249                                         sizeof(vsi->info.qs_handle));
4250         return I40E_SUCCESS;
4251 }
4252
4253 static enum i40e_status_code
4254 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4255                                  struct i40e_aqc_vsi_properties_data *info,
4256                                  uint8_t enabled_tcmap)
4257 {
4258         enum i40e_status_code ret;
4259         int i, total_tc = 0;
4260         uint16_t qpnum_per_tc, bsf, qp_idx;
4261
4262         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4263         if (ret != I40E_SUCCESS)
4264                 return ret;
4265
4266         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4267                 if (enabled_tcmap & (1 << i))
4268                         total_tc++;
4269         vsi->enabled_tc = enabled_tcmap;
4270
4271         /* Number of queues per enabled TC */
4272         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4273         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4274         bsf = rte_bsf32(qpnum_per_tc);
4275
4276         /* Adjust the queue number to actual queues that can be applied */
4277         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4278                 vsi->nb_qps = qpnum_per_tc * total_tc;
4279
4280         /**
4281          * Configure TC and queue mapping parameters, for enabled TC,
4282          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4283          * default queue will serve it.
4284          */
4285         qp_idx = 0;
4286         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4287                 if (vsi->enabled_tc & (1 << i)) {
4288                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4289                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4290                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4291                         qp_idx += qpnum_per_tc;
4292                 } else
4293                         info->tc_mapping[i] = 0;
4294         }
4295
4296         /* Associate queue number with VSI */
4297         if (vsi->type == I40E_VSI_SRIOV) {
4298                 info->mapping_flags |=
4299                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4300                 for (i = 0; i < vsi->nb_qps; i++)
4301                         info->queue_mapping[i] =
4302                                 rte_cpu_to_le_16(vsi->base_queue + i);
4303         } else {
4304                 info->mapping_flags |=
4305                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4306                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4307         }
4308         info->valid_sections |=
4309                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4310
4311         return I40E_SUCCESS;
4312 }
4313
4314 static int
4315 i40e_veb_release(struct i40e_veb *veb)
4316 {
4317         struct i40e_vsi *vsi;
4318         struct i40e_hw *hw;
4319
4320         if (veb == NULL)
4321                 return -EINVAL;
4322
4323         if (!TAILQ_EMPTY(&veb->head)) {
4324                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4325                 return -EACCES;
4326         }
4327         /* associate_vsi field is NULL for floating VEB */
4328         if (veb->associate_vsi != NULL) {
4329                 vsi = veb->associate_vsi;
4330                 hw = I40E_VSI_TO_HW(vsi);
4331
4332                 vsi->uplink_seid = veb->uplink_seid;
4333                 vsi->veb = NULL;
4334         } else {
4335                 veb->associate_pf->main_vsi->floating_veb = NULL;
4336                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4337         }
4338
4339         i40e_aq_delete_element(hw, veb->seid, NULL);
4340         rte_free(veb);
4341         return I40E_SUCCESS;
4342 }
4343
4344 /* Setup a veb */
4345 static struct i40e_veb *
4346 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4347 {
4348         struct i40e_veb *veb;
4349         int ret;
4350         struct i40e_hw *hw;
4351
4352         if (pf == NULL) {
4353                 PMD_DRV_LOG(ERR,
4354                             "veb setup failed, associated PF shouldn't null");
4355                 return NULL;
4356         }
4357         hw = I40E_PF_TO_HW(pf);
4358
4359         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4360         if (!veb) {
4361                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4362                 goto fail;
4363         }
4364
4365         veb->associate_vsi = vsi;
4366         veb->associate_pf = pf;
4367         TAILQ_INIT(&veb->head);
4368         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4369
4370         /* create floating veb if vsi is NULL */
4371         if (vsi != NULL) {
4372                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4373                                       I40E_DEFAULT_TCMAP, false,
4374                                       &veb->seid, false, NULL);
4375         } else {
4376                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4377                                       true, &veb->seid, false, NULL);
4378         }
4379
4380         if (ret != I40E_SUCCESS) {
4381                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4382                             hw->aq.asq_last_status);
4383                 goto fail;
4384         }
4385         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4386
4387         /* get statistics index */
4388         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4389                                 &veb->stats_idx, NULL, NULL, NULL);
4390         if (ret != I40E_SUCCESS) {
4391                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4392                             hw->aq.asq_last_status);
4393                 goto fail;
4394         }
4395         /* Get VEB bandwidth, to be implemented */
4396         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4397         if (vsi)
4398                 vsi->uplink_seid = veb->seid;
4399
4400         return veb;
4401 fail:
4402         rte_free(veb);
4403         return NULL;
4404 }
4405
4406 int
4407 i40e_vsi_release(struct i40e_vsi *vsi)
4408 {
4409         struct i40e_pf *pf;
4410         struct i40e_hw *hw;
4411         struct i40e_vsi_list *vsi_list;
4412         void *temp;
4413         int ret;
4414         struct i40e_mac_filter *f;
4415         uint16_t user_param;
4416
4417         if (!vsi)
4418                 return I40E_SUCCESS;
4419
4420         if (!vsi->adapter)
4421                 return -EFAULT;
4422
4423         user_param = vsi->user_param;
4424
4425         pf = I40E_VSI_TO_PF(vsi);
4426         hw = I40E_VSI_TO_HW(vsi);
4427
4428         /* VSI has child to attach, release child first */
4429         if (vsi->veb) {
4430                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4431                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4432                                 return -1;
4433                 }
4434                 i40e_veb_release(vsi->veb);
4435         }
4436
4437         if (vsi->floating_veb) {
4438                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4439                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4440                                 return -1;
4441                 }
4442         }
4443
4444         /* Remove all macvlan filters of the VSI */
4445         i40e_vsi_remove_all_macvlan_filter(vsi);
4446         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4447                 rte_free(f);
4448
4449         if (vsi->type != I40E_VSI_MAIN &&
4450             ((vsi->type != I40E_VSI_SRIOV) ||
4451             !pf->floating_veb_list[user_param])) {
4452                 /* Remove vsi from parent's sibling list */
4453                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4454                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4455                         return I40E_ERR_PARAM;
4456                 }
4457                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4458                                 &vsi->sib_vsi_list, list);
4459
4460                 /* Remove all switch element of the VSI */
4461                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4462                 if (ret != I40E_SUCCESS)
4463                         PMD_DRV_LOG(ERR, "Failed to delete element");
4464         }
4465
4466         if ((vsi->type == I40E_VSI_SRIOV) &&
4467             pf->floating_veb_list[user_param]) {
4468                 /* Remove vsi from parent's sibling list */
4469                 if (vsi->parent_vsi == NULL ||
4470                     vsi->parent_vsi->floating_veb == NULL) {
4471                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4472                         return I40E_ERR_PARAM;
4473                 }
4474                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4475                              &vsi->sib_vsi_list, list);
4476
4477                 /* Remove all switch element of the VSI */
4478                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4479                 if (ret != I40E_SUCCESS)
4480                         PMD_DRV_LOG(ERR, "Failed to delete element");
4481         }
4482
4483         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4484
4485         if (vsi->type != I40E_VSI_SRIOV)
4486                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4487         rte_free(vsi);
4488
4489         return I40E_SUCCESS;
4490 }
4491
4492 static int
4493 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4494 {
4495         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4496         struct i40e_aqc_remove_macvlan_element_data def_filter;
4497         struct i40e_mac_filter_info filter;
4498         int ret;
4499
4500         if (vsi->type != I40E_VSI_MAIN)
4501                 return I40E_ERR_CONFIG;
4502         memset(&def_filter, 0, sizeof(def_filter));
4503         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4504                                         ETH_ADDR_LEN);
4505         def_filter.vlan_tag = 0;
4506         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4507                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4508         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4509         if (ret != I40E_SUCCESS) {
4510                 struct i40e_mac_filter *f;
4511                 struct ether_addr *mac;
4512
4513                 PMD_DRV_LOG(WARNING,
4514                         "Cannot remove the default macvlan filter");
4515                 /* It needs to add the permanent mac into mac list */
4516                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4517                 if (f == NULL) {
4518                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4519                         return I40E_ERR_NO_MEMORY;
4520                 }
4521                 mac = &f->mac_info.mac_addr;
4522                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4523                                 ETH_ADDR_LEN);
4524                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4525                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4526                 vsi->mac_num++;
4527
4528                 return ret;
4529         }
4530         (void)rte_memcpy(&filter.mac_addr,
4531                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4532         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4533         return i40e_vsi_add_mac(vsi, &filter);
4534 }
4535
4536 /*
4537  * i40e_vsi_get_bw_config - Query VSI BW Information
4538  * @vsi: the VSI to be queried
4539  *
4540  * Returns 0 on success, negative value on failure
4541  */
4542 static enum i40e_status_code
4543 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4544 {
4545         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4546         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4547         struct i40e_hw *hw = &vsi->adapter->hw;
4548         i40e_status ret;
4549         int i;
4550         uint32_t bw_max;
4551
4552         memset(&bw_config, 0, sizeof(bw_config));
4553         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4554         if (ret != I40E_SUCCESS) {
4555                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4556                             hw->aq.asq_last_status);
4557                 return ret;
4558         }
4559
4560         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4561         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4562                                         &ets_sla_config, NULL);
4563         if (ret != I40E_SUCCESS) {
4564                 PMD_DRV_LOG(ERR,
4565                         "VSI failed to get TC bandwdith configuration %u",
4566                         hw->aq.asq_last_status);
4567                 return ret;
4568         }
4569
4570         /* store and print out BW info */
4571         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4572         vsi->bw_info.bw_max = bw_config.max_bw;
4573         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4574         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4575         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4576                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4577                      I40E_16_BIT_WIDTH);
4578         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4579                 vsi->bw_info.bw_ets_share_credits[i] =
4580                                 ets_sla_config.share_credits[i];
4581                 vsi->bw_info.bw_ets_credits[i] =
4582                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4583                 /* 4 bits per TC, 4th bit is reserved */
4584                 vsi->bw_info.bw_ets_max[i] =
4585                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4586                                   RTE_LEN2MASK(3, uint8_t));
4587                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4588                             vsi->bw_info.bw_ets_share_credits[i]);
4589                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4590                             vsi->bw_info.bw_ets_credits[i]);
4591                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4592                             vsi->bw_info.bw_ets_max[i]);
4593         }
4594
4595         return I40E_SUCCESS;
4596 }
4597
4598 /* i40e_enable_pf_lb
4599  * @pf: pointer to the pf structure
4600  *
4601  * allow loopback on pf
4602  */
4603 static inline void
4604 i40e_enable_pf_lb(struct i40e_pf *pf)
4605 {
4606         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4607         struct i40e_vsi_context ctxt;
4608         int ret;
4609
4610         /* Use the FW API if FW >= v5.0 */
4611         if (hw->aq.fw_maj_ver < 5) {
4612                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4613                 return;
4614         }
4615
4616         memset(&ctxt, 0, sizeof(ctxt));
4617         ctxt.seid = pf->main_vsi_seid;
4618         ctxt.pf_num = hw->pf_id;
4619         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4620         if (ret) {
4621                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4622                             ret, hw->aq.asq_last_status);
4623                 return;
4624         }
4625         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4626         ctxt.info.valid_sections =
4627                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4628         ctxt.info.switch_id |=
4629                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4630
4631         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4632         if (ret)
4633                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4634                             hw->aq.asq_last_status);
4635 }
4636
4637 /* Setup a VSI */
4638 struct i40e_vsi *
4639 i40e_vsi_setup(struct i40e_pf *pf,
4640                enum i40e_vsi_type type,
4641                struct i40e_vsi *uplink_vsi,
4642                uint16_t user_param)
4643 {
4644         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4645         struct i40e_vsi *vsi;
4646         struct i40e_mac_filter_info filter;
4647         int ret;
4648         struct i40e_vsi_context ctxt;
4649         struct ether_addr broadcast =
4650                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4651
4652         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4653             uplink_vsi == NULL) {
4654                 PMD_DRV_LOG(ERR,
4655                         "VSI setup failed, VSI link shouldn't be NULL");
4656                 return NULL;
4657         }
4658
4659         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4660                 PMD_DRV_LOG(ERR,
4661                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4662                 return NULL;
4663         }
4664
4665         /* two situations
4666          * 1.type is not MAIN and uplink vsi is not NULL
4667          * If uplink vsi didn't setup VEB, create one first under veb field
4668          * 2.type is SRIOV and the uplink is NULL
4669          * If floating VEB is NULL, create one veb under floating veb field
4670          */
4671
4672         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4673             uplink_vsi->veb == NULL) {
4674                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4675
4676                 if (uplink_vsi->veb == NULL) {
4677                         PMD_DRV_LOG(ERR, "VEB setup failed");
4678                         return NULL;
4679                 }
4680                 /* set ALLOWLOOPBACk on pf, when veb is created */
4681                 i40e_enable_pf_lb(pf);
4682         }
4683
4684         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4685             pf->main_vsi->floating_veb == NULL) {
4686                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4687
4688                 if (pf->main_vsi->floating_veb == NULL) {
4689                         PMD_DRV_LOG(ERR, "VEB setup failed");
4690                         return NULL;
4691                 }
4692         }
4693
4694         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4695         if (!vsi) {
4696                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4697                 return NULL;
4698         }
4699         TAILQ_INIT(&vsi->mac_list);
4700         vsi->type = type;
4701         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4702         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4703         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4704         vsi->user_param = user_param;
4705         vsi->vlan_anti_spoof_on = 0;
4706         vsi->vlan_filter_on = 0;
4707         /* Allocate queues */
4708         switch (vsi->type) {
4709         case I40E_VSI_MAIN  :
4710                 vsi->nb_qps = pf->lan_nb_qps;
4711                 break;
4712         case I40E_VSI_SRIOV :
4713                 vsi->nb_qps = pf->vf_nb_qps;
4714                 break;
4715         case I40E_VSI_VMDQ2:
4716                 vsi->nb_qps = pf->vmdq_nb_qps;
4717                 break;
4718         case I40E_VSI_FDIR:
4719                 vsi->nb_qps = pf->fdir_nb_qps;
4720                 break;
4721         default:
4722                 goto fail_mem;
4723         }
4724         /*
4725          * The filter status descriptor is reported in rx queue 0,
4726          * while the tx queue for fdir filter programming has no
4727          * such constraints, can be non-zero queues.
4728          * To simplify it, choose FDIR vsi use queue 0 pair.
4729          * To make sure it will use queue 0 pair, queue allocation
4730          * need be done before this function is called
4731          */
4732         if (type != I40E_VSI_FDIR) {
4733                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4734                         if (ret < 0) {
4735                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4736                                                 vsi->seid, ret);
4737                                 goto fail_mem;
4738                         }
4739                         vsi->base_queue = ret;
4740         } else
4741                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4742
4743         /* VF has MSIX interrupt in VF range, don't allocate here */
4744         if (type == I40E_VSI_MAIN) {
4745                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4746                                           RTE_MIN(vsi->nb_qps,
4747                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4748                 if (ret < 0) {
4749                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4750                                     vsi->seid, ret);
4751                         goto fail_queue_alloc;
4752                 }
4753                 vsi->msix_intr = ret;
4754                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4755         } else if (type != I40E_VSI_SRIOV) {
4756                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4757                 if (ret < 0) {
4758                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4759                         goto fail_queue_alloc;
4760                 }
4761                 vsi->msix_intr = ret;
4762                 vsi->nb_msix = 1;
4763         } else {
4764                 vsi->msix_intr = 0;
4765                 vsi->nb_msix = 0;
4766         }
4767
4768         /* Add VSI */
4769         if (type == I40E_VSI_MAIN) {
4770                 /* For main VSI, no need to add since it's default one */
4771                 vsi->uplink_seid = pf->mac_seid;
4772                 vsi->seid = pf->main_vsi_seid;
4773                 /* Bind queues with specific MSIX interrupt */
4774                 /**
4775                  * Needs 2 interrupt at least, one for misc cause which will
4776                  * enabled from OS side, Another for queues binding the
4777                  * interrupt from device side only.
4778                  */
4779
4780                 /* Get default VSI parameters from hardware */
4781                 memset(&ctxt, 0, sizeof(ctxt));
4782                 ctxt.seid = vsi->seid;
4783                 ctxt.pf_num = hw->pf_id;
4784                 ctxt.uplink_seid = vsi->uplink_seid;
4785                 ctxt.vf_num = 0;
4786                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4787                 if (ret != I40E_SUCCESS) {
4788                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4789                         goto fail_msix_alloc;
4790                 }
4791                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4792                         sizeof(struct i40e_aqc_vsi_properties_data));
4793                 vsi->vsi_id = ctxt.vsi_number;
4794                 vsi->info.valid_sections = 0;
4795
4796                 /* Configure tc, enabled TC0 only */
4797                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4798                         I40E_SUCCESS) {
4799                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4800                         goto fail_msix_alloc;
4801                 }
4802
4803                 /* TC, queue mapping */
4804                 memset(&ctxt, 0, sizeof(ctxt));
4805                 vsi->info.valid_sections |=
4806                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4807                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4808                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4809                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4810                         sizeof(struct i40e_aqc_vsi_properties_data));
4811                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4812                                                 I40E_DEFAULT_TCMAP);
4813                 if (ret != I40E_SUCCESS) {
4814                         PMD_DRV_LOG(ERR,
4815                                 "Failed to configure TC queue mapping");
4816                         goto fail_msix_alloc;
4817                 }
4818                 ctxt.seid = vsi->seid;
4819                 ctxt.pf_num = hw->pf_id;
4820                 ctxt.uplink_seid = vsi->uplink_seid;
4821                 ctxt.vf_num = 0;
4822
4823                 /* Update VSI parameters */
4824                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4825                 if (ret != I40E_SUCCESS) {
4826                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4827                         goto fail_msix_alloc;
4828                 }
4829
4830                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4831                                                 sizeof(vsi->info.tc_mapping));
4832                 (void)rte_memcpy(&vsi->info.queue_mapping,
4833                                 &ctxt.info.queue_mapping,
4834                         sizeof(vsi->info.queue_mapping));
4835                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4836                 vsi->info.valid_sections = 0;
4837
4838                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4839                                 ETH_ADDR_LEN);
4840
4841                 /**
4842                  * Updating default filter settings are necessary to prevent
4843                  * reception of tagged packets.
4844                  * Some old firmware configurations load a default macvlan
4845                  * filter which accepts both tagged and untagged packets.
4846                  * The updating is to use a normal filter instead if needed.
4847                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4848                  * The firmware with correct configurations load the default
4849                  * macvlan filter which is expected and cannot be removed.
4850                  */
4851                 i40e_update_default_filter_setting(vsi);
4852                 i40e_config_qinq(hw, vsi);
4853         } else if (type == I40E_VSI_SRIOV) {
4854                 memset(&ctxt, 0, sizeof(ctxt));
4855                 /**
4856                  * For other VSI, the uplink_seid equals to uplink VSI's
4857                  * uplink_seid since they share same VEB
4858                  */
4859                 if (uplink_vsi == NULL)
4860                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4861                 else
4862                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4863                 ctxt.pf_num = hw->pf_id;
4864                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4865                 ctxt.uplink_seid = vsi->uplink_seid;
4866                 ctxt.connection_type = 0x1;
4867                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4868
4869                 /* Use the VEB configuration if FW >= v5.0 */
4870                 if (hw->aq.fw_maj_ver >= 5) {
4871                         /* Configure switch ID */
4872                         ctxt.info.valid_sections |=
4873                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4874                         ctxt.info.switch_id =
4875                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4876                 }
4877
4878                 /* Configure port/vlan */
4879                 ctxt.info.valid_sections |=
4880                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4881                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4882                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4883                                                 hw->func_caps.enabled_tcmap);
4884                 if (ret != I40E_SUCCESS) {
4885                         PMD_DRV_LOG(ERR,
4886                                 "Failed to configure TC queue mapping");
4887                         goto fail_msix_alloc;
4888                 }
4889
4890                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4891                 ctxt.info.valid_sections |=
4892                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4893                 /**
4894                  * Since VSI is not created yet, only configure parameter,
4895                  * will add vsi below.
4896                  */
4897
4898                 i40e_config_qinq(hw, vsi);
4899         } else if (type == I40E_VSI_VMDQ2) {
4900                 memset(&ctxt, 0, sizeof(ctxt));
4901                 /*
4902                  * For other VSI, the uplink_seid equals to uplink VSI's
4903                  * uplink_seid since they share same VEB
4904                  */
4905                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4906                 ctxt.pf_num = hw->pf_id;
4907                 ctxt.vf_num = 0;
4908                 ctxt.uplink_seid = vsi->uplink_seid;
4909                 ctxt.connection_type = 0x1;
4910                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4911
4912                 ctxt.info.valid_sections |=
4913                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4914                 /* user_param carries flag to enable loop back */
4915                 if (user_param) {
4916                         ctxt.info.switch_id =
4917                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4918                         ctxt.info.switch_id |=
4919                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4920                 }
4921
4922                 /* Configure port/vlan */
4923                 ctxt.info.valid_sections |=
4924                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4925                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4926                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4927                                                 I40E_DEFAULT_TCMAP);
4928                 if (ret != I40E_SUCCESS) {
4929                         PMD_DRV_LOG(ERR,
4930                                 "Failed to configure TC queue mapping");
4931                         goto fail_msix_alloc;
4932                 }
4933                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4934                 ctxt.info.valid_sections |=
4935                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4936         } else if (type == I40E_VSI_FDIR) {
4937                 memset(&ctxt, 0, sizeof(ctxt));
4938                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4939                 ctxt.pf_num = hw->pf_id;
4940                 ctxt.vf_num = 0;
4941                 ctxt.uplink_seid = vsi->uplink_seid;
4942                 ctxt.connection_type = 0x1;     /* regular data port */
4943                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4944                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4945                                                 I40E_DEFAULT_TCMAP);
4946                 if (ret != I40E_SUCCESS) {
4947                         PMD_DRV_LOG(ERR,
4948                                 "Failed to configure TC queue mapping.");
4949                         goto fail_msix_alloc;
4950                 }
4951                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4952                 ctxt.info.valid_sections |=
4953                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4954         } else {
4955                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4956                 goto fail_msix_alloc;
4957         }
4958
4959         if (vsi->type != I40E_VSI_MAIN) {
4960                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4961                 if (ret != I40E_SUCCESS) {
4962                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4963                                     hw->aq.asq_last_status);
4964                         goto fail_msix_alloc;
4965                 }
4966                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4967                 vsi->info.valid_sections = 0;
4968                 vsi->seid = ctxt.seid;
4969                 vsi->vsi_id = ctxt.vsi_number;
4970                 vsi->sib_vsi_list.vsi = vsi;
4971                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4972                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4973                                           &vsi->sib_vsi_list, list);
4974                 } else {
4975                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4976                                           &vsi->sib_vsi_list, list);
4977                 }
4978         }
4979
4980         /* MAC/VLAN configuration */
4981         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4982         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4983
4984         ret = i40e_vsi_add_mac(vsi, &filter);
4985         if (ret != I40E_SUCCESS) {
4986                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4987                 goto fail_msix_alloc;
4988         }
4989
4990         /* Get VSI BW information */
4991         i40e_vsi_get_bw_config(vsi);
4992         return vsi;
4993 fail_msix_alloc:
4994         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4995 fail_queue_alloc:
4996         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4997 fail_mem:
4998         rte_free(vsi);
4999         return NULL;
5000 }
5001
5002 /* Configure vlan filter on or off */
5003 int
5004 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5005 {
5006         int i, num;
5007         struct i40e_mac_filter *f;
5008         void *temp;
5009         struct i40e_mac_filter_info *mac_filter;
5010         enum rte_mac_filter_type desired_filter;
5011         int ret = I40E_SUCCESS;
5012
5013         if (on) {
5014                 /* Filter to match MAC and VLAN */
5015                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5016         } else {
5017                 /* Filter to match only MAC */
5018                 desired_filter = RTE_MAC_PERFECT_MATCH;
5019         }
5020
5021         num = vsi->mac_num;
5022
5023         mac_filter = rte_zmalloc("mac_filter_info_data",
5024                                  num * sizeof(*mac_filter), 0);
5025         if (mac_filter == NULL) {
5026                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5027                 return I40E_ERR_NO_MEMORY;
5028         }
5029
5030         i = 0;
5031
5032         /* Remove all existing mac */
5033         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5034                 mac_filter[i] = f->mac_info;
5035                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5036                 if (ret) {
5037                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5038                                     on ? "enable" : "disable");
5039                         goto DONE;
5040                 }
5041                 i++;
5042         }
5043
5044         /* Override with new filter */
5045         for (i = 0; i < num; i++) {
5046                 mac_filter[i].filter_type = desired_filter;
5047                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5048                 if (ret) {
5049                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5050                                     on ? "enable" : "disable");
5051                         goto DONE;
5052                 }
5053         }
5054
5055 DONE:
5056         rte_free(mac_filter);
5057         return ret;
5058 }
5059
5060 /* Configure vlan stripping on or off */
5061 int
5062 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5063 {
5064         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5065         struct i40e_vsi_context ctxt;
5066         uint8_t vlan_flags;
5067         int ret = I40E_SUCCESS;
5068
5069         /* Check if it has been already on or off */
5070         if (vsi->info.valid_sections &
5071                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5072                 if (on) {
5073                         if ((vsi->info.port_vlan_flags &
5074                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5075                                 return 0; /* already on */
5076                 } else {
5077                         if ((vsi->info.port_vlan_flags &
5078                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5079                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5080                                 return 0; /* already off */
5081                 }
5082         }
5083
5084         if (on)
5085                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5086         else
5087                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5088         vsi->info.valid_sections =
5089                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5090         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5091         vsi->info.port_vlan_flags |= vlan_flags;
5092         ctxt.seid = vsi->seid;
5093         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5094         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5095         if (ret)
5096                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5097                             on ? "enable" : "disable");
5098
5099         return ret;
5100 }
5101
5102 static int
5103 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5104 {
5105         struct rte_eth_dev_data *data = dev->data;
5106         int ret;
5107         int mask = 0;
5108
5109         /* Apply vlan offload setting */
5110         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5111         i40e_vlan_offload_set(dev, mask);
5112
5113         /* Apply double-vlan setting, not implemented yet */
5114
5115         /* Apply pvid setting */
5116         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5117                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5118         if (ret)
5119                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5120
5121         return ret;
5122 }
5123
5124 static int
5125 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5126 {
5127         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5128
5129         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5130 }
5131
5132 static int
5133 i40e_update_flow_control(struct i40e_hw *hw)
5134 {
5135 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5136         struct i40e_link_status link_status;
5137         uint32_t rxfc = 0, txfc = 0, reg;
5138         uint8_t an_info;
5139         int ret;
5140
5141         memset(&link_status, 0, sizeof(link_status));
5142         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5143         if (ret != I40E_SUCCESS) {
5144                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5145                 goto write_reg; /* Disable flow control */
5146         }
5147
5148         an_info = hw->phy.link_info.an_info;
5149         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5150                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5151                 ret = I40E_ERR_NOT_READY;
5152                 goto write_reg; /* Disable flow control */
5153         }
5154         /**
5155          * If link auto negotiation is enabled, flow control needs to
5156          * be configured according to it
5157          */
5158         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5159         case I40E_LINK_PAUSE_RXTX:
5160                 rxfc = 1;
5161                 txfc = 1;
5162                 hw->fc.current_mode = I40E_FC_FULL;
5163                 break;
5164         case I40E_AQ_LINK_PAUSE_RX:
5165                 rxfc = 1;
5166                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5167                 break;
5168         case I40E_AQ_LINK_PAUSE_TX:
5169                 txfc = 1;
5170                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5171                 break;
5172         default:
5173                 hw->fc.current_mode = I40E_FC_NONE;
5174                 break;
5175         }
5176
5177 write_reg:
5178         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5179                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5180         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5181         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5182         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5183         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5184
5185         return ret;
5186 }
5187
5188 /* PF setup */
5189 static int
5190 i40e_pf_setup(struct i40e_pf *pf)
5191 {
5192         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5193         struct i40e_filter_control_settings settings;
5194         struct i40e_vsi *vsi;
5195         int ret;
5196
5197         /* Clear all stats counters */
5198         pf->offset_loaded = FALSE;
5199         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5200         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5201
5202         ret = i40e_pf_get_switch_config(pf);
5203         if (ret != I40E_SUCCESS) {
5204                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5205                 return ret;
5206         }
5207         if (pf->flags & I40E_FLAG_FDIR) {
5208                 /* make queue allocated first, let FDIR use queue pair 0*/
5209                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5210                 if (ret != I40E_FDIR_QUEUE_ID) {
5211                         PMD_DRV_LOG(ERR,
5212                                 "queue allocation fails for FDIR: ret =%d",
5213                                 ret);
5214                         pf->flags &= ~I40E_FLAG_FDIR;
5215                 }
5216         }
5217         /*  main VSI setup */
5218         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5219         if (!vsi) {
5220                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5221                 return I40E_ERR_NOT_READY;
5222         }
5223         pf->main_vsi = vsi;
5224
5225         /* Configure filter control */
5226         memset(&settings, 0, sizeof(settings));
5227         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5228                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5229         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5230                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5231         else {
5232                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5233                         hw->func_caps.rss_table_size);
5234                 return I40E_ERR_PARAM;
5235         }
5236         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5237                 hw->func_caps.rss_table_size);
5238         pf->hash_lut_size = hw->func_caps.rss_table_size;
5239
5240         /* Enable ethtype and macvlan filters */
5241         settings.enable_ethtype = TRUE;
5242         settings.enable_macvlan = TRUE;
5243         ret = i40e_set_filter_control(hw, &settings);
5244         if (ret)
5245                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5246                                                                 ret);
5247
5248         /* Update flow control according to the auto negotiation */
5249         i40e_update_flow_control(hw);
5250
5251         return I40E_SUCCESS;
5252 }
5253
5254 int
5255 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5256 {
5257         uint32_t reg;
5258         uint16_t j;
5259
5260         /**
5261          * Set or clear TX Queue Disable flags,
5262          * which is required by hardware.
5263          */
5264         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5265         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5266
5267         /* Wait until the request is finished */
5268         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5269                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5270                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5271                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5272                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5273                                                         & 0x1))) {
5274                         break;
5275                 }
5276         }
5277         if (on) {
5278                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5279                         return I40E_SUCCESS; /* already on, skip next steps */
5280
5281                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5282                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5283         } else {
5284                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5285                         return I40E_SUCCESS; /* already off, skip next steps */
5286                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5287         }
5288         /* Write the register */
5289         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5290         /* Check the result */
5291         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5292                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5293                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5294                 if (on) {
5295                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5296                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5297                                 break;
5298                 } else {
5299                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5300                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5301                                 break;
5302                 }
5303         }
5304         /* Check if it is timeout */
5305         if (j >= I40E_CHK_Q_ENA_COUNT) {
5306                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5307                             (on ? "enable" : "disable"), q_idx);
5308                 return I40E_ERR_TIMEOUT;
5309         }
5310
5311         return I40E_SUCCESS;
5312 }
5313
5314 /* Swith on or off the tx queues */
5315 static int
5316 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5317 {
5318         struct rte_eth_dev_data *dev_data = pf->dev_data;
5319         struct i40e_tx_queue *txq;
5320         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5321         uint16_t i;
5322         int ret;
5323
5324         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5325                 txq = dev_data->tx_queues[i];
5326                 /* Don't operate the queue if not configured or
5327                  * if starting only per queue */
5328                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5329                         continue;
5330                 if (on)
5331                         ret = i40e_dev_tx_queue_start(dev, i);
5332                 else
5333                         ret = i40e_dev_tx_queue_stop(dev, i);
5334                 if ( ret != I40E_SUCCESS)
5335                         return ret;
5336         }
5337
5338         return I40E_SUCCESS;
5339 }
5340
5341 int
5342 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5343 {
5344         uint32_t reg;
5345         uint16_t j;
5346
5347         /* Wait until the request is finished */
5348         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5349                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5350                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5351                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5352                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5353                         break;
5354         }
5355
5356         if (on) {
5357                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5358                         return I40E_SUCCESS; /* Already on, skip next steps */
5359                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5360         } else {
5361                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5362                         return I40E_SUCCESS; /* Already off, skip next steps */
5363                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5364         }
5365
5366         /* Write the register */
5367         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5368         /* Check the result */
5369         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5370                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5371                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5372                 if (on) {
5373                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5374                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5375                                 break;
5376                 } else {
5377                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5378                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5379                                 break;
5380                 }
5381         }
5382
5383         /* Check if it is timeout */
5384         if (j >= I40E_CHK_Q_ENA_COUNT) {
5385                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5386                             (on ? "enable" : "disable"), q_idx);
5387                 return I40E_ERR_TIMEOUT;
5388         }
5389
5390         return I40E_SUCCESS;
5391 }
5392 /* Switch on or off the rx queues */
5393 static int
5394 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5395 {
5396         struct rte_eth_dev_data *dev_data = pf->dev_data;
5397         struct i40e_rx_queue *rxq;
5398         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5399         uint16_t i;
5400         int ret;
5401
5402         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5403                 rxq = dev_data->rx_queues[i];
5404                 /* Don't operate the queue if not configured or
5405                  * if starting only per queue */
5406                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5407                         continue;
5408                 if (on)
5409                         ret = i40e_dev_rx_queue_start(dev, i);
5410                 else
5411                         ret = i40e_dev_rx_queue_stop(dev, i);
5412                 if (ret != I40E_SUCCESS)
5413                         return ret;
5414         }
5415
5416         return I40E_SUCCESS;
5417 }
5418
5419 /* Switch on or off all the rx/tx queues */
5420 int
5421 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5422 {
5423         int ret;
5424
5425         if (on) {
5426                 /* enable rx queues before enabling tx queues */
5427                 ret = i40e_dev_switch_rx_queues(pf, on);
5428                 if (ret) {
5429                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5430                         return ret;
5431                 }
5432                 ret = i40e_dev_switch_tx_queues(pf, on);
5433         } else {
5434                 /* Stop tx queues before stopping rx queues */
5435                 ret = i40e_dev_switch_tx_queues(pf, on);
5436                 if (ret) {
5437                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5438                         return ret;
5439                 }
5440                 ret = i40e_dev_switch_rx_queues(pf, on);
5441         }
5442
5443         return ret;
5444 }
5445
5446 /* Initialize VSI for TX */
5447 static int
5448 i40e_dev_tx_init(struct i40e_pf *pf)
5449 {
5450         struct rte_eth_dev_data *data = pf->dev_data;
5451         uint16_t i;
5452         uint32_t ret = I40E_SUCCESS;
5453         struct i40e_tx_queue *txq;
5454
5455         for (i = 0; i < data->nb_tx_queues; i++) {
5456                 txq = data->tx_queues[i];
5457                 if (!txq || !txq->q_set)
5458                         continue;
5459                 ret = i40e_tx_queue_init(txq);
5460                 if (ret != I40E_SUCCESS)
5461                         break;
5462         }
5463         if (ret == I40E_SUCCESS)
5464                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5465                                      ->eth_dev);
5466
5467         return ret;
5468 }
5469
5470 /* Initialize VSI for RX */
5471 static int
5472 i40e_dev_rx_init(struct i40e_pf *pf)
5473 {
5474         struct rte_eth_dev_data *data = pf->dev_data;
5475         int ret = I40E_SUCCESS;
5476         uint16_t i;
5477         struct i40e_rx_queue *rxq;
5478
5479         i40e_pf_config_mq_rx(pf);
5480         for (i = 0; i < data->nb_rx_queues; i++) {
5481                 rxq = data->rx_queues[i];
5482                 if (!rxq || !rxq->q_set)
5483                         continue;
5484
5485                 ret = i40e_rx_queue_init(rxq);
5486                 if (ret != I40E_SUCCESS) {
5487                         PMD_DRV_LOG(ERR,
5488                                 "Failed to do RX queue initialization");
5489                         break;
5490                 }
5491         }
5492         if (ret == I40E_SUCCESS)
5493                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5494                                      ->eth_dev);
5495
5496         return ret;
5497 }
5498
5499 static int
5500 i40e_dev_rxtx_init(struct i40e_pf *pf)
5501 {
5502         int err;
5503
5504         err = i40e_dev_tx_init(pf);
5505         if (err) {
5506                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5507                 return err;
5508         }
5509         err = i40e_dev_rx_init(pf);
5510         if (err) {
5511                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5512                 return err;
5513         }
5514
5515         return err;
5516 }
5517
5518 static int
5519 i40e_vmdq_setup(struct rte_eth_dev *dev)
5520 {
5521         struct rte_eth_conf *conf = &dev->data->dev_conf;
5522         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5523         int i, err, conf_vsis, j, loop;
5524         struct i40e_vsi *vsi;
5525         struct i40e_vmdq_info *vmdq_info;
5526         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5527         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5528
5529         /*
5530          * Disable interrupt to avoid message from VF. Furthermore, it will
5531          * avoid race condition in VSI creation/destroy.
5532          */
5533         i40e_pf_disable_irq0(hw);
5534
5535         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5536                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5537                 return -ENOTSUP;
5538         }
5539
5540         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5541         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5542                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5543                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5544                         pf->max_nb_vmdq_vsi);
5545                 return -ENOTSUP;
5546         }
5547
5548         if (pf->vmdq != NULL) {
5549                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5550                 return 0;
5551         }
5552
5553         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5554                                 sizeof(*vmdq_info) * conf_vsis, 0);
5555
5556         if (pf->vmdq == NULL) {
5557                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5558                 return -ENOMEM;
5559         }
5560
5561         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5562
5563         /* Create VMDQ VSI */
5564         for (i = 0; i < conf_vsis; i++) {
5565                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5566                                 vmdq_conf->enable_loop_back);
5567                 if (vsi == NULL) {
5568                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5569                         err = -1;
5570                         goto err_vsi_setup;
5571                 }
5572                 vmdq_info = &pf->vmdq[i];
5573                 vmdq_info->pf = pf;
5574                 vmdq_info->vsi = vsi;
5575         }
5576         pf->nb_cfg_vmdq_vsi = conf_vsis;
5577
5578         /* Configure Vlan */
5579         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5580         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5581                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5582                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5583                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5584                                         vmdq_conf->pool_map[i].vlan_id, j);
5585
5586                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5587                                                 vmdq_conf->pool_map[i].vlan_id);
5588                                 if (err) {
5589                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5590                                         err = -1;
5591                                         goto err_vsi_setup;
5592                                 }
5593                         }
5594                 }
5595         }
5596
5597         i40e_pf_enable_irq0(hw);
5598
5599         return 0;
5600
5601 err_vsi_setup:
5602         for (i = 0; i < conf_vsis; i++)
5603                 if (pf->vmdq[i].vsi == NULL)
5604                         break;
5605                 else
5606                         i40e_vsi_release(pf->vmdq[i].vsi);
5607
5608         rte_free(pf->vmdq);
5609         pf->vmdq = NULL;
5610         i40e_pf_enable_irq0(hw);
5611         return err;
5612 }
5613
5614 static void
5615 i40e_stat_update_32(struct i40e_hw *hw,
5616                    uint32_t reg,
5617                    bool offset_loaded,
5618                    uint64_t *offset,
5619                    uint64_t *stat)
5620 {
5621         uint64_t new_data;
5622
5623         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5624         if (!offset_loaded)
5625                 *offset = new_data;
5626
5627         if (new_data >= *offset)
5628                 *stat = (uint64_t)(new_data - *offset);
5629         else
5630                 *stat = (uint64_t)((new_data +
5631                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5632 }
5633
5634 static void
5635 i40e_stat_update_48(struct i40e_hw *hw,
5636                    uint32_t hireg,
5637                    uint32_t loreg,
5638                    bool offset_loaded,
5639                    uint64_t *offset,
5640                    uint64_t *stat)
5641 {
5642         uint64_t new_data;
5643
5644         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5645         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5646                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5647
5648         if (!offset_loaded)
5649                 *offset = new_data;
5650
5651         if (new_data >= *offset)
5652                 *stat = new_data - *offset;
5653         else
5654                 *stat = (uint64_t)((new_data +
5655                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5656
5657         *stat &= I40E_48_BIT_MASK;
5658 }
5659
5660 /* Disable IRQ0 */
5661 void
5662 i40e_pf_disable_irq0(struct i40e_hw *hw)
5663 {
5664         /* Disable all interrupt types */
5665         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5666         I40E_WRITE_FLUSH(hw);
5667 }
5668
5669 /* Enable IRQ0 */
5670 void
5671 i40e_pf_enable_irq0(struct i40e_hw *hw)
5672 {
5673         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5674                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5675                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5676                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5677         I40E_WRITE_FLUSH(hw);
5678 }
5679
5680 static void
5681 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5682 {
5683         /* read pending request and disable first */
5684         i40e_pf_disable_irq0(hw);
5685         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5686         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5687                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5688
5689         if (no_queue)
5690                 /* Link no queues with irq0 */
5691                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5692                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5693 }
5694
5695 static void
5696 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5697 {
5698         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5699         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5700         int i;
5701         uint16_t abs_vf_id;
5702         uint32_t index, offset, val;
5703
5704         if (!pf->vfs)
5705                 return;
5706         /**
5707          * Try to find which VF trigger a reset, use absolute VF id to access
5708          * since the reg is global register.
5709          */
5710         for (i = 0; i < pf->vf_num; i++) {
5711                 abs_vf_id = hw->func_caps.vf_base_id + i;
5712                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5713                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5714                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5715                 /* VFR event occured */
5716                 if (val & (0x1 << offset)) {
5717                         int ret;
5718
5719                         /* Clear the event first */
5720                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5721                                                         (0x1 << offset));
5722                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5723                         /**
5724                          * Only notify a VF reset event occured,
5725                          * don't trigger another SW reset
5726                          */
5727                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5728                         if (ret != I40E_SUCCESS)
5729                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5730                 }
5731         }
5732 }
5733
5734 static void
5735 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5736 {
5737         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5738         struct i40e_virtchnl_pf_event event;
5739         int i;
5740
5741         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5742         event.event_data.link_event.link_status =
5743                 dev->data->dev_link.link_status;
5744         event.event_data.link_event.link_speed =
5745                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5746
5747         for (i = 0; i < pf->vf_num; i++)
5748                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5749                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5750 }
5751
5752 static void
5753 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5754 {
5755         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5756         struct i40e_arq_event_info info;
5757         uint16_t pending, opcode;
5758         int ret;
5759
5760         info.buf_len = I40E_AQ_BUF_SZ;
5761         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5762         if (!info.msg_buf) {
5763                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5764                 return;
5765         }
5766
5767         pending = 1;
5768         while (pending) {
5769                 ret = i40e_clean_arq_element(hw, &info, &pending);
5770
5771                 if (ret != I40E_SUCCESS) {
5772                         PMD_DRV_LOG(INFO,
5773                                 "Failed to read msg from AdminQ, aq_err: %u",
5774                                 hw->aq.asq_last_status);
5775                         break;
5776                 }
5777                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5778
5779                 switch (opcode) {
5780                 case i40e_aqc_opc_send_msg_to_pf:
5781                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5782                         i40e_pf_host_handle_vf_msg(dev,
5783                                         rte_le_to_cpu_16(info.desc.retval),
5784                                         rte_le_to_cpu_32(info.desc.cookie_high),
5785                                         rte_le_to_cpu_32(info.desc.cookie_low),
5786                                         info.msg_buf,
5787                                         info.msg_len);
5788                         break;
5789                 case i40e_aqc_opc_get_link_status:
5790                         ret = i40e_dev_link_update(dev, 0);
5791                         if (!ret) {
5792                                 i40e_notify_all_vfs_link_status(dev);
5793                                 _rte_eth_dev_callback_process(dev,
5794                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5795                         }
5796                         break;
5797                 default:
5798                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5799                                     opcode);
5800                         break;
5801                 }
5802         }
5803         rte_free(info.msg_buf);
5804 }
5805
5806 /**
5807  * Interrupt handler triggered by NIC  for handling
5808  * specific interrupt.
5809  *
5810  * @param handle
5811  *  Pointer to interrupt handle.
5812  * @param param
5813  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5814  *
5815  * @return
5816  *  void
5817  */
5818 static void
5819 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5820                            void *param)
5821 {
5822         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5823         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5824         uint32_t icr0;
5825
5826         /* Disable interrupt */
5827         i40e_pf_disable_irq0(hw);
5828
5829         /* read out interrupt causes */
5830         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5831
5832         /* No interrupt event indicated */
5833         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5834                 PMD_DRV_LOG(INFO, "No interrupt event");
5835                 goto done;
5836         }
5837         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5838                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5839         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5840                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5841         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5842                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5843         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5844                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5845         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5846                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5847         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5848                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5849         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5850                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5851
5852         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5853                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5854                 i40e_dev_handle_vfr_event(dev);
5855         }
5856         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5857                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5858                 i40e_dev_handle_aq_msg(dev);
5859         }
5860
5861 done:
5862         /* Enable interrupt */
5863         i40e_pf_enable_irq0(hw);
5864         rte_intr_enable(intr_handle);
5865 }
5866
5867 static int
5868 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5869                          struct i40e_macvlan_filter *filter,
5870                          int total)
5871 {
5872         int ele_num, ele_buff_size;
5873         int num, actual_num, i;
5874         uint16_t flags;
5875         int ret = I40E_SUCCESS;
5876         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5877         struct i40e_aqc_add_macvlan_element_data *req_list;
5878
5879         if (filter == NULL  || total == 0)
5880                 return I40E_ERR_PARAM;
5881         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5882         ele_buff_size = hw->aq.asq_buf_size;
5883
5884         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5885         if (req_list == NULL) {
5886                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5887                 return I40E_ERR_NO_MEMORY;
5888         }
5889
5890         num = 0;
5891         do {
5892                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5893                 memset(req_list, 0, ele_buff_size);
5894
5895                 for (i = 0; i < actual_num; i++) {
5896                         (void)rte_memcpy(req_list[i].mac_addr,
5897                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5898                         req_list[i].vlan_tag =
5899                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5900
5901                         switch (filter[num + i].filter_type) {
5902                         case RTE_MAC_PERFECT_MATCH:
5903                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5904                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5905                                 break;
5906                         case RTE_MACVLAN_PERFECT_MATCH:
5907                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5908                                 break;
5909                         case RTE_MAC_HASH_MATCH:
5910                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5911                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5912                                 break;
5913                         case RTE_MACVLAN_HASH_MATCH:
5914                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5915                                 break;
5916                         default:
5917                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5918                                 ret = I40E_ERR_PARAM;
5919                                 goto DONE;
5920                         }
5921
5922                         req_list[i].queue_number = 0;
5923
5924                         req_list[i].flags = rte_cpu_to_le_16(flags);
5925                 }
5926
5927                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5928                                                 actual_num, NULL);
5929                 if (ret != I40E_SUCCESS) {
5930                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5931                         goto DONE;
5932                 }
5933                 num += actual_num;
5934         } while (num < total);
5935
5936 DONE:
5937         rte_free(req_list);
5938         return ret;
5939 }
5940
5941 static int
5942 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5943                             struct i40e_macvlan_filter *filter,
5944                             int total)
5945 {
5946         int ele_num, ele_buff_size;
5947         int num, actual_num, i;
5948         uint16_t flags;
5949         int ret = I40E_SUCCESS;
5950         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5951         struct i40e_aqc_remove_macvlan_element_data *req_list;
5952
5953         if (filter == NULL  || total == 0)
5954                 return I40E_ERR_PARAM;
5955
5956         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5957         ele_buff_size = hw->aq.asq_buf_size;
5958
5959         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5960         if (req_list == NULL) {
5961                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5962                 return I40E_ERR_NO_MEMORY;
5963         }
5964
5965         num = 0;
5966         do {
5967                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5968                 memset(req_list, 0, ele_buff_size);
5969
5970                 for (i = 0; i < actual_num; i++) {
5971                         (void)rte_memcpy(req_list[i].mac_addr,
5972                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5973                         req_list[i].vlan_tag =
5974                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5975
5976                         switch (filter[num + i].filter_type) {
5977                         case RTE_MAC_PERFECT_MATCH:
5978                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5979                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5980                                 break;
5981                         case RTE_MACVLAN_PERFECT_MATCH:
5982                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5983                                 break;
5984                         case RTE_MAC_HASH_MATCH:
5985                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5986                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5987                                 break;
5988                         case RTE_MACVLAN_HASH_MATCH:
5989                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5990                                 break;
5991                         default:
5992                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5993                                 ret = I40E_ERR_PARAM;
5994                                 goto DONE;
5995                         }
5996                         req_list[i].flags = rte_cpu_to_le_16(flags);
5997                 }
5998
5999                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6000                                                 actual_num, NULL);
6001                 if (ret != I40E_SUCCESS) {
6002                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6003                         goto DONE;
6004                 }
6005                 num += actual_num;
6006         } while (num < total);
6007
6008 DONE:
6009         rte_free(req_list);
6010         return ret;
6011 }
6012
6013 /* Find out specific MAC filter */
6014 static struct i40e_mac_filter *
6015 i40e_find_mac_filter(struct i40e_vsi *vsi,
6016                          struct ether_addr *macaddr)
6017 {
6018         struct i40e_mac_filter *f;
6019
6020         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6021                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6022                         return f;
6023         }
6024
6025         return NULL;
6026 }
6027
6028 static bool
6029 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6030                          uint16_t vlan_id)
6031 {
6032         uint32_t vid_idx, vid_bit;
6033
6034         if (vlan_id > ETH_VLAN_ID_MAX)
6035                 return 0;
6036
6037         vid_idx = I40E_VFTA_IDX(vlan_id);
6038         vid_bit = I40E_VFTA_BIT(vlan_id);
6039
6040         if (vsi->vfta[vid_idx] & vid_bit)
6041                 return 1;
6042         else
6043                 return 0;
6044 }
6045
6046 static void
6047 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6048                        uint16_t vlan_id, bool on)
6049 {
6050         uint32_t vid_idx, vid_bit;
6051
6052         vid_idx = I40E_VFTA_IDX(vlan_id);
6053         vid_bit = I40E_VFTA_BIT(vlan_id);
6054
6055         if (on)
6056                 vsi->vfta[vid_idx] |= vid_bit;
6057         else
6058                 vsi->vfta[vid_idx] &= ~vid_bit;
6059 }
6060
6061 static void
6062 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6063                      uint16_t vlan_id, bool on)
6064 {
6065         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6066         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6067         int ret;
6068
6069         if (vlan_id > ETH_VLAN_ID_MAX)
6070                 return;
6071
6072         i40e_store_vlan_filter(vsi, vlan_id, on);
6073
6074         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6075                 return;
6076
6077         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6078
6079         if (on) {
6080                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6081                                        &vlan_data, 1, NULL);
6082                 if (ret != I40E_SUCCESS)
6083                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6084         } else {
6085                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6086                                           &vlan_data, 1, NULL);
6087                 if (ret != I40E_SUCCESS)
6088                         PMD_DRV_LOG(ERR,
6089                                     "Failed to remove vlan filter");
6090         }
6091 }
6092
6093 /**
6094  * Find all vlan options for specific mac addr,
6095  * return with actual vlan found.
6096  */
6097 static inline int
6098 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6099                            struct i40e_macvlan_filter *mv_f,
6100                            int num, struct ether_addr *addr)
6101 {
6102         int i;
6103         uint32_t j, k;
6104
6105         /**
6106          * Not to use i40e_find_vlan_filter to decrease the loop time,
6107          * although the code looks complex.
6108           */
6109         if (num < vsi->vlan_num)
6110                 return I40E_ERR_PARAM;
6111
6112         i = 0;
6113         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6114                 if (vsi->vfta[j]) {
6115                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6116                                 if (vsi->vfta[j] & (1 << k)) {
6117                                         if (i > num - 1) {
6118                                                 PMD_DRV_LOG(ERR,
6119                                                         "vlan number doesn't match");
6120                                                 return I40E_ERR_PARAM;
6121                                         }
6122                                         (void)rte_memcpy(&mv_f[i].macaddr,
6123                                                         addr, ETH_ADDR_LEN);
6124                                         mv_f[i].vlan_id =
6125                                                 j * I40E_UINT32_BIT_SIZE + k;
6126                                         i++;
6127                                 }
6128                         }
6129                 }
6130         }
6131         return I40E_SUCCESS;
6132 }
6133
6134 static inline int
6135 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6136                            struct i40e_macvlan_filter *mv_f,
6137                            int num,
6138                            uint16_t vlan)
6139 {
6140         int i = 0;
6141         struct i40e_mac_filter *f;
6142
6143         if (num < vsi->mac_num)
6144                 return I40E_ERR_PARAM;
6145
6146         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6147                 if (i > num - 1) {
6148                         PMD_DRV_LOG(ERR, "buffer number not match");
6149                         return I40E_ERR_PARAM;
6150                 }
6151                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6152                                 ETH_ADDR_LEN);
6153                 mv_f[i].vlan_id = vlan;
6154                 mv_f[i].filter_type = f->mac_info.filter_type;
6155                 i++;
6156         }
6157
6158         return I40E_SUCCESS;
6159 }
6160
6161 static int
6162 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6163 {
6164         int i, j, num;
6165         struct i40e_mac_filter *f;
6166         struct i40e_macvlan_filter *mv_f;
6167         int ret = I40E_SUCCESS;
6168
6169         if (vsi == NULL || vsi->mac_num == 0)
6170                 return I40E_ERR_PARAM;
6171
6172         /* Case that no vlan is set */
6173         if (vsi->vlan_num == 0)
6174                 num = vsi->mac_num;
6175         else
6176                 num = vsi->mac_num * vsi->vlan_num;
6177
6178         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6179         if (mv_f == NULL) {
6180                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6181                 return I40E_ERR_NO_MEMORY;
6182         }
6183
6184         i = 0;
6185         if (vsi->vlan_num == 0) {
6186                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6187                         (void)rte_memcpy(&mv_f[i].macaddr,
6188                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6189                         mv_f[i].filter_type = f->mac_info.filter_type;
6190                         mv_f[i].vlan_id = 0;
6191                         i++;
6192                 }
6193         } else {
6194                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6195                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6196                                         vsi->vlan_num, &f->mac_info.mac_addr);
6197                         if (ret != I40E_SUCCESS)
6198                                 goto DONE;
6199                         for (j = i; j < i + vsi->vlan_num; j++)
6200                                 mv_f[j].filter_type = f->mac_info.filter_type;
6201                         i += vsi->vlan_num;
6202                 }
6203         }
6204
6205         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6206 DONE:
6207         rte_free(mv_f);
6208
6209         return ret;
6210 }
6211
6212 int
6213 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6214 {
6215         struct i40e_macvlan_filter *mv_f;
6216         int mac_num;
6217         int ret = I40E_SUCCESS;
6218
6219         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6220                 return I40E_ERR_PARAM;
6221
6222         /* If it's already set, just return */
6223         if (i40e_find_vlan_filter(vsi,vlan))
6224                 return I40E_SUCCESS;
6225
6226         mac_num = vsi->mac_num;
6227
6228         if (mac_num == 0) {
6229                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6230                 return I40E_ERR_PARAM;
6231         }
6232
6233         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6234
6235         if (mv_f == NULL) {
6236                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6237                 return I40E_ERR_NO_MEMORY;
6238         }
6239
6240         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6241
6242         if (ret != I40E_SUCCESS)
6243                 goto DONE;
6244
6245         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6246
6247         if (ret != I40E_SUCCESS)
6248                 goto DONE;
6249
6250         i40e_set_vlan_filter(vsi, vlan, 1);
6251
6252         vsi->vlan_num++;
6253         ret = I40E_SUCCESS;
6254 DONE:
6255         rte_free(mv_f);
6256         return ret;
6257 }
6258
6259 int
6260 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6261 {
6262         struct i40e_macvlan_filter *mv_f;
6263         int mac_num;
6264         int ret = I40E_SUCCESS;
6265
6266         /**
6267          * Vlan 0 is the generic filter for untagged packets
6268          * and can't be removed.
6269          */
6270         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6271                 return I40E_ERR_PARAM;
6272
6273         /* If can't find it, just return */
6274         if (!i40e_find_vlan_filter(vsi, vlan))
6275                 return I40E_ERR_PARAM;
6276
6277         mac_num = vsi->mac_num;
6278
6279         if (mac_num == 0) {
6280                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6281                 return I40E_ERR_PARAM;
6282         }
6283
6284         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6285
6286         if (mv_f == NULL) {
6287                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6288                 return I40E_ERR_NO_MEMORY;
6289         }
6290
6291         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6292
6293         if (ret != I40E_SUCCESS)
6294                 goto DONE;
6295
6296         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6297
6298         if (ret != I40E_SUCCESS)
6299                 goto DONE;
6300
6301         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6302         if (vsi->vlan_num == 1) {
6303                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6304                 if (ret != I40E_SUCCESS)
6305                         goto DONE;
6306
6307                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6308                 if (ret != I40E_SUCCESS)
6309                         goto DONE;
6310         }
6311
6312         i40e_set_vlan_filter(vsi, vlan, 0);
6313
6314         vsi->vlan_num--;
6315         ret = I40E_SUCCESS;
6316 DONE:
6317         rte_free(mv_f);
6318         return ret;
6319 }
6320
6321 int
6322 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6323 {
6324         struct i40e_mac_filter *f;
6325         struct i40e_macvlan_filter *mv_f;
6326         int i, vlan_num = 0;
6327         int ret = I40E_SUCCESS;
6328
6329         /* If it's add and we've config it, return */
6330         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6331         if (f != NULL)
6332                 return I40E_SUCCESS;
6333         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6334                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6335
6336                 /**
6337                  * If vlan_num is 0, that's the first time to add mac,
6338                  * set mask for vlan_id 0.
6339                  */
6340                 if (vsi->vlan_num == 0) {
6341                         i40e_set_vlan_filter(vsi, 0, 1);
6342                         vsi->vlan_num = 1;
6343                 }
6344                 vlan_num = vsi->vlan_num;
6345         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6346                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6347                 vlan_num = 1;
6348
6349         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6350         if (mv_f == NULL) {
6351                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6352                 return I40E_ERR_NO_MEMORY;
6353         }
6354
6355         for (i = 0; i < vlan_num; i++) {
6356                 mv_f[i].filter_type = mac_filter->filter_type;
6357                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6358                                 ETH_ADDR_LEN);
6359         }
6360
6361         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6362                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6363                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6364                                         &mac_filter->mac_addr);
6365                 if (ret != I40E_SUCCESS)
6366                         goto DONE;
6367         }
6368
6369         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6370         if (ret != I40E_SUCCESS)
6371                 goto DONE;
6372
6373         /* Add the mac addr into mac list */
6374         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6375         if (f == NULL) {
6376                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6377                 ret = I40E_ERR_NO_MEMORY;
6378                 goto DONE;
6379         }
6380         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6381                         ETH_ADDR_LEN);
6382         f->mac_info.filter_type = mac_filter->filter_type;
6383         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6384         vsi->mac_num++;
6385
6386         ret = I40E_SUCCESS;
6387 DONE:
6388         rte_free(mv_f);
6389
6390         return ret;
6391 }
6392
6393 int
6394 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6395 {
6396         struct i40e_mac_filter *f;
6397         struct i40e_macvlan_filter *mv_f;
6398         int i, vlan_num;
6399         enum rte_mac_filter_type filter_type;
6400         int ret = I40E_SUCCESS;
6401
6402         /* Can't find it, return an error */
6403         f = i40e_find_mac_filter(vsi, addr);
6404         if (f == NULL)
6405                 return I40E_ERR_PARAM;
6406
6407         vlan_num = vsi->vlan_num;
6408         filter_type = f->mac_info.filter_type;
6409         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6410                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6411                 if (vlan_num == 0) {
6412                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6413                         return I40E_ERR_PARAM;
6414                 }
6415         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6416                         filter_type == RTE_MAC_HASH_MATCH)
6417                 vlan_num = 1;
6418
6419         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6420         if (mv_f == NULL) {
6421                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6422                 return I40E_ERR_NO_MEMORY;
6423         }
6424
6425         for (i = 0; i < vlan_num; i++) {
6426                 mv_f[i].filter_type = filter_type;
6427                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6428                                 ETH_ADDR_LEN);
6429         }
6430         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6431                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6432                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6433                 if (ret != I40E_SUCCESS)
6434                         goto DONE;
6435         }
6436
6437         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6438         if (ret != I40E_SUCCESS)
6439                 goto DONE;
6440
6441         /* Remove the mac addr into mac list */
6442         TAILQ_REMOVE(&vsi->mac_list, f, next);
6443         rte_free(f);
6444         vsi->mac_num--;
6445
6446         ret = I40E_SUCCESS;
6447 DONE:
6448         rte_free(mv_f);
6449         return ret;
6450 }
6451
6452 /* Configure hash enable flags for RSS */
6453 uint64_t
6454 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6455 {
6456         uint64_t hena = 0;
6457
6458         if (!flags)
6459                 return hena;
6460
6461         if (flags & ETH_RSS_FRAG_IPV4)
6462                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6463         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6464                 if (type == I40E_MAC_X722) {
6465                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6466                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6467                 } else
6468                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6469         }
6470         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6471                 if (type == I40E_MAC_X722) {
6472                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6473                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6474                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6475                 } else
6476                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6477         }
6478         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6479                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6480         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6481                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6482         if (flags & ETH_RSS_FRAG_IPV6)
6483                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6484         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6485                 if (type == I40E_MAC_X722) {
6486                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6487                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6488                 } else
6489                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6490         }
6491         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6492                 if (type == I40E_MAC_X722) {
6493                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6494                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6495                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6496                 } else
6497                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6498         }
6499         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6500                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6501         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6502                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6503         if (flags & ETH_RSS_L2_PAYLOAD)
6504                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6505
6506         return hena;
6507 }
6508
6509 /* Parse the hash enable flags */
6510 uint64_t
6511 i40e_parse_hena(uint64_t flags)
6512 {
6513         uint64_t rss_hf = 0;
6514
6515         if (!flags)
6516                 return rss_hf;
6517         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6518                 rss_hf |= ETH_RSS_FRAG_IPV4;
6519         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6520                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6521         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6522                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6523         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6524                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6525         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6526                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6527         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6528                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6529         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6530                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6531         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6532                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6533         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6534                 rss_hf |= ETH_RSS_FRAG_IPV6;
6535         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6536                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6537         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6538                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6539         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6540                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6541         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6542                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6543         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6544                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6545         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6546                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6547         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6548                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6549         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6550                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6551
6552         return rss_hf;
6553 }
6554
6555 /* Disable RSS */
6556 static void
6557 i40e_pf_disable_rss(struct i40e_pf *pf)
6558 {
6559         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6560         uint64_t hena;
6561
6562         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6563         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6564         if (hw->mac.type == I40E_MAC_X722)
6565                 hena &= ~I40E_RSS_HENA_ALL_X722;
6566         else
6567                 hena &= ~I40E_RSS_HENA_ALL;
6568         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6569         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6570         I40E_WRITE_FLUSH(hw);
6571 }
6572
6573 static int
6574 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6575 {
6576         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6577         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6578         int ret = 0;
6579
6580         if (!key || key_len == 0) {
6581                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6582                 return 0;
6583         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6584                 sizeof(uint32_t)) {
6585                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6586                 return -EINVAL;
6587         }
6588
6589         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6590                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6591                         (struct i40e_aqc_get_set_rss_key_data *)key;
6592
6593                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6594                 if (ret)
6595                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6596         } else {
6597                 uint32_t *hash_key = (uint32_t *)key;
6598                 uint16_t i;
6599
6600                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6601                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6602                 I40E_WRITE_FLUSH(hw);
6603         }
6604
6605         return ret;
6606 }
6607
6608 static int
6609 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6610 {
6611         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6612         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6613         int ret;
6614
6615         if (!key || !key_len)
6616                 return -EINVAL;
6617
6618         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6619                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6620                         (struct i40e_aqc_get_set_rss_key_data *)key);
6621                 if (ret) {
6622                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6623                         return ret;
6624                 }
6625         } else {
6626                 uint32_t *key_dw = (uint32_t *)key;
6627                 uint16_t i;
6628
6629                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6630                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6631         }
6632         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6633
6634         return 0;
6635 }
6636
6637 static int
6638 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6639 {
6640         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6641         uint64_t rss_hf;
6642         uint64_t hena;
6643         int ret;
6644
6645         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6646                                rss_conf->rss_key_len);
6647         if (ret)
6648                 return ret;
6649
6650         rss_hf = rss_conf->rss_hf;
6651         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6652         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6653         if (hw->mac.type == I40E_MAC_X722)
6654                 hena &= ~I40E_RSS_HENA_ALL_X722;
6655         else
6656                 hena &= ~I40E_RSS_HENA_ALL;
6657         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6658         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6659         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6660         I40E_WRITE_FLUSH(hw);
6661
6662         return 0;
6663 }
6664
6665 static int
6666 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6667                          struct rte_eth_rss_conf *rss_conf)
6668 {
6669         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6670         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6671         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6672         uint64_t hena;
6673
6674         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6675         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6676         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6677                  ? I40E_RSS_HENA_ALL_X722
6678                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6679                 if (rss_hf != 0) /* Enable RSS */
6680                         return -EINVAL;
6681                 return 0; /* Nothing to do */
6682         }
6683         /* RSS enabled */
6684         if (rss_hf == 0) /* Disable RSS */
6685                 return -EINVAL;
6686
6687         return i40e_hw_rss_hash_set(pf, rss_conf);
6688 }
6689
6690 static int
6691 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6692                            struct rte_eth_rss_conf *rss_conf)
6693 {
6694         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6695         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6696         uint64_t hena;
6697
6698         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6699                          &rss_conf->rss_key_len);
6700
6701         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6702         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6703         rss_conf->rss_hf = i40e_parse_hena(hena);
6704
6705         return 0;
6706 }
6707
6708 static int
6709 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6710 {
6711         switch (filter_type) {
6712         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6713                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6714                 break;
6715         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6716                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6717                 break;
6718         case RTE_TUNNEL_FILTER_IMAC_TENID:
6719                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6720                 break;
6721         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6722                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6723                 break;
6724         case ETH_TUNNEL_FILTER_IMAC:
6725                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6726                 break;
6727         case ETH_TUNNEL_FILTER_OIP:
6728                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6729                 break;
6730         case ETH_TUNNEL_FILTER_IIP:
6731                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6732                 break;
6733         default:
6734                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6735                 return -EINVAL;
6736         }
6737
6738         return 0;
6739 }
6740
6741 /* Convert tunnel filter structure */
6742 static int
6743 i40e_tunnel_filter_convert(
6744         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6745         struct i40e_tunnel_filter *tunnel_filter)
6746 {
6747         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6748                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6749         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6750                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6751         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6752         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6753              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6754             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6755                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6756         else
6757                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6758         tunnel_filter->input.flags = cld_filter->element.flags;
6759         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6760         tunnel_filter->queue = cld_filter->element.queue_number;
6761         rte_memcpy(tunnel_filter->input.general_fields,
6762                    cld_filter->general_fields,
6763                    sizeof(cld_filter->general_fields));
6764
6765         return 0;
6766 }
6767
6768 /* Check if there exists the tunnel filter */
6769 struct i40e_tunnel_filter *
6770 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6771                              const struct i40e_tunnel_filter_input *input)
6772 {
6773         int ret;
6774
6775         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6776         if (ret < 0)
6777                 return NULL;
6778
6779         return tunnel_rule->hash_map[ret];
6780 }
6781
6782 /* Add a tunnel filter into the SW list */
6783 static int
6784 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6785                              struct i40e_tunnel_filter *tunnel_filter)
6786 {
6787         struct i40e_tunnel_rule *rule = &pf->tunnel;
6788         int ret;
6789
6790         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6791         if (ret < 0) {
6792                 PMD_DRV_LOG(ERR,
6793                             "Failed to insert tunnel filter to hash table %d!",
6794                             ret);
6795                 return ret;
6796         }
6797         rule->hash_map[ret] = tunnel_filter;
6798
6799         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6800
6801         return 0;
6802 }
6803
6804 /* Delete a tunnel filter from the SW list */
6805 int
6806 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6807                           struct i40e_tunnel_filter_input *input)
6808 {
6809         struct i40e_tunnel_rule *rule = &pf->tunnel;
6810         struct i40e_tunnel_filter *tunnel_filter;
6811         int ret;
6812
6813         ret = rte_hash_del_key(rule->hash_table, input);
6814         if (ret < 0) {
6815                 PMD_DRV_LOG(ERR,
6816                             "Failed to delete tunnel filter to hash table %d!",
6817                             ret);
6818                 return ret;
6819         }
6820         tunnel_filter = rule->hash_map[ret];
6821         rule->hash_map[ret] = NULL;
6822
6823         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6824         rte_free(tunnel_filter);
6825
6826         return 0;
6827 }
6828
6829 int
6830 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6831                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6832                         uint8_t add)
6833 {
6834         uint16_t ip_type;
6835         uint32_t ipv4_addr;
6836         uint8_t i, tun_type = 0;
6837         /* internal varialbe to convert ipv6 byte order */
6838         uint32_t convert_ipv6[4];
6839         int val, ret = 0;
6840         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6841         struct i40e_vsi *vsi = pf->main_vsi;
6842         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6843         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6844         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6845         struct i40e_tunnel_filter *tunnel, *node;
6846         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6847
6848         cld_filter = rte_zmalloc("tunnel_filter",
6849                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6850         0);
6851
6852         if (NULL == cld_filter) {
6853                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6854                 return -ENOMEM;
6855         }
6856         pfilter = cld_filter;
6857
6858         ether_addr_copy(&tunnel_filter->outer_mac,
6859                         (struct ether_addr *)&pfilter->element.outer_mac);
6860         ether_addr_copy(&tunnel_filter->inner_mac,
6861                         (struct ether_addr *)&pfilter->element.inner_mac);
6862
6863         pfilter->element.inner_vlan =
6864                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6865         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6866                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6867                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6868                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6869                                 &rte_cpu_to_le_32(ipv4_addr),
6870                                 sizeof(pfilter->element.ipaddr.v4.data));
6871         } else {
6872                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6873                 for (i = 0; i < 4; i++) {
6874                         convert_ipv6[i] =
6875                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6876                 }
6877                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6878                            &convert_ipv6,
6879                            sizeof(pfilter->element.ipaddr.v6.data));
6880         }
6881
6882         /* check tunneled type */
6883         switch (tunnel_filter->tunnel_type) {
6884         case RTE_TUNNEL_TYPE_VXLAN:
6885                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6886                 break;
6887         case RTE_TUNNEL_TYPE_NVGRE:
6888                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6889                 break;
6890         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6891                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6892                 break;
6893         default:
6894                 /* Other tunnel types is not supported. */
6895                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6896                 rte_free(cld_filter);
6897                 return -EINVAL;
6898         }
6899
6900         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6901                                        &pfilter->element.flags);
6902         if (val < 0) {
6903                 rte_free(cld_filter);
6904                 return -EINVAL;
6905         }
6906
6907         pfilter->element.flags |= rte_cpu_to_le_16(
6908                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6909                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6910         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6911         pfilter->element.queue_number =
6912                 rte_cpu_to_le_16(tunnel_filter->queue_id);
6913
6914         /* Check if there is the filter in SW list */
6915         memset(&check_filter, 0, sizeof(check_filter));
6916         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6917         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6918         if (add && node) {
6919                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6920                 return -EINVAL;
6921         }
6922
6923         if (!add && !node) {
6924                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6925                 return -EINVAL;
6926         }
6927
6928         if (add) {
6929                 ret = i40e_aq_add_cloud_filters(hw,
6930                                         vsi->seid, &cld_filter->element, 1);
6931                 if (ret < 0) {
6932                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6933                         return -ENOTSUP;
6934                 }
6935                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6936                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6937                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6938         } else {
6939                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6940                                                    &cld_filter->element, 1);
6941                 if (ret < 0) {
6942                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6943                         return -ENOTSUP;
6944                 }
6945                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6946         }
6947
6948         rte_free(cld_filter);
6949         return ret;
6950 }
6951
6952 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
6953 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
6954 #define I40E_TR_GENEVE_KEY_MASK                 0x8
6955 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
6956 #define I40E_TR_GRE_KEY_MASK                    0x400
6957 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
6958 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
6959
6960 static enum
6961 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
6962 {
6963         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
6964         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
6965         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6966         enum i40e_status_code status = I40E_SUCCESS;
6967
6968         memset(&filter_replace, 0,
6969                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
6970         memset(&filter_replace_buf, 0,
6971                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
6972
6973         /* create L1 filter */
6974         filter_replace.old_filter_type =
6975                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
6976         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
6977         filter_replace.tr_bit = 0;
6978
6979         /* Prepare the buffer, 3 entries */
6980         filter_replace_buf.data[0] =
6981                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
6982         filter_replace_buf.data[0] |=
6983                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6984         filter_replace_buf.data[2] = 0xFF;
6985         filter_replace_buf.data[3] = 0xFF;
6986         filter_replace_buf.data[4] =
6987                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
6988         filter_replace_buf.data[4] |=
6989                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6990         filter_replace_buf.data[7] = 0xF0;
6991         filter_replace_buf.data[8]
6992                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
6993         filter_replace_buf.data[8] |=
6994                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6995         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
6996                 I40E_TR_GENEVE_KEY_MASK |
6997                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
6998         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
6999                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7000                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7001
7002         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7003                                                &filter_replace_buf);
7004         return status;
7005 }
7006
7007 static enum
7008 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7009 {
7010         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7011         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7012         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7013         enum i40e_status_code status = I40E_SUCCESS;
7014
7015         /* For MPLSoUDP */
7016         memset(&filter_replace, 0,
7017                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7018         memset(&filter_replace_buf, 0,
7019                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7020         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7021                 I40E_AQC_MIRROR_CLOUD_FILTER;
7022         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7023         filter_replace.new_filter_type =
7024                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7025         /* Prepare the buffer, 2 entries */
7026         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7027         filter_replace_buf.data[0] |=
7028                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7029         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7030         filter_replace_buf.data[4] |=
7031                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7032         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7033                                                &filter_replace_buf);
7034         if (status < 0)
7035                 return status;
7036
7037         /* For MPLSoGRE */
7038         memset(&filter_replace, 0,
7039                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7040         memset(&filter_replace_buf, 0,
7041                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7042
7043         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7044                 I40E_AQC_MIRROR_CLOUD_FILTER;
7045         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7046         filter_replace.new_filter_type =
7047                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7048         /* Prepare the buffer, 2 entries */
7049         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7050         filter_replace_buf.data[0] |=
7051                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7052         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7053         filter_replace_buf.data[4] |=
7054                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7055
7056         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7057                                                &filter_replace_buf);
7058         return status;
7059 }
7060
7061 int
7062 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7063                       struct i40e_tunnel_filter_conf *tunnel_filter,
7064                       uint8_t add)
7065 {
7066         uint16_t ip_type;
7067         uint32_t ipv4_addr;
7068         uint8_t i, tun_type = 0;
7069         /* internal variable to convert ipv6 byte order */
7070         uint32_t convert_ipv6[4];
7071         int val, ret = 0;
7072         struct i40e_pf_vf *vf = NULL;
7073         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7074         struct i40e_vsi *vsi;
7075         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7076         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7077         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7078         struct i40e_tunnel_filter *tunnel, *node;
7079         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7080         uint32_t teid_le;
7081         bool big_buffer = 0;
7082
7083         cld_filter = rte_zmalloc("tunnel_filter",
7084                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7085                          0);
7086
7087         if (cld_filter == NULL) {
7088                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7089                 return -ENOMEM;
7090         }
7091         pfilter = cld_filter;
7092
7093         ether_addr_copy(&tunnel_filter->outer_mac,
7094                         (struct ether_addr *)&pfilter->element.outer_mac);
7095         ether_addr_copy(&tunnel_filter->inner_mac,
7096                         (struct ether_addr *)&pfilter->element.inner_mac);
7097
7098         pfilter->element.inner_vlan =
7099                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7100         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7101                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7102                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7103                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7104                                 &rte_cpu_to_le_32(ipv4_addr),
7105                                 sizeof(pfilter->element.ipaddr.v4.data));
7106         } else {
7107                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7108                 for (i = 0; i < 4; i++) {
7109                         convert_ipv6[i] =
7110                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7111                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7112                 }
7113                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7114                            &convert_ipv6,
7115                            sizeof(pfilter->element.ipaddr.v6.data));
7116         }
7117
7118         /* check tunneled type */
7119         switch (tunnel_filter->tunnel_type) {
7120         case I40E_TUNNEL_TYPE_VXLAN:
7121                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7122                 break;
7123         case I40E_TUNNEL_TYPE_NVGRE:
7124                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7125                 break;
7126         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7127                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7128                 break;
7129         case I40E_TUNNEL_TYPE_MPLSoUDP:
7130                 if (!pf->mpls_replace_flag) {
7131                         i40e_replace_mpls_l1_filter(pf);
7132                         i40e_replace_mpls_cloud_filter(pf);
7133                         pf->mpls_replace_flag = 1;
7134                 }
7135                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7136                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7137                         teid_le >> 4;
7138                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7139                         (teid_le & 0xF) << 12;
7140                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7141                         0x40;
7142                 big_buffer = 1;
7143                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7144                 break;
7145         case I40E_TUNNEL_TYPE_MPLSoGRE:
7146                 if (!pf->mpls_replace_flag) {
7147                         i40e_replace_mpls_l1_filter(pf);
7148                         i40e_replace_mpls_cloud_filter(pf);
7149                         pf->mpls_replace_flag = 1;
7150                 }
7151                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7152                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7153                         teid_le >> 4;
7154                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7155                         (teid_le & 0xF) << 12;
7156                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7157                         0x0;
7158                 big_buffer = 1;
7159                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7160                 break;
7161         case I40E_TUNNEL_TYPE_QINQ:
7162                 if (!pf->qinq_replace_flag) {
7163                         ret = i40e_cloud_filter_qinq_create(pf);
7164                         if (ret < 0)
7165                                 PMD_DRV_LOG(ERR,
7166                                         "Failed to create a qinq tunnel filter.");
7167                         pf->qinq_replace_flag = 1;
7168                 }
7169                 /*      Add in the General fields the values of
7170                  *      the Outer and Inner VLAN
7171                  *      Big Buffer should be set, see changes in
7172                  *      i40e_aq_add_cloud_filters
7173                  */
7174                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7175                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7176                 big_buffer = 1;
7177                 break;
7178         default:
7179                 /* Other tunnel types is not supported. */
7180                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7181                 rte_free(cld_filter);
7182                 return -EINVAL;
7183         }
7184
7185         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7186                 pfilter->element.flags =
7187                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7188         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7189                 pfilter->element.flags =
7190                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7191         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7192                 pfilter->element.flags |=
7193                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7194         else {
7195                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7196                                                 &pfilter->element.flags);
7197                 if (val < 0) {
7198                         rte_free(cld_filter);
7199                         return -EINVAL;
7200                 }
7201         }
7202
7203         pfilter->element.flags |= rte_cpu_to_le_16(
7204                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7205                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7206         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7207         pfilter->element.queue_number =
7208                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7209
7210         if (!tunnel_filter->is_to_vf)
7211                 vsi = pf->main_vsi;
7212         else {
7213                 if (tunnel_filter->vf_id >= pf->vf_num) {
7214                         PMD_DRV_LOG(ERR, "Invalid argument.");
7215                         return -EINVAL;
7216                 }
7217                 vf = &pf->vfs[tunnel_filter->vf_id];
7218                 vsi = vf->vsi;
7219         }
7220
7221         /* Check if there is the filter in SW list */
7222         memset(&check_filter, 0, sizeof(check_filter));
7223         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7224         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7225         if (add && node) {
7226                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7227                 return -EINVAL;
7228         }
7229
7230         if (!add && !node) {
7231                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7232                 return -EINVAL;
7233         }
7234
7235         if (add) {
7236                 if (big_buffer)
7237                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7238                                                    vsi->seid, cld_filter, 1);
7239                 else
7240                         ret = i40e_aq_add_cloud_filters(hw,
7241                                         vsi->seid, &cld_filter->element, 1);
7242                 if (ret < 0) {
7243                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7244                         return -ENOTSUP;
7245                 }
7246                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7247                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7248                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7249         } else {
7250                 if (big_buffer)
7251                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7252                                 hw, vsi->seid, cld_filter, 1);
7253                 else
7254                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7255                                                    &cld_filter->element, 1);
7256                 if (ret < 0) {
7257                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7258                         return -ENOTSUP;
7259                 }
7260                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7261         }
7262
7263         rte_free(cld_filter);
7264         return ret;
7265 }
7266
7267 static int
7268 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7269 {
7270         uint8_t i;
7271
7272         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7273                 if (pf->vxlan_ports[i] == port)
7274                         return i;
7275         }
7276
7277         return -1;
7278 }
7279
7280 static int
7281 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7282 {
7283         int  idx, ret;
7284         uint8_t filter_idx;
7285         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7286
7287         idx = i40e_get_vxlan_port_idx(pf, port);
7288
7289         /* Check if port already exists */
7290         if (idx >= 0) {
7291                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7292                 return -EINVAL;
7293         }
7294
7295         /* Now check if there is space to add the new port */
7296         idx = i40e_get_vxlan_port_idx(pf, 0);
7297         if (idx < 0) {
7298                 PMD_DRV_LOG(ERR,
7299                         "Maximum number of UDP ports reached, not adding port %d",
7300                         port);
7301                 return -ENOSPC;
7302         }
7303
7304         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7305                                         &filter_idx, NULL);
7306         if (ret < 0) {
7307                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7308                 return -1;
7309         }
7310
7311         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7312                          port,  filter_idx);
7313
7314         /* New port: add it and mark its index in the bitmap */
7315         pf->vxlan_ports[idx] = port;
7316         pf->vxlan_bitmap |= (1 << idx);
7317
7318         if (!(pf->flags & I40E_FLAG_VXLAN))
7319                 pf->flags |= I40E_FLAG_VXLAN;
7320
7321         return 0;
7322 }
7323
7324 static int
7325 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7326 {
7327         int idx;
7328         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7329
7330         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7331                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7332                 return -EINVAL;
7333         }
7334
7335         idx = i40e_get_vxlan_port_idx(pf, port);
7336
7337         if (idx < 0) {
7338                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7339                 return -EINVAL;
7340         }
7341
7342         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7343                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7344                 return -1;
7345         }
7346
7347         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7348                         port, idx);
7349
7350         pf->vxlan_ports[idx] = 0;
7351         pf->vxlan_bitmap &= ~(1 << idx);
7352
7353         if (!pf->vxlan_bitmap)
7354                 pf->flags &= ~I40E_FLAG_VXLAN;
7355
7356         return 0;
7357 }
7358
7359 /* Add UDP tunneling port */
7360 static int
7361 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7362                              struct rte_eth_udp_tunnel *udp_tunnel)
7363 {
7364         int ret = 0;
7365         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7366
7367         if (udp_tunnel == NULL)
7368                 return -EINVAL;
7369
7370         switch (udp_tunnel->prot_type) {
7371         case RTE_TUNNEL_TYPE_VXLAN:
7372                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7373                 break;
7374
7375         case RTE_TUNNEL_TYPE_GENEVE:
7376         case RTE_TUNNEL_TYPE_TEREDO:
7377                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7378                 ret = -1;
7379                 break;
7380
7381         default:
7382                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7383                 ret = -1;
7384                 break;
7385         }
7386
7387         return ret;
7388 }
7389
7390 /* Remove UDP tunneling port */
7391 static int
7392 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7393                              struct rte_eth_udp_tunnel *udp_tunnel)
7394 {
7395         int ret = 0;
7396         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7397
7398         if (udp_tunnel == NULL)
7399                 return -EINVAL;
7400
7401         switch (udp_tunnel->prot_type) {
7402         case RTE_TUNNEL_TYPE_VXLAN:
7403                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7404                 break;
7405         case RTE_TUNNEL_TYPE_GENEVE:
7406         case RTE_TUNNEL_TYPE_TEREDO:
7407                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7408                 ret = -1;
7409                 break;
7410         default:
7411                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7412                 ret = -1;
7413                 break;
7414         }
7415
7416         return ret;
7417 }
7418
7419 /* Calculate the maximum number of contiguous PF queues that are configured */
7420 static int
7421 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7422 {
7423         struct rte_eth_dev_data *data = pf->dev_data;
7424         int i, num;
7425         struct i40e_rx_queue *rxq;
7426
7427         num = 0;
7428         for (i = 0; i < pf->lan_nb_qps; i++) {
7429                 rxq = data->rx_queues[i];
7430                 if (rxq && rxq->q_set)
7431                         num++;
7432                 else
7433                         break;
7434         }
7435
7436         return num;
7437 }
7438
7439 /* Configure RSS */
7440 static int
7441 i40e_pf_config_rss(struct i40e_pf *pf)
7442 {
7443         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7444         struct rte_eth_rss_conf rss_conf;
7445         uint32_t i, lut = 0;
7446         uint16_t j, num;
7447
7448         /*
7449          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7450          * It's necessary to calulate the actual PF queues that are configured.
7451          */
7452         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7453                 num = i40e_pf_calc_configured_queues_num(pf);
7454         else
7455                 num = pf->dev_data->nb_rx_queues;
7456
7457         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7458         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7459                         num);
7460
7461         if (num == 0) {
7462                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7463                 return -ENOTSUP;
7464         }
7465
7466         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7467                 if (j == num)
7468                         j = 0;
7469                 lut = (lut << 8) | (j & ((0x1 <<
7470                         hw->func_caps.rss_table_entry_width) - 1));
7471                 if ((i & 3) == 3)
7472                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7473         }
7474
7475         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7476         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7477                 i40e_pf_disable_rss(pf);
7478                 return 0;
7479         }
7480         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7481                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7482                 /* Random default keys */
7483                 static uint32_t rss_key_default[] = {0x6b793944,
7484                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7485                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7486                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7487
7488                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7489                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7490                                                         sizeof(uint32_t);
7491         }
7492
7493         return i40e_hw_rss_hash_set(pf, &rss_conf);
7494 }
7495
7496 static int
7497 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7498                                struct rte_eth_tunnel_filter_conf *filter)
7499 {
7500         if (pf == NULL || filter == NULL) {
7501                 PMD_DRV_LOG(ERR, "Invalid parameter");
7502                 return -EINVAL;
7503         }
7504
7505         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7506                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7507                 return -EINVAL;
7508         }
7509
7510         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7511                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7512                 return -EINVAL;
7513         }
7514
7515         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7516                 (is_zero_ether_addr(&filter->outer_mac))) {
7517                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7518                 return -EINVAL;
7519         }
7520
7521         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7522                 (is_zero_ether_addr(&filter->inner_mac))) {
7523                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7524                 return -EINVAL;
7525         }
7526
7527         return 0;
7528 }
7529
7530 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7531 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7532 static int
7533 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7534 {
7535         uint32_t val, reg;
7536         int ret = -EINVAL;
7537
7538         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7539         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7540
7541         if (len == 3) {
7542                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7543         } else if (len == 4) {
7544                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7545         } else {
7546                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7547                 return ret;
7548         }
7549
7550         if (reg != val) {
7551                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7552                                                    reg, NULL);
7553                 if (ret != 0)
7554                         return ret;
7555         } else {
7556                 ret = 0;
7557         }
7558         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7559                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7560
7561         return ret;
7562 }
7563
7564 static int
7565 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7566 {
7567         int ret = -EINVAL;
7568
7569         if (!hw || !cfg)
7570                 return -EINVAL;
7571
7572         switch (cfg->cfg_type) {
7573         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7574                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7575                 break;
7576         default:
7577                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7578                 break;
7579         }
7580
7581         return ret;
7582 }
7583
7584 static int
7585 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7586                                enum rte_filter_op filter_op,
7587                                void *arg)
7588 {
7589         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7590         int ret = I40E_ERR_PARAM;
7591
7592         switch (filter_op) {
7593         case RTE_ETH_FILTER_SET:
7594                 ret = i40e_dev_global_config_set(hw,
7595                         (struct rte_eth_global_cfg *)arg);
7596                 break;
7597         default:
7598                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7599                 break;
7600         }
7601
7602         return ret;
7603 }
7604
7605 static int
7606 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7607                           enum rte_filter_op filter_op,
7608                           void *arg)
7609 {
7610         struct rte_eth_tunnel_filter_conf *filter;
7611         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7612         int ret = I40E_SUCCESS;
7613
7614         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7615
7616         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7617                 return I40E_ERR_PARAM;
7618
7619         switch (filter_op) {
7620         case RTE_ETH_FILTER_NOP:
7621                 if (!(pf->flags & I40E_FLAG_VXLAN))
7622                         ret = I40E_NOT_SUPPORTED;
7623                 break;
7624         case RTE_ETH_FILTER_ADD:
7625                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7626                 break;
7627         case RTE_ETH_FILTER_DELETE:
7628                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7629                 break;
7630         default:
7631                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7632                 ret = I40E_ERR_PARAM;
7633                 break;
7634         }
7635
7636         return ret;
7637 }
7638
7639 static int
7640 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7641 {
7642         int ret = 0;
7643         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7644
7645         /* RSS setup */
7646         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7647                 ret = i40e_pf_config_rss(pf);
7648         else
7649                 i40e_pf_disable_rss(pf);
7650
7651         return ret;
7652 }
7653
7654 /* Get the symmetric hash enable configurations per port */
7655 static void
7656 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7657 {
7658         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7659
7660         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7661 }
7662
7663 /* Set the symmetric hash enable configurations per port */
7664 static void
7665 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7666 {
7667         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7668
7669         if (enable > 0) {
7670                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7671                         PMD_DRV_LOG(INFO,
7672                                 "Symmetric hash has already been enabled");
7673                         return;
7674                 }
7675                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7676         } else {
7677                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7678                         PMD_DRV_LOG(INFO,
7679                                 "Symmetric hash has already been disabled");
7680                         return;
7681                 }
7682                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7683         }
7684         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7685         I40E_WRITE_FLUSH(hw);
7686 }
7687
7688 /*
7689  * Get global configurations of hash function type and symmetric hash enable
7690  * per flow type (pctype). Note that global configuration means it affects all
7691  * the ports on the same NIC.
7692  */
7693 static int
7694 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7695                                    struct rte_eth_hash_global_conf *g_cfg)
7696 {
7697         uint32_t reg, mask = I40E_FLOW_TYPES;
7698         uint16_t i;
7699         enum i40e_filter_pctype pctype;
7700
7701         memset(g_cfg, 0, sizeof(*g_cfg));
7702         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7703         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7704                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7705         else
7706                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7707         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7708                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7709
7710         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7711                 if (!(mask & (1UL << i)))
7712                         continue;
7713                 mask &= ~(1UL << i);
7714                 /* Bit set indicats the coresponding flow type is supported */
7715                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7716                 /* if flowtype is invalid, continue */
7717                 if (!I40E_VALID_FLOW(i))
7718                         continue;
7719                 pctype = i40e_flowtype_to_pctype(i);
7720                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7721                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7722                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7723         }
7724
7725         return 0;
7726 }
7727
7728 static int
7729 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7730 {
7731         uint32_t i;
7732         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7733
7734         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7735                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7736                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7737                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7738                                                 g_cfg->hash_func);
7739                 return -EINVAL;
7740         }
7741
7742         /*
7743          * As i40e supports less than 32 flow types, only first 32 bits need to
7744          * be checked.
7745          */
7746         mask0 = g_cfg->valid_bit_mask[0];
7747         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7748                 if (i == 0) {
7749                         /* Check if any unsupported flow type configured */
7750                         if ((mask0 | i40e_mask) ^ i40e_mask)
7751                                 goto mask_err;
7752                 } else {
7753                         if (g_cfg->valid_bit_mask[i])
7754                                 goto mask_err;
7755                 }
7756         }
7757
7758         return 0;
7759
7760 mask_err:
7761         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7762
7763         return -EINVAL;
7764 }
7765
7766 /*
7767  * Set global configurations of hash function type and symmetric hash enable
7768  * per flow type (pctype). Note any modifying global configuration will affect
7769  * all the ports on the same NIC.
7770  */
7771 static int
7772 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7773                                    struct rte_eth_hash_global_conf *g_cfg)
7774 {
7775         int ret;
7776         uint16_t i;
7777         uint32_t reg;
7778         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7779         enum i40e_filter_pctype pctype;
7780
7781         /* Check the input parameters */
7782         ret = i40e_hash_global_config_check(g_cfg);
7783         if (ret < 0)
7784                 return ret;
7785
7786         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7787                 if (!(mask0 & (1UL << i)))
7788                         continue;
7789                 mask0 &= ~(1UL << i);
7790                 /* if flowtype is invalid, continue */
7791                 if (!I40E_VALID_FLOW(i))
7792                         continue;
7793                 pctype = i40e_flowtype_to_pctype(i);
7794                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7795                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7796                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7797         }
7798
7799         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7800         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7801                 /* Toeplitz */
7802                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7803                         PMD_DRV_LOG(DEBUG,
7804                                 "Hash function already set to Toeplitz");
7805                         goto out;
7806                 }
7807                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7808         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7809                 /* Simple XOR */
7810                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7811                         PMD_DRV_LOG(DEBUG,
7812                                 "Hash function already set to Simple XOR");
7813                         goto out;
7814                 }
7815                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7816         } else
7817                 /* Use the default, and keep it as it is */
7818                 goto out;
7819
7820         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7821
7822 out:
7823         I40E_WRITE_FLUSH(hw);
7824
7825         return 0;
7826 }
7827
7828 /**
7829  * Valid input sets for hash and flow director filters per PCTYPE
7830  */
7831 static uint64_t
7832 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7833                 enum rte_filter_type filter)
7834 {
7835         uint64_t valid;
7836
7837         static const uint64_t valid_hash_inset_table[] = {
7838                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7839                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7840                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7841                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7842                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7843                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7844                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7845                         I40E_INSET_FLEX_PAYLOAD,
7846                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7847                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7848                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7849                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7850                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7851                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7852                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7853                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7854                         I40E_INSET_FLEX_PAYLOAD,
7855                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7856                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7857                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7858                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7859                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7860                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7861                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7862                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7863                         I40E_INSET_FLEX_PAYLOAD,
7864                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7865                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7866                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7867                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7868                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7869                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7870                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7871                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7872                         I40E_INSET_FLEX_PAYLOAD,
7873                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7874                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7875                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7876                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7877                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7878                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7879                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7880                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7881                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7882                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7883                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7884                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7885                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7886                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7887                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7888                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7889                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7890                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7891                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7892                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7893                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7894                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7895                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7896                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7897                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7898                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7899                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7900                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7901                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7902                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7903                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7904                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7905                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7906                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7907                         I40E_INSET_FLEX_PAYLOAD,
7908                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7909                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7910                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7911                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7912                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7913                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7914                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7915                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7916                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7917                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7918                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7919                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7920                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7921                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7922                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7923                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7924                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7925                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7926                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7927                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7928                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7929                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7930                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7931                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7932                         I40E_INSET_FLEX_PAYLOAD,
7933                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7934                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7935                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7936                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7937                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7938                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7939                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7940                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7941                         I40E_INSET_FLEX_PAYLOAD,
7942                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7943                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7944                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7945                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7946                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7947                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7948                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7949                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7950                         I40E_INSET_FLEX_PAYLOAD,
7951                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7952                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7953                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7954                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7955                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7956                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7957                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7958                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7959                         I40E_INSET_FLEX_PAYLOAD,
7960                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7961                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7962                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7963                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7964                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7965                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7966                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7967                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7968                         I40E_INSET_FLEX_PAYLOAD,
7969                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7970                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7971                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7972                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7973                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7974                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7975                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7976                         I40E_INSET_FLEX_PAYLOAD,
7977                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7978                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7979                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7980                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7981                         I40E_INSET_FLEX_PAYLOAD,
7982         };
7983
7984         /**
7985          * Flow director supports only fields defined in
7986          * union rte_eth_fdir_flow.
7987          */
7988         static const uint64_t valid_fdir_inset_table[] = {
7989                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7990                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7991                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7992                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7993                 I40E_INSET_IPV4_TTL,
7994                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7995                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7996                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7997                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7998                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7999                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8000                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8001                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8002                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8003                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8004                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8005                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8006                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8007                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8008                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8009                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8010                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8011                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8012                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8013                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8014                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8015                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8016                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8017                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8018                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8019                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8020                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8021                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8022                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8023                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8024                 I40E_INSET_SCTP_VT,
8025                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8026                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8027                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8028                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8029                 I40E_INSET_IPV4_TTL,
8030                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8031                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8032                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8033                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8034                 I40E_INSET_IPV6_HOP_LIMIT,
8035                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8036                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8037                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8038                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8039                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8040                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8041                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8042                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8043                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8044                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8045                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8046                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8047                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8048                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8049                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8050                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8051                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8052                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8053                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8054                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8055                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8056                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8057                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8058                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8059                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8060                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8061                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8062                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8063                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8064                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8065                 I40E_INSET_SCTP_VT,
8066                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8067                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8068                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8069                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8070                 I40E_INSET_IPV6_HOP_LIMIT,
8071                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8072                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8073                 I40E_INSET_LAST_ETHER_TYPE,
8074         };
8075
8076         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8077                 return 0;
8078         if (filter == RTE_ETH_FILTER_HASH)
8079                 valid = valid_hash_inset_table[pctype];
8080         else
8081                 valid = valid_fdir_inset_table[pctype];
8082
8083         return valid;
8084 }
8085
8086 /**
8087  * Validate if the input set is allowed for a specific PCTYPE
8088  */
8089 static int
8090 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8091                 enum rte_filter_type filter, uint64_t inset)
8092 {
8093         uint64_t valid;
8094
8095         valid = i40e_get_valid_input_set(pctype, filter);
8096         if (inset & (~valid))
8097                 return -EINVAL;
8098
8099         return 0;
8100 }
8101
8102 /* default input set fields combination per pctype */
8103 uint64_t
8104 i40e_get_default_input_set(uint16_t pctype)
8105 {
8106         static const uint64_t default_inset_table[] = {
8107                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8108                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8109                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8110                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8111                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8112                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8113                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8114                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8115                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8116                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8117                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8118                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8119                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8120                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8121                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8122                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8123                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8124                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8125                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8126                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8127                         I40E_INSET_SCTP_VT,
8128                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8129                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8130                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8131                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8132                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8133                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8134                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8135                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8136                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8137                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8138                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8139                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8140                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8141                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8142                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8143                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8144                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8145                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8146                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8147                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8148                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8149                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8150                         I40E_INSET_SCTP_VT,
8151                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8152                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8153                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8154                         I40E_INSET_LAST_ETHER_TYPE,
8155         };
8156
8157         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8158                 return 0;
8159
8160         return default_inset_table[pctype];
8161 }
8162
8163 /**
8164  * Parse the input set from index to logical bit masks
8165  */
8166 static int
8167 i40e_parse_input_set(uint64_t *inset,
8168                      enum i40e_filter_pctype pctype,
8169                      enum rte_eth_input_set_field *field,
8170                      uint16_t size)
8171 {
8172         uint16_t i, j;
8173         int ret = -EINVAL;
8174
8175         static const struct {
8176                 enum rte_eth_input_set_field field;
8177                 uint64_t inset;
8178         } inset_convert_table[] = {
8179                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8180                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8181                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8182                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8183                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8184                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8185                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8186                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8187                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8188                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8189                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8190                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8191                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8192                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8193                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8194                         I40E_INSET_IPV6_NEXT_HDR},
8195                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8196                         I40E_INSET_IPV6_HOP_LIMIT},
8197                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8198                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8199                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8200                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8201                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8202                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8203                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8204                         I40E_INSET_SCTP_VT},
8205                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8206                         I40E_INSET_TUNNEL_DMAC},
8207                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8208                         I40E_INSET_VLAN_TUNNEL},
8209                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8210                         I40E_INSET_TUNNEL_ID},
8211                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8212                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8213                         I40E_INSET_FLEX_PAYLOAD_W1},
8214                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8215                         I40E_INSET_FLEX_PAYLOAD_W2},
8216                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8217                         I40E_INSET_FLEX_PAYLOAD_W3},
8218                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8219                         I40E_INSET_FLEX_PAYLOAD_W4},
8220                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8221                         I40E_INSET_FLEX_PAYLOAD_W5},
8222                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8223                         I40E_INSET_FLEX_PAYLOAD_W6},
8224                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8225                         I40E_INSET_FLEX_PAYLOAD_W7},
8226                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8227                         I40E_INSET_FLEX_PAYLOAD_W8},
8228         };
8229
8230         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8231                 return ret;
8232
8233         /* Only one item allowed for default or all */
8234         if (size == 1) {
8235                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8236                         *inset = i40e_get_default_input_set(pctype);
8237                         return 0;
8238                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8239                         *inset = I40E_INSET_NONE;
8240                         return 0;
8241                 }
8242         }
8243
8244         for (i = 0, *inset = 0; i < size; i++) {
8245                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8246                         if (field[i] == inset_convert_table[j].field) {
8247                                 *inset |= inset_convert_table[j].inset;
8248                                 break;
8249                         }
8250                 }
8251
8252                 /* It contains unsupported input set, return immediately */
8253                 if (j == RTE_DIM(inset_convert_table))
8254                         return ret;
8255         }
8256
8257         return 0;
8258 }
8259
8260 /**
8261  * Translate the input set from bit masks to register aware bit masks
8262  * and vice versa
8263  */
8264 static uint64_t
8265 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8266 {
8267         uint64_t val = 0;
8268         uint16_t i;
8269
8270         struct inset_map {
8271                 uint64_t inset;
8272                 uint64_t inset_reg;
8273         };
8274
8275         static const struct inset_map inset_map_common[] = {
8276                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8277                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8278                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8279                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8280                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8281                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8282                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8283                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8284                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8285                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8286                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8287                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8288                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8289                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8290                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8291                 {I40E_INSET_TUNNEL_DMAC,
8292                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8293                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8294                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8295                 {I40E_INSET_TUNNEL_SRC_PORT,
8296                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8297                 {I40E_INSET_TUNNEL_DST_PORT,
8298                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8299                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8300                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8301                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8302                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8303                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8304                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8305                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8306                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8307                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8308         };
8309
8310     /* some different registers map in x722*/
8311         static const struct inset_map inset_map_diff_x722[] = {
8312                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8313                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8314                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8315                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8316         };
8317
8318         static const struct inset_map inset_map_diff_not_x722[] = {
8319                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8320                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8321                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8322                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8323         };
8324
8325         if (input == 0)
8326                 return val;
8327
8328         /* Translate input set to register aware inset */
8329         if (type == I40E_MAC_X722) {
8330                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8331                         if (input & inset_map_diff_x722[i].inset)
8332                                 val |= inset_map_diff_x722[i].inset_reg;
8333                 }
8334         } else {
8335                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8336                         if (input & inset_map_diff_not_x722[i].inset)
8337                                 val |= inset_map_diff_not_x722[i].inset_reg;
8338                 }
8339         }
8340
8341         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8342                 if (input & inset_map_common[i].inset)
8343                         val |= inset_map_common[i].inset_reg;
8344         }
8345
8346         return val;
8347 }
8348
8349 static int
8350 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8351 {
8352         uint8_t i, idx = 0;
8353         uint64_t inset_need_mask = inset;
8354
8355         static const struct {
8356                 uint64_t inset;
8357                 uint32_t mask;
8358         } inset_mask_map[] = {
8359                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8360                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8361                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8362                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8363                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8364                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8365                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8366                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8367         };
8368
8369         if (!inset || !mask || !nb_elem)
8370                 return 0;
8371
8372         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8373                 /* Clear the inset bit, if no MASK is required,
8374                  * for example proto + ttl
8375                  */
8376                 if ((inset & inset_mask_map[i].inset) ==
8377                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8378                         inset_need_mask &= ~inset_mask_map[i].inset;
8379                 if (!inset_need_mask)
8380                         return 0;
8381         }
8382         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8383                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8384                     inset_mask_map[i].inset) {
8385                         if (idx >= nb_elem) {
8386                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8387                                 return -EINVAL;
8388                         }
8389                         mask[idx] = inset_mask_map[i].mask;
8390                         idx++;
8391                 }
8392         }
8393
8394         return idx;
8395 }
8396
8397 static void
8398 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8399 {
8400         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8401
8402         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8403         if (reg != val)
8404                 i40e_write_rx_ctl(hw, addr, val);
8405         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8406                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8407 }
8408
8409 static void
8410 i40e_filter_input_set_init(struct i40e_pf *pf)
8411 {
8412         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8413         enum i40e_filter_pctype pctype;
8414         uint64_t input_set, inset_reg;
8415         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8416         int num, i;
8417
8418         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8419              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8420                 if (hw->mac.type == I40E_MAC_X722) {
8421                         if (!I40E_VALID_PCTYPE_X722(pctype))
8422                                 continue;
8423                 } else {
8424                         if (!I40E_VALID_PCTYPE(pctype))
8425                                 continue;
8426                 }
8427
8428                 input_set = i40e_get_default_input_set(pctype);
8429
8430                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8431                                                    I40E_INSET_MASK_NUM_REG);
8432                 if (num < 0)
8433                         return;
8434                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8435                                         input_set);
8436
8437                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8438                                       (uint32_t)(inset_reg & UINT32_MAX));
8439                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8440                                      (uint32_t)((inset_reg >>
8441                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8442                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8443                                       (uint32_t)(inset_reg & UINT32_MAX));
8444                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8445                                      (uint32_t)((inset_reg >>
8446                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8447
8448                 for (i = 0; i < num; i++) {
8449                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8450                                              mask_reg[i]);
8451                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8452                                              mask_reg[i]);
8453                 }
8454                 /*clear unused mask registers of the pctype */
8455                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8456                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8457                                              0);
8458                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8459                                              0);
8460                 }
8461                 I40E_WRITE_FLUSH(hw);
8462
8463                 /* store the default input set */
8464                 pf->hash_input_set[pctype] = input_set;
8465                 pf->fdir.input_set[pctype] = input_set;
8466         }
8467 }
8468
8469 int
8470 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8471                          struct rte_eth_input_set_conf *conf)
8472 {
8473         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8474         enum i40e_filter_pctype pctype;
8475         uint64_t input_set, inset_reg = 0;
8476         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8477         int ret, i, num;
8478
8479         if (!conf) {
8480                 PMD_DRV_LOG(ERR, "Invalid pointer");
8481                 return -EFAULT;
8482         }
8483         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8484             conf->op != RTE_ETH_INPUT_SET_ADD) {
8485                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8486                 return -EINVAL;
8487         }
8488
8489         if (!I40E_VALID_FLOW(conf->flow_type)) {
8490                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8491                 return -EINVAL;
8492         }
8493
8494         if (hw->mac.type == I40E_MAC_X722) {
8495                 /* get translated pctype value in fd pctype register */
8496                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8497                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8498                         conf->flow_type)));
8499         } else
8500                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8501
8502         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8503                                    conf->inset_size);
8504         if (ret) {
8505                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8506                 return -EINVAL;
8507         }
8508         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8509                                     input_set) != 0) {
8510                 PMD_DRV_LOG(ERR, "Invalid input set");
8511                 return -EINVAL;
8512         }
8513         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8514                 /* get inset value in register */
8515                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8516                 inset_reg <<= I40E_32_BIT_WIDTH;
8517                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8518                 input_set |= pf->hash_input_set[pctype];
8519         }
8520         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8521                                            I40E_INSET_MASK_NUM_REG);
8522         if (num < 0)
8523                 return -EINVAL;
8524
8525         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8526
8527         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8528                               (uint32_t)(inset_reg & UINT32_MAX));
8529         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8530                              (uint32_t)((inset_reg >>
8531                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8532
8533         for (i = 0; i < num; i++)
8534                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8535                                      mask_reg[i]);
8536         /*clear unused mask registers of the pctype */
8537         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8538                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8539                                      0);
8540         I40E_WRITE_FLUSH(hw);
8541
8542         pf->hash_input_set[pctype] = input_set;
8543         return 0;
8544 }
8545
8546 int
8547 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8548                          struct rte_eth_input_set_conf *conf)
8549 {
8550         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8551         enum i40e_filter_pctype pctype;
8552         uint64_t input_set, inset_reg = 0;
8553         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8554         int ret, i, num;
8555
8556         if (!hw || !conf) {
8557                 PMD_DRV_LOG(ERR, "Invalid pointer");
8558                 return -EFAULT;
8559         }
8560         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8561             conf->op != RTE_ETH_INPUT_SET_ADD) {
8562                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8563                 return -EINVAL;
8564         }
8565
8566         if (!I40E_VALID_FLOW(conf->flow_type)) {
8567                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8568                 return -EINVAL;
8569         }
8570
8571         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8572
8573         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8574                                    conf->inset_size);
8575         if (ret) {
8576                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8577                 return -EINVAL;
8578         }
8579         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8580                                     input_set) != 0) {
8581                 PMD_DRV_LOG(ERR, "Invalid input set");
8582                 return -EINVAL;
8583         }
8584
8585         /* get inset value in register */
8586         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8587         inset_reg <<= I40E_32_BIT_WIDTH;
8588         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8589
8590         /* Can not change the inset reg for flex payload for fdir,
8591          * it is done by writing I40E_PRTQF_FD_FLXINSET
8592          * in i40e_set_flex_mask_on_pctype.
8593          */
8594         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8595                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8596         else
8597                 input_set |= pf->fdir.input_set[pctype];
8598         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8599                                            I40E_INSET_MASK_NUM_REG);
8600         if (num < 0)
8601                 return -EINVAL;
8602
8603         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8604
8605         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8606                               (uint32_t)(inset_reg & UINT32_MAX));
8607         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8608                              (uint32_t)((inset_reg >>
8609                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8610
8611         for (i = 0; i < num; i++)
8612                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8613                                      mask_reg[i]);
8614         /*clear unused mask registers of the pctype */
8615         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8616                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8617                                      0);
8618         I40E_WRITE_FLUSH(hw);
8619
8620         pf->fdir.input_set[pctype] = input_set;
8621         return 0;
8622 }
8623
8624 static int
8625 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8626 {
8627         int ret = 0;
8628
8629         if (!hw || !info) {
8630                 PMD_DRV_LOG(ERR, "Invalid pointer");
8631                 return -EFAULT;
8632         }
8633
8634         switch (info->info_type) {
8635         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8636                 i40e_get_symmetric_hash_enable_per_port(hw,
8637                                         &(info->info.enable));
8638                 break;
8639         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8640                 ret = i40e_get_hash_filter_global_config(hw,
8641                                 &(info->info.global_conf));
8642                 break;
8643         default:
8644                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8645                                                         info->info_type);
8646                 ret = -EINVAL;
8647                 break;
8648         }
8649
8650         return ret;
8651 }
8652
8653 static int
8654 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8655 {
8656         int ret = 0;
8657
8658         if (!hw || !info) {
8659                 PMD_DRV_LOG(ERR, "Invalid pointer");
8660                 return -EFAULT;
8661         }
8662
8663         switch (info->info_type) {
8664         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8665                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8666                 break;
8667         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8668                 ret = i40e_set_hash_filter_global_config(hw,
8669                                 &(info->info.global_conf));
8670                 break;
8671         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8672                 ret = i40e_hash_filter_inset_select(hw,
8673                                                &(info->info.input_set_conf));
8674                 break;
8675
8676         default:
8677                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8678                                                         info->info_type);
8679                 ret = -EINVAL;
8680                 break;
8681         }
8682
8683         return ret;
8684 }
8685
8686 /* Operations for hash function */
8687 static int
8688 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8689                       enum rte_filter_op filter_op,
8690                       void *arg)
8691 {
8692         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8693         int ret = 0;
8694
8695         switch (filter_op) {
8696         case RTE_ETH_FILTER_NOP:
8697                 break;
8698         case RTE_ETH_FILTER_GET:
8699                 ret = i40e_hash_filter_get(hw,
8700                         (struct rte_eth_hash_filter_info *)arg);
8701                 break;
8702         case RTE_ETH_FILTER_SET:
8703                 ret = i40e_hash_filter_set(hw,
8704                         (struct rte_eth_hash_filter_info *)arg);
8705                 break;
8706         default:
8707                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8708                                                                 filter_op);
8709                 ret = -ENOTSUP;
8710                 break;
8711         }
8712
8713         return ret;
8714 }
8715
8716 /* Convert ethertype filter structure */
8717 static int
8718 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8719                               struct i40e_ethertype_filter *filter)
8720 {
8721         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8722         filter->input.ether_type = input->ether_type;
8723         filter->flags = input->flags;
8724         filter->queue = input->queue;
8725
8726         return 0;
8727 }
8728
8729 /* Check if there exists the ehtertype filter */
8730 struct i40e_ethertype_filter *
8731 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8732                                 const struct i40e_ethertype_filter_input *input)
8733 {
8734         int ret;
8735
8736         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8737         if (ret < 0)
8738                 return NULL;
8739
8740         return ethertype_rule->hash_map[ret];
8741 }
8742
8743 /* Add ethertype filter in SW list */
8744 static int
8745 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8746                                 struct i40e_ethertype_filter *filter)
8747 {
8748         struct i40e_ethertype_rule *rule = &pf->ethertype;
8749         int ret;
8750
8751         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8752         if (ret < 0) {
8753                 PMD_DRV_LOG(ERR,
8754                             "Failed to insert ethertype filter"
8755                             " to hash table %d!",
8756                             ret);
8757                 return ret;
8758         }
8759         rule->hash_map[ret] = filter;
8760
8761         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8762
8763         return 0;
8764 }
8765
8766 /* Delete ethertype filter in SW list */
8767 int
8768 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8769                              struct i40e_ethertype_filter_input *input)
8770 {
8771         struct i40e_ethertype_rule *rule = &pf->ethertype;
8772         struct i40e_ethertype_filter *filter;
8773         int ret;
8774
8775         ret = rte_hash_del_key(rule->hash_table, input);
8776         if (ret < 0) {
8777                 PMD_DRV_LOG(ERR,
8778                             "Failed to delete ethertype filter"
8779                             " to hash table %d!",
8780                             ret);
8781                 return ret;
8782         }
8783         filter = rule->hash_map[ret];
8784         rule->hash_map[ret] = NULL;
8785
8786         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8787         rte_free(filter);
8788
8789         return 0;
8790 }
8791
8792 /*
8793  * Configure ethertype filter, which can director packet by filtering
8794  * with mac address and ether_type or only ether_type
8795  */
8796 int
8797 i40e_ethertype_filter_set(struct i40e_pf *pf,
8798                         struct rte_eth_ethertype_filter *filter,
8799                         bool add)
8800 {
8801         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8802         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8803         struct i40e_ethertype_filter *ethertype_filter, *node;
8804         struct i40e_ethertype_filter check_filter;
8805         struct i40e_control_filter_stats stats;
8806         uint16_t flags = 0;
8807         int ret;
8808
8809         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8810                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8811                 return -EINVAL;
8812         }
8813         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8814                 filter->ether_type == ETHER_TYPE_IPv6) {
8815                 PMD_DRV_LOG(ERR,
8816                         "unsupported ether_type(0x%04x) in control packet filter.",
8817                         filter->ether_type);
8818                 return -EINVAL;
8819         }
8820         if (filter->ether_type == ETHER_TYPE_VLAN)
8821                 PMD_DRV_LOG(WARNING,
8822                         "filter vlan ether_type in first tag is not supported.");
8823
8824         /* Check if there is the filter in SW list */
8825         memset(&check_filter, 0, sizeof(check_filter));
8826         i40e_ethertype_filter_convert(filter, &check_filter);
8827         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8828                                                &check_filter.input);
8829         if (add && node) {
8830                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8831                 return -EINVAL;
8832         }
8833
8834         if (!add && !node) {
8835                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8836                 return -EINVAL;
8837         }
8838
8839         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8840                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8841         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8842                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8843         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8844
8845         memset(&stats, 0, sizeof(stats));
8846         ret = i40e_aq_add_rem_control_packet_filter(hw,
8847                         filter->mac_addr.addr_bytes,
8848                         filter->ether_type, flags,
8849                         pf->main_vsi->seid,
8850                         filter->queue, add, &stats, NULL);
8851
8852         PMD_DRV_LOG(INFO,
8853                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8854                 ret, stats.mac_etype_used, stats.etype_used,
8855                 stats.mac_etype_free, stats.etype_free);
8856         if (ret < 0)
8857                 return -ENOSYS;
8858
8859         /* Add or delete a filter in SW list */
8860         if (add) {
8861                 ethertype_filter = rte_zmalloc("ethertype_filter",
8862                                        sizeof(*ethertype_filter), 0);
8863                 rte_memcpy(ethertype_filter, &check_filter,
8864                            sizeof(check_filter));
8865                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8866         } else {
8867                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8868         }
8869
8870         return ret;
8871 }
8872
8873 /*
8874  * Handle operations for ethertype filter.
8875  */
8876 static int
8877 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8878                                 enum rte_filter_op filter_op,
8879                                 void *arg)
8880 {
8881         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8882         int ret = 0;
8883
8884         if (filter_op == RTE_ETH_FILTER_NOP)
8885                 return ret;
8886
8887         if (arg == NULL) {
8888                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8889                             filter_op);
8890                 return -EINVAL;
8891         }
8892
8893         switch (filter_op) {
8894         case RTE_ETH_FILTER_ADD:
8895                 ret = i40e_ethertype_filter_set(pf,
8896                         (struct rte_eth_ethertype_filter *)arg,
8897                         TRUE);
8898                 break;
8899         case RTE_ETH_FILTER_DELETE:
8900                 ret = i40e_ethertype_filter_set(pf,
8901                         (struct rte_eth_ethertype_filter *)arg,
8902                         FALSE);
8903                 break;
8904         default:
8905                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8906                 ret = -ENOSYS;
8907                 break;
8908         }
8909         return ret;
8910 }
8911
8912 static int
8913 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8914                      enum rte_filter_type filter_type,
8915                      enum rte_filter_op filter_op,
8916                      void *arg)
8917 {
8918         int ret = 0;
8919
8920         if (dev == NULL)
8921                 return -EINVAL;
8922
8923         switch (filter_type) {
8924         case RTE_ETH_FILTER_NONE:
8925                 /* For global configuration */
8926                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8927                 break;
8928         case RTE_ETH_FILTER_HASH:
8929                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8930                 break;
8931         case RTE_ETH_FILTER_MACVLAN:
8932                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8933                 break;
8934         case RTE_ETH_FILTER_ETHERTYPE:
8935                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8936                 break;
8937         case RTE_ETH_FILTER_TUNNEL:
8938                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8939                 break;
8940         case RTE_ETH_FILTER_FDIR:
8941                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8942                 break;
8943         case RTE_ETH_FILTER_GENERIC:
8944                 if (filter_op != RTE_ETH_FILTER_GET)
8945                         return -EINVAL;
8946                 *(const void **)arg = &i40e_flow_ops;
8947                 break;
8948         default:
8949                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8950                                                         filter_type);
8951                 ret = -EINVAL;
8952                 break;
8953         }
8954
8955         return ret;
8956 }
8957
8958 /*
8959  * Check and enable Extended Tag.
8960  * Enabling Extended Tag is important for 40G performance.
8961  */
8962 static void
8963 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8964 {
8965         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8966         uint32_t buf = 0;
8967         int ret;
8968
8969         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8970                                       PCI_DEV_CAP_REG);
8971         if (ret < 0) {
8972                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8973                             PCI_DEV_CAP_REG);
8974                 return;
8975         }
8976         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8977                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8978                 return;
8979         }
8980
8981         buf = 0;
8982         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8983                                       PCI_DEV_CTRL_REG);
8984         if (ret < 0) {
8985                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8986                             PCI_DEV_CTRL_REG);
8987                 return;
8988         }
8989         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8990                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8991                 return;
8992         }
8993         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8994         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8995                                        PCI_DEV_CTRL_REG);
8996         if (ret < 0) {
8997                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8998                             PCI_DEV_CTRL_REG);
8999                 return;
9000         }
9001 }
9002
9003 /*
9004  * As some registers wouldn't be reset unless a global hardware reset,
9005  * hardware initialization is needed to put those registers into an
9006  * expected initial state.
9007  */
9008 static void
9009 i40e_hw_init(struct rte_eth_dev *dev)
9010 {
9011         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9012
9013         i40e_enable_extended_tag(dev);
9014
9015         /* clear the PF Queue Filter control register */
9016         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9017
9018         /* Disable symmetric hash per port */
9019         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9020 }
9021
9022 enum i40e_filter_pctype
9023 i40e_flowtype_to_pctype(uint16_t flow_type)
9024 {
9025         static const enum i40e_filter_pctype pctype_table[] = {
9026                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9027                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9028                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9029                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9030                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9031                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9032                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9033                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9034                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9035                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9036                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9037                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9038                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9039                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9040                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9041                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9042                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9043                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9044                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9045         };
9046
9047         return pctype_table[flow_type];
9048 }
9049
9050 uint16_t
9051 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9052 {
9053         static const uint16_t flowtype_table[] = {
9054                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9055                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9056                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9057                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9058                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9059                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9060                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9061                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9062                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9063                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9064                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9065                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9066                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9067                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9068                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9069                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9070                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9071                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9072                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9073                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9074                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9075                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9076                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9077                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9078                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9079                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9080                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9081                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9082                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9083                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9084                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9085         };
9086
9087         return flowtype_table[pctype];
9088 }
9089
9090 /*
9091  * On X710, performance number is far from the expectation on recent firmware
9092  * versions; on XL710, performance number is also far from the expectation on
9093  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9094  * mode is enabled and port MAC address is equal to the packet destination MAC
9095  * address. The fix for this issue may not be integrated in the following
9096  * firmware version. So the workaround in software driver is needed. It needs
9097  * to modify the initial values of 3 internal only registers for both X710 and
9098  * XL710. Note that the values for X710 or XL710 could be different, and the
9099  * workaround can be removed when it is fixed in firmware in the future.
9100  */
9101
9102 /* For both X710 and XL710 */
9103 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9104 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
9105
9106 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9107 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9108
9109 /* For X722 */
9110 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9111 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9112
9113 /* For X710 */
9114 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9115 /* For XL710 */
9116 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9117 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9118
9119 static int
9120 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9121 {
9122         enum i40e_status_code status;
9123         struct i40e_aq_get_phy_abilities_resp phy_ab;
9124         int ret = -ENOTSUP;
9125
9126         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9127                                               NULL);
9128
9129         if (status)
9130                 return ret;
9131
9132         return 0;
9133 }
9134
9135 static void
9136 i40e_configure_registers(struct i40e_hw *hw)
9137 {
9138         static struct {
9139                 uint32_t addr;
9140                 uint64_t val;
9141         } reg_table[] = {
9142                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9143                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9144                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9145         };
9146         uint64_t reg;
9147         uint32_t i;
9148         int ret;
9149
9150         for (i = 0; i < RTE_DIM(reg_table); i++) {
9151                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9152                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9153                                 reg_table[i].val =
9154                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9155                         else /* For X710/XL710/XXV710 */
9156                                 reg_table[i].val =
9157                                         I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9158                 }
9159
9160                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9161                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9162                                 reg_table[i].val =
9163                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9164                         else /* For X710/XL710/XXV710 */
9165                                 reg_table[i].val =
9166                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9167                 }
9168
9169                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9170                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9171                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9172                                 reg_table[i].val =
9173                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9174                         else /* For X710 */
9175                                 reg_table[i].val =
9176                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9177                 }
9178
9179                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9180                                                         &reg, NULL);
9181                 if (ret < 0) {
9182                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9183                                                         reg_table[i].addr);
9184                         break;
9185                 }
9186                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9187                                                 reg_table[i].addr, reg);
9188                 if (reg == reg_table[i].val)
9189                         continue;
9190
9191                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9192                                                 reg_table[i].val, NULL);
9193                 if (ret < 0) {
9194                         PMD_DRV_LOG(ERR,
9195                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9196                                 reg_table[i].val, reg_table[i].addr);
9197                         break;
9198                 }
9199                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9200                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9201         }
9202 }
9203
9204 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9205 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9206 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9207 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9208 static int
9209 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9210 {
9211         uint32_t reg;
9212         int ret;
9213
9214         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9215                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9216                 return -EINVAL;
9217         }
9218
9219         /* Configure for double VLAN RX stripping */
9220         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9221         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9222                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9223                 ret = i40e_aq_debug_write_register(hw,
9224                                                    I40E_VSI_TSR(vsi->vsi_id),
9225                                                    reg, NULL);
9226                 if (ret < 0) {
9227                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9228                                     vsi->vsi_id);
9229                         return I40E_ERR_CONFIG;
9230                 }
9231         }
9232
9233         /* Configure for double VLAN TX insertion */
9234         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9235         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9236                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9237                 ret = i40e_aq_debug_write_register(hw,
9238                                                    I40E_VSI_L2TAGSTXVALID(
9239                                                    vsi->vsi_id), reg, NULL);
9240                 if (ret < 0) {
9241                         PMD_DRV_LOG(ERR,
9242                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9243                                 vsi->vsi_id);
9244                         return I40E_ERR_CONFIG;
9245                 }
9246         }
9247
9248         return 0;
9249 }
9250
9251 /**
9252  * i40e_aq_add_mirror_rule
9253  * @hw: pointer to the hardware structure
9254  * @seid: VEB seid to add mirror rule to
9255  * @dst_id: destination vsi seid
9256  * @entries: Buffer which contains the entities to be mirrored
9257  * @count: number of entities contained in the buffer
9258  * @rule_id:the rule_id of the rule to be added
9259  *
9260  * Add a mirror rule for a given veb.
9261  *
9262  **/
9263 static enum i40e_status_code
9264 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9265                         uint16_t seid, uint16_t dst_id,
9266                         uint16_t rule_type, uint16_t *entries,
9267                         uint16_t count, uint16_t *rule_id)
9268 {
9269         struct i40e_aq_desc desc;
9270         struct i40e_aqc_add_delete_mirror_rule cmd;
9271         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9272                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9273                 &desc.params.raw;
9274         uint16_t buff_len;
9275         enum i40e_status_code status;
9276
9277         i40e_fill_default_direct_cmd_desc(&desc,
9278                                           i40e_aqc_opc_add_mirror_rule);
9279         memset(&cmd, 0, sizeof(cmd));
9280
9281         buff_len = sizeof(uint16_t) * count;
9282         desc.datalen = rte_cpu_to_le_16(buff_len);
9283         if (buff_len > 0)
9284                 desc.flags |= rte_cpu_to_le_16(
9285                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9286         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9287                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9288         cmd.num_entries = rte_cpu_to_le_16(count);
9289         cmd.seid = rte_cpu_to_le_16(seid);
9290         cmd.destination = rte_cpu_to_le_16(dst_id);
9291
9292         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9293         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9294         PMD_DRV_LOG(INFO,
9295                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9296                 hw->aq.asq_last_status, resp->rule_id,
9297                 resp->mirror_rules_used, resp->mirror_rules_free);
9298         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9299
9300         return status;
9301 }
9302
9303 /**
9304  * i40e_aq_del_mirror_rule
9305  * @hw: pointer to the hardware structure
9306  * @seid: VEB seid to add mirror rule to
9307  * @entries: Buffer which contains the entities to be mirrored
9308  * @count: number of entities contained in the buffer
9309  * @rule_id:the rule_id of the rule to be delete
9310  *
9311  * Delete a mirror rule for a given veb.
9312  *
9313  **/
9314 static enum i40e_status_code
9315 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9316                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9317                 uint16_t count, uint16_t rule_id)
9318 {
9319         struct i40e_aq_desc desc;
9320         struct i40e_aqc_add_delete_mirror_rule cmd;
9321         uint16_t buff_len = 0;
9322         enum i40e_status_code status;
9323         void *buff = NULL;
9324
9325         i40e_fill_default_direct_cmd_desc(&desc,
9326                                           i40e_aqc_opc_delete_mirror_rule);
9327         memset(&cmd, 0, sizeof(cmd));
9328         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9329                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9330                                                           I40E_AQ_FLAG_RD));
9331                 cmd.num_entries = count;
9332                 buff_len = sizeof(uint16_t) * count;
9333                 desc.datalen = rte_cpu_to_le_16(buff_len);
9334                 buff = (void *)entries;
9335         } else
9336                 /* rule id is filled in destination field for deleting mirror rule */
9337                 cmd.destination = rte_cpu_to_le_16(rule_id);
9338
9339         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9340                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9341         cmd.seid = rte_cpu_to_le_16(seid);
9342
9343         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9344         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9345
9346         return status;
9347 }
9348
9349 /**
9350  * i40e_mirror_rule_set
9351  * @dev: pointer to the hardware structure
9352  * @mirror_conf: mirror rule info
9353  * @sw_id: mirror rule's sw_id
9354  * @on: enable/disable
9355  *
9356  * set a mirror rule.
9357  *
9358  **/
9359 static int
9360 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9361                         struct rte_eth_mirror_conf *mirror_conf,
9362                         uint8_t sw_id, uint8_t on)
9363 {
9364         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9365         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9366         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9367         struct i40e_mirror_rule *parent = NULL;
9368         uint16_t seid, dst_seid, rule_id;
9369         uint16_t i, j = 0;
9370         int ret;
9371
9372         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9373
9374         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9375                 PMD_DRV_LOG(ERR,
9376                         "mirror rule can not be configured without veb or vfs.");
9377                 return -ENOSYS;
9378         }
9379         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9380                 PMD_DRV_LOG(ERR, "mirror table is full.");
9381                 return -ENOSPC;
9382         }
9383         if (mirror_conf->dst_pool > pf->vf_num) {
9384                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9385                                  mirror_conf->dst_pool);
9386                 return -EINVAL;
9387         }
9388
9389         seid = pf->main_vsi->veb->seid;
9390
9391         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9392                 if (sw_id <= it->index) {
9393                         mirr_rule = it;
9394                         break;
9395                 }
9396                 parent = it;
9397         }
9398         if (mirr_rule && sw_id == mirr_rule->index) {
9399                 if (on) {
9400                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9401                         return -EEXIST;
9402                 } else {
9403                         ret = i40e_aq_del_mirror_rule(hw, seid,
9404                                         mirr_rule->rule_type,
9405                                         mirr_rule->entries,
9406                                         mirr_rule->num_entries, mirr_rule->id);
9407                         if (ret < 0) {
9408                                 PMD_DRV_LOG(ERR,
9409                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9410                                         ret, hw->aq.asq_last_status);
9411                                 return -ENOSYS;
9412                         }
9413                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9414                         rte_free(mirr_rule);
9415                         pf->nb_mirror_rule--;
9416                         return 0;
9417                 }
9418         } else if (!on) {
9419                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9420                 return -ENOENT;
9421         }
9422
9423         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9424                                 sizeof(struct i40e_mirror_rule) , 0);
9425         if (!mirr_rule) {
9426                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9427                 return I40E_ERR_NO_MEMORY;
9428         }
9429         switch (mirror_conf->rule_type) {
9430         case ETH_MIRROR_VLAN:
9431                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9432                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9433                                 mirr_rule->entries[j] =
9434                                         mirror_conf->vlan.vlan_id[i];
9435                                 j++;
9436                         }
9437                 }
9438                 if (j == 0) {
9439                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9440                         rte_free(mirr_rule);
9441                         return -EINVAL;
9442                 }
9443                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9444                 break;
9445         case ETH_MIRROR_VIRTUAL_POOL_UP:
9446         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9447                 /* check if the specified pool bit is out of range */
9448                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9449                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9450                         rte_free(mirr_rule);
9451                         return -EINVAL;
9452                 }
9453                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9454                         if (mirror_conf->pool_mask & (1ULL << i)) {
9455                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9456                                 j++;
9457                         }
9458                 }
9459                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9460                         /* add pf vsi to entries */
9461                         mirr_rule->entries[j] = pf->main_vsi_seid;
9462                         j++;
9463                 }
9464                 if (j == 0) {
9465                         PMD_DRV_LOG(ERR, "pool is not specified.");
9466                         rte_free(mirr_rule);
9467                         return -EINVAL;
9468                 }
9469                 /* egress and ingress in aq commands means from switch but not port */
9470                 mirr_rule->rule_type =
9471                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9472                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9473                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9474                 break;
9475         case ETH_MIRROR_UPLINK_PORT:
9476                 /* egress and ingress in aq commands means from switch but not port*/
9477                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9478                 break;
9479         case ETH_MIRROR_DOWNLINK_PORT:
9480                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9481                 break;
9482         default:
9483                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9484                         mirror_conf->rule_type);
9485                 rte_free(mirr_rule);
9486                 return -EINVAL;
9487         }
9488
9489         /* If the dst_pool is equal to vf_num, consider it as PF */
9490         if (mirror_conf->dst_pool == pf->vf_num)
9491                 dst_seid = pf->main_vsi_seid;
9492         else
9493                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9494
9495         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9496                                       mirr_rule->rule_type, mirr_rule->entries,
9497                                       j, &rule_id);
9498         if (ret < 0) {
9499                 PMD_DRV_LOG(ERR,
9500                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9501                         ret, hw->aq.asq_last_status);
9502                 rte_free(mirr_rule);
9503                 return -ENOSYS;
9504         }
9505
9506         mirr_rule->index = sw_id;
9507         mirr_rule->num_entries = j;
9508         mirr_rule->id = rule_id;
9509         mirr_rule->dst_vsi_seid = dst_seid;
9510
9511         if (parent)
9512                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9513         else
9514                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9515
9516         pf->nb_mirror_rule++;
9517         return 0;
9518 }
9519
9520 /**
9521  * i40e_mirror_rule_reset
9522  * @dev: pointer to the device
9523  * @sw_id: mirror rule's sw_id
9524  *
9525  * reset a mirror rule.
9526  *
9527  **/
9528 static int
9529 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9530 {
9531         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9532         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9533         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9534         uint16_t seid;
9535         int ret;
9536
9537         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9538
9539         seid = pf->main_vsi->veb->seid;
9540
9541         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9542                 if (sw_id == it->index) {
9543                         mirr_rule = it;
9544                         break;
9545                 }
9546         }
9547         if (mirr_rule) {
9548                 ret = i40e_aq_del_mirror_rule(hw, seid,
9549                                 mirr_rule->rule_type,
9550                                 mirr_rule->entries,
9551                                 mirr_rule->num_entries, mirr_rule->id);
9552                 if (ret < 0) {
9553                         PMD_DRV_LOG(ERR,
9554                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9555                                 ret, hw->aq.asq_last_status);
9556                         return -ENOSYS;
9557                 }
9558                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9559                 rte_free(mirr_rule);
9560                 pf->nb_mirror_rule--;
9561         } else {
9562                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9563                 return -ENOENT;
9564         }
9565         return 0;
9566 }
9567
9568 static uint64_t
9569 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9570 {
9571         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9572         uint64_t systim_cycles;
9573
9574         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9575         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9576                         << 32;
9577
9578         return systim_cycles;
9579 }
9580
9581 static uint64_t
9582 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9583 {
9584         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9585         uint64_t rx_tstamp;
9586
9587         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9588         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9589                         << 32;
9590
9591         return rx_tstamp;
9592 }
9593
9594 static uint64_t
9595 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9596 {
9597         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9598         uint64_t tx_tstamp;
9599
9600         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9601         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9602                         << 32;
9603
9604         return tx_tstamp;
9605 }
9606
9607 static void
9608 i40e_start_timecounters(struct rte_eth_dev *dev)
9609 {
9610         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9611         struct i40e_adapter *adapter =
9612                         (struct i40e_adapter *)dev->data->dev_private;
9613         struct rte_eth_link link;
9614         uint32_t tsync_inc_l;
9615         uint32_t tsync_inc_h;
9616
9617         /* Get current link speed. */
9618         memset(&link, 0, sizeof(link));
9619         i40e_dev_link_update(dev, 1);
9620         rte_i40e_dev_atomic_read_link_status(dev, &link);
9621
9622         switch (link.link_speed) {
9623         case ETH_SPEED_NUM_40G:
9624                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9625                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9626                 break;
9627         case ETH_SPEED_NUM_10G:
9628                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9629                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9630                 break;
9631         case ETH_SPEED_NUM_1G:
9632                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9633                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9634                 break;
9635         default:
9636                 tsync_inc_l = 0x0;
9637                 tsync_inc_h = 0x0;
9638         }
9639
9640         /* Set the timesync increment value. */
9641         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9642         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9643
9644         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9645         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9646         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9647
9648         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9649         adapter->systime_tc.cc_shift = 0;
9650         adapter->systime_tc.nsec_mask = 0;
9651
9652         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9653         adapter->rx_tstamp_tc.cc_shift = 0;
9654         adapter->rx_tstamp_tc.nsec_mask = 0;
9655
9656         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9657         adapter->tx_tstamp_tc.cc_shift = 0;
9658         adapter->tx_tstamp_tc.nsec_mask = 0;
9659 }
9660
9661 static int
9662 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9663 {
9664         struct i40e_adapter *adapter =
9665                         (struct i40e_adapter *)dev->data->dev_private;
9666
9667         adapter->systime_tc.nsec += delta;
9668         adapter->rx_tstamp_tc.nsec += delta;
9669         adapter->tx_tstamp_tc.nsec += delta;
9670
9671         return 0;
9672 }
9673
9674 static int
9675 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9676 {
9677         uint64_t ns;
9678         struct i40e_adapter *adapter =
9679                         (struct i40e_adapter *)dev->data->dev_private;
9680
9681         ns = rte_timespec_to_ns(ts);
9682
9683         /* Set the timecounters to a new value. */
9684         adapter->systime_tc.nsec = ns;
9685         adapter->rx_tstamp_tc.nsec = ns;
9686         adapter->tx_tstamp_tc.nsec = ns;
9687
9688         return 0;
9689 }
9690
9691 static int
9692 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9693 {
9694         uint64_t ns, systime_cycles;
9695         struct i40e_adapter *adapter =
9696                         (struct i40e_adapter *)dev->data->dev_private;
9697
9698         systime_cycles = i40e_read_systime_cyclecounter(dev);
9699         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9700         *ts = rte_ns_to_timespec(ns);
9701
9702         return 0;
9703 }
9704
9705 static int
9706 i40e_timesync_enable(struct rte_eth_dev *dev)
9707 {
9708         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9709         uint32_t tsync_ctl_l;
9710         uint32_t tsync_ctl_h;
9711
9712         /* Stop the timesync system time. */
9713         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9714         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9715         /* Reset the timesync system time value. */
9716         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9717         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9718
9719         i40e_start_timecounters(dev);
9720
9721         /* Clear timesync registers. */
9722         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9723         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9724         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9725         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9726         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9727         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9728
9729         /* Enable timestamping of PTP packets. */
9730         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9731         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9732
9733         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9734         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9735         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9736
9737         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9738         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9739
9740         return 0;
9741 }
9742
9743 static int
9744 i40e_timesync_disable(struct rte_eth_dev *dev)
9745 {
9746         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9747         uint32_t tsync_ctl_l;
9748         uint32_t tsync_ctl_h;
9749
9750         /* Disable timestamping of transmitted PTP packets. */
9751         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9752         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9753
9754         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9755         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9756
9757         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9758         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9759
9760         /* Reset the timesync increment value. */
9761         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9762         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9763
9764         return 0;
9765 }
9766
9767 static int
9768 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9769                                 struct timespec *timestamp, uint32_t flags)
9770 {
9771         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9772         struct i40e_adapter *adapter =
9773                 (struct i40e_adapter *)dev->data->dev_private;
9774
9775         uint32_t sync_status;
9776         uint32_t index = flags & 0x03;
9777         uint64_t rx_tstamp_cycles;
9778         uint64_t ns;
9779
9780         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9781         if ((sync_status & (1 << index)) == 0)
9782                 return -EINVAL;
9783
9784         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9785         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9786         *timestamp = rte_ns_to_timespec(ns);
9787
9788         return 0;
9789 }
9790
9791 static int
9792 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9793                                 struct timespec *timestamp)
9794 {
9795         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9796         struct i40e_adapter *adapter =
9797                 (struct i40e_adapter *)dev->data->dev_private;
9798
9799         uint32_t sync_status;
9800         uint64_t tx_tstamp_cycles;
9801         uint64_t ns;
9802
9803         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9804         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9805                 return -EINVAL;
9806
9807         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9808         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9809         *timestamp = rte_ns_to_timespec(ns);
9810
9811         return 0;
9812 }
9813
9814 /*
9815  * i40e_parse_dcb_configure - parse dcb configure from user
9816  * @dev: the device being configured
9817  * @dcb_cfg: pointer of the result of parse
9818  * @*tc_map: bit map of enabled traffic classes
9819  *
9820  * Returns 0 on success, negative value on failure
9821  */
9822 static int
9823 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9824                          struct i40e_dcbx_config *dcb_cfg,
9825                          uint8_t *tc_map)
9826 {
9827         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9828         uint8_t i, tc_bw, bw_lf;
9829
9830         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9831
9832         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9833         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9834                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9835                 return -EINVAL;
9836         }
9837
9838         /* assume each tc has the same bw */
9839         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9840         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9841                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9842         /* to ensure the sum of tcbw is equal to 100 */
9843         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9844         for (i = 0; i < bw_lf; i++)
9845                 dcb_cfg->etscfg.tcbwtable[i]++;
9846
9847         /* assume each tc has the same Transmission Selection Algorithm */
9848         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9849                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9850
9851         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9852                 dcb_cfg->etscfg.prioritytable[i] =
9853                                 dcb_rx_conf->dcb_tc[i];
9854
9855         /* FW needs one App to configure HW */
9856         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9857         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9858         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9859         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9860
9861         if (dcb_rx_conf->nb_tcs == 0)
9862                 *tc_map = 1; /* tc0 only */
9863         else
9864                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9865
9866         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9867                 dcb_cfg->pfc.willing = 0;
9868                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9869                 dcb_cfg->pfc.pfcenable = *tc_map;
9870         }
9871         return 0;
9872 }
9873
9874
9875 static enum i40e_status_code
9876 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9877                               struct i40e_aqc_vsi_properties_data *info,
9878                               uint8_t enabled_tcmap)
9879 {
9880         enum i40e_status_code ret;
9881         int i, total_tc = 0;
9882         uint16_t qpnum_per_tc, bsf, qp_idx;
9883         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9884         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9885         uint16_t used_queues;
9886
9887         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9888         if (ret != I40E_SUCCESS)
9889                 return ret;
9890
9891         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9892                 if (enabled_tcmap & (1 << i))
9893                         total_tc++;
9894         }
9895         if (total_tc == 0)
9896                 total_tc = 1;
9897         vsi->enabled_tc = enabled_tcmap;
9898
9899         /* different VSI has different queues assigned */
9900         if (vsi->type == I40E_VSI_MAIN)
9901                 used_queues = dev_data->nb_rx_queues -
9902                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9903         else if (vsi->type == I40E_VSI_VMDQ2)
9904                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9905         else {
9906                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9907                 return I40E_ERR_NO_AVAILABLE_VSI;
9908         }
9909
9910         qpnum_per_tc = used_queues / total_tc;
9911         /* Number of queues per enabled TC */
9912         if (qpnum_per_tc == 0) {
9913                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9914                 return I40E_ERR_INVALID_QP_ID;
9915         }
9916         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9917                                 I40E_MAX_Q_PER_TC);
9918         bsf = rte_bsf32(qpnum_per_tc);
9919
9920         /**
9921          * Configure TC and queue mapping parameters, for enabled TC,
9922          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9923          * default queue will serve it.
9924          */
9925         qp_idx = 0;
9926         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9927                 if (vsi->enabled_tc & (1 << i)) {
9928                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9929                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9930                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9931                         qp_idx += qpnum_per_tc;
9932                 } else
9933                         info->tc_mapping[i] = 0;
9934         }
9935
9936         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9937         if (vsi->type == I40E_VSI_SRIOV) {
9938                 info->mapping_flags |=
9939                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9940                 for (i = 0; i < vsi->nb_qps; i++)
9941                         info->queue_mapping[i] =
9942                                 rte_cpu_to_le_16(vsi->base_queue + i);
9943         } else {
9944                 info->mapping_flags |=
9945                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9946                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9947         }
9948         info->valid_sections |=
9949                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9950
9951         return I40E_SUCCESS;
9952 }
9953
9954 /*
9955  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9956  * @veb: VEB to be configured
9957  * @tc_map: enabled TC bitmap
9958  *
9959  * Returns 0 on success, negative value on failure
9960  */
9961 static enum i40e_status_code
9962 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9963 {
9964         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9965         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9966         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9967         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9968         enum i40e_status_code ret = I40E_SUCCESS;
9969         int i;
9970         uint32_t bw_max;
9971
9972         /* Check if enabled_tc is same as existing or new TCs */
9973         if (veb->enabled_tc == tc_map)
9974                 return ret;
9975
9976         /* configure tc bandwidth */
9977         memset(&veb_bw, 0, sizeof(veb_bw));
9978         veb_bw.tc_valid_bits = tc_map;
9979         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9980         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9981                 if (tc_map & BIT_ULL(i))
9982                         veb_bw.tc_bw_share_credits[i] = 1;
9983         }
9984         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9985                                                    &veb_bw, NULL);
9986         if (ret) {
9987                 PMD_INIT_LOG(ERR,
9988                         "AQ command Config switch_comp BW allocation per TC failed = %d",
9989                         hw->aq.asq_last_status);
9990                 return ret;
9991         }
9992
9993         memset(&ets_query, 0, sizeof(ets_query));
9994         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9995                                                    &ets_query, NULL);
9996         if (ret != I40E_SUCCESS) {
9997                 PMD_DRV_LOG(ERR,
9998                         "Failed to get switch_comp ETS configuration %u",
9999                         hw->aq.asq_last_status);
10000                 return ret;
10001         }
10002         memset(&bw_query, 0, sizeof(bw_query));
10003         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10004                                                   &bw_query, NULL);
10005         if (ret != I40E_SUCCESS) {
10006                 PMD_DRV_LOG(ERR,
10007                         "Failed to get switch_comp bandwidth configuration %u",
10008                         hw->aq.asq_last_status);
10009                 return ret;
10010         }
10011
10012         /* store and print out BW info */
10013         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10014         veb->bw_info.bw_max = ets_query.tc_bw_max;
10015         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10016         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10017         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10018                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10019                      I40E_16_BIT_WIDTH);
10020         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10021                 veb->bw_info.bw_ets_share_credits[i] =
10022                                 bw_query.tc_bw_share_credits[i];
10023                 veb->bw_info.bw_ets_credits[i] =
10024                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10025                 /* 4 bits per TC, 4th bit is reserved */
10026                 veb->bw_info.bw_ets_max[i] =
10027                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10028                                   RTE_LEN2MASK(3, uint8_t));
10029                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10030                             veb->bw_info.bw_ets_share_credits[i]);
10031                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10032                             veb->bw_info.bw_ets_credits[i]);
10033                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10034                             veb->bw_info.bw_ets_max[i]);
10035         }
10036
10037         veb->enabled_tc = tc_map;
10038
10039         return ret;
10040 }
10041
10042
10043 /*
10044  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10045  * @vsi: VSI to be configured
10046  * @tc_map: enabled TC bitmap
10047  *
10048  * Returns 0 on success, negative value on failure
10049  */
10050 static enum i40e_status_code
10051 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10052 {
10053         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10054         struct i40e_vsi_context ctxt;
10055         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10056         enum i40e_status_code ret = I40E_SUCCESS;
10057         int i;
10058
10059         /* Check if enabled_tc is same as existing or new TCs */
10060         if (vsi->enabled_tc == tc_map)
10061                 return ret;
10062
10063         /* configure tc bandwidth */
10064         memset(&bw_data, 0, sizeof(bw_data));
10065         bw_data.tc_valid_bits = tc_map;
10066         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10067         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10068                 if (tc_map & BIT_ULL(i))
10069                         bw_data.tc_bw_credits[i] = 1;
10070         }
10071         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10072         if (ret) {
10073                 PMD_INIT_LOG(ERR,
10074                         "AQ command Config VSI BW allocation per TC failed = %d",
10075                         hw->aq.asq_last_status);
10076                 goto out;
10077         }
10078         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10079                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10080
10081         /* Update Queue Pairs Mapping for currently enabled UPs */
10082         ctxt.seid = vsi->seid;
10083         ctxt.pf_num = hw->pf_id;
10084         ctxt.vf_num = 0;
10085         ctxt.uplink_seid = vsi->uplink_seid;
10086         ctxt.info = vsi->info;
10087         i40e_get_cap(hw);
10088         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10089         if (ret)
10090                 goto out;
10091
10092         /* Update the VSI after updating the VSI queue-mapping information */
10093         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10094         if (ret) {
10095                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10096                         hw->aq.asq_last_status);
10097                 goto out;
10098         }
10099         /* update the local VSI info with updated queue map */
10100         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10101                                         sizeof(vsi->info.tc_mapping));
10102         (void)rte_memcpy(&vsi->info.queue_mapping,
10103                         &ctxt.info.queue_mapping,
10104                 sizeof(vsi->info.queue_mapping));
10105         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10106         vsi->info.valid_sections = 0;
10107
10108         /* query and update current VSI BW information */
10109         ret = i40e_vsi_get_bw_config(vsi);
10110         if (ret) {
10111                 PMD_INIT_LOG(ERR,
10112                          "Failed updating vsi bw info, err %s aq_err %s",
10113                          i40e_stat_str(hw, ret),
10114                          i40e_aq_str(hw, hw->aq.asq_last_status));
10115                 goto out;
10116         }
10117
10118         vsi->enabled_tc = tc_map;
10119
10120 out:
10121         return ret;
10122 }
10123
10124 /*
10125  * i40e_dcb_hw_configure - program the dcb setting to hw
10126  * @pf: pf the configuration is taken on
10127  * @new_cfg: new configuration
10128  * @tc_map: enabled TC bitmap
10129  *
10130  * Returns 0 on success, negative value on failure
10131  */
10132 static enum i40e_status_code
10133 i40e_dcb_hw_configure(struct i40e_pf *pf,
10134                       struct i40e_dcbx_config *new_cfg,
10135                       uint8_t tc_map)
10136 {
10137         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10138         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10139         struct i40e_vsi *main_vsi = pf->main_vsi;
10140         struct i40e_vsi_list *vsi_list;
10141         enum i40e_status_code ret;
10142         int i;
10143         uint32_t val;
10144
10145         /* Use the FW API if FW > v4.4*/
10146         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10147               (hw->aq.fw_maj_ver >= 5))) {
10148                 PMD_INIT_LOG(ERR,
10149                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10150                 return I40E_ERR_FIRMWARE_API_VERSION;
10151         }
10152
10153         /* Check if need reconfiguration */
10154         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10155                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10156                 return I40E_SUCCESS;
10157         }
10158
10159         /* Copy the new config to the current config */
10160         *old_cfg = *new_cfg;
10161         old_cfg->etsrec = old_cfg->etscfg;
10162         ret = i40e_set_dcb_config(hw);
10163         if (ret) {
10164                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10165                          i40e_stat_str(hw, ret),
10166                          i40e_aq_str(hw, hw->aq.asq_last_status));
10167                 return ret;
10168         }
10169         /* set receive Arbiter to RR mode and ETS scheme by default */
10170         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10171                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10172                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10173                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10174                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10175                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10176                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10177                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10178                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10179                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10180                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10181                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10182                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10183         }
10184         /* get local mib to check whether it is configured correctly */
10185         /* IEEE mode */
10186         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10187         /* Get Local DCB Config */
10188         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10189                                      &hw->local_dcbx_config);
10190
10191         /* if Veb is created, need to update TC of it at first */
10192         if (main_vsi->veb) {
10193                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10194                 if (ret)
10195                         PMD_INIT_LOG(WARNING,
10196                                  "Failed configuring TC for VEB seid=%d",
10197                                  main_vsi->veb->seid);
10198         }
10199         /* Update each VSI */
10200         i40e_vsi_config_tc(main_vsi, tc_map);
10201         if (main_vsi->veb) {
10202                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10203                         /* Beside main VSI and VMDQ VSIs, only enable default
10204                          * TC for other VSIs
10205                          */
10206                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10207                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10208                                                          tc_map);
10209                         else
10210                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10211                                                          I40E_DEFAULT_TCMAP);
10212                         if (ret)
10213                                 PMD_INIT_LOG(WARNING,
10214                                         "Failed configuring TC for VSI seid=%d",
10215                                         vsi_list->vsi->seid);
10216                         /* continue */
10217                 }
10218         }
10219         return I40E_SUCCESS;
10220 }
10221
10222 /*
10223  * i40e_dcb_init_configure - initial dcb config
10224  * @dev: device being configured
10225  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10226  *
10227  * Returns 0 on success, negative value on failure
10228  */
10229 static int
10230 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10231 {
10232         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10233         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10234         int i, ret = 0;
10235
10236         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10237                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10238                 return -ENOTSUP;
10239         }
10240
10241         /* DCB initialization:
10242          * Update DCB configuration from the Firmware and configure
10243          * LLDP MIB change event.
10244          */
10245         if (sw_dcb == TRUE) {
10246                 ret = i40e_init_dcb(hw);
10247                 /* If lldp agent is stopped, the return value from
10248                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10249                  * adminq status. Otherwise, it should return success.
10250                  */
10251                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10252                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10253                         memset(&hw->local_dcbx_config, 0,
10254                                 sizeof(struct i40e_dcbx_config));
10255                         /* set dcb default configuration */
10256                         hw->local_dcbx_config.etscfg.willing = 0;
10257                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10258                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10259                         hw->local_dcbx_config.etscfg.tsatable[0] =
10260                                                 I40E_IEEE_TSA_ETS;
10261                         /* all UPs mapping to TC0 */
10262                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10263                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10264                         hw->local_dcbx_config.etsrec =
10265                                 hw->local_dcbx_config.etscfg;
10266                         hw->local_dcbx_config.pfc.willing = 0;
10267                         hw->local_dcbx_config.pfc.pfccap =
10268                                                 I40E_MAX_TRAFFIC_CLASS;
10269                         hw->local_dcbx_config.pfc.pfcenable =
10270                                                 I40E_DEFAULT_TCMAP;
10271                         /* FW needs one App to configure HW */
10272                         hw->local_dcbx_config.numapps = 1;
10273                         hw->local_dcbx_config.app[0].selector =
10274                                                 I40E_APP_SEL_ETHTYPE;
10275                         hw->local_dcbx_config.app[0].priority = 3;
10276                         hw->local_dcbx_config.app[0].protocolid =
10277                                                 I40E_APP_PROTOID_FCOE;
10278                         ret = i40e_set_dcb_config(hw);
10279                         if (ret) {
10280                                 PMD_INIT_LOG(ERR,
10281                                         "default dcb config fails. err = %d, aq_err = %d.",
10282                                         ret, hw->aq.asq_last_status);
10283                                 return -ENOSYS;
10284                         }
10285                 } else {
10286                         PMD_INIT_LOG(ERR,
10287                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10288                                 ret, hw->aq.asq_last_status);
10289                         return -ENOTSUP;
10290                 }
10291         } else {
10292                 ret = i40e_aq_start_lldp(hw, NULL);
10293                 if (ret != I40E_SUCCESS)
10294                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10295
10296                 ret = i40e_init_dcb(hw);
10297                 if (!ret) {
10298                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10299                                 PMD_INIT_LOG(ERR,
10300                                         "HW doesn't support DCBX offload.");
10301                                 return -ENOTSUP;
10302                         }
10303                 } else {
10304                         PMD_INIT_LOG(ERR,
10305                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10306                                 ret, hw->aq.asq_last_status);
10307                         return -ENOTSUP;
10308                 }
10309         }
10310         return 0;
10311 }
10312
10313 /*
10314  * i40e_dcb_setup - setup dcb related config
10315  * @dev: device being configured
10316  *
10317  * Returns 0 on success, negative value on failure
10318  */
10319 static int
10320 i40e_dcb_setup(struct rte_eth_dev *dev)
10321 {
10322         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10323         struct i40e_dcbx_config dcb_cfg;
10324         uint8_t tc_map = 0;
10325         int ret = 0;
10326
10327         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10328                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10329                 return -ENOTSUP;
10330         }
10331
10332         if (pf->vf_num != 0)
10333                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10334
10335         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10336         if (ret) {
10337                 PMD_INIT_LOG(ERR, "invalid dcb config");
10338                 return -EINVAL;
10339         }
10340         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10341         if (ret) {
10342                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10343                 return -ENOSYS;
10344         }
10345
10346         return 0;
10347 }
10348
10349 static int
10350 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10351                       struct rte_eth_dcb_info *dcb_info)
10352 {
10353         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10354         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10355         struct i40e_vsi *vsi = pf->main_vsi;
10356         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10357         uint16_t bsf, tc_mapping;
10358         int i, j = 0;
10359
10360         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10361                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10362         else
10363                 dcb_info->nb_tcs = 1;
10364         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10365                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10366         for (i = 0; i < dcb_info->nb_tcs; i++)
10367                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10368
10369         /* get queue mapping if vmdq is disabled */
10370         if (!pf->nb_cfg_vmdq_vsi) {
10371                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10372                         if (!(vsi->enabled_tc & (1 << i)))
10373                                 continue;
10374                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10375                         dcb_info->tc_queue.tc_rxq[j][i].base =
10376                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10377                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10378                         dcb_info->tc_queue.tc_txq[j][i].base =
10379                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10380                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10381                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10382                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10383                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10384                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10385                 }
10386                 return 0;
10387         }
10388
10389         /* get queue mapping if vmdq is enabled */
10390         do {
10391                 vsi = pf->vmdq[j].vsi;
10392                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10393                         if (!(vsi->enabled_tc & (1 << i)))
10394                                 continue;
10395                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10396                         dcb_info->tc_queue.tc_rxq[j][i].base =
10397                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10398                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10399                         dcb_info->tc_queue.tc_txq[j][i].base =
10400                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10401                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10402                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10403                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10404                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10405                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10406                 }
10407                 j++;
10408         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10409         return 0;
10410 }
10411
10412 static int
10413 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10414 {
10415         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10416         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10417         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10418         uint16_t interval =
10419                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10420         uint16_t msix_intr;
10421
10422         msix_intr = intr_handle->intr_vec[queue_id];
10423         if (msix_intr == I40E_MISC_VEC_ID)
10424                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10425                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10426                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10427                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10428                                (interval <<
10429                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10430         else
10431                 I40E_WRITE_REG(hw,
10432                                I40E_PFINT_DYN_CTLN(msix_intr -
10433                                                    I40E_RX_VEC_START),
10434                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10435                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10436                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10437                                (interval <<
10438                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10439
10440         I40E_WRITE_FLUSH(hw);
10441         rte_intr_enable(&pci_dev->intr_handle);
10442
10443         return 0;
10444 }
10445
10446 static int
10447 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10448 {
10449         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10450         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10451         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10452         uint16_t msix_intr;
10453
10454         msix_intr = intr_handle->intr_vec[queue_id];
10455         if (msix_intr == I40E_MISC_VEC_ID)
10456                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10457         else
10458                 I40E_WRITE_REG(hw,
10459                                I40E_PFINT_DYN_CTLN(msix_intr -
10460                                                    I40E_RX_VEC_START),
10461                                0);
10462         I40E_WRITE_FLUSH(hw);
10463
10464         return 0;
10465 }
10466
10467 static int i40e_get_regs(struct rte_eth_dev *dev,
10468                          struct rte_dev_reg_info *regs)
10469 {
10470         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10471         uint32_t *ptr_data = regs->data;
10472         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10473         const struct i40e_reg_info *reg_info;
10474
10475         if (ptr_data == NULL) {
10476                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10477                 regs->width = sizeof(uint32_t);
10478                 return 0;
10479         }
10480
10481         /* The first few registers have to be read using AQ operations */
10482         reg_idx = 0;
10483         while (i40e_regs_adminq[reg_idx].name) {
10484                 reg_info = &i40e_regs_adminq[reg_idx++];
10485                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10486                         for (arr_idx2 = 0;
10487                                         arr_idx2 <= reg_info->count2;
10488                                         arr_idx2++) {
10489                                 reg_offset = arr_idx * reg_info->stride1 +
10490                                         arr_idx2 * reg_info->stride2;
10491                                 reg_offset += reg_info->base_addr;
10492                                 ptr_data[reg_offset >> 2] =
10493                                         i40e_read_rx_ctl(hw, reg_offset);
10494                         }
10495         }
10496
10497         /* The remaining registers can be read using primitives */
10498         reg_idx = 0;
10499         while (i40e_regs_others[reg_idx].name) {
10500                 reg_info = &i40e_regs_others[reg_idx++];
10501                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10502                         for (arr_idx2 = 0;
10503                                         arr_idx2 <= reg_info->count2;
10504                                         arr_idx2++) {
10505                                 reg_offset = arr_idx * reg_info->stride1 +
10506                                         arr_idx2 * reg_info->stride2;
10507                                 reg_offset += reg_info->base_addr;
10508                                 ptr_data[reg_offset >> 2] =
10509                                         I40E_READ_REG(hw, reg_offset);
10510                         }
10511         }
10512
10513         return 0;
10514 }
10515
10516 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10517 {
10518         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10519
10520         /* Convert word count to byte count */
10521         return hw->nvm.sr_size << 1;
10522 }
10523
10524 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10525                            struct rte_dev_eeprom_info *eeprom)
10526 {
10527         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10528         uint16_t *data = eeprom->data;
10529         uint16_t offset, length, cnt_words;
10530         int ret_code;
10531
10532         offset = eeprom->offset >> 1;
10533         length = eeprom->length >> 1;
10534         cnt_words = length;
10535
10536         if (offset > hw->nvm.sr_size ||
10537                 offset + length > hw->nvm.sr_size) {
10538                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10539                 return -EINVAL;
10540         }
10541
10542         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10543
10544         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10545         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10546                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10547                 return -EIO;
10548         }
10549
10550         return 0;
10551 }
10552
10553 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10554                                       struct ether_addr *mac_addr)
10555 {
10556         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10557
10558         if (!is_valid_assigned_ether_addr(mac_addr)) {
10559                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10560                 return;
10561         }
10562
10563         /* Flags: 0x3 updates port address */
10564         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10565 }
10566
10567 static int
10568 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10569 {
10570         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10571         struct rte_eth_dev_data *dev_data = pf->dev_data;
10572         uint32_t frame_size = mtu + ETHER_HDR_LEN
10573                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10574         int ret = 0;
10575
10576         /* check if mtu is within the allowed range */
10577         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10578                 return -EINVAL;
10579
10580         /* mtu setting is forbidden if port is start */
10581         if (dev_data->dev_started) {
10582                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10583                             dev_data->port_id);
10584                 return -EBUSY;
10585         }
10586
10587         if (frame_size > ETHER_MAX_LEN)
10588                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10589         else
10590                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10591
10592         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10593
10594         return ret;
10595 }
10596
10597 /* Restore ethertype filter */
10598 static void
10599 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10600 {
10601         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10602         struct i40e_ethertype_filter_list
10603                 *ethertype_list = &pf->ethertype.ethertype_list;
10604         struct i40e_ethertype_filter *f;
10605         struct i40e_control_filter_stats stats;
10606         uint16_t flags;
10607
10608         TAILQ_FOREACH(f, ethertype_list, rules) {
10609                 flags = 0;
10610                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10611                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10612                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10613                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10614                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10615
10616                 memset(&stats, 0, sizeof(stats));
10617                 i40e_aq_add_rem_control_packet_filter(hw,
10618                                             f->input.mac_addr.addr_bytes,
10619                                             f->input.ether_type,
10620                                             flags, pf->main_vsi->seid,
10621                                             f->queue, 1, &stats, NULL);
10622         }
10623         PMD_DRV_LOG(INFO, "Ethertype filter:"
10624                     " mac_etype_used = %u, etype_used = %u,"
10625                     " mac_etype_free = %u, etype_free = %u",
10626                     stats.mac_etype_used, stats.etype_used,
10627                     stats.mac_etype_free, stats.etype_free);
10628 }
10629
10630 /* Restore tunnel filter */
10631 static void
10632 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10633 {
10634         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10635         struct i40e_vsi *vsi = pf->main_vsi;
10636         struct i40e_tunnel_filter_list
10637                 *tunnel_list = &pf->tunnel.tunnel_list;
10638         struct i40e_tunnel_filter *f;
10639         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10640         bool big_buffer = 0;
10641
10642         TAILQ_FOREACH(f, tunnel_list, rules) {
10643                 memset(&cld_filter, 0, sizeof(cld_filter));
10644                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10645                         (struct ether_addr *)&cld_filter.element.outer_mac);
10646                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10647                         (struct ether_addr *)&cld_filter.element.inner_mac);
10648                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10649                 cld_filter.element.flags = f->input.flags;
10650                 cld_filter.element.tenant_id = f->input.tenant_id;
10651                 cld_filter.element.queue_number = f->queue;
10652                 rte_memcpy(cld_filter.general_fields,
10653                            f->input.general_fields,
10654                            sizeof(f->input.general_fields));
10655
10656                 if (((f->input.flags &
10657                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10658                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10659                     ((f->input.flags &
10660                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10661                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10662                     ((f->input.flags &
10663                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10664                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10665                         big_buffer = 1;
10666
10667                 if (big_buffer)
10668                         i40e_aq_add_cloud_filters_big_buffer(hw,
10669                                              vsi->seid, &cld_filter, 1);
10670                 else
10671                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10672                                                   &cld_filter.element, 1);
10673         }
10674 }
10675
10676 static void
10677 i40e_filter_restore(struct i40e_pf *pf)
10678 {
10679         i40e_ethertype_filter_restore(pf);
10680         i40e_tunnel_filter_restore(pf);
10681         i40e_fdir_filter_restore(pf);
10682 }
10683
10684 static bool
10685 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
10686 {
10687         if (strcmp(dev->driver->pci_drv.driver.name,
10688                    drv->pci_drv.driver.name))
10689                 return false;
10690
10691         return true;
10692 }
10693
10694 int
10695 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10696 {
10697         struct rte_eth_dev *dev;
10698         struct i40e_pf *pf;
10699
10700         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10701
10702         dev = &rte_eth_devices[port];
10703
10704         if (!is_device_supported(dev, &rte_i40e_pmd))
10705                 return -ENOTSUP;
10706
10707         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10708
10709         if (vf >= pf->vf_num || !pf->vfs) {
10710                 PMD_DRV_LOG(ERR, "Invalid argument.");
10711                 return -EINVAL;
10712         }
10713
10714         i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10715
10716         return 0;
10717 }
10718
10719 int
10720 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10721 {
10722         struct rte_eth_dev *dev;
10723         struct i40e_pf *pf;
10724         struct i40e_vsi *vsi;
10725         struct i40e_hw *hw;
10726         struct i40e_vsi_context ctxt;
10727         int ret;
10728
10729         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10730
10731         dev = &rte_eth_devices[port];
10732
10733         if (!is_device_supported(dev, &rte_i40e_pmd))
10734                 return -ENOTSUP;
10735
10736         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10737
10738         if (vf_id >= pf->vf_num || !pf->vfs) {
10739                 PMD_DRV_LOG(ERR, "Invalid argument.");
10740                 return -EINVAL;
10741         }
10742
10743         vsi = pf->vfs[vf_id].vsi;
10744         if (!vsi) {
10745                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10746                 return -EINVAL;
10747         }
10748
10749         /* Check if it has been already on or off */
10750         if (vsi->info.valid_sections &
10751                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10752                 if (on) {
10753                         if ((vsi->info.sec_flags &
10754                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10755                             I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10756                                 return 0; /* already on */
10757                 } else {
10758                         if ((vsi->info.sec_flags &
10759                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10760                                 return 0; /* already off */
10761                 }
10762         }
10763
10764         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10765         if (on)
10766                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10767         else
10768                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10769
10770         memset(&ctxt, 0, sizeof(ctxt));
10771         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10772         ctxt.seid = vsi->seid;
10773
10774         hw = I40E_VSI_TO_HW(vsi);
10775         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10776         if (ret != I40E_SUCCESS) {
10777                 ret = -ENOTSUP;
10778                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10779         }
10780
10781         return ret;
10782 }
10783
10784 static int
10785 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10786 {
10787         uint32_t j, k;
10788         uint16_t vlan_id;
10789         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10790         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10791         int ret;
10792
10793         for (j = 0; j < I40E_VFTA_SIZE; j++) {
10794                 if (!vsi->vfta[j])
10795                         continue;
10796
10797                 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10798                         if (!(vsi->vfta[j] & (1 << k)))
10799                                 continue;
10800
10801                         vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10802                         if (!vlan_id)
10803                                 continue;
10804
10805                         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10806                         if (add)
10807                                 ret = i40e_aq_add_vlan(hw, vsi->seid,
10808                                                        &vlan_data, 1, NULL);
10809                         else
10810                                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10811                                                           &vlan_data, 1, NULL);
10812                         if (ret != I40E_SUCCESS) {
10813                                 PMD_DRV_LOG(ERR,
10814                                             "Failed to add/rm vlan filter");
10815                                 return ret;
10816                         }
10817                 }
10818         }
10819
10820         return I40E_SUCCESS;
10821 }
10822
10823 int
10824 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10825 {
10826         struct rte_eth_dev *dev;
10827         struct i40e_pf *pf;
10828         struct i40e_vsi *vsi;
10829         struct i40e_hw *hw;
10830         struct i40e_vsi_context ctxt;
10831         int ret;
10832
10833         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10834
10835         dev = &rte_eth_devices[port];
10836
10837         if (!is_device_supported(dev, &rte_i40e_pmd))
10838                 return -ENOTSUP;
10839
10840         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10841
10842         if (vf_id >= pf->vf_num || !pf->vfs) {
10843                 PMD_DRV_LOG(ERR, "Invalid argument.");
10844                 return -EINVAL;
10845         }
10846
10847         vsi = pf->vfs[vf_id].vsi;
10848         if (!vsi) {
10849                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10850                 return -EINVAL;
10851         }
10852
10853         /* Check if it has been already on or off */
10854         if (vsi->vlan_anti_spoof_on == on)
10855                 return 0; /* already on or off */
10856
10857         vsi->vlan_anti_spoof_on = on;
10858         if (!vsi->vlan_filter_on) {
10859                 ret = i40e_add_rm_all_vlan_filter(vsi, on);
10860                 if (ret) {
10861                         PMD_DRV_LOG(ERR, "Failed to add/remove VLAN filters.");
10862                         return -ENOTSUP;
10863                 }
10864         }
10865
10866         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10867         if (on)
10868                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10869         else
10870                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10871
10872         memset(&ctxt, 0, sizeof(ctxt));
10873         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10874         ctxt.seid = vsi->seid;
10875
10876         hw = I40E_VSI_TO_HW(vsi);
10877         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10878         if (ret != I40E_SUCCESS) {
10879                 ret = -ENOTSUP;
10880                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10881         }
10882
10883         return ret;
10884 }
10885
10886 static int
10887 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10888 {
10889         struct i40e_mac_filter *f;
10890         struct i40e_macvlan_filter *mv_f;
10891         int i, vlan_num;
10892         enum rte_mac_filter_type filter_type;
10893         int ret = I40E_SUCCESS;
10894         void *temp;
10895
10896         /* remove all the MACs */
10897         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10898                 vlan_num = vsi->vlan_num;
10899                 filter_type = f->mac_info.filter_type;
10900                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10901                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10902                         if (vlan_num == 0) {
10903                                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10904                                 return I40E_ERR_PARAM;
10905                         }
10906                 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10907                            filter_type == RTE_MAC_HASH_MATCH)
10908                         vlan_num = 1;
10909
10910                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10911                 if (!mv_f) {
10912                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10913                         return I40E_ERR_NO_MEMORY;
10914                 }
10915
10916                 for (i = 0; i < vlan_num; i++) {
10917                         mv_f[i].filter_type = filter_type;
10918                         (void)rte_memcpy(&mv_f[i].macaddr,
10919                                          &f->mac_info.mac_addr,
10920                                          ETH_ADDR_LEN);
10921                 }
10922                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10923                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10924                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10925                                                          &f->mac_info.mac_addr);
10926                         if (ret != I40E_SUCCESS) {
10927                                 rte_free(mv_f);
10928                                 return ret;
10929                         }
10930                 }
10931
10932                 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10933                 if (ret != I40E_SUCCESS) {
10934                         rte_free(mv_f);
10935                         return ret;
10936                 }
10937
10938                 rte_free(mv_f);
10939                 ret = I40E_SUCCESS;
10940         }
10941
10942         return ret;
10943 }
10944
10945 static int
10946 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10947 {
10948         struct i40e_mac_filter *f;
10949         struct i40e_macvlan_filter *mv_f;
10950         int i, vlan_num = 0;
10951         int ret = I40E_SUCCESS;
10952         void *temp;
10953
10954         /* restore all the MACs */
10955         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10956                 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10957                     (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10958                         /**
10959                          * If vlan_num is 0, that's the first time to add mac,
10960                          * set mask for vlan_id 0.
10961                          */
10962                         if (vsi->vlan_num == 0) {
10963                                 i40e_set_vlan_filter(vsi, 0, 1);
10964                                 vsi->vlan_num = 1;
10965                         }
10966                         vlan_num = vsi->vlan_num;
10967                 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10968                            (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10969                         vlan_num = 1;
10970
10971                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10972                 if (!mv_f) {
10973                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10974                         return I40E_ERR_NO_MEMORY;
10975                 }
10976
10977                 for (i = 0; i < vlan_num; i++) {
10978                         mv_f[i].filter_type = f->mac_info.filter_type;
10979                         (void)rte_memcpy(&mv_f[i].macaddr,
10980                                          &f->mac_info.mac_addr,
10981                                          ETH_ADDR_LEN);
10982                 }
10983
10984                 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10985                     f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10986                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10987                                                          &f->mac_info.mac_addr);
10988                         if (ret != I40E_SUCCESS) {
10989                                 rte_free(mv_f);
10990                                 return ret;
10991                         }
10992                 }
10993
10994                 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
10995                 if (ret != I40E_SUCCESS) {
10996                         rte_free(mv_f);
10997                         return ret;
10998                 }
10999
11000                 rte_free(mv_f);
11001                 ret = I40E_SUCCESS;
11002         }
11003
11004         return ret;
11005 }
11006
11007 static int
11008 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
11009 {
11010         struct i40e_vsi_context ctxt;
11011         struct i40e_hw *hw;
11012         int ret;
11013
11014         if (!vsi)
11015                 return -EINVAL;
11016
11017         hw = I40E_VSI_TO_HW(vsi);
11018
11019         /* Use the FW API if FW >= v5.0 */
11020         if (hw->aq.fw_maj_ver < 5) {
11021                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
11022                 return -ENOTSUP;
11023         }
11024
11025         /* Check if it has been already on or off */
11026         if (vsi->info.valid_sections &
11027                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
11028                 if (on) {
11029                         if ((vsi->info.switch_id &
11030                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
11031                             I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
11032                                 return 0; /* already on */
11033                 } else {
11034                         if ((vsi->info.switch_id &
11035                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
11036                                 return 0; /* already off */
11037                 }
11038         }
11039
11040         /* remove all the MAC and VLAN first */
11041         ret = i40e_vsi_rm_mac_filter(vsi);
11042         if (ret) {
11043                 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
11044                 return ret;
11045         }
11046         if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
11047                 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
11048                 if (ret) {
11049                         PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
11050                         return ret;
11051                 }
11052         }
11053
11054         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
11055         if (on)
11056                 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
11057         else
11058                 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
11059
11060         memset(&ctxt, 0, sizeof(ctxt));
11061         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11062         ctxt.seid = vsi->seid;
11063
11064         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11065         if (ret != I40E_SUCCESS) {
11066                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11067                 return ret;
11068         }
11069
11070         /* add all the MAC and VLAN back */
11071         ret = i40e_vsi_restore_mac_filter(vsi);
11072         if (ret)
11073                 return ret;
11074         if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
11075                 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
11076                 if (ret)
11077                         return ret;
11078         }
11079
11080         return ret;
11081 }
11082
11083 int
11084 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
11085 {
11086         struct rte_eth_dev *dev;
11087         struct i40e_pf *pf;
11088         struct i40e_pf_vf *vf;
11089         struct i40e_vsi *vsi;
11090         uint16_t vf_id;
11091         int ret;
11092
11093         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11094
11095         dev = &rte_eth_devices[port];
11096
11097         if (!is_device_supported(dev, &rte_i40e_pmd))
11098                 return -ENOTSUP;
11099
11100         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11101
11102         /* setup PF TX loopback */
11103         vsi = pf->main_vsi;
11104         ret = i40e_vsi_set_tx_loopback(vsi, on);
11105         if (ret)
11106                 return -ENOTSUP;
11107
11108         /* setup TX loopback for all the VFs */
11109         if (!pf->vfs) {
11110                 /* if no VF, do nothing. */
11111                 return 0;
11112         }
11113
11114         for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
11115                 vf = &pf->vfs[vf_id];
11116                 vsi = vf->vsi;
11117
11118                 ret = i40e_vsi_set_tx_loopback(vsi, on);
11119                 if (ret)
11120                         return -ENOTSUP;
11121         }
11122
11123         return ret;
11124 }
11125
11126 int
11127 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
11128 {
11129         struct rte_eth_dev *dev;
11130         struct i40e_pf *pf;
11131         struct i40e_vsi *vsi;
11132         struct i40e_hw *hw;
11133         int ret;
11134
11135         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11136
11137         dev = &rte_eth_devices[port];
11138
11139         if (!is_device_supported(dev, &rte_i40e_pmd))
11140                 return -ENOTSUP;
11141
11142         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11143
11144         if (vf_id >= pf->vf_num || !pf->vfs) {
11145                 PMD_DRV_LOG(ERR, "Invalid argument.");
11146                 return -EINVAL;
11147         }
11148
11149         vsi = pf->vfs[vf_id].vsi;
11150         if (!vsi) {
11151                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11152                 return -EINVAL;
11153         }
11154
11155         hw = I40E_VSI_TO_HW(vsi);
11156
11157         ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
11158                                                   on, NULL, true);
11159         if (ret != I40E_SUCCESS) {
11160                 ret = -ENOTSUP;
11161                 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
11162         }
11163
11164         return ret;
11165 }
11166
11167 int
11168 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
11169 {
11170         struct rte_eth_dev *dev;
11171         struct i40e_pf *pf;
11172         struct i40e_vsi *vsi;
11173         struct i40e_hw *hw;
11174         int ret;
11175
11176         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11177
11178         dev = &rte_eth_devices[port];
11179
11180         if (!is_device_supported(dev, &rte_i40e_pmd))
11181                 return -ENOTSUP;
11182
11183         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11184
11185         if (vf_id >= pf->vf_num || !pf->vfs) {
11186                 PMD_DRV_LOG(ERR, "Invalid argument.");
11187                 return -EINVAL;
11188         }
11189
11190         vsi = pf->vfs[vf_id].vsi;
11191         if (!vsi) {
11192                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11193                 return -EINVAL;
11194         }
11195
11196         hw = I40E_VSI_TO_HW(vsi);
11197
11198         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
11199                                                     on, NULL);
11200         if (ret != I40E_SUCCESS) {
11201                 ret = -ENOTSUP;
11202                 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
11203         }
11204
11205         return ret;
11206 }
11207
11208 int
11209 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
11210                              struct ether_addr *mac_addr)
11211 {
11212         struct i40e_mac_filter *f;
11213         struct rte_eth_dev *dev;
11214         struct i40e_pf_vf *vf;
11215         struct i40e_vsi *vsi;
11216         struct i40e_pf *pf;
11217         void *temp;
11218
11219         if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
11220                 return -EINVAL;
11221
11222         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11223
11224         dev = &rte_eth_devices[port];
11225
11226         if (!is_device_supported(dev, &rte_i40e_pmd))
11227                 return -ENOTSUP;
11228
11229         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11230
11231         if (vf_id >= pf->vf_num || !pf->vfs)
11232                 return -EINVAL;
11233
11234         vf = &pf->vfs[vf_id];
11235         vsi = vf->vsi;
11236         if (!vsi) {
11237                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11238                 return -EINVAL;
11239         }
11240
11241         ether_addr_copy(mac_addr, &vf->mac_addr);
11242
11243         /* Remove all existing mac */
11244         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
11245                 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
11246
11247         return 0;
11248 }
11249
11250 /* Set vlan strip on/off for specific VF from host */
11251 int
11252 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
11253 {
11254         struct rte_eth_dev *dev;
11255         struct i40e_pf *pf;
11256         struct i40e_vsi *vsi;
11257         int ret;
11258
11259         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11260
11261         dev = &rte_eth_devices[port];
11262
11263         if (!is_device_supported(dev, &rte_i40e_pmd))
11264                 return -ENOTSUP;
11265
11266         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11267
11268         if (vf_id >= pf->vf_num || !pf->vfs) {
11269                 PMD_DRV_LOG(ERR, "Invalid argument.");
11270                 return -EINVAL;
11271         }
11272
11273         vsi = pf->vfs[vf_id].vsi;
11274
11275         if (!vsi)
11276                 return -EINVAL;
11277
11278         ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
11279         if (ret != I40E_SUCCESS) {
11280                 ret = -ENOTSUP;
11281                 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
11282         }
11283
11284         return ret;
11285 }
11286
11287 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
11288                                     uint16_t vlan_id)
11289 {
11290         struct rte_eth_dev *dev;
11291         struct i40e_pf *pf;
11292         struct i40e_hw *hw;
11293         struct i40e_vsi *vsi;
11294         struct i40e_vsi_context ctxt;
11295         int ret;
11296
11297         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11298
11299         if (vlan_id > ETHER_MAX_VLAN_ID) {
11300                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11301                 return -EINVAL;
11302         }
11303
11304         dev = &rte_eth_devices[port];
11305
11306         if (!is_device_supported(dev, &rte_i40e_pmd))
11307                 return -ENOTSUP;
11308
11309         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11310         hw = I40E_PF_TO_HW(pf);
11311
11312         /**
11313          * return -ENODEV if SRIOV not enabled, VF number not configured
11314          * or no queue assigned.
11315          */
11316         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11317             pf->vf_nb_qps == 0)
11318                 return -ENODEV;
11319
11320         if (vf_id >= pf->vf_num || !pf->vfs) {
11321                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11322                 return -EINVAL;
11323         }
11324
11325         vsi = pf->vfs[vf_id].vsi;
11326         if (!vsi) {
11327                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11328                 return -EINVAL;
11329         }
11330
11331         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11332         vsi->info.pvid = vlan_id;
11333         if (vlan_id > 0)
11334                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
11335         else
11336                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
11337
11338         memset(&ctxt, 0, sizeof(ctxt));
11339         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11340         ctxt.seid = vsi->seid;
11341
11342         hw = I40E_VSI_TO_HW(vsi);
11343         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11344         if (ret != I40E_SUCCESS) {
11345                 ret = -ENOTSUP;
11346                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11347         }
11348
11349         return ret;
11350 }
11351
11352 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
11353                                   uint8_t on)
11354 {
11355         struct rte_eth_dev *dev;
11356         struct i40e_pf *pf;
11357         struct i40e_vsi *vsi;
11358         struct i40e_hw *hw;
11359         struct i40e_mac_filter_info filter;
11360         struct ether_addr broadcast = {
11361                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
11362         int ret;
11363
11364         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11365
11366         if (on > 1) {
11367                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11368                 return -EINVAL;
11369         }
11370
11371         dev = &rte_eth_devices[port];
11372
11373         if (!is_device_supported(dev, &rte_i40e_pmd))
11374                 return -ENOTSUP;
11375
11376         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11377         hw = I40E_PF_TO_HW(pf);
11378
11379         if (vf_id >= pf->vf_num || !pf->vfs) {
11380                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11381                 return -EINVAL;
11382         }
11383
11384         /**
11385          * return -ENODEV if SRIOV not enabled, VF number not configured
11386          * or no queue assigned.
11387          */
11388         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11389             pf->vf_nb_qps == 0) {
11390                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11391                 return -ENODEV;
11392         }
11393
11394         vsi = pf->vfs[vf_id].vsi;
11395         if (!vsi) {
11396                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11397                 return -EINVAL;
11398         }
11399
11400         if (on) {
11401                 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
11402                 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
11403                 ret = i40e_vsi_add_mac(vsi, &filter);
11404         } else {
11405                 ret = i40e_vsi_delete_mac(vsi, &broadcast);
11406         }
11407
11408         if (ret != I40E_SUCCESS && ret != I40E_ERR_PARAM) {
11409                 ret = -ENOTSUP;
11410                 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11411         } else {
11412                 ret = 0;
11413         }
11414
11415         return ret;
11416 }
11417
11418 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11419 {
11420         struct rte_eth_dev *dev;
11421         struct i40e_pf *pf;
11422         struct i40e_hw *hw;
11423         struct i40e_vsi *vsi;
11424         struct i40e_vsi_context ctxt;
11425         int ret;
11426
11427         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11428
11429         if (on > 1) {
11430                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11431                 return -EINVAL;
11432         }
11433
11434         dev = &rte_eth_devices[port];
11435
11436         if (!is_device_supported(dev, &rte_i40e_pmd))
11437                 return -ENOTSUP;
11438
11439         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11440         hw = I40E_PF_TO_HW(pf);
11441
11442         /**
11443          * return -ENODEV if SRIOV not enabled, VF number not configured
11444          * or no queue assigned.
11445          */
11446         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11447             pf->vf_nb_qps == 0) {
11448                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11449                 return -ENODEV;
11450         }
11451
11452         if (vf_id >= pf->vf_num || !pf->vfs) {
11453                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11454                 return -EINVAL;
11455         }
11456
11457         vsi = pf->vfs[vf_id].vsi;
11458         if (!vsi) {
11459                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11460                 return -EINVAL;
11461         }
11462
11463         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11464         if (on) {
11465                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11466                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11467         } else {
11468                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11469                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11470         }
11471
11472         memset(&ctxt, 0, sizeof(ctxt));
11473         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11474         ctxt.seid = vsi->seid;
11475
11476         hw = I40E_VSI_TO_HW(vsi);
11477         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11478         if (ret != I40E_SUCCESS) {
11479                 ret = -ENOTSUP;
11480                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11481         }
11482
11483         return ret;
11484 }
11485
11486 static int
11487 i40e_vlan_filter_count(struct i40e_vsi *vsi)
11488 {
11489         uint32_t j, k;
11490         uint16_t vlan_id;
11491         int count = 0;
11492
11493         for (j = 0; j < I40E_VFTA_SIZE; j++) {
11494                 if (!vsi->vfta[j])
11495                         continue;
11496
11497                 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
11498                         if (!(vsi->vfta[j] & (1 << k)))
11499                                 continue;
11500
11501                         vlan_id = j * I40E_UINT32_BIT_SIZE + k;
11502                         if (!vlan_id)
11503                                 continue;
11504
11505                         count++;
11506                 }
11507         }
11508
11509         return count;
11510 }
11511
11512 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11513                                     uint64_t vf_mask, uint8_t on)
11514 {
11515         struct rte_eth_dev *dev;
11516         struct i40e_pf *pf;
11517         struct i40e_hw *hw;
11518         struct i40e_vsi *vsi;
11519         uint16_t vf_idx;
11520         int ret = I40E_SUCCESS;
11521
11522         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11523
11524         dev = &rte_eth_devices[port];
11525
11526         if (!is_device_supported(dev, &rte_i40e_pmd))
11527                 return -ENOTSUP;
11528
11529         if (vlan_id > ETHER_MAX_VLAN_ID || !vlan_id) {
11530                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11531                 return -EINVAL;
11532         }
11533
11534         if (vf_mask == 0) {
11535                 PMD_DRV_LOG(ERR, "No VF.");
11536                 return -EINVAL;
11537         }
11538
11539         if (on > 1) {
11540                 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11541                 return -EINVAL;
11542         }
11543
11544         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11545         hw = I40E_PF_TO_HW(pf);
11546
11547         /**
11548          * return -ENODEV if SRIOV not enabled, VF number not configured
11549          * or no queue assigned.
11550          */
11551         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11552             pf->vf_nb_qps == 0) {
11553                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11554                 return -ENODEV;
11555         }
11556
11557         for (vf_idx = 0; vf_idx < pf->vf_num && ret == I40E_SUCCESS; vf_idx++) {
11558                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11559                         vsi = pf->vfs[vf_idx].vsi;
11560                         if (on) {
11561                                 if (!vsi->vlan_filter_on) {
11562                                         vsi->vlan_filter_on = true;
11563                                         i40e_aq_set_vsi_vlan_promisc(hw,
11564                                                                      vsi->seid,
11565                                                                      false,
11566                                                                      NULL);
11567                                         if (!vsi->vlan_anti_spoof_on)
11568                                                 i40e_add_rm_all_vlan_filter(
11569                                                         vsi, true);
11570                                 }
11571                                 ret = i40e_vsi_add_vlan(vsi, vlan_id);
11572                         } else {
11573                                 ret = i40e_vsi_delete_vlan(vsi, vlan_id);
11574
11575                                 if (!i40e_vlan_filter_count(vsi)) {
11576                                         vsi->vlan_filter_on = false;
11577                                         i40e_aq_set_vsi_vlan_promisc(hw,
11578                                                                      vsi->seid,
11579                                                                      true,
11580                                                                      NULL);
11581                                 }
11582                         }
11583                 }
11584         }
11585
11586         if (ret != I40E_SUCCESS) {
11587                 ret = -ENOTSUP;
11588                 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11589         }
11590
11591         return ret;
11592 }
11593
11594 int
11595 rte_pmd_i40e_get_vf_stats(uint8_t port,
11596                           uint16_t vf_id,
11597                           struct rte_eth_stats *stats)
11598 {
11599         struct rte_eth_dev *dev;
11600         struct i40e_pf *pf;
11601         struct i40e_vsi *vsi;
11602
11603         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11604
11605         dev = &rte_eth_devices[port];
11606
11607         if (!is_device_supported(dev, &rte_i40e_pmd))
11608                 return -ENOTSUP;
11609
11610         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11611
11612         if (vf_id >= pf->vf_num || !pf->vfs) {
11613                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11614                 return -EINVAL;
11615         }
11616
11617         vsi = pf->vfs[vf_id].vsi;
11618         if (!vsi) {
11619                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11620                 return -EINVAL;
11621         }
11622
11623         i40e_update_vsi_stats(vsi);
11624
11625         stats->ipackets = vsi->eth_stats.rx_unicast +
11626                         vsi->eth_stats.rx_multicast +
11627                         vsi->eth_stats.rx_broadcast;
11628         stats->opackets = vsi->eth_stats.tx_unicast +
11629                         vsi->eth_stats.tx_multicast +
11630                         vsi->eth_stats.tx_broadcast;
11631         stats->ibytes   = vsi->eth_stats.rx_bytes;
11632         stats->obytes   = vsi->eth_stats.tx_bytes;
11633         stats->ierrors  = vsi->eth_stats.rx_discards;
11634         stats->oerrors  = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11635
11636         return 0;
11637 }
11638
11639 int
11640 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11641                             uint16_t vf_id)
11642 {
11643         struct rte_eth_dev *dev;
11644         struct i40e_pf *pf;
11645         struct i40e_vsi *vsi;
11646
11647         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11648
11649         dev = &rte_eth_devices[port];
11650
11651         if (!is_device_supported(dev, &rte_i40e_pmd))
11652                 return -ENOTSUP;
11653
11654         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11655
11656         if (vf_id >= pf->vf_num || !pf->vfs) {
11657                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11658                 return -EINVAL;
11659         }
11660
11661         vsi = pf->vfs[vf_id].vsi;
11662         if (!vsi) {
11663                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11664                 return -EINVAL;
11665         }
11666
11667         vsi->offset_loaded = false;
11668         i40e_update_vsi_stats(vsi);
11669
11670         return 0;
11671 }
11672
11673 int
11674 rte_pmd_i40e_set_vf_max_bw(uint8_t port, uint16_t vf_id, uint32_t bw)
11675 {
11676         struct rte_eth_dev *dev;
11677         struct i40e_pf *pf;
11678         struct i40e_vsi *vsi;
11679         struct i40e_hw *hw;
11680         int ret = 0;
11681         int i;
11682
11683         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11684
11685         dev = &rte_eth_devices[port];
11686
11687         if (!is_device_supported(dev, &rte_i40e_pmd))
11688                 return -ENOTSUP;
11689
11690         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11691
11692         if (vf_id >= pf->vf_num || !pf->vfs) {
11693                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11694                 return -EINVAL;
11695         }
11696
11697         vsi = pf->vfs[vf_id].vsi;
11698         if (!vsi) {
11699                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11700                 return -EINVAL;
11701         }
11702
11703         if (bw > I40E_QOS_BW_MAX) {
11704                 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11705                             I40E_QOS_BW_MAX);
11706                 return -EINVAL;
11707         }
11708
11709         if (bw % I40E_QOS_BW_GRANULARITY) {
11710                 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11711                             I40E_QOS_BW_GRANULARITY);
11712                 return -EINVAL;
11713         }
11714
11715         bw /= I40E_QOS_BW_GRANULARITY;
11716
11717         hw = I40E_VSI_TO_HW(vsi);
11718
11719         /* No change. */
11720         if (bw == vsi->bw_info.bw_limit) {
11721                 PMD_DRV_LOG(INFO,
11722                             "No change for VF max bandwidth. Nothing to do.");
11723                 return 0;
11724         }
11725
11726         /**
11727          * VF bandwidth limitation and TC bandwidth limitation cannot be
11728          * enabled in parallel, quit if TC bandwidth limitation is enabled.
11729          *
11730          * If bw is 0, means disable bandwidth limitation. Then no need to
11731          * check TC bandwidth limitation.
11732          */
11733         if (bw) {
11734                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11735                         if ((vsi->enabled_tc & BIT_ULL(i)) &&
11736                             vsi->bw_info.bw_ets_credits[i])
11737                                 break;
11738                 }
11739                 if (i != I40E_MAX_TRAFFIC_CLASS) {
11740                         PMD_DRV_LOG(ERR,
11741                                     "TC max bandwidth has been set on this VF,"
11742                                     " please disable it first.");
11743                         return -EINVAL;
11744                 }
11745         }
11746
11747         ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, (uint16_t)bw, 0, NULL);
11748         if (ret) {
11749                 PMD_DRV_LOG(ERR,
11750                             "Failed to set VF %d bandwidth, err(%d).",
11751                             vf_id, ret);
11752                 return -EINVAL;
11753         }
11754
11755         /* Store the configuration. */
11756         vsi->bw_info.bw_limit = (uint16_t)bw;
11757         vsi->bw_info.bw_max = 0;
11758
11759         return 0;
11760 }
11761
11762 int
11763 rte_pmd_i40e_set_vf_tc_bw_alloc(uint8_t port, uint16_t vf_id,
11764                                 uint8_t tc_num, uint8_t *bw_weight)
11765 {
11766         struct rte_eth_dev *dev;
11767         struct i40e_pf *pf;
11768         struct i40e_vsi *vsi;
11769         struct i40e_hw *hw;
11770         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw;
11771         int ret = 0;
11772         int i, j;
11773         uint16_t sum;
11774         bool b_change = false;
11775
11776         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11777
11778         dev = &rte_eth_devices[port];
11779
11780         if (!is_device_supported(dev, &rte_i40e_pmd))
11781                 return -ENOTSUP;
11782
11783         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11784
11785         if (vf_id >= pf->vf_num || !pf->vfs) {
11786                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11787                 return -EINVAL;
11788         }
11789
11790         vsi = pf->vfs[vf_id].vsi;
11791         if (!vsi) {
11792                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11793                 return -EINVAL;
11794         }
11795
11796         if (tc_num > I40E_MAX_TRAFFIC_CLASS) {
11797                 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
11798                             I40E_MAX_TRAFFIC_CLASS);
11799                 return -EINVAL;
11800         }
11801
11802         sum = 0;
11803         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11804                 if (vsi->enabled_tc & BIT_ULL(i))
11805                         sum++;
11806         }
11807         if (sum != tc_num) {
11808                 PMD_DRV_LOG(ERR,
11809                             "Weight should be set for all %d enabled TCs.",
11810                             sum);
11811                 return -EINVAL;
11812         }
11813
11814         sum = 0;
11815         for (i = 0; i < tc_num; i++) {
11816                 if (!bw_weight[i]) {
11817                         PMD_DRV_LOG(ERR,
11818                                     "The weight should be 1 at least.");
11819                         return -EINVAL;
11820                 }
11821                 sum += bw_weight[i];
11822         }
11823         if (sum != 100) {
11824                 PMD_DRV_LOG(ERR,
11825                             "The summary of the TC weight should be 100.");
11826                 return -EINVAL;
11827         }
11828
11829         /**
11830          * Create the configuration for all the TCs.
11831          */
11832         memset(&tc_bw, 0, sizeof(tc_bw));
11833         tc_bw.tc_valid_bits = vsi->enabled_tc;
11834         j = 0;
11835         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11836                 if (vsi->enabled_tc & BIT_ULL(i)) {
11837                         if (bw_weight[j] !=
11838                                 vsi->bw_info.bw_ets_share_credits[i])
11839                                 b_change = true;
11840
11841                         tc_bw.tc_bw_credits[i] = bw_weight[j];
11842                         j++;
11843                 }
11844         }
11845
11846         /* No change. */
11847         if (!b_change) {
11848                 PMD_DRV_LOG(INFO,
11849                             "No change for TC allocated bandwidth."
11850                             " Nothing to do.");
11851                 return 0;
11852         }
11853
11854         hw = I40E_VSI_TO_HW(vsi);
11855
11856         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw, NULL);
11857         if (ret) {
11858                 PMD_DRV_LOG(ERR,
11859                             "Failed to set VF %d TC bandwidth weight, err(%d).",
11860                             vf_id, ret);
11861                 return -EINVAL;
11862         }
11863
11864         /* Store the configuration. */
11865         j = 0;
11866         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11867                 if (vsi->enabled_tc & BIT_ULL(i)) {
11868                         vsi->bw_info.bw_ets_share_credits[i] = bw_weight[j];
11869                         j++;
11870                 }
11871         }
11872
11873         return 0;
11874 }
11875
11876 int
11877 rte_pmd_i40e_set_vf_tc_max_bw(uint8_t port, uint16_t vf_id,
11878                               uint8_t tc_no, uint32_t bw)
11879 {
11880         struct rte_eth_dev *dev;
11881         struct i40e_pf *pf;
11882         struct i40e_vsi *vsi;
11883         struct i40e_hw *hw;
11884         struct i40e_aqc_configure_vsi_ets_sla_bw_data tc_bw;
11885         int ret = 0;
11886         int i;
11887
11888         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11889
11890         dev = &rte_eth_devices[port];
11891
11892         if (!is_device_supported(dev, &rte_i40e_pmd))
11893                 return -ENOTSUP;
11894
11895         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11896
11897         if (vf_id >= pf->vf_num || !pf->vfs) {
11898                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11899                 return -EINVAL;
11900         }
11901
11902         vsi = pf->vfs[vf_id].vsi;
11903         if (!vsi) {
11904                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11905                 return -EINVAL;
11906         }
11907
11908         if (bw > I40E_QOS_BW_MAX) {
11909                 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11910                             I40E_QOS_BW_MAX);
11911                 return -EINVAL;
11912         }
11913
11914         if (bw % I40E_QOS_BW_GRANULARITY) {
11915                 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11916                             I40E_QOS_BW_GRANULARITY);
11917                 return -EINVAL;
11918         }
11919
11920         bw /= I40E_QOS_BW_GRANULARITY;
11921
11922         if (tc_no >= I40E_MAX_TRAFFIC_CLASS) {
11923                 PMD_DRV_LOG(ERR, "TC No. should be less than %d.",
11924                             I40E_MAX_TRAFFIC_CLASS);
11925                 return -EINVAL;
11926         }
11927
11928         hw = I40E_VSI_TO_HW(vsi);
11929
11930         if (!(vsi->enabled_tc & BIT_ULL(tc_no))) {
11931                 PMD_DRV_LOG(ERR, "VF %d TC %d isn't enabled.",
11932                             vf_id, tc_no);
11933                 return -EINVAL;
11934         }
11935
11936         /* No change. */
11937         if (bw == vsi->bw_info.bw_ets_credits[tc_no]) {
11938                 PMD_DRV_LOG(INFO,
11939                             "No change for TC max bandwidth. Nothing to do.");
11940                 return 0;
11941         }
11942
11943         /**
11944          * VF bandwidth limitation and TC bandwidth limitation cannot be
11945          * enabled in parallel, disable VF bandwidth limitation if it's
11946          * enabled.
11947          * If bw is 0, means disable bandwidth limitation. Then no need to
11948          * care about VF bandwidth limitation configuration.
11949          */
11950         if (bw && vsi->bw_info.bw_limit) {
11951                 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, 0, 0, NULL);
11952                 if (ret) {
11953                         PMD_DRV_LOG(ERR,
11954                                     "Failed to disable VF(%d)"
11955                                     " bandwidth limitation, err(%d).",
11956                                     vf_id, ret);
11957                         return -EINVAL;
11958                 }
11959
11960                 PMD_DRV_LOG(INFO,
11961                             "VF max bandwidth is disabled according"
11962                             " to TC max bandwidth setting.");
11963         }
11964
11965         /**
11966          * Get all the TCs' info to create a whole picture.
11967          * Because the incremental change isn't permitted.
11968          */
11969         memset(&tc_bw, 0, sizeof(tc_bw));
11970         tc_bw.tc_valid_bits = vsi->enabled_tc;
11971         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11972                 if (vsi->enabled_tc & BIT_ULL(i)) {
11973                         tc_bw.tc_bw_credits[i] =
11974                                 rte_cpu_to_le_16(
11975                                         vsi->bw_info.bw_ets_credits[i]);
11976                 }
11977         }
11978         tc_bw.tc_bw_credits[tc_no] = rte_cpu_to_le_16((uint16_t)bw);
11979
11980         ret = i40e_aq_config_vsi_ets_sla_bw_limit(hw, vsi->seid, &tc_bw, NULL);
11981         if (ret) {
11982                 PMD_DRV_LOG(ERR,
11983                             "Failed to set VF %d TC %d max bandwidth, err(%d).",
11984                             vf_id, tc_no, ret);
11985                 return -EINVAL;
11986         }
11987
11988         /* Store the configuration. */
11989         vsi->bw_info.bw_ets_credits[tc_no] = (uint16_t)bw;
11990
11991         return 0;
11992 }
11993
11994 int
11995 rte_pmd_i40e_set_tc_strict_prio(uint8_t port, uint8_t tc_map)
11996 {
11997         struct rte_eth_dev *dev;
11998         struct i40e_pf *pf;
11999         struct i40e_vsi *vsi;
12000         struct i40e_veb *veb;
12001         struct i40e_hw *hw;
12002         struct i40e_aqc_configure_switching_comp_ets_data ets_data;
12003         int i;
12004         int ret;
12005
12006         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12007
12008         dev = &rte_eth_devices[port];
12009
12010         if (!is_device_supported(dev, &rte_i40e_pmd))
12011                 return -ENOTSUP;
12012
12013         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12014
12015         vsi = pf->main_vsi;
12016         if (!vsi) {
12017                 PMD_DRV_LOG(ERR, "Invalid VSI.");
12018                 return -EINVAL;
12019         }
12020
12021         veb = vsi->veb;
12022         if (!veb) {
12023                 PMD_DRV_LOG(ERR, "Invalid VEB.");
12024                 return -EINVAL;
12025         }
12026
12027         if ((tc_map & veb->enabled_tc) != tc_map) {
12028                 PMD_DRV_LOG(ERR,
12029                             "TC bitmap isn't the subset of enabled TCs 0x%x.",
12030                             veb->enabled_tc);
12031                 return -EINVAL;
12032         }
12033
12034         if (tc_map == veb->strict_prio_tc) {
12035                 PMD_DRV_LOG(INFO, "No change for TC bitmap. Nothing to do.");
12036                 return 0;
12037         }
12038
12039         hw = I40E_VSI_TO_HW(vsi);
12040
12041         /* Disable DCBx if it's the first time to set strict priority. */
12042         if (!veb->strict_prio_tc) {
12043                 ret = i40e_aq_stop_lldp(hw, true, NULL);
12044                 if (ret)
12045                         PMD_DRV_LOG(INFO,
12046                                     "Failed to disable DCBx as it's already"
12047                                     " disabled.");
12048                 else
12049                         PMD_DRV_LOG(INFO,
12050                                     "DCBx is disabled according to strict"
12051                                     " priority setting.");
12052         }
12053
12054         memset(&ets_data, 0, sizeof(ets_data));
12055         ets_data.tc_valid_bits = veb->enabled_tc;
12056         ets_data.seepage = I40E_AQ_ETS_SEEPAGE_EN_MASK;
12057         ets_data.tc_strict_priority_flags = tc_map;
12058         /* Get all TCs' bandwidth. */
12059         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12060                 if (veb->enabled_tc & BIT_ULL(i)) {
12061                         /* For rubust, if bandwidth is 0, use 1 instead. */
12062                         if (veb->bw_info.bw_ets_share_credits[i])
12063                                 ets_data.tc_bw_share_credits[i] =
12064                                         veb->bw_info.bw_ets_share_credits[i];
12065                         else
12066                                 ets_data.tc_bw_share_credits[i] =
12067                                         I40E_QOS_BW_WEIGHT_MIN;
12068                 }
12069         }
12070
12071         if (!veb->strict_prio_tc)
12072                 ret = i40e_aq_config_switch_comp_ets(
12073                         hw, veb->uplink_seid,
12074                         &ets_data, i40e_aqc_opc_enable_switching_comp_ets,
12075                         NULL);
12076         else if (tc_map)
12077                 ret = i40e_aq_config_switch_comp_ets(
12078                         hw, veb->uplink_seid,
12079                         &ets_data, i40e_aqc_opc_modify_switching_comp_ets,
12080                         NULL);
12081         else
12082                 ret = i40e_aq_config_switch_comp_ets(
12083                         hw, veb->uplink_seid,
12084                         &ets_data, i40e_aqc_opc_disable_switching_comp_ets,
12085                         NULL);
12086
12087         if (ret) {
12088                 PMD_DRV_LOG(ERR,
12089                             "Failed to set TCs' strict priority mode."
12090                             " err (%d)", ret);
12091                 return -EINVAL;
12092         }
12093
12094         veb->strict_prio_tc = tc_map;
12095
12096         /* Enable DCBx again, if all the TCs' strict priority disabled. */
12097         if (!tc_map) {
12098                 ret = i40e_aq_start_lldp(hw, NULL);
12099                 if (ret) {
12100                         PMD_DRV_LOG(ERR,
12101                                     "Failed to enable DCBx, err(%d).", ret);
12102                         return -EINVAL;
12103                 }
12104
12105                 PMD_DRV_LOG(INFO,
12106                             "DCBx is enabled again according to strict"
12107                             " priority setting.");
12108         }
12109
12110         return ret;
12111 }
12112
12113 #define I40E_PROFILE_INFO_SIZE 48
12114 #define I40E_MAX_PROFILE_NUM 16
12115
12116 static void
12117 i40e_generate_profile_info_sec(char *name, struct i40e_ddp_version *version,
12118                                uint32_t track_id, uint8_t *profile_info_sec,
12119                                bool add)
12120 {
12121         struct i40e_profile_section_header *sec = NULL;
12122         struct i40e_profile_info *pinfo;
12123
12124         sec = (struct i40e_profile_section_header *)profile_info_sec;
12125         sec->tbl_size = 1;
12126         sec->data_end = sizeof(struct i40e_profile_section_header) +
12127                 sizeof(struct i40e_profile_info);
12128         sec->section.type = SECTION_TYPE_INFO;
12129         sec->section.offset = sizeof(struct i40e_profile_section_header);
12130         sec->section.size = sizeof(struct i40e_profile_info);
12131         pinfo = (struct i40e_profile_info *)(profile_info_sec +
12132                                              sec->section.offset);
12133         pinfo->track_id = track_id;
12134         memcpy(pinfo->name, name, I40E_DDP_NAME_SIZE);
12135         memcpy(&pinfo->version, version, sizeof(struct i40e_ddp_version));
12136         if (add)
12137                 pinfo->op = I40E_DDP_ADD_TRACKID;
12138         else
12139                 pinfo->op = I40E_DDP_REMOVE_TRACKID;
12140 }
12141
12142 static enum i40e_status_code
12143 i40e_add_rm_profile_info(struct i40e_hw *hw, uint8_t *profile_info_sec)
12144 {
12145         enum i40e_status_code status = I40E_SUCCESS;
12146         struct i40e_profile_section_header *sec;
12147         uint32_t track_id;
12148         uint32_t offset = 0;
12149         uint32_t info = 0;
12150
12151         sec = (struct i40e_profile_section_header *)profile_info_sec;
12152         track_id = ((struct i40e_profile_info *)(profile_info_sec +
12153                                          sec->section.offset))->track_id;
12154
12155         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
12156                                    track_id, &offset, &info, NULL);
12157         if (status)
12158                 PMD_DRV_LOG(ERR, "Failed to add/remove profile info: "
12159                             "offset %d, info %d",
12160                             offset, info);
12161
12162         return status;
12163 }
12164
12165 #define I40E_PROFILE_INFO_SIZE 48
12166 #define I40E_MAX_PROFILE_NUM 16
12167
12168 /* Check if the profile info exists */
12169 static int
12170 i40e_check_profile_info(uint8_t port, uint8_t *profile_info_sec)
12171 {
12172         struct rte_eth_dev *dev = &rte_eth_devices[port];
12173         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12174         uint8_t *buff;
12175         struct rte_pmd_i40e_profile_list *p_list;
12176         struct rte_pmd_i40e_profile_info *pinfo, *p;
12177         uint32_t i;
12178         int ret;
12179
12180         buff = rte_zmalloc("pinfo_list",
12181                            (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
12182                            0);
12183         if (!buff) {
12184                 PMD_DRV_LOG(ERR, "failed to allocate memory");
12185                 return -1;
12186         }
12187
12188         ret = i40e_aq_get_ddp_list(hw, (void *)buff,
12189                       (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
12190                       0, NULL);
12191         if (ret) {
12192                 PMD_DRV_LOG(ERR, "Failed to get profile info list.");
12193                 rte_free(buff);
12194                 return -1;
12195         }
12196         p_list = (struct rte_pmd_i40e_profile_list *)buff;
12197         pinfo = (struct rte_pmd_i40e_profile_info *)(profile_info_sec +
12198                              sizeof(struct i40e_profile_section_header));
12199         for (i = 0; i < p_list->p_count; i++) {
12200                 p = &p_list->p_info[i];
12201                 if ((pinfo->track_id == p->track_id) &&
12202                     !memcmp(&pinfo->version, &p->version,
12203                             sizeof(struct i40e_ddp_version)) &&
12204                     !memcmp(&pinfo->name, &p->name,
12205                             I40E_DDP_NAME_SIZE)) {
12206                         PMD_DRV_LOG(INFO, "Profile exists.");
12207                         rte_free(buff);
12208                         return 1;
12209                 }
12210         }
12211
12212         rte_free(buff);
12213         return 0;
12214 }
12215
12216 int
12217 rte_pmd_i40e_process_ddp_package(uint8_t port, uint8_t *buff,
12218                                  uint32_t size,
12219                                  enum rte_pmd_i40e_package_op op)
12220 {
12221         struct rte_eth_dev *dev;
12222         struct i40e_hw *hw;
12223         struct i40e_package_header *pkg_hdr;
12224         struct i40e_generic_seg_header *profile_seg_hdr;
12225         struct i40e_generic_seg_header *metadata_seg_hdr;
12226         uint32_t track_id;
12227         uint8_t *profile_info_sec;
12228         int is_exist;
12229         enum i40e_status_code status = I40E_SUCCESS;
12230
12231         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12232
12233         dev = &rte_eth_devices[port];
12234
12235         if (!is_device_supported(dev, &rte_i40e_pmd))
12236                 return -ENOTSUP;
12237
12238         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12239
12240         if (size < (sizeof(struct i40e_package_header) +
12241                     sizeof(struct i40e_metadata_segment) +
12242                     sizeof(uint32_t) * 2)) {
12243                 PMD_DRV_LOG(ERR, "Buff is invalid.");
12244                 return -EINVAL;
12245         }
12246
12247         pkg_hdr = (struct i40e_package_header *)buff;
12248
12249         if (!pkg_hdr) {
12250                 PMD_DRV_LOG(ERR, "Failed to fill the package structure");
12251                 return -EINVAL;
12252         }
12253
12254         if (pkg_hdr->segment_count < 2) {
12255                 PMD_DRV_LOG(ERR, "Segment_count should be 2 at least.");
12256                 return -EINVAL;
12257         }
12258
12259         /* Find metadata segment */
12260         metadata_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_METADATA,
12261                                                         pkg_hdr);
12262         if (!metadata_seg_hdr) {
12263                 PMD_DRV_LOG(ERR, "Failed to find metadata segment header");
12264                 return -EINVAL;
12265         }
12266         track_id = ((struct i40e_metadata_segment *)metadata_seg_hdr)->track_id;
12267
12268         /* Find profile segment */
12269         profile_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_I40E,
12270                                                        pkg_hdr);
12271         if (!profile_seg_hdr) {
12272                 PMD_DRV_LOG(ERR, "Failed to find profile segment header");
12273                 return -EINVAL;
12274         }
12275
12276         profile_info_sec = rte_zmalloc("i40e_profile_info",
12277                                sizeof(struct i40e_profile_section_header) +
12278                                sizeof(struct i40e_profile_info),
12279                                0);
12280         if (!profile_info_sec) {
12281                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12282                 return -EINVAL;
12283         }
12284
12285         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12286                 /* Check if the profile exists */
12287                 i40e_generate_profile_info_sec(
12288                      ((struct i40e_profile_segment *)profile_seg_hdr)->name,
12289                      &((struct i40e_profile_segment *)profile_seg_hdr)->version,
12290                      track_id, profile_info_sec, 1);
12291                 is_exist = i40e_check_profile_info(port, profile_info_sec);
12292                 if (is_exist > 0) {
12293                         PMD_DRV_LOG(ERR, "Profile already exists.");
12294                         rte_free(profile_info_sec);
12295                         return 1;
12296                 } else if (is_exist < 0) {
12297                         PMD_DRV_LOG(ERR, "Failed to check profile.");
12298                         rte_free(profile_info_sec);
12299                         return -EINVAL;
12300                 }
12301
12302                 /* Write profile to HW */
12303                 status = i40e_write_profile(hw,
12304                                  (struct i40e_profile_segment *)profile_seg_hdr,
12305                                  track_id);
12306                 if (status) {
12307                         PMD_DRV_LOG(ERR, "Failed to write profile.");
12308                         rte_free(profile_info_sec);
12309                         return status;
12310                 }
12311
12312                 /* Add profile info to info list */
12313                 status = i40e_add_rm_profile_info(hw, profile_info_sec);
12314                 if (status)
12315                         PMD_DRV_LOG(ERR, "Failed to add profile info.");
12316         } else
12317                 PMD_DRV_LOG(ERR, "Operation not supported.");
12318
12319         rte_free(profile_info_sec);
12320         return status;
12321 }
12322
12323 int
12324 rte_pmd_i40e_get_ddp_list(uint8_t port, uint8_t *buff, uint32_t size)
12325 {
12326         struct rte_eth_dev *dev;
12327         struct i40e_hw *hw;
12328         enum i40e_status_code status = I40E_SUCCESS;
12329
12330         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12331
12332         dev = &rte_eth_devices[port];
12333
12334         if (!is_device_supported(dev, &rte_i40e_pmd))
12335                 return -ENOTSUP;
12336
12337         if (size < (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4))
12338                 return -EINVAL;
12339
12340         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12341
12342         status = i40e_aq_get_ddp_list(hw, (void *)buff,
12343                                       size, 0, NULL);
12344
12345         return status;
12346 }
12347
12348 /* Create a QinQ cloud filter
12349  *
12350  * The Fortville NIC has limited resources for tunnel filters,
12351  * so we can only reuse existing filters.
12352  *
12353  * In step 1 we define which Field Vector fields can be used for
12354  * filter types.
12355  * As we do not have the inner tag defined as a field,
12356  * we have to define it first, by reusing one of L1 entries.
12357  *
12358  * In step 2 we are replacing one of existing filter types with
12359  * a new one for QinQ.
12360  * As we reusing L1 and replacing L2, some of the default filter
12361  * types will disappear,which depends on L1 and L2 entries we reuse.
12362  *
12363  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12364  *
12365  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12366  *              later when we define the cloud filter.
12367  *      a.      Valid_flags.replace_cloud = 0
12368  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12369  *      c.      New_filter = 0x10
12370  *      d.      TR bit = 0xff (optional, not used here)
12371  *      e.      Buffer – 2 entries:
12372  *              i.      Byte 0 = 8 (outer vlan FV index).
12373  *                      Byte 1 = 0 (rsv)
12374  *                      Byte 2-3 = 0x0fff
12375  *              ii.     Byte 0 = 37 (inner vlan FV index).
12376  *                      Byte 1 =0 (rsv)
12377  *                      Byte 2-3 = 0x0fff
12378  *
12379  * Step 2:
12380  * 2.   Create cloud filter using two L1 filters entries: stag and
12381  *              new filter(outer vlan+ inner vlan)
12382  *      a.      Valid_flags.replace_cloud = 1
12383  *      b.      Old_filter = 1 (instead of outer IP)
12384  *      c.      New_filter = 0x10
12385  *      d.      Buffer – 2 entries:
12386  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12387  *                      Byte 1-3 = 0 (rsv)
12388  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12389  *                      Byte 9-11 = 0 (rsv)
12390  */
12391 static int
12392 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12393 {
12394         int ret = -ENOTSUP;
12395         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12396         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12397         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12398
12399         /* Init */
12400         memset(&filter_replace, 0,
12401                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12402         memset(&filter_replace_buf, 0,
12403                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12404
12405         /* create L1 filter */
12406         filter_replace.old_filter_type =
12407                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12408         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12409         filter_replace.tr_bit = 0;
12410
12411         /* Prepare the buffer, 2 entries */
12412         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12413         filter_replace_buf.data[0] |=
12414                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12415         /* Field Vector 12b mask */
12416         filter_replace_buf.data[2] = 0xff;
12417         filter_replace_buf.data[3] = 0x0f;
12418         filter_replace_buf.data[4] =
12419                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12420         filter_replace_buf.data[4] |=
12421                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12422         /* Field Vector 12b mask */
12423         filter_replace_buf.data[6] = 0xff;
12424         filter_replace_buf.data[7] = 0x0f;
12425         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12426                         &filter_replace_buf);
12427         if (ret != I40E_SUCCESS)
12428                 return ret;
12429
12430         /* Apply the second L2 cloud filter */
12431         memset(&filter_replace, 0,
12432                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12433         memset(&filter_replace_buf, 0,
12434                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12435
12436         /* create L2 filter, input for L2 filter will be L1 filter  */
12437         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12438         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12439         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12440
12441         /* Prepare the buffer, 2 entries */
12442         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12443         filter_replace_buf.data[0] |=
12444                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12445         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12446         filter_replace_buf.data[4] |=
12447                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12448         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12449                         &filter_replace_buf);
12450         return ret;
12451 }
12452
12453 RTE_INIT(i40e_init_log);
12454 static void
12455 i40e_init_log(void)
12456 {
12457         i40e_logtype_init = rte_log_register("pmd.i40e.init");
12458         if (i40e_logtype_init >= 0)
12459                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12460         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
12461         if (i40e_logtype_driver >= 0)
12462                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12463 }