drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64
  65 /* Maximun number of MAC addresses */
  66 #define I40E_NUM_MACADDR_MAX       64
  67 #define I40E_CLEAR_PXE_WAIT_MS     200
  68
  69 /* Maximun number of capability elements */
  70 #define I40E_MAX_CAP_ELE_NUM       128
  71
  72 /* Wait count and inteval */
  73 #define I40E_CHK_Q_ENA_COUNT       1000
  74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  75
  76 /* Maximun number of VSI */
  77 #define I40E_MAX_NUM_VSIS          (384UL)
  78
  79 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  80
  81 /* Flow control default timer */
  82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  83
  84 /* Flow control default high water */
  85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  86
  87 /* Flow control default low water */
  88 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Receive Average Packet Size in Byte*/
 100 #define I40E_PACKET_AVERAGE_SIZE 128
 101
 102 /* Mask of PF interrupt causes */
 103 #define I40E_PFINT_ICR0_ENA_MASK ( \
 104                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 105                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 106                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 107                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 108                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 110                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 114
 115 #define I40E_FLOW_TYPES ( \
 116         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 127
 128 /* Additional timesync values. */
 129 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 130 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 131 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 132 #define I40E_PRTTSYN_TSYNENA     0x80000000
 133 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 134 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 135
 136 #define I40E_MAX_PERCENT            100
 137 #define I40E_DEFAULT_DCB_APP_NUM    1
 138 #define I40E_DEFAULT_DCB_APP_PRIO   3
 139
 140 #define I40E_PRTQF_FD_INSET(_i, _j)  (0x00250000 + ((_i) * 64 + (_j) * 32))
 141 #define I40E_GLQF_FD_MSK(_i, _j)     (0x00267200 + ((_i) * 4 + (_j) * 8))
 142 #define I40E_GLQF_FD_MSK_FIELD       0x0000FFFF
 143 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))
 144 #define I40E_GLQF_HASH_MSK(_i, _j)   (0x00267A00 + ((_i) * 4 + (_j) * 8))
 145 #define I40E_GLQF_HASH_MSK_FIELD      0x0000FFFF
 146
 147 #define I40E_INSET_NONE            0x00000000000000000ULL
 148
 149 /* bit0 ~ bit 7 */
 150 #define I40E_INSET_DMAC            0x0000000000000001ULL
 151 #define I40E_INSET_SMAC            0x0000000000000002ULL
 152 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 153 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 154 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 155
 156 /* bit 8 ~ bit 15 */
 157 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 158 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 159 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 160 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 161 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 162 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 163 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 164
 165 /* bit 16 ~ bit 31 */
 166 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 167 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 168 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 169 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 170 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 171 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 172 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 173 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 174
 175 /* bit 32 ~ bit 47, tunnel fields */
 176 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 177 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 178 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 179 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 180 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 181 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 182
 183 /* bit 48 ~ bit 55 */
 184 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 185
 186 /* bit 56 ~ bit 63, Flex Payload */
 187 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 191 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 192 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 193 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 194 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 195 #define I40E_INSET_FLEX_PAYLOAD \
 196         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 197         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 198         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 199         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 200
 201 /**
 202  * Below are values for writing un-exposed registers suggested
 203  * by silicon experts
 204  */
 205 /* Destination MAC address */
 206 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 207 /* Source MAC address */
 208 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 209 /* VLAN tag in the outer L2 header */
 210 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0080000000000000ULL
 211 /* VLAN tag in the inner L2 header */
 212 #define I40E_REG_INSET_L2_INNER_VLAN             0x0100000000000000ULL
 213 /* Source IPv4 address */
 214 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 215 /* Destination IPv4 address */
 216 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 217 /* IPv4 Type of Service (TOS) */
 218 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 219 /* IPv4 Protocol */
 220 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 221 /* Source IPv6 address */
 222 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 223 /* Destination IPv6 address */
 224 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 225 /* IPv6 Traffic Class (TC) */
 226 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 227 /* IPv6 Next Header */
 228 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 229 /* Source L4 port */
 230 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 231 /* Destination L4 port */
 232 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 233 /* SCTP verification tag */
 234 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 235 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 236 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 237 /* Source port of tunneling UDP */
 238 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 239 /* Destination port of tunneling UDP */
 240 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 241 /* UDP Tunneling ID, NVGRE/GRE key */
 242 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 243 /* Last ether type */
 244 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 245 /* Tunneling outer destination IPv4 address */
 246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 247 /* Tunneling outer destination IPv6 address */
 248 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 249 /* 1st word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 251 /* 2nd word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 253 /* 3rd word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 255 /* 4th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 257 /* 5th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 259 /* 6th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 261 /* 7th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 263 /* 8th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 265
 266 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 267
 268 #define I40E_TRANSLATE_INSET 0
 269 #define I40E_TRANSLATE_REG   1
 270
 271 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 272 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 273 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 274 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 275
 276 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 277 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 278 static int i40e_dev_configure(struct rte_eth_dev *dev);
 279 static int i40e_dev_start(struct rte_eth_dev *dev);
 280 static void i40e_dev_stop(struct rte_eth_dev *dev);
 281 static void i40e_dev_close(struct rte_eth_dev *dev);
 282 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 283 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 284 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 285 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 286 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 287 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 288 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 289                                struct rte_eth_stats *stats);
 290 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 291                                struct rte_eth_xstats *xstats, unsigned n);
 292 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 293 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 294                                             uint16_t queue_id,
 295                                             uint8_t stat_idx,
 296                                             uint8_t is_rx);
 297 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 298                               struct rte_eth_dev_info *dev_info);
 299 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 300                                 uint16_t vlan_id,
 301                                 int on);
 302 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 303 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 304 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 305                                       uint16_t queue,
 306                                       int on);
 307 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 308 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 309 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 310 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 311                               struct rte_eth_fc_conf *fc_conf);
 312 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 313                               struct rte_eth_fc_conf *fc_conf);
 314 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 315                                        struct rte_eth_pfc_conf *pfc_conf);
 316 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 317                           struct ether_addr *mac_addr,
 318                           uint32_t index,
 319                           uint32_t pool);
 320 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 321 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 322                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 323                                     uint16_t reta_size);
 324 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 325                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 326                                    uint16_t reta_size);
 327
 328 static int i40e_get_cap(struct i40e_hw *hw);
 329 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 330 static int i40e_pf_setup(struct i40e_pf *pf);
 331 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 332 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 333 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 334 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 335 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 336                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 337 static void i40e_stat_update_48(struct i40e_hw *hw,
 338                                uint32_t hireg,
 339                                uint32_t loreg,
 340                                bool offset_loaded,
 341                                uint64_t *offset,
 342                                uint64_t *stat);
 343 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 344 static void i40e_dev_interrupt_handler(
 345                 __rte_unused struct rte_intr_handle *handle, void *param);
 346 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 347                                 uint32_t base, uint32_t num);
 348 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 349 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 350                         uint32_t base);
 351 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 352                         uint16_t num);
 353 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 354 static int i40e_veb_release(struct i40e_veb *veb);
 355 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 356                                                 struct i40e_vsi *vsi);
 357 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 358 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 359 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 360                                              struct i40e_macvlan_filter *mv_f,
 361                                              int num,
 362                                              struct ether_addr *addr);
 363 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 364                                              struct i40e_macvlan_filter *mv_f,
 365                                              int num,
 366                                              uint16_t vlan);
 367 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 368 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 369                                     struct rte_eth_rss_conf *rss_conf);
 370 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 371                                       struct rte_eth_rss_conf *rss_conf);
 372 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 373                                 struct rte_eth_udp_tunnel *udp_tunnel);
 374 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 375                                 struct rte_eth_udp_tunnel *udp_tunnel);
 376 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 377                         struct rte_eth_ethertype_filter *filter,
 378                         bool add);
 379 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 380                                 enum rte_filter_op filter_op,
 381                                 void *arg);
 382 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 383                                 enum rte_filter_type filter_type,
 384                                 enum rte_filter_op filter_op,
 385                                 void *arg);
 386 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 387                                   struct rte_eth_dcb_info *dcb_info);
 388 static void i40e_configure_registers(struct i40e_hw *hw);
 389 static void i40e_hw_init(struct i40e_hw *hw);
 390 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 391 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 392                         struct rte_eth_mirror_conf *mirror_conf,
 393                         uint8_t sw_id, uint8_t on);
 394 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 395
 396 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 397 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 398 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 399                                            struct timespec *timestamp,
 400                                            uint32_t flags);
 401 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 402                                            struct timespec *timestamp);
 403 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 404
 405 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 406
 407 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 408                                    struct timespec *timestamp);
 409 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 410                                     const struct timespec *timestamp);
 411
 412 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 413                                          uint16_t queue_id);
 414 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 415                                           uint16_t queue_id);
 416
 417
 418 static const struct rte_pci_id pci_id_i40e_map[] = {
 419 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 420 #include "rte_pci_dev_ids.h"
 421 { .vendor_id = 0, /* sentinel */ },
 422 };
 423
 424 static const struct eth_dev_ops i40e_eth_dev_ops = {
 425         .dev_configure                = i40e_dev_configure,
 426         .dev_start                    = i40e_dev_start,
 427         .dev_stop                     = i40e_dev_stop,
 428         .dev_close                    = i40e_dev_close,
 429         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 430         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 431         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 432         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 433         .dev_set_link_up              = i40e_dev_set_link_up,
 434         .dev_set_link_down            = i40e_dev_set_link_down,
 435         .link_update                  = i40e_dev_link_update,
 436         .stats_get                    = i40e_dev_stats_get,
 437         .xstats_get                   = i40e_dev_xstats_get,
 438         .stats_reset                  = i40e_dev_stats_reset,
 439         .xstats_reset                 = i40e_dev_stats_reset,
 440         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 441         .dev_infos_get                = i40e_dev_info_get,
 442         .vlan_filter_set              = i40e_vlan_filter_set,
 443         .vlan_tpid_set                = i40e_vlan_tpid_set,
 444         .vlan_offload_set             = i40e_vlan_offload_set,
 445         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 446         .vlan_pvid_set                = i40e_vlan_pvid_set,
 447         .rx_queue_start               = i40e_dev_rx_queue_start,
 448         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 449         .tx_queue_start               = i40e_dev_tx_queue_start,
 450         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 451         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 452         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 453         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 454         .rx_queue_release             = i40e_dev_rx_queue_release,
 455         .rx_queue_count               = i40e_dev_rx_queue_count,
 456         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 457         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 458         .tx_queue_release             = i40e_dev_tx_queue_release,
 459         .dev_led_on                   = i40e_dev_led_on,
 460         .dev_led_off                  = i40e_dev_led_off,
 461         .flow_ctrl_get                = i40e_flow_ctrl_get,
 462         .flow_ctrl_set                = i40e_flow_ctrl_set,
 463         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 464         .mac_addr_add                 = i40e_macaddr_add,
 465         .mac_addr_remove              = i40e_macaddr_remove,
 466         .reta_update                  = i40e_dev_rss_reta_update,
 467         .reta_query                   = i40e_dev_rss_reta_query,
 468         .rss_hash_update              = i40e_dev_rss_hash_update,
 469         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 470         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 471         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 472         .filter_ctrl                  = i40e_dev_filter_ctrl,
 473         .rxq_info_get                 = i40e_rxq_info_get,
 474         .txq_info_get                 = i40e_txq_info_get,
 475         .mirror_rule_set              = i40e_mirror_rule_set,
 476         .mirror_rule_reset            = i40e_mirror_rule_reset,
 477         .timesync_enable              = i40e_timesync_enable,
 478         .timesync_disable             = i40e_timesync_disable,
 479         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 480         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 481         .get_dcb_info                 = i40e_dev_get_dcb_info,
 482         .timesync_adjust_time         = i40e_timesync_adjust_time,
 483         .timesync_read_time           = i40e_timesync_read_time,
 484         .timesync_write_time          = i40e_timesync_write_time,
 485 };
 486
 487 /* store statistics names and its offset in stats structure */
 488 struct rte_i40e_xstats_name_off {
 489         char name[RTE_ETH_XSTATS_NAME_SIZE];
 490         unsigned offset;
 491 };
 492
 493 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 494         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 495         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 496         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 497         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 498         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 499                 rx_unknown_protocol)},
 500         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 501         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 502         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 503         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 504 };
 505
 506 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 507                 sizeof(rte_i40e_stats_strings[0]))
 508
 509 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 510         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 511                 tx_dropped_link_down)},
 512         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 513         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 514                 illegal_bytes)},
 515         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 516         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 517                 mac_local_faults)},
 518         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 519                 mac_remote_faults)},
 520         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 521                 rx_length_errors)},
 522         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 523         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 524         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 525         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 526         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 527         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 528                 rx_size_127)},
 529         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 530                 rx_size_255)},
 531         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 532                 rx_size_511)},
 533         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 534                 rx_size_1023)},
 535         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 536                 rx_size_1522)},
 537         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 538                 rx_size_big)},
 539         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 540                 rx_undersize)},
 541         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 542                 rx_oversize)},
 543         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 544                 mac_short_packet_dropped)},
 545         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 546                 rx_fragments)},
 547         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 548         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 549         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 550                 tx_size_127)},
 551         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 552                 tx_size_255)},
 553         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 554                 tx_size_511)},
 555         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 556                 tx_size_1023)},
 557         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 558                 tx_size_1522)},
 559         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 560                 tx_size_big)},
 561         {"rx_flow_director_atr_match_packets",
 562                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 563         {"rx_flow_director_sb_match_packets",
 564                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 565         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 566                 tx_lpi_status)},
 567         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 568                 rx_lpi_status)},
 569         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 570                 tx_lpi_count)},
 571         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 572                 rx_lpi_count)},
 573 };
 574
 575 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 576                 sizeof(rte_i40e_hw_port_strings[0]))
 577
 578 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 579         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 580                 priority_xon_rx)},
 581         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 582                 priority_xoff_rx)},
 583 };
 584
 585 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 586                 sizeof(rte_i40e_rxq_prio_strings[0]))
 587
 588 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 589         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 590                 priority_xon_tx)},
 591         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 592                 priority_xoff_tx)},
 593         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 594                 priority_xon_2_xoff)},
 595 };
 596
 597 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 598                 sizeof(rte_i40e_txq_prio_strings[0]))
 599
 600 static struct eth_driver rte_i40e_pmd = {
 601         .pci_drv = {
 602                 .name = "rte_i40e_pmd",
 603                 .id_table = pci_id_i40e_map,
 604                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 605                         RTE_PCI_DRV_DETACHABLE,
 606         },
 607         .eth_dev_init = eth_i40e_dev_init,
 608         .eth_dev_uninit = eth_i40e_dev_uninit,
 609         .dev_private_size = sizeof(struct i40e_adapter),
 610 };
 611
 612 static inline int
 613 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 614                                      struct rte_eth_link *link)
 615 {
 616         struct rte_eth_link *dst = link;
 617         struct rte_eth_link *src = &(dev->data->dev_link);
 618
 619         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 620                                         *(uint64_t *)src) == 0)
 621                 return -1;
 622
 623         return 0;
 624 }
 625
 626 static inline int
 627 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 628                                       struct rte_eth_link *link)
 629 {
 630         struct rte_eth_link *dst = &(dev->data->dev_link);
 631         struct rte_eth_link *src = link;
 632
 633         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 634                                         *(uint64_t *)src) == 0)
 635                 return -1;
 636
 637         return 0;
 638 }
 639
 640 /*
 641  * Driver initialization routine.
 642  * Invoked once at EAL init time.
 643  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 644  */
 645 static int
 646 rte_i40e_pmd_init(const char *name __rte_unused,
 647                   const char *params __rte_unused)
 648 {
 649         PMD_INIT_FUNC_TRACE();
 650         rte_eth_driver_register(&rte_i40e_pmd);
 651
 652         return 0;
 653 }
 654
 655 static struct rte_driver rte_i40e_driver = {
 656         .type = PMD_PDEV,
 657         .init = rte_i40e_pmd_init,
 658 };
 659
 660 PMD_REGISTER_DRIVER(rte_i40e_driver);
 661
 662 /*
 663  * Initialize registers for flexible payload, which should be set by NVM.
 664  * This should be removed from code once it is fixed in NVM.
 665  */
 666 #ifndef I40E_GLQF_ORT
 667 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 668 #endif
 669 #ifndef I40E_GLQF_PIT
 670 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 671 #endif
 672
 673 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 674 {
 675         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 676         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 677         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 678         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 679         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 680         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 681         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 682         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 683         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 684         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 685
 686         /* GLQF_PIT Registers */
 687         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 688         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 689 }
 690
 691 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 692
 693 /*
 694  * Add a ethertype filter to drop all flow control frames transmitted
 695  * from VSIs.
 696 */
 697 static void
 698 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 699 {
 700         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 701         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 702                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 703                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 704         int ret;
 705
 706         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 707                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 708                                 pf->main_vsi_seid, 0,
 709                                 TRUE, NULL, NULL);
 710         if (ret)
 711                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 712                                   " frames from VSIs.");
 713 }
 714
 715 static int
 716 eth_i40e_dev_init(struct rte_eth_dev *dev)
 717 {
 718         struct rte_pci_device *pci_dev;
 719         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 720         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 721         struct i40e_vsi *vsi;
 722         int ret;
 723         uint32_t len;
 724         uint8_t aq_fail = 0;
 725
 726         PMD_INIT_FUNC_TRACE();
 727
 728         dev->dev_ops = &i40e_eth_dev_ops;
 729         dev->rx_pkt_burst = i40e_recv_pkts;
 730         dev->tx_pkt_burst = i40e_xmit_pkts;
 731
 732         /* for secondary processes, we don't initialise any further as primary
 733          * has already done this work. Only check we don't need a different
 734          * RX function */
 735         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 736                 i40e_set_rx_function(dev);
 737                 i40e_set_tx_function(dev);
 738                 return 0;
 739         }
 740         pci_dev = dev->pci_dev;
 741
 742         rte_eth_copy_pci_info(dev, pci_dev);
 743
 744         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 745         pf->adapter->eth_dev = dev;
 746         pf->dev_data = dev->data;
 747
 748         hw->back = I40E_PF_TO_ADAPTER(pf);
 749         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 750         if (!hw->hw_addr) {
 751                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 752                              "as address is NULL");
 753                 return -ENODEV;
 754         }
 755
 756         hw->vendor_id = pci_dev->id.vendor_id;
 757         hw->device_id = pci_dev->id.device_id;
 758         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 759         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 760         hw->bus.device = pci_dev->addr.devid;
 761         hw->bus.func = pci_dev->addr.function;
 762         hw->adapter_stopped = 0;
 763
 764         /* Make sure all is clean before doing PF reset */
 765         i40e_clear_hw(hw);
 766
 767         /* Initialize the hardware */
 768         i40e_hw_init(hw);
 769
 770         /* Reset here to make sure all is clean for each PF */
 771         ret = i40e_pf_reset(hw);
 772         if (ret) {
 773                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 774                 return ret;
 775         }
 776
 777         /* Initialize the shared code (base driver) */
 778         ret = i40e_init_shared_code(hw);
 779         if (ret) {
 780                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 781                 return ret;
 782         }
 783
 784         /*
 785          * To work around the NVM issue,initialize registers
 786          * for flexible payload by software.
 787          * It should be removed once issues are fixed in NVM.
 788          */
 789         i40e_flex_payload_reg_init(hw);
 790
 791         /* Initialize the parameters for adminq */
 792         i40e_init_adminq_parameter(hw);
 793         ret = i40e_init_adminq(hw);
 794         if (ret != I40E_SUCCESS) {
 795                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 796                 return -EIO;
 797         }
 798         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 799                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 800                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 801                      ((hw->nvm.version >> 12) & 0xf),
 802                      ((hw->nvm.version >> 4) & 0xff),
 803                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 804
 805         /* Clear PXE mode */
 806         i40e_clear_pxe_mode(hw);
 807
 808         /*
 809          * On X710, performance number is far from the expectation on recent
 810          * firmware versions. The fix for this issue may not be integrated in
 811          * the following firmware version. So the workaround in software driver
 812          * is needed. It needs to modify the initial values of 3 internal only
 813          * registers. Note that the workaround can be removed when it is fixed
 814          * in firmware in the future.
 815          */
 816         i40e_configure_registers(hw);
 817
 818         /* Get hw capabilities */
 819         ret = i40e_get_cap(hw);
 820         if (ret != I40E_SUCCESS) {
 821                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 822                 goto err_get_capabilities;
 823         }
 824
 825         /* Initialize parameters for PF */
 826         ret = i40e_pf_parameter_init(dev);
 827         if (ret != 0) {
 828                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 829                 goto err_parameter_init;
 830         }
 831
 832         /* Initialize the queue management */
 833         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 834         if (ret < 0) {
 835                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 836                 goto err_qp_pool_init;
 837         }
 838         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 839                                 hw->func_caps.num_msix_vectors - 1);
 840         if (ret < 0) {
 841                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 842                 goto err_msix_pool_init;
 843         }
 844
 845         /* Initialize lan hmc */
 846         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 847                                 hw->func_caps.num_rx_qp, 0, 0);
 848         if (ret != I40E_SUCCESS) {
 849                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 850                 goto err_init_lan_hmc;
 851         }
 852
 853         /* Configure lan hmc */
 854         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 855         if (ret != I40E_SUCCESS) {
 856                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 857                 goto err_configure_lan_hmc;
 858         }
 859
 860         /* Get and check the mac address */
 861         i40e_get_mac_addr(hw, hw->mac.addr);
 862         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 863                 PMD_INIT_LOG(ERR, "mac address is not valid");
 864                 ret = -EIO;
 865                 goto err_get_mac_addr;
 866         }
 867         /* Copy the permanent MAC address */
 868         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 869                         (struct ether_addr *) hw->mac.perm_addr);
 870
 871         /* Disable flow control */
 872         hw->fc.requested_mode = I40E_FC_NONE;
 873         i40e_set_fc(hw, &aq_fail, TRUE);
 874
 875         /* PF setup, which includes VSI setup */
 876         ret = i40e_pf_setup(pf);
 877         if (ret) {
 878                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 879                 goto err_setup_pf_switch;
 880         }
 881
 882         vsi = pf->main_vsi;
 883
 884         /* Disable double vlan by default */
 885         i40e_vsi_config_double_vlan(vsi, FALSE);
 886
 887         if (!vsi->max_macaddrs)
 888                 len = ETHER_ADDR_LEN;
 889         else
 890                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 891
 892         /* Should be after VSI initialized */
 893         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 894         if (!dev->data->mac_addrs) {
 895                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 896                                         "for storing mac address");
 897                 goto err_mac_alloc;
 898         }
 899         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 900                                         &dev->data->mac_addrs[0]);
 901
 902         /* initialize pf host driver to setup SRIOV resource if applicable */
 903         i40e_pf_host_init(dev);
 904
 905         /* register callback func to eal lib */
 906         rte_intr_callback_register(&(pci_dev->intr_handle),
 907                 i40e_dev_interrupt_handler, (void *)dev);
 908
 909         /* configure and enable device interrupt */
 910         i40e_pf_config_irq0(hw, TRUE);
 911         i40e_pf_enable_irq0(hw);
 912
 913         /* enable uio intr after callback register */
 914         rte_intr_enable(&(pci_dev->intr_handle));
 915         /*
 916          * Add an ethertype filter to drop all flow control frames transmitted
 917          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 918          * frames to wire.
 919          */
 920         i40e_add_tx_flow_control_drop_filter(pf);
 921
 922         /* Set the max frame size to 0x2600 by default,
 923          * in case other drivers changed the default value.
 924          */
 925         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
 926
 927         /* initialize mirror rule list */
 928         TAILQ_INIT(&pf->mirror_list);
 929
 930         /* Init dcb to sw mode by default */
 931         ret = i40e_dcb_init_configure(dev, TRUE);
 932         if (ret != I40E_SUCCESS) {
 933                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 934                 pf->flags &= ~I40E_FLAG_DCB;
 935         }
 936
 937         return 0;
 938
 939 err_mac_alloc:
 940         i40e_vsi_release(pf->main_vsi);
 941 err_setup_pf_switch:
 942 err_get_mac_addr:
 943 err_configure_lan_hmc:
 944         (void)i40e_shutdown_lan_hmc(hw);
 945 err_init_lan_hmc:
 946         i40e_res_pool_destroy(&pf->msix_pool);
 947 err_msix_pool_init:
 948         i40e_res_pool_destroy(&pf->qp_pool);
 949 err_qp_pool_init:
 950 err_parameter_init:
 951 err_get_capabilities:
 952         (void)i40e_shutdown_adminq(hw);
 953
 954         return ret;
 955 }
 956
 957 static int
 958 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 959 {
 960         struct rte_pci_device *pci_dev;
 961         struct i40e_hw *hw;
 962         struct i40e_filter_control_settings settings;
 963         int ret;
 964         uint8_t aq_fail = 0;
 965
 966         PMD_INIT_FUNC_TRACE();
 967
 968         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 969                 return 0;
 970
 971         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 972         pci_dev = dev->pci_dev;
 973
 974         if (hw->adapter_stopped == 0)
 975                 i40e_dev_close(dev);
 976
 977         dev->dev_ops = NULL;
 978         dev->rx_pkt_burst = NULL;
 979         dev->tx_pkt_burst = NULL;
 980
 981         /* Disable LLDP */
 982         ret = i40e_aq_stop_lldp(hw, true, NULL);
 983         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 984                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 985
 986         /* Clear PXE mode */
 987         i40e_clear_pxe_mode(hw);
 988
 989         /* Unconfigure filter control */
 990         memset(&settings, 0, sizeof(settings));
 991         ret = i40e_set_filter_control(hw, &settings);
 992         if (ret)
 993                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 994                                         ret);
 995
 996         /* Disable flow control */
 997         hw->fc.requested_mode = I40E_FC_NONE;
 998         i40e_set_fc(hw, &aq_fail, TRUE);
 999
1000         /* uninitialize pf host driver */
1001         i40e_pf_host_uninit(dev);
1002
1003         rte_free(dev->data->mac_addrs);
1004         dev->data->mac_addrs = NULL;
1005
1006         /* disable uio intr before callback unregister */
1007         rte_intr_disable(&(pci_dev->intr_handle));
1008
1009         /* register callback func to eal lib */
1010         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1011                 i40e_dev_interrupt_handler, (void *)dev);
1012
1013         return 0;
1014 }
1015
1016 static int
1017 i40e_dev_configure(struct rte_eth_dev *dev)
1018 {
1019         struct i40e_adapter *ad =
1020                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1021         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1022         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1023         int i, ret;
1024
1025         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1026          * bulk allocation or vector Rx preconditions we will reset it.
1027          */
1028         ad->rx_bulk_alloc_allowed = true;
1029         ad->rx_vec_allowed = true;
1030         ad->tx_simple_allowed = true;
1031         ad->tx_vec_allowed = true;
1032
1033         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1034                 ret = i40e_fdir_setup(pf);
1035                 if (ret != I40E_SUCCESS) {
1036                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1037                         return -ENOTSUP;
1038                 }
1039                 ret = i40e_fdir_configure(dev);
1040                 if (ret < 0) {
1041                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1042                         goto err;
1043                 }
1044         } else
1045                 i40e_fdir_teardown(pf);
1046
1047         ret = i40e_dev_init_vlan(dev);
1048         if (ret < 0)
1049                 goto err;
1050
1051         /* VMDQ setup.
1052          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1053          *  RSS setting have different requirements.
1054          *  General PMD driver call sequence are NIC init, configure,
1055          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1056          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1057          *  applicable. So, VMDQ setting has to be done before
1058          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1059          *  For RSS setting, it will try to calculate actual configured RX queue
1060          *  number, which will be available after rx_queue_setup(). dev_start()
1061          *  function is good to place RSS setup.
1062          */
1063         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1064                 ret = i40e_vmdq_setup(dev);
1065                 if (ret)
1066                         goto err;
1067         }
1068
1069         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1070                 ret = i40e_dcb_setup(dev);
1071                 if (ret) {
1072                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1073                         goto err_dcb;
1074                 }
1075         }
1076
1077         return 0;
1078
1079 err_dcb:
1080         /* need to release vmdq resource if exists */
1081         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1082                 i40e_vsi_release(pf->vmdq[i].vsi);
1083                 pf->vmdq[i].vsi = NULL;
1084         }
1085         rte_free(pf->vmdq);
1086         pf->vmdq = NULL;
1087 err:
1088         /* need to release fdir resource if exists */
1089         i40e_fdir_teardown(pf);
1090         return ret;
1091 }
1092
1093 void
1094 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1095 {
1096         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1097         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1098         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1099         uint16_t msix_vect = vsi->msix_intr;
1100         uint16_t i;
1101
1102         for (i = 0; i < vsi->nb_qps; i++) {
1103                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1104                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1105                 rte_wmb();
1106         }
1107
1108         if (vsi->type != I40E_VSI_SRIOV) {
1109                 if (!rte_intr_allow_others(intr_handle)) {
1110                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1111                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1112                         I40E_WRITE_REG(hw,
1113                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1114                                        0);
1115                 } else {
1116                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1117                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1118                         I40E_WRITE_REG(hw,
1119                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1120                                                        msix_vect - 1), 0);
1121                 }
1122         } else {
1123                 uint32_t reg;
1124                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1125                         vsi->user_param + (msix_vect - 1);
1126
1127                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1128                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1129         }
1130         I40E_WRITE_FLUSH(hw);
1131 }
1132
1133 static void
1134 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1135                        int base_queue, int nb_queue)
1136 {
1137         int i;
1138         uint32_t val;
1139         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1140
1141         /* Bind all RX queues to allocated MSIX interrupt */
1142         for (i = 0; i < nb_queue; i++) {
1143                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1144                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1145                         ((base_queue + i + 1) <<
1146                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1147                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1148                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1149
1150                 if (i == nb_queue - 1)
1151                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1152                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1153         }
1154
1155         /* Write first RX queue to Link list register as the head element */
1156         if (vsi->type != I40E_VSI_SRIOV) {
1157                 uint16_t interval =
1158                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1159
1160                 if (msix_vect == I40E_MISC_VEC_ID) {
1161                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1162                                        (base_queue <<
1163                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1164                                        (0x0 <<
1165                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1166                         I40E_WRITE_REG(hw,
1167                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1168                                        interval);
1169                 } else {
1170                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1171                                        (base_queue <<
1172                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1173                                        (0x0 <<
1174                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1175                         I40E_WRITE_REG(hw,
1176                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1177                                                        msix_vect - 1),
1178                                        interval);
1179                 }
1180         } else {
1181                 uint32_t reg;
1182
1183                 if (msix_vect == I40E_MISC_VEC_ID) {
1184                         I40E_WRITE_REG(hw,
1185                                        I40E_VPINT_LNKLST0(vsi->user_param),
1186                                        (base_queue <<
1187                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1188                                        (0x0 <<
1189                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1190                 } else {
1191                         /* num_msix_vectors_vf needs to minus irq0 */
1192                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1193                                 vsi->user_param + (msix_vect - 1);
1194
1195                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1196                                        (base_queue <<
1197                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1198                                        (0x0 <<
1199                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1200                 }
1201         }
1202
1203         I40E_WRITE_FLUSH(hw);
1204 }
1205
1206 void
1207 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1208 {
1209         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1210         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1211         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1212         uint16_t msix_vect = vsi->msix_intr;
1213         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1214         uint16_t queue_idx = 0;
1215         int record = 0;
1216         uint32_t val;
1217         int i;
1218
1219         for (i = 0; i < vsi->nb_qps; i++) {
1220                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1221                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1222         }
1223
1224         /* INTENA flag is not auto-cleared for interrupt */
1225         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1226         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1227                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1228                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1229         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1230
1231         /* VF bind interrupt */
1232         if (vsi->type == I40E_VSI_SRIOV) {
1233                 __vsi_queues_bind_intr(vsi, msix_vect,
1234                                        vsi->base_queue, vsi->nb_qps);
1235                 return;
1236         }
1237
1238         /* PF & VMDq bind interrupt */
1239         if (rte_intr_dp_is_en(intr_handle)) {
1240                 if (vsi->type == I40E_VSI_MAIN) {
1241                         queue_idx = 0;
1242                         record = 1;
1243                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1244                         struct i40e_vsi *main_vsi =
1245                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1246                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1247                         record = 1;
1248                 }
1249         }
1250
1251         for (i = 0; i < vsi->nb_used_qps; i++) {
1252                 if (nb_msix <= 1) {
1253                         if (!rte_intr_allow_others(intr_handle))
1254                                 /* allow to share MISC_VEC_ID */
1255                                 msix_vect = I40E_MISC_VEC_ID;
1256
1257                         /* no enough msix_vect, map all to one */
1258                         __vsi_queues_bind_intr(vsi, msix_vect,
1259                                                vsi->base_queue + i,
1260                                                vsi->nb_used_qps - i);
1261                         for (; !!record && i < vsi->nb_used_qps; i++)
1262                                 intr_handle->intr_vec[queue_idx + i] =
1263                                         msix_vect;
1264                         break;
1265                 }
1266                 /* 1:1 queue/msix_vect mapping */
1267                 __vsi_queues_bind_intr(vsi, msix_vect,
1268                                        vsi->base_queue + i, 1);
1269                 if (!!record)
1270                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1271
1272                 msix_vect++;
1273                 nb_msix--;
1274         }
1275 }
1276
1277 static void
1278 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1279 {
1280         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1281         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1282         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1283         uint16_t interval = i40e_calc_itr_interval(\
1284                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1285         uint16_t msix_intr, i;
1286
1287         if (rte_intr_allow_others(intr_handle))
1288                 for (i = 0; i < vsi->nb_msix; i++) {
1289                         msix_intr = vsi->msix_intr + i;
1290                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1291                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1292                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1293                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1294                                 (interval <<
1295                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1296                 }
1297         else
1298                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1299                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1300                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1301                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1302                                (interval <<
1303                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1304
1305         I40E_WRITE_FLUSH(hw);
1306 }
1307
1308 static void
1309 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1310 {
1311         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1312         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1313         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1314         uint16_t msix_intr, i;
1315
1316         if (rte_intr_allow_others(intr_handle))
1317                 for (i = 0; i < vsi->nb_msix; i++) {
1318                         msix_intr = vsi->msix_intr + i;
1319                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1320                                        0);
1321                 }
1322         else
1323                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1324
1325         I40E_WRITE_FLUSH(hw);
1326 }
1327
1328 static inline uint8_t
1329 i40e_parse_link_speed(uint16_t eth_link_speed)
1330 {
1331         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1332
1333         switch (eth_link_speed) {
1334         case ETH_LINK_SPEED_40G:
1335                 link_speed = I40E_LINK_SPEED_40GB;
1336                 break;
1337         case ETH_LINK_SPEED_20G:
1338                 link_speed = I40E_LINK_SPEED_20GB;
1339                 break;
1340         case ETH_LINK_SPEED_10G:
1341                 link_speed = I40E_LINK_SPEED_10GB;
1342                 break;
1343         case ETH_LINK_SPEED_1000:
1344                 link_speed = I40E_LINK_SPEED_1GB;
1345                 break;
1346         case ETH_LINK_SPEED_100:
1347                 link_speed = I40E_LINK_SPEED_100MB;
1348                 break;
1349         }
1350
1351         return link_speed;
1352 }
1353
1354 static int
1355 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1356                    __rte_unused uint8_t abilities,
1357                    __rte_unused uint8_t force_speed)
1358 {
1359         /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1360          * for the link control limitation of that all link control should be
1361          * handled by firmware. It should follow up if link control will be
1362          * opened to software driver in future firmware versions.
1363          */
1364         return I40E_SUCCESS;
1365 }
1366
1367 static int
1368 i40e_apply_link_speed(struct rte_eth_dev *dev)
1369 {
1370         uint8_t speed;
1371         uint8_t abilities = 0;
1372         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1373         struct rte_eth_conf *conf = &dev->data->dev_conf;
1374
1375         speed = i40e_parse_link_speed(conf->link_speed);
1376         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1377         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1378                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1379         else
1380                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1381
1382         return i40e_phy_conf_link(hw, abilities, speed);
1383 }
1384
1385 static int
1386 i40e_dev_start(struct rte_eth_dev *dev)
1387 {
1388         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1389         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1390         struct i40e_vsi *main_vsi = pf->main_vsi;
1391         int ret, i;
1392         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1393         uint32_t intr_vector = 0;
1394
1395         hw->adapter_stopped = 0;
1396
1397         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1398                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1399                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1400                              dev->data->dev_conf.link_duplex,
1401                              dev->data->port_id);
1402                 return -EINVAL;
1403         }
1404
1405         rte_intr_disable(intr_handle);
1406
1407         if ((rte_intr_cap_multiple(intr_handle) ||
1408              !RTE_ETH_DEV_SRIOV(dev).active) &&
1409             dev->data->dev_conf.intr_conf.rxq != 0) {
1410                 intr_vector = dev->data->nb_rx_queues;
1411                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1412                         return -1;
1413         }
1414
1415         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1416                 intr_handle->intr_vec =
1417                         rte_zmalloc("intr_vec",
1418                                     dev->data->nb_rx_queues * sizeof(int),
1419                                     0);
1420                 if (!intr_handle->intr_vec) {
1421                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1422                                      " intr_vec\n", dev->data->nb_rx_queues);
1423                         return -ENOMEM;
1424                 }
1425         }
1426
1427         /* Initialize VSI */
1428         ret = i40e_dev_rxtx_init(pf);
1429         if (ret != I40E_SUCCESS) {
1430                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1431                 goto err_up;
1432         }
1433
1434         /* Map queues with MSIX interrupt */
1435         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1436                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1437         i40e_vsi_queues_bind_intr(main_vsi);
1438         i40e_vsi_enable_queues_intr(main_vsi);
1439
1440         /* Map VMDQ VSI queues with MSIX interrupt */
1441         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1442                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1443                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1444                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1445         }
1446
1447         /* enable FDIR MSIX interrupt */
1448         if (pf->fdir.fdir_vsi) {
1449                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1450                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1451         }
1452
1453         /* Enable all queues which have been configured */
1454         ret = i40e_dev_switch_queues(pf, TRUE);
1455         if (ret != I40E_SUCCESS) {
1456                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1457                 goto err_up;
1458         }
1459
1460         /* Enable receiving broadcast packets */
1461         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1462         if (ret != I40E_SUCCESS)
1463                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1464
1465         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1466                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1467                                                 true, NULL);
1468                 if (ret != I40E_SUCCESS)
1469                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1470         }
1471
1472         /* Apply link configure */
1473         ret = i40e_apply_link_speed(dev);
1474         if (I40E_SUCCESS != ret) {
1475                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1476                 goto err_up;
1477         }
1478
1479         if (!rte_intr_allow_others(intr_handle)) {
1480                 rte_intr_callback_unregister(intr_handle,
1481                                              i40e_dev_interrupt_handler,
1482                                              (void *)dev);
1483                 /* configure and enable device interrupt */
1484                 i40e_pf_config_irq0(hw, FALSE);
1485                 i40e_pf_enable_irq0(hw);
1486
1487                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1488                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1489                                      " no intr multiplex\n");
1490         }
1491
1492         /* enable uio intr after callback register */
1493         rte_intr_enable(intr_handle);
1494
1495         return I40E_SUCCESS;
1496
1497 err_up:
1498         i40e_dev_switch_queues(pf, FALSE);
1499         i40e_dev_clear_queues(dev);
1500
1501         return ret;
1502 }
1503
1504 static void
1505 i40e_dev_stop(struct rte_eth_dev *dev)
1506 {
1507         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1508         struct i40e_vsi *main_vsi = pf->main_vsi;
1509         struct i40e_mirror_rule *p_mirror;
1510         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1511         int i;
1512
1513         /* Disable all queues */
1514         i40e_dev_switch_queues(pf, FALSE);
1515
1516         /* un-map queues with interrupt registers */
1517         i40e_vsi_disable_queues_intr(main_vsi);
1518         i40e_vsi_queues_unbind_intr(main_vsi);
1519
1520         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1521                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1522                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1523         }
1524
1525         if (pf->fdir.fdir_vsi) {
1526                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1527                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1528         }
1529         /* Clear all queues and release memory */
1530         i40e_dev_clear_queues(dev);
1531
1532         /* Set link down */
1533         i40e_dev_set_link_down(dev);
1534
1535         /* Remove all mirror rules */
1536         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1537                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1538                 rte_free(p_mirror);
1539         }
1540         pf->nb_mirror_rule = 0;
1541
1542         if (!rte_intr_allow_others(intr_handle))
1543                 /* resume to the default handler */
1544                 rte_intr_callback_register(intr_handle,
1545                                            i40e_dev_interrupt_handler,
1546                                            (void *)dev);
1547
1548         /* Clean datapath event and queue/vec mapping */
1549         rte_intr_efd_disable(intr_handle);
1550         if (intr_handle->intr_vec) {
1551                 rte_free(intr_handle->intr_vec);
1552                 intr_handle->intr_vec = NULL;
1553         }
1554 }
1555
1556 static void
1557 i40e_dev_close(struct rte_eth_dev *dev)
1558 {
1559         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1560         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1561         uint32_t reg;
1562         int i;
1563
1564         PMD_INIT_FUNC_TRACE();
1565
1566         i40e_dev_stop(dev);
1567         hw->adapter_stopped = 1;
1568         i40e_dev_free_queues(dev);
1569
1570         /* Disable interrupt */
1571         i40e_pf_disable_irq0(hw);
1572         rte_intr_disable(&(dev->pci_dev->intr_handle));
1573
1574         /* shutdown and destroy the HMC */
1575         i40e_shutdown_lan_hmc(hw);
1576
1577         /* release all the existing VSIs and VEBs */
1578         i40e_fdir_teardown(pf);
1579         i40e_vsi_release(pf->main_vsi);
1580
1581         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1582                 i40e_vsi_release(pf->vmdq[i].vsi);
1583                 pf->vmdq[i].vsi = NULL;
1584         }
1585
1586         rte_free(pf->vmdq);
1587         pf->vmdq = NULL;
1588
1589         /* shutdown the adminq */
1590         i40e_aq_queue_shutdown(hw, true);
1591         i40e_shutdown_adminq(hw);
1592
1593         i40e_res_pool_destroy(&pf->qp_pool);
1594         i40e_res_pool_destroy(&pf->msix_pool);
1595
1596         /* force a PF reset to clean anything leftover */
1597         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1598         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1599                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1600         I40E_WRITE_FLUSH(hw);
1601 }
1602
1603 static void
1604 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1605 {
1606         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1607         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1608         struct i40e_vsi *vsi = pf->main_vsi;
1609         int status;
1610
1611         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1612                                                         true, NULL);
1613         if (status != I40E_SUCCESS)
1614                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1615
1616         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1617                                                         TRUE, NULL);
1618         if (status != I40E_SUCCESS)
1619                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1620
1621 }
1622
1623 static void
1624 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1625 {
1626         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1627         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1628         struct i40e_vsi *vsi = pf->main_vsi;
1629         int status;
1630
1631         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1632                                                         false, NULL);
1633         if (status != I40E_SUCCESS)
1634                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1635
1636         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1637                                                         false, NULL);
1638         if (status != I40E_SUCCESS)
1639                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1640 }
1641
1642 static void
1643 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1644 {
1645         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1646         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1647         struct i40e_vsi *vsi = pf->main_vsi;
1648         int ret;
1649
1650         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1651         if (ret != I40E_SUCCESS)
1652                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1653 }
1654
1655 static void
1656 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1657 {
1658         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1659         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1660         struct i40e_vsi *vsi = pf->main_vsi;
1661         int ret;
1662
1663         if (dev->data->promiscuous == 1)
1664                 return; /* must remain in all_multicast mode */
1665
1666         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1667                                 vsi->seid, FALSE, NULL);
1668         if (ret != I40E_SUCCESS)
1669                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1670 }
1671
1672 /*
1673  * Set device link up.
1674  */
1675 static int
1676 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1677 {
1678         /* re-apply link speed setting */
1679         return i40e_apply_link_speed(dev);
1680 }
1681
1682 /*
1683  * Set device link down.
1684  */
1685 static int
1686 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1687 {
1688         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1689         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1690         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1691
1692         return i40e_phy_conf_link(hw, abilities, speed);
1693 }
1694
1695 int
1696 i40e_dev_link_update(struct rte_eth_dev *dev,
1697                      int wait_to_complete)
1698 {
1699 #define CHECK_INTERVAL 100  /* 100ms */
1700 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1701         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1702         struct i40e_link_status link_status;
1703         struct rte_eth_link link, old;
1704         int status;
1705         unsigned rep_cnt = MAX_REPEAT_TIME;
1706
1707         memset(&link, 0, sizeof(link));
1708         memset(&old, 0, sizeof(old));
1709         memset(&link_status, 0, sizeof(link_status));
1710         rte_i40e_dev_atomic_read_link_status(dev, &old);
1711
1712         do {
1713                 /* Get link status information from hardware */
1714                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1715                 if (status != I40E_SUCCESS) {
1716                         link.link_speed = ETH_LINK_SPEED_100;
1717                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1718                         PMD_DRV_LOG(ERR, "Failed to get link info");
1719                         goto out;
1720                 }
1721
1722                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1723                 if (!wait_to_complete)
1724                         break;
1725
1726                 rte_delay_ms(CHECK_INTERVAL);
1727         } while (!link.link_status && rep_cnt--);
1728
1729         if (!link.link_status)
1730                 goto out;
1731
1732         /* i40e uses full duplex only */
1733         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1734
1735         /* Parse the link status */
1736         switch (link_status.link_speed) {
1737         case I40E_LINK_SPEED_100MB:
1738                 link.link_speed = ETH_LINK_SPEED_100;
1739                 break;
1740         case I40E_LINK_SPEED_1GB:
1741                 link.link_speed = ETH_LINK_SPEED_1000;
1742                 break;
1743         case I40E_LINK_SPEED_10GB:
1744                 link.link_speed = ETH_LINK_SPEED_10G;
1745                 break;
1746         case I40E_LINK_SPEED_20GB:
1747                 link.link_speed = ETH_LINK_SPEED_20G;
1748                 break;
1749         case I40E_LINK_SPEED_40GB:
1750                 link.link_speed = ETH_LINK_SPEED_40G;
1751                 break;
1752         default:
1753                 link.link_speed = ETH_LINK_SPEED_100;
1754                 break;
1755         }
1756
1757 out:
1758         rte_i40e_dev_atomic_write_link_status(dev, &link);
1759         if (link.link_status == old.link_status)
1760                 return -1;
1761
1762         return 0;
1763 }
1764
1765 /* Get all the statistics of a VSI */
1766 void
1767 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1768 {
1769         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1770         struct i40e_eth_stats *nes = &vsi->eth_stats;
1771         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1772         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1773
1774         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1775                             vsi->offset_loaded, &oes->rx_bytes,
1776                             &nes->rx_bytes);
1777         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1778                             vsi->offset_loaded, &oes->rx_unicast,
1779                             &nes->rx_unicast);
1780         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1781                             vsi->offset_loaded, &oes->rx_multicast,
1782                             &nes->rx_multicast);
1783         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1784                             vsi->offset_loaded, &oes->rx_broadcast,
1785                             &nes->rx_broadcast);
1786         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1787                             &oes->rx_discards, &nes->rx_discards);
1788         /* GLV_REPC not supported */
1789         /* GLV_RMPC not supported */
1790         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1791                             &oes->rx_unknown_protocol,
1792                             &nes->rx_unknown_protocol);
1793         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1794                             vsi->offset_loaded, &oes->tx_bytes,
1795                             &nes->tx_bytes);
1796         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1797                             vsi->offset_loaded, &oes->tx_unicast,
1798                             &nes->tx_unicast);
1799         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1800                             vsi->offset_loaded, &oes->tx_multicast,
1801                             &nes->tx_multicast);
1802         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1803                             vsi->offset_loaded,  &oes->tx_broadcast,
1804                             &nes->tx_broadcast);
1805         /* GLV_TDPC not supported */
1806         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1807                             &oes->tx_errors, &nes->tx_errors);
1808         vsi->offset_loaded = true;
1809
1810         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1811                     vsi->vsi_id);
1812         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1813         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1814         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1815         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1816         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1817         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1818                     nes->rx_unknown_protocol);
1819         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1820         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1821         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1822         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1823         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1824         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1825         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1826                     vsi->vsi_id);
1827 }
1828
1829 static void
1830 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1831 {
1832         unsigned int i;
1833         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1834         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1835
1836         /* Get statistics of struct i40e_eth_stats */
1837         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1838                             I40E_GLPRT_GORCL(hw->port),
1839                             pf->offset_loaded, &os->eth.rx_bytes,
1840                             &ns->eth.rx_bytes);
1841         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1842                             I40E_GLPRT_UPRCL(hw->port),
1843                             pf->offset_loaded, &os->eth.rx_unicast,
1844                             &ns->eth.rx_unicast);
1845         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1846                             I40E_GLPRT_MPRCL(hw->port),
1847                             pf->offset_loaded, &os->eth.rx_multicast,
1848                             &ns->eth.rx_multicast);
1849         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1850                             I40E_GLPRT_BPRCL(hw->port),
1851                             pf->offset_loaded, &os->eth.rx_broadcast,
1852                             &ns->eth.rx_broadcast);
1853         /* Workaround: CRC size should not be included in byte statistics,
1854          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1855          */
1856         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1857                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1858
1859         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1860                             pf->offset_loaded, &os->eth.rx_discards,
1861                             &ns->eth.rx_discards);
1862         /* GLPRT_REPC not supported */
1863         /* GLPRT_RMPC not supported */
1864         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1865                             pf->offset_loaded,
1866                             &os->eth.rx_unknown_protocol,
1867                             &ns->eth.rx_unknown_protocol);
1868         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1869                             I40E_GLPRT_GOTCL(hw->port),
1870                             pf->offset_loaded, &os->eth.tx_bytes,
1871                             &ns->eth.tx_bytes);
1872         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1873                             I40E_GLPRT_UPTCL(hw->port),
1874                             pf->offset_loaded, &os->eth.tx_unicast,
1875                             &ns->eth.tx_unicast);
1876         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1877                             I40E_GLPRT_MPTCL(hw->port),
1878                             pf->offset_loaded, &os->eth.tx_multicast,
1879                             &ns->eth.tx_multicast);
1880         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1881                             I40E_GLPRT_BPTCL(hw->port),
1882                             pf->offset_loaded, &os->eth.tx_broadcast,
1883                             &ns->eth.tx_broadcast);
1884         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1885                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1886         /* GLPRT_TEPC not supported */
1887
1888         /* additional port specific stats */
1889         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1890                             pf->offset_loaded, &os->tx_dropped_link_down,
1891                             &ns->tx_dropped_link_down);
1892         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1893                             pf->offset_loaded, &os->crc_errors,
1894                             &ns->crc_errors);
1895         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1896                             pf->offset_loaded, &os->illegal_bytes,
1897                             &ns->illegal_bytes);
1898         /* GLPRT_ERRBC not supported */
1899         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1900                             pf->offset_loaded, &os->mac_local_faults,
1901                             &ns->mac_local_faults);
1902         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1903                             pf->offset_loaded, &os->mac_remote_faults,
1904                             &ns->mac_remote_faults);
1905         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1906                             pf->offset_loaded, &os->rx_length_errors,
1907                             &ns->rx_length_errors);
1908         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1909                             pf->offset_loaded, &os->link_xon_rx,
1910                             &ns->link_xon_rx);
1911         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1912                             pf->offset_loaded, &os->link_xoff_rx,
1913                             &ns->link_xoff_rx);
1914         for (i = 0; i < 8; i++) {
1915                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1916                                     pf->offset_loaded,
1917                                     &os->priority_xon_rx[i],
1918                                     &ns->priority_xon_rx[i]);
1919                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1920                                     pf->offset_loaded,
1921                                     &os->priority_xoff_rx[i],
1922                                     &ns->priority_xoff_rx[i]);
1923         }
1924         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1925                             pf->offset_loaded, &os->link_xon_tx,
1926                             &ns->link_xon_tx);
1927         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1928                             pf->offset_loaded, &os->link_xoff_tx,
1929                             &ns->link_xoff_tx);
1930         for (i = 0; i < 8; i++) {
1931                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1932                                     pf->offset_loaded,
1933                                     &os->priority_xon_tx[i],
1934                                     &ns->priority_xon_tx[i]);
1935                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1936                                     pf->offset_loaded,
1937                                     &os->priority_xoff_tx[i],
1938                                     &ns->priority_xoff_tx[i]);
1939                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1940                                     pf->offset_loaded,
1941                                     &os->priority_xon_2_xoff[i],
1942                                     &ns->priority_xon_2_xoff[i]);
1943         }
1944         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1945                             I40E_GLPRT_PRC64L(hw->port),
1946                             pf->offset_loaded, &os->rx_size_64,
1947                             &ns->rx_size_64);
1948         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1949                             I40E_GLPRT_PRC127L(hw->port),
1950                             pf->offset_loaded, &os->rx_size_127,
1951                             &ns->rx_size_127);
1952         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1953                             I40E_GLPRT_PRC255L(hw->port),
1954                             pf->offset_loaded, &os->rx_size_255,
1955                             &ns->rx_size_255);
1956         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1957                             I40E_GLPRT_PRC511L(hw->port),
1958                             pf->offset_loaded, &os->rx_size_511,
1959                             &ns->rx_size_511);
1960         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1961                             I40E_GLPRT_PRC1023L(hw->port),
1962                             pf->offset_loaded, &os->rx_size_1023,
1963                             &ns->rx_size_1023);
1964         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1965                             I40E_GLPRT_PRC1522L(hw->port),
1966                             pf->offset_loaded, &os->rx_size_1522,
1967                             &ns->rx_size_1522);
1968         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1969                             I40E_GLPRT_PRC9522L(hw->port),
1970                             pf->offset_loaded, &os->rx_size_big,
1971                             &ns->rx_size_big);
1972         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1973                             pf->offset_loaded, &os->rx_undersize,
1974                             &ns->rx_undersize);
1975         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1976                             pf->offset_loaded, &os->rx_fragments,
1977                             &ns->rx_fragments);
1978         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1979                             pf->offset_loaded, &os->rx_oversize,
1980                             &ns->rx_oversize);
1981         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1982                             pf->offset_loaded, &os->rx_jabber,
1983                             &ns->rx_jabber);
1984         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1985                             I40E_GLPRT_PTC64L(hw->port),
1986                             pf->offset_loaded, &os->tx_size_64,
1987                             &ns->tx_size_64);
1988         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1989                             I40E_GLPRT_PTC127L(hw->port),
1990                             pf->offset_loaded, &os->tx_size_127,
1991                             &ns->tx_size_127);
1992         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1993                             I40E_GLPRT_PTC255L(hw->port),
1994                             pf->offset_loaded, &os->tx_size_255,
1995                             &ns->tx_size_255);
1996         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1997                             I40E_GLPRT_PTC511L(hw->port),
1998                             pf->offset_loaded, &os->tx_size_511,
1999                             &ns->tx_size_511);
2000         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2001                             I40E_GLPRT_PTC1023L(hw->port),
2002                             pf->offset_loaded, &os->tx_size_1023,
2003                             &ns->tx_size_1023);
2004         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2005                             I40E_GLPRT_PTC1522L(hw->port),
2006                             pf->offset_loaded, &os->tx_size_1522,
2007                             &ns->tx_size_1522);
2008         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2009                             I40E_GLPRT_PTC9522L(hw->port),
2010                             pf->offset_loaded, &os->tx_size_big,
2011                             &ns->tx_size_big);
2012         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2013                            pf->offset_loaded,
2014                            &os->fd_sb_match, &ns->fd_sb_match);
2015         /* GLPRT_MSPDC not supported */
2016         /* GLPRT_XEC not supported */
2017
2018         pf->offset_loaded = true;
2019
2020         if (pf->main_vsi)
2021                 i40e_update_vsi_stats(pf->main_vsi);
2022 }
2023
2024 /* Get all statistics of a port */
2025 static void
2026 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2027 {
2028         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2029         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2030         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2031         unsigned i;
2032
2033         /* call read registers - updates values, now write them to struct */
2034         i40e_read_stats_registers(pf, hw);
2035
2036         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2037                         pf->main_vsi->eth_stats.rx_multicast +
2038                         pf->main_vsi->eth_stats.rx_broadcast -
2039                         pf->main_vsi->eth_stats.rx_discards;
2040         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2041                         pf->main_vsi->eth_stats.tx_multicast +
2042                         pf->main_vsi->eth_stats.tx_broadcast;
2043         stats->ibytes   = ns->eth.rx_bytes;
2044         stats->obytes   = ns->eth.tx_bytes;
2045         stats->oerrors  = ns->eth.tx_errors +
2046                         pf->main_vsi->eth_stats.tx_errors;
2047         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2048
2049         /* Rx Errors */
2050         stats->imissed  = ns->eth.rx_discards +
2051                         pf->main_vsi->eth_stats.rx_discards;
2052         stats->ierrors  = ns->crc_errors +
2053                         ns->rx_length_errors + ns->rx_undersize +
2054                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
2055                         stats->imissed;
2056
2057         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2058         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2059         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2060         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2061         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2062         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2063         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2064                     ns->eth.rx_unknown_protocol);
2065         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2066         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2067         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2068         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2069         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2070         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2071
2072         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2073                     ns->tx_dropped_link_down);
2074         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2075         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2076                     ns->illegal_bytes);
2077         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2078         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2079                     ns->mac_local_faults);
2080         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2081                     ns->mac_remote_faults);
2082         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2083                     ns->rx_length_errors);
2084         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2085         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2086         for (i = 0; i < 8; i++) {
2087                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2088                                 i, ns->priority_xon_rx[i]);
2089                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2090                                 i, ns->priority_xoff_rx[i]);
2091         }
2092         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2093         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2094         for (i = 0; i < 8; i++) {
2095                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2096                                 i, ns->priority_xon_tx[i]);
2097                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2098                                 i, ns->priority_xoff_tx[i]);
2099                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2100                                 i, ns->priority_xon_2_xoff[i]);
2101         }
2102         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2103         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2104         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2105         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2106         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2107         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2108         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2109         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2110         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2111         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2112         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2113         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2114         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2115         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2116         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2117         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2118         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2119         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2120         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2121                         ns->mac_short_packet_dropped);
2122         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2123                     ns->checksum_error);
2124         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2125         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2126 }
2127
2128 /* Reset the statistics */
2129 static void
2130 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2131 {
2132         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2133         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134
2135         /* Mark PF and VSI stats to update the offset, aka "reset" */
2136         pf->offset_loaded = false;
2137         if (pf->main_vsi)
2138                 pf->main_vsi->offset_loaded = false;
2139
2140         /* read the stats, reading current register values into offset */
2141         i40e_read_stats_registers(pf, hw);
2142 }
2143
2144 static uint32_t
2145 i40e_xstats_calc_num(void)
2146 {
2147         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2148                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2149                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2150 }
2151
2152 static int
2153 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2154                     unsigned n)
2155 {
2156         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2157         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158         unsigned i, count, prio;
2159         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2160
2161         count = i40e_xstats_calc_num();
2162         if (n < count)
2163                 return count;
2164
2165         i40e_read_stats_registers(pf, hw);
2166
2167         if (xstats == NULL)
2168                 return 0;
2169
2170         count = 0;
2171
2172         /* Get stats from i40e_eth_stats struct */
2173         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2174                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2175                          "%s", rte_i40e_stats_strings[i].name);
2176                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2177                         rte_i40e_stats_strings[i].offset);
2178                 count++;
2179         }
2180
2181         /* Get individiual stats from i40e_hw_port struct */
2182         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2183                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2184                          "%s", rte_i40e_hw_port_strings[i].name);
2185                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2186                                 rte_i40e_hw_port_strings[i].offset);
2187                 count++;
2188         }
2189
2190         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2191                 for (prio = 0; prio < 8; prio++) {
2192                         snprintf(xstats[count].name,
2193                                  sizeof(xstats[count].name),
2194                                  "rx_priority%u_%s", prio,
2195                                  rte_i40e_rxq_prio_strings[i].name);
2196                         xstats[count].value =
2197                                 *(uint64_t *)(((char *)hw_stats) +
2198                                 rte_i40e_rxq_prio_strings[i].offset +
2199                                 (sizeof(uint64_t) * prio));
2200                         count++;
2201                 }
2202         }
2203
2204         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2205                 for (prio = 0; prio < 8; prio++) {
2206                         snprintf(xstats[count].name,
2207                                  sizeof(xstats[count].name),
2208                                  "tx_priority%u_%s", prio,
2209                                  rte_i40e_txq_prio_strings[i].name);
2210                         xstats[count].value =
2211                                 *(uint64_t *)(((char *)hw_stats) +
2212                                 rte_i40e_txq_prio_strings[i].offset +
2213                                 (sizeof(uint64_t) * prio));
2214                         count++;
2215                 }
2216         }
2217
2218         return count;
2219 }
2220
2221 static int
2222 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2223                                  __rte_unused uint16_t queue_id,
2224                                  __rte_unused uint8_t stat_idx,
2225                                  __rte_unused uint8_t is_rx)
2226 {
2227         PMD_INIT_FUNC_TRACE();
2228
2229         return -ENOSYS;
2230 }
2231
2232 static void
2233 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2234 {
2235         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2236         struct i40e_vsi *vsi = pf->main_vsi;
2237
2238         dev_info->max_rx_queues = vsi->nb_qps;
2239         dev_info->max_tx_queues = vsi->nb_qps;
2240         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2241         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2242         dev_info->max_mac_addrs = vsi->max_macaddrs;
2243         dev_info->max_vfs = dev->pci_dev->max_vfs;
2244         dev_info->rx_offload_capa =
2245                 DEV_RX_OFFLOAD_VLAN_STRIP |
2246                 DEV_RX_OFFLOAD_QINQ_STRIP |
2247                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2248                 DEV_RX_OFFLOAD_UDP_CKSUM |
2249                 DEV_RX_OFFLOAD_TCP_CKSUM;
2250         dev_info->tx_offload_capa =
2251                 DEV_TX_OFFLOAD_VLAN_INSERT |
2252                 DEV_TX_OFFLOAD_QINQ_INSERT |
2253                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2254                 DEV_TX_OFFLOAD_UDP_CKSUM |
2255                 DEV_TX_OFFLOAD_TCP_CKSUM |
2256                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2257                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2258                 DEV_TX_OFFLOAD_TCP_TSO;
2259         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2260                                                 sizeof(uint32_t);
2261         dev_info->reta_size = pf->hash_lut_size;
2262         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2263
2264         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2265                 .rx_thresh = {
2266                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2267                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2268                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2269                 },
2270                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2271                 .rx_drop_en = 0,
2272         };
2273
2274         dev_info->default_txconf = (struct rte_eth_txconf) {
2275                 .tx_thresh = {
2276                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2277                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2278                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2279                 },
2280                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2281                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2282                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2283                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2284         };
2285
2286         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2287                 .nb_max = I40E_MAX_RING_DESC,
2288                 .nb_min = I40E_MIN_RING_DESC,
2289                 .nb_align = I40E_ALIGN_RING_DESC,
2290         };
2291
2292         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2293                 .nb_max = I40E_MAX_RING_DESC,
2294                 .nb_min = I40E_MIN_RING_DESC,
2295                 .nb_align = I40E_ALIGN_RING_DESC,
2296         };
2297
2298         if (pf->flags & I40E_FLAG_VMDQ) {
2299                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2300                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2301                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2302                                                 pf->max_nb_vmdq_vsi;
2303                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2304                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2305                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2306         }
2307 }
2308
2309 static int
2310 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2311 {
2312         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2313         struct i40e_vsi *vsi = pf->main_vsi;
2314         PMD_INIT_FUNC_TRACE();
2315
2316         if (on)
2317                 return i40e_vsi_add_vlan(vsi, vlan_id);
2318         else
2319                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2320 }
2321
2322 static void
2323 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2324                    __rte_unused uint16_t tpid)
2325 {
2326         PMD_INIT_FUNC_TRACE();
2327 }
2328
2329 static void
2330 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2331 {
2332         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2333         struct i40e_vsi *vsi = pf->main_vsi;
2334
2335         if (mask & ETH_VLAN_STRIP_MASK) {
2336                 /* Enable or disable VLAN stripping */
2337                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2338                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2339                 else
2340                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2341         }
2342
2343         if (mask & ETH_VLAN_EXTEND_MASK) {
2344                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2345                         i40e_vsi_config_double_vlan(vsi, TRUE);
2346                 else
2347                         i40e_vsi_config_double_vlan(vsi, FALSE);
2348         }
2349 }
2350
2351 static void
2352 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2353                           __rte_unused uint16_t queue,
2354                           __rte_unused int on)
2355 {
2356         PMD_INIT_FUNC_TRACE();
2357 }
2358
2359 static int
2360 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2361 {
2362         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2363         struct i40e_vsi *vsi = pf->main_vsi;
2364         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2365         struct i40e_vsi_vlan_pvid_info info;
2366
2367         memset(&info, 0, sizeof(info));
2368         info.on = on;
2369         if (info.on)
2370                 info.config.pvid = pvid;
2371         else {
2372                 info.config.reject.tagged =
2373                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2374                 info.config.reject.untagged =
2375                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2376         }
2377
2378         return i40e_vsi_vlan_pvid_set(vsi, &info);
2379 }
2380
2381 static int
2382 i40e_dev_led_on(struct rte_eth_dev *dev)
2383 {
2384         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2385         uint32_t mode = i40e_led_get(hw);
2386
2387         if (mode == 0)
2388                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2389
2390         return 0;
2391 }
2392
2393 static int
2394 i40e_dev_led_off(struct rte_eth_dev *dev)
2395 {
2396         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2397         uint32_t mode = i40e_led_get(hw);
2398
2399         if (mode != 0)
2400                 i40e_led_set(hw, 0, false);
2401
2402         return 0;
2403 }
2404
2405 static int
2406 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2407 {
2408         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2409         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2410
2411         fc_conf->pause_time = pf->fc_conf.pause_time;
2412         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2413         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2414
2415          /* Return current mode according to actual setting*/
2416         switch (hw->fc.current_mode) {
2417         case I40E_FC_FULL:
2418                 fc_conf->mode = RTE_FC_FULL;
2419                 break;
2420         case I40E_FC_TX_PAUSE:
2421                 fc_conf->mode = RTE_FC_TX_PAUSE;
2422                 break;
2423         case I40E_FC_RX_PAUSE:
2424                 fc_conf->mode = RTE_FC_RX_PAUSE;
2425                 break;
2426         case I40E_FC_NONE:
2427         default:
2428                 fc_conf->mode = RTE_FC_NONE;
2429         };
2430
2431         return 0;
2432 }
2433
2434 static int
2435 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2436 {
2437         uint32_t mflcn_reg, fctrl_reg, reg;
2438         uint32_t max_high_water;
2439         uint8_t i, aq_failure;
2440         int err;
2441         struct i40e_hw *hw;
2442         struct i40e_pf *pf;
2443         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2444                 [RTE_FC_NONE] = I40E_FC_NONE,
2445                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2446                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2447                 [RTE_FC_FULL] = I40E_FC_FULL
2448         };
2449
2450         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2451
2452         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2453         if ((fc_conf->high_water > max_high_water) ||
2454                         (fc_conf->high_water < fc_conf->low_water)) {
2455                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2456                         "High_water must <= %d.", max_high_water);
2457                 return -EINVAL;
2458         }
2459
2460         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2461         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2462         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2463
2464         pf->fc_conf.pause_time = fc_conf->pause_time;
2465         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2466         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2467
2468         PMD_INIT_FUNC_TRACE();
2469
2470         /* All the link flow control related enable/disable register
2471          * configuration is handle by the F/W
2472          */
2473         err = i40e_set_fc(hw, &aq_failure, true);
2474         if (err < 0)
2475                 return -ENOSYS;
2476
2477         if (i40e_is_40G_device(hw->device_id)) {
2478                 /* Configure flow control refresh threshold,
2479                  * the value for stat_tx_pause_refresh_timer[8]
2480                  * is used for global pause operation.
2481                  */
2482
2483                 I40E_WRITE_REG(hw,
2484                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2485                                pf->fc_conf.pause_time);
2486
2487                 /* configure the timer value included in transmitted pause
2488                  * frame,
2489                  * the value for stat_tx_pause_quanta[8] is used for global
2490                  * pause operation
2491                  */
2492                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2493                                pf->fc_conf.pause_time);
2494
2495                 fctrl_reg = I40E_READ_REG(hw,
2496                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2497
2498                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2499                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2500                 else
2501                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2502
2503                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2504                                fctrl_reg);
2505         } else {
2506                 /* Configure pause time (2 TCs per register) */
2507                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2508                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2509                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2510
2511                 /* Configure flow control refresh threshold value */
2512                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2513                                pf->fc_conf.pause_time / 2);
2514
2515                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2516
2517                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2518                  *depending on configuration
2519                  */
2520                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2521                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2522                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2523                 } else {
2524                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2525                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2526                 }
2527
2528                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2529         }
2530
2531         /* config the water marker both based on the packets and bytes */
2532         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2533                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2534                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2535         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2536                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2537                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2538         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2539                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2540                        << I40E_KILOSHIFT);
2541         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2542                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2543                        << I40E_KILOSHIFT);
2544
2545         I40E_WRITE_FLUSH(hw);
2546
2547         return 0;
2548 }
2549
2550 static int
2551 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2552                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2553 {
2554         PMD_INIT_FUNC_TRACE();
2555
2556         return -ENOSYS;
2557 }
2558
2559 /* Add a MAC address, and update filters */
2560 static void
2561 i40e_macaddr_add(struct rte_eth_dev *dev,
2562                  struct ether_addr *mac_addr,
2563                  __rte_unused uint32_t index,
2564                  uint32_t pool)
2565 {
2566         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2567         struct i40e_mac_filter_info mac_filter;
2568         struct i40e_vsi *vsi;
2569         int ret;
2570
2571         /* If VMDQ not enabled or configured, return */
2572         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2573                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2574                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2575                         pool);
2576                 return;
2577         }
2578
2579         if (pool > pf->nb_cfg_vmdq_vsi) {
2580                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2581                                 pool, pf->nb_cfg_vmdq_vsi);
2582                 return;
2583         }
2584
2585         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2586         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2587
2588         if (pool == 0)
2589                 vsi = pf->main_vsi;
2590         else
2591                 vsi = pf->vmdq[pool - 1].vsi;
2592
2593         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2594         if (ret != I40E_SUCCESS) {
2595                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2596                 return;
2597         }
2598 }
2599
2600 /* Remove a MAC address, and update filters */
2601 static void
2602 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2603 {
2604         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2605         struct i40e_vsi *vsi;
2606         struct rte_eth_dev_data *data = dev->data;
2607         struct ether_addr *macaddr;
2608         int ret;
2609         uint32_t i;
2610         uint64_t pool_sel;
2611
2612         macaddr = &(data->mac_addrs[index]);
2613
2614         pool_sel = dev->data->mac_pool_sel[index];
2615
2616         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2617                 if (pool_sel & (1ULL << i)) {
2618                         if (i == 0)
2619                                 vsi = pf->main_vsi;
2620                         else {
2621                                 /* No VMDQ pool enabled or configured */
2622                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2623                                         (i > pf->nb_cfg_vmdq_vsi)) {
2624                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2625                                                         "/configured");
2626                                         return;
2627                                 }
2628                                 vsi = pf->vmdq[i - 1].vsi;
2629                         }
2630                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2631
2632                         if (ret) {
2633                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2634                                 return;
2635                         }
2636                 }
2637         }
2638 }
2639
2640 /* Set perfect match or hash match of MAC and VLAN for a VF */
2641 static int
2642 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2643                  struct rte_eth_mac_filter *filter,
2644                  bool add)
2645 {
2646         struct i40e_hw *hw;
2647         struct i40e_mac_filter_info mac_filter;
2648         struct ether_addr old_mac;
2649         struct ether_addr *new_mac;
2650         struct i40e_pf_vf *vf = NULL;
2651         uint16_t vf_id;
2652         int ret;
2653
2654         if (pf == NULL) {
2655                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2656                 return -EINVAL;
2657         }
2658         hw = I40E_PF_TO_HW(pf);
2659
2660         if (filter == NULL) {
2661                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2662                 return -EINVAL;
2663         }
2664
2665         new_mac = &filter->mac_addr;
2666
2667         if (is_zero_ether_addr(new_mac)) {
2668                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2669                 return -EINVAL;
2670         }
2671
2672         vf_id = filter->dst_id;
2673
2674         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2675                 PMD_DRV_LOG(ERR, "Invalid argument.");
2676                 return -EINVAL;
2677         }
2678         vf = &pf->vfs[vf_id];
2679
2680         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2681                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2682                 return -EINVAL;
2683         }
2684
2685         if (add) {
2686                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2687                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2688                                 ETHER_ADDR_LEN);
2689                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2690                                  ETHER_ADDR_LEN);
2691
2692                 mac_filter.filter_type = filter->filter_type;
2693                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2694                 if (ret != I40E_SUCCESS) {
2695                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2696                         return -1;
2697                 }
2698                 ether_addr_copy(new_mac, &pf->dev_addr);
2699         } else {
2700                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2701                                 ETHER_ADDR_LEN);
2702                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2703                 if (ret != I40E_SUCCESS) {
2704                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2705                         return -1;
2706                 }
2707
2708                 /* Clear device address as it has been removed */
2709                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2710                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2711         }
2712
2713         return 0;
2714 }
2715
2716 /* MAC filter handle */
2717 static int
2718 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2719                 void *arg)
2720 {
2721         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2722         struct rte_eth_mac_filter *filter;
2723         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2724         int ret = I40E_NOT_SUPPORTED;
2725
2726         filter = (struct rte_eth_mac_filter *)(arg);
2727
2728         switch (filter_op) {
2729         case RTE_ETH_FILTER_NOP:
2730                 ret = I40E_SUCCESS;
2731                 break;
2732         case RTE_ETH_FILTER_ADD:
2733                 i40e_pf_disable_irq0(hw);
2734                 if (filter->is_vf)
2735                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2736                 i40e_pf_enable_irq0(hw);
2737                 break;
2738         case RTE_ETH_FILTER_DELETE:
2739                 i40e_pf_disable_irq0(hw);
2740                 if (filter->is_vf)
2741                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2742                 i40e_pf_enable_irq0(hw);
2743                 break;
2744         default:
2745                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2746                 ret = I40E_ERR_PARAM;
2747                 break;
2748         }
2749
2750         return ret;
2751 }
2752
2753 static int
2754 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2755 {
2756         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2757         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2758         int ret;
2759
2760         if (!lut)
2761                 return -EINVAL;
2762
2763         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2764                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2765                                           lut, lut_size);
2766                 if (ret) {
2767                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2768                         return ret;
2769                 }
2770         } else {
2771                 uint32_t *lut_dw = (uint32_t *)lut;
2772                 uint16_t i, lut_size_dw = lut_size / 4;
2773
2774                 for (i = 0; i < lut_size_dw; i++)
2775                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2776         }
2777
2778         return 0;
2779 }
2780
2781 static int
2782 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2783 {
2784         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2785         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2786         int ret;
2787
2788         if (!vsi || !lut)
2789                 return -EINVAL;
2790
2791         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2792                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2793                                           lut, lut_size);
2794                 if (ret) {
2795                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2796                         return ret;
2797                 }
2798         } else {
2799                 uint32_t *lut_dw = (uint32_t *)lut;
2800                 uint16_t i, lut_size_dw = lut_size / 4;
2801
2802                 for (i = 0; i < lut_size_dw; i++)
2803                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2804                 I40E_WRITE_FLUSH(hw);
2805         }
2806
2807         return 0;
2808 }
2809
2810 static int
2811 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2812                          struct rte_eth_rss_reta_entry64 *reta_conf,
2813                          uint16_t reta_size)
2814 {
2815         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2816         uint16_t i, lut_size = pf->hash_lut_size;
2817         uint16_t idx, shift;
2818         uint8_t *lut;
2819         int ret;
2820
2821         if (reta_size != lut_size ||
2822                 reta_size > ETH_RSS_RETA_SIZE_512) {
2823                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2824                         "(%d) doesn't match the number hardware can supported "
2825                                         "(%d)\n", reta_size, lut_size);
2826                 return -EINVAL;
2827         }
2828
2829         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2830         if (!lut) {
2831                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2832                 return -ENOMEM;
2833         }
2834         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2835         if (ret)
2836                 goto out;
2837         for (i = 0; i < reta_size; i++) {
2838                 idx = i / RTE_RETA_GROUP_SIZE;
2839                 shift = i % RTE_RETA_GROUP_SIZE;
2840                 if (reta_conf[idx].mask & (1ULL << shift))
2841                         lut[i] = reta_conf[idx].reta[shift];
2842         }
2843         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2844
2845 out:
2846         rte_free(lut);
2847
2848         return ret;
2849 }
2850
2851 static int
2852 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2853                         struct rte_eth_rss_reta_entry64 *reta_conf,
2854                         uint16_t reta_size)
2855 {
2856         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2857         uint16_t i, lut_size = pf->hash_lut_size;
2858         uint16_t idx, shift;
2859         uint8_t *lut;
2860         int ret;
2861
2862         if (reta_size != lut_size ||
2863                 reta_size > ETH_RSS_RETA_SIZE_512) {
2864                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2865                         "(%d) doesn't match the number hardware can supported "
2866                                         "(%d)\n", reta_size, lut_size);
2867                 return -EINVAL;
2868         }
2869
2870         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2871         if (!lut) {
2872                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2873                 return -ENOMEM;
2874         }
2875
2876         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2877         if (ret)
2878                 goto out;
2879         for (i = 0; i < reta_size; i++) {
2880                 idx = i / RTE_RETA_GROUP_SIZE;
2881                 shift = i % RTE_RETA_GROUP_SIZE;
2882                 if (reta_conf[idx].mask & (1ULL << shift))
2883                         reta_conf[idx].reta[shift] = lut[i];
2884         }
2885
2886 out:
2887         rte_free(lut);
2888
2889         return ret;
2890 }
2891
2892 /**
2893  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2894  * @hw:   pointer to the HW structure
2895  * @mem:  pointer to mem struct to fill out
2896  * @size: size of memory requested
2897  * @alignment: what to align the allocation to
2898  **/
2899 enum i40e_status_code
2900 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2901                         struct i40e_dma_mem *mem,
2902                         u64 size,
2903                         u32 alignment)
2904 {
2905         const struct rte_memzone *mz = NULL;
2906         char z_name[RTE_MEMZONE_NAMESIZE];
2907
2908         if (!mem)
2909                 return I40E_ERR_PARAM;
2910
2911         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
2912         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2913                                          alignment, RTE_PGSIZE_2M);
2914         if (!mz)
2915                 return I40E_ERR_NO_MEMORY;
2916
2917         mem->size = size;
2918         mem->va = mz->addr;
2919         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2920         mem->zone = (const void *)mz;
2921         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
2922                     "%"PRIu64, mz->name, mem->pa);
2923
2924         return I40E_SUCCESS;
2925 }
2926
2927 /**
2928  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2929  * @hw:   pointer to the HW structure
2930  * @mem:  ptr to mem struct to free
2931  **/
2932 enum i40e_status_code
2933 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2934                     struct i40e_dma_mem *mem)
2935 {
2936         if (!mem)
2937                 return I40E_ERR_PARAM;
2938
2939         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
2940                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
2941                     mem->pa);
2942         rte_memzone_free((const struct rte_memzone *)mem->zone);
2943         mem->zone = NULL;
2944         mem->va = NULL;
2945         mem->pa = (u64)0;
2946
2947         return I40E_SUCCESS;
2948 }
2949
2950 /**
2951  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2952  * @hw:   pointer to the HW structure
2953  * @mem:  pointer to mem struct to fill out
2954  * @size: size of memory requested
2955  **/
2956 enum i40e_status_code
2957 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2958                          struct i40e_virt_mem *mem,
2959                          u32 size)
2960 {
2961         if (!mem)
2962                 return I40E_ERR_PARAM;
2963
2964         mem->size = size;
2965         mem->va = rte_zmalloc("i40e", size, 0);
2966
2967         if (mem->va)
2968                 return I40E_SUCCESS;
2969         else
2970                 return I40E_ERR_NO_MEMORY;
2971 }
2972
2973 /**
2974  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2975  * @hw:   pointer to the HW structure
2976  * @mem:  pointer to mem struct to free
2977  **/
2978 enum i40e_status_code
2979 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2980                      struct i40e_virt_mem *mem)
2981 {
2982         if (!mem)
2983                 return I40E_ERR_PARAM;
2984
2985         rte_free(mem->va);
2986         mem->va = NULL;
2987
2988         return I40E_SUCCESS;
2989 }
2990
2991 void
2992 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2993 {
2994         rte_spinlock_init(&sp->spinlock);
2995 }
2996
2997 void
2998 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2999 {
3000         rte_spinlock_lock(&sp->spinlock);
3001 }
3002
3003 void
3004 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3005 {
3006         rte_spinlock_unlock(&sp->spinlock);
3007 }
3008
3009 void
3010 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3011 {
3012         return;
3013 }
3014
3015 /**
3016  * Get the hardware capabilities, which will be parsed
3017  * and saved into struct i40e_hw.
3018  */
3019 static int
3020 i40e_get_cap(struct i40e_hw *hw)
3021 {
3022         struct i40e_aqc_list_capabilities_element_resp *buf;
3023         uint16_t len, size = 0;
3024         int ret;
3025
3026         /* Calculate a huge enough buff for saving response data temporarily */
3027         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3028                                                 I40E_MAX_CAP_ELE_NUM;
3029         buf = rte_zmalloc("i40e", len, 0);
3030         if (!buf) {
3031                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3032                 return I40E_ERR_NO_MEMORY;
3033         }
3034
3035         /* Get, parse the capabilities and save it to hw */
3036         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3037                         i40e_aqc_opc_list_func_capabilities, NULL);
3038         if (ret != I40E_SUCCESS)
3039                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3040
3041         /* Free the temporary buffer after being used */
3042         rte_free(buf);
3043
3044         return ret;
3045 }
3046
3047 static int
3048 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3049 {
3050         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3051         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3052         uint16_t qp_count = 0, vsi_count = 0;
3053
3054         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3055                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3056                 return -EINVAL;
3057         }
3058         /* Add the parameter init for LFC */
3059         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3060         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3061         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3062
3063         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3064         pf->max_num_vsi = hw->func_caps.num_vsis;
3065         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3066         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3067         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3068
3069         /* FDir queue/VSI allocation */
3070         pf->fdir_qp_offset = 0;
3071         if (hw->func_caps.fd) {
3072                 pf->flags |= I40E_FLAG_FDIR;
3073                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3074         } else {
3075                 pf->fdir_nb_qps = 0;
3076         }
3077         qp_count += pf->fdir_nb_qps;
3078         vsi_count += 1;
3079
3080         /* LAN queue/VSI allocation */
3081         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3082         if (!hw->func_caps.rss) {
3083                 pf->lan_nb_qps = 1;
3084         } else {
3085                 pf->flags |= I40E_FLAG_RSS;
3086                 if (hw->mac.type == I40E_MAC_X722)
3087                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3088                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3089         }
3090         qp_count += pf->lan_nb_qps;
3091         vsi_count += 1;
3092
3093         /* VF queue/VSI allocation */
3094         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3095         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3096                 pf->flags |= I40E_FLAG_SRIOV;
3097                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3098                 pf->vf_num = dev->pci_dev->max_vfs;
3099                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3100                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3101                             pf->vf_nb_qps * pf->vf_num);
3102         } else {
3103                 pf->vf_nb_qps = 0;
3104                 pf->vf_num = 0;
3105         }
3106         qp_count += pf->vf_nb_qps * pf->vf_num;
3107         vsi_count += pf->vf_num;
3108
3109         /* VMDq queue/VSI allocation */
3110         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3111         pf->vmdq_nb_qps = 0;
3112         pf->max_nb_vmdq_vsi = 0;
3113         if (hw->func_caps.vmdq) {
3114                 if (qp_count < hw->func_caps.num_tx_qp &&
3115                         vsi_count < hw->func_caps.num_vsis) {
3116                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3117                                 qp_count) / pf->vmdq_nb_qp_max;
3118
3119                         /* Limit the maximum number of VMDq vsi to the maximum
3120                          * ethdev can support
3121                          */
3122                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3123                                 hw->func_caps.num_vsis - vsi_count);
3124                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3125                                 ETH_64_POOLS);
3126                         if (pf->max_nb_vmdq_vsi) {
3127                                 pf->flags |= I40E_FLAG_VMDQ;
3128                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3129                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3130                                             "per VMDQ VSI, in total %u queues",
3131                                             pf->max_nb_vmdq_vsi,
3132                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3133                                             pf->max_nb_vmdq_vsi);
3134                         } else {
3135                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3136                                             "VMDq");
3137                         }
3138                 } else {
3139                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3140                 }
3141         }
3142         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3143         vsi_count += pf->max_nb_vmdq_vsi;
3144
3145         if (hw->func_caps.dcb)
3146                 pf->flags |= I40E_FLAG_DCB;
3147
3148         if (qp_count > hw->func_caps.num_tx_qp) {
3149                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3150                             "the hardware maximum %u", qp_count,
3151                             hw->func_caps.num_tx_qp);
3152                 return -EINVAL;
3153         }
3154         if (vsi_count > hw->func_caps.num_vsis) {
3155                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3156                             "the hardware maximum %u", vsi_count,
3157                             hw->func_caps.num_vsis);
3158                 return -EINVAL;
3159         }
3160
3161         return 0;
3162 }
3163
3164 static int
3165 i40e_pf_get_switch_config(struct i40e_pf *pf)
3166 {
3167         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3168         struct i40e_aqc_get_switch_config_resp *switch_config;
3169         struct i40e_aqc_switch_config_element_resp *element;
3170         uint16_t start_seid = 0, num_reported;
3171         int ret;
3172
3173         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3174                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3175         if (!switch_config) {
3176                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3177                 return -ENOMEM;
3178         }
3179
3180         /* Get the switch configurations */
3181         ret = i40e_aq_get_switch_config(hw, switch_config,
3182                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3183         if (ret != I40E_SUCCESS) {
3184                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3185                 goto fail;
3186         }
3187         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3188         if (num_reported != 1) { /* The number should be 1 */
3189                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3190                 goto fail;
3191         }
3192
3193         /* Parse the switch configuration elements */
3194         element = &(switch_config->element[0]);
3195         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3196                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3197                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3198         } else
3199                 PMD_DRV_LOG(INFO, "Unknown element type");
3200
3201 fail:
3202         rte_free(switch_config);
3203
3204         return ret;
3205 }
3206
3207 static int
3208 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3209                         uint32_t num)
3210 {
3211         struct pool_entry *entry;
3212
3213         if (pool == NULL || num == 0)
3214                 return -EINVAL;
3215
3216         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3217         if (entry == NULL) {
3218                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3219                 return -ENOMEM;
3220         }
3221
3222         /* queue heap initialize */
3223         pool->num_free = num;
3224         pool->num_alloc = 0;
3225         pool->base = base;
3226         LIST_INIT(&pool->alloc_list);
3227         LIST_INIT(&pool->free_list);
3228
3229         /* Initialize element  */
3230         entry->base = 0;
3231         entry->len = num;
3232
3233         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3234         return 0;
3235 }
3236
3237 static void
3238 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3239 {
3240         struct pool_entry *entry;
3241
3242         if (pool == NULL)
3243                 return;
3244
3245         LIST_FOREACH(entry, &pool->alloc_list, next) {
3246                 LIST_REMOVE(entry, next);
3247                 rte_free(entry);
3248         }
3249
3250         LIST_FOREACH(entry, &pool->free_list, next) {
3251                 LIST_REMOVE(entry, next);
3252                 rte_free(entry);
3253         }
3254
3255         pool->num_free = 0;
3256         pool->num_alloc = 0;
3257         pool->base = 0;
3258         LIST_INIT(&pool->alloc_list);
3259         LIST_INIT(&pool->free_list);
3260 }
3261
3262 static int
3263 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3264                        uint32_t base)
3265 {
3266         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3267         uint32_t pool_offset;
3268         int insert;
3269
3270         if (pool == NULL) {
3271                 PMD_DRV_LOG(ERR, "Invalid parameter");
3272                 return -EINVAL;
3273         }
3274
3275         pool_offset = base - pool->base;
3276         /* Lookup in alloc list */
3277         LIST_FOREACH(entry, &pool->alloc_list, next) {
3278                 if (entry->base == pool_offset) {
3279                         valid_entry = entry;
3280                         LIST_REMOVE(entry, next);
3281                         break;
3282                 }
3283         }
3284
3285         /* Not find, return */
3286         if (valid_entry == NULL) {
3287                 PMD_DRV_LOG(ERR, "Failed to find entry");
3288                 return -EINVAL;
3289         }
3290
3291         /**
3292          * Found it, move it to free list  and try to merge.
3293          * In order to make merge easier, always sort it by qbase.
3294          * Find adjacent prev and last entries.
3295          */
3296         prev = next = NULL;
3297         LIST_FOREACH(entry, &pool->free_list, next) {
3298                 if (entry->base > valid_entry->base) {
3299                         next = entry;
3300                         break;
3301                 }
3302                 prev = entry;
3303         }
3304
3305         insert = 0;
3306         /* Try to merge with next one*/
3307         if (next != NULL) {
3308                 /* Merge with next one */
3309                 if (valid_entry->base + valid_entry->len == next->base) {
3310                         next->base = valid_entry->base;
3311                         next->len += valid_entry->len;
3312                         rte_free(valid_entry);
3313                         valid_entry = next;
3314                         insert = 1;
3315                 }
3316         }
3317
3318         if (prev != NULL) {
3319                 /* Merge with previous one */
3320                 if (prev->base + prev->len == valid_entry->base) {
3321                         prev->len += valid_entry->len;
3322                         /* If it merge with next one, remove next node */
3323                         if (insert == 1) {
3324                                 LIST_REMOVE(valid_entry, next);
3325                                 rte_free(valid_entry);
3326                         } else {
3327                                 rte_free(valid_entry);
3328                                 insert = 1;
3329                         }
3330                 }
3331         }
3332
3333         /* Not find any entry to merge, insert */
3334         if (insert == 0) {
3335                 if (prev != NULL)
3336                         LIST_INSERT_AFTER(prev, valid_entry, next);
3337                 else if (next != NULL)
3338                         LIST_INSERT_BEFORE(next, valid_entry, next);
3339                 else /* It's empty list, insert to head */
3340                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3341         }
3342
3343         pool->num_free += valid_entry->len;
3344         pool->num_alloc -= valid_entry->len;
3345
3346         return 0;
3347 }
3348
3349 static int
3350 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3351                        uint16_t num)
3352 {
3353         struct pool_entry *entry, *valid_entry;
3354
3355         if (pool == NULL || num == 0) {
3356                 PMD_DRV_LOG(ERR, "Invalid parameter");
3357                 return -EINVAL;
3358         }
3359
3360         if (pool->num_free < num) {
3361                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3362                             num, pool->num_free);
3363                 return -ENOMEM;
3364         }
3365
3366         valid_entry = NULL;
3367         /* Lookup  in free list and find most fit one */
3368         LIST_FOREACH(entry, &pool->free_list, next) {
3369                 if (entry->len >= num) {
3370                         /* Find best one */
3371                         if (entry->len == num) {
3372                                 valid_entry = entry;
3373                                 break;
3374                         }
3375                         if (valid_entry == NULL || valid_entry->len > entry->len)
3376                                 valid_entry = entry;
3377                 }
3378         }
3379
3380         /* Not find one to satisfy the request, return */
3381         if (valid_entry == NULL) {
3382                 PMD_DRV_LOG(ERR, "No valid entry found");
3383                 return -ENOMEM;
3384         }
3385         /**
3386          * The entry have equal queue number as requested,
3387          * remove it from alloc_list.
3388          */
3389         if (valid_entry->len == num) {
3390                 LIST_REMOVE(valid_entry, next);
3391         } else {
3392                 /**
3393                  * The entry have more numbers than requested,
3394                  * create a new entry for alloc_list and minus its
3395                  * queue base and number in free_list.
3396                  */
3397                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3398                 if (entry == NULL) {
3399                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3400                                     "resource pool");
3401                         return -ENOMEM;
3402                 }
3403                 entry->base = valid_entry->base;
3404                 entry->len = num;
3405                 valid_entry->base += num;
3406                 valid_entry->len -= num;
3407                 valid_entry = entry;
3408         }
3409
3410         /* Insert it into alloc list, not sorted */
3411         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3412
3413         pool->num_free -= valid_entry->len;
3414         pool->num_alloc += valid_entry->len;
3415
3416         return valid_entry->base + pool->base;
3417 }
3418
3419 /**
3420  * bitmap_is_subset - Check whether src2 is subset of src1
3421  **/
3422 static inline int
3423 bitmap_is_subset(uint8_t src1, uint8_t src2)
3424 {
3425         return !((src1 ^ src2) & src2);
3426 }
3427
3428 static enum i40e_status_code
3429 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3430 {
3431         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3432
3433         /* If DCB is not supported, only default TC is supported */
3434         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3435                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3436                 return I40E_NOT_SUPPORTED;
3437         }
3438
3439         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3440                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3441                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3442                             enabled_tcmap);
3443                 return I40E_NOT_SUPPORTED;
3444         }
3445         return I40E_SUCCESS;
3446 }
3447
3448 int
3449 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3450                                 struct i40e_vsi_vlan_pvid_info *info)
3451 {
3452         struct i40e_hw *hw;
3453         struct i40e_vsi_context ctxt;
3454         uint8_t vlan_flags = 0;
3455         int ret;
3456
3457         if (vsi == NULL || info == NULL) {
3458                 PMD_DRV_LOG(ERR, "invalid parameters");
3459                 return I40E_ERR_PARAM;
3460         }
3461
3462         if (info->on) {
3463                 vsi->info.pvid = info->config.pvid;
3464                 /**
3465                  * If insert pvid is enabled, only tagged pkts are
3466                  * allowed to be sent out.
3467                  */
3468                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3469                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3470         } else {
3471                 vsi->info.pvid = 0;
3472                 if (info->config.reject.tagged == 0)
3473                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3474
3475                 if (info->config.reject.untagged == 0)
3476                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3477         }
3478         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3479                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3480         vsi->info.port_vlan_flags |= vlan_flags;
3481         vsi->info.valid_sections =
3482                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3483         memset(&ctxt, 0, sizeof(ctxt));
3484         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3485         ctxt.seid = vsi->seid;
3486
3487         hw = I40E_VSI_TO_HW(vsi);
3488         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3489         if (ret != I40E_SUCCESS)
3490                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3491
3492         return ret;
3493 }
3494
3495 static int
3496 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3497 {
3498         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3499         int i, ret;
3500         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3501
3502         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3503         if (ret != I40E_SUCCESS)
3504                 return ret;
3505
3506         if (!vsi->seid) {
3507                 PMD_DRV_LOG(ERR, "seid not valid");
3508                 return -EINVAL;
3509         }
3510
3511         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3512         tc_bw_data.tc_valid_bits = enabled_tcmap;
3513         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3514                 tc_bw_data.tc_bw_credits[i] =
3515                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3516
3517         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3518         if (ret != I40E_SUCCESS) {
3519                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3520                 return ret;
3521         }
3522
3523         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3524                                         sizeof(vsi->info.qs_handle));
3525         return I40E_SUCCESS;
3526 }
3527
3528 static enum i40e_status_code
3529 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3530                                  struct i40e_aqc_vsi_properties_data *info,
3531                                  uint8_t enabled_tcmap)
3532 {
3533         enum i40e_status_code ret;
3534         int i, total_tc = 0;
3535         uint16_t qpnum_per_tc, bsf, qp_idx;
3536
3537         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3538         if (ret != I40E_SUCCESS)
3539                 return ret;
3540
3541         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3542                 if (enabled_tcmap & (1 << i))
3543                         total_tc++;
3544         vsi->enabled_tc = enabled_tcmap;
3545
3546         /* Number of queues per enabled TC */
3547         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3548         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3549         bsf = rte_bsf32(qpnum_per_tc);
3550
3551         /* Adjust the queue number to actual queues that can be applied */
3552         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3553                 vsi->nb_qps = qpnum_per_tc * total_tc;
3554
3555         /**
3556          * Configure TC and queue mapping parameters, for enabled TC,
3557          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3558          * default queue will serve it.
3559          */
3560         qp_idx = 0;
3561         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3562                 if (vsi->enabled_tc & (1 << i)) {
3563                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3564                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3565                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3566                         qp_idx += qpnum_per_tc;
3567                 } else
3568                         info->tc_mapping[i] = 0;
3569         }
3570
3571         /* Associate queue number with VSI */
3572         if (vsi->type == I40E_VSI_SRIOV) {
3573                 info->mapping_flags |=
3574                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3575                 for (i = 0; i < vsi->nb_qps; i++)
3576                         info->queue_mapping[i] =
3577                                 rte_cpu_to_le_16(vsi->base_queue + i);
3578         } else {
3579                 info->mapping_flags |=
3580                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3581                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3582         }
3583         info->valid_sections |=
3584                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3585
3586         return I40E_SUCCESS;
3587 }
3588
3589 static int
3590 i40e_veb_release(struct i40e_veb *veb)
3591 {
3592         struct i40e_vsi *vsi;
3593         struct i40e_hw *hw;
3594
3595         if (veb == NULL || veb->associate_vsi == NULL)
3596                 return -EINVAL;
3597
3598         if (!TAILQ_EMPTY(&veb->head)) {
3599                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3600                 return -EACCES;
3601         }
3602
3603         vsi = veb->associate_vsi;
3604         hw = I40E_VSI_TO_HW(vsi);
3605
3606         vsi->uplink_seid = veb->uplink_seid;
3607         i40e_aq_delete_element(hw, veb->seid, NULL);
3608         rte_free(veb);
3609         vsi->veb = NULL;
3610         return I40E_SUCCESS;
3611 }
3612
3613 /* Setup a veb */
3614 static struct i40e_veb *
3615 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3616 {
3617         struct i40e_veb *veb;
3618         int ret;
3619         struct i40e_hw *hw;
3620
3621         if (NULL == pf || vsi == NULL) {
3622                 PMD_DRV_LOG(ERR, "veb setup failed, "
3623                             "associated VSI shouldn't null");
3624                 return NULL;
3625         }
3626         hw = I40E_PF_TO_HW(pf);
3627
3628         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3629         if (!veb) {
3630                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3631                 goto fail;
3632         }
3633
3634         veb->associate_vsi = vsi;
3635         TAILQ_INIT(&veb->head);
3636         veb->uplink_seid = vsi->uplink_seid;
3637
3638         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3639                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3640
3641         if (ret != I40E_SUCCESS) {
3642                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3643                             hw->aq.asq_last_status);
3644                 goto fail;
3645         }
3646
3647         /* get statistics index */
3648         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3649                                 &veb->stats_idx, NULL, NULL, NULL);
3650         if (ret != I40E_SUCCESS) {
3651                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3652                             hw->aq.asq_last_status);
3653                 goto fail;
3654         }
3655
3656         /* Get VEB bandwidth, to be implemented */
3657         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3658         vsi->uplink_seid = veb->seid;
3659
3660         return veb;
3661 fail:
3662         rte_free(veb);
3663         return NULL;
3664 }
3665
3666 int
3667 i40e_vsi_release(struct i40e_vsi *vsi)
3668 {
3669         struct i40e_pf *pf;
3670         struct i40e_hw *hw;
3671         struct i40e_vsi_list *vsi_list;
3672         int ret;
3673         struct i40e_mac_filter *f;
3674
3675         if (!vsi)
3676                 return I40E_SUCCESS;
3677
3678         pf = I40E_VSI_TO_PF(vsi);
3679         hw = I40E_VSI_TO_HW(vsi);
3680
3681         /* VSI has child to attach, release child first */
3682         if (vsi->veb) {
3683                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3684                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3685                                 return -1;
3686                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3687                 }
3688                 i40e_veb_release(vsi->veb);
3689         }
3690
3691         /* Remove all macvlan filters of the VSI */
3692         i40e_vsi_remove_all_macvlan_filter(vsi);
3693         TAILQ_FOREACH(f, &vsi->mac_list, next)
3694                 rte_free(f);
3695
3696         if (vsi->type != I40E_VSI_MAIN) {
3697                 /* Remove vsi from parent's sibling list */
3698                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3699                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3700                         return I40E_ERR_PARAM;
3701                 }
3702                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3703                                 &vsi->sib_vsi_list, list);
3704
3705                 /* Remove all switch element of the VSI */
3706                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3707                 if (ret != I40E_SUCCESS)
3708                         PMD_DRV_LOG(ERR, "Failed to delete element");
3709         }
3710         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3711
3712         if (vsi->type != I40E_VSI_SRIOV)
3713                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3714         rte_free(vsi);
3715
3716         return I40E_SUCCESS;
3717 }
3718
3719 static int
3720 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3721 {
3722         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3723         struct i40e_aqc_remove_macvlan_element_data def_filter;
3724         struct i40e_mac_filter_info filter;
3725         int ret;
3726
3727         if (vsi->type != I40E_VSI_MAIN)
3728                 return I40E_ERR_CONFIG;
3729         memset(&def_filter, 0, sizeof(def_filter));
3730         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3731                                         ETH_ADDR_LEN);
3732         def_filter.vlan_tag = 0;
3733         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3734                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3735         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3736         if (ret != I40E_SUCCESS) {
3737                 struct i40e_mac_filter *f;
3738                 struct ether_addr *mac;
3739
3740                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3741                             "macvlan filter");
3742                 /* It needs to add the permanent mac into mac list */
3743                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3744                 if (f == NULL) {
3745                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3746                         return I40E_ERR_NO_MEMORY;
3747                 }
3748                 mac = &f->mac_info.mac_addr;
3749                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3750                                 ETH_ADDR_LEN);
3751                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3752                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3753                 vsi->mac_num++;
3754
3755                 return ret;
3756         }
3757         (void)rte_memcpy(&filter.mac_addr,
3758                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3759         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3760         return i40e_vsi_add_mac(vsi, &filter);
3761 }
3762
3763 #define I40E_3_BIT_MASK     0x7
3764 /*
3765  * i40e_vsi_get_bw_config - Query VSI BW Information
3766  * @vsi: the VSI to be queried
3767  *
3768  * Returns 0 on success, negative value on failure
3769  */
3770 static enum i40e_status_code
3771 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3772 {
3773         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3774         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3775         struct i40e_hw *hw = &vsi->adapter->hw;
3776         i40e_status ret;
3777         int i;
3778         uint32_t bw_max;
3779
3780         memset(&bw_config, 0, sizeof(bw_config));
3781         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3782         if (ret != I40E_SUCCESS) {
3783                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3784                             hw->aq.asq_last_status);
3785                 return ret;
3786         }
3787
3788         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3789         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3790                                         &ets_sla_config, NULL);
3791         if (ret != I40E_SUCCESS) {
3792                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3793                             "configuration %u", hw->aq.asq_last_status);
3794                 return ret;
3795         }
3796
3797         /* store and print out BW info */
3798         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3799         vsi->bw_info.bw_max = bw_config.max_bw;
3800         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3801         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3802         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3803                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3804                      I40E_16_BIT_WIDTH);
3805         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3806                 vsi->bw_info.bw_ets_share_credits[i] =
3807                                 ets_sla_config.share_credits[i];
3808                 vsi->bw_info.bw_ets_credits[i] =
3809                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3810                 /* 4 bits per TC, 4th bit is reserved */
3811                 vsi->bw_info.bw_ets_max[i] =
3812                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3813                                   I40E_3_BIT_MASK);
3814                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3815                             vsi->bw_info.bw_ets_share_credits[i]);
3816                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3817                             vsi->bw_info.bw_ets_credits[i]);
3818                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3819                             vsi->bw_info.bw_ets_max[i]);
3820         }
3821
3822         return I40E_SUCCESS;
3823 }
3824
3825 /* Setup a VSI */
3826 struct i40e_vsi *
3827 i40e_vsi_setup(struct i40e_pf *pf,
3828                enum i40e_vsi_type type,
3829                struct i40e_vsi *uplink_vsi,
3830                uint16_t user_param)
3831 {
3832         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3833         struct i40e_vsi *vsi;
3834         struct i40e_mac_filter_info filter;
3835         int ret;
3836         struct i40e_vsi_context ctxt;
3837         struct ether_addr broadcast =
3838                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3839
3840         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3841                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3842                             "VSI link shouldn't be NULL");
3843                 return NULL;
3844         }
3845
3846         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3847                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3848                             "uplink VSI should be NULL");
3849                 return NULL;
3850         }
3851
3852         /* If uplink vsi didn't setup VEB, create one first */
3853         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3854                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3855
3856                 if (NULL == uplink_vsi->veb) {
3857                         PMD_DRV_LOG(ERR, "VEB setup failed");
3858                         return NULL;
3859                 }
3860         }
3861
3862         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3863         if (!vsi) {
3864                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3865                 return NULL;
3866         }
3867         TAILQ_INIT(&vsi->mac_list);
3868         vsi->type = type;
3869         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3870         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3871         vsi->parent_vsi = uplink_vsi;
3872         vsi->user_param = user_param;
3873         /* Allocate queues */
3874         switch (vsi->type) {
3875         case I40E_VSI_MAIN  :
3876                 vsi->nb_qps = pf->lan_nb_qps;
3877                 break;
3878         case I40E_VSI_SRIOV :
3879                 vsi->nb_qps = pf->vf_nb_qps;
3880                 break;
3881         case I40E_VSI_VMDQ2:
3882                 vsi->nb_qps = pf->vmdq_nb_qps;
3883                 break;
3884         case I40E_VSI_FDIR:
3885                 vsi->nb_qps = pf->fdir_nb_qps;
3886                 break;
3887         default:
3888                 goto fail_mem;
3889         }
3890         /*
3891          * The filter status descriptor is reported in rx queue 0,
3892          * while the tx queue for fdir filter programming has no
3893          * such constraints, can be non-zero queues.
3894          * To simplify it, choose FDIR vsi use queue 0 pair.
3895          * To make sure it will use queue 0 pair, queue allocation
3896          * need be done before this function is called
3897          */
3898         if (type != I40E_VSI_FDIR) {
3899                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3900                         if (ret < 0) {
3901                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3902                                                 vsi->seid, ret);
3903                                 goto fail_mem;
3904                         }
3905                         vsi->base_queue = ret;
3906         } else
3907                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3908
3909         /* VF has MSIX interrupt in VF range, don't allocate here */
3910         if (type == I40E_VSI_MAIN) {
3911                 ret = i40e_res_pool_alloc(&pf->msix_pool,
3912                                           RTE_MIN(vsi->nb_qps,
3913                                                   RTE_MAX_RXTX_INTR_VEC_ID));
3914                 if (ret < 0) {
3915                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
3916                                     vsi->seid, ret);
3917                         goto fail_queue_alloc;
3918                 }
3919                 vsi->msix_intr = ret;
3920                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
3921         } else if (type != I40E_VSI_SRIOV) {
3922                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3923                 if (ret < 0) {
3924                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3925                         goto fail_queue_alloc;
3926                 }
3927                 vsi->msix_intr = ret;
3928                 vsi->nb_msix = 1;
3929         } else {
3930                 vsi->msix_intr = 0;
3931                 vsi->nb_msix = 0;
3932         }
3933
3934         /* Add VSI */
3935         if (type == I40E_VSI_MAIN) {
3936                 /* For main VSI, no need to add since it's default one */
3937                 vsi->uplink_seid = pf->mac_seid;
3938                 vsi->seid = pf->main_vsi_seid;
3939                 /* Bind queues with specific MSIX interrupt */
3940                 /**
3941                  * Needs 2 interrupt at least, one for misc cause which will
3942                  * enabled from OS side, Another for queues binding the
3943                  * interrupt from device side only.
3944                  */
3945
3946                 /* Get default VSI parameters from hardware */
3947                 memset(&ctxt, 0, sizeof(ctxt));
3948                 ctxt.seid = vsi->seid;
3949                 ctxt.pf_num = hw->pf_id;
3950                 ctxt.uplink_seid = vsi->uplink_seid;
3951                 ctxt.vf_num = 0;
3952                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3953                 if (ret != I40E_SUCCESS) {
3954                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3955                         goto fail_msix_alloc;
3956                 }
3957                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3958                         sizeof(struct i40e_aqc_vsi_properties_data));
3959                 vsi->vsi_id = ctxt.vsi_number;
3960                 vsi->info.valid_sections = 0;
3961
3962                 /* Configure tc, enabled TC0 only */
3963                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3964                         I40E_SUCCESS) {
3965                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3966                         goto fail_msix_alloc;
3967                 }
3968
3969                 /* TC, queue mapping */
3970                 memset(&ctxt, 0, sizeof(ctxt));
3971                 vsi->info.valid_sections |=
3972                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3973                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3974                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3975                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3976                         sizeof(struct i40e_aqc_vsi_properties_data));
3977                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3978                                                 I40E_DEFAULT_TCMAP);
3979                 if (ret != I40E_SUCCESS) {
3980                         PMD_DRV_LOG(ERR, "Failed to configure "
3981                                     "TC queue mapping");
3982                         goto fail_msix_alloc;
3983                 }
3984                 ctxt.seid = vsi->seid;
3985                 ctxt.pf_num = hw->pf_id;
3986                 ctxt.uplink_seid = vsi->uplink_seid;
3987                 ctxt.vf_num = 0;
3988
3989                 /* Update VSI parameters */
3990                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3991                 if (ret != I40E_SUCCESS) {
3992                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3993                         goto fail_msix_alloc;
3994                 }
3995
3996                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3997                                                 sizeof(vsi->info.tc_mapping));
3998                 (void)rte_memcpy(&vsi->info.queue_mapping,
3999                                 &ctxt.info.queue_mapping,
4000                         sizeof(vsi->info.queue_mapping));
4001                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4002                 vsi->info.valid_sections = 0;
4003
4004                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4005                                 ETH_ADDR_LEN);
4006
4007                 /**
4008                  * Updating default filter settings are necessary to prevent
4009                  * reception of tagged packets.
4010                  * Some old firmware configurations load a default macvlan
4011                  * filter which accepts both tagged and untagged packets.
4012                  * The updating is to use a normal filter instead if needed.
4013                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4014                  * The firmware with correct configurations load the default
4015                  * macvlan filter which is expected and cannot be removed.
4016                  */
4017                 i40e_update_default_filter_setting(vsi);
4018                 i40e_config_qinq(hw, vsi);
4019         } else if (type == I40E_VSI_SRIOV) {
4020                 memset(&ctxt, 0, sizeof(ctxt));
4021                 /**
4022                  * For other VSI, the uplink_seid equals to uplink VSI's
4023                  * uplink_seid since they share same VEB
4024                  */
4025                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4026                 ctxt.pf_num = hw->pf_id;
4027                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4028                 ctxt.uplink_seid = vsi->uplink_seid;
4029                 ctxt.connection_type = 0x1;
4030                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4031
4032                 /**
4033                  * Do not configure switch ID to enable VEB switch by
4034                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
4035                  * if the source mac address of packet sent from VF is not
4036                  * listed in the VEB's mac table, the VEB will switch the
4037                  * packet back to the VF. Need to enable it when HW issue
4038                  * is fixed.
4039                  */
4040
4041                 /* Configure port/vlan */
4042                 ctxt.info.valid_sections |=
4043                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4044                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4045                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4046                                                 I40E_DEFAULT_TCMAP);
4047                 if (ret != I40E_SUCCESS) {
4048                         PMD_DRV_LOG(ERR, "Failed to configure "
4049                                     "TC queue mapping");
4050                         goto fail_msix_alloc;
4051                 }
4052                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4053                 ctxt.info.valid_sections |=
4054                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4055                 /**
4056                  * Since VSI is not created yet, only configure parameter,
4057                  * will add vsi below.
4058                  */
4059
4060                 i40e_config_qinq(hw, vsi);
4061         } else if (type == I40E_VSI_VMDQ2) {
4062                 memset(&ctxt, 0, sizeof(ctxt));
4063                 /*
4064                  * For other VSI, the uplink_seid equals to uplink VSI's
4065                  * uplink_seid since they share same VEB
4066                  */
4067                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4068                 ctxt.pf_num = hw->pf_id;
4069                 ctxt.vf_num = 0;
4070                 ctxt.uplink_seid = vsi->uplink_seid;
4071                 ctxt.connection_type = 0x1;
4072                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4073
4074                 ctxt.info.valid_sections |=
4075                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4076                 /* user_param carries flag to enable loop back */
4077                 if (user_param) {
4078                         ctxt.info.switch_id =
4079                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4080                         ctxt.info.switch_id |=
4081                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4082                 }
4083
4084                 /* Configure port/vlan */
4085                 ctxt.info.valid_sections |=
4086                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4087                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4088                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4089                                                 I40E_DEFAULT_TCMAP);
4090                 if (ret != I40E_SUCCESS) {
4091                         PMD_DRV_LOG(ERR, "Failed to configure "
4092                                         "TC queue mapping");
4093                         goto fail_msix_alloc;
4094                 }
4095                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4096                 ctxt.info.valid_sections |=
4097                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4098         } else if (type == I40E_VSI_FDIR) {
4099                 memset(&ctxt, 0, sizeof(ctxt));
4100                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4101                 ctxt.pf_num = hw->pf_id;
4102                 ctxt.vf_num = 0;
4103                 ctxt.uplink_seid = vsi->uplink_seid;
4104                 ctxt.connection_type = 0x1;     /* regular data port */
4105                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4106                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4107                                                 I40E_DEFAULT_TCMAP);
4108                 if (ret != I40E_SUCCESS) {
4109                         PMD_DRV_LOG(ERR, "Failed to configure "
4110                                         "TC queue mapping.");
4111                         goto fail_msix_alloc;
4112                 }
4113                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4114                 ctxt.info.valid_sections |=
4115                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4116         } else {
4117                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4118                 goto fail_msix_alloc;
4119         }
4120
4121         if (vsi->type != I40E_VSI_MAIN) {
4122                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4123                 if (ret != I40E_SUCCESS) {
4124                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4125                                     hw->aq.asq_last_status);
4126                         goto fail_msix_alloc;
4127                 }
4128                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4129                 vsi->info.valid_sections = 0;
4130                 vsi->seid = ctxt.seid;
4131                 vsi->vsi_id = ctxt.vsi_number;
4132                 vsi->sib_vsi_list.vsi = vsi;
4133                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4134                                 &vsi->sib_vsi_list, list);
4135         }
4136
4137         /* MAC/VLAN configuration */
4138         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4139         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4140
4141         ret = i40e_vsi_add_mac(vsi, &filter);
4142         if (ret != I40E_SUCCESS) {
4143                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4144                 goto fail_msix_alloc;
4145         }
4146
4147         /* Get VSI BW information */
4148         i40e_vsi_get_bw_config(vsi);
4149         return vsi;
4150 fail_msix_alloc:
4151         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4152 fail_queue_alloc:
4153         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4154 fail_mem:
4155         rte_free(vsi);
4156         return NULL;
4157 }
4158
4159 /* Configure vlan stripping on or off */
4160 int
4161 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4162 {
4163         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4164         struct i40e_vsi_context ctxt;
4165         uint8_t vlan_flags;
4166         int ret = I40E_SUCCESS;
4167
4168         /* Check if it has been already on or off */
4169         if (vsi->info.valid_sections &
4170                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4171                 if (on) {
4172                         if ((vsi->info.port_vlan_flags &
4173                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4174                                 return 0; /* already on */
4175                 } else {
4176                         if ((vsi->info.port_vlan_flags &
4177                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4178                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4179                                 return 0; /* already off */
4180                 }
4181         }
4182
4183         if (on)
4184                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4185         else
4186                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4187         vsi->info.valid_sections =
4188                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4189         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4190         vsi->info.port_vlan_flags |= vlan_flags;
4191         ctxt.seid = vsi->seid;
4192         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4193         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4194         if (ret)
4195                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4196                             on ? "enable" : "disable");
4197
4198         return ret;
4199 }
4200
4201 static int
4202 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4203 {
4204         struct rte_eth_dev_data *data = dev->data;
4205         int ret;
4206
4207         /* Apply vlan offload setting */
4208         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
4209
4210         /* Apply double-vlan setting, not implemented yet */
4211
4212         /* Apply pvid setting */
4213         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4214                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4215         if (ret)
4216                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4217
4218         return ret;
4219 }
4220
4221 static int
4222 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4223 {
4224         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4225
4226         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4227 }
4228
4229 static int
4230 i40e_update_flow_control(struct i40e_hw *hw)
4231 {
4232 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4233         struct i40e_link_status link_status;
4234         uint32_t rxfc = 0, txfc = 0, reg;
4235         uint8_t an_info;
4236         int ret;
4237
4238         memset(&link_status, 0, sizeof(link_status));
4239         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4240         if (ret != I40E_SUCCESS) {
4241                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4242                 goto write_reg; /* Disable flow control */
4243         }
4244
4245         an_info = hw->phy.link_info.an_info;
4246         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4247                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4248                 ret = I40E_ERR_NOT_READY;
4249                 goto write_reg; /* Disable flow control */
4250         }
4251         /**
4252          * If link auto negotiation is enabled, flow control needs to
4253          * be configured according to it
4254          */
4255         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4256         case I40E_LINK_PAUSE_RXTX:
4257                 rxfc = 1;
4258                 txfc = 1;
4259                 hw->fc.current_mode = I40E_FC_FULL;
4260                 break;
4261         case I40E_AQ_LINK_PAUSE_RX:
4262                 rxfc = 1;
4263                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4264                 break;
4265         case I40E_AQ_LINK_PAUSE_TX:
4266                 txfc = 1;
4267                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4268                 break;
4269         default:
4270                 hw->fc.current_mode = I40E_FC_NONE;
4271                 break;
4272         }
4273
4274 write_reg:
4275         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4276                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4277         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4278         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4279         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4280         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4281
4282         return ret;
4283 }
4284
4285 /* PF setup */
4286 static int
4287 i40e_pf_setup(struct i40e_pf *pf)
4288 {
4289         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4290         struct i40e_filter_control_settings settings;
4291         struct i40e_vsi *vsi;
4292         int ret;
4293
4294         /* Clear all stats counters */
4295         pf->offset_loaded = FALSE;
4296         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4297         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4298
4299         ret = i40e_pf_get_switch_config(pf);
4300         if (ret != I40E_SUCCESS) {
4301                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4302                 return ret;
4303         }
4304         if (pf->flags & I40E_FLAG_FDIR) {
4305                 /* make queue allocated first, let FDIR use queue pair 0*/
4306                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4307                 if (ret != I40E_FDIR_QUEUE_ID) {
4308                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4309                                     " ret =%d", ret);
4310                         pf->flags &= ~I40E_FLAG_FDIR;
4311                 }
4312         }
4313         /*  main VSI setup */
4314         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4315         if (!vsi) {
4316                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4317                 return I40E_ERR_NOT_READY;
4318         }
4319         pf->main_vsi = vsi;
4320
4321         /* Configure filter control */
4322         memset(&settings, 0, sizeof(settings));
4323         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4324                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4325         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4326                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4327         else {
4328                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4329                                                 hw->func_caps.rss_table_size);
4330                 return I40E_ERR_PARAM;
4331         }
4332         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4333                         "size: %u\n", hw->func_caps.rss_table_size);
4334         pf->hash_lut_size = hw->func_caps.rss_table_size;
4335
4336         /* Enable ethtype and macvlan filters */
4337         settings.enable_ethtype = TRUE;
4338         settings.enable_macvlan = TRUE;
4339         ret = i40e_set_filter_control(hw, &settings);
4340         if (ret)
4341                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4342                                                                 ret);
4343
4344         /* Update flow control according to the auto negotiation */
4345         i40e_update_flow_control(hw);
4346
4347         return I40E_SUCCESS;
4348 }
4349
4350 int
4351 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4352 {
4353         uint32_t reg;
4354         uint16_t j;
4355
4356         /**
4357          * Set or clear TX Queue Disable flags,
4358          * which is required by hardware.
4359          */
4360         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4361         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4362
4363         /* Wait until the request is finished */
4364         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4365                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4366                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4367                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4368                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4369                                                         & 0x1))) {
4370                         break;
4371                 }
4372         }
4373         if (on) {
4374                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4375                         return I40E_SUCCESS; /* already on, skip next steps */
4376
4377                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4378                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4379         } else {
4380                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4381                         return I40E_SUCCESS; /* already off, skip next steps */
4382                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4383         }
4384         /* Write the register */
4385         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4386         /* Check the result */
4387         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4388                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4389                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4390                 if (on) {
4391                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4392                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4393                                 break;
4394                 } else {
4395                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4396                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4397                                 break;
4398                 }
4399         }
4400         /* Check if it is timeout */
4401         if (j >= I40E_CHK_Q_ENA_COUNT) {
4402                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4403                             (on ? "enable" : "disable"), q_idx);
4404                 return I40E_ERR_TIMEOUT;
4405         }
4406
4407         return I40E_SUCCESS;
4408 }
4409
4410 /* Swith on or off the tx queues */
4411 static int
4412 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4413 {
4414         struct rte_eth_dev_data *dev_data = pf->dev_data;
4415         struct i40e_tx_queue *txq;
4416         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4417         uint16_t i;
4418         int ret;
4419
4420         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4421                 txq = dev_data->tx_queues[i];
4422                 /* Don't operate the queue if not configured or
4423                  * if starting only per queue */
4424                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4425                         continue;
4426                 if (on)
4427                         ret = i40e_dev_tx_queue_start(dev, i);
4428                 else
4429                         ret = i40e_dev_tx_queue_stop(dev, i);
4430                 if ( ret != I40E_SUCCESS)
4431                         return ret;
4432         }
4433
4434         return I40E_SUCCESS;
4435 }
4436
4437 int
4438 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4439 {
4440         uint32_t reg;
4441         uint16_t j;
4442
4443         /* Wait until the request is finished */
4444         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4445                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4446                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4447                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4448                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4449                         break;
4450         }
4451
4452         if (on) {
4453                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4454                         return I40E_SUCCESS; /* Already on, skip next steps */
4455                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4456         } else {
4457                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4458                         return I40E_SUCCESS; /* Already off, skip next steps */
4459                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4460         }
4461
4462         /* Write the register */
4463         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4464         /* Check the result */
4465         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4466                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4467                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4468                 if (on) {
4469                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4470                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4471                                 break;
4472                 } else {
4473                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4474                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4475                                 break;
4476                 }
4477         }
4478
4479         /* Check if it is timeout */
4480         if (j >= I40E_CHK_Q_ENA_COUNT) {
4481                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4482                             (on ? "enable" : "disable"), q_idx);
4483                 return I40E_ERR_TIMEOUT;
4484         }
4485
4486         return I40E_SUCCESS;
4487 }
4488 /* Switch on or off the rx queues */
4489 static int
4490 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4491 {
4492         struct rte_eth_dev_data *dev_data = pf->dev_data;
4493         struct i40e_rx_queue *rxq;
4494         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4495         uint16_t i;
4496         int ret;
4497
4498         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4499                 rxq = dev_data->rx_queues[i];
4500                 /* Don't operate the queue if not configured or
4501                  * if starting only per queue */
4502                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4503                         continue;
4504                 if (on)
4505                         ret = i40e_dev_rx_queue_start(dev, i);
4506                 else
4507                         ret = i40e_dev_rx_queue_stop(dev, i);
4508                 if (ret != I40E_SUCCESS)
4509                         return ret;
4510         }
4511
4512         return I40E_SUCCESS;
4513 }
4514
4515 /* Switch on or off all the rx/tx queues */
4516 int
4517 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4518 {
4519         int ret;
4520
4521         if (on) {
4522                 /* enable rx queues before enabling tx queues */
4523                 ret = i40e_dev_switch_rx_queues(pf, on);
4524                 if (ret) {
4525                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4526                         return ret;
4527                 }
4528                 ret = i40e_dev_switch_tx_queues(pf, on);
4529         } else {
4530                 /* Stop tx queues before stopping rx queues */
4531                 ret = i40e_dev_switch_tx_queues(pf, on);
4532                 if (ret) {
4533                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4534                         return ret;
4535                 }
4536                 ret = i40e_dev_switch_rx_queues(pf, on);
4537         }
4538
4539         return ret;
4540 }
4541
4542 /* Initialize VSI for TX */
4543 static int
4544 i40e_dev_tx_init(struct i40e_pf *pf)
4545 {
4546         struct rte_eth_dev_data *data = pf->dev_data;
4547         uint16_t i;
4548         uint32_t ret = I40E_SUCCESS;
4549         struct i40e_tx_queue *txq;
4550
4551         for (i = 0; i < data->nb_tx_queues; i++) {
4552                 txq = data->tx_queues[i];
4553                 if (!txq || !txq->q_set)
4554                         continue;
4555                 ret = i40e_tx_queue_init(txq);
4556                 if (ret != I40E_SUCCESS)
4557                         break;
4558         }
4559         if (ret == I40E_SUCCESS)
4560                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4561                                      ->eth_dev);
4562
4563         return ret;
4564 }
4565
4566 /* Initialize VSI for RX */
4567 static int
4568 i40e_dev_rx_init(struct i40e_pf *pf)
4569 {
4570         struct rte_eth_dev_data *data = pf->dev_data;
4571         int ret = I40E_SUCCESS;
4572         uint16_t i;
4573         struct i40e_rx_queue *rxq;
4574
4575         i40e_pf_config_mq_rx(pf);
4576         for (i = 0; i < data->nb_rx_queues; i++) {
4577                 rxq = data->rx_queues[i];
4578                 if (!rxq || !rxq->q_set)
4579                         continue;
4580
4581                 ret = i40e_rx_queue_init(rxq);
4582                 if (ret != I40E_SUCCESS) {
4583                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4584                                     "initialization");
4585                         break;
4586                 }
4587         }
4588         if (ret == I40E_SUCCESS)
4589                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4590                                      ->eth_dev);
4591
4592         return ret;
4593 }
4594
4595 static int
4596 i40e_dev_rxtx_init(struct i40e_pf *pf)
4597 {
4598         int err;
4599
4600         err = i40e_dev_tx_init(pf);
4601         if (err) {
4602                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4603                 return err;
4604         }
4605         err = i40e_dev_rx_init(pf);
4606         if (err) {
4607                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4608                 return err;
4609         }
4610
4611         return err;
4612 }
4613
4614 static int
4615 i40e_vmdq_setup(struct rte_eth_dev *dev)
4616 {
4617         struct rte_eth_conf *conf = &dev->data->dev_conf;
4618         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4619         int i, err, conf_vsis, j, loop;
4620         struct i40e_vsi *vsi;
4621         struct i40e_vmdq_info *vmdq_info;
4622         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4623         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4624
4625         /*
4626          * Disable interrupt to avoid message from VF. Furthermore, it will
4627          * avoid race condition in VSI creation/destroy.
4628          */
4629         i40e_pf_disable_irq0(hw);
4630
4631         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4632                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4633                 return -ENOTSUP;
4634         }
4635
4636         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4637         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4638                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4639                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4640                         pf->max_nb_vmdq_vsi);
4641                 return -ENOTSUP;
4642         }
4643
4644         if (pf->vmdq != NULL) {
4645                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4646                 return 0;
4647         }
4648
4649         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4650                                 sizeof(*vmdq_info) * conf_vsis, 0);
4651
4652         if (pf->vmdq == NULL) {
4653                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4654                 return -ENOMEM;
4655         }
4656
4657         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4658
4659         /* Create VMDQ VSI */
4660         for (i = 0; i < conf_vsis; i++) {
4661                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4662                                 vmdq_conf->enable_loop_back);
4663                 if (vsi == NULL) {
4664                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4665                         err = -1;
4666                         goto err_vsi_setup;
4667                 }
4668                 vmdq_info = &pf->vmdq[i];
4669                 vmdq_info->pf = pf;
4670                 vmdq_info->vsi = vsi;
4671         }
4672         pf->nb_cfg_vmdq_vsi = conf_vsis;
4673
4674         /* Configure Vlan */
4675         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4676         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4677                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4678                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4679                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4680                                         vmdq_conf->pool_map[i].vlan_id, j);
4681
4682                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4683                                                 vmdq_conf->pool_map[i].vlan_id);
4684                                 if (err) {
4685                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4686                                         err = -1;
4687                                         goto err_vsi_setup;
4688                                 }
4689                         }
4690                 }
4691         }
4692
4693         i40e_pf_enable_irq0(hw);
4694
4695         return 0;
4696
4697 err_vsi_setup:
4698         for (i = 0; i < conf_vsis; i++)
4699                 if (pf->vmdq[i].vsi == NULL)
4700                         break;
4701                 else
4702                         i40e_vsi_release(pf->vmdq[i].vsi);
4703
4704         rte_free(pf->vmdq);
4705         pf->vmdq = NULL;
4706         i40e_pf_enable_irq0(hw);
4707         return err;
4708 }
4709
4710 static void
4711 i40e_stat_update_32(struct i40e_hw *hw,
4712                    uint32_t reg,
4713                    bool offset_loaded,
4714                    uint64_t *offset,
4715                    uint64_t *stat)
4716 {
4717         uint64_t new_data;
4718
4719         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4720         if (!offset_loaded)
4721                 *offset = new_data;
4722
4723         if (new_data >= *offset)
4724                 *stat = (uint64_t)(new_data - *offset);
4725         else
4726                 *stat = (uint64_t)((new_data +
4727                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4728 }
4729
4730 static void
4731 i40e_stat_update_48(struct i40e_hw *hw,
4732                    uint32_t hireg,
4733                    uint32_t loreg,
4734                    bool offset_loaded,
4735                    uint64_t *offset,
4736                    uint64_t *stat)
4737 {
4738         uint64_t new_data;
4739
4740         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4741         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4742                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4743
4744         if (!offset_loaded)
4745                 *offset = new_data;
4746
4747         if (new_data >= *offset)
4748                 *stat = new_data - *offset;
4749         else
4750                 *stat = (uint64_t)((new_data +
4751                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4752
4753         *stat &= I40E_48_BIT_MASK;
4754 }
4755
4756 /* Disable IRQ0 */
4757 void
4758 i40e_pf_disable_irq0(struct i40e_hw *hw)
4759 {
4760         /* Disable all interrupt types */
4761         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4762         I40E_WRITE_FLUSH(hw);
4763 }
4764
4765 /* Enable IRQ0 */
4766 void
4767 i40e_pf_enable_irq0(struct i40e_hw *hw)
4768 {
4769         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4770                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4771                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4772                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4773         I40E_WRITE_FLUSH(hw);
4774 }
4775
4776 static void
4777 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4778 {
4779         /* read pending request and disable first */
4780         i40e_pf_disable_irq0(hw);
4781         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4782         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4783                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4784
4785         if (no_queue)
4786                 /* Link no queues with irq0 */
4787                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4788                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4789 }
4790
4791 static void
4792 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4793 {
4794         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4795         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4796         int i;
4797         uint16_t abs_vf_id;
4798         uint32_t index, offset, val;
4799
4800         if (!pf->vfs)
4801                 return;
4802         /**
4803          * Try to find which VF trigger a reset, use absolute VF id to access
4804          * since the reg is global register.
4805          */
4806         for (i = 0; i < pf->vf_num; i++) {
4807                 abs_vf_id = hw->func_caps.vf_base_id + i;
4808                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4809                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4810                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4811                 /* VFR event occured */
4812                 if (val & (0x1 << offset)) {
4813                         int ret;
4814
4815                         /* Clear the event first */
4816                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4817                                                         (0x1 << offset));
4818                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4819                         /**
4820                          * Only notify a VF reset event occured,
4821                          * don't trigger another SW reset
4822                          */
4823                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4824                         if (ret != I40E_SUCCESS)
4825                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4826                 }
4827         }
4828 }
4829
4830 static void
4831 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4832 {
4833         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4834         struct i40e_arq_event_info info;
4835         uint16_t pending, opcode;
4836         int ret;
4837
4838         info.buf_len = I40E_AQ_BUF_SZ;
4839         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4840         if (!info.msg_buf) {
4841                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4842                 return;
4843         }
4844
4845         pending = 1;
4846         while (pending) {
4847                 ret = i40e_clean_arq_element(hw, &info, &pending);
4848
4849                 if (ret != I40E_SUCCESS) {
4850                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4851                                     "aq_err: %u", hw->aq.asq_last_status);
4852                         break;
4853                 }
4854                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4855
4856                 switch (opcode) {
4857                 case i40e_aqc_opc_send_msg_to_pf:
4858                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4859                         i40e_pf_host_handle_vf_msg(dev,
4860                                         rte_le_to_cpu_16(info.desc.retval),
4861                                         rte_le_to_cpu_32(info.desc.cookie_high),
4862                                         rte_le_to_cpu_32(info.desc.cookie_low),
4863                                         info.msg_buf,
4864                                         info.msg_len);
4865                         break;
4866                 default:
4867                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4868                                     opcode);
4869                         break;
4870                 }
4871         }
4872         rte_free(info.msg_buf);
4873 }
4874
4875 /*
4876  * Interrupt handler is registered as the alarm callback for handling LSC
4877  * interrupt in a definite of time, in order to wait the NIC into a stable
4878  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4879  * no need for link down interrupt.
4880  */
4881 static void
4882 i40e_dev_interrupt_delayed_handler(void *param)
4883 {
4884         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4885         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4886         uint32_t icr0;
4887
4888         /* read interrupt causes again */
4889         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4890
4891 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4892         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4893                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4894         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4895                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4896         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4897                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4898         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4899                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4900         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4901                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4902                                                                 "state\n");
4903         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4904                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4905         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4906                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4907 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4908
4909         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4910                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4911                 i40e_dev_handle_vfr_event(dev);
4912         }
4913         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4914                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4915                 i40e_dev_handle_aq_msg(dev);
4916         }
4917
4918         /* handle the link up interrupt in an alarm callback */
4919         i40e_dev_link_update(dev, 0);
4920         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4921
4922         i40e_pf_enable_irq0(hw);
4923         rte_intr_enable(&(dev->pci_dev->intr_handle));
4924 }
4925
4926 /**
4927  * Interrupt handler triggered by NIC  for handling
4928  * specific interrupt.
4929  *
4930  * @param handle
4931  *  Pointer to interrupt handle.
4932  * @param param
4933  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4934  *
4935  * @return
4936  *  void
4937  */
4938 static void
4939 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4940                            void *param)
4941 {
4942         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4943         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4944         uint32_t icr0;
4945
4946         /* Disable interrupt */
4947         i40e_pf_disable_irq0(hw);
4948
4949         /* read out interrupt causes */
4950         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4951
4952         /* No interrupt event indicated */
4953         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4954                 PMD_DRV_LOG(INFO, "No interrupt event");
4955                 goto done;
4956         }
4957 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4958         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4959                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4960         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4961                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4962         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4963                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4964         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4965                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4966         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4967                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4968         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4969                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4970         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4971                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4972 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4973
4974         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4975                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4976                 i40e_dev_handle_vfr_event(dev);
4977         }
4978         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4979                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4980                 i40e_dev_handle_aq_msg(dev);
4981         }
4982
4983         /* Link Status Change interrupt */
4984         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4985 #define I40E_US_PER_SECOND 1000000
4986                 struct rte_eth_link link;
4987
4988                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4989                 memset(&link, 0, sizeof(link));
4990                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4991                 i40e_dev_link_update(dev, 0);
4992
4993                 /*
4994                  * For link up interrupt, it needs to wait 1 second to let the
4995                  * hardware be a stable state. Otherwise several consecutive
4996                  * interrupts can be observed.
4997                  * For link down interrupt, no need to wait.
4998                  */
4999                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5000                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5001                         return;
5002                 else
5003                         _rte_eth_dev_callback_process(dev,
5004                                 RTE_ETH_EVENT_INTR_LSC);
5005         }
5006
5007 done:
5008         /* Enable interrupt */
5009         i40e_pf_enable_irq0(hw);
5010         rte_intr_enable(&(dev->pci_dev->intr_handle));
5011 }
5012
5013 static int
5014 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5015                          struct i40e_macvlan_filter *filter,
5016                          int total)
5017 {
5018         int ele_num, ele_buff_size;
5019         int num, actual_num, i;
5020         uint16_t flags;
5021         int ret = I40E_SUCCESS;
5022         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5023         struct i40e_aqc_add_macvlan_element_data *req_list;
5024
5025         if (filter == NULL  || total == 0)
5026                 return I40E_ERR_PARAM;
5027         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5028         ele_buff_size = hw->aq.asq_buf_size;
5029
5030         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5031         if (req_list == NULL) {
5032                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5033                 return I40E_ERR_NO_MEMORY;
5034         }
5035
5036         num = 0;
5037         do {
5038                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5039                 memset(req_list, 0, ele_buff_size);
5040
5041                 for (i = 0; i < actual_num; i++) {
5042                         (void)rte_memcpy(req_list[i].mac_addr,
5043                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5044                         req_list[i].vlan_tag =
5045                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5046
5047                         switch (filter[num + i].filter_type) {
5048                         case RTE_MAC_PERFECT_MATCH:
5049                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5050                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5051                                 break;
5052                         case RTE_MACVLAN_PERFECT_MATCH:
5053                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5054                                 break;
5055                         case RTE_MAC_HASH_MATCH:
5056                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5057                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5058                                 break;
5059                         case RTE_MACVLAN_HASH_MATCH:
5060                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5061                                 break;
5062                         default:
5063                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5064                                 ret = I40E_ERR_PARAM;
5065                                 goto DONE;
5066                         }
5067
5068                         req_list[i].queue_number = 0;
5069
5070                         req_list[i].flags = rte_cpu_to_le_16(flags);
5071                 }
5072
5073                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5074                                                 actual_num, NULL);
5075                 if (ret != I40E_SUCCESS) {
5076                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5077                         goto DONE;
5078                 }
5079                 num += actual_num;
5080         } while (num < total);
5081
5082 DONE:
5083         rte_free(req_list);
5084         return ret;
5085 }
5086
5087 static int
5088 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5089                             struct i40e_macvlan_filter *filter,
5090                             int total)
5091 {
5092         int ele_num, ele_buff_size;
5093         int num, actual_num, i;
5094         uint16_t flags;
5095         int ret = I40E_SUCCESS;
5096         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5097         struct i40e_aqc_remove_macvlan_element_data *req_list;
5098
5099         if (filter == NULL  || total == 0)
5100                 return I40E_ERR_PARAM;
5101
5102         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5103         ele_buff_size = hw->aq.asq_buf_size;
5104
5105         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5106         if (req_list == NULL) {
5107                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5108                 return I40E_ERR_NO_MEMORY;
5109         }
5110
5111         num = 0;
5112         do {
5113                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5114                 memset(req_list, 0, ele_buff_size);
5115
5116                 for (i = 0; i < actual_num; i++) {
5117                         (void)rte_memcpy(req_list[i].mac_addr,
5118                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5119                         req_list[i].vlan_tag =
5120                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5121
5122                         switch (filter[num + i].filter_type) {
5123                         case RTE_MAC_PERFECT_MATCH:
5124                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5125                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5126                                 break;
5127                         case RTE_MACVLAN_PERFECT_MATCH:
5128                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5129                                 break;
5130                         case RTE_MAC_HASH_MATCH:
5131                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5132                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5133                                 break;
5134                         case RTE_MACVLAN_HASH_MATCH:
5135                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5136                                 break;
5137                         default:
5138                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5139                                 ret = I40E_ERR_PARAM;
5140                                 goto DONE;
5141                         }
5142                         req_list[i].flags = rte_cpu_to_le_16(flags);
5143                 }
5144
5145                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5146                                                 actual_num, NULL);
5147                 if (ret != I40E_SUCCESS) {
5148                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5149                         goto DONE;
5150                 }
5151                 num += actual_num;
5152         } while (num < total);
5153
5154 DONE:
5155         rte_free(req_list);
5156         return ret;
5157 }
5158
5159 /* Find out specific MAC filter */
5160 static struct i40e_mac_filter *
5161 i40e_find_mac_filter(struct i40e_vsi *vsi,
5162                          struct ether_addr *macaddr)
5163 {
5164         struct i40e_mac_filter *f;
5165
5166         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5167                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5168                         return f;
5169         }
5170
5171         return NULL;
5172 }
5173
5174 static bool
5175 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5176                          uint16_t vlan_id)
5177 {
5178         uint32_t vid_idx, vid_bit;
5179
5180         if (vlan_id > ETH_VLAN_ID_MAX)
5181                 return 0;
5182
5183         vid_idx = I40E_VFTA_IDX(vlan_id);
5184         vid_bit = I40E_VFTA_BIT(vlan_id);
5185
5186         if (vsi->vfta[vid_idx] & vid_bit)
5187                 return 1;
5188         else
5189                 return 0;
5190 }
5191
5192 static void
5193 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5194                          uint16_t vlan_id, bool on)
5195 {
5196         uint32_t vid_idx, vid_bit;
5197
5198         if (vlan_id > ETH_VLAN_ID_MAX)
5199                 return;
5200
5201         vid_idx = I40E_VFTA_IDX(vlan_id);
5202         vid_bit = I40E_VFTA_BIT(vlan_id);
5203
5204         if (on)
5205                 vsi->vfta[vid_idx] |= vid_bit;
5206         else
5207                 vsi->vfta[vid_idx] &= ~vid_bit;
5208 }
5209
5210 /**
5211  * Find all vlan options for specific mac addr,
5212  * return with actual vlan found.
5213  */
5214 static inline int
5215 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5216                            struct i40e_macvlan_filter *mv_f,
5217                            int num, struct ether_addr *addr)
5218 {
5219         int i;
5220         uint32_t j, k;
5221
5222         /**
5223          * Not to use i40e_find_vlan_filter to decrease the loop time,
5224          * although the code looks complex.
5225           */
5226         if (num < vsi->vlan_num)
5227                 return I40E_ERR_PARAM;
5228
5229         i = 0;
5230         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5231                 if (vsi->vfta[j]) {
5232                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5233                                 if (vsi->vfta[j] & (1 << k)) {
5234                                         if (i > num - 1) {
5235                                                 PMD_DRV_LOG(ERR, "vlan number "
5236                                                             "not match");
5237                                                 return I40E_ERR_PARAM;
5238                                         }
5239                                         (void)rte_memcpy(&mv_f[i].macaddr,
5240                                                         addr, ETH_ADDR_LEN);
5241                                         mv_f[i].vlan_id =
5242                                                 j * I40E_UINT32_BIT_SIZE + k;
5243                                         i++;
5244                                 }
5245                         }
5246                 }
5247         }
5248         return I40E_SUCCESS;
5249 }
5250
5251 static inline int
5252 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5253                            struct i40e_macvlan_filter *mv_f,
5254                            int num,
5255                            uint16_t vlan)
5256 {
5257         int i = 0;
5258         struct i40e_mac_filter *f;
5259
5260         if (num < vsi->mac_num)
5261                 return I40E_ERR_PARAM;
5262
5263         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5264                 if (i > num - 1) {
5265                         PMD_DRV_LOG(ERR, "buffer number not match");
5266                         return I40E_ERR_PARAM;
5267                 }
5268                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5269                                 ETH_ADDR_LEN);
5270                 mv_f[i].vlan_id = vlan;
5271                 mv_f[i].filter_type = f->mac_info.filter_type;
5272                 i++;
5273         }
5274
5275         return I40E_SUCCESS;
5276 }
5277
5278 static int
5279 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5280 {
5281         int i, num;
5282         struct i40e_mac_filter *f;
5283         struct i40e_macvlan_filter *mv_f;
5284         int ret = I40E_SUCCESS;
5285
5286         if (vsi == NULL || vsi->mac_num == 0)
5287                 return I40E_ERR_PARAM;
5288
5289         /* Case that no vlan is set */
5290         if (vsi->vlan_num == 0)
5291                 num = vsi->mac_num;
5292         else
5293                 num = vsi->mac_num * vsi->vlan_num;
5294
5295         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5296         if (mv_f == NULL) {
5297                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5298                 return I40E_ERR_NO_MEMORY;
5299         }
5300
5301         i = 0;
5302         if (vsi->vlan_num == 0) {
5303                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5304                         (void)rte_memcpy(&mv_f[i].macaddr,
5305                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5306                         mv_f[i].vlan_id = 0;
5307                         i++;
5308                 }
5309         } else {
5310                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5311                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5312                                         vsi->vlan_num, &f->mac_info.mac_addr);
5313                         if (ret != I40E_SUCCESS)
5314                                 goto DONE;
5315                         i += vsi->vlan_num;
5316                 }
5317         }
5318
5319         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5320 DONE:
5321         rte_free(mv_f);
5322
5323         return ret;
5324 }
5325
5326 int
5327 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5328 {
5329         struct i40e_macvlan_filter *mv_f;
5330         int mac_num;
5331         int ret = I40E_SUCCESS;
5332
5333         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5334                 return I40E_ERR_PARAM;
5335
5336         /* If it's already set, just return */
5337         if (i40e_find_vlan_filter(vsi,vlan))
5338                 return I40E_SUCCESS;
5339
5340         mac_num = vsi->mac_num;
5341
5342         if (mac_num == 0) {
5343                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5344                 return I40E_ERR_PARAM;
5345         }
5346
5347         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5348
5349         if (mv_f == NULL) {
5350                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5351                 return I40E_ERR_NO_MEMORY;
5352         }
5353
5354         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5355
5356         if (ret != I40E_SUCCESS)
5357                 goto DONE;
5358
5359         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5360
5361         if (ret != I40E_SUCCESS)
5362                 goto DONE;
5363
5364         i40e_set_vlan_filter(vsi, vlan, 1);
5365
5366         vsi->vlan_num++;
5367         ret = I40E_SUCCESS;
5368 DONE:
5369         rte_free(mv_f);
5370         return ret;
5371 }
5372
5373 int
5374 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5375 {
5376         struct i40e_macvlan_filter *mv_f;
5377         int mac_num;
5378         int ret = I40E_SUCCESS;
5379
5380         /**
5381          * Vlan 0 is the generic filter for untagged packets
5382          * and can't be removed.
5383          */
5384         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5385                 return I40E_ERR_PARAM;
5386
5387         /* If can't find it, just return */
5388         if (!i40e_find_vlan_filter(vsi, vlan))
5389                 return I40E_ERR_PARAM;
5390
5391         mac_num = vsi->mac_num;
5392
5393         if (mac_num == 0) {
5394                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5395                 return I40E_ERR_PARAM;
5396         }
5397
5398         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5399
5400         if (mv_f == NULL) {
5401                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5402                 return I40E_ERR_NO_MEMORY;
5403         }
5404
5405         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5406
5407         if (ret != I40E_SUCCESS)
5408                 goto DONE;
5409
5410         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5411
5412         if (ret != I40E_SUCCESS)
5413                 goto DONE;
5414
5415         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5416         if (vsi->vlan_num == 1) {
5417                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5418                 if (ret != I40E_SUCCESS)
5419                         goto DONE;
5420
5421                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5422                 if (ret != I40E_SUCCESS)
5423                         goto DONE;
5424         }
5425
5426         i40e_set_vlan_filter(vsi, vlan, 0);
5427
5428         vsi->vlan_num--;
5429         ret = I40E_SUCCESS;
5430 DONE:
5431         rte_free(mv_f);
5432         return ret;
5433 }
5434
5435 int
5436 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5437 {
5438         struct i40e_mac_filter *f;
5439         struct i40e_macvlan_filter *mv_f;
5440         int i, vlan_num = 0;
5441         int ret = I40E_SUCCESS;
5442
5443         /* If it's add and we've config it, return */
5444         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5445         if (f != NULL)
5446                 return I40E_SUCCESS;
5447         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5448                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5449
5450                 /**
5451                  * If vlan_num is 0, that's the first time to add mac,
5452                  * set mask for vlan_id 0.
5453                  */
5454                 if (vsi->vlan_num == 0) {
5455                         i40e_set_vlan_filter(vsi, 0, 1);
5456                         vsi->vlan_num = 1;
5457                 }
5458                 vlan_num = vsi->vlan_num;
5459         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5460                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5461                 vlan_num = 1;
5462
5463         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5464         if (mv_f == NULL) {
5465                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5466                 return I40E_ERR_NO_MEMORY;
5467         }
5468
5469         for (i = 0; i < vlan_num; i++) {
5470                 mv_f[i].filter_type = mac_filter->filter_type;
5471                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5472                                 ETH_ADDR_LEN);
5473         }
5474
5475         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5476                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5477                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5478                                         &mac_filter->mac_addr);
5479                 if (ret != I40E_SUCCESS)
5480                         goto DONE;
5481         }
5482
5483         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5484         if (ret != I40E_SUCCESS)
5485                 goto DONE;
5486
5487         /* Add the mac addr into mac list */
5488         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5489         if (f == NULL) {
5490                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5491                 ret = I40E_ERR_NO_MEMORY;
5492                 goto DONE;
5493         }
5494         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5495                         ETH_ADDR_LEN);
5496         f->mac_info.filter_type = mac_filter->filter_type;
5497         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5498         vsi->mac_num++;
5499
5500         ret = I40E_SUCCESS;
5501 DONE:
5502         rte_free(mv_f);
5503
5504         return ret;
5505 }
5506
5507 int
5508 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5509 {
5510         struct i40e_mac_filter *f;
5511         struct i40e_macvlan_filter *mv_f;
5512         int i, vlan_num;
5513         enum rte_mac_filter_type filter_type;
5514         int ret = I40E_SUCCESS;
5515
5516         /* Can't find it, return an error */
5517         f = i40e_find_mac_filter(vsi, addr);
5518         if (f == NULL)
5519                 return I40E_ERR_PARAM;
5520
5521         vlan_num = vsi->vlan_num;
5522         filter_type = f->mac_info.filter_type;
5523         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5524                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5525                 if (vlan_num == 0) {
5526                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5527                         return I40E_ERR_PARAM;
5528                 }
5529         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5530                         filter_type == RTE_MAC_HASH_MATCH)
5531                 vlan_num = 1;
5532
5533         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5534         if (mv_f == NULL) {
5535                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5536                 return I40E_ERR_NO_MEMORY;
5537         }
5538
5539         for (i = 0; i < vlan_num; i++) {
5540                 mv_f[i].filter_type = filter_type;
5541                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5542                                 ETH_ADDR_LEN);
5543         }
5544         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5545                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5546                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5547                 if (ret != I40E_SUCCESS)
5548                         goto DONE;
5549         }
5550
5551         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5552         if (ret != I40E_SUCCESS)
5553                 goto DONE;
5554
5555         /* Remove the mac addr into mac list */
5556         TAILQ_REMOVE(&vsi->mac_list, f, next);
5557         rte_free(f);
5558         vsi->mac_num--;
5559
5560         ret = I40E_SUCCESS;
5561 DONE:
5562         rte_free(mv_f);
5563         return ret;
5564 }
5565
5566 /* Configure hash enable flags for RSS */
5567 uint64_t
5568 i40e_config_hena(uint64_t flags)
5569 {
5570         uint64_t hena = 0;
5571
5572         if (!flags)
5573                 return hena;
5574
5575         if (flags & ETH_RSS_FRAG_IPV4)
5576                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5577         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5578                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5579         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5580                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5581         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5582                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5583         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5584                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5585         if (flags & ETH_RSS_FRAG_IPV6)
5586                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5587         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5588                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5589         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5590                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5591         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5592                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5593         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5594                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5595         if (flags & ETH_RSS_L2_PAYLOAD)
5596                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5597
5598         return hena;
5599 }
5600
5601 /* Parse the hash enable flags */
5602 uint64_t
5603 i40e_parse_hena(uint64_t flags)
5604 {
5605         uint64_t rss_hf = 0;
5606
5607         if (!flags)
5608                 return rss_hf;
5609         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5610                 rss_hf |= ETH_RSS_FRAG_IPV4;
5611         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5612                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5613         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5614                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5615         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5616                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5617         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5618                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5619         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5620                 rss_hf |= ETH_RSS_FRAG_IPV6;
5621         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5622                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5623         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5624                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5625         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5626                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5627         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5628                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5629         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5630                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5631
5632         return rss_hf;
5633 }
5634
5635 /* Disable RSS */
5636 static void
5637 i40e_pf_disable_rss(struct i40e_pf *pf)
5638 {
5639         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5640         uint64_t hena;
5641
5642         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5643         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5644         hena &= ~I40E_RSS_HENA_ALL;
5645         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5646         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5647         I40E_WRITE_FLUSH(hw);
5648 }
5649
5650 static int
5651 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5652 {
5653         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5654         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5655         int ret = 0;
5656
5657         if (!key || key_len == 0) {
5658                 PMD_DRV_LOG(DEBUG, "No key to be configured");
5659                 return 0;
5660         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5661                 sizeof(uint32_t)) {
5662                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5663                 return -EINVAL;
5664         }
5665
5666         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5667                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5668                         (struct i40e_aqc_get_set_rss_key_data *)key;
5669
5670                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5671                 if (ret)
5672                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5673                                      "via AQ");
5674         } else {
5675                 uint32_t *hash_key = (uint32_t *)key;
5676                 uint16_t i;
5677
5678                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5679                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5680                 I40E_WRITE_FLUSH(hw);
5681         }
5682
5683         return ret;
5684 }
5685
5686 static int
5687 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5688 {
5689         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5690         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5691         int ret;
5692
5693         if (!key || !key_len)
5694                 return -EINVAL;
5695
5696         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5697                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5698                         (struct i40e_aqc_get_set_rss_key_data *)key);
5699                 if (ret) {
5700                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5701                         return ret;
5702                 }
5703         } else {
5704                 uint32_t *key_dw = (uint32_t *)key;
5705                 uint16_t i;
5706
5707                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5708                         key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5709         }
5710         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5711
5712         return 0;
5713 }
5714
5715 static int
5716 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5717 {
5718         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5719         uint64_t rss_hf;
5720         uint64_t hena;
5721         int ret;
5722
5723         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5724                                rss_conf->rss_key_len);
5725         if (ret)
5726                 return ret;
5727
5728         rss_hf = rss_conf->rss_hf;
5729         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5730         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5731         hena &= ~I40E_RSS_HENA_ALL;
5732         hena |= i40e_config_hena(rss_hf);
5733         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5734         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5735         I40E_WRITE_FLUSH(hw);
5736
5737         return 0;
5738 }
5739
5740 static int
5741 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5742                          struct rte_eth_rss_conf *rss_conf)
5743 {
5744         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5745         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5746         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5747         uint64_t hena;
5748
5749         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5750         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5751         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5752                 if (rss_hf != 0) /* Enable RSS */
5753                         return -EINVAL;
5754                 return 0; /* Nothing to do */
5755         }
5756         /* RSS enabled */
5757         if (rss_hf == 0) /* Disable RSS */
5758                 return -EINVAL;
5759
5760         return i40e_hw_rss_hash_set(pf, rss_conf);
5761 }
5762
5763 static int
5764 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5765                            struct rte_eth_rss_conf *rss_conf)
5766 {
5767         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5768         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5769         uint64_t hena;
5770
5771         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5772                          &rss_conf->rss_key_len);
5773
5774         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5775         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5776         rss_conf->rss_hf = i40e_parse_hena(hena);
5777
5778         return 0;
5779 }
5780
5781 static int
5782 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5783 {
5784         switch (filter_type) {
5785         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5786                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5787                 break;
5788         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5789                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5790                 break;
5791         case RTE_TUNNEL_FILTER_IMAC_TENID:
5792                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5793                 break;
5794         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5795                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5796                 break;
5797         case ETH_TUNNEL_FILTER_IMAC:
5798                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5799                 break;
5800         default:
5801                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5802                 return -EINVAL;
5803         }
5804
5805         return 0;
5806 }
5807
5808 static int
5809 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5810                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5811                         uint8_t add)
5812 {
5813         uint16_t ip_type;
5814         uint8_t tun_type = 0;
5815         int val, ret = 0;
5816         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5817         struct i40e_vsi *vsi = pf->main_vsi;
5818         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5819         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5820
5821         cld_filter = rte_zmalloc("tunnel_filter",
5822                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5823                 0);
5824
5825         if (NULL == cld_filter) {
5826                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5827                 return -EINVAL;
5828         }
5829         pfilter = cld_filter;
5830
5831         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5832                         sizeof(struct ether_addr));
5833         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5834                         sizeof(struct ether_addr));
5835
5836         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5837         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5838                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5839                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5840                                 &tunnel_filter->ip_addr,
5841                                 sizeof(pfilter->ipaddr.v4.data));
5842         } else {
5843                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5844                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5845                                 &tunnel_filter->ip_addr,
5846                                 sizeof(pfilter->ipaddr.v6.data));
5847         }
5848
5849         /* check tunneled type */
5850         switch (tunnel_filter->tunnel_type) {
5851         case RTE_TUNNEL_TYPE_VXLAN:
5852                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5853                 break;
5854         case RTE_TUNNEL_TYPE_NVGRE:
5855                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5856                 break;
5857         default:
5858                 /* Other tunnel types is not supported. */
5859                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5860                 rte_free(cld_filter);
5861                 return -EINVAL;
5862         }
5863
5864         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5865                                                 &pfilter->flags);
5866         if (val < 0) {
5867                 rte_free(cld_filter);
5868                 return -EINVAL;
5869         }
5870
5871         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5872                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5873         pfilter->tenant_id = tunnel_filter->tenant_id;
5874         pfilter->queue_number = tunnel_filter->queue_id;
5875
5876         if (add)
5877                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5878         else
5879                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5880                                                 cld_filter, 1);
5881
5882         rte_free(cld_filter);
5883         return ret;
5884 }
5885
5886 static int
5887 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5888 {
5889         uint8_t i;
5890
5891         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5892                 if (pf->vxlan_ports[i] == port)
5893                         return i;
5894         }
5895
5896         return -1;
5897 }
5898
5899 static int
5900 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5901 {
5902         int  idx, ret;
5903         uint8_t filter_idx;
5904         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5905
5906         idx = i40e_get_vxlan_port_idx(pf, port);
5907
5908         /* Check if port already exists */
5909         if (idx >= 0) {
5910                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5911                 return -EINVAL;
5912         }
5913
5914         /* Now check if there is space to add the new port */
5915         idx = i40e_get_vxlan_port_idx(pf, 0);
5916         if (idx < 0) {
5917                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5918                         "not adding port %d", port);
5919                 return -ENOSPC;
5920         }
5921
5922         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5923                                         &filter_idx, NULL);
5924         if (ret < 0) {
5925                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5926                 return -1;
5927         }
5928
5929         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5930                          port,  filter_idx);
5931
5932         /* New port: add it and mark its index in the bitmap */
5933         pf->vxlan_ports[idx] = port;
5934         pf->vxlan_bitmap |= (1 << idx);
5935
5936         if (!(pf->flags & I40E_FLAG_VXLAN))
5937                 pf->flags |= I40E_FLAG_VXLAN;
5938
5939         return 0;
5940 }
5941
5942 static int
5943 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5944 {
5945         int idx;
5946         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5947
5948         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5949                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5950                 return -EINVAL;
5951         }
5952
5953         idx = i40e_get_vxlan_port_idx(pf, port);
5954
5955         if (idx < 0) {
5956                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5957                 return -EINVAL;
5958         }
5959
5960         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5961                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5962                 return -1;
5963         }
5964
5965         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5966                         port, idx);
5967
5968         pf->vxlan_ports[idx] = 0;
5969         pf->vxlan_bitmap &= ~(1 << idx);
5970
5971         if (!pf->vxlan_bitmap)
5972                 pf->flags &= ~I40E_FLAG_VXLAN;
5973
5974         return 0;
5975 }
5976
5977 /* Add UDP tunneling port */
5978 static int
5979 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5980                         struct rte_eth_udp_tunnel *udp_tunnel)
5981 {
5982         int ret = 0;
5983         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5984
5985         if (udp_tunnel == NULL)
5986                 return -EINVAL;
5987
5988         switch (udp_tunnel->prot_type) {
5989         case RTE_TUNNEL_TYPE_VXLAN:
5990                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5991                 break;
5992
5993         case RTE_TUNNEL_TYPE_GENEVE:
5994         case RTE_TUNNEL_TYPE_TEREDO:
5995                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5996                 ret = -1;
5997                 break;
5998
5999         default:
6000                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6001                 ret = -1;
6002                 break;
6003         }
6004
6005         return ret;
6006 }
6007
6008 /* Remove UDP tunneling port */
6009 static int
6010 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
6011                         struct rte_eth_udp_tunnel *udp_tunnel)
6012 {
6013         int ret = 0;
6014         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6015
6016         if (udp_tunnel == NULL)
6017                 return -EINVAL;
6018
6019         switch (udp_tunnel->prot_type) {
6020         case RTE_TUNNEL_TYPE_VXLAN:
6021                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6022                 break;
6023         case RTE_TUNNEL_TYPE_GENEVE:
6024         case RTE_TUNNEL_TYPE_TEREDO:
6025                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6026                 ret = -1;
6027                 break;
6028         default:
6029                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6030                 ret = -1;
6031                 break;
6032         }
6033
6034         return ret;
6035 }
6036
6037 /* Calculate the maximum number of contiguous PF queues that are configured */
6038 static int
6039 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6040 {
6041         struct rte_eth_dev_data *data = pf->dev_data;
6042         int i, num;
6043         struct i40e_rx_queue *rxq;
6044
6045         num = 0;
6046         for (i = 0; i < pf->lan_nb_qps; i++) {
6047                 rxq = data->rx_queues[i];
6048                 if (rxq && rxq->q_set)
6049                         num++;
6050                 else
6051                         break;
6052         }
6053
6054         return num;
6055 }
6056
6057 /* Configure RSS */
6058 static int
6059 i40e_pf_config_rss(struct i40e_pf *pf)
6060 {
6061         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6062         struct rte_eth_rss_conf rss_conf;
6063         uint32_t i, lut = 0;
6064         uint16_t j, num;
6065
6066         /*
6067          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6068          * It's necessary to calulate the actual PF queues that are configured.
6069          */
6070         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6071                 num = i40e_pf_calc_configured_queues_num(pf);
6072         else
6073                 num = pf->dev_data->nb_rx_queues;
6074
6075         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6076         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6077                         num);
6078
6079         if (num == 0) {
6080                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6081                 return -ENOTSUP;
6082         }
6083
6084         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6085                 if (j == num)
6086                         j = 0;
6087                 lut = (lut << 8) | (j & ((0x1 <<
6088                         hw->func_caps.rss_table_entry_width) - 1));
6089                 if ((i & 3) == 3)
6090                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6091         }
6092
6093         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6094         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6095                 i40e_pf_disable_rss(pf);
6096                 return 0;
6097         }
6098         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6099                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6100                 /* Random default keys */
6101                 static uint32_t rss_key_default[] = {0x6b793944,
6102                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6103                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6104                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6105
6106                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6107                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6108                                                         sizeof(uint32_t);
6109         }
6110
6111         return i40e_hw_rss_hash_set(pf, &rss_conf);
6112 }
6113
6114 static int
6115 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6116                                struct rte_eth_tunnel_filter_conf *filter)
6117 {
6118         if (pf == NULL || filter == NULL) {
6119                 PMD_DRV_LOG(ERR, "Invalid parameter");
6120                 return -EINVAL;
6121         }
6122
6123         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6124                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6125                 return -EINVAL;
6126         }
6127
6128         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6129                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6130                 return -EINVAL;
6131         }
6132
6133         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6134                 (is_zero_ether_addr(filter->outer_mac))) {
6135                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6136                 return -EINVAL;
6137         }
6138
6139         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6140                 (is_zero_ether_addr(filter->inner_mac))) {
6141                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6142                 return -EINVAL;
6143         }
6144
6145         return 0;
6146 }
6147
6148 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6149 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6150 static int
6151 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6152 {
6153         uint32_t val, reg;
6154         int ret = -EINVAL;
6155
6156         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6157         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6158
6159         if (len == 3) {
6160                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6161         } else if (len == 4) {
6162                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6163         } else {
6164                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6165                 return ret;
6166         }
6167
6168         if (reg != val) {
6169                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6170                                                    reg, NULL);
6171                 if (ret != 0)
6172                         return ret;
6173         } else {
6174                 ret = 0;
6175         }
6176         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6177                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6178
6179         return ret;
6180 }
6181
6182 static int
6183 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6184 {
6185         int ret = -EINVAL;
6186
6187         if (!hw || !cfg)
6188                 return -EINVAL;
6189
6190         switch (cfg->cfg_type) {
6191         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6192                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6193                 break;
6194         default:
6195                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6196                 break;
6197         }
6198
6199         return ret;
6200 }
6201
6202 static int
6203 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6204                                enum rte_filter_op filter_op,
6205                                void *arg)
6206 {
6207         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6208         int ret = I40E_ERR_PARAM;
6209
6210         switch (filter_op) {
6211         case RTE_ETH_FILTER_SET:
6212                 ret = i40e_dev_global_config_set(hw,
6213                         (struct rte_eth_global_cfg *)arg);
6214                 break;
6215         default:
6216                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6217                 break;
6218         }
6219
6220         return ret;
6221 }
6222
6223 static int
6224 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6225                           enum rte_filter_op filter_op,
6226                           void *arg)
6227 {
6228         struct rte_eth_tunnel_filter_conf *filter;
6229         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6230         int ret = I40E_SUCCESS;
6231
6232         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6233
6234         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6235                 return I40E_ERR_PARAM;
6236
6237         switch (filter_op) {
6238         case RTE_ETH_FILTER_NOP:
6239                 if (!(pf->flags & I40E_FLAG_VXLAN))
6240                         ret = I40E_NOT_SUPPORTED;
6241                 break;
6242         case RTE_ETH_FILTER_ADD:
6243                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6244                 break;
6245         case RTE_ETH_FILTER_DELETE:
6246                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6247                 break;
6248         default:
6249                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6250                 ret = I40E_ERR_PARAM;
6251                 break;
6252         }
6253
6254         return ret;
6255 }
6256
6257 static int
6258 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6259 {
6260         int ret = 0;
6261         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6262
6263         /* RSS setup */
6264         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6265                 ret = i40e_pf_config_rss(pf);
6266         else
6267                 i40e_pf_disable_rss(pf);
6268
6269         return ret;
6270 }
6271
6272 /* Get the symmetric hash enable configurations per port */
6273 static void
6274 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6275 {
6276         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6277
6278         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6279 }
6280
6281 /* Set the symmetric hash enable configurations per port */
6282 static void
6283 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6284 {
6285         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6286
6287         if (enable > 0) {
6288                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6289                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6290                                                         "been enabled");
6291                         return;
6292                 }
6293                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6294         } else {
6295                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6296                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6297                                                         "been disabled");
6298                         return;
6299                 }
6300                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6301         }
6302         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
6303         I40E_WRITE_FLUSH(hw);
6304 }
6305
6306 /*
6307  * Get global configurations of hash function type and symmetric hash enable
6308  * per flow type (pctype). Note that global configuration means it affects all
6309  * the ports on the same NIC.
6310  */
6311 static int
6312 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6313                                    struct rte_eth_hash_global_conf *g_cfg)
6314 {
6315         uint32_t reg, mask = I40E_FLOW_TYPES;
6316         uint16_t i;
6317         enum i40e_filter_pctype pctype;
6318
6319         memset(g_cfg, 0, sizeof(*g_cfg));
6320         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6321         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6322                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6323         else
6324                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6325         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6326                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6327
6328         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6329                 if (!(mask & (1UL << i)))
6330                         continue;
6331                 mask &= ~(1UL << i);
6332                 /* Bit set indicats the coresponding flow type is supported */
6333                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6334                 pctype = i40e_flowtype_to_pctype(i);
6335                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
6336                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6337                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6338         }
6339
6340         return 0;
6341 }
6342
6343 static int
6344 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6345 {
6346         uint32_t i;
6347         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6348
6349         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6350                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6351                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6352                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6353                                                 g_cfg->hash_func);
6354                 return -EINVAL;
6355         }
6356
6357         /*
6358          * As i40e supports less than 32 flow types, only first 32 bits need to
6359          * be checked.
6360          */
6361         mask0 = g_cfg->valid_bit_mask[0];
6362         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6363                 if (i == 0) {
6364                         /* Check if any unsupported flow type configured */
6365                         if ((mask0 | i40e_mask) ^ i40e_mask)
6366                                 goto mask_err;
6367                 } else {
6368                         if (g_cfg->valid_bit_mask[i])
6369                                 goto mask_err;
6370                 }
6371         }
6372
6373         return 0;
6374
6375 mask_err:
6376         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6377
6378         return -EINVAL;
6379 }
6380
6381 /*
6382  * Set global configurations of hash function type and symmetric hash enable
6383  * per flow type (pctype). Note any modifying global configuration will affect
6384  * all the ports on the same NIC.
6385  */
6386 static int
6387 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6388                                    struct rte_eth_hash_global_conf *g_cfg)
6389 {
6390         int ret;
6391         uint16_t i;
6392         uint32_t reg;
6393         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6394         enum i40e_filter_pctype pctype;
6395
6396         /* Check the input parameters */
6397         ret = i40e_hash_global_config_check(g_cfg);
6398         if (ret < 0)
6399                 return ret;
6400
6401         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6402                 if (!(mask0 & (1UL << i)))
6403                         continue;
6404                 mask0 &= ~(1UL << i);
6405                 pctype = i40e_flowtype_to_pctype(i);
6406                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6407                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6408                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
6409         }
6410
6411         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6412         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6413                 /* Toeplitz */
6414                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6415                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6416                                                                 "Toeplitz");
6417                         goto out;
6418                 }
6419                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6420         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6421                 /* Simple XOR */
6422                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6423                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6424                                                         "Simple XOR");
6425                         goto out;
6426                 }
6427                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6428         } else
6429                 /* Use the default, and keep it as it is */
6430                 goto out;
6431
6432         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6433
6434 out:
6435         I40E_WRITE_FLUSH(hw);
6436
6437         return 0;
6438 }
6439
6440 /**
6441  * Valid input sets for hash and flow director filters per PCTYPE
6442  */
6443 static uint64_t
6444 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6445                 enum rte_filter_type filter)
6446 {
6447         uint64_t valid;
6448
6449         static const uint64_t valid_hash_inset_table[] = {
6450                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6451                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6452                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6453                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6454                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6455                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6456                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6457                         I40E_INSET_FLEX_PAYLOAD,
6458                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6459                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6460                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6461                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6462                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6463                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6464                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6465                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6466                         I40E_INSET_FLEX_PAYLOAD,
6467                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6468                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6469                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6470                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6471                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6472                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6473                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6474                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6475                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6476                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6477                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6478                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6479                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6480                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6481                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6482                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6483                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6484                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6485                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6486                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6487                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6488                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6489                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6490                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6491                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6492                         I40E_INSET_FLEX_PAYLOAD,
6493                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6494                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6495                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6496                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6497                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6498                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6499                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6500                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6501                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6502                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6503                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6504                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6505                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6506                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6507                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6508                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6509                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6510                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6511                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6512                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6513                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6514                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6515                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6516                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6517                         I40E_INSET_FLEX_PAYLOAD,
6518                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6519                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6520                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6521                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6522                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6523                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6524                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6525                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6526                         I40E_INSET_FLEX_PAYLOAD,
6527                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6528                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6529                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6530                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6531                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6532                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6533                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6534                         I40E_INSET_FLEX_PAYLOAD,
6535                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6536                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6537                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6538                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6539                         I40E_INSET_FLEX_PAYLOAD,
6540         };
6541
6542         /**
6543          * Flow director supports only fields defined in
6544          * union rte_eth_fdir_flow.
6545          */
6546         static const uint64_t valid_fdir_inset_table[] = {
6547                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6548                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6549                 I40E_INSET_FLEX_PAYLOAD,
6550                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6551                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6552                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6553                 I40E_INSET_FLEX_PAYLOAD,
6554                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6555                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6556                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6557                 I40E_INSET_FLEX_PAYLOAD,
6558                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6559                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6560                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6561                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6562                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6563                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6564                 I40E_INSET_FLEX_PAYLOAD,
6565                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6566                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6567                 I40E_INSET_FLEX_PAYLOAD,
6568                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6569                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6570                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6571                 I40E_INSET_FLEX_PAYLOAD,
6572                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6573                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6574                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6575                 I40E_INSET_FLEX_PAYLOAD,
6576                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6577                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6578                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6579                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6580                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6581                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6582                 I40E_INSET_FLEX_PAYLOAD,
6583                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6584                 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6585         };
6586
6587         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6588                 return 0;
6589         if (filter == RTE_ETH_FILTER_HASH)
6590                 valid = valid_hash_inset_table[pctype];
6591         else
6592                 valid = valid_fdir_inset_table[pctype];
6593
6594         return valid;
6595 }
6596
6597 /**
6598  * Validate if the input set is allowed for a specific PCTYPE
6599  */
6600 static int
6601 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6602                 enum rte_filter_type filter, uint64_t inset)
6603 {
6604         uint64_t valid;
6605
6606         valid = i40e_get_valid_input_set(pctype, filter);
6607         if (inset & (~valid))
6608                 return -EINVAL;
6609
6610         return 0;
6611 }
6612
6613 /* default input set fields combination per pctype */
6614 static uint64_t
6615 i40e_get_default_input_set(uint16_t pctype)
6616 {
6617         static const uint64_t default_inset_table[] = {
6618                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6619                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6620                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6621                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6622                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6623                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6624                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6625                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6626                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6627                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6628                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6629                         I40E_INSET_SCTP_VT,
6630                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6631                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6632                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6633                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6634                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6635                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6636                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6637                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6638                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6639                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6640                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6641                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6642                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6643                         I40E_INSET_SCTP_VT,
6644                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6645                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6646                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6647                         I40E_INSET_LAST_ETHER_TYPE,
6648         };
6649
6650         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6651                 return 0;
6652
6653         return default_inset_table[pctype];
6654 }
6655
6656 /**
6657  * Parse the input set from index to logical bit masks
6658  */
6659 static int
6660 i40e_parse_input_set(uint64_t *inset,
6661                      enum i40e_filter_pctype pctype,
6662                      enum rte_eth_input_set_field *field,
6663                      uint16_t size)
6664 {
6665         uint16_t i, j;
6666         int ret = -EINVAL;
6667
6668         static const struct {
6669                 enum rte_eth_input_set_field field;
6670                 uint64_t inset;
6671         } inset_convert_table[] = {
6672                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6673                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6674                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6675                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6676                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6677                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6678                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6679                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6680                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6681                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6682                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6683                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6684                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6685                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6686                         I40E_INSET_IPV6_NEXT_HDR},
6687                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6688                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6689                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6690                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6691                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6692                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6693                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6694                         I40E_INSET_SCTP_VT},
6695                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6696                         I40E_INSET_TUNNEL_DMAC},
6697                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6698                         I40E_INSET_VLAN_TUNNEL},
6699                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6700                         I40E_INSET_TUNNEL_ID},
6701                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6702                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6703                         I40E_INSET_FLEX_PAYLOAD_W1},
6704                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6705                         I40E_INSET_FLEX_PAYLOAD_W2},
6706                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6707                         I40E_INSET_FLEX_PAYLOAD_W3},
6708                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6709                         I40E_INSET_FLEX_PAYLOAD_W4},
6710                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6711                         I40E_INSET_FLEX_PAYLOAD_W5},
6712                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6713                         I40E_INSET_FLEX_PAYLOAD_W6},
6714                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6715                         I40E_INSET_FLEX_PAYLOAD_W7},
6716                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6717                         I40E_INSET_FLEX_PAYLOAD_W8},
6718         };
6719
6720         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6721                 return ret;
6722
6723         /* Only one item allowed for default or all */
6724         if (size == 1) {
6725                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6726                         *inset = i40e_get_default_input_set(pctype);
6727                         return 0;
6728                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6729                         *inset = I40E_INSET_NONE;
6730                         return 0;
6731                 }
6732         }
6733
6734         for (i = 0, *inset = 0; i < size; i++) {
6735                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6736                         if (field[i] == inset_convert_table[j].field) {
6737                                 *inset |= inset_convert_table[j].inset;
6738                                 break;
6739                         }
6740                 }
6741
6742                 /* It contains unsupported input set, return immediately */
6743                 if (j == RTE_DIM(inset_convert_table))
6744                         return ret;
6745         }
6746
6747         return 0;
6748 }
6749
6750 /**
6751  * Translate the input set from bit masks to register aware bit masks
6752  * and vice versa
6753  */
6754 static uint64_t
6755 i40e_translate_input_set_reg(uint64_t input)
6756 {
6757         uint64_t val = 0;
6758         uint16_t i;
6759
6760         static const struct {
6761                 uint64_t inset;
6762                 uint64_t inset_reg;
6763         } inset_map[] = {
6764                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6765                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6766                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6767                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6768                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6769                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6770                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6771                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6772                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6773                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6774                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6775                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6776                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6777                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6778                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6779                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6780                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6781                 {I40E_INSET_TUNNEL_DMAC,
6782                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6783                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6784                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6785                 {I40E_INSET_TUNNEL_SRC_PORT,
6786                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6787                 {I40E_INSET_TUNNEL_DST_PORT,
6788                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6789                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6790                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6791                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6792                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6793                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6794                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6795                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6796                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6797                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6798         };
6799
6800         if (input == 0)
6801                 return val;
6802
6803         /* Translate input set to register aware inset */
6804         for (i = 0; i < RTE_DIM(inset_map); i++) {
6805                 if (input & inset_map[i].inset)
6806                         val |= inset_map[i].inset_reg;
6807         }
6808
6809         return val;
6810 }
6811
6812 static uint8_t
6813 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6814 {
6815         uint8_t i, idx = 0;
6816
6817         static const struct {
6818                 uint64_t inset;
6819                 uint32_t mask;
6820         } inset_mask_map[] = {
6821                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6822                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6823                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6824                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6825         };
6826
6827         if (!inset || !mask || !nb_elem)
6828                 return 0;
6829
6830         if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6831                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6832                         mask[i] = 0;
6833                 return I40E_INSET_MASK_NUM_REG;
6834         }
6835
6836         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6837                 if (idx >= nb_elem)
6838                         break;
6839                 if (inset & inset_mask_map[i].inset) {
6840                         mask[idx] = inset_mask_map[i].mask;
6841                         idx++;
6842                 }
6843         }
6844
6845         return idx;
6846 }
6847
6848 static uint64_t
6849 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
6850                             enum i40e_filter_pctype pctype)
6851 {
6852         uint64_t reg = 0;
6853
6854         if (filter == RTE_ETH_FILTER_HASH) {
6855                 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
6856                 reg <<= I40E_32_BIT_WIDTH;
6857                 reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
6858         } else if (filter == RTE_ETH_FILTER_FDIR) {
6859                 reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
6860                 reg <<= I40E_32_BIT_WIDTH;
6861                 reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
6862         }
6863
6864         return reg;
6865 }
6866
6867 static void
6868 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
6869 {
6870         uint32_t reg = I40E_READ_REG(hw, addr);
6871
6872         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
6873         if (reg != val)
6874                 I40E_WRITE_REG(hw, addr, val);
6875         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
6876                     (uint32_t)I40E_READ_REG(hw, addr));
6877 }
6878
6879 static int
6880 i40e_set_hash_inset_mask(struct i40e_hw *hw,
6881                          enum i40e_filter_pctype pctype,
6882                          enum rte_filter_input_set_op op,
6883                          uint32_t *mask_reg,
6884                          uint8_t num)
6885 {
6886         uint32_t reg;
6887         uint8_t i;
6888
6889         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6890                 return -EINVAL;
6891
6892         if (op == RTE_ETH_INPUT_SET_SELECT) {
6893                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6894                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6895                                              0);
6896                         if (i >= num)
6897                                 continue;
6898                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6899                                              mask_reg[i]);
6900                 }
6901         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6902                 uint8_t j, count = 0;
6903
6904                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6905                         reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
6906                         if (reg & I40E_GLQF_HASH_MSK_FIELD)
6907                                 count++;
6908                 }
6909                 if (count + num > I40E_INSET_MASK_NUM_REG)
6910                         return -EINVAL;
6911
6912                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6913                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6914                                              mask_reg[j]);
6915         }
6916
6917         return 0;
6918 }
6919
6920 static int
6921 i40e_set_fd_inset_mask(struct i40e_hw *hw,
6922                        enum i40e_filter_pctype pctype,
6923                        enum rte_filter_input_set_op op,
6924                        uint32_t *mask_reg,
6925                        uint8_t num)
6926 {
6927         uint32_t reg;
6928         uint8_t i;
6929
6930         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6931                 return -EINVAL;
6932
6933         if (op == RTE_ETH_INPUT_SET_SELECT) {
6934                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6935                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6936                                              0);
6937                         if (i >= num)
6938                                 continue;
6939                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6940                                              mask_reg[i]);
6941                 }
6942         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6943                 uint8_t j, count = 0;
6944
6945                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6946                         reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
6947                         if (reg & I40E_GLQF_FD_MSK_FIELD)
6948                                 count++;
6949                 }
6950                 if (count + num > I40E_INSET_MASK_NUM_REG)
6951                         return -EINVAL;
6952
6953                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6954                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6955                                              mask_reg[j]);
6956         }
6957
6958         return 0;
6959 }
6960
6961 int
6962 i40e_filter_inset_select(struct i40e_hw *hw,
6963                          struct rte_eth_input_set_conf *conf,
6964                          enum rte_filter_type filter)
6965 {
6966         enum i40e_filter_pctype pctype;
6967         uint64_t inset_reg = 0, input_set;
6968         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
6969         uint8_t num;
6970         int ret;
6971
6972         if (!hw || !conf) {
6973                 PMD_DRV_LOG(ERR, "Invalid pointer");
6974                 return -EFAULT;
6975         }
6976
6977         pctype = i40e_flowtype_to_pctype(conf->flow_type);
6978         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
6979                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
6980                             conf->flow_type);
6981                 return -EINVAL;
6982         }
6983         if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
6984                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6985                 return -EINVAL;
6986         }
6987
6988         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
6989                                    conf->inset_size);
6990         if (ret) {
6991                 PMD_DRV_LOG(ERR, "Failed to parse input set");
6992                 return -EINVAL;
6993         }
6994         if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
6995                 PMD_DRV_LOG(ERR, "Invalid input set");
6996                 return -EINVAL;
6997         }
6998
6999         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7000                 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
7001         } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
7002                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7003                 return -EINVAL;
7004         }
7005         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7006                                            I40E_INSET_MASK_NUM_REG);
7007         inset_reg |= i40e_translate_input_set_reg(input_set);
7008
7009         if (filter == RTE_ETH_FILTER_HASH) {
7010                 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
7011                                                num);
7012                 if (ret)
7013                         return -EINVAL;
7014
7015                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7016                                       (uint32_t)(inset_reg & UINT32_MAX));
7017                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7018                                      (uint32_t)((inset_reg >>
7019                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7020         } else if (filter == RTE_ETH_FILTER_FDIR) {
7021                 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
7022                                              num);
7023                 if (ret)
7024                         return -EINVAL;
7025
7026                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7027                                       (uint32_t)(inset_reg & UINT32_MAX));
7028                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7029                                      (uint32_t)((inset_reg >>
7030                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7031         } else {
7032                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7033                 return -EINVAL;
7034         }
7035         I40E_WRITE_FLUSH(hw);
7036
7037         return 0;
7038 }
7039
7040 static int
7041 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7042 {
7043         int ret = 0;
7044
7045         if (!hw || !info) {
7046                 PMD_DRV_LOG(ERR, "Invalid pointer");
7047                 return -EFAULT;
7048         }
7049
7050         switch (info->info_type) {
7051         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7052                 i40e_get_symmetric_hash_enable_per_port(hw,
7053                                         &(info->info.enable));
7054                 break;
7055         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7056                 ret = i40e_get_hash_filter_global_config(hw,
7057                                 &(info->info.global_conf));
7058                 break;
7059         default:
7060                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7061                                                         info->info_type);
7062                 ret = -EINVAL;
7063                 break;
7064         }
7065
7066         return ret;
7067 }
7068
7069 static int
7070 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7071 {
7072         int ret = 0;
7073
7074         if (!hw || !info) {
7075                 PMD_DRV_LOG(ERR, "Invalid pointer");
7076                 return -EFAULT;
7077         }
7078
7079         switch (info->info_type) {
7080         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7081                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7082                 break;
7083         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7084                 ret = i40e_set_hash_filter_global_config(hw,
7085                                 &(info->info.global_conf));
7086                 break;
7087         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7088                 ret = i40e_filter_inset_select(hw,
7089                                                &(info->info.input_set_conf),
7090                                                RTE_ETH_FILTER_HASH);
7091                 break;
7092
7093         default:
7094                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7095                                                         info->info_type);
7096                 ret = -EINVAL;
7097                 break;
7098         }
7099
7100         return ret;
7101 }
7102
7103 /* Operations for hash function */
7104 static int
7105 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7106                       enum rte_filter_op filter_op,
7107                       void *arg)
7108 {
7109         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7110         int ret = 0;
7111
7112         switch (filter_op) {
7113         case RTE_ETH_FILTER_NOP:
7114                 break;
7115         case RTE_ETH_FILTER_GET:
7116                 ret = i40e_hash_filter_get(hw,
7117                         (struct rte_eth_hash_filter_info *)arg);
7118                 break;
7119         case RTE_ETH_FILTER_SET:
7120                 ret = i40e_hash_filter_set(hw,
7121                         (struct rte_eth_hash_filter_info *)arg);
7122                 break;
7123         default:
7124                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7125                                                                 filter_op);
7126                 ret = -ENOTSUP;
7127                 break;
7128         }
7129
7130         return ret;
7131 }
7132
7133 /*
7134  * Configure ethertype filter, which can director packet by filtering
7135  * with mac address and ether_type or only ether_type
7136  */
7137 static int
7138 i40e_ethertype_filter_set(struct i40e_pf *pf,
7139                         struct rte_eth_ethertype_filter *filter,
7140                         bool add)
7141 {
7142         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7143         struct i40e_control_filter_stats stats;
7144         uint16_t flags = 0;
7145         int ret;
7146
7147         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7148                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7149                 return -EINVAL;
7150         }
7151         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7152                 filter->ether_type == ETHER_TYPE_IPv6) {
7153                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7154                         " control packet filter.", filter->ether_type);
7155                 return -EINVAL;
7156         }
7157         if (filter->ether_type == ETHER_TYPE_VLAN)
7158                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7159                         " not supported.");
7160
7161         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7162                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7163         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7164                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7165         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7166
7167         memset(&stats, 0, sizeof(stats));
7168         ret = i40e_aq_add_rem_control_packet_filter(hw,
7169                         filter->mac_addr.addr_bytes,
7170                         filter->ether_type, flags,
7171                         pf->main_vsi->seid,
7172                         filter->queue, add, &stats, NULL);
7173
7174         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7175                          " mac_etype_used = %u, etype_used = %u,"
7176                          " mac_etype_free = %u, etype_free = %u\n",
7177                          ret, stats.mac_etype_used, stats.etype_used,
7178                          stats.mac_etype_free, stats.etype_free);
7179         if (ret < 0)
7180                 return -ENOSYS;
7181         return 0;
7182 }
7183
7184 /*
7185  * Handle operations for ethertype filter.
7186  */
7187 static int
7188 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7189                                 enum rte_filter_op filter_op,
7190                                 void *arg)
7191 {
7192         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7193         int ret = 0;
7194
7195         if (filter_op == RTE_ETH_FILTER_NOP)
7196                 return ret;
7197
7198         if (arg == NULL) {
7199                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7200                             filter_op);
7201                 return -EINVAL;
7202         }
7203
7204         switch (filter_op) {
7205         case RTE_ETH_FILTER_ADD:
7206                 ret = i40e_ethertype_filter_set(pf,
7207                         (struct rte_eth_ethertype_filter *)arg,
7208                         TRUE);
7209                 break;
7210         case RTE_ETH_FILTER_DELETE:
7211                 ret = i40e_ethertype_filter_set(pf,
7212                         (struct rte_eth_ethertype_filter *)arg,
7213                         FALSE);
7214                 break;
7215         default:
7216                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7217                 ret = -ENOSYS;
7218                 break;
7219         }
7220         return ret;
7221 }
7222
7223 static int
7224 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7225                      enum rte_filter_type filter_type,
7226                      enum rte_filter_op filter_op,
7227                      void *arg)
7228 {
7229         int ret = 0;
7230
7231         if (dev == NULL)
7232                 return -EINVAL;
7233
7234         switch (filter_type) {
7235         case RTE_ETH_FILTER_NONE:
7236                 /* For global configuration */
7237                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7238                 break;
7239         case RTE_ETH_FILTER_HASH:
7240                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7241                 break;
7242         case RTE_ETH_FILTER_MACVLAN:
7243                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7244                 break;
7245         case RTE_ETH_FILTER_ETHERTYPE:
7246                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7247                 break;
7248         case RTE_ETH_FILTER_TUNNEL:
7249                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7250                 break;
7251         case RTE_ETH_FILTER_FDIR:
7252                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7253                 break;
7254         default:
7255                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7256                                                         filter_type);
7257                 ret = -EINVAL;
7258                 break;
7259         }
7260
7261         return ret;
7262 }
7263
7264 /*
7265  * As some registers wouldn't be reset unless a global hardware reset,
7266  * hardware initialization is needed to put those registers into an
7267  * expected initial state.
7268  */
7269 static void
7270 i40e_hw_init(struct i40e_hw *hw)
7271 {
7272         /* clear the PF Queue Filter control register */
7273         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
7274
7275         /* Disable symmetric hash per port */
7276         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7277 }
7278
7279 enum i40e_filter_pctype
7280 i40e_flowtype_to_pctype(uint16_t flow_type)
7281 {
7282         static const enum i40e_filter_pctype pctype_table[] = {
7283                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7284                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7285                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7286                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7287                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7288                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7289                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7290                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7291                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7292                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7293                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7294                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7295                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7296                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7297                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7298                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7299                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7300                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7301                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7302         };
7303
7304         return pctype_table[flow_type];
7305 }
7306
7307 uint16_t
7308 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7309 {
7310         static const uint16_t flowtype_table[] = {
7311                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7312                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7313                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7314                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7315                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7316                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7317                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7318                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7319                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7320                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7321                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7322                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7323                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7324                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7325                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7326                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7327                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7328                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7329                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7330         };
7331
7332         return flowtype_table[pctype];
7333 }
7334
7335 /*
7336  * On X710, performance number is far from the expectation on recent firmware
7337  * versions; on XL710, performance number is also far from the expectation on
7338  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7339  * mode is enabled and port MAC address is equal to the packet destination MAC
7340  * address. The fix for this issue may not be integrated in the following
7341  * firmware version. So the workaround in software driver is needed. It needs
7342  * to modify the initial values of 3 internal only registers for both X710 and
7343  * XL710. Note that the values for X710 or XL710 could be different, and the
7344  * workaround can be removed when it is fixed in firmware in the future.
7345  */
7346
7347 /* For both X710 and XL710 */
7348 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7349 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7350
7351 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7352 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7353
7354 /* For X710 */
7355 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7356 /* For XL710 */
7357 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7358 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7359
7360 static void
7361 i40e_configure_registers(struct i40e_hw *hw)
7362 {
7363         static struct {
7364                 uint32_t addr;
7365                 uint64_t val;
7366         } reg_table[] = {
7367                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7368                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7369                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7370         };
7371         uint64_t reg;
7372         uint32_t i;
7373         int ret;
7374
7375         for (i = 0; i < RTE_DIM(reg_table); i++) {
7376                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7377                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7378                                 reg_table[i].val =
7379                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7380                         else /* For X710 */
7381                                 reg_table[i].val =
7382                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7383                 }
7384
7385                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7386                                                         &reg, NULL);
7387                 if (ret < 0) {
7388                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7389                                                         reg_table[i].addr);
7390                         break;
7391                 }
7392                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7393                                                 reg_table[i].addr, reg);
7394                 if (reg == reg_table[i].val)
7395                         continue;
7396
7397                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7398                                                 reg_table[i].val, NULL);
7399                 if (ret < 0) {
7400                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7401                                 "address of 0x%"PRIx32, reg_table[i].val,
7402                                                         reg_table[i].addr);
7403                         break;
7404                 }
7405                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7406                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7407         }
7408 }
7409
7410 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7411 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7412 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7413 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7414 static int
7415 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7416 {
7417         uint32_t reg;
7418         int ret;
7419
7420         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7421                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7422                 return -EINVAL;
7423         }
7424
7425         /* Configure for double VLAN RX stripping */
7426         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7427         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7428                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7429                 ret = i40e_aq_debug_write_register(hw,
7430                                                    I40E_VSI_TSR(vsi->vsi_id),
7431                                                    reg, NULL);
7432                 if (ret < 0) {
7433                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7434                                     vsi->vsi_id);
7435                         return I40E_ERR_CONFIG;
7436                 }
7437         }
7438
7439         /* Configure for double VLAN TX insertion */
7440         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7441         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7442                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7443                 ret = i40e_aq_debug_write_register(hw,
7444                                                    I40E_VSI_L2TAGSTXVALID(
7445                                                    vsi->vsi_id), reg, NULL);
7446                 if (ret < 0) {
7447                         PMD_DRV_LOG(ERR, "Failed to update "
7448                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7449                         return I40E_ERR_CONFIG;
7450                 }
7451         }
7452
7453         return 0;
7454 }
7455
7456 /**
7457  * i40e_aq_add_mirror_rule
7458  * @hw: pointer to the hardware structure
7459  * @seid: VEB seid to add mirror rule to
7460  * @dst_id: destination vsi seid
7461  * @entries: Buffer which contains the entities to be mirrored
7462  * @count: number of entities contained in the buffer
7463  * @rule_id:the rule_id of the rule to be added
7464  *
7465  * Add a mirror rule for a given veb.
7466  *
7467  **/
7468 static enum i40e_status_code
7469 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7470                         uint16_t seid, uint16_t dst_id,
7471                         uint16_t rule_type, uint16_t *entries,
7472                         uint16_t count, uint16_t *rule_id)
7473 {
7474         struct i40e_aq_desc desc;
7475         struct i40e_aqc_add_delete_mirror_rule cmd;
7476         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7477                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7478                 &desc.params.raw;
7479         uint16_t buff_len;
7480         enum i40e_status_code status;
7481
7482         i40e_fill_default_direct_cmd_desc(&desc,
7483                                           i40e_aqc_opc_add_mirror_rule);
7484         memset(&cmd, 0, sizeof(cmd));
7485
7486         buff_len = sizeof(uint16_t) * count;
7487         desc.datalen = rte_cpu_to_le_16(buff_len);
7488         if (buff_len > 0)
7489                 desc.flags |= rte_cpu_to_le_16(
7490                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7491         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7492                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7493         cmd.num_entries = rte_cpu_to_le_16(count);
7494         cmd.seid = rte_cpu_to_le_16(seid);
7495         cmd.destination = rte_cpu_to_le_16(dst_id);
7496
7497         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7498         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7499         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7500                          "rule_id = %u"
7501                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7502                          hw->aq.asq_last_status, resp->rule_id,
7503                          resp->mirror_rules_used, resp->mirror_rules_free);
7504         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7505
7506         return status;
7507 }
7508
7509 /**
7510  * i40e_aq_del_mirror_rule
7511  * @hw: pointer to the hardware structure
7512  * @seid: VEB seid to add mirror rule to
7513  * @entries: Buffer which contains the entities to be mirrored
7514  * @count: number of entities contained in the buffer
7515  * @rule_id:the rule_id of the rule to be delete
7516  *
7517  * Delete a mirror rule for a given veb.
7518  *
7519  **/
7520 static enum i40e_status_code
7521 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7522                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7523                 uint16_t count, uint16_t rule_id)
7524 {
7525         struct i40e_aq_desc desc;
7526         struct i40e_aqc_add_delete_mirror_rule cmd;
7527         uint16_t buff_len = 0;
7528         enum i40e_status_code status;
7529         void *buff = NULL;
7530
7531         i40e_fill_default_direct_cmd_desc(&desc,
7532                                           i40e_aqc_opc_delete_mirror_rule);
7533         memset(&cmd, 0, sizeof(cmd));
7534         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7535                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7536                                                           I40E_AQ_FLAG_RD));
7537                 cmd.num_entries = count;
7538                 buff_len = sizeof(uint16_t) * count;
7539                 desc.datalen = rte_cpu_to_le_16(buff_len);
7540                 buff = (void *)entries;
7541         } else
7542                 /* rule id is filled in destination field for deleting mirror rule */
7543                 cmd.destination = rte_cpu_to_le_16(rule_id);
7544
7545         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7546                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7547         cmd.seid = rte_cpu_to_le_16(seid);
7548
7549         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7550         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7551
7552         return status;
7553 }
7554
7555 /**
7556  * i40e_mirror_rule_set
7557  * @dev: pointer to the hardware structure
7558  * @mirror_conf: mirror rule info
7559  * @sw_id: mirror rule's sw_id
7560  * @on: enable/disable
7561  *
7562  * set a mirror rule.
7563  *
7564  **/
7565 static int
7566 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7567                         struct rte_eth_mirror_conf *mirror_conf,
7568                         uint8_t sw_id, uint8_t on)
7569 {
7570         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7571         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7572         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7573         struct i40e_mirror_rule *parent = NULL;
7574         uint16_t seid, dst_seid, rule_id;
7575         uint16_t i, j = 0;
7576         int ret;
7577
7578         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7579
7580         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7581                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7582                         " without veb or vfs.");
7583                 return -ENOSYS;
7584         }
7585         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7586                 PMD_DRV_LOG(ERR, "mirror table is full.");
7587                 return -ENOSPC;
7588         }
7589         if (mirror_conf->dst_pool > pf->vf_num) {
7590                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7591                                  mirror_conf->dst_pool);
7592                 return -EINVAL;
7593         }
7594
7595         seid = pf->main_vsi->veb->seid;
7596
7597         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7598                 if (sw_id <= it->index) {
7599                         mirr_rule = it;
7600                         break;
7601                 }
7602                 parent = it;
7603         }
7604         if (mirr_rule && sw_id == mirr_rule->index) {
7605                 if (on) {
7606                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7607                         return -EEXIST;
7608                 } else {
7609                         ret = i40e_aq_del_mirror_rule(hw, seid,
7610                                         mirr_rule->rule_type,
7611                                         mirr_rule->entries,
7612                                         mirr_rule->num_entries, mirr_rule->id);
7613                         if (ret < 0) {
7614                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7615                                                    " ret = %d, aq_err = %d.",
7616                                                    ret, hw->aq.asq_last_status);
7617                                 return -ENOSYS;
7618                         }
7619                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7620                         rte_free(mirr_rule);
7621                         pf->nb_mirror_rule--;
7622                         return 0;
7623                 }
7624         } else if (!on) {
7625                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7626                 return -ENOENT;
7627         }
7628
7629         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7630                                 sizeof(struct i40e_mirror_rule) , 0);
7631         if (!mirr_rule) {
7632                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7633                 return I40E_ERR_NO_MEMORY;
7634         }
7635         switch (mirror_conf->rule_type) {
7636         case ETH_MIRROR_VLAN:
7637                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7638                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7639                                 mirr_rule->entries[j] =
7640                                         mirror_conf->vlan.vlan_id[i];
7641                                 j++;
7642                         }
7643                 }
7644                 if (j == 0) {
7645                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7646                         rte_free(mirr_rule);
7647                         return -EINVAL;
7648                 }
7649                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7650                 break;
7651         case ETH_MIRROR_VIRTUAL_POOL_UP:
7652         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7653                 /* check if the specified pool bit is out of range */
7654                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7655                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7656                         rte_free(mirr_rule);
7657                         return -EINVAL;
7658                 }
7659                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7660                         if (mirror_conf->pool_mask & (1ULL << i)) {
7661                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7662                                 j++;
7663                         }
7664                 }
7665                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7666                         /* add pf vsi to entries */
7667                         mirr_rule->entries[j] = pf->main_vsi_seid;
7668                         j++;
7669                 }
7670                 if (j == 0) {
7671                         PMD_DRV_LOG(ERR, "pool is not specified.");
7672                         rte_free(mirr_rule);
7673                         return -EINVAL;
7674                 }
7675                 /* egress and ingress in aq commands means from switch but not port */
7676                 mirr_rule->rule_type =
7677                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7678                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7679                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7680                 break;
7681         case ETH_MIRROR_UPLINK_PORT:
7682                 /* egress and ingress in aq commands means from switch but not port*/
7683                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7684                 break;
7685         case ETH_MIRROR_DOWNLINK_PORT:
7686                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7687                 break;
7688         default:
7689                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7690                         mirror_conf->rule_type);
7691                 rte_free(mirr_rule);
7692                 return -EINVAL;
7693         }
7694
7695         /* If the dst_pool is equal to vf_num, consider it as PF */
7696         if (mirror_conf->dst_pool == pf->vf_num)
7697                 dst_seid = pf->main_vsi_seid;
7698         else
7699                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7700
7701         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7702                                       mirr_rule->rule_type, mirr_rule->entries,
7703                                       j, &rule_id);
7704         if (ret < 0) {
7705                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7706                                    " ret = %d, aq_err = %d.",
7707                                    ret, hw->aq.asq_last_status);
7708                 rte_free(mirr_rule);
7709                 return -ENOSYS;
7710         }
7711
7712         mirr_rule->index = sw_id;
7713         mirr_rule->num_entries = j;
7714         mirr_rule->id = rule_id;
7715         mirr_rule->dst_vsi_seid = dst_seid;
7716
7717         if (parent)
7718                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7719         else
7720                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7721
7722         pf->nb_mirror_rule++;
7723         return 0;
7724 }
7725
7726 /**
7727  * i40e_mirror_rule_reset
7728  * @dev: pointer to the device
7729  * @sw_id: mirror rule's sw_id
7730  *
7731  * reset a mirror rule.
7732  *
7733  **/
7734 static int
7735 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7736 {
7737         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7738         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7739         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7740         uint16_t seid;
7741         int ret;
7742
7743         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7744
7745         seid = pf->main_vsi->veb->seid;
7746
7747         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7748                 if (sw_id == it->index) {
7749                         mirr_rule = it;
7750                         break;
7751                 }
7752         }
7753         if (mirr_rule) {
7754                 ret = i40e_aq_del_mirror_rule(hw, seid,
7755                                 mirr_rule->rule_type,
7756                                 mirr_rule->entries,
7757                                 mirr_rule->num_entries, mirr_rule->id);
7758                 if (ret < 0) {
7759                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7760                                            " status = %d, aq_err = %d.",
7761                                            ret, hw->aq.asq_last_status);
7762                         return -ENOSYS;
7763                 }
7764                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7765                 rte_free(mirr_rule);
7766                 pf->nb_mirror_rule--;
7767         } else {
7768                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7769                 return -ENOENT;
7770         }
7771         return 0;
7772 }
7773
7774 static uint64_t
7775 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
7776 {
7777         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7778         uint64_t systim_cycles;
7779
7780         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
7781         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
7782                         << 32;
7783
7784         return systim_cycles;
7785 }
7786
7787 static uint64_t
7788 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
7789 {
7790         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7791         uint64_t rx_tstamp;
7792
7793         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7794         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
7795                         << 32;
7796
7797         return rx_tstamp;
7798 }
7799
7800 static uint64_t
7801 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7802 {
7803         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7804         uint64_t tx_tstamp;
7805
7806         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
7807         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
7808                         << 32;
7809
7810         return tx_tstamp;
7811 }
7812
7813 static void
7814 i40e_start_timecounters(struct rte_eth_dev *dev)
7815 {
7816         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7817         struct i40e_adapter *adapter =
7818                         (struct i40e_adapter *)dev->data->dev_private;
7819         struct rte_eth_link link;
7820         uint32_t tsync_inc_l;
7821         uint32_t tsync_inc_h;
7822
7823         /* Get current link speed. */
7824         memset(&link, 0, sizeof(link));
7825         i40e_dev_link_update(dev, 1);
7826         rte_i40e_dev_atomic_read_link_status(dev, &link);
7827
7828         switch (link.link_speed) {
7829         case ETH_LINK_SPEED_40G:
7830                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
7831                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
7832                 break;
7833         case ETH_LINK_SPEED_10G:
7834                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
7835                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
7836                 break;
7837         case ETH_LINK_SPEED_1000:
7838                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
7839                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
7840                 break;
7841         default:
7842                 tsync_inc_l = 0x0;
7843                 tsync_inc_h = 0x0;
7844         }
7845
7846         /* Set the timesync increment value. */
7847         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
7848         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
7849
7850         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7851         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7852         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7853
7854         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7855         adapter->systime_tc.cc_shift = 0;
7856         adapter->systime_tc.nsec_mask = 0;
7857
7858         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7859         adapter->rx_tstamp_tc.cc_shift = 0;
7860         adapter->rx_tstamp_tc.nsec_mask = 0;
7861
7862         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7863         adapter->tx_tstamp_tc.cc_shift = 0;
7864         adapter->tx_tstamp_tc.nsec_mask = 0;
7865 }
7866
7867 static int
7868 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7869 {
7870         struct i40e_adapter *adapter =
7871                         (struct i40e_adapter *)dev->data->dev_private;
7872
7873         adapter->systime_tc.nsec += delta;
7874         adapter->rx_tstamp_tc.nsec += delta;
7875         adapter->tx_tstamp_tc.nsec += delta;
7876
7877         return 0;
7878 }
7879
7880 static int
7881 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7882 {
7883         uint64_t ns;
7884         struct i40e_adapter *adapter =
7885                         (struct i40e_adapter *)dev->data->dev_private;
7886
7887         ns = rte_timespec_to_ns(ts);
7888
7889         /* Set the timecounters to a new value. */
7890         adapter->systime_tc.nsec = ns;
7891         adapter->rx_tstamp_tc.nsec = ns;
7892         adapter->tx_tstamp_tc.nsec = ns;
7893
7894         return 0;
7895 }
7896
7897 static int
7898 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7899 {
7900         uint64_t ns, systime_cycles;
7901         struct i40e_adapter *adapter =
7902                         (struct i40e_adapter *)dev->data->dev_private;
7903
7904         systime_cycles = i40e_read_systime_cyclecounter(dev);
7905         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7906         *ts = rte_ns_to_timespec(ns);
7907
7908         return 0;
7909 }
7910
7911 static int
7912 i40e_timesync_enable(struct rte_eth_dev *dev)
7913 {
7914         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7915         uint32_t tsync_ctl_l;
7916         uint32_t tsync_ctl_h;
7917
7918         /* Stop the timesync system time. */
7919         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7920         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7921         /* Reset the timesync system time value. */
7922         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
7923         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
7924
7925         i40e_start_timecounters(dev);
7926
7927         /* Clear timesync registers. */
7928         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7929         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7930         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
7931         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
7932         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
7933         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
7934
7935         /* Enable timestamping of PTP packets. */
7936         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7937         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
7938
7939         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7940         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
7941         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
7942
7943         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7944         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7945
7946         return 0;
7947 }
7948
7949 static int
7950 i40e_timesync_disable(struct rte_eth_dev *dev)
7951 {
7952         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7953         uint32_t tsync_ctl_l;
7954         uint32_t tsync_ctl_h;
7955
7956         /* Disable timestamping of transmitted PTP packets. */
7957         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7958         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
7959
7960         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7961         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
7962
7963         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7964         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7965
7966         /* Reset the timesync increment value. */
7967         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7968         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7969
7970         return 0;
7971 }
7972
7973 static int
7974 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7975                                 struct timespec *timestamp, uint32_t flags)
7976 {
7977         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7978         struct i40e_adapter *adapter =
7979                 (struct i40e_adapter *)dev->data->dev_private;
7980
7981         uint32_t sync_status;
7982         uint32_t index = flags & 0x03;
7983         uint64_t rx_tstamp_cycles;
7984         uint64_t ns;
7985
7986         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
7987         if ((sync_status & (1 << index)) == 0)
7988                 return -EINVAL;
7989
7990         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
7991         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7992         *timestamp = rte_ns_to_timespec(ns);
7993
7994         return 0;
7995 }
7996
7997 static int
7998 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7999                                 struct timespec *timestamp)
8000 {
8001         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8002         struct i40e_adapter *adapter =
8003                 (struct i40e_adapter *)dev->data->dev_private;
8004
8005         uint32_t sync_status;
8006         uint64_t tx_tstamp_cycles;
8007         uint64_t ns;
8008
8009         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8010         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8011                 return -EINVAL;
8012
8013         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8014         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8015         *timestamp = rte_ns_to_timespec(ns);
8016
8017         return 0;
8018 }
8019
8020 /*
8021  * i40e_parse_dcb_configure - parse dcb configure from user
8022  * @dev: the device being configured
8023  * @dcb_cfg: pointer of the result of parse
8024  * @*tc_map: bit map of enabled traffic classes
8025  *
8026  * Returns 0 on success, negative value on failure
8027  */
8028 static int
8029 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8030                          struct i40e_dcbx_config *dcb_cfg,
8031                          uint8_t *tc_map)
8032 {
8033         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8034         uint8_t i, tc_bw, bw_lf;
8035
8036         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8037
8038         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8039         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8040                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8041                 return -EINVAL;
8042         }
8043
8044         /* assume each tc has the same bw */
8045         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8046         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8047                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8048         /* to ensure the sum of tcbw is equal to 100 */
8049         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8050         for (i = 0; i < bw_lf; i++)
8051                 dcb_cfg->etscfg.tcbwtable[i]++;
8052
8053         /* assume each tc has the same Transmission Selection Algorithm */
8054         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8055                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8056
8057         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8058                 dcb_cfg->etscfg.prioritytable[i] =
8059                                 dcb_rx_conf->dcb_tc[i];
8060
8061         /* FW needs one App to configure HW */
8062         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8063         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8064         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8065         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8066
8067         if (dcb_rx_conf->nb_tcs == 0)
8068                 *tc_map = 1; /* tc0 only */
8069         else
8070                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8071
8072         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8073                 dcb_cfg->pfc.willing = 0;
8074                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8075                 dcb_cfg->pfc.pfcenable = *tc_map;
8076         }
8077         return 0;
8078 }
8079
8080
8081 static enum i40e_status_code
8082 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8083                               struct i40e_aqc_vsi_properties_data *info,
8084                               uint8_t enabled_tcmap)
8085 {
8086         enum i40e_status_code ret;
8087         int i, total_tc = 0;
8088         uint16_t qpnum_per_tc, bsf, qp_idx;
8089         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8090
8091         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8092         if (ret != I40E_SUCCESS)
8093                 return ret;
8094
8095         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8096                 if (enabled_tcmap & (1 << i))
8097                         total_tc++;
8098         }
8099         if (total_tc == 0)
8100                 total_tc = 1;
8101         vsi->enabled_tc = enabled_tcmap;
8102
8103         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
8104         /* Number of queues per enabled TC */
8105         if (qpnum_per_tc == 0) {
8106                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8107                 return I40E_ERR_INVALID_QP_ID;
8108         }
8109         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8110                                 I40E_MAX_Q_PER_TC);
8111         bsf = rte_bsf32(qpnum_per_tc);
8112
8113         /**
8114          * Configure TC and queue mapping parameters, for enabled TC,
8115          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8116          * default queue will serve it.
8117          */
8118         qp_idx = 0;
8119         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8120                 if (vsi->enabled_tc & (1 << i)) {
8121                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8122                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8123                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8124                         qp_idx += qpnum_per_tc;
8125                 } else
8126                         info->tc_mapping[i] = 0;
8127         }
8128
8129         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8130         if (vsi->type == I40E_VSI_SRIOV) {
8131                 info->mapping_flags |=
8132                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8133                 for (i = 0; i < vsi->nb_qps; i++)
8134                         info->queue_mapping[i] =
8135                                 rte_cpu_to_le_16(vsi->base_queue + i);
8136         } else {
8137                 info->mapping_flags |=
8138                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8139                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8140         }
8141         info->valid_sections |=
8142                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8143
8144         return I40E_SUCCESS;
8145 }
8146
8147 /*
8148  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8149  * @vsi: VSI to be configured
8150  * @tc_map: enabled TC bitmap
8151  *
8152  * Returns 0 on success, negative value on failure
8153  */
8154 static enum i40e_status_code
8155 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
8156 {
8157         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8158         struct i40e_vsi_context ctxt;
8159         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8160         enum i40e_status_code ret = I40E_SUCCESS;
8161         int i;
8162
8163         /* Check if enabled_tc is same as existing or new TCs */
8164         if (vsi->enabled_tc == tc_map)
8165                 return ret;
8166
8167         /* configure tc bandwidth */
8168         memset(&bw_data, 0, sizeof(bw_data));
8169         bw_data.tc_valid_bits = tc_map;
8170         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8171         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8172                 if (tc_map & BIT_ULL(i))
8173                         bw_data.tc_bw_credits[i] = 1;
8174         }
8175         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8176         if (ret) {
8177                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8178                         " per TC failed = %d",
8179                         hw->aq.asq_last_status);
8180                 goto out;
8181         }
8182         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8183                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8184
8185         /* Update Queue Pairs Mapping for currently enabled UPs */
8186         ctxt.seid = vsi->seid;
8187         ctxt.pf_num = hw->pf_id;
8188         ctxt.vf_num = 0;
8189         ctxt.uplink_seid = vsi->uplink_seid;
8190         ctxt.info = vsi->info;
8191         i40e_get_cap(hw);
8192         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8193         if (ret)
8194                 goto out;
8195
8196         /* Update the VSI after updating the VSI queue-mapping information */
8197         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8198         if (ret) {
8199                 PMD_INIT_LOG(ERR, "Failed to configure "
8200                             "TC queue mapping = %d",
8201                             hw->aq.asq_last_status);
8202                 goto out;
8203         }
8204         /* update the local VSI info with updated queue map */
8205         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8206                                         sizeof(vsi->info.tc_mapping));
8207         (void)rte_memcpy(&vsi->info.queue_mapping,
8208                         &ctxt.info.queue_mapping,
8209                 sizeof(vsi->info.queue_mapping));
8210         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8211         vsi->info.valid_sections = 0;
8212
8213         /* query and update current VSI BW information */
8214         ret = i40e_vsi_get_bw_config(vsi);
8215         if (ret) {
8216                 PMD_INIT_LOG(ERR,
8217                          "Failed updating vsi bw info, err %s aq_err %s",
8218                          i40e_stat_str(hw, ret),
8219                          i40e_aq_str(hw, hw->aq.asq_last_status));
8220                 goto out;
8221         }
8222
8223         vsi->enabled_tc = tc_map;
8224
8225 out:
8226         return ret;
8227 }
8228
8229 /*
8230  * i40e_dcb_hw_configure - program the dcb setting to hw
8231  * @pf: pf the configuration is taken on
8232  * @new_cfg: new configuration
8233  * @tc_map: enabled TC bitmap
8234  *
8235  * Returns 0 on success, negative value on failure
8236  */
8237 static enum i40e_status_code
8238 i40e_dcb_hw_configure(struct i40e_pf *pf,
8239                       struct i40e_dcbx_config *new_cfg,
8240                       uint8_t tc_map)
8241 {
8242         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8243         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8244         struct i40e_vsi *main_vsi = pf->main_vsi;
8245         struct i40e_vsi_list *vsi_list;
8246         enum i40e_status_code ret;
8247         int i;
8248         uint32_t val;
8249
8250         /* Use the FW API if FW > v4.4*/
8251         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8252               (hw->aq.fw_maj_ver >= 5))) {
8253                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8254                                   " to configure DCB");
8255                 return I40E_ERR_FIRMWARE_API_VERSION;
8256         }
8257
8258         /* Check if need reconfiguration */
8259         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8260                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8261                 return I40E_SUCCESS;
8262         }
8263
8264         /* Copy the new config to the current config */
8265         *old_cfg = *new_cfg;
8266         old_cfg->etsrec = old_cfg->etscfg;
8267         ret = i40e_set_dcb_config(hw);
8268         if (ret) {
8269                 PMD_INIT_LOG(ERR,
8270                          "Set DCB Config failed, err %s aq_err %s\n",
8271                          i40e_stat_str(hw, ret),
8272                          i40e_aq_str(hw, hw->aq.asq_last_status));
8273                 return ret;
8274         }
8275         /* set receive Arbiter to RR mode and ETS scheme by default */
8276         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8277                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8278                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8279                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8280                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8281                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8282                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8283                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8284                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8285                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8286                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8287                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8288                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8289         }
8290         /* get local mib to check whether it is configured correctly */
8291         /* IEEE mode */
8292         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8293         /* Get Local DCB Config */
8294         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8295                                      &hw->local_dcbx_config);
8296
8297         /* Update each VSI */
8298         i40e_vsi_config_tc(main_vsi, tc_map);
8299         if (main_vsi->veb) {
8300                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8301                         /* Beside main VSI, only enable default
8302                          * TC for other VSIs
8303                          */
8304                         ret = i40e_vsi_config_tc(vsi_list->vsi,
8305                                                 I40E_DEFAULT_TCMAP);
8306                         if (ret)
8307                                 PMD_INIT_LOG(WARNING,
8308                                          "Failed configuring TC for VSI seid=%d\n",
8309                                          vsi_list->vsi->seid);
8310                         /* continue */
8311                 }
8312         }
8313         return I40E_SUCCESS;
8314 }
8315
8316 /*
8317  * i40e_dcb_init_configure - initial dcb config
8318  * @dev: device being configured
8319  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8320  *
8321  * Returns 0 on success, negative value on failure
8322  */
8323 static int
8324 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8325 {
8326         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8327         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8328         int ret = 0;
8329
8330         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8331                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8332                 return -ENOTSUP;
8333         }
8334
8335         /* DCB initialization:
8336          * Update DCB configuration from the Firmware and configure
8337          * LLDP MIB change event.
8338          */
8339         if (sw_dcb == TRUE) {
8340                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8341                 if (ret != I40E_SUCCESS)
8342                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8343
8344                 ret = i40e_init_dcb(hw);
8345                 /* if sw_dcb, lldp agent is stopped, the return from
8346                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8347                  * adminq status.
8348                  */
8349                 if (ret != I40E_SUCCESS &&
8350                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8351                         memset(&hw->local_dcbx_config, 0,
8352                                 sizeof(struct i40e_dcbx_config));
8353                         /* set dcb default configuration */
8354                         hw->local_dcbx_config.etscfg.willing = 0;
8355                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8356                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8357                         hw->local_dcbx_config.etscfg.tsatable[0] =
8358                                                 I40E_IEEE_TSA_ETS;
8359                         hw->local_dcbx_config.etsrec =
8360                                 hw->local_dcbx_config.etscfg;
8361                         hw->local_dcbx_config.pfc.willing = 0;
8362                         hw->local_dcbx_config.pfc.pfccap =
8363                                                 I40E_MAX_TRAFFIC_CLASS;
8364                         /* FW needs one App to configure HW */
8365                         hw->local_dcbx_config.numapps = 1;
8366                         hw->local_dcbx_config.app[0].selector =
8367                                                 I40E_APP_SEL_ETHTYPE;
8368                         hw->local_dcbx_config.app[0].priority = 3;
8369                         hw->local_dcbx_config.app[0].protocolid =
8370                                                 I40E_APP_PROTOID_FCOE;
8371                         ret = i40e_set_dcb_config(hw);
8372                         if (ret) {
8373                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8374                                         " err = %d, aq_err = %d.", ret,
8375                                           hw->aq.asq_last_status);
8376                                 return -ENOSYS;
8377                         }
8378                 } else {
8379                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8380                                           " aq_err = %d.", ret,
8381                                           hw->aq.asq_last_status);
8382                         return -ENOTSUP;
8383                 }
8384         } else {
8385                 ret = i40e_aq_start_lldp(hw, NULL);
8386                 if (ret != I40E_SUCCESS)
8387                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8388
8389                 ret = i40e_init_dcb(hw);
8390                 if (!ret) {
8391                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8392                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8393                                                   " DCBX offload.");
8394                                 return -ENOTSUP;
8395                         }
8396                 } else {
8397                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8398                                           " aq_err = %d.", ret,
8399                                           hw->aq.asq_last_status);
8400                         return -ENOTSUP;
8401                 }
8402         }
8403         return 0;
8404 }
8405
8406 /*
8407  * i40e_dcb_setup - setup dcb related config
8408  * @dev: device being configured
8409  *
8410  * Returns 0 on success, negative value on failure
8411  */
8412 static int
8413 i40e_dcb_setup(struct rte_eth_dev *dev)
8414 {
8415         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8416         struct i40e_dcbx_config dcb_cfg;
8417         uint8_t tc_map = 0;
8418         int ret = 0;
8419
8420         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8421                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8422                 return -ENOTSUP;
8423         }
8424
8425         if (pf->vf_num != 0 ||
8426             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8427                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8428
8429         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8430         if (ret) {
8431                 PMD_INIT_LOG(ERR, "invalid dcb config");
8432                 return -EINVAL;
8433         }
8434         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8435         if (ret) {
8436                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8437                 return -ENOSYS;
8438         }
8439
8440         return 0;
8441 }
8442
8443 static int
8444 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8445                       struct rte_eth_dcb_info *dcb_info)
8446 {
8447         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8448         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8449         struct i40e_vsi *vsi = pf->main_vsi;
8450         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8451         uint16_t bsf, tc_mapping;
8452         int i;
8453
8454         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8455                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8456         else
8457                 dcb_info->nb_tcs = 1;
8458         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8459                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8460         for (i = 0; i < dcb_info->nb_tcs; i++)
8461                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8462
8463         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8464                 if (vsi->enabled_tc & (1 << i)) {
8465                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8466                         /* only main vsi support multi TCs */
8467                         dcb_info->tc_queue.tc_rxq[0][i].base =
8468                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8469                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8470                         dcb_info->tc_queue.tc_txq[0][i].base =
8471                                 dcb_info->tc_queue.tc_rxq[0][i].base;
8472                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8473                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8474                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8475                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8476                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
8477                 }
8478         }
8479
8480         return 0;
8481 }
8482
8483 static int
8484 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8485 {
8486         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8487         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8488         uint16_t interval =
8489                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8490         uint16_t msix_intr;
8491
8492         msix_intr = intr_handle->intr_vec[queue_id];
8493         if (msix_intr == I40E_MISC_VEC_ID)
8494                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8495                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8496                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8497                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8498                                (interval <<
8499                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8500         else
8501                 I40E_WRITE_REG(hw,
8502                                I40E_PFINT_DYN_CTLN(msix_intr -
8503                                                    I40E_RX_VEC_START),
8504                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8505                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8506                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8507                                (interval <<
8508                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8509
8510         I40E_WRITE_FLUSH(hw);
8511         rte_intr_enable(&dev->pci_dev->intr_handle);
8512
8513         return 0;
8514 }
8515
8516 static int
8517 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8518 {
8519         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8520         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8521         uint16_t msix_intr;
8522
8523         msix_intr = intr_handle->intr_vec[queue_id];
8524         if (msix_intr == I40E_MISC_VEC_ID)
8525                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8526         else
8527                 I40E_WRITE_REG(hw,
8528                                I40E_PFINT_DYN_CTLN(msix_intr -
8529                                                    I40E_RX_VEC_START),
8530                                0);
8531         I40E_WRITE_FLUSH(hw);
8532
8533         return 0;
8534 }