drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  47
  48 #define I40E_CLEAR_PXE_WAIT_MS     200
  49
  50 /* Maximun number of capability elements */
  51 #define I40E_MAX_CAP_ELE_NUM       128
  52
  53 /* Wait count and interval */
  54 #define I40E_CHK_Q_ENA_COUNT       1000
  55 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  56
  57 /* Maximun number of VSI */
  58 #define I40E_MAX_NUM_VSIS          (384UL)
  59
  60 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  61
  62 /* Flow control default timer */
  63 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  64
  65 /* Flow control enable fwd bit */
  66 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  67
  68 /* Receive Packet Buffer size */
  69 #define I40E_RXPBSIZE (968 * 1024)
  70
  71 /* Kilobytes shift */
  72 #define I40E_KILOSHIFT 10
  73
  74 /* Flow control default high water */
  75 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Flow control default low water */
  78 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  79
  80 /* Receive Average Packet Size in Byte*/
  81 #define I40E_PACKET_AVERAGE_SIZE 128
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  94
  95 #define I40E_FLOW_TYPES ( \
  96         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 101         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 106         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 107
 108 /* Additional timesync values. */
 109 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 110 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 111 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 112 #define I40E_PRTTSYN_TSYNENA     0x80000000
 113 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 114 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 115
 116 /**
 117  * Below are values for writing un-exposed registers suggested
 118  * by silicon experts
 119  */
 120 /* Destination MAC address */
 121 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 122 /* Source MAC address */
 123 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 124 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 125 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 126 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 127 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 128 /* Single VLAN tag in the inner L2 header */
 129 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 130 /* Source IPv4 address */
 131 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 132 /* Destination IPv4 address */
 133 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 134 /* Source IPv4 address for X722 */
 135 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 136 /* Destination IPv4 address for X722 */
 137 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 138 /* IPv4 Protocol for X722 */
 139 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 140 /* IPv4 Time to Live for X722 */
 141 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 142 /* IPv4 Type of Service (TOS) */
 143 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 144 /* IPv4 Protocol */
 145 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 146 /* IPv4 Time to Live */
 147 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 148 /* Source IPv6 address */
 149 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 150 /* Destination IPv6 address */
 151 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 152 /* IPv6 Traffic Class (TC) */
 153 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 154 /* IPv6 Next Header */
 155 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 156 /* IPv6 Hop Limit */
 157 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 158 /* Source L4 port */
 159 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 160 /* Destination L4 port */
 161 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 162 /* SCTP verification tag */
 163 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 164 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 165 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 166 /* Source port of tunneling UDP */
 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 168 /* Destination port of tunneling UDP */
 169 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 170 /* UDP Tunneling ID, NVGRE/GRE key */
 171 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 172 /* Last ether type */
 173 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 174 /* Tunneling outer destination IPv4 address */
 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 176 /* Tunneling outer destination IPv6 address */
 177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 178 /* 1st word of flex payload */
 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 180 /* 2nd word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 182 /* 3rd word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 184 /* 4th word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 186 /* 5th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 188 /* 6th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 190 /* 7th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 192 /* 8th word of flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 194 /* all 8 words flex payload */
 195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 196 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 197
 198 #define I40E_TRANSLATE_INSET 0
 199 #define I40E_TRANSLATE_REG   1
 200
 201 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 202 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 203 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 204 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 205 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 206 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 207
 208 /* PCI offset for querying capability */
 209 #define PCI_DEV_CAP_REG            0xA4
 210 /* PCI offset for enabling/disabling Extended Tag */
 211 #define PCI_DEV_CTRL_REG           0xA8
 212 /* Bit mask of Extended Tag capability */
 213 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 214 /* Bit shift of Extended Tag enable/disable */
 215 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 216 /* Bit mask of Extended Tag enable/disable */
 217 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 218
 219 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 220 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 221 static int i40e_dev_configure(struct rte_eth_dev *dev);
 222 static int i40e_dev_start(struct rte_eth_dev *dev);
 223 static void i40e_dev_stop(struct rte_eth_dev *dev);
 224 static void i40e_dev_close(struct rte_eth_dev *dev);
 225 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 226 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 227 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 228 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 229 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 230 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 232 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 233                                struct rte_eth_stats *stats);
 234 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 235                                struct rte_eth_xstat *xstats, unsigned n);
 236 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 237                                      struct rte_eth_xstat_name *xstats_names,
 238                                      unsigned limit);
 239 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 240 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 241                                             uint16_t queue_id,
 242                                             uint8_t stat_idx,
 243                                             uint8_t is_rx);
 244 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 245                                 char *fw_version, size_t fw_size);
 246 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 247                               struct rte_eth_dev_info *dev_info);
 248 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 249                                 uint16_t vlan_id,
 250                                 int on);
 251 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 252                               enum rte_vlan_type vlan_type,
 253                               uint16_t tpid);
 254 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 255 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 256                                       uint16_t queue,
 257                                       int on);
 258 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 259 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 260 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 261 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 264                               struct rte_eth_fc_conf *fc_conf);
 265 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 266                                        struct rte_eth_pfc_conf *pfc_conf);
 267 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 268                             struct rte_ether_addr *mac_addr,
 269                             uint32_t index,
 270                             uint32_t pool);
 271 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 272 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 273                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                     uint16_t reta_size);
 275 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 276                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 277                                    uint16_t reta_size);
 278
 279 static int i40e_get_cap(struct i40e_hw *hw);
 280 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 281 static int i40e_pf_setup(struct i40e_pf *pf);
 282 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 283 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 284 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 285 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 286                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 287 static void i40e_stat_update_48(struct i40e_hw *hw,
 288                                uint32_t hireg,
 289                                uint32_t loreg,
 290                                bool offset_loaded,
 291                                uint64_t *offset,
 292                                uint64_t *stat);
 293 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 294 static void i40e_dev_interrupt_handler(void *param);
 295 static void i40e_dev_alarm_handler(void *param);
 296 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 297                                 uint32_t base, uint32_t num);
 298 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 299 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 300                         uint32_t base);
 301 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 302                         uint16_t num);
 303 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 304 static int i40e_veb_release(struct i40e_veb *veb);
 305 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 306                                                 struct i40e_vsi *vsi);
 307 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 308 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 309 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 310                                              struct i40e_macvlan_filter *mv_f,
 311                                              int num,
 312                                              uint16_t vlan);
 313 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 314 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 315                                     struct rte_eth_rss_conf *rss_conf);
 316 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 317                                       struct rte_eth_rss_conf *rss_conf);
 318 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 319                                         struct rte_eth_udp_tunnel *udp_tunnel);
 320 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 321                                         struct rte_eth_udp_tunnel *udp_tunnel);
 322 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 323 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 327                                 enum rte_filter_type filter_type,
 328                                 enum rte_filter_op filter_op,
 329                                 void *arg);
 330 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 331                                   struct rte_eth_dcb_info *dcb_info);
 332 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 333 static void i40e_configure_registers(struct i40e_hw *hw);
 334 static void i40e_hw_init(struct rte_eth_dev *dev);
 335 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 336 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 337                                                      uint16_t seid,
 338                                                      uint16_t rule_type,
 339                                                      uint16_t *entries,
 340                                                      uint16_t count,
 341                                                      uint16_t rule_id);
 342 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 343                         struct rte_eth_mirror_conf *mirror_conf,
 344                         uint8_t sw_id, uint8_t on);
 345 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 346
 347 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 348 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 349 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp,
 351                                            uint32_t flags);
 352 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 353                                            struct timespec *timestamp);
 354 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 355
 356 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 357
 358 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 359                                    struct timespec *timestamp);
 360 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 361                                     const struct timespec *timestamp);
 362
 363 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 364                                          uint16_t queue_id);
 365 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 366                                           uint16_t queue_id);
 367
 368 static int i40e_get_regs(struct rte_eth_dev *dev,
 369                          struct rte_dev_reg_info *regs);
 370
 371 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 372
 373 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 374                            struct rte_dev_eeprom_info *eeprom);
 375
 376 static int i40e_get_module_info(struct rte_eth_dev *dev,
 377                                 struct rte_eth_dev_module_info *modinfo);
 378 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 379                                   struct rte_dev_eeprom_info *info);
 380
 381 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 382                                       struct rte_ether_addr *mac_addr);
 383
 384 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 385
 386 static int i40e_ethertype_filter_convert(
 387         const struct rte_eth_ethertype_filter *input,
 388         struct i40e_ethertype_filter *filter);
 389 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 390                                    struct i40e_ethertype_filter *filter);
 391
 392 static int i40e_tunnel_filter_convert(
 393         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 394         struct i40e_tunnel_filter *tunnel_filter);
 395 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 396                                 struct i40e_tunnel_filter *tunnel_filter);
 397 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 398
 399 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 400 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 401 static void i40e_filter_restore(struct i40e_pf *pf);
 402 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 403
 404 int i40e_logtype_init;
 405 int i40e_logtype_driver;
 406
 407 static const char *const valid_keys[] = {
 408         ETH_I40E_FLOATING_VEB_ARG,
 409         ETH_I40E_FLOATING_VEB_LIST_ARG,
 410         ETH_I40E_SUPPORT_MULTI_DRIVER,
 411         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 412         ETH_I40E_USE_LATEST_VEC,
 413         NULL};
 414
 415 static const struct rte_pci_id pci_id_i40e_map[] = {
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 439         { .vendor_id = 0, /* sentinel */ },
 440 };
 441
 442 static const struct eth_dev_ops i40e_eth_dev_ops = {
 443         .dev_configure                = i40e_dev_configure,
 444         .dev_start                    = i40e_dev_start,
 445         .dev_stop                     = i40e_dev_stop,
 446         .dev_close                    = i40e_dev_close,
 447         .dev_reset                    = i40e_dev_reset,
 448         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 449         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 450         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 451         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 452         .dev_set_link_up              = i40e_dev_set_link_up,
 453         .dev_set_link_down            = i40e_dev_set_link_down,
 454         .link_update                  = i40e_dev_link_update,
 455         .stats_get                    = i40e_dev_stats_get,
 456         .xstats_get                   = i40e_dev_xstats_get,
 457         .xstats_get_names             = i40e_dev_xstats_get_names,
 458         .stats_reset                  = i40e_dev_stats_reset,
 459         .xstats_reset                 = i40e_dev_stats_reset,
 460         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 461         .fw_version_get               = i40e_fw_version_get,
 462         .dev_infos_get                = i40e_dev_info_get,
 463         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 464         .vlan_filter_set              = i40e_vlan_filter_set,
 465         .vlan_tpid_set                = i40e_vlan_tpid_set,
 466         .vlan_offload_set             = i40e_vlan_offload_set,
 467         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 468         .vlan_pvid_set                = i40e_vlan_pvid_set,
 469         .rx_queue_start               = i40e_dev_rx_queue_start,
 470         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 471         .tx_queue_start               = i40e_dev_tx_queue_start,
 472         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 473         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 474         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 475         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 476         .rx_queue_release             = i40e_dev_rx_queue_release,
 477         .rx_queue_count               = i40e_dev_rx_queue_count,
 478         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 479         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 480         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 481         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 482         .tx_queue_release             = i40e_dev_tx_queue_release,
 483         .dev_led_on                   = i40e_dev_led_on,
 484         .dev_led_off                  = i40e_dev_led_off,
 485         .flow_ctrl_get                = i40e_flow_ctrl_get,
 486         .flow_ctrl_set                = i40e_flow_ctrl_set,
 487         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 488         .mac_addr_add                 = i40e_macaddr_add,
 489         .mac_addr_remove              = i40e_macaddr_remove,
 490         .reta_update                  = i40e_dev_rss_reta_update,
 491         .reta_query                   = i40e_dev_rss_reta_query,
 492         .rss_hash_update              = i40e_dev_rss_hash_update,
 493         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 494         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 495         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 496         .filter_ctrl                  = i40e_dev_filter_ctrl,
 497         .rxq_info_get                 = i40e_rxq_info_get,
 498         .txq_info_get                 = i40e_txq_info_get,
 499         .mirror_rule_set              = i40e_mirror_rule_set,
 500         .mirror_rule_reset            = i40e_mirror_rule_reset,
 501         .timesync_enable              = i40e_timesync_enable,
 502         .timesync_disable             = i40e_timesync_disable,
 503         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 504         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 505         .get_dcb_info                 = i40e_dev_get_dcb_info,
 506         .timesync_adjust_time         = i40e_timesync_adjust_time,
 507         .timesync_read_time           = i40e_timesync_read_time,
 508         .timesync_write_time          = i40e_timesync_write_time,
 509         .get_reg                      = i40e_get_regs,
 510         .get_eeprom_length            = i40e_get_eeprom_length,
 511         .get_eeprom                   = i40e_get_eeprom,
 512         .get_module_info              = i40e_get_module_info,
 513         .get_module_eeprom            = i40e_get_module_eeprom,
 514         .mac_addr_set                 = i40e_set_default_mac_addr,
 515         .mtu_set                      = i40e_dev_mtu_set,
 516         .tm_ops_get                   = i40e_tm_ops_get,
 517 };
 518
 519 /* store statistics names and its offset in stats structure */
 520 struct rte_i40e_xstats_name_off {
 521         char name[RTE_ETH_XSTATS_NAME_SIZE];
 522         unsigned offset;
 523 };
 524
 525 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 526         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 527         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 528         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 529         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 530         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 531                 rx_unknown_protocol)},
 532         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 533         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 534         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 535         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 536 };
 537
 538 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 539                 sizeof(rte_i40e_stats_strings[0]))
 540
 541 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 542         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 543                 tx_dropped_link_down)},
 544         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 545         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 546                 illegal_bytes)},
 547         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 548         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_local_faults)},
 550         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 551                 mac_remote_faults)},
 552         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 553                 rx_length_errors)},
 554         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 555         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 556         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 557         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 558         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 559         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_127)},
 561         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_255)},
 563         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_511)},
 565         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1023)},
 567         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_1522)},
 569         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_big)},
 571         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_undersize)},
 573         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_oversize)},
 575         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 576                 mac_short_packet_dropped)},
 577         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_fragments)},
 579         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 580         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 581         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_127)},
 583         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_255)},
 585         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_511)},
 587         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1023)},
 589         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_1522)},
 591         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_big)},
 593         {"rx_flow_director_atr_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 595         {"rx_flow_director_sb_match_packets",
 596                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 597         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 tx_lpi_status)},
 599         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 600                 rx_lpi_status)},
 601         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 tx_lpi_count)},
 603         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 604                 rx_lpi_count)},
 605 };
 606
 607 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 608                 sizeof(rte_i40e_hw_port_strings[0]))
 609
 610 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 611         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xon_rx)},
 613         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 614                 priority_xoff_rx)},
 615 };
 616
 617 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 618                 sizeof(rte_i40e_rxq_prio_strings[0]))
 619
 620 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 621         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xon_tx)},
 623         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xoff_tx)},
 625         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_2_xoff)},
 627 };
 628
 629 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 630                 sizeof(rte_i40e_txq_prio_strings[0]))
 631
 632 static int
 633 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 634         struct rte_pci_device *pci_dev)
 635 {
 636         char name[RTE_ETH_NAME_MAX_LEN];
 637         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 638         int i, retval;
 639
 640         if (pci_dev->device.devargs) {
 641                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 642                                 &eth_da);
 643                 if (retval)
 644                         return retval;
 645         }
 646
 647         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 648                 sizeof(struct i40e_adapter),
 649                 eth_dev_pci_specific_init, pci_dev,
 650                 eth_i40e_dev_init, NULL);
 651
 652         if (retval || eth_da.nb_representor_ports < 1)
 653                 return retval;
 654
 655         /* probe VF representor ports */
 656         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 657                 pci_dev->device.name);
 658
 659         if (pf_ethdev == NULL)
 660                 return -ENODEV;
 661
 662         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 663                 struct i40e_vf_representor representor = {
 664                         .vf_id = eth_da.representor_ports[i],
 665                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 666                                 pf_ethdev->data->dev_private)->switch_domain_id,
 667                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 668                                 pf_ethdev->data->dev_private)
 669                 };
 670
 671                 /* representor port net_bdf_port */
 672                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 673                         pci_dev->device.name, eth_da.representor_ports[i]);
 674
 675                 retval = rte_eth_dev_create(&pci_dev->device, name,
 676                         sizeof(struct i40e_vf_representor), NULL, NULL,
 677                         i40e_vf_representor_init, &representor);
 678
 679                 if (retval)
 680                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 681                                 "representor %s.", name);
 682         }
 683
 684         return 0;
 685 }
 686
 687 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 688 {
 689         struct rte_eth_dev *ethdev;
 690
 691         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 692         if (!ethdev)
 693                 return -ENODEV;
 694
 695
 696         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 697                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 698         else
 699                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 700 }
 701
 702 static struct rte_pci_driver rte_i40e_pmd = {
 703         .id_table = pci_id_i40e_map,
 704         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 705                      RTE_PCI_DRV_IOVA_AS_VA,
 706         .probe = eth_i40e_pci_probe,
 707         .remove = eth_i40e_pci_remove,
 708 };
 709
 710 static inline void
 711 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 712                          uint32_t reg_val)
 713 {
 714         uint32_t ori_reg_val;
 715         struct rte_eth_dev *dev;
 716
 717         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 718         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 719         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 720         if (ori_reg_val != reg_val)
 721                 PMD_DRV_LOG(WARNING,
 722                             "i40e device %s changed global register [0x%08x]."
 723                             " original: 0x%08x, new: 0x%08x",
 724                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 725 }
 726
 727 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 728 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 729 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 730
 731 #ifndef I40E_GLQF_ORT
 732 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 733 #endif
 734 #ifndef I40E_GLQF_PIT
 735 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 736 #endif
 737 #ifndef I40E_GLQF_L3_MAP
 738 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 739 #endif
 740
 741 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 742 {
 743         /*
 744          * Initialize registers for parsing packet type of QinQ
 745          * This should be removed from code once proper
 746          * configuration API is added to avoid configuration conflicts
 747          * between ports of the same device.
 748          */
 749         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 750         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 751 }
 752
 753 static inline void i40e_config_automask(struct i40e_pf *pf)
 754 {
 755         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 756         uint32_t val;
 757
 758         /* INTENA flag is not auto-cleared for interrupt */
 759         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 760         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 761                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 762
 763         /* If support multi-driver, PF will use INT0. */
 764         if (!pf->support_multi_driver)
 765                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 766
 767         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 768 }
 769
 770 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 771
 772 /*
 773  * Add a ethertype filter to drop all flow control frames transmitted
 774  * from VSIs.
 775 */
 776 static void
 777 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 778 {
 779         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 780         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 781                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 782                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 783         int ret;
 784
 785         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 786                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 787                                 pf->main_vsi_seid, 0,
 788                                 TRUE, NULL, NULL);
 789         if (ret)
 790                 PMD_INIT_LOG(ERR,
 791                         "Failed to add filter to drop flow control frames from VSIs.");
 792 }
 793
 794 static int
 795 floating_veb_list_handler(__rte_unused const char *key,
 796                           const char *floating_veb_value,
 797                           void *opaque)
 798 {
 799         int idx = 0;
 800         unsigned int count = 0;
 801         char *end = NULL;
 802         int min, max;
 803         bool *vf_floating_veb = opaque;
 804
 805         while (isblank(*floating_veb_value))
 806                 floating_veb_value++;
 807
 808         /* Reset floating VEB configuration for VFs */
 809         for (idx = 0; idx < I40E_MAX_VF; idx++)
 810                 vf_floating_veb[idx] = false;
 811
 812         min = I40E_MAX_VF;
 813         do {
 814                 while (isblank(*floating_veb_value))
 815                         floating_veb_value++;
 816                 if (*floating_veb_value == '\0')
 817                         return -1;
 818                 errno = 0;
 819                 idx = strtoul(floating_veb_value, &end, 10);
 820                 if (errno || end == NULL)
 821                         return -1;
 822                 while (isblank(*end))
 823                         end++;
 824                 if (*end == '-') {
 825                         min = idx;
 826                 } else if ((*end == ';') || (*end == '\0')) {
 827                         max = idx;
 828                         if (min == I40E_MAX_VF)
 829                                 min = idx;
 830                         if (max >= I40E_MAX_VF)
 831                                 max = I40E_MAX_VF - 1;
 832                         for (idx = min; idx <= max; idx++) {
 833                                 vf_floating_veb[idx] = true;
 834                                 count++;
 835                         }
 836                         min = I40E_MAX_VF;
 837                 } else {
 838                         return -1;
 839                 }
 840                 floating_veb_value = end + 1;
 841         } while (*end != '\0');
 842
 843         if (count == 0)
 844                 return -1;
 845
 846         return 0;
 847 }
 848
 849 static void
 850 config_vf_floating_veb(struct rte_devargs *devargs,
 851                        uint16_t floating_veb,
 852                        bool *vf_floating_veb)
 853 {
 854         struct rte_kvargs *kvlist;
 855         int i;
 856         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 857
 858         if (!floating_veb)
 859                 return;
 860         /* All the VFs attach to the floating VEB by default
 861          * when the floating VEB is enabled.
 862          */
 863         for (i = 0; i < I40E_MAX_VF; i++)
 864                 vf_floating_veb[i] = true;
 865
 866         if (devargs == NULL)
 867                 return;
 868
 869         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 870         if (kvlist == NULL)
 871                 return;
 872
 873         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 874                 rte_kvargs_free(kvlist);
 875                 return;
 876         }
 877         /* When the floating_veb_list parameter exists, all the VFs
 878          * will attach to the legacy VEB firstly, then configure VFs
 879          * to the floating VEB according to the floating_veb_list.
 880          */
 881         if (rte_kvargs_process(kvlist, floating_veb_list,
 882                                floating_veb_list_handler,
 883                                vf_floating_veb) < 0) {
 884                 rte_kvargs_free(kvlist);
 885                 return;
 886         }
 887         rte_kvargs_free(kvlist);
 888 }
 889
 890 static int
 891 i40e_check_floating_handler(__rte_unused const char *key,
 892                             const char *value,
 893                             __rte_unused void *opaque)
 894 {
 895         if (strcmp(value, "1"))
 896                 return -1;
 897
 898         return 0;
 899 }
 900
 901 static int
 902 is_floating_veb_supported(struct rte_devargs *devargs)
 903 {
 904         struct rte_kvargs *kvlist;
 905         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 906
 907         if (devargs == NULL)
 908                 return 0;
 909
 910         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 911         if (kvlist == NULL)
 912                 return 0;
 913
 914         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 915                 rte_kvargs_free(kvlist);
 916                 return 0;
 917         }
 918         /* Floating VEB is enabled when there's key-value:
 919          * enable_floating_veb=1
 920          */
 921         if (rte_kvargs_process(kvlist, floating_veb_key,
 922                                i40e_check_floating_handler, NULL) < 0) {
 923                 rte_kvargs_free(kvlist);
 924                 return 0;
 925         }
 926         rte_kvargs_free(kvlist);
 927
 928         return 1;
 929 }
 930
 931 static void
 932 config_floating_veb(struct rte_eth_dev *dev)
 933 {
 934         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 935         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 936         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 937
 938         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 939
 940         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 941                 pf->floating_veb =
 942                         is_floating_veb_supported(pci_dev->device.devargs);
 943                 config_vf_floating_veb(pci_dev->device.devargs,
 944                                        pf->floating_veb,
 945                                        pf->floating_veb_list);
 946         } else {
 947                 pf->floating_veb = false;
 948         }
 949 }
 950
 951 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 952 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 953
 954 static int
 955 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 956 {
 957         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 958         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 959         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 960         int ret;
 961
 962         struct rte_hash_parameters ethertype_hash_params = {
 963                 .name = ethertype_hash_name,
 964                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 965                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 966                 .hash_func = rte_hash_crc,
 967                 .hash_func_init_val = 0,
 968                 .socket_id = rte_socket_id(),
 969         };
 970
 971         /* Initialize ethertype filter rule list and hash */
 972         TAILQ_INIT(&ethertype_rule->ethertype_list);
 973         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 974                  "ethertype_%s", dev->device->name);
 975         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 976         if (!ethertype_rule->hash_table) {
 977                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 978                 return -EINVAL;
 979         }
 980         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 981                                        sizeof(struct i40e_ethertype_filter *) *
 982                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 983                                        0);
 984         if (!ethertype_rule->hash_map) {
 985                 PMD_INIT_LOG(ERR,
 986                              "Failed to allocate memory for ethertype hash map!");
 987                 ret = -ENOMEM;
 988                 goto err_ethertype_hash_map_alloc;
 989         }
 990
 991         return 0;
 992
 993 err_ethertype_hash_map_alloc:
 994         rte_hash_free(ethertype_rule->hash_table);
 995
 996         return ret;
 997 }
 998
 999 static int
1000 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1001 {
1002         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1003         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1004         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1005         int ret;
1006
1007         struct rte_hash_parameters tunnel_hash_params = {
1008                 .name = tunnel_hash_name,
1009                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1010                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1011                 .hash_func = rte_hash_crc,
1012                 .hash_func_init_val = 0,
1013                 .socket_id = rte_socket_id(),
1014         };
1015
1016         /* Initialize tunnel filter rule list and hash */
1017         TAILQ_INIT(&tunnel_rule->tunnel_list);
1018         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1019                  "tunnel_%s", dev->device->name);
1020         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1021         if (!tunnel_rule->hash_table) {
1022                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1023                 return -EINVAL;
1024         }
1025         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1026                                     sizeof(struct i40e_tunnel_filter *) *
1027                                     I40E_MAX_TUNNEL_FILTER_NUM,
1028                                     0);
1029         if (!tunnel_rule->hash_map) {
1030                 PMD_INIT_LOG(ERR,
1031                              "Failed to allocate memory for tunnel hash map!");
1032                 ret = -ENOMEM;
1033                 goto err_tunnel_hash_map_alloc;
1034         }
1035
1036         return 0;
1037
1038 err_tunnel_hash_map_alloc:
1039         rte_hash_free(tunnel_rule->hash_table);
1040
1041         return ret;
1042 }
1043
1044 static int
1045 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1046 {
1047         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1048         struct i40e_fdir_info *fdir_info = &pf->fdir;
1049         char fdir_hash_name[RTE_HASH_NAMESIZE];
1050         int ret;
1051
1052         struct rte_hash_parameters fdir_hash_params = {
1053                 .name = fdir_hash_name,
1054                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1055                 .key_len = sizeof(struct i40e_fdir_input),
1056                 .hash_func = rte_hash_crc,
1057                 .hash_func_init_val = 0,
1058                 .socket_id = rte_socket_id(),
1059         };
1060
1061         /* Initialize flow director filter rule list and hash */
1062         TAILQ_INIT(&fdir_info->fdir_list);
1063         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1064                  "fdir_%s", dev->device->name);
1065         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1066         if (!fdir_info->hash_table) {
1067                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1068                 return -EINVAL;
1069         }
1070         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1071                                           sizeof(struct i40e_fdir_filter *) *
1072                                           I40E_MAX_FDIR_FILTER_NUM,
1073                                           0);
1074         if (!fdir_info->hash_map) {
1075                 PMD_INIT_LOG(ERR,
1076                              "Failed to allocate memory for fdir hash map!");
1077                 ret = -ENOMEM;
1078                 goto err_fdir_hash_map_alloc;
1079         }
1080         return 0;
1081
1082 err_fdir_hash_map_alloc:
1083         rte_hash_free(fdir_info->hash_table);
1084
1085         return ret;
1086 }
1087
1088 static void
1089 i40e_init_customized_info(struct i40e_pf *pf)
1090 {
1091         int i;
1092
1093         /* Initialize customized pctype */
1094         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1095                 pf->customized_pctype[i].index = i;
1096                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1097                 pf->customized_pctype[i].valid = false;
1098         }
1099
1100         pf->gtp_support = false;
1101 }
1102
1103 void
1104 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1105 {
1106         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1107         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1108         struct i40e_queue_regions *info = &pf->queue_region;
1109         uint16_t i;
1110
1111         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1112                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1113
1114         memset(info, 0, sizeof(struct i40e_queue_regions));
1115 }
1116
1117 static int
1118 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1119                                const char *value,
1120                                void *opaque)
1121 {
1122         struct i40e_pf *pf;
1123         unsigned long support_multi_driver;
1124         char *end;
1125
1126         pf = (struct i40e_pf *)opaque;
1127
1128         errno = 0;
1129         support_multi_driver = strtoul(value, &end, 10);
1130         if (errno != 0 || end == value || *end != 0) {
1131                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1132                 return -(EINVAL);
1133         }
1134
1135         if (support_multi_driver == 1 || support_multi_driver == 0)
1136                 pf->support_multi_driver = (bool)support_multi_driver;
1137         else
1138                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1139                             "enable global configuration by default."
1140                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1141         return 0;
1142 }
1143
1144 static int
1145 i40e_support_multi_driver(struct rte_eth_dev *dev)
1146 {
1147         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1148         struct rte_kvargs *kvlist;
1149         int kvargs_count;
1150
1151         /* Enable global configuration by default */
1152         pf->support_multi_driver = false;
1153
1154         if (!dev->device->devargs)
1155                 return 0;
1156
1157         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1158         if (!kvlist)
1159                 return -EINVAL;
1160
1161         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1162         if (!kvargs_count) {
1163                 rte_kvargs_free(kvlist);
1164                 return 0;
1165         }
1166
1167         if (kvargs_count > 1)
1168                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1169                             "the first invalid or last valid one is used !",
1170                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1171
1172         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1173                                i40e_parse_multi_drv_handler, pf) < 0) {
1174                 rte_kvargs_free(kvlist);
1175                 return -EINVAL;
1176         }
1177
1178         rte_kvargs_free(kvlist);
1179         return 0;
1180 }
1181
1182 static int
1183 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1184                                     uint32_t reg_addr, uint64_t reg_val,
1185                                     struct i40e_asq_cmd_details *cmd_details)
1186 {
1187         uint64_t ori_reg_val;
1188         struct rte_eth_dev *dev;
1189         int ret;
1190
1191         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1192         if (ret != I40E_SUCCESS) {
1193                 PMD_DRV_LOG(ERR,
1194                             "Fail to debug read from 0x%08x",
1195                             reg_addr);
1196                 return -EIO;
1197         }
1198         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1199
1200         if (ori_reg_val != reg_val)
1201                 PMD_DRV_LOG(WARNING,
1202                             "i40e device %s changed global register [0x%08x]."
1203                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1204                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1205
1206         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1207 }
1208
1209 static int
1210 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1211                                 const char *value,
1212                                 void *opaque)
1213 {
1214         struct i40e_adapter *ad;
1215         int use_latest_vec;
1216
1217         ad = (struct i40e_adapter *)opaque;
1218
1219         use_latest_vec = atoi(value);
1220
1221         if (use_latest_vec != 0 && use_latest_vec != 1)
1222                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1223
1224         ad->use_latest_vec = (uint8_t)use_latest_vec;
1225
1226         return 0;
1227 }
1228
1229 static int
1230 i40e_use_latest_vec(struct rte_eth_dev *dev)
1231 {
1232         struct i40e_adapter *ad =
1233                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1234         struct rte_kvargs *kvlist;
1235         int kvargs_count;
1236
1237         ad->use_latest_vec = false;
1238
1239         if (!dev->device->devargs)
1240                 return 0;
1241
1242         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1243         if (!kvlist)
1244                 return -EINVAL;
1245
1246         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1247         if (!kvargs_count) {
1248                 rte_kvargs_free(kvlist);
1249                 return 0;
1250         }
1251
1252         if (kvargs_count > 1)
1253                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1254                             "the first invalid or last valid one is used !",
1255                             ETH_I40E_USE_LATEST_VEC);
1256
1257         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1258                                 i40e_parse_latest_vec_handler, ad) < 0) {
1259                 rte_kvargs_free(kvlist);
1260                 return -EINVAL;
1261         }
1262
1263         rte_kvargs_free(kvlist);
1264         return 0;
1265 }
1266
1267 #define I40E_ALARM_INTERVAL 50000 /* us */
1268
1269 static int
1270 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1271 {
1272         struct rte_pci_device *pci_dev;
1273         struct rte_intr_handle *intr_handle;
1274         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1275         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1276         struct i40e_vsi *vsi;
1277         int ret;
1278         uint32_t len, val;
1279         uint8_t aq_fail = 0;
1280
1281         PMD_INIT_FUNC_TRACE();
1282
1283         dev->dev_ops = &i40e_eth_dev_ops;
1284         dev->rx_pkt_burst = i40e_recv_pkts;
1285         dev->tx_pkt_burst = i40e_xmit_pkts;
1286         dev->tx_pkt_prepare = i40e_prep_pkts;
1287
1288         /* for secondary processes, we don't initialise any further as primary
1289          * has already done this work. Only check we don't need a different
1290          * RX function */
1291         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1292                 i40e_set_rx_function(dev);
1293                 i40e_set_tx_function(dev);
1294                 return 0;
1295         }
1296         i40e_set_default_ptype_table(dev);
1297         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1298         intr_handle = &pci_dev->intr_handle;
1299
1300         rte_eth_copy_pci_info(dev, pci_dev);
1301
1302         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1303         pf->adapter->eth_dev = dev;
1304         pf->dev_data = dev->data;
1305
1306         hw->back = I40E_PF_TO_ADAPTER(pf);
1307         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1308         if (!hw->hw_addr) {
1309                 PMD_INIT_LOG(ERR,
1310                         "Hardware is not available, as address is NULL");
1311                 return -ENODEV;
1312         }
1313
1314         hw->vendor_id = pci_dev->id.vendor_id;
1315         hw->device_id = pci_dev->id.device_id;
1316         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1317         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1318         hw->bus.device = pci_dev->addr.devid;
1319         hw->bus.func = pci_dev->addr.function;
1320         hw->adapter_stopped = 0;
1321         hw->adapter_closed = 0;
1322
1323         /*
1324          * Switch Tag value should not be identical to either the First Tag
1325          * or Second Tag values. So set something other than common Ethertype
1326          * for internal switching.
1327          */
1328         hw->switch_tag = 0xffff;
1329
1330         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1331         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1332                 PMD_INIT_LOG(ERR, "\nERROR: "
1333                         "Firmware recovery mode detected. Limiting functionality.\n"
1334                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1335                         "User Guide for details on firmware recovery mode.");
1336                 return -EIO;
1337         }
1338
1339         /* Check if need to support multi-driver */
1340         i40e_support_multi_driver(dev);
1341         /* Check if users want the latest supported vec path */
1342         i40e_use_latest_vec(dev);
1343
1344         /* Make sure all is clean before doing PF reset */
1345         i40e_clear_hw(hw);
1346
1347         /* Reset here to make sure all is clean for each PF */
1348         ret = i40e_pf_reset(hw);
1349         if (ret) {
1350                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1351                 return ret;
1352         }
1353
1354         /* Initialize the shared code (base driver) */
1355         ret = i40e_init_shared_code(hw);
1356         if (ret) {
1357                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1358                 return ret;
1359         }
1360
1361         /* Initialize the parameters for adminq */
1362         i40e_init_adminq_parameter(hw);
1363         ret = i40e_init_adminq(hw);
1364         if (ret != I40E_SUCCESS) {
1365                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1366                 return -EIO;
1367         }
1368         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1369                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1370                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1371                      ((hw->nvm.version >> 12) & 0xf),
1372                      ((hw->nvm.version >> 4) & 0xff),
1373                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1374
1375         /* Initialize the hardware */
1376         i40e_hw_init(dev);
1377
1378         i40e_config_automask(pf);
1379
1380         i40e_set_default_pctype_table(dev);
1381
1382         /*
1383          * To work around the NVM issue, initialize registers
1384          * for packet type of QinQ by software.
1385          * It should be removed once issues are fixed in NVM.
1386          */
1387         if (!pf->support_multi_driver)
1388                 i40e_GLQF_reg_init(hw);
1389
1390         /* Initialize the input set for filters (hash and fd) to default value */
1391         i40e_filter_input_set_init(pf);
1392
1393         /* initialise the L3_MAP register */
1394         if (!pf->support_multi_driver) {
1395                 ret = i40e_aq_debug_write_global_register(hw,
1396                                                    I40E_GLQF_L3_MAP(40),
1397                                                    0x00000028,  NULL);
1398                 if (ret)
1399                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1400                                      ret);
1401                 PMD_INIT_LOG(DEBUG,
1402                              "Global register 0x%08x is changed with 0x28",
1403                              I40E_GLQF_L3_MAP(40));
1404         }
1405
1406         /* Need the special FW version to support floating VEB */
1407         config_floating_veb(dev);
1408         /* Clear PXE mode */
1409         i40e_clear_pxe_mode(hw);
1410         i40e_dev_sync_phy_type(hw);
1411
1412         /*
1413          * On X710, performance number is far from the expectation on recent
1414          * firmware versions. The fix for this issue may not be integrated in
1415          * the following firmware version. So the workaround in software driver
1416          * is needed. It needs to modify the initial values of 3 internal only
1417          * registers. Note that the workaround can be removed when it is fixed
1418          * in firmware in the future.
1419          */
1420         i40e_configure_registers(hw);
1421
1422         /* Get hw capabilities */
1423         ret = i40e_get_cap(hw);
1424         if (ret != I40E_SUCCESS) {
1425                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1426                 goto err_get_capabilities;
1427         }
1428
1429         /* Initialize parameters for PF */
1430         ret = i40e_pf_parameter_init(dev);
1431         if (ret != 0) {
1432                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1433                 goto err_parameter_init;
1434         }
1435
1436         /* Initialize the queue management */
1437         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1438         if (ret < 0) {
1439                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1440                 goto err_qp_pool_init;
1441         }
1442         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1443                                 hw->func_caps.num_msix_vectors - 1);
1444         if (ret < 0) {
1445                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1446                 goto err_msix_pool_init;
1447         }
1448
1449         /* Initialize lan hmc */
1450         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1451                                 hw->func_caps.num_rx_qp, 0, 0);
1452         if (ret != I40E_SUCCESS) {
1453                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1454                 goto err_init_lan_hmc;
1455         }
1456
1457         /* Configure lan hmc */
1458         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1459         if (ret != I40E_SUCCESS) {
1460                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1461                 goto err_configure_lan_hmc;
1462         }
1463
1464         /* Get and check the mac address */
1465         i40e_get_mac_addr(hw, hw->mac.addr);
1466         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1467                 PMD_INIT_LOG(ERR, "mac address is not valid");
1468                 ret = -EIO;
1469                 goto err_get_mac_addr;
1470         }
1471         /* Copy the permanent MAC address */
1472         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1473                         (struct rte_ether_addr *)hw->mac.perm_addr);
1474
1475         /* Disable flow control */
1476         hw->fc.requested_mode = I40E_FC_NONE;
1477         i40e_set_fc(hw, &aq_fail, TRUE);
1478
1479         /* Set the global registers with default ether type value */
1480         if (!pf->support_multi_driver) {
1481                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1482                                          RTE_ETHER_TYPE_VLAN);
1483                 if (ret != I40E_SUCCESS) {
1484                         PMD_INIT_LOG(ERR,
1485                                      "Failed to set the default outer "
1486                                      "VLAN ether type");
1487                         goto err_setup_pf_switch;
1488                 }
1489         }
1490
1491         /* PF setup, which includes VSI setup */
1492         ret = i40e_pf_setup(pf);
1493         if (ret) {
1494                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1495                 goto err_setup_pf_switch;
1496         }
1497
1498         vsi = pf->main_vsi;
1499
1500         /* Disable double vlan by default */
1501         i40e_vsi_config_double_vlan(vsi, FALSE);
1502
1503         /* Disable S-TAG identification when floating_veb is disabled */
1504         if (!pf->floating_veb) {
1505                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1506                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1507                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1508                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1509                 }
1510         }
1511
1512         if (!vsi->max_macaddrs)
1513                 len = RTE_ETHER_ADDR_LEN;
1514         else
1515                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1516
1517         /* Should be after VSI initialized */
1518         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1519         if (!dev->data->mac_addrs) {
1520                 PMD_INIT_LOG(ERR,
1521                         "Failed to allocated memory for storing mac address");
1522                 goto err_mac_alloc;
1523         }
1524         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1525                                         &dev->data->mac_addrs[0]);
1526
1527         /* Init dcb to sw mode by default */
1528         ret = i40e_dcb_init_configure(dev, TRUE);
1529         if (ret != I40E_SUCCESS) {
1530                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1531                 pf->flags &= ~I40E_FLAG_DCB;
1532         }
1533         /* Update HW struct after DCB configuration */
1534         i40e_get_cap(hw);
1535
1536         /* initialize pf host driver to setup SRIOV resource if applicable */
1537         i40e_pf_host_init(dev);
1538
1539         /* register callback func to eal lib */
1540         rte_intr_callback_register(intr_handle,
1541                                    i40e_dev_interrupt_handler, dev);
1542
1543         /* configure and enable device interrupt */
1544         i40e_pf_config_irq0(hw, TRUE);
1545         i40e_pf_enable_irq0(hw);
1546
1547         /* enable uio intr after callback register */
1548         rte_intr_enable(intr_handle);
1549
1550         /* By default disable flexible payload in global configuration */
1551         if (!pf->support_multi_driver)
1552                 i40e_flex_payload_reg_set_default(hw);
1553
1554         /*
1555          * Add an ethertype filter to drop all flow control frames transmitted
1556          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1557          * frames to wire.
1558          */
1559         i40e_add_tx_flow_control_drop_filter(pf);
1560
1561         /* Set the max frame size to 0x2600 by default,
1562          * in case other drivers changed the default value.
1563          */
1564         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1565
1566         /* initialize mirror rule list */
1567         TAILQ_INIT(&pf->mirror_list);
1568
1569         /* initialize Traffic Manager configuration */
1570         i40e_tm_conf_init(dev);
1571
1572         /* Initialize customized information */
1573         i40e_init_customized_info(pf);
1574
1575         ret = i40e_init_ethtype_filter_list(dev);
1576         if (ret < 0)
1577                 goto err_init_ethtype_filter_list;
1578         ret = i40e_init_tunnel_filter_list(dev);
1579         if (ret < 0)
1580                 goto err_init_tunnel_filter_list;
1581         ret = i40e_init_fdir_filter_list(dev);
1582         if (ret < 0)
1583                 goto err_init_fdir_filter_list;
1584
1585         /* initialize queue region configuration */
1586         i40e_init_queue_region_conf(dev);
1587
1588         /* initialize rss configuration from rte_flow */
1589         memset(&pf->rss_info, 0,
1590                 sizeof(struct i40e_rte_flow_rss_conf));
1591
1592         /* reset all stats of the device, including pf and main vsi */
1593         i40e_dev_stats_reset(dev);
1594
1595         return 0;
1596
1597 err_init_fdir_filter_list:
1598         rte_free(pf->tunnel.hash_table);
1599         rte_free(pf->tunnel.hash_map);
1600 err_init_tunnel_filter_list:
1601         rte_free(pf->ethertype.hash_table);
1602         rte_free(pf->ethertype.hash_map);
1603 err_init_ethtype_filter_list:
1604         rte_free(dev->data->mac_addrs);
1605 err_mac_alloc:
1606         i40e_vsi_release(pf->main_vsi);
1607 err_setup_pf_switch:
1608 err_get_mac_addr:
1609 err_configure_lan_hmc:
1610         (void)i40e_shutdown_lan_hmc(hw);
1611 err_init_lan_hmc:
1612         i40e_res_pool_destroy(&pf->msix_pool);
1613 err_msix_pool_init:
1614         i40e_res_pool_destroy(&pf->qp_pool);
1615 err_qp_pool_init:
1616 err_parameter_init:
1617 err_get_capabilities:
1618         (void)i40e_shutdown_adminq(hw);
1619
1620         return ret;
1621 }
1622
1623 static void
1624 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1625 {
1626         struct i40e_ethertype_filter *p_ethertype;
1627         struct i40e_ethertype_rule *ethertype_rule;
1628
1629         ethertype_rule = &pf->ethertype;
1630         /* Remove all ethertype filter rules and hash */
1631         if (ethertype_rule->hash_map)
1632                 rte_free(ethertype_rule->hash_map);
1633         if (ethertype_rule->hash_table)
1634                 rte_hash_free(ethertype_rule->hash_table);
1635
1636         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1637                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1638                              p_ethertype, rules);
1639                 rte_free(p_ethertype);
1640         }
1641 }
1642
1643 static void
1644 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1645 {
1646         struct i40e_tunnel_filter *p_tunnel;
1647         struct i40e_tunnel_rule *tunnel_rule;
1648
1649         tunnel_rule = &pf->tunnel;
1650         /* Remove all tunnel director rules and hash */
1651         if (tunnel_rule->hash_map)
1652                 rte_free(tunnel_rule->hash_map);
1653         if (tunnel_rule->hash_table)
1654                 rte_hash_free(tunnel_rule->hash_table);
1655
1656         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1657                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1658                 rte_free(p_tunnel);
1659         }
1660 }
1661
1662 static void
1663 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1664 {
1665         struct i40e_fdir_filter *p_fdir;
1666         struct i40e_fdir_info *fdir_info;
1667
1668         fdir_info = &pf->fdir;
1669         /* Remove all flow director rules and hash */
1670         if (fdir_info->hash_map)
1671                 rte_free(fdir_info->hash_map);
1672         if (fdir_info->hash_table)
1673                 rte_hash_free(fdir_info->hash_table);
1674
1675         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1676                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1677                 rte_free(p_fdir);
1678         }
1679 }
1680
1681 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1682 {
1683         /*
1684          * Disable by default flexible payload
1685          * for corresponding L2/L3/L4 layers.
1686          */
1687         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1688         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1689         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1690 }
1691
1692 static int
1693 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1694 {
1695         struct i40e_pf *pf;
1696         struct rte_pci_device *pci_dev;
1697         struct rte_intr_handle *intr_handle;
1698         struct i40e_hw *hw;
1699         struct i40e_filter_control_settings settings;
1700         struct rte_flow *p_flow;
1701         int ret;
1702         uint8_t aq_fail = 0;
1703         int retries = 0;
1704
1705         PMD_INIT_FUNC_TRACE();
1706
1707         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1708                 return 0;
1709
1710         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1711         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1712         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1713         intr_handle = &pci_dev->intr_handle;
1714
1715         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1716         if (ret)
1717                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1718
1719         if (hw->adapter_closed == 0)
1720                 i40e_dev_close(dev);
1721
1722         dev->dev_ops = NULL;
1723         dev->rx_pkt_burst = NULL;
1724         dev->tx_pkt_burst = NULL;
1725
1726         /* Clear PXE mode */
1727         i40e_clear_pxe_mode(hw);
1728
1729         /* Unconfigure filter control */
1730         memset(&settings, 0, sizeof(settings));
1731         ret = i40e_set_filter_control(hw, &settings);
1732         if (ret)
1733                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1734                                         ret);
1735
1736         /* Disable flow control */
1737         hw->fc.requested_mode = I40E_FC_NONE;
1738         i40e_set_fc(hw, &aq_fail, TRUE);
1739
1740         /* uninitialize pf host driver */
1741         i40e_pf_host_uninit(dev);
1742
1743         /* disable uio intr before callback unregister */
1744         rte_intr_disable(intr_handle);
1745
1746         /* unregister callback func to eal lib */
1747         do {
1748                 ret = rte_intr_callback_unregister(intr_handle,
1749                                 i40e_dev_interrupt_handler, dev);
1750                 if (ret >= 0) {
1751                         break;
1752                 } else if (ret != -EAGAIN) {
1753                         PMD_INIT_LOG(ERR,
1754                                  "intr callback unregister failed: %d",
1755                                  ret);
1756                         return ret;
1757                 }
1758                 i40e_msec_delay(500);
1759         } while (retries++ < 5);
1760
1761         i40e_rm_ethtype_filter_list(pf);
1762         i40e_rm_tunnel_filter_list(pf);
1763         i40e_rm_fdir_filter_list(pf);
1764
1765         /* Remove all flows */
1766         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1767                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1768                 rte_free(p_flow);
1769         }
1770
1771         /* Remove all Traffic Manager configuration */
1772         i40e_tm_conf_uninit(dev);
1773
1774         return 0;
1775 }
1776
1777 static int
1778 i40e_dev_configure(struct rte_eth_dev *dev)
1779 {
1780         struct i40e_adapter *ad =
1781                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1782         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1783         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1784         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1785         int i, ret;
1786
1787         ret = i40e_dev_sync_phy_type(hw);
1788         if (ret)
1789                 return ret;
1790
1791         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1792          * bulk allocation or vector Rx preconditions we will reset it.
1793          */
1794         ad->rx_bulk_alloc_allowed = true;
1795         ad->rx_vec_allowed = true;
1796         ad->tx_simple_allowed = true;
1797         ad->tx_vec_allowed = true;
1798
1799         /* Only legacy filter API needs the following fdir config. So when the
1800          * legacy filter API is deprecated, the following codes should also be
1801          * removed.
1802          */
1803         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1804                 ret = i40e_fdir_setup(pf);
1805                 if (ret != I40E_SUCCESS) {
1806                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1807                         return -ENOTSUP;
1808                 }
1809                 ret = i40e_fdir_configure(dev);
1810                 if (ret < 0) {
1811                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1812                         goto err;
1813                 }
1814         } else
1815                 i40e_fdir_teardown(pf);
1816
1817         ret = i40e_dev_init_vlan(dev);
1818         if (ret < 0)
1819                 goto err;
1820
1821         /* VMDQ setup.
1822          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1823          *  RSS setting have different requirements.
1824          *  General PMD driver call sequence are NIC init, configure,
1825          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1826          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1827          *  applicable. So, VMDQ setting has to be done before
1828          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1829          *  For RSS setting, it will try to calculate actual configured RX queue
1830          *  number, which will be available after rx_queue_setup(). dev_start()
1831          *  function is good to place RSS setup.
1832          */
1833         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1834                 ret = i40e_vmdq_setup(dev);
1835                 if (ret)
1836                         goto err;
1837         }
1838
1839         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1840                 ret = i40e_dcb_setup(dev);
1841                 if (ret) {
1842                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1843                         goto err_dcb;
1844                 }
1845         }
1846
1847         TAILQ_INIT(&pf->flow_list);
1848
1849         return 0;
1850
1851 err_dcb:
1852         /* need to release vmdq resource if exists */
1853         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1854                 i40e_vsi_release(pf->vmdq[i].vsi);
1855                 pf->vmdq[i].vsi = NULL;
1856         }
1857         rte_free(pf->vmdq);
1858         pf->vmdq = NULL;
1859 err:
1860         /* Need to release fdir resource if exists.
1861          * Only legacy filter API needs the following fdir config. So when the
1862          * legacy filter API is deprecated, the following code should also be
1863          * removed.
1864          */
1865         i40e_fdir_teardown(pf);
1866         return ret;
1867 }
1868
1869 void
1870 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1871 {
1872         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1873         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1874         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1875         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1876         uint16_t msix_vect = vsi->msix_intr;
1877         uint16_t i;
1878
1879         for (i = 0; i < vsi->nb_qps; i++) {
1880                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1881                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1882                 rte_wmb();
1883         }
1884
1885         if (vsi->type != I40E_VSI_SRIOV) {
1886                 if (!rte_intr_allow_others(intr_handle)) {
1887                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1888                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1889                         I40E_WRITE_REG(hw,
1890                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1891                                        0);
1892                 } else {
1893                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1894                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1895                         I40E_WRITE_REG(hw,
1896                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1897                                                        msix_vect - 1), 0);
1898                 }
1899         } else {
1900                 uint32_t reg;
1901                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1902                         vsi->user_param + (msix_vect - 1);
1903
1904                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1905                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1906         }
1907         I40E_WRITE_FLUSH(hw);
1908 }
1909
1910 static void
1911 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1912                        int base_queue, int nb_queue,
1913                        uint16_t itr_idx)
1914 {
1915         int i;
1916         uint32_t val;
1917         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1918         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1919
1920         /* Bind all RX queues to allocated MSIX interrupt */
1921         for (i = 0; i < nb_queue; i++) {
1922                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1923                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1924                         ((base_queue + i + 1) <<
1925                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1926                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1927                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1928
1929                 if (i == nb_queue - 1)
1930                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1931                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1932         }
1933
1934         /* Write first RX queue to Link list register as the head element */
1935         if (vsi->type != I40E_VSI_SRIOV) {
1936                 uint16_t interval =
1937                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1938
1939                 if (msix_vect == I40E_MISC_VEC_ID) {
1940                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1941                                        (base_queue <<
1942                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1943                                        (0x0 <<
1944                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1945                         I40E_WRITE_REG(hw,
1946                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1947                                        interval);
1948                 } else {
1949                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1950                                        (base_queue <<
1951                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1952                                        (0x0 <<
1953                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1954                         I40E_WRITE_REG(hw,
1955                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1956                                                        msix_vect - 1),
1957                                        interval);
1958                 }
1959         } else {
1960                 uint32_t reg;
1961
1962                 if (msix_vect == I40E_MISC_VEC_ID) {
1963                         I40E_WRITE_REG(hw,
1964                                        I40E_VPINT_LNKLST0(vsi->user_param),
1965                                        (base_queue <<
1966                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1967                                        (0x0 <<
1968                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1969                 } else {
1970                         /* num_msix_vectors_vf needs to minus irq0 */
1971                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1972                                 vsi->user_param + (msix_vect - 1);
1973
1974                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1975                                        (base_queue <<
1976                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1977                                        (0x0 <<
1978                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1979                 }
1980         }
1981
1982         I40E_WRITE_FLUSH(hw);
1983 }
1984
1985 void
1986 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1987 {
1988         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1989         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1990         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1991         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1992         uint16_t msix_vect = vsi->msix_intr;
1993         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1994         uint16_t queue_idx = 0;
1995         int record = 0;
1996         int i;
1997
1998         for (i = 0; i < vsi->nb_qps; i++) {
1999                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2000                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2001         }
2002
2003         /* VF bind interrupt */
2004         if (vsi->type == I40E_VSI_SRIOV) {
2005                 __vsi_queues_bind_intr(vsi, msix_vect,
2006                                        vsi->base_queue, vsi->nb_qps,
2007                                        itr_idx);
2008                 return;
2009         }
2010
2011         /* PF & VMDq bind interrupt */
2012         if (rte_intr_dp_is_en(intr_handle)) {
2013                 if (vsi->type == I40E_VSI_MAIN) {
2014                         queue_idx = 0;
2015                         record = 1;
2016                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2017                         struct i40e_vsi *main_vsi =
2018                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2019                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2020                         record = 1;
2021                 }
2022         }
2023
2024         for (i = 0; i < vsi->nb_used_qps; i++) {
2025                 if (nb_msix <= 1) {
2026                         if (!rte_intr_allow_others(intr_handle))
2027                                 /* allow to share MISC_VEC_ID */
2028                                 msix_vect = I40E_MISC_VEC_ID;
2029
2030                         /* no enough msix_vect, map all to one */
2031                         __vsi_queues_bind_intr(vsi, msix_vect,
2032                                                vsi->base_queue + i,
2033                                                vsi->nb_used_qps - i,
2034                                                itr_idx);
2035                         for (; !!record && i < vsi->nb_used_qps; i++)
2036                                 intr_handle->intr_vec[queue_idx + i] =
2037                                         msix_vect;
2038                         break;
2039                 }
2040                 /* 1:1 queue/msix_vect mapping */
2041                 __vsi_queues_bind_intr(vsi, msix_vect,
2042                                        vsi->base_queue + i, 1,
2043                                        itr_idx);
2044                 if (!!record)
2045                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2046
2047                 msix_vect++;
2048                 nb_msix--;
2049         }
2050 }
2051
2052 static void
2053 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2054 {
2055         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2056         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2057         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2058         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2059         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2060         uint16_t msix_intr, i;
2061
2062         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2063                 for (i = 0; i < vsi->nb_msix; i++) {
2064                         msix_intr = vsi->msix_intr + i;
2065                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2066                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2067                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2068                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2069                 }
2070         else
2071                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2072                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2073                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2074                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2075
2076         I40E_WRITE_FLUSH(hw);
2077 }
2078
2079 static void
2080 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2081 {
2082         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2083         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2084         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2085         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2086         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2087         uint16_t msix_intr, i;
2088
2089         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2090                 for (i = 0; i < vsi->nb_msix; i++) {
2091                         msix_intr = vsi->msix_intr + i;
2092                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2093                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2094                 }
2095         else
2096                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2097                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2098
2099         I40E_WRITE_FLUSH(hw);
2100 }
2101
2102 static inline uint8_t
2103 i40e_parse_link_speeds(uint16_t link_speeds)
2104 {
2105         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2106
2107         if (link_speeds & ETH_LINK_SPEED_40G)
2108                 link_speed |= I40E_LINK_SPEED_40GB;
2109         if (link_speeds & ETH_LINK_SPEED_25G)
2110                 link_speed |= I40E_LINK_SPEED_25GB;
2111         if (link_speeds & ETH_LINK_SPEED_20G)
2112                 link_speed |= I40E_LINK_SPEED_20GB;
2113         if (link_speeds & ETH_LINK_SPEED_10G)
2114                 link_speed |= I40E_LINK_SPEED_10GB;
2115         if (link_speeds & ETH_LINK_SPEED_1G)
2116                 link_speed |= I40E_LINK_SPEED_1GB;
2117         if (link_speeds & ETH_LINK_SPEED_100M)
2118                 link_speed |= I40E_LINK_SPEED_100MB;
2119
2120         return link_speed;
2121 }
2122
2123 static int
2124 i40e_phy_conf_link(struct i40e_hw *hw,
2125                    uint8_t abilities,
2126                    uint8_t force_speed,
2127                    bool is_up)
2128 {
2129         enum i40e_status_code status;
2130         struct i40e_aq_get_phy_abilities_resp phy_ab;
2131         struct i40e_aq_set_phy_config phy_conf;
2132         enum i40e_aq_phy_type cnt;
2133         uint8_t avail_speed;
2134         uint32_t phy_type_mask = 0;
2135
2136         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2137                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2138                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2139                         I40E_AQ_PHY_FLAG_LOW_POWER;
2140         int ret = -ENOTSUP;
2141
2142         /* To get phy capabilities of available speeds. */
2143         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2144                                               NULL);
2145         if (status) {
2146                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2147                                 status);
2148                 return ret;
2149         }
2150         avail_speed = phy_ab.link_speed;
2151
2152         /* To get the current phy config. */
2153         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2154                                               NULL);
2155         if (status) {
2156                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2157                                 status);
2158                 return ret;
2159         }
2160
2161         /* If link needs to go up and it is in autoneg mode the speed is OK,
2162          * no need to set up again.
2163          */
2164         if (is_up && phy_ab.phy_type != 0 &&
2165                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2166                      phy_ab.link_speed != 0)
2167                 return I40E_SUCCESS;
2168
2169         memset(&phy_conf, 0, sizeof(phy_conf));
2170
2171         /* bits 0-2 use the values from get_phy_abilities_resp */
2172         abilities &= ~mask;
2173         abilities |= phy_ab.abilities & mask;
2174
2175         phy_conf.abilities = abilities;
2176
2177         /* If link needs to go up, but the force speed is not supported,
2178          * Warn users and config the default available speeds.
2179          */
2180         if (is_up && !(force_speed & avail_speed)) {
2181                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2182                 phy_conf.link_speed = avail_speed;
2183         } else {
2184                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2185         }
2186
2187         /* PHY type mask needs to include each type except PHY type extension */
2188         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2189                 phy_type_mask |= 1 << cnt;
2190
2191         /* use get_phy_abilities_resp value for the rest */
2192         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2193         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2194                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2195                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2196         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2197         phy_conf.eee_capability = phy_ab.eee_capability;
2198         phy_conf.eeer = phy_ab.eeer_val;
2199         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2200
2201         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2202                     phy_ab.abilities, phy_ab.link_speed);
2203         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2204                     phy_conf.abilities, phy_conf.link_speed);
2205
2206         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2207         if (status)
2208                 return ret;
2209
2210         return I40E_SUCCESS;
2211 }
2212
2213 static int
2214 i40e_apply_link_speed(struct rte_eth_dev *dev)
2215 {
2216         uint8_t speed;
2217         uint8_t abilities = 0;
2218         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2219         struct rte_eth_conf *conf = &dev->data->dev_conf;
2220
2221         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2222                 conf->link_speeds = ETH_LINK_SPEED_40G |
2223                                     ETH_LINK_SPEED_25G |
2224                                     ETH_LINK_SPEED_20G |
2225                                     ETH_LINK_SPEED_10G |
2226                                     ETH_LINK_SPEED_1G |
2227                                     ETH_LINK_SPEED_100M;
2228         }
2229         speed = i40e_parse_link_speeds(conf->link_speeds);
2230         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2231                      I40E_AQ_PHY_AN_ENABLED |
2232                      I40E_AQ_PHY_LINK_ENABLED;
2233
2234         return i40e_phy_conf_link(hw, abilities, speed, true);
2235 }
2236
2237 static int
2238 i40e_dev_start(struct rte_eth_dev *dev)
2239 {
2240         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2241         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2242         struct i40e_vsi *main_vsi = pf->main_vsi;
2243         int ret, i;
2244         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2245         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2246         uint32_t intr_vector = 0;
2247         struct i40e_vsi *vsi;
2248
2249         hw->adapter_stopped = 0;
2250
2251         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2252                 PMD_INIT_LOG(ERR,
2253                 "Invalid link_speeds for port %u, autonegotiation disabled",
2254                               dev->data->port_id);
2255                 return -EINVAL;
2256         }
2257
2258         rte_intr_disable(intr_handle);
2259
2260         if ((rte_intr_cap_multiple(intr_handle) ||
2261              !RTE_ETH_DEV_SRIOV(dev).active) &&
2262             dev->data->dev_conf.intr_conf.rxq != 0) {
2263                 intr_vector = dev->data->nb_rx_queues;
2264                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2265                 if (ret)
2266                         return ret;
2267         }
2268
2269         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2270                 intr_handle->intr_vec =
2271                         rte_zmalloc("intr_vec",
2272                                     dev->data->nb_rx_queues * sizeof(int),
2273                                     0);
2274                 if (!intr_handle->intr_vec) {
2275                         PMD_INIT_LOG(ERR,
2276                                 "Failed to allocate %d rx_queues intr_vec",
2277                                 dev->data->nb_rx_queues);
2278                         return -ENOMEM;
2279                 }
2280         }
2281
2282         /* Initialize VSI */
2283         ret = i40e_dev_rxtx_init(pf);
2284         if (ret != I40E_SUCCESS) {
2285                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2286                 goto err_up;
2287         }
2288
2289         /* Map queues with MSIX interrupt */
2290         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2291                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2292         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2293         i40e_vsi_enable_queues_intr(main_vsi);
2294
2295         /* Map VMDQ VSI queues with MSIX interrupt */
2296         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2297                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2298                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2299                                           I40E_ITR_INDEX_DEFAULT);
2300                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2301         }
2302
2303         /* enable FDIR MSIX interrupt */
2304         if (pf->fdir.fdir_vsi) {
2305                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2306                                           I40E_ITR_INDEX_NONE);
2307                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2308         }
2309
2310         /* Enable all queues which have been configured */
2311         ret = i40e_dev_switch_queues(pf, TRUE);
2312         if (ret != I40E_SUCCESS) {
2313                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2314                 goto err_up;
2315         }
2316
2317         /* Enable receiving broadcast packets */
2318         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2319         if (ret != I40E_SUCCESS)
2320                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2321
2322         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2323                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2324                                                 true, NULL);
2325                 if (ret != I40E_SUCCESS)
2326                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2327         }
2328
2329         /* Enable the VLAN promiscuous mode. */
2330         if (pf->vfs) {
2331                 for (i = 0; i < pf->vf_num; i++) {
2332                         vsi = pf->vfs[i].vsi;
2333                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2334                                                      true, NULL);
2335                 }
2336         }
2337
2338         /* Enable mac loopback mode */
2339         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2340             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2341                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2342                 if (ret != I40E_SUCCESS) {
2343                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2344                         goto err_up;
2345                 }
2346         }
2347
2348         /* Apply link configure */
2349         ret = i40e_apply_link_speed(dev);
2350         if (I40E_SUCCESS != ret) {
2351                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2352                 goto err_up;
2353         }
2354
2355         if (!rte_intr_allow_others(intr_handle)) {
2356                 rte_intr_callback_unregister(intr_handle,
2357                                              i40e_dev_interrupt_handler,
2358                                              (void *)dev);
2359                 /* configure and enable device interrupt */
2360                 i40e_pf_config_irq0(hw, FALSE);
2361                 i40e_pf_enable_irq0(hw);
2362
2363                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2364                         PMD_INIT_LOG(INFO,
2365                                 "lsc won't enable because of no intr multiplex");
2366         } else {
2367                 ret = i40e_aq_set_phy_int_mask(hw,
2368                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2369                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2370                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2371                 if (ret != I40E_SUCCESS)
2372                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2373
2374                 /* Call get_link_info aq commond to enable/disable LSE */
2375                 i40e_dev_link_update(dev, 0);
2376         }
2377
2378         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2379                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2380                                   i40e_dev_alarm_handler, dev);
2381         } else {
2382                 /* enable uio intr after callback register */
2383                 rte_intr_enable(intr_handle);
2384         }
2385
2386         i40e_filter_restore(pf);
2387
2388         if (pf->tm_conf.root && !pf->tm_conf.committed)
2389                 PMD_DRV_LOG(WARNING,
2390                             "please call hierarchy_commit() "
2391                             "before starting the port");
2392
2393         return I40E_SUCCESS;
2394
2395 err_up:
2396         i40e_dev_switch_queues(pf, FALSE);
2397         i40e_dev_clear_queues(dev);
2398
2399         return ret;
2400 }
2401
2402 static void
2403 i40e_dev_stop(struct rte_eth_dev *dev)
2404 {
2405         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2406         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2407         struct i40e_vsi *main_vsi = pf->main_vsi;
2408         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2409         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2410         int i;
2411
2412         if (hw->adapter_stopped == 1)
2413                 return;
2414
2415         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2416                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2417                 rte_intr_enable(intr_handle);
2418         }
2419
2420         /* Disable all queues */
2421         i40e_dev_switch_queues(pf, FALSE);
2422
2423         /* un-map queues with interrupt registers */
2424         i40e_vsi_disable_queues_intr(main_vsi);
2425         i40e_vsi_queues_unbind_intr(main_vsi);
2426
2427         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2428                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2429                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2430         }
2431
2432         if (pf->fdir.fdir_vsi) {
2433                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2434                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2435         }
2436         /* Clear all queues and release memory */
2437         i40e_dev_clear_queues(dev);
2438
2439         /* Set link down */
2440         i40e_dev_set_link_down(dev);
2441
2442         if (!rte_intr_allow_others(intr_handle))
2443                 /* resume to the default handler */
2444                 rte_intr_callback_register(intr_handle,
2445                                            i40e_dev_interrupt_handler,
2446                                            (void *)dev);
2447
2448         /* Clean datapath event and queue/vec mapping */
2449         rte_intr_efd_disable(intr_handle);
2450         if (intr_handle->intr_vec) {
2451                 rte_free(intr_handle->intr_vec);
2452                 intr_handle->intr_vec = NULL;
2453         }
2454
2455         /* reset hierarchy commit */
2456         pf->tm_conf.committed = false;
2457
2458         hw->adapter_stopped = 1;
2459
2460         pf->adapter->rss_reta_updated = 0;
2461 }
2462
2463 static void
2464 i40e_dev_close(struct rte_eth_dev *dev)
2465 {
2466         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2467         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2468         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2469         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2470         struct i40e_mirror_rule *p_mirror;
2471         uint32_t reg;
2472         int i;
2473         int ret;
2474
2475         PMD_INIT_FUNC_TRACE();
2476
2477         i40e_dev_stop(dev);
2478
2479         /* Remove all mirror rules */
2480         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2481                 ret = i40e_aq_del_mirror_rule(hw,
2482                                               pf->main_vsi->veb->seid,
2483                                               p_mirror->rule_type,
2484                                               p_mirror->entries,
2485                                               p_mirror->num_entries,
2486                                               p_mirror->id);
2487                 if (ret < 0)
2488                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2489                                     "status = %d, aq_err = %d.", ret,
2490                                     hw->aq.asq_last_status);
2491
2492                 /* remove mirror software resource anyway */
2493                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2494                 rte_free(p_mirror);
2495                 pf->nb_mirror_rule--;
2496         }
2497
2498         i40e_dev_free_queues(dev);
2499
2500         /* Disable interrupt */
2501         i40e_pf_disable_irq0(hw);
2502         rte_intr_disable(intr_handle);
2503
2504         /*
2505          * Only legacy filter API needs the following fdir config. So when the
2506          * legacy filter API is deprecated, the following code should also be
2507          * removed.
2508          */
2509         i40e_fdir_teardown(pf);
2510
2511         /* shutdown and destroy the HMC */
2512         i40e_shutdown_lan_hmc(hw);
2513
2514         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2515                 i40e_vsi_release(pf->vmdq[i].vsi);
2516                 pf->vmdq[i].vsi = NULL;
2517         }
2518         rte_free(pf->vmdq);
2519         pf->vmdq = NULL;
2520
2521         /* release all the existing VSIs and VEBs */
2522         i40e_vsi_release(pf->main_vsi);
2523
2524         /* shutdown the adminq */
2525         i40e_aq_queue_shutdown(hw, true);
2526         i40e_shutdown_adminq(hw);
2527
2528         i40e_res_pool_destroy(&pf->qp_pool);
2529         i40e_res_pool_destroy(&pf->msix_pool);
2530
2531         /* Disable flexible payload in global configuration */
2532         if (!pf->support_multi_driver)
2533                 i40e_flex_payload_reg_set_default(hw);
2534
2535         /* force a PF reset to clean anything leftover */
2536         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2537         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2538                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2539         I40E_WRITE_FLUSH(hw);
2540
2541         hw->adapter_closed = 1;
2542 }
2543
2544 /*
2545  * Reset PF device only to re-initialize resources in PMD layer
2546  */
2547 static int
2548 i40e_dev_reset(struct rte_eth_dev *dev)
2549 {
2550         int ret;
2551
2552         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2553          * its VF to make them align with it. The detailed notification
2554          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2555          * To avoid unexpected behavior in VF, currently reset of PF with
2556          * SR-IOV activation is not supported. It might be supported later.
2557          */
2558         if (dev->data->sriov.active)
2559                 return -ENOTSUP;
2560
2561         ret = eth_i40e_dev_uninit(dev);
2562         if (ret)
2563                 return ret;
2564
2565         ret = eth_i40e_dev_init(dev, NULL);
2566
2567         return ret;
2568 }
2569
2570 static void
2571 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2572 {
2573         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2574         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2575         struct i40e_vsi *vsi = pf->main_vsi;
2576         int status;
2577
2578         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2579                                                      true, NULL, true);
2580         if (status != I40E_SUCCESS)
2581                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2582
2583         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2584                                                         TRUE, NULL);
2585         if (status != I40E_SUCCESS)
2586                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2587
2588 }
2589
2590 static void
2591 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2592 {
2593         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2594         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2595         struct i40e_vsi *vsi = pf->main_vsi;
2596         int status;
2597
2598         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2599                                                      false, NULL, true);
2600         if (status != I40E_SUCCESS)
2601                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2602
2603         /* must remain in all_multicast mode */
2604         if (dev->data->all_multicast == 1)
2605                 return;
2606
2607         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2608                                                         false, NULL);
2609         if (status != I40E_SUCCESS)
2610                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2611 }
2612
2613 static void
2614 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2615 {
2616         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2617         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2618         struct i40e_vsi *vsi = pf->main_vsi;
2619         int ret;
2620
2621         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2622         if (ret != I40E_SUCCESS)
2623                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2624 }
2625
2626 static void
2627 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2628 {
2629         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2630         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2631         struct i40e_vsi *vsi = pf->main_vsi;
2632         int ret;
2633
2634         if (dev->data->promiscuous == 1)
2635                 return; /* must remain in all_multicast mode */
2636
2637         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2638                                 vsi->seid, FALSE, NULL);
2639         if (ret != I40E_SUCCESS)
2640                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2641 }
2642
2643 /*
2644  * Set device link up.
2645  */
2646 static int
2647 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2648 {
2649         /* re-apply link speed setting */
2650         return i40e_apply_link_speed(dev);
2651 }
2652
2653 /*
2654  * Set device link down.
2655  */
2656 static int
2657 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2658 {
2659         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2660         uint8_t abilities = 0;
2661         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2662
2663         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2664         return i40e_phy_conf_link(hw, abilities, speed, false);
2665 }
2666
2667 static __rte_always_inline void
2668 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2669 {
2670 /* Link status registers and values*/
2671 #define I40E_PRTMAC_LINKSTA             0x001E2420
2672 #define I40E_REG_LINK_UP                0x40000080
2673 #define I40E_PRTMAC_MACC                0x001E24E0
2674 #define I40E_REG_MACC_25GB              0x00020000
2675 #define I40E_REG_SPEED_MASK             0x38000000
2676 #define I40E_REG_SPEED_0                0x00000000
2677 #define I40E_REG_SPEED_1                0x08000000
2678 #define I40E_REG_SPEED_2                0x10000000
2679 #define I40E_REG_SPEED_3                0x18000000
2680 #define I40E_REG_SPEED_4                0x20000000
2681         uint32_t link_speed;
2682         uint32_t reg_val;
2683
2684         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2685         link_speed = reg_val & I40E_REG_SPEED_MASK;
2686         reg_val &= I40E_REG_LINK_UP;
2687         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2688
2689         if (unlikely(link->link_status == 0))
2690                 return;
2691
2692         /* Parse the link status */
2693         switch (link_speed) {
2694         case I40E_REG_SPEED_0:
2695                 link->link_speed = ETH_SPEED_NUM_100M;
2696                 break;
2697         case I40E_REG_SPEED_1:
2698                 link->link_speed = ETH_SPEED_NUM_1G;
2699                 break;
2700         case I40E_REG_SPEED_2:
2701                 if (hw->mac.type == I40E_MAC_X722)
2702                         link->link_speed = ETH_SPEED_NUM_2_5G;
2703                 else
2704                         link->link_speed = ETH_SPEED_NUM_10G;
2705                 break;
2706         case I40E_REG_SPEED_3:
2707                 if (hw->mac.type == I40E_MAC_X722) {
2708                         link->link_speed = ETH_SPEED_NUM_5G;
2709                 } else {
2710                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2711
2712                         if (reg_val & I40E_REG_MACC_25GB)
2713                                 link->link_speed = ETH_SPEED_NUM_25G;
2714                         else
2715                                 link->link_speed = ETH_SPEED_NUM_40G;
2716                 }
2717                 break;
2718         case I40E_REG_SPEED_4:
2719                 if (hw->mac.type == I40E_MAC_X722)
2720                         link->link_speed = ETH_SPEED_NUM_10G;
2721                 else
2722                         link->link_speed = ETH_SPEED_NUM_20G;
2723                 break;
2724         default:
2725                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2726                 break;
2727         }
2728 }
2729
2730 static __rte_always_inline void
2731 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2732         bool enable_lse, int wait_to_complete)
2733 {
2734 #define CHECK_INTERVAL             100  /* 100ms */
2735 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2736         uint32_t rep_cnt = MAX_REPEAT_TIME;
2737         struct i40e_link_status link_status;
2738         int status;
2739
2740         memset(&link_status, 0, sizeof(link_status));
2741
2742         do {
2743                 memset(&link_status, 0, sizeof(link_status));
2744
2745                 /* Get link status information from hardware */
2746                 status = i40e_aq_get_link_info(hw, enable_lse,
2747                                                 &link_status, NULL);
2748                 if (unlikely(status != I40E_SUCCESS)) {
2749                         link->link_speed = ETH_SPEED_NUM_100M;
2750                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2751                         PMD_DRV_LOG(ERR, "Failed to get link info");
2752                         return;
2753                 }
2754
2755                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2756                 if (!wait_to_complete || link->link_status)
2757                         break;
2758
2759                 rte_delay_ms(CHECK_INTERVAL);
2760         } while (--rep_cnt);
2761
2762         /* Parse the link status */
2763         switch (link_status.link_speed) {
2764         case I40E_LINK_SPEED_100MB:
2765                 link->link_speed = ETH_SPEED_NUM_100M;
2766                 break;
2767         case I40E_LINK_SPEED_1GB:
2768                 link->link_speed = ETH_SPEED_NUM_1G;
2769                 break;
2770         case I40E_LINK_SPEED_10GB:
2771                 link->link_speed = ETH_SPEED_NUM_10G;
2772                 break;
2773         case I40E_LINK_SPEED_20GB:
2774                 link->link_speed = ETH_SPEED_NUM_20G;
2775                 break;
2776         case I40E_LINK_SPEED_25GB:
2777                 link->link_speed = ETH_SPEED_NUM_25G;
2778                 break;
2779         case I40E_LINK_SPEED_40GB:
2780                 link->link_speed = ETH_SPEED_NUM_40G;
2781                 break;
2782         default:
2783                 link->link_speed = ETH_SPEED_NUM_100M;
2784                 break;
2785         }
2786 }
2787
2788 int
2789 i40e_dev_link_update(struct rte_eth_dev *dev,
2790                      int wait_to_complete)
2791 {
2792         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2793         struct rte_eth_link link;
2794         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2795         int ret;
2796
2797         memset(&link, 0, sizeof(link));
2798
2799         /* i40e uses full duplex only */
2800         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2801         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2802                         ETH_LINK_SPEED_FIXED);
2803
2804         if (!wait_to_complete && !enable_lse)
2805                 update_link_reg(hw, &link);
2806         else
2807                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2808
2809         ret = rte_eth_linkstatus_set(dev, &link);
2810         i40e_notify_all_vfs_link_status(dev);
2811
2812         return ret;
2813 }
2814
2815 /* Get all the statistics of a VSI */
2816 void
2817 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2818 {
2819         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2820         struct i40e_eth_stats *nes = &vsi->eth_stats;
2821         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2822         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2823
2824         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2825                             vsi->offset_loaded, &oes->rx_bytes,
2826                             &nes->rx_bytes);
2827         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2828                             vsi->offset_loaded, &oes->rx_unicast,
2829                             &nes->rx_unicast);
2830         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2831                             vsi->offset_loaded, &oes->rx_multicast,
2832                             &nes->rx_multicast);
2833         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2834                             vsi->offset_loaded, &oes->rx_broadcast,
2835                             &nes->rx_broadcast);
2836         /* exclude CRC bytes */
2837         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2838                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2839
2840         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2841                             &oes->rx_discards, &nes->rx_discards);
2842         /* GLV_REPC not supported */
2843         /* GLV_RMPC not supported */
2844         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2845                             &oes->rx_unknown_protocol,
2846                             &nes->rx_unknown_protocol);
2847         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2848                             vsi->offset_loaded, &oes->tx_bytes,
2849                             &nes->tx_bytes);
2850         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2851                             vsi->offset_loaded, &oes->tx_unicast,
2852                             &nes->tx_unicast);
2853         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2854                             vsi->offset_loaded, &oes->tx_multicast,
2855                             &nes->tx_multicast);
2856         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2857                             vsi->offset_loaded,  &oes->tx_broadcast,
2858                             &nes->tx_broadcast);
2859         /* GLV_TDPC not supported */
2860         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2861                             &oes->tx_errors, &nes->tx_errors);
2862         vsi->offset_loaded = true;
2863
2864         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2865                     vsi->vsi_id);
2866         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2867         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2868         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2869         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2870         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2871         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2872                     nes->rx_unknown_protocol);
2873         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2874         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2875         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2876         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2877         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2878         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2879         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2880                     vsi->vsi_id);
2881 }
2882
2883 static void
2884 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2885 {
2886         unsigned int i;
2887         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2888         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2889
2890         /* Get rx/tx bytes of internal transfer packets */
2891         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2892                         I40E_GLV_GORCL(hw->port),
2893                         pf->offset_loaded,
2894                         &pf->internal_stats_offset.rx_bytes,
2895                         &pf->internal_stats.rx_bytes);
2896
2897         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2898                         I40E_GLV_GOTCL(hw->port),
2899                         pf->offset_loaded,
2900                         &pf->internal_stats_offset.tx_bytes,
2901                         &pf->internal_stats.tx_bytes);
2902         /* Get total internal rx packet count */
2903         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2904                             I40E_GLV_UPRCL(hw->port),
2905                             pf->offset_loaded,
2906                             &pf->internal_stats_offset.rx_unicast,
2907                             &pf->internal_stats.rx_unicast);
2908         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2909                             I40E_GLV_MPRCL(hw->port),
2910                             pf->offset_loaded,
2911                             &pf->internal_stats_offset.rx_multicast,
2912                             &pf->internal_stats.rx_multicast);
2913         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2914                             I40E_GLV_BPRCL(hw->port),
2915                             pf->offset_loaded,
2916                             &pf->internal_stats_offset.rx_broadcast,
2917                             &pf->internal_stats.rx_broadcast);
2918         /* Get total internal tx packet count */
2919         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2920                             I40E_GLV_UPTCL(hw->port),
2921                             pf->offset_loaded,
2922                             &pf->internal_stats_offset.tx_unicast,
2923                             &pf->internal_stats.tx_unicast);
2924         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2925                             I40E_GLV_MPTCL(hw->port),
2926                             pf->offset_loaded,
2927                             &pf->internal_stats_offset.tx_multicast,
2928                             &pf->internal_stats.tx_multicast);
2929         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2930                             I40E_GLV_BPTCL(hw->port),
2931                             pf->offset_loaded,
2932                             &pf->internal_stats_offset.tx_broadcast,
2933                             &pf->internal_stats.tx_broadcast);
2934
2935         /* exclude CRC size */
2936         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2937                 pf->internal_stats.rx_multicast +
2938                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
2939
2940         /* Get statistics of struct i40e_eth_stats */
2941         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2942                             I40E_GLPRT_GORCL(hw->port),
2943                             pf->offset_loaded, &os->eth.rx_bytes,
2944                             &ns->eth.rx_bytes);
2945         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2946                             I40E_GLPRT_UPRCL(hw->port),
2947                             pf->offset_loaded, &os->eth.rx_unicast,
2948                             &ns->eth.rx_unicast);
2949         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2950                             I40E_GLPRT_MPRCL(hw->port),
2951                             pf->offset_loaded, &os->eth.rx_multicast,
2952                             &ns->eth.rx_multicast);
2953         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2954                             I40E_GLPRT_BPRCL(hw->port),
2955                             pf->offset_loaded, &os->eth.rx_broadcast,
2956                             &ns->eth.rx_broadcast);
2957         /* Workaround: CRC size should not be included in byte statistics,
2958          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
2959          * packet.
2960          */
2961         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2962                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
2963
2964         /* exclude internal rx bytes
2965          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2966          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2967          * value.
2968          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2969          */
2970         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2971                 ns->eth.rx_bytes = 0;
2972         else
2973                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2974
2975         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2976                 ns->eth.rx_unicast = 0;
2977         else
2978                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2979
2980         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2981                 ns->eth.rx_multicast = 0;
2982         else
2983                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2984
2985         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2986                 ns->eth.rx_broadcast = 0;
2987         else
2988                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2989
2990         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2991                             pf->offset_loaded, &os->eth.rx_discards,
2992                             &ns->eth.rx_discards);
2993         /* GLPRT_REPC not supported */
2994         /* GLPRT_RMPC not supported */
2995         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2996                             pf->offset_loaded,
2997                             &os->eth.rx_unknown_protocol,
2998                             &ns->eth.rx_unknown_protocol);
2999         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3000                             I40E_GLPRT_GOTCL(hw->port),
3001                             pf->offset_loaded, &os->eth.tx_bytes,
3002                             &ns->eth.tx_bytes);
3003         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3004                             I40E_GLPRT_UPTCL(hw->port),
3005                             pf->offset_loaded, &os->eth.tx_unicast,
3006                             &ns->eth.tx_unicast);
3007         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3008                             I40E_GLPRT_MPTCL(hw->port),
3009                             pf->offset_loaded, &os->eth.tx_multicast,
3010                             &ns->eth.tx_multicast);
3011         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3012                             I40E_GLPRT_BPTCL(hw->port),
3013                             pf->offset_loaded, &os->eth.tx_broadcast,
3014                             &ns->eth.tx_broadcast);
3015         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3016                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3017
3018         /* exclude internal tx bytes
3019          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3020          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3021          * value.
3022          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3023          */
3024         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3025                 ns->eth.tx_bytes = 0;
3026         else
3027                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3028
3029         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3030                 ns->eth.tx_unicast = 0;
3031         else
3032                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3033
3034         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3035                 ns->eth.tx_multicast = 0;
3036         else
3037                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3038
3039         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3040                 ns->eth.tx_broadcast = 0;
3041         else
3042                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3043
3044         /* GLPRT_TEPC not supported */
3045
3046         /* additional port specific stats */
3047         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3048                             pf->offset_loaded, &os->tx_dropped_link_down,
3049                             &ns->tx_dropped_link_down);
3050         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3051                             pf->offset_loaded, &os->crc_errors,
3052                             &ns->crc_errors);
3053         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3054                             pf->offset_loaded, &os->illegal_bytes,
3055                             &ns->illegal_bytes);
3056         /* GLPRT_ERRBC not supported */
3057         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3058                             pf->offset_loaded, &os->mac_local_faults,
3059                             &ns->mac_local_faults);
3060         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3061                             pf->offset_loaded, &os->mac_remote_faults,
3062                             &ns->mac_remote_faults);
3063         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3064                             pf->offset_loaded, &os->rx_length_errors,
3065                             &ns->rx_length_errors);
3066         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3067                             pf->offset_loaded, &os->link_xon_rx,
3068                             &ns->link_xon_rx);
3069         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3070                             pf->offset_loaded, &os->link_xoff_rx,
3071                             &ns->link_xoff_rx);
3072         for (i = 0; i < 8; i++) {
3073                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3074                                     pf->offset_loaded,
3075                                     &os->priority_xon_rx[i],
3076                                     &ns->priority_xon_rx[i]);
3077                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3078                                     pf->offset_loaded,
3079                                     &os->priority_xoff_rx[i],
3080                                     &ns->priority_xoff_rx[i]);
3081         }
3082         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3083                             pf->offset_loaded, &os->link_xon_tx,
3084                             &ns->link_xon_tx);
3085         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3086                             pf->offset_loaded, &os->link_xoff_tx,
3087                             &ns->link_xoff_tx);
3088         for (i = 0; i < 8; i++) {
3089                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3090                                     pf->offset_loaded,
3091                                     &os->priority_xon_tx[i],
3092                                     &ns->priority_xon_tx[i]);
3093                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3094                                     pf->offset_loaded,
3095                                     &os->priority_xoff_tx[i],
3096                                     &ns->priority_xoff_tx[i]);
3097                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3098                                     pf->offset_loaded,
3099                                     &os->priority_xon_2_xoff[i],
3100                                     &ns->priority_xon_2_xoff[i]);
3101         }
3102         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3103                             I40E_GLPRT_PRC64L(hw->port),
3104                             pf->offset_loaded, &os->rx_size_64,
3105                             &ns->rx_size_64);
3106         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3107                             I40E_GLPRT_PRC127L(hw->port),
3108                             pf->offset_loaded, &os->rx_size_127,
3109                             &ns->rx_size_127);
3110         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3111                             I40E_GLPRT_PRC255L(hw->port),
3112                             pf->offset_loaded, &os->rx_size_255,
3113                             &ns->rx_size_255);
3114         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3115                             I40E_GLPRT_PRC511L(hw->port),
3116                             pf->offset_loaded, &os->rx_size_511,
3117                             &ns->rx_size_511);
3118         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3119                             I40E_GLPRT_PRC1023L(hw->port),
3120                             pf->offset_loaded, &os->rx_size_1023,
3121                             &ns->rx_size_1023);
3122         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3123                             I40E_GLPRT_PRC1522L(hw->port),
3124                             pf->offset_loaded, &os->rx_size_1522,
3125                             &ns->rx_size_1522);
3126         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3127                             I40E_GLPRT_PRC9522L(hw->port),
3128                             pf->offset_loaded, &os->rx_size_big,
3129                             &ns->rx_size_big);
3130         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3131                             pf->offset_loaded, &os->rx_undersize,
3132                             &ns->rx_undersize);
3133         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3134                             pf->offset_loaded, &os->rx_fragments,
3135                             &ns->rx_fragments);
3136         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3137                             pf->offset_loaded, &os->rx_oversize,
3138                             &ns->rx_oversize);
3139         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3140                             pf->offset_loaded, &os->rx_jabber,
3141                             &ns->rx_jabber);
3142         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3143                             I40E_GLPRT_PTC64L(hw->port),
3144                             pf->offset_loaded, &os->tx_size_64,
3145                             &ns->tx_size_64);
3146         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3147                             I40E_GLPRT_PTC127L(hw->port),
3148                             pf->offset_loaded, &os->tx_size_127,
3149                             &ns->tx_size_127);
3150         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3151                             I40E_GLPRT_PTC255L(hw->port),
3152                             pf->offset_loaded, &os->tx_size_255,
3153                             &ns->tx_size_255);
3154         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3155                             I40E_GLPRT_PTC511L(hw->port),
3156                             pf->offset_loaded, &os->tx_size_511,
3157                             &ns->tx_size_511);
3158         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3159                             I40E_GLPRT_PTC1023L(hw->port),
3160                             pf->offset_loaded, &os->tx_size_1023,
3161                             &ns->tx_size_1023);
3162         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3163                             I40E_GLPRT_PTC1522L(hw->port),
3164                             pf->offset_loaded, &os->tx_size_1522,
3165                             &ns->tx_size_1522);
3166         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3167                             I40E_GLPRT_PTC9522L(hw->port),
3168                             pf->offset_loaded, &os->tx_size_big,
3169                             &ns->tx_size_big);
3170         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3171                            pf->offset_loaded,
3172                            &os->fd_sb_match, &ns->fd_sb_match);
3173         /* GLPRT_MSPDC not supported */
3174         /* GLPRT_XEC not supported */
3175
3176         pf->offset_loaded = true;
3177
3178         if (pf->main_vsi)
3179                 i40e_update_vsi_stats(pf->main_vsi);
3180 }
3181
3182 /* Get all statistics of a port */
3183 static int
3184 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3185 {
3186         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3187         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3188         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3189         struct i40e_vsi *vsi;
3190         unsigned i;
3191
3192         /* call read registers - updates values, now write them to struct */
3193         i40e_read_stats_registers(pf, hw);
3194
3195         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3196                         pf->main_vsi->eth_stats.rx_multicast +
3197                         pf->main_vsi->eth_stats.rx_broadcast -
3198                         pf->main_vsi->eth_stats.rx_discards;
3199         stats->opackets = ns->eth.tx_unicast +
3200                         ns->eth.tx_multicast +
3201                         ns->eth.tx_broadcast;
3202         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3203         stats->obytes   = ns->eth.tx_bytes;
3204         stats->oerrors  = ns->eth.tx_errors +
3205                         pf->main_vsi->eth_stats.tx_errors;
3206
3207         /* Rx Errors */
3208         stats->imissed  = ns->eth.rx_discards +
3209                         pf->main_vsi->eth_stats.rx_discards;
3210         stats->ierrors  = ns->crc_errors +
3211                         ns->rx_length_errors + ns->rx_undersize +
3212                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3213
3214         if (pf->vfs) {
3215                 for (i = 0; i < pf->vf_num; i++) {
3216                         vsi = pf->vfs[i].vsi;
3217                         i40e_update_vsi_stats(vsi);
3218
3219                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3220                                         vsi->eth_stats.rx_multicast +
3221                                         vsi->eth_stats.rx_broadcast -
3222                                         vsi->eth_stats.rx_discards);
3223                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3224                         stats->oerrors  += vsi->eth_stats.tx_errors;
3225                         stats->imissed  += vsi->eth_stats.rx_discards;
3226                 }
3227         }
3228
3229         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3230         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3231         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3232         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3233         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3234         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3235         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3236                     ns->eth.rx_unknown_protocol);
3237         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3238         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3239         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3240         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3241         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3242         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3243
3244         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3245                     ns->tx_dropped_link_down);
3246         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3247         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3248                     ns->illegal_bytes);
3249         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3250         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3251                     ns->mac_local_faults);
3252         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3253                     ns->mac_remote_faults);
3254         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3255                     ns->rx_length_errors);
3256         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3257         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3258         for (i = 0; i < 8; i++) {
3259                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3260                                 i, ns->priority_xon_rx[i]);
3261                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3262                                 i, ns->priority_xoff_rx[i]);
3263         }
3264         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3265         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3266         for (i = 0; i < 8; i++) {
3267                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3268                                 i, ns->priority_xon_tx[i]);
3269                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3270                                 i, ns->priority_xoff_tx[i]);
3271                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3272                                 i, ns->priority_xon_2_xoff[i]);
3273         }
3274         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3275         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3276         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3277         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3278         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3279         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3280         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3281         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3282         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3283         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3284         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3285         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3286         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3287         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3288         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3289         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3290         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3291         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3292         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3293                         ns->mac_short_packet_dropped);
3294         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3295                     ns->checksum_error);
3296         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3297         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3298         return 0;
3299 }
3300
3301 /* Reset the statistics */
3302 static void
3303 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3304 {
3305         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3306         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3307
3308         /* Mark PF and VSI stats to update the offset, aka "reset" */
3309         pf->offset_loaded = false;
3310         if (pf->main_vsi)
3311                 pf->main_vsi->offset_loaded = false;
3312
3313         /* read the stats, reading current register values into offset */
3314         i40e_read_stats_registers(pf, hw);
3315 }
3316
3317 static uint32_t
3318 i40e_xstats_calc_num(void)
3319 {
3320         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3321                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3322                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3323 }
3324
3325 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3326                                      struct rte_eth_xstat_name *xstats_names,
3327                                      __rte_unused unsigned limit)
3328 {
3329         unsigned count = 0;
3330         unsigned i, prio;
3331
3332         if (xstats_names == NULL)
3333                 return i40e_xstats_calc_num();
3334
3335         /* Note: limit checked in rte_eth_xstats_names() */
3336
3337         /* Get stats from i40e_eth_stats struct */
3338         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3339                 strlcpy(xstats_names[count].name,
3340                         rte_i40e_stats_strings[i].name,
3341                         sizeof(xstats_names[count].name));
3342                 count++;
3343         }
3344
3345         /* Get individiual stats from i40e_hw_port struct */
3346         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3347                 strlcpy(xstats_names[count].name,
3348                         rte_i40e_hw_port_strings[i].name,
3349                         sizeof(xstats_names[count].name));
3350                 count++;
3351         }
3352
3353         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3354                 for (prio = 0; prio < 8; prio++) {
3355                         snprintf(xstats_names[count].name,
3356                                  sizeof(xstats_names[count].name),
3357                                  "rx_priority%u_%s", prio,
3358                                  rte_i40e_rxq_prio_strings[i].name);
3359                         count++;
3360                 }
3361         }
3362
3363         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3364                 for (prio = 0; prio < 8; prio++) {
3365                         snprintf(xstats_names[count].name,
3366                                  sizeof(xstats_names[count].name),
3367                                  "tx_priority%u_%s", prio,
3368                                  rte_i40e_txq_prio_strings[i].name);
3369                         count++;
3370                 }
3371         }
3372         return count;
3373 }
3374
3375 static int
3376 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3377                     unsigned n)
3378 {
3379         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3380         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3381         unsigned i, count, prio;
3382         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3383
3384         count = i40e_xstats_calc_num();
3385         if (n < count)
3386                 return count;
3387
3388         i40e_read_stats_registers(pf, hw);
3389
3390         if (xstats == NULL)
3391                 return 0;
3392
3393         count = 0;
3394
3395         /* Get stats from i40e_eth_stats struct */
3396         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3397                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3398                         rte_i40e_stats_strings[i].offset);
3399                 xstats[count].id = count;
3400                 count++;
3401         }
3402
3403         /* Get individiual stats from i40e_hw_port struct */
3404         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3405                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3406                         rte_i40e_hw_port_strings[i].offset);
3407                 xstats[count].id = count;
3408                 count++;
3409         }
3410
3411         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3412                 for (prio = 0; prio < 8; prio++) {
3413                         xstats[count].value =
3414                                 *(uint64_t *)(((char *)hw_stats) +
3415                                 rte_i40e_rxq_prio_strings[i].offset +
3416                                 (sizeof(uint64_t) * prio));
3417                         xstats[count].id = count;
3418                         count++;
3419                 }
3420         }
3421
3422         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3423                 for (prio = 0; prio < 8; prio++) {
3424                         xstats[count].value =
3425                                 *(uint64_t *)(((char *)hw_stats) +
3426                                 rte_i40e_txq_prio_strings[i].offset +
3427                                 (sizeof(uint64_t) * prio));
3428                         xstats[count].id = count;
3429                         count++;
3430                 }
3431         }
3432
3433         return count;
3434 }
3435
3436 static int
3437 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3438                                  __rte_unused uint16_t queue_id,
3439                                  __rte_unused uint8_t stat_idx,
3440                                  __rte_unused uint8_t is_rx)
3441 {
3442         PMD_INIT_FUNC_TRACE();
3443
3444         return -ENOSYS;
3445 }
3446
3447 static int
3448 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3449 {
3450         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3451         u32 full_ver;
3452         u8 ver, patch;
3453         u16 build;
3454         int ret;
3455
3456         full_ver = hw->nvm.oem_ver;
3457         ver = (u8)(full_ver >> 24);
3458         build = (u16)((full_ver >> 8) & 0xffff);
3459         patch = (u8)(full_ver & 0xff);
3460
3461         ret = snprintf(fw_version, fw_size,
3462                  "%d.%d%d 0x%08x %d.%d.%d",
3463                  ((hw->nvm.version >> 12) & 0xf),
3464                  ((hw->nvm.version >> 4) & 0xff),
3465                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3466                  ver, build, patch);
3467
3468         ret += 1; /* add the size of '\0' */
3469         if (fw_size < (u32)ret)
3470                 return ret;
3471         else
3472                 return 0;
3473 }
3474
3475 /*
3476  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3477  * the Rx data path does not hang if the FW LLDP is stopped.
3478  * return true if lldp need to stop
3479  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3480  */
3481 static bool
3482 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3483 {
3484         double nvm_ver;
3485         char ver_str[64] = {0};
3486         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3487
3488         i40e_fw_version_get(dev, ver_str, 64);
3489         nvm_ver = atof(ver_str);
3490         if ((hw->mac.type == I40E_MAC_X722 ||
3491              hw->mac.type == I40E_MAC_X722_VF) &&
3492              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3493                 return true;
3494         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3495                 return true;
3496
3497         return false;
3498 }
3499
3500 static void
3501 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3502 {
3503         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3504         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3505         struct i40e_vsi *vsi = pf->main_vsi;
3506         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3507
3508         dev_info->max_rx_queues = vsi->nb_qps;
3509         dev_info->max_tx_queues = vsi->nb_qps;
3510         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3511         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3512         dev_info->max_mac_addrs = vsi->max_macaddrs;
3513         dev_info->max_vfs = pci_dev->max_vfs;
3514         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3515         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3516         dev_info->rx_queue_offload_capa = 0;
3517         dev_info->rx_offload_capa =
3518                 DEV_RX_OFFLOAD_VLAN_STRIP |
3519                 DEV_RX_OFFLOAD_QINQ_STRIP |
3520                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3521                 DEV_RX_OFFLOAD_UDP_CKSUM |
3522                 DEV_RX_OFFLOAD_TCP_CKSUM |
3523                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3524                 DEV_RX_OFFLOAD_KEEP_CRC |
3525                 DEV_RX_OFFLOAD_SCATTER |
3526                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3527                 DEV_RX_OFFLOAD_VLAN_FILTER |
3528                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3529
3530         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3531         dev_info->tx_offload_capa =
3532                 DEV_TX_OFFLOAD_VLAN_INSERT |
3533                 DEV_TX_OFFLOAD_QINQ_INSERT |
3534                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3535                 DEV_TX_OFFLOAD_UDP_CKSUM |
3536                 DEV_TX_OFFLOAD_TCP_CKSUM |
3537                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3538                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3539                 DEV_TX_OFFLOAD_TCP_TSO |
3540                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3541                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3542                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3543                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3544                 DEV_TX_OFFLOAD_MULTI_SEGS |
3545                 dev_info->tx_queue_offload_capa;
3546         dev_info->dev_capa =
3547                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3548                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3549
3550         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3551                                                 sizeof(uint32_t);
3552         dev_info->reta_size = pf->hash_lut_size;
3553         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3554
3555         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3556                 .rx_thresh = {
3557                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3558                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3559                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3560                 },
3561                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3562                 .rx_drop_en = 0,
3563                 .offloads = 0,
3564         };
3565
3566         dev_info->default_txconf = (struct rte_eth_txconf) {
3567                 .tx_thresh = {
3568                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3569                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3570                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3571                 },
3572                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3573                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3574                 .offloads = 0,
3575         };
3576
3577         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3578                 .nb_max = I40E_MAX_RING_DESC,
3579                 .nb_min = I40E_MIN_RING_DESC,
3580                 .nb_align = I40E_ALIGN_RING_DESC,
3581         };
3582
3583         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3584                 .nb_max = I40E_MAX_RING_DESC,
3585                 .nb_min = I40E_MIN_RING_DESC,
3586                 .nb_align = I40E_ALIGN_RING_DESC,
3587                 .nb_seg_max = I40E_TX_MAX_SEG,
3588                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3589         };
3590
3591         if (pf->flags & I40E_FLAG_VMDQ) {
3592                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3593                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3594                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3595                                                 pf->max_nb_vmdq_vsi;
3596                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3597                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3598                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3599         }
3600
3601         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3602                 /* For XL710 */
3603                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3604                 dev_info->default_rxportconf.nb_queues = 2;
3605                 dev_info->default_txportconf.nb_queues = 2;
3606                 if (dev->data->nb_rx_queues == 1)
3607                         dev_info->default_rxportconf.ring_size = 2048;
3608                 else
3609                         dev_info->default_rxportconf.ring_size = 1024;
3610                 if (dev->data->nb_tx_queues == 1)
3611                         dev_info->default_txportconf.ring_size = 1024;
3612                 else
3613                         dev_info->default_txportconf.ring_size = 512;
3614
3615         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3616                 /* For XXV710 */
3617                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3618                 dev_info->default_rxportconf.nb_queues = 1;
3619                 dev_info->default_txportconf.nb_queues = 1;
3620                 dev_info->default_rxportconf.ring_size = 256;
3621                 dev_info->default_txportconf.ring_size = 256;
3622         } else {
3623                 /* For X710 */
3624                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3625                 dev_info->default_rxportconf.nb_queues = 1;
3626                 dev_info->default_txportconf.nb_queues = 1;
3627                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3628                         dev_info->default_rxportconf.ring_size = 512;
3629                         dev_info->default_txportconf.ring_size = 256;
3630                 } else {
3631                         dev_info->default_rxportconf.ring_size = 256;
3632                         dev_info->default_txportconf.ring_size = 256;
3633                 }
3634         }
3635         dev_info->default_rxportconf.burst_size = 32;
3636         dev_info->default_txportconf.burst_size = 32;
3637 }
3638
3639 static int
3640 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3641 {
3642         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3643         struct i40e_vsi *vsi = pf->main_vsi;
3644         PMD_INIT_FUNC_TRACE();
3645
3646         if (on)
3647                 return i40e_vsi_add_vlan(vsi, vlan_id);
3648         else
3649                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3650 }
3651
3652 static int
3653 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3654                                 enum rte_vlan_type vlan_type,
3655                                 uint16_t tpid, int qinq)
3656 {
3657         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3658         uint64_t reg_r = 0;
3659         uint64_t reg_w = 0;
3660         uint16_t reg_id = 3;
3661         int ret;
3662
3663         if (qinq) {
3664                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3665                         reg_id = 2;
3666         }
3667
3668         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3669                                           &reg_r, NULL);
3670         if (ret != I40E_SUCCESS) {
3671                 PMD_DRV_LOG(ERR,
3672                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3673                            reg_id);
3674                 return -EIO;
3675         }
3676         PMD_DRV_LOG(DEBUG,
3677                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3678                     reg_id, reg_r);
3679
3680         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3681         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3682         if (reg_r == reg_w) {
3683                 PMD_DRV_LOG(DEBUG, "No need to write");
3684                 return 0;
3685         }
3686
3687         ret = i40e_aq_debug_write_global_register(hw,
3688                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3689                                            reg_w, NULL);
3690         if (ret != I40E_SUCCESS) {
3691                 PMD_DRV_LOG(ERR,
3692                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3693                             reg_id);
3694                 return -EIO;
3695         }
3696         PMD_DRV_LOG(DEBUG,
3697                     "Global register 0x%08x is changed with value 0x%08x",
3698                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3699
3700         return 0;
3701 }
3702
3703 static int
3704 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3705                    enum rte_vlan_type vlan_type,
3706                    uint16_t tpid)
3707 {
3708         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3709         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3710         int qinq = dev->data->dev_conf.rxmode.offloads &
3711                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3712         int ret = 0;
3713
3714         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3715              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3716             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3717                 PMD_DRV_LOG(ERR,
3718                             "Unsupported vlan type.");
3719                 return -EINVAL;
3720         }
3721
3722         if (pf->support_multi_driver) {
3723                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3724                 return -ENOTSUP;
3725         }
3726
3727         /* 802.1ad frames ability is added in NVM API 1.7*/
3728         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3729                 if (qinq) {
3730                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3731                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3732                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3733                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3734                 } else {
3735                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3736                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3737                 }
3738                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3739                 if (ret != I40E_SUCCESS) {
3740                         PMD_DRV_LOG(ERR,
3741                                     "Set switch config failed aq_err: %d",
3742                                     hw->aq.asq_last_status);
3743                         ret = -EIO;
3744                 }
3745         } else
3746                 /* If NVM API < 1.7, keep the register setting */
3747                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3748                                                       tpid, qinq);
3749
3750         return ret;
3751 }
3752
3753 static int
3754 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3755 {
3756         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3757         struct i40e_vsi *vsi = pf->main_vsi;
3758         struct rte_eth_rxmode *rxmode;
3759
3760         rxmode = &dev->data->dev_conf.rxmode;
3761         if (mask & ETH_VLAN_FILTER_MASK) {
3762                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3763                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3764                 else
3765                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3766         }
3767
3768         if (mask & ETH_VLAN_STRIP_MASK) {
3769                 /* Enable or disable VLAN stripping */
3770                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3771                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3772                 else
3773                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3774         }
3775
3776         if (mask & ETH_VLAN_EXTEND_MASK) {
3777                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3778                         i40e_vsi_config_double_vlan(vsi, TRUE);
3779                         /* Set global registers with default ethertype. */
3780                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3781                                            RTE_ETHER_TYPE_VLAN);
3782                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3783                                            RTE_ETHER_TYPE_VLAN);
3784                 }
3785                 else
3786                         i40e_vsi_config_double_vlan(vsi, FALSE);
3787         }
3788
3789         return 0;
3790 }
3791
3792 static void
3793 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3794                           __rte_unused uint16_t queue,
3795                           __rte_unused int on)
3796 {
3797         PMD_INIT_FUNC_TRACE();
3798 }
3799
3800 static int
3801 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3802 {
3803         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3804         struct i40e_vsi *vsi = pf->main_vsi;
3805         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3806         struct i40e_vsi_vlan_pvid_info info;
3807
3808         memset(&info, 0, sizeof(info));
3809         info.on = on;
3810         if (info.on)
3811                 info.config.pvid = pvid;
3812         else {
3813                 info.config.reject.tagged =
3814                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3815                 info.config.reject.untagged =
3816                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3817         }
3818
3819         return i40e_vsi_vlan_pvid_set(vsi, &info);
3820 }
3821
3822 static int
3823 i40e_dev_led_on(struct rte_eth_dev *dev)
3824 {
3825         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3826         uint32_t mode = i40e_led_get(hw);
3827
3828         if (mode == 0)
3829                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3830
3831         return 0;
3832 }
3833
3834 static int
3835 i40e_dev_led_off(struct rte_eth_dev *dev)
3836 {
3837         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3838         uint32_t mode = i40e_led_get(hw);
3839
3840         if (mode != 0)
3841                 i40e_led_set(hw, 0, false);
3842
3843         return 0;
3844 }
3845
3846 static int
3847 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3848 {
3849         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3850         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3851
3852         fc_conf->pause_time = pf->fc_conf.pause_time;
3853
3854         /* read out from register, in case they are modified by other port */
3855         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3856                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3857         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3858                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3859
3860         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3861         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3862
3863          /* Return current mode according to actual setting*/
3864         switch (hw->fc.current_mode) {
3865         case I40E_FC_FULL:
3866                 fc_conf->mode = RTE_FC_FULL;
3867                 break;
3868         case I40E_FC_TX_PAUSE:
3869                 fc_conf->mode = RTE_FC_TX_PAUSE;
3870                 break;
3871         case I40E_FC_RX_PAUSE:
3872                 fc_conf->mode = RTE_FC_RX_PAUSE;
3873                 break;
3874         case I40E_FC_NONE:
3875         default:
3876                 fc_conf->mode = RTE_FC_NONE;
3877         };
3878
3879         return 0;
3880 }
3881
3882 static int
3883 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3884 {
3885         uint32_t mflcn_reg, fctrl_reg, reg;
3886         uint32_t max_high_water;
3887         uint8_t i, aq_failure;
3888         int err;
3889         struct i40e_hw *hw;
3890         struct i40e_pf *pf;
3891         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3892                 [RTE_FC_NONE] = I40E_FC_NONE,
3893                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3894                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3895                 [RTE_FC_FULL] = I40E_FC_FULL
3896         };
3897
3898         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3899
3900         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3901         if ((fc_conf->high_water > max_high_water) ||
3902                         (fc_conf->high_water < fc_conf->low_water)) {
3903                 PMD_INIT_LOG(ERR,
3904                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3905                         max_high_water);
3906                 return -EINVAL;
3907         }
3908
3909         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3910         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3911         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3912
3913         pf->fc_conf.pause_time = fc_conf->pause_time;
3914         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3915         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3916
3917         PMD_INIT_FUNC_TRACE();
3918
3919         /* All the link flow control related enable/disable register
3920          * configuration is handle by the F/W
3921          */
3922         err = i40e_set_fc(hw, &aq_failure, true);
3923         if (err < 0)
3924                 return -ENOSYS;
3925
3926         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3927                 /* Configure flow control refresh threshold,
3928                  * the value for stat_tx_pause_refresh_timer[8]
3929                  * is used for global pause operation.
3930                  */
3931
3932                 I40E_WRITE_REG(hw,
3933                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3934                                pf->fc_conf.pause_time);
3935
3936                 /* configure the timer value included in transmitted pause
3937                  * frame,
3938                  * the value for stat_tx_pause_quanta[8] is used for global
3939                  * pause operation
3940                  */
3941                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3942                                pf->fc_conf.pause_time);
3943
3944                 fctrl_reg = I40E_READ_REG(hw,
3945                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3946
3947                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3948                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3949                 else
3950                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3951
3952                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3953                                fctrl_reg);
3954         } else {
3955                 /* Configure pause time (2 TCs per register) */
3956                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3957                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3958                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3959
3960                 /* Configure flow control refresh threshold value */
3961                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3962                                pf->fc_conf.pause_time / 2);
3963
3964                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3965
3966                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3967                  *depending on configuration
3968                  */
3969                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3970                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3971                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3972                 } else {
3973                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3974                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3975                 }
3976
3977                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3978         }
3979
3980         if (!pf->support_multi_driver) {
3981                 /* config water marker both based on the packets and bytes */
3982                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3983                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3984                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3985                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3986                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3987                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3988                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3989                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3990                                   << I40E_KILOSHIFT);
3991                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3992                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3993                                    << I40E_KILOSHIFT);
3994         } else {
3995                 PMD_DRV_LOG(ERR,
3996                             "Water marker configuration is not supported.");
3997         }
3998
3999         I40E_WRITE_FLUSH(hw);
4000
4001         return 0;
4002 }
4003
4004 static int
4005 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4006                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4007 {
4008         PMD_INIT_FUNC_TRACE();
4009
4010         return -ENOSYS;
4011 }
4012
4013 /* Add a MAC address, and update filters */
4014 static int
4015 i40e_macaddr_add(struct rte_eth_dev *dev,
4016                  struct rte_ether_addr *mac_addr,
4017                  __rte_unused uint32_t index,
4018                  uint32_t pool)
4019 {
4020         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4021         struct i40e_mac_filter_info mac_filter;
4022         struct i40e_vsi *vsi;
4023         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4024         int ret;
4025
4026         /* If VMDQ not enabled or configured, return */
4027         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4028                           !pf->nb_cfg_vmdq_vsi)) {
4029                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4030                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4031                         pool);
4032                 return -ENOTSUP;
4033         }
4034
4035         if (pool > pf->nb_cfg_vmdq_vsi) {
4036                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4037                                 pool, pf->nb_cfg_vmdq_vsi);
4038                 return -EINVAL;
4039         }
4040
4041         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4042         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4043                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4044         else
4045                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4046
4047         if (pool == 0)
4048                 vsi = pf->main_vsi;
4049         else
4050                 vsi = pf->vmdq[pool - 1].vsi;
4051
4052         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4053         if (ret != I40E_SUCCESS) {
4054                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4055                 return -ENODEV;
4056         }
4057         return 0;
4058 }
4059
4060 /* Remove a MAC address, and update filters */
4061 static void
4062 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4063 {
4064         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4065         struct i40e_vsi *vsi;
4066         struct rte_eth_dev_data *data = dev->data;
4067         struct rte_ether_addr *macaddr;
4068         int ret;
4069         uint32_t i;
4070         uint64_t pool_sel;
4071
4072         macaddr = &(data->mac_addrs[index]);
4073
4074         pool_sel = dev->data->mac_pool_sel[index];
4075
4076         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4077                 if (pool_sel & (1ULL << i)) {
4078                         if (i == 0)
4079                                 vsi = pf->main_vsi;
4080                         else {
4081                                 /* No VMDQ pool enabled or configured */
4082                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4083                                         (i > pf->nb_cfg_vmdq_vsi)) {
4084                                         PMD_DRV_LOG(ERR,
4085                                                 "No VMDQ pool enabled/configured");
4086                                         return;
4087                                 }
4088                                 vsi = pf->vmdq[i - 1].vsi;
4089                         }
4090                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4091
4092                         if (ret) {
4093                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4094                                 return;
4095                         }
4096                 }
4097         }
4098 }
4099
4100 /* Set perfect match or hash match of MAC and VLAN for a VF */
4101 static int
4102 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4103                  struct rte_eth_mac_filter *filter,
4104                  bool add)
4105 {
4106         struct i40e_hw *hw;
4107         struct i40e_mac_filter_info mac_filter;
4108         struct rte_ether_addr old_mac;
4109         struct rte_ether_addr *new_mac;
4110         struct i40e_pf_vf *vf = NULL;
4111         uint16_t vf_id;
4112         int ret;
4113
4114         if (pf == NULL) {
4115                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4116                 return -EINVAL;
4117         }
4118         hw = I40E_PF_TO_HW(pf);
4119
4120         if (filter == NULL) {
4121                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4122                 return -EINVAL;
4123         }
4124
4125         new_mac = &filter->mac_addr;
4126
4127         if (rte_is_zero_ether_addr(new_mac)) {
4128                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4129                 return -EINVAL;
4130         }
4131
4132         vf_id = filter->dst_id;
4133
4134         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4135                 PMD_DRV_LOG(ERR, "Invalid argument.");
4136                 return -EINVAL;
4137         }
4138         vf = &pf->vfs[vf_id];
4139
4140         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4141                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4142                 return -EINVAL;
4143         }
4144
4145         if (add) {
4146                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4147                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4148                                 RTE_ETHER_ADDR_LEN);
4149                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4150                                  RTE_ETHER_ADDR_LEN);
4151
4152                 mac_filter.filter_type = filter->filter_type;
4153                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4154                 if (ret != I40E_SUCCESS) {
4155                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4156                         return -1;
4157                 }
4158                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4159         } else {
4160                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4161                                 RTE_ETHER_ADDR_LEN);
4162                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4163                 if (ret != I40E_SUCCESS) {
4164                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4165                         return -1;
4166                 }
4167
4168                 /* Clear device address as it has been removed */
4169                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4170                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4171         }
4172
4173         return 0;
4174 }
4175
4176 /* MAC filter handle */
4177 static int
4178 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4179                 void *arg)
4180 {
4181         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4182         struct rte_eth_mac_filter *filter;
4183         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4184         int ret = I40E_NOT_SUPPORTED;
4185
4186         filter = (struct rte_eth_mac_filter *)(arg);
4187
4188         switch (filter_op) {
4189         case RTE_ETH_FILTER_NOP:
4190                 ret = I40E_SUCCESS;
4191                 break;
4192         case RTE_ETH_FILTER_ADD:
4193                 i40e_pf_disable_irq0(hw);
4194                 if (filter->is_vf)
4195                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4196                 i40e_pf_enable_irq0(hw);
4197                 break;
4198         case RTE_ETH_FILTER_DELETE:
4199                 i40e_pf_disable_irq0(hw);
4200                 if (filter->is_vf)
4201                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4202                 i40e_pf_enable_irq0(hw);
4203                 break;
4204         default:
4205                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4206                 ret = I40E_ERR_PARAM;
4207                 break;
4208         }
4209
4210         return ret;
4211 }
4212
4213 static int
4214 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4215 {
4216         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4217         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4218         uint32_t reg;
4219         int ret;
4220
4221         if (!lut)
4222                 return -EINVAL;
4223
4224         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4225                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4226                                           vsi->type != I40E_VSI_SRIOV,
4227                                           lut, lut_size);
4228                 if (ret) {
4229                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4230                         return ret;
4231                 }
4232         } else {
4233                 uint32_t *lut_dw = (uint32_t *)lut;
4234                 uint16_t i, lut_size_dw = lut_size / 4;
4235
4236                 if (vsi->type == I40E_VSI_SRIOV) {
4237                         for (i = 0; i <= lut_size_dw; i++) {
4238                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4239                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4240                         }
4241                 } else {
4242                         for (i = 0; i < lut_size_dw; i++)
4243                                 lut_dw[i] = I40E_READ_REG(hw,
4244                                                           I40E_PFQF_HLUT(i));
4245                 }
4246         }
4247
4248         return 0;
4249 }
4250
4251 int
4252 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4253 {
4254         struct i40e_pf *pf;
4255         struct i40e_hw *hw;
4256         int ret;
4257
4258         if (!vsi || !lut)
4259                 return -EINVAL;
4260
4261         pf = I40E_VSI_TO_PF(vsi);
4262         hw = I40E_VSI_TO_HW(vsi);
4263
4264         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4265                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4266                                           vsi->type != I40E_VSI_SRIOV,
4267                                           lut, lut_size);
4268                 if (ret) {
4269                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4270                         return ret;
4271                 }
4272         } else {
4273                 uint32_t *lut_dw = (uint32_t *)lut;
4274                 uint16_t i, lut_size_dw = lut_size / 4;
4275
4276                 if (vsi->type == I40E_VSI_SRIOV) {
4277                         for (i = 0; i < lut_size_dw; i++)
4278                                 I40E_WRITE_REG(
4279                                         hw,
4280                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4281                                         lut_dw[i]);
4282                 } else {
4283                         for (i = 0; i < lut_size_dw; i++)
4284                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4285                                                lut_dw[i]);
4286                 }
4287                 I40E_WRITE_FLUSH(hw);
4288         }
4289
4290         return 0;
4291 }
4292
4293 static int
4294 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4295                          struct rte_eth_rss_reta_entry64 *reta_conf,
4296                          uint16_t reta_size)
4297 {
4298         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4299         uint16_t i, lut_size = pf->hash_lut_size;
4300         uint16_t idx, shift;
4301         uint8_t *lut;
4302         int ret;
4303
4304         if (reta_size != lut_size ||
4305                 reta_size > ETH_RSS_RETA_SIZE_512) {
4306                 PMD_DRV_LOG(ERR,
4307                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4308                         reta_size, lut_size);
4309                 return -EINVAL;
4310         }
4311
4312         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4313         if (!lut) {
4314                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4315                 return -ENOMEM;
4316         }
4317         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4318         if (ret)
4319                 goto out;
4320         for (i = 0; i < reta_size; i++) {
4321                 idx = i / RTE_RETA_GROUP_SIZE;
4322                 shift = i % RTE_RETA_GROUP_SIZE;
4323                 if (reta_conf[idx].mask & (1ULL << shift))
4324                         lut[i] = reta_conf[idx].reta[shift];
4325         }
4326         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4327
4328         pf->adapter->rss_reta_updated = 1;
4329
4330 out:
4331         rte_free(lut);
4332
4333         return ret;
4334 }
4335
4336 static int
4337 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4338                         struct rte_eth_rss_reta_entry64 *reta_conf,
4339                         uint16_t reta_size)
4340 {
4341         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4342         uint16_t i, lut_size = pf->hash_lut_size;
4343         uint16_t idx, shift;
4344         uint8_t *lut;
4345         int ret;
4346
4347         if (reta_size != lut_size ||
4348                 reta_size > ETH_RSS_RETA_SIZE_512) {
4349                 PMD_DRV_LOG(ERR,
4350                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4351                         reta_size, lut_size);
4352                 return -EINVAL;
4353         }
4354
4355         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4356         if (!lut) {
4357                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4358                 return -ENOMEM;
4359         }
4360
4361         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4362         if (ret)
4363                 goto out;
4364         for (i = 0; i < reta_size; i++) {
4365                 idx = i / RTE_RETA_GROUP_SIZE;
4366                 shift = i % RTE_RETA_GROUP_SIZE;
4367                 if (reta_conf[idx].mask & (1ULL << shift))
4368                         reta_conf[idx].reta[shift] = lut[i];
4369         }
4370
4371 out:
4372         rte_free(lut);
4373
4374         return ret;
4375 }
4376
4377 /**
4378  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4379  * @hw:   pointer to the HW structure
4380  * @mem:  pointer to mem struct to fill out
4381  * @size: size of memory requested
4382  * @alignment: what to align the allocation to
4383  **/
4384 enum i40e_status_code
4385 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4386                         struct i40e_dma_mem *mem,
4387                         u64 size,
4388                         u32 alignment)
4389 {
4390         const struct rte_memzone *mz = NULL;
4391         char z_name[RTE_MEMZONE_NAMESIZE];
4392
4393         if (!mem)
4394                 return I40E_ERR_PARAM;
4395
4396         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4397         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4398                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4399         if (!mz)
4400                 return I40E_ERR_NO_MEMORY;
4401
4402         mem->size = size;
4403         mem->va = mz->addr;
4404         mem->pa = mz->iova;
4405         mem->zone = (const void *)mz;
4406         PMD_DRV_LOG(DEBUG,
4407                 "memzone %s allocated with physical address: %"PRIu64,
4408                 mz->name, mem->pa);
4409
4410         return I40E_SUCCESS;
4411 }
4412
4413 /**
4414  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4415  * @hw:   pointer to the HW structure
4416  * @mem:  ptr to mem struct to free
4417  **/
4418 enum i40e_status_code
4419 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4420                     struct i40e_dma_mem *mem)
4421 {
4422         if (!mem)
4423                 return I40E_ERR_PARAM;
4424
4425         PMD_DRV_LOG(DEBUG,
4426                 "memzone %s to be freed with physical address: %"PRIu64,
4427                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4428         rte_memzone_free((const struct rte_memzone *)mem->zone);
4429         mem->zone = NULL;
4430         mem->va = NULL;
4431         mem->pa = (u64)0;
4432
4433         return I40E_SUCCESS;
4434 }
4435
4436 /**
4437  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4438  * @hw:   pointer to the HW structure
4439  * @mem:  pointer to mem struct to fill out
4440  * @size: size of memory requested
4441  **/
4442 enum i40e_status_code
4443 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4444                          struct i40e_virt_mem *mem,
4445                          u32 size)
4446 {
4447         if (!mem)
4448                 return I40E_ERR_PARAM;
4449
4450         mem->size = size;
4451         mem->va = rte_zmalloc("i40e", size, 0);
4452
4453         if (mem->va)
4454                 return I40E_SUCCESS;
4455         else
4456                 return I40E_ERR_NO_MEMORY;
4457 }
4458
4459 /**
4460  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4461  * @hw:   pointer to the HW structure
4462  * @mem:  pointer to mem struct to free
4463  **/
4464 enum i40e_status_code
4465 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4466                      struct i40e_virt_mem *mem)
4467 {
4468         if (!mem)
4469                 return I40E_ERR_PARAM;
4470
4471         rte_free(mem->va);
4472         mem->va = NULL;
4473
4474         return I40E_SUCCESS;
4475 }
4476
4477 void
4478 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4479 {
4480         rte_spinlock_init(&sp->spinlock);
4481 }
4482
4483 void
4484 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4485 {
4486         rte_spinlock_lock(&sp->spinlock);
4487 }
4488
4489 void
4490 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4491 {
4492         rte_spinlock_unlock(&sp->spinlock);
4493 }
4494
4495 void
4496 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4497 {
4498         return;
4499 }
4500
4501 /**
4502  * Get the hardware capabilities, which will be parsed
4503  * and saved into struct i40e_hw.
4504  */
4505 static int
4506 i40e_get_cap(struct i40e_hw *hw)
4507 {
4508         struct i40e_aqc_list_capabilities_element_resp *buf;
4509         uint16_t len, size = 0;
4510         int ret;
4511
4512         /* Calculate a huge enough buff for saving response data temporarily */
4513         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4514                                                 I40E_MAX_CAP_ELE_NUM;
4515         buf = rte_zmalloc("i40e", len, 0);
4516         if (!buf) {
4517                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4518                 return I40E_ERR_NO_MEMORY;
4519         }
4520
4521         /* Get, parse the capabilities and save it to hw */
4522         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4523                         i40e_aqc_opc_list_func_capabilities, NULL);
4524         if (ret != I40E_SUCCESS)
4525                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4526
4527         /* Free the temporary buffer after being used */
4528         rte_free(buf);
4529
4530         return ret;
4531 }
4532
4533 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4534
4535 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4536                 const char *value,
4537                 void *opaque)
4538 {
4539         struct i40e_pf *pf;
4540         unsigned long num;
4541         char *end;
4542
4543         pf = (struct i40e_pf *)opaque;
4544         RTE_SET_USED(key);
4545
4546         errno = 0;
4547         num = strtoul(value, &end, 0);
4548         if (errno != 0 || end == value || *end != 0) {
4549                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4550                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4551                 return -(EINVAL);
4552         }
4553
4554         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4555                 pf->vf_nb_qp_max = (uint16_t)num;
4556         else
4557                 /* here return 0 to make next valid same argument work */
4558                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4559                             "power of 2 and equal or less than 16 !, Now it is "
4560                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4561
4562         return 0;
4563 }
4564
4565 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4566 {
4567         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4568         struct rte_kvargs *kvlist;
4569         int kvargs_count;
4570
4571         /* set default queue number per VF as 4 */
4572         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4573
4574         if (dev->device->devargs == NULL)
4575                 return 0;
4576
4577         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4578         if (kvlist == NULL)
4579                 return -(EINVAL);
4580
4581         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4582         if (!kvargs_count) {
4583                 rte_kvargs_free(kvlist);
4584                 return 0;
4585         }
4586
4587         if (kvargs_count > 1)
4588                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4589                             "the first invalid or last valid one is used !",
4590                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4591
4592         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4593                            i40e_pf_parse_vf_queue_number_handler, pf);
4594
4595         rte_kvargs_free(kvlist);
4596
4597         return 0;
4598 }
4599
4600 static int
4601 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4602 {
4603         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4604         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4605         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4606         uint16_t qp_count = 0, vsi_count = 0;
4607
4608         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4609                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4610                 return -EINVAL;
4611         }
4612
4613         i40e_pf_config_vf_rxq_number(dev);
4614
4615         /* Add the parameter init for LFC */
4616         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4617         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4618         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4619
4620         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4621         pf->max_num_vsi = hw->func_caps.num_vsis;
4622         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4623         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4624
4625         /* FDir queue/VSI allocation */
4626         pf->fdir_qp_offset = 0;
4627         if (hw->func_caps.fd) {
4628                 pf->flags |= I40E_FLAG_FDIR;
4629                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4630         } else {
4631                 pf->fdir_nb_qps = 0;
4632         }
4633         qp_count += pf->fdir_nb_qps;
4634         vsi_count += 1;
4635
4636         /* LAN queue/VSI allocation */
4637         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4638         if (!hw->func_caps.rss) {
4639                 pf->lan_nb_qps = 1;
4640         } else {
4641                 pf->flags |= I40E_FLAG_RSS;
4642                 if (hw->mac.type == I40E_MAC_X722)
4643                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4644                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4645         }
4646         qp_count += pf->lan_nb_qps;
4647         vsi_count += 1;
4648
4649         /* VF queue/VSI allocation */
4650         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4651         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4652                 pf->flags |= I40E_FLAG_SRIOV;
4653                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4654                 pf->vf_num = pci_dev->max_vfs;
4655                 PMD_DRV_LOG(DEBUG,
4656                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4657                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4658         } else {
4659                 pf->vf_nb_qps = 0;
4660                 pf->vf_num = 0;
4661         }
4662         qp_count += pf->vf_nb_qps * pf->vf_num;
4663         vsi_count += pf->vf_num;
4664
4665         /* VMDq queue/VSI allocation */
4666         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4667         pf->vmdq_nb_qps = 0;
4668         pf->max_nb_vmdq_vsi = 0;
4669         if (hw->func_caps.vmdq) {
4670                 if (qp_count < hw->func_caps.num_tx_qp &&
4671                         vsi_count < hw->func_caps.num_vsis) {
4672                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4673                                 qp_count) / pf->vmdq_nb_qp_max;
4674
4675                         /* Limit the maximum number of VMDq vsi to the maximum
4676                          * ethdev can support
4677                          */
4678                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4679                                 hw->func_caps.num_vsis - vsi_count);
4680                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4681                                 ETH_64_POOLS);
4682                         if (pf->max_nb_vmdq_vsi) {
4683                                 pf->flags |= I40E_FLAG_VMDQ;
4684                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4685                                 PMD_DRV_LOG(DEBUG,
4686                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4687                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4688                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4689                         } else {
4690                                 PMD_DRV_LOG(INFO,
4691                                         "No enough queues left for VMDq");
4692                         }
4693                 } else {
4694                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4695                 }
4696         }
4697         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4698         vsi_count += pf->max_nb_vmdq_vsi;
4699
4700         if (hw->func_caps.dcb)
4701                 pf->flags |= I40E_FLAG_DCB;
4702
4703         if (qp_count > hw->func_caps.num_tx_qp) {
4704                 PMD_DRV_LOG(ERR,
4705                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4706                         qp_count, hw->func_caps.num_tx_qp);
4707                 return -EINVAL;
4708         }
4709         if (vsi_count > hw->func_caps.num_vsis) {
4710                 PMD_DRV_LOG(ERR,
4711                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4712                         vsi_count, hw->func_caps.num_vsis);
4713                 return -EINVAL;
4714         }
4715
4716         return 0;
4717 }
4718
4719 static int
4720 i40e_pf_get_switch_config(struct i40e_pf *pf)
4721 {
4722         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4723         struct i40e_aqc_get_switch_config_resp *switch_config;
4724         struct i40e_aqc_switch_config_element_resp *element;
4725         uint16_t start_seid = 0, num_reported;
4726         int ret;
4727
4728         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4729                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4730         if (!switch_config) {
4731                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4732                 return -ENOMEM;
4733         }
4734
4735         /* Get the switch configurations */
4736         ret = i40e_aq_get_switch_config(hw, switch_config,
4737                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4738         if (ret != I40E_SUCCESS) {
4739                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4740                 goto fail;
4741         }
4742         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4743         if (num_reported != 1) { /* The number should be 1 */
4744                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4745                 goto fail;
4746         }
4747
4748         /* Parse the switch configuration elements */
4749         element = &(switch_config->element[0]);
4750         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4751                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4752                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4753         } else
4754                 PMD_DRV_LOG(INFO, "Unknown element type");
4755
4756 fail:
4757         rte_free(switch_config);
4758
4759         return ret;
4760 }
4761
4762 static int
4763 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4764                         uint32_t num)
4765 {
4766         struct pool_entry *entry;
4767
4768         if (pool == NULL || num == 0)
4769                 return -EINVAL;
4770
4771         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4772         if (entry == NULL) {
4773                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4774                 return -ENOMEM;
4775         }
4776
4777         /* queue heap initialize */
4778         pool->num_free = num;
4779         pool->num_alloc = 0;
4780         pool->base = base;
4781         LIST_INIT(&pool->alloc_list);
4782         LIST_INIT(&pool->free_list);
4783
4784         /* Initialize element  */
4785         entry->base = 0;
4786         entry->len = num;
4787
4788         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4789         return 0;
4790 }
4791
4792 static void
4793 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4794 {
4795         struct pool_entry *entry, *next_entry;
4796
4797         if (pool == NULL)
4798                 return;
4799
4800         for (entry = LIST_FIRST(&pool->alloc_list);
4801                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4802                         entry = next_entry) {
4803                 LIST_REMOVE(entry, next);
4804                 rte_free(entry);
4805         }
4806
4807         for (entry = LIST_FIRST(&pool->free_list);
4808                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4809                         entry = next_entry) {
4810                 LIST_REMOVE(entry, next);
4811                 rte_free(entry);
4812         }
4813
4814         pool->num_free = 0;
4815         pool->num_alloc = 0;
4816         pool->base = 0;
4817         LIST_INIT(&pool->alloc_list);
4818         LIST_INIT(&pool->free_list);
4819 }
4820
4821 static int
4822 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4823                        uint32_t base)
4824 {
4825         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4826         uint32_t pool_offset;
4827         int insert;
4828
4829         if (pool == NULL) {
4830                 PMD_DRV_LOG(ERR, "Invalid parameter");
4831                 return -EINVAL;
4832         }
4833
4834         pool_offset = base - pool->base;
4835         /* Lookup in alloc list */
4836         LIST_FOREACH(entry, &pool->alloc_list, next) {
4837                 if (entry->base == pool_offset) {
4838                         valid_entry = entry;
4839                         LIST_REMOVE(entry, next);
4840                         break;
4841                 }
4842         }
4843
4844         /* Not find, return */
4845         if (valid_entry == NULL) {
4846                 PMD_DRV_LOG(ERR, "Failed to find entry");
4847                 return -EINVAL;
4848         }
4849
4850         /**
4851          * Found it, move it to free list  and try to merge.
4852          * In order to make merge easier, always sort it by qbase.
4853          * Find adjacent prev and last entries.
4854          */
4855         prev = next = NULL;
4856         LIST_FOREACH(entry, &pool->free_list, next) {
4857                 if (entry->base > valid_entry->base) {
4858                         next = entry;
4859                         break;
4860                 }
4861                 prev = entry;
4862         }
4863
4864         insert = 0;
4865         /* Try to merge with next one*/
4866         if (next != NULL) {
4867                 /* Merge with next one */
4868                 if (valid_entry->base + valid_entry->len == next->base) {
4869                         next->base = valid_entry->base;
4870                         next->len += valid_entry->len;
4871                         rte_free(valid_entry);
4872                         valid_entry = next;
4873                         insert = 1;
4874                 }
4875         }
4876
4877         if (prev != NULL) {
4878                 /* Merge with previous one */
4879                 if (prev->base + prev->len == valid_entry->base) {
4880                         prev->len += valid_entry->len;
4881                         /* If it merge with next one, remove next node */
4882                         if (insert == 1) {
4883                                 LIST_REMOVE(valid_entry, next);
4884                                 rte_free(valid_entry);
4885                         } else {
4886                                 rte_free(valid_entry);
4887                                 insert = 1;
4888                         }
4889                 }
4890         }
4891
4892         /* Not find any entry to merge, insert */
4893         if (insert == 0) {
4894                 if (prev != NULL)
4895                         LIST_INSERT_AFTER(prev, valid_entry, next);
4896                 else if (next != NULL)
4897                         LIST_INSERT_BEFORE(next, valid_entry, next);
4898                 else /* It's empty list, insert to head */
4899                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4900         }
4901
4902         pool->num_free += valid_entry->len;
4903         pool->num_alloc -= valid_entry->len;
4904
4905         return 0;
4906 }
4907
4908 static int
4909 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4910                        uint16_t num)
4911 {
4912         struct pool_entry *entry, *valid_entry;
4913
4914         if (pool == NULL || num == 0) {
4915                 PMD_DRV_LOG(ERR, "Invalid parameter");
4916                 return -EINVAL;
4917         }
4918
4919         if (pool->num_free < num) {
4920                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4921                             num, pool->num_free);
4922                 return -ENOMEM;
4923         }
4924
4925         valid_entry = NULL;
4926         /* Lookup  in free list and find most fit one */
4927         LIST_FOREACH(entry, &pool->free_list, next) {
4928                 if (entry->len >= num) {
4929                         /* Find best one */
4930                         if (entry->len == num) {
4931                                 valid_entry = entry;
4932                                 break;
4933                         }
4934                         if (valid_entry == NULL || valid_entry->len > entry->len)
4935                                 valid_entry = entry;
4936                 }
4937         }
4938
4939         /* Not find one to satisfy the request, return */
4940         if (valid_entry == NULL) {
4941                 PMD_DRV_LOG(ERR, "No valid entry found");
4942                 return -ENOMEM;
4943         }
4944         /**
4945          * The entry have equal queue number as requested,
4946          * remove it from alloc_list.
4947          */
4948         if (valid_entry->len == num) {
4949                 LIST_REMOVE(valid_entry, next);
4950         } else {
4951                 /**
4952                  * The entry have more numbers than requested,
4953                  * create a new entry for alloc_list and minus its
4954                  * queue base and number in free_list.
4955                  */
4956                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4957                 if (entry == NULL) {
4958                         PMD_DRV_LOG(ERR,
4959                                 "Failed to allocate memory for resource pool");
4960                         return -ENOMEM;
4961                 }
4962                 entry->base = valid_entry->base;
4963                 entry->len = num;
4964                 valid_entry->base += num;
4965                 valid_entry->len -= num;
4966                 valid_entry = entry;
4967         }
4968
4969         /* Insert it into alloc list, not sorted */
4970         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4971
4972         pool->num_free -= valid_entry->len;
4973         pool->num_alloc += valid_entry->len;
4974
4975         return valid_entry->base + pool->base;
4976 }
4977
4978 /**
4979  * bitmap_is_subset - Check whether src2 is subset of src1
4980  **/
4981 static inline int
4982 bitmap_is_subset(uint8_t src1, uint8_t src2)
4983 {
4984         return !((src1 ^ src2) & src2);
4985 }
4986
4987 static enum i40e_status_code
4988 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4989 {
4990         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4991
4992         /* If DCB is not supported, only default TC is supported */
4993         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4994                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4995                 return I40E_NOT_SUPPORTED;
4996         }
4997
4998         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4999                 PMD_DRV_LOG(ERR,
5000                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5001                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5002                 return I40E_NOT_SUPPORTED;
5003         }
5004         return I40E_SUCCESS;
5005 }
5006
5007 int
5008 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5009                                 struct i40e_vsi_vlan_pvid_info *info)
5010 {
5011         struct i40e_hw *hw;
5012         struct i40e_vsi_context ctxt;
5013         uint8_t vlan_flags = 0;
5014         int ret;
5015
5016         if (vsi == NULL || info == NULL) {
5017                 PMD_DRV_LOG(ERR, "invalid parameters");
5018                 return I40E_ERR_PARAM;
5019         }
5020
5021         if (info->on) {
5022                 vsi->info.pvid = info->config.pvid;
5023                 /**
5024                  * If insert pvid is enabled, only tagged pkts are
5025                  * allowed to be sent out.
5026                  */
5027                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5028                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5029         } else {
5030                 vsi->info.pvid = 0;
5031                 if (info->config.reject.tagged == 0)
5032                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5033
5034                 if (info->config.reject.untagged == 0)
5035                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5036         }
5037         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5038                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5039         vsi->info.port_vlan_flags |= vlan_flags;
5040         vsi->info.valid_sections =
5041                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5042         memset(&ctxt, 0, sizeof(ctxt));
5043         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5044         ctxt.seid = vsi->seid;
5045
5046         hw = I40E_VSI_TO_HW(vsi);
5047         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5048         if (ret != I40E_SUCCESS)
5049                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5050
5051         return ret;
5052 }
5053
5054 static int
5055 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5056 {
5057         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5058         int i, ret;
5059         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5060
5061         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5062         if (ret != I40E_SUCCESS)
5063                 return ret;
5064
5065         if (!vsi->seid) {
5066                 PMD_DRV_LOG(ERR, "seid not valid");
5067                 return -EINVAL;
5068         }
5069
5070         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5071         tc_bw_data.tc_valid_bits = enabled_tcmap;
5072         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5073                 tc_bw_data.tc_bw_credits[i] =
5074                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5075
5076         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5077         if (ret != I40E_SUCCESS) {
5078                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5079                 return ret;
5080         }
5081
5082         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5083                                         sizeof(vsi->info.qs_handle));
5084         return I40E_SUCCESS;
5085 }
5086
5087 static enum i40e_status_code
5088 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5089                                  struct i40e_aqc_vsi_properties_data *info,
5090                                  uint8_t enabled_tcmap)
5091 {
5092         enum i40e_status_code ret;
5093         int i, total_tc = 0;
5094         uint16_t qpnum_per_tc, bsf, qp_idx;
5095
5096         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5097         if (ret != I40E_SUCCESS)
5098                 return ret;
5099
5100         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5101                 if (enabled_tcmap & (1 << i))
5102                         total_tc++;
5103         if (total_tc == 0)
5104                 total_tc = 1;
5105         vsi->enabled_tc = enabled_tcmap;
5106
5107         /* Number of queues per enabled TC */
5108         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5109         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5110         bsf = rte_bsf32(qpnum_per_tc);
5111
5112         /* Adjust the queue number to actual queues that can be applied */
5113         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5114                 vsi->nb_qps = qpnum_per_tc * total_tc;
5115
5116         /**
5117          * Configure TC and queue mapping parameters, for enabled TC,
5118          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5119          * default queue will serve it.
5120          */
5121         qp_idx = 0;
5122         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5123                 if (vsi->enabled_tc & (1 << i)) {
5124                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5125                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5126                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5127                         qp_idx += qpnum_per_tc;
5128                 } else
5129                         info->tc_mapping[i] = 0;
5130         }
5131
5132         /* Associate queue number with VSI */
5133         if (vsi->type == I40E_VSI_SRIOV) {
5134                 info->mapping_flags |=
5135                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5136                 for (i = 0; i < vsi->nb_qps; i++)
5137                         info->queue_mapping[i] =
5138                                 rte_cpu_to_le_16(vsi->base_queue + i);
5139         } else {
5140                 info->mapping_flags |=
5141                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5142                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5143         }
5144         info->valid_sections |=
5145                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5146
5147         return I40E_SUCCESS;
5148 }
5149
5150 static int
5151 i40e_veb_release(struct i40e_veb *veb)
5152 {
5153         struct i40e_vsi *vsi;
5154         struct i40e_hw *hw;
5155
5156         if (veb == NULL)
5157                 return -EINVAL;
5158
5159         if (!TAILQ_EMPTY(&veb->head)) {
5160                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5161                 return -EACCES;
5162         }
5163         /* associate_vsi field is NULL for floating VEB */
5164         if (veb->associate_vsi != NULL) {
5165                 vsi = veb->associate_vsi;
5166                 hw = I40E_VSI_TO_HW(vsi);
5167
5168                 vsi->uplink_seid = veb->uplink_seid;
5169                 vsi->veb = NULL;
5170         } else {
5171                 veb->associate_pf->main_vsi->floating_veb = NULL;
5172                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5173         }
5174
5175         i40e_aq_delete_element(hw, veb->seid, NULL);
5176         rte_free(veb);
5177         return I40E_SUCCESS;
5178 }
5179
5180 /* Setup a veb */
5181 static struct i40e_veb *
5182 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5183 {
5184         struct i40e_veb *veb;
5185         int ret;
5186         struct i40e_hw *hw;
5187
5188         if (pf == NULL) {
5189                 PMD_DRV_LOG(ERR,
5190                             "veb setup failed, associated PF shouldn't null");
5191                 return NULL;
5192         }
5193         hw = I40E_PF_TO_HW(pf);
5194
5195         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5196         if (!veb) {
5197                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5198                 goto fail;
5199         }
5200
5201         veb->associate_vsi = vsi;
5202         veb->associate_pf = pf;
5203         TAILQ_INIT(&veb->head);
5204         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5205
5206         /* create floating veb if vsi is NULL */
5207         if (vsi != NULL) {
5208                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5209                                       I40E_DEFAULT_TCMAP, false,
5210                                       &veb->seid, false, NULL);
5211         } else {
5212                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5213                                       true, &veb->seid, false, NULL);
5214         }
5215
5216         if (ret != I40E_SUCCESS) {
5217                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5218                             hw->aq.asq_last_status);
5219                 goto fail;
5220         }
5221         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5222
5223         /* get statistics index */
5224         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5225                                 &veb->stats_idx, NULL, NULL, NULL);
5226         if (ret != I40E_SUCCESS) {
5227                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5228                             hw->aq.asq_last_status);
5229                 goto fail;
5230         }
5231         /* Get VEB bandwidth, to be implemented */
5232         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5233         if (vsi)
5234                 vsi->uplink_seid = veb->seid;
5235
5236         return veb;
5237 fail:
5238         rte_free(veb);
5239         return NULL;
5240 }
5241
5242 int
5243 i40e_vsi_release(struct i40e_vsi *vsi)
5244 {
5245         struct i40e_pf *pf;
5246         struct i40e_hw *hw;
5247         struct i40e_vsi_list *vsi_list;
5248         void *temp;
5249         int ret;
5250         struct i40e_mac_filter *f;
5251         uint16_t user_param;
5252
5253         if (!vsi)
5254                 return I40E_SUCCESS;
5255
5256         if (!vsi->adapter)
5257                 return -EFAULT;
5258
5259         user_param = vsi->user_param;
5260
5261         pf = I40E_VSI_TO_PF(vsi);
5262         hw = I40E_VSI_TO_HW(vsi);
5263
5264         /* VSI has child to attach, release child first */
5265         if (vsi->veb) {
5266                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5267                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5268                                 return -1;
5269                 }
5270                 i40e_veb_release(vsi->veb);
5271         }
5272
5273         if (vsi->floating_veb) {
5274                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5275                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5276                                 return -1;
5277                 }
5278         }
5279
5280         /* Remove all macvlan filters of the VSI */
5281         i40e_vsi_remove_all_macvlan_filter(vsi);
5282         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5283                 rte_free(f);
5284
5285         if (vsi->type != I40E_VSI_MAIN &&
5286             ((vsi->type != I40E_VSI_SRIOV) ||
5287             !pf->floating_veb_list[user_param])) {
5288                 /* Remove vsi from parent's sibling list */
5289                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5290                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5291                         return I40E_ERR_PARAM;
5292                 }
5293                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5294                                 &vsi->sib_vsi_list, list);
5295
5296                 /* Remove all switch element of the VSI */
5297                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5298                 if (ret != I40E_SUCCESS)
5299                         PMD_DRV_LOG(ERR, "Failed to delete element");
5300         }
5301
5302         if ((vsi->type == I40E_VSI_SRIOV) &&
5303             pf->floating_veb_list[user_param]) {
5304                 /* Remove vsi from parent's sibling list */
5305                 if (vsi->parent_vsi == NULL ||
5306                     vsi->parent_vsi->floating_veb == NULL) {
5307                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5308                         return I40E_ERR_PARAM;
5309                 }
5310                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5311                              &vsi->sib_vsi_list, list);
5312
5313                 /* Remove all switch element of the VSI */
5314                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5315                 if (ret != I40E_SUCCESS)
5316                         PMD_DRV_LOG(ERR, "Failed to delete element");
5317         }
5318
5319         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5320
5321         if (vsi->type != I40E_VSI_SRIOV)
5322                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5323         rte_free(vsi);
5324
5325         return I40E_SUCCESS;
5326 }
5327
5328 static int
5329 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5330 {
5331         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5332         struct i40e_aqc_remove_macvlan_element_data def_filter;
5333         struct i40e_mac_filter_info filter;
5334         int ret;
5335
5336         if (vsi->type != I40E_VSI_MAIN)
5337                 return I40E_ERR_CONFIG;
5338         memset(&def_filter, 0, sizeof(def_filter));
5339         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5340                                         ETH_ADDR_LEN);
5341         def_filter.vlan_tag = 0;
5342         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5343                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5344         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5345         if (ret != I40E_SUCCESS) {
5346                 struct i40e_mac_filter *f;
5347                 struct rte_ether_addr *mac;
5348
5349                 PMD_DRV_LOG(DEBUG,
5350                             "Cannot remove the default macvlan filter");
5351                 /* It needs to add the permanent mac into mac list */
5352                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5353                 if (f == NULL) {
5354                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5355                         return I40E_ERR_NO_MEMORY;
5356                 }
5357                 mac = &f->mac_info.mac_addr;
5358                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5359                                 ETH_ADDR_LEN);
5360                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5361                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5362                 vsi->mac_num++;
5363
5364                 return ret;
5365         }
5366         rte_memcpy(&filter.mac_addr,
5367                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5368         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5369         return i40e_vsi_add_mac(vsi, &filter);
5370 }
5371
5372 /*
5373  * i40e_vsi_get_bw_config - Query VSI BW Information
5374  * @vsi: the VSI to be queried
5375  *
5376  * Returns 0 on success, negative value on failure
5377  */
5378 static enum i40e_status_code
5379 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5380 {
5381         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5382         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5383         struct i40e_hw *hw = &vsi->adapter->hw;
5384         i40e_status ret;
5385         int i;
5386         uint32_t bw_max;
5387
5388         memset(&bw_config, 0, sizeof(bw_config));
5389         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5390         if (ret != I40E_SUCCESS) {
5391                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5392                             hw->aq.asq_last_status);
5393                 return ret;
5394         }
5395
5396         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5397         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5398                                         &ets_sla_config, NULL);
5399         if (ret != I40E_SUCCESS) {
5400                 PMD_DRV_LOG(ERR,
5401                         "VSI failed to get TC bandwdith configuration %u",
5402                         hw->aq.asq_last_status);
5403                 return ret;
5404         }
5405
5406         /* store and print out BW info */
5407         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5408         vsi->bw_info.bw_max = bw_config.max_bw;
5409         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5410         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5411         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5412                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5413                      I40E_16_BIT_WIDTH);
5414         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5415                 vsi->bw_info.bw_ets_share_credits[i] =
5416                                 ets_sla_config.share_credits[i];
5417                 vsi->bw_info.bw_ets_credits[i] =
5418                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5419                 /* 4 bits per TC, 4th bit is reserved */
5420                 vsi->bw_info.bw_ets_max[i] =
5421                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5422                                   RTE_LEN2MASK(3, uint8_t));
5423                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5424                             vsi->bw_info.bw_ets_share_credits[i]);
5425                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5426                             vsi->bw_info.bw_ets_credits[i]);
5427                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5428                             vsi->bw_info.bw_ets_max[i]);
5429         }
5430
5431         return I40E_SUCCESS;
5432 }
5433
5434 /* i40e_enable_pf_lb
5435  * @pf: pointer to the pf structure
5436  *
5437  * allow loopback on pf
5438  */
5439 static inline void
5440 i40e_enable_pf_lb(struct i40e_pf *pf)
5441 {
5442         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5443         struct i40e_vsi_context ctxt;
5444         int ret;
5445
5446         /* Use the FW API if FW >= v5.0 */
5447         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5448                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5449                 return;
5450         }
5451
5452         memset(&ctxt, 0, sizeof(ctxt));
5453         ctxt.seid = pf->main_vsi_seid;
5454         ctxt.pf_num = hw->pf_id;
5455         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5456         if (ret) {
5457                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5458                             ret, hw->aq.asq_last_status);
5459                 return;
5460         }
5461         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5462         ctxt.info.valid_sections =
5463                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5464         ctxt.info.switch_id |=
5465                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5466
5467         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5468         if (ret)
5469                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5470                             hw->aq.asq_last_status);
5471 }
5472
5473 /* Setup a VSI */
5474 struct i40e_vsi *
5475 i40e_vsi_setup(struct i40e_pf *pf,
5476                enum i40e_vsi_type type,
5477                struct i40e_vsi *uplink_vsi,
5478                uint16_t user_param)
5479 {
5480         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5481         struct i40e_vsi *vsi;
5482         struct i40e_mac_filter_info filter;
5483         int ret;
5484         struct i40e_vsi_context ctxt;
5485         struct rte_ether_addr broadcast =
5486                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5487
5488         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5489             uplink_vsi == NULL) {
5490                 PMD_DRV_LOG(ERR,
5491                         "VSI setup failed, VSI link shouldn't be NULL");
5492                 return NULL;
5493         }
5494
5495         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5496                 PMD_DRV_LOG(ERR,
5497                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5498                 return NULL;
5499         }
5500
5501         /* two situations
5502          * 1.type is not MAIN and uplink vsi is not NULL
5503          * If uplink vsi didn't setup VEB, create one first under veb field
5504          * 2.type is SRIOV and the uplink is NULL
5505          * If floating VEB is NULL, create one veb under floating veb field
5506          */
5507
5508         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5509             uplink_vsi->veb == NULL) {
5510                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5511
5512                 if (uplink_vsi->veb == NULL) {
5513                         PMD_DRV_LOG(ERR, "VEB setup failed");
5514                         return NULL;
5515                 }
5516                 /* set ALLOWLOOPBACk on pf, when veb is created */
5517                 i40e_enable_pf_lb(pf);
5518         }
5519
5520         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5521             pf->main_vsi->floating_veb == NULL) {
5522                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5523
5524                 if (pf->main_vsi->floating_veb == NULL) {
5525                         PMD_DRV_LOG(ERR, "VEB setup failed");
5526                         return NULL;
5527                 }
5528         }
5529
5530         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5531         if (!vsi) {
5532                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5533                 return NULL;
5534         }
5535         TAILQ_INIT(&vsi->mac_list);
5536         vsi->type = type;
5537         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5538         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5539         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5540         vsi->user_param = user_param;
5541         vsi->vlan_anti_spoof_on = 0;
5542         vsi->vlan_filter_on = 0;
5543         /* Allocate queues */
5544         switch (vsi->type) {
5545         case I40E_VSI_MAIN  :
5546                 vsi->nb_qps = pf->lan_nb_qps;
5547                 break;
5548         case I40E_VSI_SRIOV :
5549                 vsi->nb_qps = pf->vf_nb_qps;
5550                 break;
5551         case I40E_VSI_VMDQ2:
5552                 vsi->nb_qps = pf->vmdq_nb_qps;
5553                 break;
5554         case I40E_VSI_FDIR:
5555                 vsi->nb_qps = pf->fdir_nb_qps;
5556                 break;
5557         default:
5558                 goto fail_mem;
5559         }
5560         /*
5561          * The filter status descriptor is reported in rx queue 0,
5562          * while the tx queue for fdir filter programming has no
5563          * such constraints, can be non-zero queues.
5564          * To simplify it, choose FDIR vsi use queue 0 pair.
5565          * To make sure it will use queue 0 pair, queue allocation
5566          * need be done before this function is called
5567          */
5568         if (type != I40E_VSI_FDIR) {
5569                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5570                         if (ret < 0) {
5571                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5572                                                 vsi->seid, ret);
5573                                 goto fail_mem;
5574                         }
5575                         vsi->base_queue = ret;
5576         } else
5577                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5578
5579         /* VF has MSIX interrupt in VF range, don't allocate here */
5580         if (type == I40E_VSI_MAIN) {
5581                 if (pf->support_multi_driver) {
5582                         /* If support multi-driver, need to use INT0 instead of
5583                          * allocating from msix pool. The Msix pool is init from
5584                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5585                          * to 1 without calling i40e_res_pool_alloc.
5586                          */
5587                         vsi->msix_intr = 0;
5588                         vsi->nb_msix = 1;
5589                 } else {
5590                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5591                                                   RTE_MIN(vsi->nb_qps,
5592                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5593                         if (ret < 0) {
5594                                 PMD_DRV_LOG(ERR,
5595                                             "VSI MAIN %d get heap failed %d",
5596                                             vsi->seid, ret);
5597                                 goto fail_queue_alloc;
5598                         }
5599                         vsi->msix_intr = ret;
5600                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5601                                                RTE_MAX_RXTX_INTR_VEC_ID);
5602                 }
5603         } else if (type != I40E_VSI_SRIOV) {
5604                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5605                 if (ret < 0) {
5606                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5607                         goto fail_queue_alloc;
5608                 }
5609                 vsi->msix_intr = ret;
5610                 vsi->nb_msix = 1;
5611         } else {
5612                 vsi->msix_intr = 0;
5613                 vsi->nb_msix = 0;
5614         }
5615
5616         /* Add VSI */
5617         if (type == I40E_VSI_MAIN) {
5618                 /* For main VSI, no need to add since it's default one */
5619                 vsi->uplink_seid = pf->mac_seid;
5620                 vsi->seid = pf->main_vsi_seid;
5621                 /* Bind queues with specific MSIX interrupt */
5622                 /**
5623                  * Needs 2 interrupt at least, one for misc cause which will
5624                  * enabled from OS side, Another for queues binding the
5625                  * interrupt from device side only.
5626                  */
5627
5628                 /* Get default VSI parameters from hardware */
5629                 memset(&ctxt, 0, sizeof(ctxt));
5630                 ctxt.seid = vsi->seid;
5631                 ctxt.pf_num = hw->pf_id;
5632                 ctxt.uplink_seid = vsi->uplink_seid;
5633                 ctxt.vf_num = 0;
5634                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5635                 if (ret != I40E_SUCCESS) {
5636                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5637                         goto fail_msix_alloc;
5638                 }
5639                 rte_memcpy(&vsi->info, &ctxt.info,
5640                         sizeof(struct i40e_aqc_vsi_properties_data));
5641                 vsi->vsi_id = ctxt.vsi_number;
5642                 vsi->info.valid_sections = 0;
5643
5644                 /* Configure tc, enabled TC0 only */
5645                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5646                         I40E_SUCCESS) {
5647                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5648                         goto fail_msix_alloc;
5649                 }
5650
5651                 /* TC, queue mapping */
5652                 memset(&ctxt, 0, sizeof(ctxt));
5653                 vsi->info.valid_sections |=
5654                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5655                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5656                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5657                 rte_memcpy(&ctxt.info, &vsi->info,
5658                         sizeof(struct i40e_aqc_vsi_properties_data));
5659                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5660                                                 I40E_DEFAULT_TCMAP);
5661                 if (ret != I40E_SUCCESS) {
5662                         PMD_DRV_LOG(ERR,
5663                                 "Failed to configure TC queue mapping");
5664                         goto fail_msix_alloc;
5665                 }
5666                 ctxt.seid = vsi->seid;
5667                 ctxt.pf_num = hw->pf_id;
5668                 ctxt.uplink_seid = vsi->uplink_seid;
5669                 ctxt.vf_num = 0;
5670
5671                 /* Update VSI parameters */
5672                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5673                 if (ret != I40E_SUCCESS) {
5674                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5675                         goto fail_msix_alloc;
5676                 }
5677
5678                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5679                                                 sizeof(vsi->info.tc_mapping));
5680                 rte_memcpy(&vsi->info.queue_mapping,
5681                                 &ctxt.info.queue_mapping,
5682                         sizeof(vsi->info.queue_mapping));
5683                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5684                 vsi->info.valid_sections = 0;
5685
5686                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5687                                 ETH_ADDR_LEN);
5688
5689                 /**
5690                  * Updating default filter settings are necessary to prevent
5691                  * reception of tagged packets.
5692                  * Some old firmware configurations load a default macvlan
5693                  * filter which accepts both tagged and untagged packets.
5694                  * The updating is to use a normal filter instead if needed.
5695                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5696                  * The firmware with correct configurations load the default
5697                  * macvlan filter which is expected and cannot be removed.
5698                  */
5699                 i40e_update_default_filter_setting(vsi);
5700                 i40e_config_qinq(hw, vsi);
5701         } else if (type == I40E_VSI_SRIOV) {
5702                 memset(&ctxt, 0, sizeof(ctxt));
5703                 /**
5704                  * For other VSI, the uplink_seid equals to uplink VSI's
5705                  * uplink_seid since they share same VEB
5706                  */
5707                 if (uplink_vsi == NULL)
5708                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5709                 else
5710                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5711                 ctxt.pf_num = hw->pf_id;
5712                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5713                 ctxt.uplink_seid = vsi->uplink_seid;
5714                 ctxt.connection_type = 0x1;
5715                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5716
5717                 /* Use the VEB configuration if FW >= v5.0 */
5718                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5719                         /* Configure switch ID */
5720                         ctxt.info.valid_sections |=
5721                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5722                         ctxt.info.switch_id =
5723                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5724                 }
5725
5726                 /* Configure port/vlan */
5727                 ctxt.info.valid_sections |=
5728                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5729                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5730                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5731                                                 hw->func_caps.enabled_tcmap);
5732                 if (ret != I40E_SUCCESS) {
5733                         PMD_DRV_LOG(ERR,
5734                                 "Failed to configure TC queue mapping");
5735                         goto fail_msix_alloc;
5736                 }
5737
5738                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5739                 ctxt.info.valid_sections |=
5740                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5741                 /**
5742                  * Since VSI is not created yet, only configure parameter,
5743                  * will add vsi below.
5744                  */
5745
5746                 i40e_config_qinq(hw, vsi);
5747         } else if (type == I40E_VSI_VMDQ2) {
5748                 memset(&ctxt, 0, sizeof(ctxt));
5749                 /*
5750                  * For other VSI, the uplink_seid equals to uplink VSI's
5751                  * uplink_seid since they share same VEB
5752                  */
5753                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5754                 ctxt.pf_num = hw->pf_id;
5755                 ctxt.vf_num = 0;
5756                 ctxt.uplink_seid = vsi->uplink_seid;
5757                 ctxt.connection_type = 0x1;
5758                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5759
5760                 ctxt.info.valid_sections |=
5761                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5762                 /* user_param carries flag to enable loop back */
5763                 if (user_param) {
5764                         ctxt.info.switch_id =
5765                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5766                         ctxt.info.switch_id |=
5767                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5768                 }
5769
5770                 /* Configure port/vlan */
5771                 ctxt.info.valid_sections |=
5772                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5773                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5774                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5775                                                 I40E_DEFAULT_TCMAP);
5776                 if (ret != I40E_SUCCESS) {
5777                         PMD_DRV_LOG(ERR,
5778                                 "Failed to configure TC queue mapping");
5779                         goto fail_msix_alloc;
5780                 }
5781                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5782                 ctxt.info.valid_sections |=
5783                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5784         } else if (type == I40E_VSI_FDIR) {
5785                 memset(&ctxt, 0, sizeof(ctxt));
5786                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5787                 ctxt.pf_num = hw->pf_id;
5788                 ctxt.vf_num = 0;
5789                 ctxt.uplink_seid = vsi->uplink_seid;
5790                 ctxt.connection_type = 0x1;     /* regular data port */
5791                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5792                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5793                                                 I40E_DEFAULT_TCMAP);
5794                 if (ret != I40E_SUCCESS) {
5795                         PMD_DRV_LOG(ERR,
5796                                 "Failed to configure TC queue mapping.");
5797                         goto fail_msix_alloc;
5798                 }
5799                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5800                 ctxt.info.valid_sections |=
5801                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5802         } else {
5803                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5804                 goto fail_msix_alloc;
5805         }
5806
5807         if (vsi->type != I40E_VSI_MAIN) {
5808                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5809                 if (ret != I40E_SUCCESS) {
5810                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5811                                     hw->aq.asq_last_status);
5812                         goto fail_msix_alloc;
5813                 }
5814                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5815                 vsi->info.valid_sections = 0;
5816                 vsi->seid = ctxt.seid;
5817                 vsi->vsi_id = ctxt.vsi_number;
5818                 vsi->sib_vsi_list.vsi = vsi;
5819                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5820                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5821                                           &vsi->sib_vsi_list, list);
5822                 } else {
5823                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5824                                           &vsi->sib_vsi_list, list);
5825                 }
5826         }
5827
5828         /* MAC/VLAN configuration */
5829         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5830         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5831
5832         ret = i40e_vsi_add_mac(vsi, &filter);
5833         if (ret != I40E_SUCCESS) {
5834                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5835                 goto fail_msix_alloc;
5836         }
5837
5838         /* Get VSI BW information */
5839         i40e_vsi_get_bw_config(vsi);
5840         return vsi;
5841 fail_msix_alloc:
5842         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5843 fail_queue_alloc:
5844         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5845 fail_mem:
5846         rte_free(vsi);
5847         return NULL;
5848 }
5849
5850 /* Configure vlan filter on or off */
5851 int
5852 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5853 {
5854         int i, num;
5855         struct i40e_mac_filter *f;
5856         void *temp;
5857         struct i40e_mac_filter_info *mac_filter;
5858         enum rte_mac_filter_type desired_filter;
5859         int ret = I40E_SUCCESS;
5860
5861         if (on) {
5862                 /* Filter to match MAC and VLAN */
5863                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5864         } else {
5865                 /* Filter to match only MAC */
5866                 desired_filter = RTE_MAC_PERFECT_MATCH;
5867         }
5868
5869         num = vsi->mac_num;
5870
5871         mac_filter = rte_zmalloc("mac_filter_info_data",
5872                                  num * sizeof(*mac_filter), 0);
5873         if (mac_filter == NULL) {
5874                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5875                 return I40E_ERR_NO_MEMORY;
5876         }
5877
5878         i = 0;
5879
5880         /* Remove all existing mac */
5881         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5882                 mac_filter[i] = f->mac_info;
5883                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5884                 if (ret) {
5885                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5886                                     on ? "enable" : "disable");
5887                         goto DONE;
5888                 }
5889                 i++;
5890         }
5891
5892         /* Override with new filter */
5893         for (i = 0; i < num; i++) {
5894                 mac_filter[i].filter_type = desired_filter;
5895                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5896                 if (ret) {
5897                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5898                                     on ? "enable" : "disable");
5899                         goto DONE;
5900                 }
5901         }
5902
5903 DONE:
5904         rte_free(mac_filter);
5905         return ret;
5906 }
5907
5908 /* Configure vlan stripping on or off */
5909 int
5910 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5911 {
5912         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5913         struct i40e_vsi_context ctxt;
5914         uint8_t vlan_flags;
5915         int ret = I40E_SUCCESS;
5916
5917         /* Check if it has been already on or off */
5918         if (vsi->info.valid_sections &
5919                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5920                 if (on) {
5921                         if ((vsi->info.port_vlan_flags &
5922                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5923                                 return 0; /* already on */
5924                 } else {
5925                         if ((vsi->info.port_vlan_flags &
5926                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5927                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5928                                 return 0; /* already off */
5929                 }
5930         }
5931
5932         if (on)
5933                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5934         else
5935                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5936         vsi->info.valid_sections =
5937                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5938         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5939         vsi->info.port_vlan_flags |= vlan_flags;
5940         ctxt.seid = vsi->seid;
5941         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5942         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5943         if (ret)
5944                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5945                             on ? "enable" : "disable");
5946
5947         return ret;
5948 }
5949
5950 static int
5951 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5952 {
5953         struct rte_eth_dev_data *data = dev->data;
5954         int ret;
5955         int mask = 0;
5956
5957         /* Apply vlan offload setting */
5958         mask = ETH_VLAN_STRIP_MASK |
5959                ETH_VLAN_FILTER_MASK |
5960                ETH_VLAN_EXTEND_MASK;
5961         ret = i40e_vlan_offload_set(dev, mask);
5962         if (ret) {
5963                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5964                 return ret;
5965         }
5966
5967         /* Apply pvid setting */
5968         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5969                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5970         if (ret)
5971                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5972
5973         return ret;
5974 }
5975
5976 static int
5977 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5978 {
5979         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5980
5981         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5982 }
5983
5984 static int
5985 i40e_update_flow_control(struct i40e_hw *hw)
5986 {
5987 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5988         struct i40e_link_status link_status;
5989         uint32_t rxfc = 0, txfc = 0, reg;
5990         uint8_t an_info;
5991         int ret;
5992
5993         memset(&link_status, 0, sizeof(link_status));
5994         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5995         if (ret != I40E_SUCCESS) {
5996                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5997                 goto write_reg; /* Disable flow control */
5998         }
5999
6000         an_info = hw->phy.link_info.an_info;
6001         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6002                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6003                 ret = I40E_ERR_NOT_READY;
6004                 goto write_reg; /* Disable flow control */
6005         }
6006         /**
6007          * If link auto negotiation is enabled, flow control needs to
6008          * be configured according to it
6009          */
6010         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6011         case I40E_LINK_PAUSE_RXTX:
6012                 rxfc = 1;
6013                 txfc = 1;
6014                 hw->fc.current_mode = I40E_FC_FULL;
6015                 break;
6016         case I40E_AQ_LINK_PAUSE_RX:
6017                 rxfc = 1;
6018                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6019                 break;
6020         case I40E_AQ_LINK_PAUSE_TX:
6021                 txfc = 1;
6022                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6023                 break;
6024         default:
6025                 hw->fc.current_mode = I40E_FC_NONE;
6026                 break;
6027         }
6028
6029 write_reg:
6030         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6031                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6032         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6033         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6034         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6035         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6036
6037         return ret;
6038 }
6039
6040 /* PF setup */
6041 static int
6042 i40e_pf_setup(struct i40e_pf *pf)
6043 {
6044         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6045         struct i40e_filter_control_settings settings;
6046         struct i40e_vsi *vsi;
6047         int ret;
6048
6049         /* Clear all stats counters */
6050         pf->offset_loaded = FALSE;
6051         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6052         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6053         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6054         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6055
6056         ret = i40e_pf_get_switch_config(pf);
6057         if (ret != I40E_SUCCESS) {
6058                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6059                 return ret;
6060         }
6061
6062         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6063         if (ret)
6064                 PMD_INIT_LOG(WARNING,
6065                         "failed to allocate switch domain for device %d", ret);
6066
6067         if (pf->flags & I40E_FLAG_FDIR) {
6068                 /* make queue allocated first, let FDIR use queue pair 0*/
6069                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6070                 if (ret != I40E_FDIR_QUEUE_ID) {
6071                         PMD_DRV_LOG(ERR,
6072                                 "queue allocation fails for FDIR: ret =%d",
6073                                 ret);
6074                         pf->flags &= ~I40E_FLAG_FDIR;
6075                 }
6076         }
6077         /*  main VSI setup */
6078         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6079         if (!vsi) {
6080                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6081                 return I40E_ERR_NOT_READY;
6082         }
6083         pf->main_vsi = vsi;
6084
6085         /* Configure filter control */
6086         memset(&settings, 0, sizeof(settings));
6087         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6088                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6089         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6090                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6091         else {
6092                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6093                         hw->func_caps.rss_table_size);
6094                 return I40E_ERR_PARAM;
6095         }
6096         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6097                 hw->func_caps.rss_table_size);
6098         pf->hash_lut_size = hw->func_caps.rss_table_size;
6099
6100         /* Enable ethtype and macvlan filters */
6101         settings.enable_ethtype = TRUE;
6102         settings.enable_macvlan = TRUE;
6103         ret = i40e_set_filter_control(hw, &settings);
6104         if (ret)
6105                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6106                                                                 ret);
6107
6108         /* Update flow control according to the auto negotiation */
6109         i40e_update_flow_control(hw);
6110
6111         return I40E_SUCCESS;
6112 }
6113
6114 int
6115 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6116 {
6117         uint32_t reg;
6118         uint16_t j;
6119
6120         /**
6121          * Set or clear TX Queue Disable flags,
6122          * which is required by hardware.
6123          */
6124         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6125         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6126
6127         /* Wait until the request is finished */
6128         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6129                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6130                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6131                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6132                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6133                                                         & 0x1))) {
6134                         break;
6135                 }
6136         }
6137         if (on) {
6138                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6139                         return I40E_SUCCESS; /* already on, skip next steps */
6140
6141                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6142                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6143         } else {
6144                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6145                         return I40E_SUCCESS; /* already off, skip next steps */
6146                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6147         }
6148         /* Write the register */
6149         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6150         /* Check the result */
6151         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6152                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6153                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6154                 if (on) {
6155                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6156                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6157                                 break;
6158                 } else {
6159                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6160                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6161                                 break;
6162                 }
6163         }
6164         /* Check if it is timeout */
6165         if (j >= I40E_CHK_Q_ENA_COUNT) {
6166                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6167                             (on ? "enable" : "disable"), q_idx);
6168                 return I40E_ERR_TIMEOUT;
6169         }
6170
6171         return I40E_SUCCESS;
6172 }
6173
6174 /* Swith on or off the tx queues */
6175 static int
6176 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6177 {
6178         struct rte_eth_dev_data *dev_data = pf->dev_data;
6179         struct i40e_tx_queue *txq;
6180         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6181         uint16_t i;
6182         int ret;
6183
6184         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6185                 txq = dev_data->tx_queues[i];
6186                 /* Don't operate the queue if not configured or
6187                  * if starting only per queue */
6188                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6189                         continue;
6190                 if (on)
6191                         ret = i40e_dev_tx_queue_start(dev, i);
6192                 else
6193                         ret = i40e_dev_tx_queue_stop(dev, i);
6194                 if ( ret != I40E_SUCCESS)
6195                         return ret;
6196         }
6197
6198         return I40E_SUCCESS;
6199 }
6200
6201 int
6202 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6203 {
6204         uint32_t reg;
6205         uint16_t j;
6206
6207         /* Wait until the request is finished */
6208         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6209                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6210                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6211                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6212                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6213                         break;
6214         }
6215
6216         if (on) {
6217                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6218                         return I40E_SUCCESS; /* Already on, skip next steps */
6219                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6220         } else {
6221                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6222                         return I40E_SUCCESS; /* Already off, skip next steps */
6223                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6224         }
6225
6226         /* Write the register */
6227         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6228         /* Check the result */
6229         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6230                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6231                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6232                 if (on) {
6233                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6234                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6235                                 break;
6236                 } else {
6237                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6238                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6239                                 break;
6240                 }
6241         }
6242
6243         /* Check if it is timeout */
6244         if (j >= I40E_CHK_Q_ENA_COUNT) {
6245                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6246                             (on ? "enable" : "disable"), q_idx);
6247                 return I40E_ERR_TIMEOUT;
6248         }
6249
6250         return I40E_SUCCESS;
6251 }
6252 /* Switch on or off the rx queues */
6253 static int
6254 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6255 {
6256         struct rte_eth_dev_data *dev_data = pf->dev_data;
6257         struct i40e_rx_queue *rxq;
6258         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6259         uint16_t i;
6260         int ret;
6261
6262         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6263                 rxq = dev_data->rx_queues[i];
6264                 /* Don't operate the queue if not configured or
6265                  * if starting only per queue */
6266                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6267                         continue;
6268                 if (on)
6269                         ret = i40e_dev_rx_queue_start(dev, i);
6270                 else
6271                         ret = i40e_dev_rx_queue_stop(dev, i);
6272                 if (ret != I40E_SUCCESS)
6273                         return ret;
6274         }
6275
6276         return I40E_SUCCESS;
6277 }
6278
6279 /* Switch on or off all the rx/tx queues */
6280 int
6281 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6282 {
6283         int ret;
6284
6285         if (on) {
6286                 /* enable rx queues before enabling tx queues */
6287                 ret = i40e_dev_switch_rx_queues(pf, on);
6288                 if (ret) {
6289                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6290                         return ret;
6291                 }
6292                 ret = i40e_dev_switch_tx_queues(pf, on);
6293         } else {
6294                 /* Stop tx queues before stopping rx queues */
6295                 ret = i40e_dev_switch_tx_queues(pf, on);
6296                 if (ret) {
6297                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6298                         return ret;
6299                 }
6300                 ret = i40e_dev_switch_rx_queues(pf, on);
6301         }
6302
6303         return ret;
6304 }
6305
6306 /* Initialize VSI for TX */
6307 static int
6308 i40e_dev_tx_init(struct i40e_pf *pf)
6309 {
6310         struct rte_eth_dev_data *data = pf->dev_data;
6311         uint16_t i;
6312         uint32_t ret = I40E_SUCCESS;
6313         struct i40e_tx_queue *txq;
6314
6315         for (i = 0; i < data->nb_tx_queues; i++) {
6316                 txq = data->tx_queues[i];
6317                 if (!txq || !txq->q_set)
6318                         continue;
6319                 ret = i40e_tx_queue_init(txq);
6320                 if (ret != I40E_SUCCESS)
6321                         break;
6322         }
6323         if (ret == I40E_SUCCESS)
6324                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6325                                      ->eth_dev);
6326
6327         return ret;
6328 }
6329
6330 /* Initialize VSI for RX */
6331 static int
6332 i40e_dev_rx_init(struct i40e_pf *pf)
6333 {
6334         struct rte_eth_dev_data *data = pf->dev_data;
6335         int ret = I40E_SUCCESS;
6336         uint16_t i;
6337         struct i40e_rx_queue *rxq;
6338
6339         i40e_pf_config_mq_rx(pf);
6340         for (i = 0; i < data->nb_rx_queues; i++) {
6341                 rxq = data->rx_queues[i];
6342                 if (!rxq || !rxq->q_set)
6343                         continue;
6344
6345                 ret = i40e_rx_queue_init(rxq);
6346                 if (ret != I40E_SUCCESS) {
6347                         PMD_DRV_LOG(ERR,
6348                                 "Failed to do RX queue initialization");
6349                         break;
6350                 }
6351         }
6352         if (ret == I40E_SUCCESS)
6353                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6354                                      ->eth_dev);
6355
6356         return ret;
6357 }
6358
6359 static int
6360 i40e_dev_rxtx_init(struct i40e_pf *pf)
6361 {
6362         int err;
6363
6364         err = i40e_dev_tx_init(pf);
6365         if (err) {
6366                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6367                 return err;
6368         }
6369         err = i40e_dev_rx_init(pf);
6370         if (err) {
6371                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6372                 return err;
6373         }
6374
6375         return err;
6376 }
6377
6378 static int
6379 i40e_vmdq_setup(struct rte_eth_dev *dev)
6380 {
6381         struct rte_eth_conf *conf = &dev->data->dev_conf;
6382         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6383         int i, err, conf_vsis, j, loop;
6384         struct i40e_vsi *vsi;
6385         struct i40e_vmdq_info *vmdq_info;
6386         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6387         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6388
6389         /*
6390          * Disable interrupt to avoid message from VF. Furthermore, it will
6391          * avoid race condition in VSI creation/destroy.
6392          */
6393         i40e_pf_disable_irq0(hw);
6394
6395         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6396                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6397                 return -ENOTSUP;
6398         }
6399
6400         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6401         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6402                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6403                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6404                         pf->max_nb_vmdq_vsi);
6405                 return -ENOTSUP;
6406         }
6407
6408         if (pf->vmdq != NULL) {
6409                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6410                 return 0;
6411         }
6412
6413         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6414                                 sizeof(*vmdq_info) * conf_vsis, 0);
6415
6416         if (pf->vmdq == NULL) {
6417                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6418                 return -ENOMEM;
6419         }
6420
6421         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6422
6423         /* Create VMDQ VSI */
6424         for (i = 0; i < conf_vsis; i++) {
6425                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6426                                 vmdq_conf->enable_loop_back);
6427                 if (vsi == NULL) {
6428                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6429                         err = -1;
6430                         goto err_vsi_setup;
6431                 }
6432                 vmdq_info = &pf->vmdq[i];
6433                 vmdq_info->pf = pf;
6434                 vmdq_info->vsi = vsi;
6435         }
6436         pf->nb_cfg_vmdq_vsi = conf_vsis;
6437
6438         /* Configure Vlan */
6439         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6440         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6441                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6442                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6443                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6444                                         vmdq_conf->pool_map[i].vlan_id, j);
6445
6446                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6447                                                 vmdq_conf->pool_map[i].vlan_id);
6448                                 if (err) {
6449                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6450                                         err = -1;
6451                                         goto err_vsi_setup;
6452                                 }
6453                         }
6454                 }
6455         }
6456
6457         i40e_pf_enable_irq0(hw);
6458
6459         return 0;
6460
6461 err_vsi_setup:
6462         for (i = 0; i < conf_vsis; i++)
6463                 if (pf->vmdq[i].vsi == NULL)
6464                         break;
6465                 else
6466                         i40e_vsi_release(pf->vmdq[i].vsi);
6467
6468         rte_free(pf->vmdq);
6469         pf->vmdq = NULL;
6470         i40e_pf_enable_irq0(hw);
6471         return err;
6472 }
6473
6474 static void
6475 i40e_stat_update_32(struct i40e_hw *hw,
6476                    uint32_t reg,
6477                    bool offset_loaded,
6478                    uint64_t *offset,
6479                    uint64_t *stat)
6480 {
6481         uint64_t new_data;
6482
6483         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6484         if (!offset_loaded)
6485                 *offset = new_data;
6486
6487         if (new_data >= *offset)
6488                 *stat = (uint64_t)(new_data - *offset);
6489         else
6490                 *stat = (uint64_t)((new_data +
6491                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6492 }
6493
6494 static void
6495 i40e_stat_update_48(struct i40e_hw *hw,
6496                    uint32_t hireg,
6497                    uint32_t loreg,
6498                    bool offset_loaded,
6499                    uint64_t *offset,
6500                    uint64_t *stat)
6501 {
6502         uint64_t new_data;
6503
6504         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6505         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6506                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6507
6508         if (!offset_loaded)
6509                 *offset = new_data;
6510
6511         if (new_data >= *offset)
6512                 *stat = new_data - *offset;
6513         else
6514                 *stat = (uint64_t)((new_data +
6515                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6516
6517         *stat &= I40E_48_BIT_MASK;
6518 }
6519
6520 /* Disable IRQ0 */
6521 void
6522 i40e_pf_disable_irq0(struct i40e_hw *hw)
6523 {
6524         /* Disable all interrupt types */
6525         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6526                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6527         I40E_WRITE_FLUSH(hw);
6528 }
6529
6530 /* Enable IRQ0 */
6531 void
6532 i40e_pf_enable_irq0(struct i40e_hw *hw)
6533 {
6534         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6535                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6536                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6537                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6538         I40E_WRITE_FLUSH(hw);
6539 }
6540
6541 static void
6542 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6543 {
6544         /* read pending request and disable first */
6545         i40e_pf_disable_irq0(hw);
6546         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6547         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6548                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6549
6550         if (no_queue)
6551                 /* Link no queues with irq0 */
6552                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6553                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6554 }
6555
6556 static void
6557 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6558 {
6559         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6560         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6561         int i;
6562         uint16_t abs_vf_id;
6563         uint32_t index, offset, val;
6564
6565         if (!pf->vfs)
6566                 return;
6567         /**
6568          * Try to find which VF trigger a reset, use absolute VF id to access
6569          * since the reg is global register.
6570          */
6571         for (i = 0; i < pf->vf_num; i++) {
6572                 abs_vf_id = hw->func_caps.vf_base_id + i;
6573                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6574                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6575                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6576                 /* VFR event occurred */
6577                 if (val & (0x1 << offset)) {
6578                         int ret;
6579
6580                         /* Clear the event first */
6581                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6582                                                         (0x1 << offset));
6583                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6584                         /**
6585                          * Only notify a VF reset event occurred,
6586                          * don't trigger another SW reset
6587                          */
6588                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6589                         if (ret != I40E_SUCCESS)
6590                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6591                 }
6592         }
6593 }
6594
6595 static void
6596 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6597 {
6598         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6599         int i;
6600
6601         for (i = 0; i < pf->vf_num; i++)
6602                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6603 }
6604
6605 static void
6606 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6607 {
6608         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6609         struct i40e_arq_event_info info;
6610         uint16_t pending, opcode;
6611         int ret;
6612
6613         info.buf_len = I40E_AQ_BUF_SZ;
6614         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6615         if (!info.msg_buf) {
6616                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6617                 return;
6618         }
6619
6620         pending = 1;
6621         while (pending) {
6622                 ret = i40e_clean_arq_element(hw, &info, &pending);
6623
6624                 if (ret != I40E_SUCCESS) {
6625                         PMD_DRV_LOG(INFO,
6626                                 "Failed to read msg from AdminQ, aq_err: %u",
6627                                 hw->aq.asq_last_status);
6628                         break;
6629                 }
6630                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6631
6632                 switch (opcode) {
6633                 case i40e_aqc_opc_send_msg_to_pf:
6634                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6635                         i40e_pf_host_handle_vf_msg(dev,
6636                                         rte_le_to_cpu_16(info.desc.retval),
6637                                         rte_le_to_cpu_32(info.desc.cookie_high),
6638                                         rte_le_to_cpu_32(info.desc.cookie_low),
6639                                         info.msg_buf,
6640                                         info.msg_len);
6641                         break;
6642                 case i40e_aqc_opc_get_link_status:
6643                         ret = i40e_dev_link_update(dev, 0);
6644                         if (!ret)
6645                                 _rte_eth_dev_callback_process(dev,
6646                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6647                         break;
6648                 default:
6649                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6650                                     opcode);
6651                         break;
6652                 }
6653         }
6654         rte_free(info.msg_buf);
6655 }
6656
6657 /**
6658  * Interrupt handler triggered by NIC  for handling
6659  * specific interrupt.
6660  *
6661  * @param handle
6662  *  Pointer to interrupt handle.
6663  * @param param
6664  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6665  *
6666  * @return
6667  *  void
6668  */
6669 static void
6670 i40e_dev_interrupt_handler(void *param)
6671 {
6672         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6673         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6674         uint32_t icr0;
6675
6676         /* Disable interrupt */
6677         i40e_pf_disable_irq0(hw);
6678
6679         /* read out interrupt causes */
6680         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6681
6682         /* No interrupt event indicated */
6683         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6684                 PMD_DRV_LOG(INFO, "No interrupt event");
6685                 goto done;
6686         }
6687         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6688                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6689         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6690                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6691         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6692                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6693         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6694                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6695         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6696                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6697         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6698                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6699         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6700                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6701
6702         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6703                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6704                 i40e_dev_handle_vfr_event(dev);
6705         }
6706         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6707                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6708                 i40e_dev_handle_aq_msg(dev);
6709         }
6710
6711 done:
6712         /* Enable interrupt */
6713         i40e_pf_enable_irq0(hw);
6714 }
6715
6716 static void
6717 i40e_dev_alarm_handler(void *param)
6718 {
6719         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6720         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6721         uint32_t icr0;
6722
6723         /* Disable interrupt */
6724         i40e_pf_disable_irq0(hw);
6725
6726         /* read out interrupt causes */
6727         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6728
6729         /* No interrupt event indicated */
6730         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6731                 goto done;
6732         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6733                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6734         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6735                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6736         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6737                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6738         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6739                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6740         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6741                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6742         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6743                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6744         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6745                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6746
6747         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6748                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6749                 i40e_dev_handle_vfr_event(dev);
6750         }
6751         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6752                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6753                 i40e_dev_handle_aq_msg(dev);
6754         }
6755
6756 done:
6757         /* Enable interrupt */
6758         i40e_pf_enable_irq0(hw);
6759         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6760                           i40e_dev_alarm_handler, dev);
6761 }
6762
6763 int
6764 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6765                          struct i40e_macvlan_filter *filter,
6766                          int total)
6767 {
6768         int ele_num, ele_buff_size;
6769         int num, actual_num, i;
6770         uint16_t flags;
6771         int ret = I40E_SUCCESS;
6772         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6773         struct i40e_aqc_add_macvlan_element_data *req_list;
6774
6775         if (filter == NULL  || total == 0)
6776                 return I40E_ERR_PARAM;
6777         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6778         ele_buff_size = hw->aq.asq_buf_size;
6779
6780         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6781         if (req_list == NULL) {
6782                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6783                 return I40E_ERR_NO_MEMORY;
6784         }
6785
6786         num = 0;
6787         do {
6788                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6789                 memset(req_list, 0, ele_buff_size);
6790
6791                 for (i = 0; i < actual_num; i++) {
6792                         rte_memcpy(req_list[i].mac_addr,
6793                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6794                         req_list[i].vlan_tag =
6795                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6796
6797                         switch (filter[num + i].filter_type) {
6798                         case RTE_MAC_PERFECT_MATCH:
6799                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6800                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6801                                 break;
6802                         case RTE_MACVLAN_PERFECT_MATCH:
6803                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6804                                 break;
6805                         case RTE_MAC_HASH_MATCH:
6806                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6807                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6808                                 break;
6809                         case RTE_MACVLAN_HASH_MATCH:
6810                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6811                                 break;
6812                         default:
6813                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6814                                 ret = I40E_ERR_PARAM;
6815                                 goto DONE;
6816                         }
6817
6818                         req_list[i].queue_number = 0;
6819
6820                         req_list[i].flags = rte_cpu_to_le_16(flags);
6821                 }
6822
6823                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6824                                                 actual_num, NULL);
6825                 if (ret != I40E_SUCCESS) {
6826                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6827                         goto DONE;
6828                 }
6829                 num += actual_num;
6830         } while (num < total);
6831
6832 DONE:
6833         rte_free(req_list);
6834         return ret;
6835 }
6836
6837 int
6838 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6839                             struct i40e_macvlan_filter *filter,
6840                             int total)
6841 {
6842         int ele_num, ele_buff_size;
6843         int num, actual_num, i;
6844         uint16_t flags;
6845         int ret = I40E_SUCCESS;
6846         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6847         struct i40e_aqc_remove_macvlan_element_data *req_list;
6848
6849         if (filter == NULL  || total == 0)
6850                 return I40E_ERR_PARAM;
6851
6852         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6853         ele_buff_size = hw->aq.asq_buf_size;
6854
6855         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6856         if (req_list == NULL) {
6857                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6858                 return I40E_ERR_NO_MEMORY;
6859         }
6860
6861         num = 0;
6862         do {
6863                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6864                 memset(req_list, 0, ele_buff_size);
6865
6866                 for (i = 0; i < actual_num; i++) {
6867                         rte_memcpy(req_list[i].mac_addr,
6868                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6869                         req_list[i].vlan_tag =
6870                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6871
6872                         switch (filter[num + i].filter_type) {
6873                         case RTE_MAC_PERFECT_MATCH:
6874                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6875                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6876                                 break;
6877                         case RTE_MACVLAN_PERFECT_MATCH:
6878                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6879                                 break;
6880                         case RTE_MAC_HASH_MATCH:
6881                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6882                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6883                                 break;
6884                         case RTE_MACVLAN_HASH_MATCH:
6885                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6886                                 break;
6887                         default:
6888                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6889                                 ret = I40E_ERR_PARAM;
6890                                 goto DONE;
6891                         }
6892                         req_list[i].flags = rte_cpu_to_le_16(flags);
6893                 }
6894
6895                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6896                                                 actual_num, NULL);
6897                 if (ret != I40E_SUCCESS) {
6898                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6899                         goto DONE;
6900                 }
6901                 num += actual_num;
6902         } while (num < total);
6903
6904 DONE:
6905         rte_free(req_list);
6906         return ret;
6907 }
6908
6909 /* Find out specific MAC filter */
6910 static struct i40e_mac_filter *
6911 i40e_find_mac_filter(struct i40e_vsi *vsi,
6912                          struct rte_ether_addr *macaddr)
6913 {
6914         struct i40e_mac_filter *f;
6915
6916         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6917                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6918                         return f;
6919         }
6920
6921         return NULL;
6922 }
6923
6924 static bool
6925 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6926                          uint16_t vlan_id)
6927 {
6928         uint32_t vid_idx, vid_bit;
6929
6930         if (vlan_id > ETH_VLAN_ID_MAX)
6931                 return 0;
6932
6933         vid_idx = I40E_VFTA_IDX(vlan_id);
6934         vid_bit = I40E_VFTA_BIT(vlan_id);
6935
6936         if (vsi->vfta[vid_idx] & vid_bit)
6937                 return 1;
6938         else
6939                 return 0;
6940 }
6941
6942 static void
6943 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6944                        uint16_t vlan_id, bool on)
6945 {
6946         uint32_t vid_idx, vid_bit;
6947
6948         vid_idx = I40E_VFTA_IDX(vlan_id);
6949         vid_bit = I40E_VFTA_BIT(vlan_id);
6950
6951         if (on)
6952                 vsi->vfta[vid_idx] |= vid_bit;
6953         else
6954                 vsi->vfta[vid_idx] &= ~vid_bit;
6955 }
6956
6957 void
6958 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6959                      uint16_t vlan_id, bool on)
6960 {
6961         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6962         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6963         int ret;
6964
6965         if (vlan_id > ETH_VLAN_ID_MAX)
6966                 return;
6967
6968         i40e_store_vlan_filter(vsi, vlan_id, on);
6969
6970         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6971                 return;
6972
6973         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6974
6975         if (on) {
6976                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6977                                        &vlan_data, 1, NULL);
6978                 if (ret != I40E_SUCCESS)
6979                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6980         } else {
6981                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6982                                           &vlan_data, 1, NULL);
6983                 if (ret != I40E_SUCCESS)
6984                         PMD_DRV_LOG(ERR,
6985                                     "Failed to remove vlan filter");
6986         }
6987 }
6988
6989 /**
6990  * Find all vlan options for specific mac addr,
6991  * return with actual vlan found.
6992  */
6993 int
6994 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6995                            struct i40e_macvlan_filter *mv_f,
6996                            int num, struct rte_ether_addr *addr)
6997 {
6998         int i;
6999         uint32_t j, k;
7000
7001         /**
7002          * Not to use i40e_find_vlan_filter to decrease the loop time,
7003          * although the code looks complex.
7004           */
7005         if (num < vsi->vlan_num)
7006                 return I40E_ERR_PARAM;
7007
7008         i = 0;
7009         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7010                 if (vsi->vfta[j]) {
7011                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7012                                 if (vsi->vfta[j] & (1 << k)) {
7013                                         if (i > num - 1) {
7014                                                 PMD_DRV_LOG(ERR,
7015                                                         "vlan number doesn't match");
7016                                                 return I40E_ERR_PARAM;
7017                                         }
7018                                         rte_memcpy(&mv_f[i].macaddr,
7019                                                         addr, ETH_ADDR_LEN);
7020                                         mv_f[i].vlan_id =
7021                                                 j * I40E_UINT32_BIT_SIZE + k;
7022                                         i++;
7023                                 }
7024                         }
7025                 }
7026         }
7027         return I40E_SUCCESS;
7028 }
7029
7030 static inline int
7031 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7032                            struct i40e_macvlan_filter *mv_f,
7033                            int num,
7034                            uint16_t vlan)
7035 {
7036         int i = 0;
7037         struct i40e_mac_filter *f;
7038
7039         if (num < vsi->mac_num)
7040                 return I40E_ERR_PARAM;
7041
7042         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7043                 if (i > num - 1) {
7044                         PMD_DRV_LOG(ERR, "buffer number not match");
7045                         return I40E_ERR_PARAM;
7046                 }
7047                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7048                                 ETH_ADDR_LEN);
7049                 mv_f[i].vlan_id = vlan;
7050                 mv_f[i].filter_type = f->mac_info.filter_type;
7051                 i++;
7052         }
7053
7054         return I40E_SUCCESS;
7055 }
7056
7057 static int
7058 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7059 {
7060         int i, j, num;
7061         struct i40e_mac_filter *f;
7062         struct i40e_macvlan_filter *mv_f;
7063         int ret = I40E_SUCCESS;
7064
7065         if (vsi == NULL || vsi->mac_num == 0)
7066                 return I40E_ERR_PARAM;
7067
7068         /* Case that no vlan is set */
7069         if (vsi->vlan_num == 0)
7070                 num = vsi->mac_num;
7071         else
7072                 num = vsi->mac_num * vsi->vlan_num;
7073
7074         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7075         if (mv_f == NULL) {
7076                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7077                 return I40E_ERR_NO_MEMORY;
7078         }
7079
7080         i = 0;
7081         if (vsi->vlan_num == 0) {
7082                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7083                         rte_memcpy(&mv_f[i].macaddr,
7084                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7085                         mv_f[i].filter_type = f->mac_info.filter_type;
7086                         mv_f[i].vlan_id = 0;
7087                         i++;
7088                 }
7089         } else {
7090                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7091                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7092                                         vsi->vlan_num, &f->mac_info.mac_addr);
7093                         if (ret != I40E_SUCCESS)
7094                                 goto DONE;
7095                         for (j = i; j < i + vsi->vlan_num; j++)
7096                                 mv_f[j].filter_type = f->mac_info.filter_type;
7097                         i += vsi->vlan_num;
7098                 }
7099         }
7100
7101         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7102 DONE:
7103         rte_free(mv_f);
7104
7105         return ret;
7106 }
7107
7108 int
7109 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7110 {
7111         struct i40e_macvlan_filter *mv_f;
7112         int mac_num;
7113         int ret = I40E_SUCCESS;
7114
7115         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7116                 return I40E_ERR_PARAM;
7117
7118         /* If it's already set, just return */
7119         if (i40e_find_vlan_filter(vsi,vlan))
7120                 return I40E_SUCCESS;
7121
7122         mac_num = vsi->mac_num;
7123
7124         if (mac_num == 0) {
7125                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7126                 return I40E_ERR_PARAM;
7127         }
7128
7129         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7130
7131         if (mv_f == NULL) {
7132                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7133                 return I40E_ERR_NO_MEMORY;
7134         }
7135
7136         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7137
7138         if (ret != I40E_SUCCESS)
7139                 goto DONE;
7140
7141         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7142
7143         if (ret != I40E_SUCCESS)
7144                 goto DONE;
7145
7146         i40e_set_vlan_filter(vsi, vlan, 1);
7147
7148         vsi->vlan_num++;
7149         ret = I40E_SUCCESS;
7150 DONE:
7151         rte_free(mv_f);
7152         return ret;
7153 }
7154
7155 int
7156 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7157 {
7158         struct i40e_macvlan_filter *mv_f;
7159         int mac_num;
7160         int ret = I40E_SUCCESS;
7161
7162         /**
7163          * Vlan 0 is the generic filter for untagged packets
7164          * and can't be removed.
7165          */
7166         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7167                 return I40E_ERR_PARAM;
7168
7169         /* If can't find it, just return */
7170         if (!i40e_find_vlan_filter(vsi, vlan))
7171                 return I40E_ERR_PARAM;
7172
7173         mac_num = vsi->mac_num;
7174
7175         if (mac_num == 0) {
7176                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7177                 return I40E_ERR_PARAM;
7178         }
7179
7180         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7181
7182         if (mv_f == NULL) {
7183                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7184                 return I40E_ERR_NO_MEMORY;
7185         }
7186
7187         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7188
7189         if (ret != I40E_SUCCESS)
7190                 goto DONE;
7191
7192         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7193
7194         if (ret != I40E_SUCCESS)
7195                 goto DONE;
7196
7197         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7198         if (vsi->vlan_num == 1) {
7199                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7200                 if (ret != I40E_SUCCESS)
7201                         goto DONE;
7202
7203                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7204                 if (ret != I40E_SUCCESS)
7205                         goto DONE;
7206         }
7207
7208         i40e_set_vlan_filter(vsi, vlan, 0);
7209
7210         vsi->vlan_num--;
7211         ret = I40E_SUCCESS;
7212 DONE:
7213         rte_free(mv_f);
7214         return ret;
7215 }
7216
7217 int
7218 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7219 {
7220         struct i40e_mac_filter *f;
7221         struct i40e_macvlan_filter *mv_f;
7222         int i, vlan_num = 0;
7223         int ret = I40E_SUCCESS;
7224
7225         /* If it's add and we've config it, return */
7226         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7227         if (f != NULL)
7228                 return I40E_SUCCESS;
7229         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7230                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7231
7232                 /**
7233                  * If vlan_num is 0, that's the first time to add mac,
7234                  * set mask for vlan_id 0.
7235                  */
7236                 if (vsi->vlan_num == 0) {
7237                         i40e_set_vlan_filter(vsi, 0, 1);
7238                         vsi->vlan_num = 1;
7239                 }
7240                 vlan_num = vsi->vlan_num;
7241         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7242                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7243                 vlan_num = 1;
7244
7245         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7246         if (mv_f == NULL) {
7247                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7248                 return I40E_ERR_NO_MEMORY;
7249         }
7250
7251         for (i = 0; i < vlan_num; i++) {
7252                 mv_f[i].filter_type = mac_filter->filter_type;
7253                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7254                                 ETH_ADDR_LEN);
7255         }
7256
7257         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7258                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7259                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7260                                         &mac_filter->mac_addr);
7261                 if (ret != I40E_SUCCESS)
7262                         goto DONE;
7263         }
7264
7265         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7266         if (ret != I40E_SUCCESS)
7267                 goto DONE;
7268
7269         /* Add the mac addr into mac list */
7270         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7271         if (f == NULL) {
7272                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7273                 ret = I40E_ERR_NO_MEMORY;
7274                 goto DONE;
7275         }
7276         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7277                         ETH_ADDR_LEN);
7278         f->mac_info.filter_type = mac_filter->filter_type;
7279         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7280         vsi->mac_num++;
7281
7282         ret = I40E_SUCCESS;
7283 DONE:
7284         rte_free(mv_f);
7285
7286         return ret;
7287 }
7288
7289 int
7290 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7291 {
7292         struct i40e_mac_filter *f;
7293         struct i40e_macvlan_filter *mv_f;
7294         int i, vlan_num;
7295         enum rte_mac_filter_type filter_type;
7296         int ret = I40E_SUCCESS;
7297
7298         /* Can't find it, return an error */
7299         f = i40e_find_mac_filter(vsi, addr);
7300         if (f == NULL)
7301                 return I40E_ERR_PARAM;
7302
7303         vlan_num = vsi->vlan_num;
7304         filter_type = f->mac_info.filter_type;
7305         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7306                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7307                 if (vlan_num == 0) {
7308                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7309                         return I40E_ERR_PARAM;
7310                 }
7311         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7312                         filter_type == RTE_MAC_HASH_MATCH)
7313                 vlan_num = 1;
7314
7315         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7316         if (mv_f == NULL) {
7317                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7318                 return I40E_ERR_NO_MEMORY;
7319         }
7320
7321         for (i = 0; i < vlan_num; i++) {
7322                 mv_f[i].filter_type = filter_type;
7323                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7324                                 ETH_ADDR_LEN);
7325         }
7326         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7327                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7328                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7329                 if (ret != I40E_SUCCESS)
7330                         goto DONE;
7331         }
7332
7333         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7334         if (ret != I40E_SUCCESS)
7335                 goto DONE;
7336
7337         /* Remove the mac addr into mac list */
7338         TAILQ_REMOVE(&vsi->mac_list, f, next);
7339         rte_free(f);
7340         vsi->mac_num--;
7341
7342         ret = I40E_SUCCESS;
7343 DONE:
7344         rte_free(mv_f);
7345         return ret;
7346 }
7347
7348 /* Configure hash enable flags for RSS */
7349 uint64_t
7350 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7351 {
7352         uint64_t hena = 0;
7353         int i;
7354
7355         if (!flags)
7356                 return hena;
7357
7358         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7359                 if (flags & (1ULL << i))
7360                         hena |= adapter->pctypes_tbl[i];
7361         }
7362
7363         return hena;
7364 }
7365
7366 /* Parse the hash enable flags */
7367 uint64_t
7368 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7369 {
7370         uint64_t rss_hf = 0;
7371
7372         if (!flags)
7373                 return rss_hf;
7374         int i;
7375
7376         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7377                 if (flags & adapter->pctypes_tbl[i])
7378                         rss_hf |= (1ULL << i);
7379         }
7380         return rss_hf;
7381 }
7382
7383 /* Disable RSS */
7384 static void
7385 i40e_pf_disable_rss(struct i40e_pf *pf)
7386 {
7387         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7388
7389         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7390         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7391         I40E_WRITE_FLUSH(hw);
7392 }
7393
7394 int
7395 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7396 {
7397         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7398         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7399         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7400                            I40E_VFQF_HKEY_MAX_INDEX :
7401                            I40E_PFQF_HKEY_MAX_INDEX;
7402         int ret = 0;
7403
7404         if (!key || key_len == 0) {
7405                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7406                 return 0;
7407         } else if (key_len != (key_idx + 1) *
7408                 sizeof(uint32_t)) {
7409                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7410                 return -EINVAL;
7411         }
7412
7413         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7414                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7415                         (struct i40e_aqc_get_set_rss_key_data *)key;
7416
7417                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7418                 if (ret)
7419                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7420         } else {
7421                 uint32_t *hash_key = (uint32_t *)key;
7422                 uint16_t i;
7423
7424                 if (vsi->type == I40E_VSI_SRIOV) {
7425                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7426                                 I40E_WRITE_REG(
7427                                         hw,
7428                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7429                                         hash_key[i]);
7430
7431                 } else {
7432                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7433                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7434                                                hash_key[i]);
7435                 }
7436                 I40E_WRITE_FLUSH(hw);
7437         }
7438
7439         return ret;
7440 }
7441
7442 static int
7443 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7444 {
7445         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7446         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7447         uint32_t reg;
7448         int ret;
7449
7450         if (!key || !key_len)
7451                 return 0;
7452
7453         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7454                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7455                         (struct i40e_aqc_get_set_rss_key_data *)key);
7456                 if (ret) {
7457                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7458                         return ret;
7459                 }
7460         } else {
7461                 uint32_t *key_dw = (uint32_t *)key;
7462                 uint16_t i;
7463
7464                 if (vsi->type == I40E_VSI_SRIOV) {
7465                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7466                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7467                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7468                         }
7469                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7470                                    sizeof(uint32_t);
7471                 } else {
7472                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7473                                 reg = I40E_PFQF_HKEY(i);
7474                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7475                         }
7476                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7477                                    sizeof(uint32_t);
7478                 }
7479         }
7480         return 0;
7481 }
7482
7483 static int
7484 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7485 {
7486         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7487         uint64_t hena;
7488         int ret;
7489
7490         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7491                                rss_conf->rss_key_len);
7492         if (ret)
7493                 return ret;
7494
7495         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7496         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7497         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7498         I40E_WRITE_FLUSH(hw);
7499
7500         return 0;
7501 }
7502
7503 static int
7504 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7505                          struct rte_eth_rss_conf *rss_conf)
7506 {
7507         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7508         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7509         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7510         uint64_t hena;
7511
7512         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7513         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7514
7515         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7516                 if (rss_hf != 0) /* Enable RSS */
7517                         return -EINVAL;
7518                 return 0; /* Nothing to do */
7519         }
7520         /* RSS enabled */
7521         if (rss_hf == 0) /* Disable RSS */
7522                 return -EINVAL;
7523
7524         return i40e_hw_rss_hash_set(pf, rss_conf);
7525 }
7526
7527 static int
7528 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7529                            struct rte_eth_rss_conf *rss_conf)
7530 {
7531         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7532         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7533         uint64_t hena;
7534         int ret;
7535
7536         if (!rss_conf)
7537                 return -EINVAL;
7538
7539         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7540                          &rss_conf->rss_key_len);
7541         if (ret)
7542                 return ret;
7543
7544         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7545         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7546         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7547
7548         return 0;
7549 }
7550
7551 static int
7552 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7553 {
7554         switch (filter_type) {
7555         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7556                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7557                 break;
7558         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7559                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7560                 break;
7561         case RTE_TUNNEL_FILTER_IMAC_TENID:
7562                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7563                 break;
7564         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7565                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7566                 break;
7567         case ETH_TUNNEL_FILTER_IMAC:
7568                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7569                 break;
7570         case ETH_TUNNEL_FILTER_OIP:
7571                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7572                 break;
7573         case ETH_TUNNEL_FILTER_IIP:
7574                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7575                 break;
7576         default:
7577                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7578                 return -EINVAL;
7579         }
7580
7581         return 0;
7582 }
7583
7584 /* Convert tunnel filter structure */
7585 static int
7586 i40e_tunnel_filter_convert(
7587         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7588         struct i40e_tunnel_filter *tunnel_filter)
7589 {
7590         rte_ether_addr_copy((struct rte_ether_addr *)
7591                         &cld_filter->element.outer_mac,
7592                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7593         rte_ether_addr_copy((struct rte_ether_addr *)
7594                         &cld_filter->element.inner_mac,
7595                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7596         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7597         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7598              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7599             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7600                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7601         else
7602                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7603         tunnel_filter->input.flags = cld_filter->element.flags;
7604         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7605         tunnel_filter->queue = cld_filter->element.queue_number;
7606         rte_memcpy(tunnel_filter->input.general_fields,
7607                    cld_filter->general_fields,
7608                    sizeof(cld_filter->general_fields));
7609
7610         return 0;
7611 }
7612
7613 /* Check if there exists the tunnel filter */
7614 struct i40e_tunnel_filter *
7615 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7616                              const struct i40e_tunnel_filter_input *input)
7617 {
7618         int ret;
7619
7620         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7621         if (ret < 0)
7622                 return NULL;
7623
7624         return tunnel_rule->hash_map[ret];
7625 }
7626
7627 /* Add a tunnel filter into the SW list */
7628 static int
7629 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7630                              struct i40e_tunnel_filter *tunnel_filter)
7631 {
7632         struct i40e_tunnel_rule *rule = &pf->tunnel;
7633         int ret;
7634
7635         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7636         if (ret < 0) {
7637                 PMD_DRV_LOG(ERR,
7638                             "Failed to insert tunnel filter to hash table %d!",
7639                             ret);
7640                 return ret;
7641         }
7642         rule->hash_map[ret] = tunnel_filter;
7643
7644         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7645
7646         return 0;
7647 }
7648
7649 /* Delete a tunnel filter from the SW list */
7650 int
7651 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7652                           struct i40e_tunnel_filter_input *input)
7653 {
7654         struct i40e_tunnel_rule *rule = &pf->tunnel;
7655         struct i40e_tunnel_filter *tunnel_filter;
7656         int ret;
7657
7658         ret = rte_hash_del_key(rule->hash_table, input);
7659         if (ret < 0) {
7660                 PMD_DRV_LOG(ERR,
7661                             "Failed to delete tunnel filter to hash table %d!",
7662                             ret);
7663                 return ret;
7664         }
7665         tunnel_filter = rule->hash_map[ret];
7666         rule->hash_map[ret] = NULL;
7667
7668         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7669         rte_free(tunnel_filter);
7670
7671         return 0;
7672 }
7673
7674 int
7675 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7676                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7677                         uint8_t add)
7678 {
7679         uint16_t ip_type;
7680         uint32_t ipv4_addr, ipv4_addr_le;
7681         uint8_t i, tun_type = 0;
7682         /* internal varialbe to convert ipv6 byte order */
7683         uint32_t convert_ipv6[4];
7684         int val, ret = 0;
7685         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7686         struct i40e_vsi *vsi = pf->main_vsi;
7687         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7688         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7689         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7690         struct i40e_tunnel_filter *tunnel, *node;
7691         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7692
7693         cld_filter = rte_zmalloc("tunnel_filter",
7694                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7695         0);
7696
7697         if (NULL == cld_filter) {
7698                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7699                 return -ENOMEM;
7700         }
7701         pfilter = cld_filter;
7702
7703         rte_ether_addr_copy(&tunnel_filter->outer_mac,
7704                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7705         rte_ether_addr_copy(&tunnel_filter->inner_mac,
7706                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
7707
7708         pfilter->element.inner_vlan =
7709                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7710         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7711                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7712                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7713                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7714                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7715                                 &ipv4_addr_le,
7716                                 sizeof(pfilter->element.ipaddr.v4.data));
7717         } else {
7718                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7719                 for (i = 0; i < 4; i++) {
7720                         convert_ipv6[i] =
7721                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7722                 }
7723                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7724                            &convert_ipv6,
7725                            sizeof(pfilter->element.ipaddr.v6.data));
7726         }
7727
7728         /* check tunneled type */
7729         switch (tunnel_filter->tunnel_type) {
7730         case RTE_TUNNEL_TYPE_VXLAN:
7731                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7732                 break;
7733         case RTE_TUNNEL_TYPE_NVGRE:
7734                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7735                 break;
7736         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7737                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7738                 break;
7739         case RTE_TUNNEL_TYPE_VXLAN_GPE:
7740                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7741                 break;
7742         default:
7743                 /* Other tunnel types is not supported. */
7744                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7745                 rte_free(cld_filter);
7746                 return -EINVAL;
7747         }
7748
7749         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7750                                        &pfilter->element.flags);
7751         if (val < 0) {
7752                 rte_free(cld_filter);
7753                 return -EINVAL;
7754         }
7755
7756         pfilter->element.flags |= rte_cpu_to_le_16(
7757                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7758                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7759         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7760         pfilter->element.queue_number =
7761                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7762
7763         /* Check if there is the filter in SW list */
7764         memset(&check_filter, 0, sizeof(check_filter));
7765         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7766         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7767         if (add && node) {
7768                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7769                 rte_free(cld_filter);
7770                 return -EINVAL;
7771         }
7772
7773         if (!add && !node) {
7774                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7775                 rte_free(cld_filter);
7776                 return -EINVAL;
7777         }
7778
7779         if (add) {
7780                 ret = i40e_aq_add_cloud_filters(hw,
7781                                         vsi->seid, &cld_filter->element, 1);
7782                 if (ret < 0) {
7783                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7784                         rte_free(cld_filter);
7785                         return -ENOTSUP;
7786                 }
7787                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7788                 if (tunnel == NULL) {
7789                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7790                         rte_free(cld_filter);
7791                         return -ENOMEM;
7792                 }
7793
7794                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7795                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7796                 if (ret < 0)
7797                         rte_free(tunnel);
7798         } else {
7799                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7800                                                    &cld_filter->element, 1);
7801                 if (ret < 0) {
7802                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7803                         rte_free(cld_filter);
7804                         return -ENOTSUP;
7805                 }
7806                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7807         }
7808
7809         rte_free(cld_filter);
7810         return ret;
7811 }
7812
7813 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7814 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7815 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7816 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7817 #define I40E_TR_GRE_KEY_MASK                    0x400
7818 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7819 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7820
7821 static enum
7822 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7823 {
7824         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7825         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7826         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7827         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7828         enum i40e_status_code status = I40E_SUCCESS;
7829
7830         if (pf->support_multi_driver) {
7831                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7832                 return I40E_NOT_SUPPORTED;
7833         }
7834
7835         memset(&filter_replace, 0,
7836                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7837         memset(&filter_replace_buf, 0,
7838                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7839
7840         /* create L1 filter */
7841         filter_replace.old_filter_type =
7842                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7843         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7844         filter_replace.tr_bit = 0;
7845
7846         /* Prepare the buffer, 3 entries */
7847         filter_replace_buf.data[0] =
7848                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7849         filter_replace_buf.data[0] |=
7850                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7851         filter_replace_buf.data[2] = 0xFF;
7852         filter_replace_buf.data[3] = 0xFF;
7853         filter_replace_buf.data[4] =
7854                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7855         filter_replace_buf.data[4] |=
7856                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7857         filter_replace_buf.data[7] = 0xF0;
7858         filter_replace_buf.data[8]
7859                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7860         filter_replace_buf.data[8] |=
7861                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7862         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7863                 I40E_TR_GENEVE_KEY_MASK |
7864                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7865         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7866                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7867                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7868
7869         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7870                                                &filter_replace_buf);
7871         if (!status && (filter_replace.old_filter_type !=
7872                         filter_replace.new_filter_type))
7873                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7874                             " original: 0x%x, new: 0x%x",
7875                             dev->device->name,
7876                             filter_replace.old_filter_type,
7877                             filter_replace.new_filter_type);
7878
7879         return status;
7880 }
7881
7882 static enum
7883 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7884 {
7885         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7886         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7887         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7888         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7889         enum i40e_status_code status = I40E_SUCCESS;
7890
7891         if (pf->support_multi_driver) {
7892                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7893                 return I40E_NOT_SUPPORTED;
7894         }
7895
7896         /* For MPLSoUDP */
7897         memset(&filter_replace, 0,
7898                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7899         memset(&filter_replace_buf, 0,
7900                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7901         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7902                 I40E_AQC_MIRROR_CLOUD_FILTER;
7903         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7904         filter_replace.new_filter_type =
7905                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7906         /* Prepare the buffer, 2 entries */
7907         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7908         filter_replace_buf.data[0] |=
7909                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7910         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7911         filter_replace_buf.data[4] |=
7912                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7913         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7914                                                &filter_replace_buf);
7915         if (status < 0)
7916                 return status;
7917         if (filter_replace.old_filter_type !=
7918             filter_replace.new_filter_type)
7919                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7920                             " original: 0x%x, new: 0x%x",
7921                             dev->device->name,
7922                             filter_replace.old_filter_type,
7923                             filter_replace.new_filter_type);
7924
7925         /* For MPLSoGRE */
7926         memset(&filter_replace, 0,
7927                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7928         memset(&filter_replace_buf, 0,
7929                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7930
7931         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7932                 I40E_AQC_MIRROR_CLOUD_FILTER;
7933         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7934         filter_replace.new_filter_type =
7935                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7936         /* Prepare the buffer, 2 entries */
7937         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7938         filter_replace_buf.data[0] |=
7939                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7940         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7941         filter_replace_buf.data[4] |=
7942                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7943
7944         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7945                                                &filter_replace_buf);
7946         if (!status && (filter_replace.old_filter_type !=
7947                         filter_replace.new_filter_type))
7948                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7949                             " original: 0x%x, new: 0x%x",
7950                             dev->device->name,
7951                             filter_replace.old_filter_type,
7952                             filter_replace.new_filter_type);
7953
7954         return status;
7955 }
7956
7957 static enum i40e_status_code
7958 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7959 {
7960         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7961         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7962         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7963         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7964         enum i40e_status_code status = I40E_SUCCESS;
7965
7966         if (pf->support_multi_driver) {
7967                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7968                 return I40E_NOT_SUPPORTED;
7969         }
7970
7971         /* For GTP-C */
7972         memset(&filter_replace, 0,
7973                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7974         memset(&filter_replace_buf, 0,
7975                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7976         /* create L1 filter */
7977         filter_replace.old_filter_type =
7978                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7979         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7980         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7981                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7982         /* Prepare the buffer, 2 entries */
7983         filter_replace_buf.data[0] =
7984                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7985         filter_replace_buf.data[0] |=
7986                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7987         filter_replace_buf.data[2] = 0xFF;
7988         filter_replace_buf.data[3] = 0xFF;
7989         filter_replace_buf.data[4] =
7990                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7991         filter_replace_buf.data[4] |=
7992                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7993         filter_replace_buf.data[6] = 0xFF;
7994         filter_replace_buf.data[7] = 0xFF;
7995         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7996                                                &filter_replace_buf);
7997         if (status < 0)
7998                 return status;
7999         if (filter_replace.old_filter_type !=
8000             filter_replace.new_filter_type)
8001                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8002                             " original: 0x%x, new: 0x%x",
8003                             dev->device->name,
8004                             filter_replace.old_filter_type,
8005                             filter_replace.new_filter_type);
8006
8007         /* for GTP-U */
8008         memset(&filter_replace, 0,
8009                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8010         memset(&filter_replace_buf, 0,
8011                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8012         /* create L1 filter */
8013         filter_replace.old_filter_type =
8014                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8015         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8016         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8017                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8018         /* Prepare the buffer, 2 entries */
8019         filter_replace_buf.data[0] =
8020                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8021         filter_replace_buf.data[0] |=
8022                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8023         filter_replace_buf.data[2] = 0xFF;
8024         filter_replace_buf.data[3] = 0xFF;
8025         filter_replace_buf.data[4] =
8026                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8027         filter_replace_buf.data[4] |=
8028                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8029         filter_replace_buf.data[6] = 0xFF;
8030         filter_replace_buf.data[7] = 0xFF;
8031
8032         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8033                                                &filter_replace_buf);
8034         if (!status && (filter_replace.old_filter_type !=
8035                         filter_replace.new_filter_type))
8036                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8037                             " original: 0x%x, new: 0x%x",
8038                             dev->device->name,
8039                             filter_replace.old_filter_type,
8040                             filter_replace.new_filter_type);
8041
8042         return status;
8043 }
8044
8045 static enum
8046 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8047 {
8048         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8049         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8050         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8051         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8052         enum i40e_status_code status = I40E_SUCCESS;
8053
8054         if (pf->support_multi_driver) {
8055                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8056                 return I40E_NOT_SUPPORTED;
8057         }
8058
8059         /* for GTP-C */
8060         memset(&filter_replace, 0,
8061                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8062         memset(&filter_replace_buf, 0,
8063                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8064         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8065         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8066         filter_replace.new_filter_type =
8067                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8068         /* Prepare the buffer, 2 entries */
8069         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8070         filter_replace_buf.data[0] |=
8071                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8072         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8073         filter_replace_buf.data[4] |=
8074                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8075         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8076                                                &filter_replace_buf);
8077         if (status < 0)
8078                 return status;
8079         if (filter_replace.old_filter_type !=
8080             filter_replace.new_filter_type)
8081                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8082                             " original: 0x%x, new: 0x%x",
8083                             dev->device->name,
8084                             filter_replace.old_filter_type,
8085                             filter_replace.new_filter_type);
8086
8087         /* for GTP-U */
8088         memset(&filter_replace, 0,
8089                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8090         memset(&filter_replace_buf, 0,
8091                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8092         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8093         filter_replace.old_filter_type =
8094                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8095         filter_replace.new_filter_type =
8096                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8097         /* Prepare the buffer, 2 entries */
8098         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8099         filter_replace_buf.data[0] |=
8100                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8101         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8102         filter_replace_buf.data[4] |=
8103                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8104
8105         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8106                                                &filter_replace_buf);
8107         if (!status && (filter_replace.old_filter_type !=
8108                         filter_replace.new_filter_type))
8109                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8110                             " original: 0x%x, new: 0x%x",
8111                             dev->device->name,
8112                             filter_replace.old_filter_type,
8113                             filter_replace.new_filter_type);
8114
8115         return status;
8116 }
8117
8118 int
8119 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8120                       struct i40e_tunnel_filter_conf *tunnel_filter,
8121                       uint8_t add)
8122 {
8123         uint16_t ip_type;
8124         uint32_t ipv4_addr, ipv4_addr_le;
8125         uint8_t i, tun_type = 0;
8126         /* internal variable to convert ipv6 byte order */
8127         uint32_t convert_ipv6[4];
8128         int val, ret = 0;
8129         struct i40e_pf_vf *vf = NULL;
8130         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8131         struct i40e_vsi *vsi;
8132         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8133         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8134         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8135         struct i40e_tunnel_filter *tunnel, *node;
8136         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8137         uint32_t teid_le;
8138         bool big_buffer = 0;
8139
8140         cld_filter = rte_zmalloc("tunnel_filter",
8141                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8142                          0);
8143
8144         if (cld_filter == NULL) {
8145                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8146                 return -ENOMEM;
8147         }
8148         pfilter = cld_filter;
8149
8150         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8151                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8152         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8153                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8154
8155         pfilter->element.inner_vlan =
8156                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8157         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8158                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8159                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8160                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8161                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8162                                 &ipv4_addr_le,
8163                                 sizeof(pfilter->element.ipaddr.v4.data));
8164         } else {
8165                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8166                 for (i = 0; i < 4; i++) {
8167                         convert_ipv6[i] =
8168                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8169                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8170                 }
8171                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8172                            &convert_ipv6,
8173                            sizeof(pfilter->element.ipaddr.v6.data));
8174         }
8175
8176         /* check tunneled type */
8177         switch (tunnel_filter->tunnel_type) {
8178         case I40E_TUNNEL_TYPE_VXLAN:
8179                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8180                 break;
8181         case I40E_TUNNEL_TYPE_NVGRE:
8182                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8183                 break;
8184         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8185                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8186                 break;
8187         case I40E_TUNNEL_TYPE_MPLSoUDP:
8188                 if (!pf->mpls_replace_flag) {
8189                         i40e_replace_mpls_l1_filter(pf);
8190                         i40e_replace_mpls_cloud_filter(pf);
8191                         pf->mpls_replace_flag = 1;
8192                 }
8193                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8194                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8195                         teid_le >> 4;
8196                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8197                         (teid_le & 0xF) << 12;
8198                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8199                         0x40;
8200                 big_buffer = 1;
8201                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8202                 break;
8203         case I40E_TUNNEL_TYPE_MPLSoGRE:
8204                 if (!pf->mpls_replace_flag) {
8205                         i40e_replace_mpls_l1_filter(pf);
8206                         i40e_replace_mpls_cloud_filter(pf);
8207                         pf->mpls_replace_flag = 1;
8208                 }
8209                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8210                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8211                         teid_le >> 4;
8212                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8213                         (teid_le & 0xF) << 12;
8214                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8215                         0x0;
8216                 big_buffer = 1;
8217                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8218                 break;
8219         case I40E_TUNNEL_TYPE_GTPC:
8220                 if (!pf->gtp_replace_flag) {
8221                         i40e_replace_gtp_l1_filter(pf);
8222                         i40e_replace_gtp_cloud_filter(pf);
8223                         pf->gtp_replace_flag = 1;
8224                 }
8225                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8226                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8227                         (teid_le >> 16) & 0xFFFF;
8228                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8229                         teid_le & 0xFFFF;
8230                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8231                         0x0;
8232                 big_buffer = 1;
8233                 break;
8234         case I40E_TUNNEL_TYPE_GTPU:
8235                 if (!pf->gtp_replace_flag) {
8236                         i40e_replace_gtp_l1_filter(pf);
8237                         i40e_replace_gtp_cloud_filter(pf);
8238                         pf->gtp_replace_flag = 1;
8239                 }
8240                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8241                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8242                         (teid_le >> 16) & 0xFFFF;
8243                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8244                         teid_le & 0xFFFF;
8245                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8246                         0x0;
8247                 big_buffer = 1;
8248                 break;
8249         case I40E_TUNNEL_TYPE_QINQ:
8250                 if (!pf->qinq_replace_flag) {
8251                         ret = i40e_cloud_filter_qinq_create(pf);
8252                         if (ret < 0)
8253                                 PMD_DRV_LOG(DEBUG,
8254                                             "QinQ tunnel filter already created.");
8255                         pf->qinq_replace_flag = 1;
8256                 }
8257                 /*      Add in the General fields the values of
8258                  *      the Outer and Inner VLAN
8259                  *      Big Buffer should be set, see changes in
8260                  *      i40e_aq_add_cloud_filters
8261                  */
8262                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8263                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8264                 big_buffer = 1;
8265                 break;
8266         default:
8267                 /* Other tunnel types is not supported. */
8268                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8269                 rte_free(cld_filter);
8270                 return -EINVAL;
8271         }
8272
8273         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8274                 pfilter->element.flags =
8275                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8276         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8277                 pfilter->element.flags =
8278                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8279         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8280                 pfilter->element.flags =
8281                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8282         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8283                 pfilter->element.flags =
8284                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8285         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8286                 pfilter->element.flags |=
8287                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8288         else {
8289                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8290                                                 &pfilter->element.flags);
8291                 if (val < 0) {
8292                         rte_free(cld_filter);
8293                         return -EINVAL;
8294                 }
8295         }
8296
8297         pfilter->element.flags |= rte_cpu_to_le_16(
8298                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8299                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8300         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8301         pfilter->element.queue_number =
8302                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8303
8304         if (!tunnel_filter->is_to_vf)
8305                 vsi = pf->main_vsi;
8306         else {
8307                 if (tunnel_filter->vf_id >= pf->vf_num) {
8308                         PMD_DRV_LOG(ERR, "Invalid argument.");
8309                         rte_free(cld_filter);
8310                         return -EINVAL;
8311                 }
8312                 vf = &pf->vfs[tunnel_filter->vf_id];
8313                 vsi = vf->vsi;
8314         }
8315
8316         /* Check if there is the filter in SW list */
8317         memset(&check_filter, 0, sizeof(check_filter));
8318         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8319         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8320         check_filter.vf_id = tunnel_filter->vf_id;
8321         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8322         if (add && node) {
8323                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8324                 rte_free(cld_filter);
8325                 return -EINVAL;
8326         }
8327
8328         if (!add && !node) {
8329                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8330                 rte_free(cld_filter);
8331                 return -EINVAL;
8332         }
8333
8334         if (add) {
8335                 if (big_buffer)
8336                         ret = i40e_aq_add_cloud_filters_bb(hw,
8337                                                    vsi->seid, cld_filter, 1);
8338                 else
8339                         ret = i40e_aq_add_cloud_filters(hw,
8340                                         vsi->seid, &cld_filter->element, 1);
8341                 if (ret < 0) {
8342                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8343                         rte_free(cld_filter);
8344                         return -ENOTSUP;
8345                 }
8346                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8347                 if (tunnel == NULL) {
8348                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8349                         rte_free(cld_filter);
8350                         return -ENOMEM;
8351                 }
8352
8353                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8354                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8355                 if (ret < 0)
8356                         rte_free(tunnel);
8357         } else {
8358                 if (big_buffer)
8359                         ret = i40e_aq_rem_cloud_filters_bb(
8360                                 hw, vsi->seid, cld_filter, 1);
8361                 else
8362                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8363                                                 &cld_filter->element, 1);
8364                 if (ret < 0) {
8365                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8366                         rte_free(cld_filter);
8367                         return -ENOTSUP;
8368                 }
8369                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8370         }
8371
8372         rte_free(cld_filter);
8373         return ret;
8374 }
8375
8376 static int
8377 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8378 {
8379         uint8_t i;
8380
8381         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8382                 if (pf->vxlan_ports[i] == port)
8383                         return i;
8384         }
8385
8386         return -1;
8387 }
8388
8389 static int
8390 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8391 {
8392         int  idx, ret;
8393         uint8_t filter_idx;
8394         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8395
8396         idx = i40e_get_vxlan_port_idx(pf, port);
8397
8398         /* Check if port already exists */
8399         if (idx >= 0) {
8400                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8401                 return -EINVAL;
8402         }
8403
8404         /* Now check if there is space to add the new port */
8405         idx = i40e_get_vxlan_port_idx(pf, 0);
8406         if (idx < 0) {
8407                 PMD_DRV_LOG(ERR,
8408                         "Maximum number of UDP ports reached, not adding port %d",
8409                         port);
8410                 return -ENOSPC;
8411         }
8412
8413         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8414                                         &filter_idx, NULL);
8415         if (ret < 0) {
8416                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8417                 return -1;
8418         }
8419
8420         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8421                          port,  filter_idx);
8422
8423         /* New port: add it and mark its index in the bitmap */
8424         pf->vxlan_ports[idx] = port;
8425         pf->vxlan_bitmap |= (1 << idx);
8426
8427         if (!(pf->flags & I40E_FLAG_VXLAN))
8428                 pf->flags |= I40E_FLAG_VXLAN;
8429
8430         return 0;
8431 }
8432
8433 static int
8434 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8435 {
8436         int idx;
8437         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8438
8439         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8440                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8441                 return -EINVAL;
8442         }
8443
8444         idx = i40e_get_vxlan_port_idx(pf, port);
8445
8446         if (idx < 0) {
8447                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8448                 return -EINVAL;
8449         }
8450
8451         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8452                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8453                 return -1;
8454         }
8455
8456         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8457                         port, idx);
8458
8459         pf->vxlan_ports[idx] = 0;
8460         pf->vxlan_bitmap &= ~(1 << idx);
8461
8462         if (!pf->vxlan_bitmap)
8463                 pf->flags &= ~I40E_FLAG_VXLAN;
8464
8465         return 0;
8466 }
8467
8468 /* Add UDP tunneling port */
8469 static int
8470 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8471                              struct rte_eth_udp_tunnel *udp_tunnel)
8472 {
8473         int ret = 0;
8474         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8475
8476         if (udp_tunnel == NULL)
8477                 return -EINVAL;
8478
8479         switch (udp_tunnel->prot_type) {
8480         case RTE_TUNNEL_TYPE_VXLAN:
8481                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8482                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8483                 break;
8484         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8485                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8486                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8487                 break;
8488         case RTE_TUNNEL_TYPE_GENEVE:
8489         case RTE_TUNNEL_TYPE_TEREDO:
8490                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8491                 ret = -1;
8492                 break;
8493
8494         default:
8495                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8496                 ret = -1;
8497                 break;
8498         }
8499
8500         return ret;
8501 }
8502
8503 /* Remove UDP tunneling port */
8504 static int
8505 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8506                              struct rte_eth_udp_tunnel *udp_tunnel)
8507 {
8508         int ret = 0;
8509         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8510
8511         if (udp_tunnel == NULL)
8512                 return -EINVAL;
8513
8514         switch (udp_tunnel->prot_type) {
8515         case RTE_TUNNEL_TYPE_VXLAN:
8516         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8517                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8518                 break;
8519         case RTE_TUNNEL_TYPE_GENEVE:
8520         case RTE_TUNNEL_TYPE_TEREDO:
8521                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8522                 ret = -1;
8523                 break;
8524         default:
8525                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8526                 ret = -1;
8527                 break;
8528         }
8529
8530         return ret;
8531 }
8532
8533 /* Calculate the maximum number of contiguous PF queues that are configured */
8534 static int
8535 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8536 {
8537         struct rte_eth_dev_data *data = pf->dev_data;
8538         int i, num;
8539         struct i40e_rx_queue *rxq;
8540
8541         num = 0;
8542         for (i = 0; i < pf->lan_nb_qps; i++) {
8543                 rxq = data->rx_queues[i];
8544                 if (rxq && rxq->q_set)
8545                         num++;
8546                 else
8547                         break;
8548         }
8549
8550         return num;
8551 }
8552
8553 /* Configure RSS */
8554 static int
8555 i40e_pf_config_rss(struct i40e_pf *pf)
8556 {
8557         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8558         struct rte_eth_rss_conf rss_conf;
8559         uint32_t i, lut = 0;
8560         uint16_t j, num;
8561
8562         /*
8563          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8564          * It's necessary to calculate the actual PF queues that are configured.
8565          */
8566         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8567                 num = i40e_pf_calc_configured_queues_num(pf);
8568         else
8569                 num = pf->dev_data->nb_rx_queues;
8570
8571         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8572         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8573                         num);
8574
8575         if (num == 0) {
8576                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8577                 return -ENOTSUP;
8578         }
8579
8580         if (pf->adapter->rss_reta_updated == 0) {
8581                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8582                         if (j == num)
8583                                 j = 0;
8584                         lut = (lut << 8) | (j & ((0x1 <<
8585                                 hw->func_caps.rss_table_entry_width) - 1));
8586                         if ((i & 3) == 3)
8587                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8588                                                rte_bswap32(lut));
8589                 }
8590         }
8591
8592         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8593         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8594                 i40e_pf_disable_rss(pf);
8595                 return 0;
8596         }
8597         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8598                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8599                 /* Random default keys */
8600                 static uint32_t rss_key_default[] = {0x6b793944,
8601                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8602                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8603                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8604
8605                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8606                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8607                                                         sizeof(uint32_t);
8608         }
8609
8610         return i40e_hw_rss_hash_set(pf, &rss_conf);
8611 }
8612
8613 static int
8614 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8615                                struct rte_eth_tunnel_filter_conf *filter)
8616 {
8617         if (pf == NULL || filter == NULL) {
8618                 PMD_DRV_LOG(ERR, "Invalid parameter");
8619                 return -EINVAL;
8620         }
8621
8622         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8623                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8624                 return -EINVAL;
8625         }
8626
8627         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8628                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8629                 return -EINVAL;
8630         }
8631
8632         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8633                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8634                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8635                 return -EINVAL;
8636         }
8637
8638         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8639                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8640                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8641                 return -EINVAL;
8642         }
8643
8644         return 0;
8645 }
8646
8647 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8648 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8649 static int
8650 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8651 {
8652         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8653         uint32_t val, reg;
8654         int ret = -EINVAL;
8655
8656         if (pf->support_multi_driver) {
8657                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8658                 return -ENOTSUP;
8659         }
8660
8661         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8662         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8663
8664         if (len == 3) {
8665                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8666         } else if (len == 4) {
8667                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8668         } else {
8669                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8670                 return ret;
8671         }
8672
8673         if (reg != val) {
8674                 ret = i40e_aq_debug_write_global_register(hw,
8675                                                    I40E_GL_PRS_FVBM(2),
8676                                                    reg, NULL);
8677                 if (ret != 0)
8678                         return ret;
8679                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8680                             "with value 0x%08x",
8681                             I40E_GL_PRS_FVBM(2), reg);
8682         } else {
8683                 ret = 0;
8684         }
8685         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8686                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8687
8688         return ret;
8689 }
8690
8691 static int
8692 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8693 {
8694         int ret = -EINVAL;
8695
8696         if (!hw || !cfg)
8697                 return -EINVAL;
8698
8699         switch (cfg->cfg_type) {
8700         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8701                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8702                 break;
8703         default:
8704                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8705                 break;
8706         }
8707
8708         return ret;
8709 }
8710
8711 static int
8712 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8713                                enum rte_filter_op filter_op,
8714                                void *arg)
8715 {
8716         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8717         int ret = I40E_ERR_PARAM;
8718
8719         switch (filter_op) {
8720         case RTE_ETH_FILTER_SET:
8721                 ret = i40e_dev_global_config_set(hw,
8722                         (struct rte_eth_global_cfg *)arg);
8723                 break;
8724         default:
8725                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8726                 break;
8727         }
8728
8729         return ret;
8730 }
8731
8732 static int
8733 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8734                           enum rte_filter_op filter_op,
8735                           void *arg)
8736 {
8737         struct rte_eth_tunnel_filter_conf *filter;
8738         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8739         int ret = I40E_SUCCESS;
8740
8741         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8742
8743         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8744                 return I40E_ERR_PARAM;
8745
8746         switch (filter_op) {
8747         case RTE_ETH_FILTER_NOP:
8748                 if (!(pf->flags & I40E_FLAG_VXLAN))
8749                         ret = I40E_NOT_SUPPORTED;
8750                 break;
8751         case RTE_ETH_FILTER_ADD:
8752                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8753                 break;
8754         case RTE_ETH_FILTER_DELETE:
8755                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8756                 break;
8757         default:
8758                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8759                 ret = I40E_ERR_PARAM;
8760                 break;
8761         }
8762
8763         return ret;
8764 }
8765
8766 static int
8767 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8768 {
8769         int ret = 0;
8770         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8771
8772         /* RSS setup */
8773         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8774                 ret = i40e_pf_config_rss(pf);
8775         else
8776                 i40e_pf_disable_rss(pf);
8777
8778         return ret;
8779 }
8780
8781 /* Get the symmetric hash enable configurations per port */
8782 static void
8783 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8784 {
8785         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8786
8787         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8788 }
8789
8790 /* Set the symmetric hash enable configurations per port */
8791 static void
8792 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8793 {
8794         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8795
8796         if (enable > 0) {
8797                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8798                         PMD_DRV_LOG(INFO,
8799                                 "Symmetric hash has already been enabled");
8800                         return;
8801                 }
8802                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8803         } else {
8804                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8805                         PMD_DRV_LOG(INFO,
8806                                 "Symmetric hash has already been disabled");
8807                         return;
8808                 }
8809                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8810         }
8811         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8812         I40E_WRITE_FLUSH(hw);
8813 }
8814
8815 /*
8816  * Get global configurations of hash function type and symmetric hash enable
8817  * per flow type (pctype). Note that global configuration means it affects all
8818  * the ports on the same NIC.
8819  */
8820 static int
8821 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8822                                    struct rte_eth_hash_global_conf *g_cfg)
8823 {
8824         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8825         uint32_t reg;
8826         uint16_t i, j;
8827
8828         memset(g_cfg, 0, sizeof(*g_cfg));
8829         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8830         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8831                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8832         else
8833                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8834         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8835                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8836
8837         /*
8838          * As i40e supports less than 64 flow types, only first 64 bits need to
8839          * be checked.
8840          */
8841         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8842                 g_cfg->valid_bit_mask[i] = 0ULL;
8843                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8844         }
8845
8846         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8847
8848         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8849                 if (!adapter->pctypes_tbl[i])
8850                         continue;
8851                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8852                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8853                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8854                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8855                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8856                                         g_cfg->sym_hash_enable_mask[0] |=
8857                                                                 (1ULL << i);
8858                                 }
8859                         }
8860                 }
8861         }
8862
8863         return 0;
8864 }
8865
8866 static int
8867 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8868                               const struct rte_eth_hash_global_conf *g_cfg)
8869 {
8870         uint32_t i;
8871         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8872
8873         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8874                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8875                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8876                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8877                                                 g_cfg->hash_func);
8878                 return -EINVAL;
8879         }
8880
8881         /*
8882          * As i40e supports less than 64 flow types, only first 64 bits need to
8883          * be checked.
8884          */
8885         mask0 = g_cfg->valid_bit_mask[0];
8886         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8887                 if (i == 0) {
8888                         /* Check if any unsupported flow type configured */
8889                         if ((mask0 | i40e_mask) ^ i40e_mask)
8890                                 goto mask_err;
8891                 } else {
8892                         if (g_cfg->valid_bit_mask[i])
8893                                 goto mask_err;
8894                 }
8895         }
8896
8897         return 0;
8898
8899 mask_err:
8900         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8901
8902         return -EINVAL;
8903 }
8904
8905 /*
8906  * Set global configurations of hash function type and symmetric hash enable
8907  * per flow type (pctype). Note any modifying global configuration will affect
8908  * all the ports on the same NIC.
8909  */
8910 static int
8911 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8912                                    struct rte_eth_hash_global_conf *g_cfg)
8913 {
8914         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8915         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8916         int ret;
8917         uint16_t i, j;
8918         uint32_t reg;
8919         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8920
8921         if (pf->support_multi_driver) {
8922                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8923                 return -ENOTSUP;
8924         }
8925
8926         /* Check the input parameters */
8927         ret = i40e_hash_global_config_check(adapter, g_cfg);
8928         if (ret < 0)
8929                 return ret;
8930
8931         /*
8932          * As i40e supports less than 64 flow types, only first 64 bits need to
8933          * be configured.
8934          */
8935         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8936                 if (mask0 & (1UL << i)) {
8937                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8938                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8939
8940                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8941                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8942                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8943                                         i40e_write_global_rx_ctl(hw,
8944                                                           I40E_GLQF_HSYM(j),
8945                                                           reg);
8946                         }
8947                 }
8948         }
8949
8950         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8951         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8952                 /* Toeplitz */
8953                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8954                         PMD_DRV_LOG(DEBUG,
8955                                 "Hash function already set to Toeplitz");
8956                         goto out;
8957                 }
8958                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8959         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8960                 /* Simple XOR */
8961                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8962                         PMD_DRV_LOG(DEBUG,
8963                                 "Hash function already set to Simple XOR");
8964                         goto out;
8965                 }
8966                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8967         } else
8968                 /* Use the default, and keep it as it is */
8969                 goto out;
8970
8971         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8972
8973 out:
8974         I40E_WRITE_FLUSH(hw);
8975
8976         return 0;
8977 }
8978
8979 /**
8980  * Valid input sets for hash and flow director filters per PCTYPE
8981  */
8982 static uint64_t
8983 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8984                 enum rte_filter_type filter)
8985 {
8986         uint64_t valid;
8987
8988         static const uint64_t valid_hash_inset_table[] = {
8989                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8990                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8991                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8992                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8993                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8994                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8995                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8996                         I40E_INSET_FLEX_PAYLOAD,
8997                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8998                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8999                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9000                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9001                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9002                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9003                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9004                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9005                         I40E_INSET_FLEX_PAYLOAD,
9006                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9007                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9008                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9009                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9010                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9011                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9012                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9013                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9014                         I40E_INSET_FLEX_PAYLOAD,
9015                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9016                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9017                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9018                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9019                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9020                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9021                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9022                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9023                         I40E_INSET_FLEX_PAYLOAD,
9024                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9025                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9026                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9027                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9028                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9029                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9030                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9031                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9032                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9033                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9034                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9035                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9036                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9037                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9038                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9039                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9040                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9041                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9042                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9043                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9044                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9045                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9046                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9047                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9048                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9049                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9050                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9051                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9052                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9053                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9054                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9055                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9056                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9057                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9058                         I40E_INSET_FLEX_PAYLOAD,
9059                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9060                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9061                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9062                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9063                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9064                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9065                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9066                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9067                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9068                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9069                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9070                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9071                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9072                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9073                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9074                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9075                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9076                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9077                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9078                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9079                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9080                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9081                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9082                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9083                         I40E_INSET_FLEX_PAYLOAD,
9084                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9085                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9086                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9087                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9088                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9089                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9090                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9091                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9092                         I40E_INSET_FLEX_PAYLOAD,
9093                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9094                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9095                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9096                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9097                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9098                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9099                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9100                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9101                         I40E_INSET_FLEX_PAYLOAD,
9102                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9103                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9104                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9105                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9106                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9107                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9108                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9109                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9110                         I40E_INSET_FLEX_PAYLOAD,
9111                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9112                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9113                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9114                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9115                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9116                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9117                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9118                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9119                         I40E_INSET_FLEX_PAYLOAD,
9120                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9121                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9122                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9123                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9124                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9125                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9126                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9127                         I40E_INSET_FLEX_PAYLOAD,
9128                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9129                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9130                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9131                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9132                         I40E_INSET_FLEX_PAYLOAD,
9133         };
9134
9135         /**
9136          * Flow director supports only fields defined in
9137          * union rte_eth_fdir_flow.
9138          */
9139         static const uint64_t valid_fdir_inset_table[] = {
9140                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9141                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9142                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9143                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9144                 I40E_INSET_IPV4_TTL,
9145                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9146                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9147                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9148                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9149                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9150                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9151                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9152                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9153                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9154                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9155                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9156                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9157                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9158                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9159                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9160                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9161                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9162                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9163                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9164                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9165                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9166                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9167                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9168                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9169                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9170                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9171                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9172                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9173                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9174                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9175                 I40E_INSET_SCTP_VT,
9176                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9177                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9178                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9179                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9180                 I40E_INSET_IPV4_TTL,
9181                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9182                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9183                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9184                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9185                 I40E_INSET_IPV6_HOP_LIMIT,
9186                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9187                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9188                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9189                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9190                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9191                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9192                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9193                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9194                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9195                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9196                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9197                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9198                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9199                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9200                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9201                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9202                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9203                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9204                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9205                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9206                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9207                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9208                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9209                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9210                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9211                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9212                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9213                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9214                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9215                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9216                 I40E_INSET_SCTP_VT,
9217                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9218                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9219                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9220                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9221                 I40E_INSET_IPV6_HOP_LIMIT,
9222                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9223                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9224                 I40E_INSET_LAST_ETHER_TYPE,
9225         };
9226
9227         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9228                 return 0;
9229         if (filter == RTE_ETH_FILTER_HASH)
9230                 valid = valid_hash_inset_table[pctype];
9231         else
9232                 valid = valid_fdir_inset_table[pctype];
9233
9234         return valid;
9235 }
9236
9237 /**
9238  * Validate if the input set is allowed for a specific PCTYPE
9239  */
9240 int
9241 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9242                 enum rte_filter_type filter, uint64_t inset)
9243 {
9244         uint64_t valid;
9245
9246         valid = i40e_get_valid_input_set(pctype, filter);
9247         if (inset & (~valid))
9248                 return -EINVAL;
9249
9250         return 0;
9251 }
9252
9253 /* default input set fields combination per pctype */
9254 uint64_t
9255 i40e_get_default_input_set(uint16_t pctype)
9256 {
9257         static const uint64_t default_inset_table[] = {
9258                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9259                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9260                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9261                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9262                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9263                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9264                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9265                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9266                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9267                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9268                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9269                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9270                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9271                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9272                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9273                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9274                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9275                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9276                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9277                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9278                         I40E_INSET_SCTP_VT,
9279                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9280                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9281                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9282                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9283                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9284                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9285                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9286                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9287                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9288                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9289                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9290                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9291                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9292                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9293                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9294                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9295                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9296                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9297                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9298                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9299                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9300                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9301                         I40E_INSET_SCTP_VT,
9302                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9303                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9304                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9305                         I40E_INSET_LAST_ETHER_TYPE,
9306         };
9307
9308         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9309                 return 0;
9310
9311         return default_inset_table[pctype];
9312 }
9313
9314 /**
9315  * Parse the input set from index to logical bit masks
9316  */
9317 static int
9318 i40e_parse_input_set(uint64_t *inset,
9319                      enum i40e_filter_pctype pctype,
9320                      enum rte_eth_input_set_field *field,
9321                      uint16_t size)
9322 {
9323         uint16_t i, j;
9324         int ret = -EINVAL;
9325
9326         static const struct {
9327                 enum rte_eth_input_set_field field;
9328                 uint64_t inset;
9329         } inset_convert_table[] = {
9330                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9331                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9332                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9333                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9334                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9335                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9336                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9337                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9338                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9339                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9340                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9341                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9342                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9343                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9344                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9345                         I40E_INSET_IPV6_NEXT_HDR},
9346                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9347                         I40E_INSET_IPV6_HOP_LIMIT},
9348                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9349                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9350                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9351                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9352                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9353                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9354                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9355                         I40E_INSET_SCTP_VT},
9356                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9357                         I40E_INSET_TUNNEL_DMAC},
9358                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9359                         I40E_INSET_VLAN_TUNNEL},
9360                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9361                         I40E_INSET_TUNNEL_ID},
9362                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9363                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9364                         I40E_INSET_FLEX_PAYLOAD_W1},
9365                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9366                         I40E_INSET_FLEX_PAYLOAD_W2},
9367                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9368                         I40E_INSET_FLEX_PAYLOAD_W3},
9369                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9370                         I40E_INSET_FLEX_PAYLOAD_W4},
9371                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9372                         I40E_INSET_FLEX_PAYLOAD_W5},
9373                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9374                         I40E_INSET_FLEX_PAYLOAD_W6},
9375                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9376                         I40E_INSET_FLEX_PAYLOAD_W7},
9377                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9378                         I40E_INSET_FLEX_PAYLOAD_W8},
9379         };
9380
9381         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9382                 return ret;
9383
9384         /* Only one item allowed for default or all */
9385         if (size == 1) {
9386                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9387                         *inset = i40e_get_default_input_set(pctype);
9388                         return 0;
9389                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9390                         *inset = I40E_INSET_NONE;
9391                         return 0;
9392                 }
9393         }
9394
9395         for (i = 0, *inset = 0; i < size; i++) {
9396                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9397                         if (field[i] == inset_convert_table[j].field) {
9398                                 *inset |= inset_convert_table[j].inset;
9399                                 break;
9400                         }
9401                 }
9402
9403                 /* It contains unsupported input set, return immediately */
9404                 if (j == RTE_DIM(inset_convert_table))
9405                         return ret;
9406         }
9407
9408         return 0;
9409 }
9410
9411 /**
9412  * Translate the input set from bit masks to register aware bit masks
9413  * and vice versa
9414  */
9415 uint64_t
9416 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9417 {
9418         uint64_t val = 0;
9419         uint16_t i;
9420
9421         struct inset_map {
9422                 uint64_t inset;
9423                 uint64_t inset_reg;
9424         };
9425
9426         static const struct inset_map inset_map_common[] = {
9427                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9428                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9429                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9430                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9431                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9432                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9433                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9434                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9435                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9436                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9437                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9438                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9439                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9440                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9441                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9442                 {I40E_INSET_TUNNEL_DMAC,
9443                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9444                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9445                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9446                 {I40E_INSET_TUNNEL_SRC_PORT,
9447                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9448                 {I40E_INSET_TUNNEL_DST_PORT,
9449                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9450                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9451                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9452                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9453                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9454                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9455                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9456                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9457                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9458                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9459         };
9460
9461     /* some different registers map in x722*/
9462         static const struct inset_map inset_map_diff_x722[] = {
9463                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9464                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9465                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9466                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9467         };
9468
9469         static const struct inset_map inset_map_diff_not_x722[] = {
9470                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9471                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9472                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9473                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9474         };
9475
9476         if (input == 0)
9477                 return val;
9478
9479         /* Translate input set to register aware inset */
9480         if (type == I40E_MAC_X722) {
9481                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9482                         if (input & inset_map_diff_x722[i].inset)
9483                                 val |= inset_map_diff_x722[i].inset_reg;
9484                 }
9485         } else {
9486                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9487                         if (input & inset_map_diff_not_x722[i].inset)
9488                                 val |= inset_map_diff_not_x722[i].inset_reg;
9489                 }
9490         }
9491
9492         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9493                 if (input & inset_map_common[i].inset)
9494                         val |= inset_map_common[i].inset_reg;
9495         }
9496
9497         return val;
9498 }
9499
9500 int
9501 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9502 {
9503         uint8_t i, idx = 0;
9504         uint64_t inset_need_mask = inset;
9505
9506         static const struct {
9507                 uint64_t inset;
9508                 uint32_t mask;
9509         } inset_mask_map[] = {
9510                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9511                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9512                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9513                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9514                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9515                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9516                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9517                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9518         };
9519
9520         if (!inset || !mask || !nb_elem)
9521                 return 0;
9522
9523         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9524                 /* Clear the inset bit, if no MASK is required,
9525                  * for example proto + ttl
9526                  */
9527                 if ((inset & inset_mask_map[i].inset) ==
9528                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9529                         inset_need_mask &= ~inset_mask_map[i].inset;
9530                 if (!inset_need_mask)
9531                         return 0;
9532         }
9533         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9534                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9535                     inset_mask_map[i].inset) {
9536                         if (idx >= nb_elem) {
9537                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9538                                 return -EINVAL;
9539                         }
9540                         mask[idx] = inset_mask_map[i].mask;
9541                         idx++;
9542                 }
9543         }
9544
9545         return idx;
9546 }
9547
9548 void
9549 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9550 {
9551         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9552
9553         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9554         if (reg != val)
9555                 i40e_write_rx_ctl(hw, addr, val);
9556         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9557                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9558 }
9559
9560 void
9561 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9562 {
9563         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9564         struct rte_eth_dev *dev;
9565
9566         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9567         if (reg != val) {
9568                 i40e_write_rx_ctl(hw, addr, val);
9569                 PMD_DRV_LOG(WARNING,
9570                             "i40e device %s changed global register [0x%08x]."
9571                             " original: 0x%08x, new: 0x%08x",
9572                             dev->device->name, addr, reg,
9573                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9574         }
9575 }
9576
9577 static void
9578 i40e_filter_input_set_init(struct i40e_pf *pf)
9579 {
9580         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9581         enum i40e_filter_pctype pctype;
9582         uint64_t input_set, inset_reg;
9583         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9584         int num, i;
9585         uint16_t flow_type;
9586
9587         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9588              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9589                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9590
9591                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9592                         continue;
9593
9594                 input_set = i40e_get_default_input_set(pctype);
9595
9596                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9597                                                    I40E_INSET_MASK_NUM_REG);
9598                 if (num < 0)
9599                         return;
9600                 if (pf->support_multi_driver && num > 0) {
9601                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9602                         return;
9603                 }
9604                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9605                                         input_set);
9606
9607                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9608                                       (uint32_t)(inset_reg & UINT32_MAX));
9609                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9610                                      (uint32_t)((inset_reg >>
9611                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9612                 if (!pf->support_multi_driver) {
9613                         i40e_check_write_global_reg(hw,
9614                                             I40E_GLQF_HASH_INSET(0, pctype),
9615                                             (uint32_t)(inset_reg & UINT32_MAX));
9616                         i40e_check_write_global_reg(hw,
9617                                              I40E_GLQF_HASH_INSET(1, pctype),
9618                                              (uint32_t)((inset_reg >>
9619                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9620
9621                         for (i = 0; i < num; i++) {
9622                                 i40e_check_write_global_reg(hw,
9623                                                     I40E_GLQF_FD_MSK(i, pctype),
9624                                                     mask_reg[i]);
9625                                 i40e_check_write_global_reg(hw,
9626                                                   I40E_GLQF_HASH_MSK(i, pctype),
9627                                                   mask_reg[i]);
9628                         }
9629                         /*clear unused mask registers of the pctype */
9630                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9631                                 i40e_check_write_global_reg(hw,
9632                                                     I40E_GLQF_FD_MSK(i, pctype),
9633                                                     0);
9634                                 i40e_check_write_global_reg(hw,
9635                                                   I40E_GLQF_HASH_MSK(i, pctype),
9636                                                   0);
9637                         }
9638                 } else {
9639                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9640                 }
9641                 I40E_WRITE_FLUSH(hw);
9642
9643                 /* store the default input set */
9644                 if (!pf->support_multi_driver)
9645                         pf->hash_input_set[pctype] = input_set;
9646                 pf->fdir.input_set[pctype] = input_set;
9647         }
9648 }
9649
9650 int
9651 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9652                          struct rte_eth_input_set_conf *conf)
9653 {
9654         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9655         enum i40e_filter_pctype pctype;
9656         uint64_t input_set, inset_reg = 0;
9657         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9658         int ret, i, num;
9659
9660         if (!conf) {
9661                 PMD_DRV_LOG(ERR, "Invalid pointer");
9662                 return -EFAULT;
9663         }
9664         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9665             conf->op != RTE_ETH_INPUT_SET_ADD) {
9666                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9667                 return -EINVAL;
9668         }
9669
9670         if (pf->support_multi_driver) {
9671                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9672                 return -ENOTSUP;
9673         }
9674
9675         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9676         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9677                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9678                 return -EINVAL;
9679         }
9680
9681         if (hw->mac.type == I40E_MAC_X722) {
9682                 /* get translated pctype value in fd pctype register */
9683                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9684                         I40E_GLQF_FD_PCTYPES((int)pctype));
9685         }
9686
9687         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9688                                    conf->inset_size);
9689         if (ret) {
9690                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9691                 return -EINVAL;
9692         }
9693
9694         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9695                 /* get inset value in register */
9696                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9697                 inset_reg <<= I40E_32_BIT_WIDTH;
9698                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9699                 input_set |= pf->hash_input_set[pctype];
9700         }
9701         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9702                                            I40E_INSET_MASK_NUM_REG);
9703         if (num < 0)
9704                 return -EINVAL;
9705
9706         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9707
9708         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9709                                     (uint32_t)(inset_reg & UINT32_MAX));
9710         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9711                                     (uint32_t)((inset_reg >>
9712                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9713
9714         for (i = 0; i < num; i++)
9715                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9716                                             mask_reg[i]);
9717         /*clear unused mask registers of the pctype */
9718         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9719                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9720                                             0);
9721         I40E_WRITE_FLUSH(hw);
9722
9723         pf->hash_input_set[pctype] = input_set;
9724         return 0;
9725 }
9726
9727 int
9728 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9729                          struct rte_eth_input_set_conf *conf)
9730 {
9731         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9732         enum i40e_filter_pctype pctype;
9733         uint64_t input_set, inset_reg = 0;
9734         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9735         int ret, i, num;
9736
9737         if (!hw || !conf) {
9738                 PMD_DRV_LOG(ERR, "Invalid pointer");
9739                 return -EFAULT;
9740         }
9741         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9742             conf->op != RTE_ETH_INPUT_SET_ADD) {
9743                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9744                 return -EINVAL;
9745         }
9746
9747         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9748
9749         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9750                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9751                 return -EINVAL;
9752         }
9753
9754         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9755                                    conf->inset_size);
9756         if (ret) {
9757                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9758                 return -EINVAL;
9759         }
9760
9761         /* get inset value in register */
9762         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9763         inset_reg <<= I40E_32_BIT_WIDTH;
9764         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9765
9766         /* Can not change the inset reg for flex payload for fdir,
9767          * it is done by writing I40E_PRTQF_FD_FLXINSET
9768          * in i40e_set_flex_mask_on_pctype.
9769          */
9770         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9771                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9772         else
9773                 input_set |= pf->fdir.input_set[pctype];
9774         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9775                                            I40E_INSET_MASK_NUM_REG);
9776         if (num < 0)
9777                 return -EINVAL;
9778         if (pf->support_multi_driver && num > 0) {
9779                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9780                 return -ENOTSUP;
9781         }
9782
9783         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9784
9785         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9786                               (uint32_t)(inset_reg & UINT32_MAX));
9787         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9788                              (uint32_t)((inset_reg >>
9789                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9790
9791         if (!pf->support_multi_driver) {
9792                 for (i = 0; i < num; i++)
9793                         i40e_check_write_global_reg(hw,
9794                                                     I40E_GLQF_FD_MSK(i, pctype),
9795                                                     mask_reg[i]);
9796                 /*clear unused mask registers of the pctype */
9797                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9798                         i40e_check_write_global_reg(hw,
9799                                                     I40E_GLQF_FD_MSK(i, pctype),
9800                                                     0);
9801         } else {
9802                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9803         }
9804         I40E_WRITE_FLUSH(hw);
9805
9806         pf->fdir.input_set[pctype] = input_set;
9807         return 0;
9808 }
9809
9810 static int
9811 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9812 {
9813         int ret = 0;
9814
9815         if (!hw || !info) {
9816                 PMD_DRV_LOG(ERR, "Invalid pointer");
9817                 return -EFAULT;
9818         }
9819
9820         switch (info->info_type) {
9821         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9822                 i40e_get_symmetric_hash_enable_per_port(hw,
9823                                         &(info->info.enable));
9824                 break;
9825         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9826                 ret = i40e_get_hash_filter_global_config(hw,
9827                                 &(info->info.global_conf));
9828                 break;
9829         default:
9830                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9831                                                         info->info_type);
9832                 ret = -EINVAL;
9833                 break;
9834         }
9835
9836         return ret;
9837 }
9838
9839 static int
9840 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9841 {
9842         int ret = 0;
9843
9844         if (!hw || !info) {
9845                 PMD_DRV_LOG(ERR, "Invalid pointer");
9846                 return -EFAULT;
9847         }
9848
9849         switch (info->info_type) {
9850         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9851                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9852                 break;
9853         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9854                 ret = i40e_set_hash_filter_global_config(hw,
9855                                 &(info->info.global_conf));
9856                 break;
9857         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9858                 ret = i40e_hash_filter_inset_select(hw,
9859                                                &(info->info.input_set_conf));
9860                 break;
9861
9862         default:
9863                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9864                                                         info->info_type);
9865                 ret = -EINVAL;
9866                 break;
9867         }
9868
9869         return ret;
9870 }
9871
9872 /* Operations for hash function */
9873 static int
9874 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9875                       enum rte_filter_op filter_op,
9876                       void *arg)
9877 {
9878         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9879         int ret = 0;
9880
9881         switch (filter_op) {
9882         case RTE_ETH_FILTER_NOP:
9883                 break;
9884         case RTE_ETH_FILTER_GET:
9885                 ret = i40e_hash_filter_get(hw,
9886                         (struct rte_eth_hash_filter_info *)arg);
9887                 break;
9888         case RTE_ETH_FILTER_SET:
9889                 ret = i40e_hash_filter_set(hw,
9890                         (struct rte_eth_hash_filter_info *)arg);
9891                 break;
9892         default:
9893                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9894                                                                 filter_op);
9895                 ret = -ENOTSUP;
9896                 break;
9897         }
9898
9899         return ret;
9900 }
9901
9902 /* Convert ethertype filter structure */
9903 static int
9904 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9905                               struct i40e_ethertype_filter *filter)
9906 {
9907         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9908                 RTE_ETHER_ADDR_LEN);
9909         filter->input.ether_type = input->ether_type;
9910         filter->flags = input->flags;
9911         filter->queue = input->queue;
9912
9913         return 0;
9914 }
9915
9916 /* Check if there exists the ehtertype filter */
9917 struct i40e_ethertype_filter *
9918 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9919                                 const struct i40e_ethertype_filter_input *input)
9920 {
9921         int ret;
9922
9923         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9924         if (ret < 0)
9925                 return NULL;
9926
9927         return ethertype_rule->hash_map[ret];
9928 }
9929
9930 /* Add ethertype filter in SW list */
9931 static int
9932 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9933                                 struct i40e_ethertype_filter *filter)
9934 {
9935         struct i40e_ethertype_rule *rule = &pf->ethertype;
9936         int ret;
9937
9938         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9939         if (ret < 0) {
9940                 PMD_DRV_LOG(ERR,
9941                             "Failed to insert ethertype filter"
9942                             " to hash table %d!",
9943                             ret);
9944                 return ret;
9945         }
9946         rule->hash_map[ret] = filter;
9947
9948         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9949
9950         return 0;
9951 }
9952
9953 /* Delete ethertype filter in SW list */
9954 int
9955 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9956                              struct i40e_ethertype_filter_input *input)
9957 {
9958         struct i40e_ethertype_rule *rule = &pf->ethertype;
9959         struct i40e_ethertype_filter *filter;
9960         int ret;
9961
9962         ret = rte_hash_del_key(rule->hash_table, input);
9963         if (ret < 0) {
9964                 PMD_DRV_LOG(ERR,
9965                             "Failed to delete ethertype filter"
9966                             " to hash table %d!",
9967                             ret);
9968                 return ret;
9969         }
9970         filter = rule->hash_map[ret];
9971         rule->hash_map[ret] = NULL;
9972
9973         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9974         rte_free(filter);
9975
9976         return 0;
9977 }
9978
9979 /*
9980  * Configure ethertype filter, which can director packet by filtering
9981  * with mac address and ether_type or only ether_type
9982  */
9983 int
9984 i40e_ethertype_filter_set(struct i40e_pf *pf,
9985                         struct rte_eth_ethertype_filter *filter,
9986                         bool add)
9987 {
9988         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9989         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9990         struct i40e_ethertype_filter *ethertype_filter, *node;
9991         struct i40e_ethertype_filter check_filter;
9992         struct i40e_control_filter_stats stats;
9993         uint16_t flags = 0;
9994         int ret;
9995
9996         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9997                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9998                 return -EINVAL;
9999         }
10000         if (filter->ether_type == RTE_ETHER_TYPE_IPv4 ||
10001                 filter->ether_type == RTE_ETHER_TYPE_IPv6) {
10002                 PMD_DRV_LOG(ERR,
10003                         "unsupported ether_type(0x%04x) in control packet filter.",
10004                         filter->ether_type);
10005                 return -EINVAL;
10006         }
10007         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10008                 PMD_DRV_LOG(WARNING,
10009                         "filter vlan ether_type in first tag is not supported.");
10010
10011         /* Check if there is the filter in SW list */
10012         memset(&check_filter, 0, sizeof(check_filter));
10013         i40e_ethertype_filter_convert(filter, &check_filter);
10014         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10015                                                &check_filter.input);
10016         if (add && node) {
10017                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10018                 return -EINVAL;
10019         }
10020
10021         if (!add && !node) {
10022                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10023                 return -EINVAL;
10024         }
10025
10026         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10027                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10028         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10029                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10030         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10031
10032         memset(&stats, 0, sizeof(stats));
10033         ret = i40e_aq_add_rem_control_packet_filter(hw,
10034                         filter->mac_addr.addr_bytes,
10035                         filter->ether_type, flags,
10036                         pf->main_vsi->seid,
10037                         filter->queue, add, &stats, NULL);
10038
10039         PMD_DRV_LOG(INFO,
10040                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10041                 ret, stats.mac_etype_used, stats.etype_used,
10042                 stats.mac_etype_free, stats.etype_free);
10043         if (ret < 0)
10044                 return -ENOSYS;
10045
10046         /* Add or delete a filter in SW list */
10047         if (add) {
10048                 ethertype_filter = rte_zmalloc("ethertype_filter",
10049                                        sizeof(*ethertype_filter), 0);
10050                 if (ethertype_filter == NULL) {
10051                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10052                         return -ENOMEM;
10053                 }
10054
10055                 rte_memcpy(ethertype_filter, &check_filter,
10056                            sizeof(check_filter));
10057                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10058                 if (ret < 0)
10059                         rte_free(ethertype_filter);
10060         } else {
10061                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10062         }
10063
10064         return ret;
10065 }
10066
10067 /*
10068  * Handle operations for ethertype filter.
10069  */
10070 static int
10071 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10072                                 enum rte_filter_op filter_op,
10073                                 void *arg)
10074 {
10075         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10076         int ret = 0;
10077
10078         if (filter_op == RTE_ETH_FILTER_NOP)
10079                 return ret;
10080
10081         if (arg == NULL) {
10082                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10083                             filter_op);
10084                 return -EINVAL;
10085         }
10086
10087         switch (filter_op) {
10088         case RTE_ETH_FILTER_ADD:
10089                 ret = i40e_ethertype_filter_set(pf,
10090                         (struct rte_eth_ethertype_filter *)arg,
10091                         TRUE);
10092                 break;
10093         case RTE_ETH_FILTER_DELETE:
10094                 ret = i40e_ethertype_filter_set(pf,
10095                         (struct rte_eth_ethertype_filter *)arg,
10096                         FALSE);
10097                 break;
10098         default:
10099                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10100                 ret = -ENOSYS;
10101                 break;
10102         }
10103         return ret;
10104 }
10105
10106 static int
10107 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10108                      enum rte_filter_type filter_type,
10109                      enum rte_filter_op filter_op,
10110                      void *arg)
10111 {
10112         int ret = 0;
10113
10114         if (dev == NULL)
10115                 return -EINVAL;
10116
10117         switch (filter_type) {
10118         case RTE_ETH_FILTER_NONE:
10119                 /* For global configuration */
10120                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10121                 break;
10122         case RTE_ETH_FILTER_HASH:
10123                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10124                 break;
10125         case RTE_ETH_FILTER_MACVLAN:
10126                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10127                 break;
10128         case RTE_ETH_FILTER_ETHERTYPE:
10129                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10130                 break;
10131         case RTE_ETH_FILTER_TUNNEL:
10132                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10133                 break;
10134         case RTE_ETH_FILTER_FDIR:
10135                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10136                 break;
10137         case RTE_ETH_FILTER_GENERIC:
10138                 if (filter_op != RTE_ETH_FILTER_GET)
10139                         return -EINVAL;
10140                 *(const void **)arg = &i40e_flow_ops;
10141                 break;
10142         default:
10143                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10144                                                         filter_type);
10145                 ret = -EINVAL;
10146                 break;
10147         }
10148
10149         return ret;
10150 }
10151
10152 /*
10153  * Check and enable Extended Tag.
10154  * Enabling Extended Tag is important for 40G performance.
10155  */
10156 static void
10157 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10158 {
10159         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10160         uint32_t buf = 0;
10161         int ret;
10162
10163         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10164                                       PCI_DEV_CAP_REG);
10165         if (ret < 0) {
10166                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10167                             PCI_DEV_CAP_REG);
10168                 return;
10169         }
10170         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10171                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10172                 return;
10173         }
10174
10175         buf = 0;
10176         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10177                                       PCI_DEV_CTRL_REG);
10178         if (ret < 0) {
10179                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10180                             PCI_DEV_CTRL_REG);
10181                 return;
10182         }
10183         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10184                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10185                 return;
10186         }
10187         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10188         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10189                                        PCI_DEV_CTRL_REG);
10190         if (ret < 0) {
10191                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10192                             PCI_DEV_CTRL_REG);
10193                 return;
10194         }
10195 }
10196
10197 /*
10198  * As some registers wouldn't be reset unless a global hardware reset,
10199  * hardware initialization is needed to put those registers into an
10200  * expected initial state.
10201  */
10202 static void
10203 i40e_hw_init(struct rte_eth_dev *dev)
10204 {
10205         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10206
10207         i40e_enable_extended_tag(dev);
10208
10209         /* clear the PF Queue Filter control register */
10210         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10211
10212         /* Disable symmetric hash per port */
10213         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10214 }
10215
10216 /*
10217  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10218  * however this function will return only one highest pctype index,
10219  * which is not quite correct. This is known problem of i40e driver
10220  * and needs to be fixed later.
10221  */
10222 enum i40e_filter_pctype
10223 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10224 {
10225         int i;
10226         uint64_t pctype_mask;
10227
10228         if (flow_type < I40E_FLOW_TYPE_MAX) {
10229                 pctype_mask = adapter->pctypes_tbl[flow_type];
10230                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10231                         if (pctype_mask & (1ULL << i))
10232                                 return (enum i40e_filter_pctype)i;
10233                 }
10234         }
10235         return I40E_FILTER_PCTYPE_INVALID;
10236 }
10237
10238 uint16_t
10239 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10240                         enum i40e_filter_pctype pctype)
10241 {
10242         uint16_t flowtype;
10243         uint64_t pctype_mask = 1ULL << pctype;
10244
10245         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10246              flowtype++) {
10247                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10248                         return flowtype;
10249         }
10250
10251         return RTE_ETH_FLOW_UNKNOWN;
10252 }
10253
10254 /*
10255  * On X710, performance number is far from the expectation on recent firmware
10256  * versions; on XL710, performance number is also far from the expectation on
10257  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10258  * mode is enabled and port MAC address is equal to the packet destination MAC
10259  * address. The fix for this issue may not be integrated in the following
10260  * firmware version. So the workaround in software driver is needed. It needs
10261  * to modify the initial values of 3 internal only registers for both X710 and
10262  * XL710. Note that the values for X710 or XL710 could be different, and the
10263  * workaround can be removed when it is fixed in firmware in the future.
10264  */
10265
10266 /* For both X710 and XL710 */
10267 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10268 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10269 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10270
10271 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10272 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10273
10274 /* For X722 */
10275 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10276 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10277
10278 /* For X710 */
10279 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10280 /* For XL710 */
10281 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10282 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10283
10284 /*
10285  * GL_SWR_PM_UP_THR:
10286  * The value is not impacted from the link speed, its value is set according
10287  * to the total number of ports for a better pipe-monitor configuration.
10288  */
10289 static bool
10290 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10291 {
10292 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10293                 .device_id = (dev),   \
10294                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10295
10296 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10297                 .device_id = (dev),   \
10298                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10299
10300         static const struct {
10301                 uint16_t device_id;
10302                 uint32_t val;
10303         } swr_pm_table[] = {
10304                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10305                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10306                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10307                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10308
10309                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10310                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10311                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10312                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10313                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10314                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10315                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10316         };
10317         uint32_t i;
10318
10319         if (value == NULL) {
10320                 PMD_DRV_LOG(ERR, "value is NULL");
10321                 return false;
10322         }
10323
10324         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10325                 if (hw->device_id == swr_pm_table[i].device_id) {
10326                         *value = swr_pm_table[i].val;
10327
10328                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10329                                     "value - 0x%08x",
10330                                     hw->device_id, *value);
10331                         return true;
10332                 }
10333         }
10334
10335         return false;
10336 }
10337
10338 static int
10339 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10340 {
10341         enum i40e_status_code status;
10342         struct i40e_aq_get_phy_abilities_resp phy_ab;
10343         int ret = -ENOTSUP;
10344         int retries = 0;
10345
10346         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10347                                               NULL);
10348
10349         while (status) {
10350                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10351                         status);
10352                 retries++;
10353                 rte_delay_us(100000);
10354                 if  (retries < 5)
10355                         status = i40e_aq_get_phy_capabilities(hw, false,
10356                                         true, &phy_ab, NULL);
10357                 else
10358                         return ret;
10359         }
10360         return 0;
10361 }
10362
10363 static void
10364 i40e_configure_registers(struct i40e_hw *hw)
10365 {
10366         static struct {
10367                 uint32_t addr;
10368                 uint64_t val;
10369         } reg_table[] = {
10370                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10371                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10372                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10373         };
10374         uint64_t reg;
10375         uint32_t i;
10376         int ret;
10377
10378         for (i = 0; i < RTE_DIM(reg_table); i++) {
10379                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10380                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10381                                 reg_table[i].val =
10382                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10383                         else /* For X710/XL710/XXV710 */
10384                                 if (hw->aq.fw_maj_ver < 6)
10385                                         reg_table[i].val =
10386                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10387                                 else
10388                                         reg_table[i].val =
10389                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10390                 }
10391
10392                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10393                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10394                                 reg_table[i].val =
10395                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10396                         else /* For X710/XL710/XXV710 */
10397                                 reg_table[i].val =
10398                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10399                 }
10400
10401                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10402                         uint32_t cfg_val;
10403
10404                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10405                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10406                                             "GL_SWR_PM_UP_THR value fixup",
10407                                             hw->device_id);
10408                                 continue;
10409                         }
10410
10411                         reg_table[i].val = cfg_val;
10412                 }
10413
10414                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10415                                                         &reg, NULL);
10416                 if (ret < 0) {
10417                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10418                                                         reg_table[i].addr);
10419                         break;
10420                 }
10421                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10422                                                 reg_table[i].addr, reg);
10423                 if (reg == reg_table[i].val)
10424                         continue;
10425
10426                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10427                                                 reg_table[i].val, NULL);
10428                 if (ret < 0) {
10429                         PMD_DRV_LOG(ERR,
10430                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10431                                 reg_table[i].val, reg_table[i].addr);
10432                         break;
10433                 }
10434                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10435                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10436         }
10437 }
10438
10439 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10440 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10441 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10442 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10443 static int
10444 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10445 {
10446         uint32_t reg;
10447         int ret;
10448
10449         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10450                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10451                 return -EINVAL;
10452         }
10453
10454         /* Configure for double VLAN RX stripping */
10455         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10456         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10457                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10458                 ret = i40e_aq_debug_write_register(hw,
10459                                                    I40E_VSI_TSR(vsi->vsi_id),
10460                                                    reg, NULL);
10461                 if (ret < 0) {
10462                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10463                                     vsi->vsi_id);
10464                         return I40E_ERR_CONFIG;
10465                 }
10466         }
10467
10468         /* Configure for double VLAN TX insertion */
10469         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10470         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10471                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10472                 ret = i40e_aq_debug_write_register(hw,
10473                                                    I40E_VSI_L2TAGSTXVALID(
10474                                                    vsi->vsi_id), reg, NULL);
10475                 if (ret < 0) {
10476                         PMD_DRV_LOG(ERR,
10477                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10478                                 vsi->vsi_id);
10479                         return I40E_ERR_CONFIG;
10480                 }
10481         }
10482
10483         return 0;
10484 }
10485
10486 /**
10487  * i40e_aq_add_mirror_rule
10488  * @hw: pointer to the hardware structure
10489  * @seid: VEB seid to add mirror rule to
10490  * @dst_id: destination vsi seid
10491  * @entries: Buffer which contains the entities to be mirrored
10492  * @count: number of entities contained in the buffer
10493  * @rule_id:the rule_id of the rule to be added
10494  *
10495  * Add a mirror rule for a given veb.
10496  *
10497  **/
10498 static enum i40e_status_code
10499 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10500                         uint16_t seid, uint16_t dst_id,
10501                         uint16_t rule_type, uint16_t *entries,
10502                         uint16_t count, uint16_t *rule_id)
10503 {
10504         struct i40e_aq_desc desc;
10505         struct i40e_aqc_add_delete_mirror_rule cmd;
10506         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10507                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10508                 &desc.params.raw;
10509         uint16_t buff_len;
10510         enum i40e_status_code status;
10511
10512         i40e_fill_default_direct_cmd_desc(&desc,
10513                                           i40e_aqc_opc_add_mirror_rule);
10514         memset(&cmd, 0, sizeof(cmd));
10515
10516         buff_len = sizeof(uint16_t) * count;
10517         desc.datalen = rte_cpu_to_le_16(buff_len);
10518         if (buff_len > 0)
10519                 desc.flags |= rte_cpu_to_le_16(
10520                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10521         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10522                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10523         cmd.num_entries = rte_cpu_to_le_16(count);
10524         cmd.seid = rte_cpu_to_le_16(seid);
10525         cmd.destination = rte_cpu_to_le_16(dst_id);
10526
10527         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10528         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10529         PMD_DRV_LOG(INFO,
10530                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10531                 hw->aq.asq_last_status, resp->rule_id,
10532                 resp->mirror_rules_used, resp->mirror_rules_free);
10533         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10534
10535         return status;
10536 }
10537
10538 /**
10539  * i40e_aq_del_mirror_rule
10540  * @hw: pointer to the hardware structure
10541  * @seid: VEB seid to add mirror rule to
10542  * @entries: Buffer which contains the entities to be mirrored
10543  * @count: number of entities contained in the buffer
10544  * @rule_id:the rule_id of the rule to be delete
10545  *
10546  * Delete a mirror rule for a given veb.
10547  *
10548  **/
10549 static enum i40e_status_code
10550 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10551                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10552                 uint16_t count, uint16_t rule_id)
10553 {
10554         struct i40e_aq_desc desc;
10555         struct i40e_aqc_add_delete_mirror_rule cmd;
10556         uint16_t buff_len = 0;
10557         enum i40e_status_code status;
10558         void *buff = NULL;
10559
10560         i40e_fill_default_direct_cmd_desc(&desc,
10561                                           i40e_aqc_opc_delete_mirror_rule);
10562         memset(&cmd, 0, sizeof(cmd));
10563         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10564                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10565                                                           I40E_AQ_FLAG_RD));
10566                 cmd.num_entries = count;
10567                 buff_len = sizeof(uint16_t) * count;
10568                 desc.datalen = rte_cpu_to_le_16(buff_len);
10569                 buff = (void *)entries;
10570         } else
10571                 /* rule id is filled in destination field for deleting mirror rule */
10572                 cmd.destination = rte_cpu_to_le_16(rule_id);
10573
10574         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10575                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10576         cmd.seid = rte_cpu_to_le_16(seid);
10577
10578         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10579         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10580
10581         return status;
10582 }
10583
10584 /**
10585  * i40e_mirror_rule_set
10586  * @dev: pointer to the hardware structure
10587  * @mirror_conf: mirror rule info
10588  * @sw_id: mirror rule's sw_id
10589  * @on: enable/disable
10590  *
10591  * set a mirror rule.
10592  *
10593  **/
10594 static int
10595 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10596                         struct rte_eth_mirror_conf *mirror_conf,
10597                         uint8_t sw_id, uint8_t on)
10598 {
10599         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10600         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10601         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10602         struct i40e_mirror_rule *parent = NULL;
10603         uint16_t seid, dst_seid, rule_id;
10604         uint16_t i, j = 0;
10605         int ret;
10606
10607         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10608
10609         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10610                 PMD_DRV_LOG(ERR,
10611                         "mirror rule can not be configured without veb or vfs.");
10612                 return -ENOSYS;
10613         }
10614         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10615                 PMD_DRV_LOG(ERR, "mirror table is full.");
10616                 return -ENOSPC;
10617         }
10618         if (mirror_conf->dst_pool > pf->vf_num) {
10619                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10620                                  mirror_conf->dst_pool);
10621                 return -EINVAL;
10622         }
10623
10624         seid = pf->main_vsi->veb->seid;
10625
10626         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10627                 if (sw_id <= it->index) {
10628                         mirr_rule = it;
10629                         break;
10630                 }
10631                 parent = it;
10632         }
10633         if (mirr_rule && sw_id == mirr_rule->index) {
10634                 if (on) {
10635                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10636                         return -EEXIST;
10637                 } else {
10638                         ret = i40e_aq_del_mirror_rule(hw, seid,
10639                                         mirr_rule->rule_type,
10640                                         mirr_rule->entries,
10641                                         mirr_rule->num_entries, mirr_rule->id);
10642                         if (ret < 0) {
10643                                 PMD_DRV_LOG(ERR,
10644                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10645                                         ret, hw->aq.asq_last_status);
10646                                 return -ENOSYS;
10647                         }
10648                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10649                         rte_free(mirr_rule);
10650                         pf->nb_mirror_rule--;
10651                         return 0;
10652                 }
10653         } else if (!on) {
10654                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10655                 return -ENOENT;
10656         }
10657
10658         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10659                                 sizeof(struct i40e_mirror_rule) , 0);
10660         if (!mirr_rule) {
10661                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10662                 return I40E_ERR_NO_MEMORY;
10663         }
10664         switch (mirror_conf->rule_type) {
10665         case ETH_MIRROR_VLAN:
10666                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10667                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10668                                 mirr_rule->entries[j] =
10669                                         mirror_conf->vlan.vlan_id[i];
10670                                 j++;
10671                         }
10672                 }
10673                 if (j == 0) {
10674                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10675                         rte_free(mirr_rule);
10676                         return -EINVAL;
10677                 }
10678                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10679                 break;
10680         case ETH_MIRROR_VIRTUAL_POOL_UP:
10681         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10682                 /* check if the specified pool bit is out of range */
10683                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10684                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10685                         rte_free(mirr_rule);
10686                         return -EINVAL;
10687                 }
10688                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10689                         if (mirror_conf->pool_mask & (1ULL << i)) {
10690                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10691                                 j++;
10692                         }
10693                 }
10694                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10695                         /* add pf vsi to entries */
10696                         mirr_rule->entries[j] = pf->main_vsi_seid;
10697                         j++;
10698                 }
10699                 if (j == 0) {
10700                         PMD_DRV_LOG(ERR, "pool is not specified.");
10701                         rte_free(mirr_rule);
10702                         return -EINVAL;
10703                 }
10704                 /* egress and ingress in aq commands means from switch but not port */
10705                 mirr_rule->rule_type =
10706                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10707                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10708                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10709                 break;
10710         case ETH_MIRROR_UPLINK_PORT:
10711                 /* egress and ingress in aq commands means from switch but not port*/
10712                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10713                 break;
10714         case ETH_MIRROR_DOWNLINK_PORT:
10715                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10716                 break;
10717         default:
10718                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10719                         mirror_conf->rule_type);
10720                 rte_free(mirr_rule);
10721                 return -EINVAL;
10722         }
10723
10724         /* If the dst_pool is equal to vf_num, consider it as PF */
10725         if (mirror_conf->dst_pool == pf->vf_num)
10726                 dst_seid = pf->main_vsi_seid;
10727         else
10728                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10729
10730         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10731                                       mirr_rule->rule_type, mirr_rule->entries,
10732                                       j, &rule_id);
10733         if (ret < 0) {
10734                 PMD_DRV_LOG(ERR,
10735                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10736                         ret, hw->aq.asq_last_status);
10737                 rte_free(mirr_rule);
10738                 return -ENOSYS;
10739         }
10740
10741         mirr_rule->index = sw_id;
10742         mirr_rule->num_entries = j;
10743         mirr_rule->id = rule_id;
10744         mirr_rule->dst_vsi_seid = dst_seid;
10745
10746         if (parent)
10747                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10748         else
10749                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10750
10751         pf->nb_mirror_rule++;
10752         return 0;
10753 }
10754
10755 /**
10756  * i40e_mirror_rule_reset
10757  * @dev: pointer to the device
10758  * @sw_id: mirror rule's sw_id
10759  *
10760  * reset a mirror rule.
10761  *
10762  **/
10763 static int
10764 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10765 {
10766         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10767         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10768         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10769         uint16_t seid;
10770         int ret;
10771
10772         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10773
10774         seid = pf->main_vsi->veb->seid;
10775
10776         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10777                 if (sw_id == it->index) {
10778                         mirr_rule = it;
10779                         break;
10780                 }
10781         }
10782         if (mirr_rule) {
10783                 ret = i40e_aq_del_mirror_rule(hw, seid,
10784                                 mirr_rule->rule_type,
10785                                 mirr_rule->entries,
10786                                 mirr_rule->num_entries, mirr_rule->id);
10787                 if (ret < 0) {
10788                         PMD_DRV_LOG(ERR,
10789                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10790                                 ret, hw->aq.asq_last_status);
10791                         return -ENOSYS;
10792                 }
10793                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10794                 rte_free(mirr_rule);
10795                 pf->nb_mirror_rule--;
10796         } else {
10797                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10798                 return -ENOENT;
10799         }
10800         return 0;
10801 }
10802
10803 static uint64_t
10804 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10805 {
10806         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10807         uint64_t systim_cycles;
10808
10809         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10810         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10811                         << 32;
10812
10813         return systim_cycles;
10814 }
10815
10816 static uint64_t
10817 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10818 {
10819         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10820         uint64_t rx_tstamp;
10821
10822         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10823         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10824                         << 32;
10825
10826         return rx_tstamp;
10827 }
10828
10829 static uint64_t
10830 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10831 {
10832         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10833         uint64_t tx_tstamp;
10834
10835         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10836         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10837                         << 32;
10838
10839         return tx_tstamp;
10840 }
10841
10842 static void
10843 i40e_start_timecounters(struct rte_eth_dev *dev)
10844 {
10845         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10846         struct i40e_adapter *adapter =
10847                         (struct i40e_adapter *)dev->data->dev_private;
10848         struct rte_eth_link link;
10849         uint32_t tsync_inc_l;
10850         uint32_t tsync_inc_h;
10851
10852         /* Get current link speed. */
10853         i40e_dev_link_update(dev, 1);
10854         rte_eth_linkstatus_get(dev, &link);
10855
10856         switch (link.link_speed) {
10857         case ETH_SPEED_NUM_40G:
10858         case ETH_SPEED_NUM_25G:
10859                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10860                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10861                 break;
10862         case ETH_SPEED_NUM_10G:
10863                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10864                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10865                 break;
10866         case ETH_SPEED_NUM_1G:
10867                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10868                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10869                 break;
10870         default:
10871                 tsync_inc_l = 0x0;
10872                 tsync_inc_h = 0x0;
10873         }
10874
10875         /* Set the timesync increment value. */
10876         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10877         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10878
10879         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10880         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10881         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10882
10883         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10884         adapter->systime_tc.cc_shift = 0;
10885         adapter->systime_tc.nsec_mask = 0;
10886
10887         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10888         adapter->rx_tstamp_tc.cc_shift = 0;
10889         adapter->rx_tstamp_tc.nsec_mask = 0;
10890
10891         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10892         adapter->tx_tstamp_tc.cc_shift = 0;
10893         adapter->tx_tstamp_tc.nsec_mask = 0;
10894 }
10895
10896 static int
10897 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10898 {
10899         struct i40e_adapter *adapter =
10900                         (struct i40e_adapter *)dev->data->dev_private;
10901
10902         adapter->systime_tc.nsec += delta;
10903         adapter->rx_tstamp_tc.nsec += delta;
10904         adapter->tx_tstamp_tc.nsec += delta;
10905
10906         return 0;
10907 }
10908
10909 static int
10910 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10911 {
10912         uint64_t ns;
10913         struct i40e_adapter *adapter =
10914                         (struct i40e_adapter *)dev->data->dev_private;
10915
10916         ns = rte_timespec_to_ns(ts);
10917
10918         /* Set the timecounters to a new value. */
10919         adapter->systime_tc.nsec = ns;
10920         adapter->rx_tstamp_tc.nsec = ns;
10921         adapter->tx_tstamp_tc.nsec = ns;
10922
10923         return 0;
10924 }
10925
10926 static int
10927 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10928 {
10929         uint64_t ns, systime_cycles;
10930         struct i40e_adapter *adapter =
10931                         (struct i40e_adapter *)dev->data->dev_private;
10932
10933         systime_cycles = i40e_read_systime_cyclecounter(dev);
10934         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10935         *ts = rte_ns_to_timespec(ns);
10936
10937         return 0;
10938 }
10939
10940 static int
10941 i40e_timesync_enable(struct rte_eth_dev *dev)
10942 {
10943         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10944         uint32_t tsync_ctl_l;
10945         uint32_t tsync_ctl_h;
10946
10947         /* Stop the timesync system time. */
10948         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10949         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10950         /* Reset the timesync system time value. */
10951         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10952         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10953
10954         i40e_start_timecounters(dev);
10955
10956         /* Clear timesync registers. */
10957         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10958         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10959         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10960         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10961         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10962         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10963
10964         /* Enable timestamping of PTP packets. */
10965         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10966         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10967
10968         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10969         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10970         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10971
10972         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10973         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10974
10975         return 0;
10976 }
10977
10978 static int
10979 i40e_timesync_disable(struct rte_eth_dev *dev)
10980 {
10981         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10982         uint32_t tsync_ctl_l;
10983         uint32_t tsync_ctl_h;
10984
10985         /* Disable timestamping of transmitted PTP packets. */
10986         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10987         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10988
10989         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10990         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10991
10992         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10993         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10994
10995         /* Reset the timesync increment value. */
10996         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10997         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10998
10999         return 0;
11000 }
11001
11002 static int
11003 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11004                                 struct timespec *timestamp, uint32_t flags)
11005 {
11006         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11007         struct i40e_adapter *adapter =
11008                 (struct i40e_adapter *)dev->data->dev_private;
11009
11010         uint32_t sync_status;
11011         uint32_t index = flags & 0x03;
11012         uint64_t rx_tstamp_cycles;
11013         uint64_t ns;
11014
11015         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11016         if ((sync_status & (1 << index)) == 0)
11017                 return -EINVAL;
11018
11019         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11020         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11021         *timestamp = rte_ns_to_timespec(ns);
11022
11023         return 0;
11024 }
11025
11026 static int
11027 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11028                                 struct timespec *timestamp)
11029 {
11030         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11031         struct i40e_adapter *adapter =
11032                 (struct i40e_adapter *)dev->data->dev_private;
11033
11034         uint32_t sync_status;
11035         uint64_t tx_tstamp_cycles;
11036         uint64_t ns;
11037
11038         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11039         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11040                 return -EINVAL;
11041
11042         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11043         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11044         *timestamp = rte_ns_to_timespec(ns);
11045
11046         return 0;
11047 }
11048
11049 /*
11050  * i40e_parse_dcb_configure - parse dcb configure from user
11051  * @dev: the device being configured
11052  * @dcb_cfg: pointer of the result of parse
11053  * @*tc_map: bit map of enabled traffic classes
11054  *
11055  * Returns 0 on success, negative value on failure
11056  */
11057 static int
11058 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11059                          struct i40e_dcbx_config *dcb_cfg,
11060                          uint8_t *tc_map)
11061 {
11062         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11063         uint8_t i, tc_bw, bw_lf;
11064
11065         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11066
11067         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11068         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11069                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11070                 return -EINVAL;
11071         }
11072
11073         /* assume each tc has the same bw */
11074         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11075         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11076                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11077         /* to ensure the sum of tcbw is equal to 100 */
11078         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11079         for (i = 0; i < bw_lf; i++)
11080                 dcb_cfg->etscfg.tcbwtable[i]++;
11081
11082         /* assume each tc has the same Transmission Selection Algorithm */
11083         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11084                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11085
11086         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11087                 dcb_cfg->etscfg.prioritytable[i] =
11088                                 dcb_rx_conf->dcb_tc[i];
11089
11090         /* FW needs one App to configure HW */
11091         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11092         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11093         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11094         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11095
11096         if (dcb_rx_conf->nb_tcs == 0)
11097                 *tc_map = 1; /* tc0 only */
11098         else
11099                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11100
11101         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11102                 dcb_cfg->pfc.willing = 0;
11103                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11104                 dcb_cfg->pfc.pfcenable = *tc_map;
11105         }
11106         return 0;
11107 }
11108
11109
11110 static enum i40e_status_code
11111 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11112                               struct i40e_aqc_vsi_properties_data *info,
11113                               uint8_t enabled_tcmap)
11114 {
11115         enum i40e_status_code ret;
11116         int i, total_tc = 0;
11117         uint16_t qpnum_per_tc, bsf, qp_idx;
11118         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11119         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11120         uint16_t used_queues;
11121
11122         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11123         if (ret != I40E_SUCCESS)
11124                 return ret;
11125
11126         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11127                 if (enabled_tcmap & (1 << i))
11128                         total_tc++;
11129         }
11130         if (total_tc == 0)
11131                 total_tc = 1;
11132         vsi->enabled_tc = enabled_tcmap;
11133
11134         /* different VSI has different queues assigned */
11135         if (vsi->type == I40E_VSI_MAIN)
11136                 used_queues = dev_data->nb_rx_queues -
11137                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11138         else if (vsi->type == I40E_VSI_VMDQ2)
11139                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11140         else {
11141                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11142                 return I40E_ERR_NO_AVAILABLE_VSI;
11143         }
11144
11145         qpnum_per_tc = used_queues / total_tc;
11146         /* Number of queues per enabled TC */
11147         if (qpnum_per_tc == 0) {
11148                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11149                 return I40E_ERR_INVALID_QP_ID;
11150         }
11151         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11152                                 I40E_MAX_Q_PER_TC);
11153         bsf = rte_bsf32(qpnum_per_tc);
11154
11155         /**
11156          * Configure TC and queue mapping parameters, for enabled TC,
11157          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11158          * default queue will serve it.
11159          */
11160         qp_idx = 0;
11161         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11162                 if (vsi->enabled_tc & (1 << i)) {
11163                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11164                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11165                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11166                         qp_idx += qpnum_per_tc;
11167                 } else
11168                         info->tc_mapping[i] = 0;
11169         }
11170
11171         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11172         if (vsi->type == I40E_VSI_SRIOV) {
11173                 info->mapping_flags |=
11174                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11175                 for (i = 0; i < vsi->nb_qps; i++)
11176                         info->queue_mapping[i] =
11177                                 rte_cpu_to_le_16(vsi->base_queue + i);
11178         } else {
11179                 info->mapping_flags |=
11180                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11181                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11182         }
11183         info->valid_sections |=
11184                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11185
11186         return I40E_SUCCESS;
11187 }
11188
11189 /*
11190  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11191  * @veb: VEB to be configured
11192  * @tc_map: enabled TC bitmap
11193  *
11194  * Returns 0 on success, negative value on failure
11195  */
11196 static enum i40e_status_code
11197 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11198 {
11199         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11200         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11201         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11202         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11203         enum i40e_status_code ret = I40E_SUCCESS;
11204         int i;
11205         uint32_t bw_max;
11206
11207         /* Check if enabled_tc is same as existing or new TCs */
11208         if (veb->enabled_tc == tc_map)
11209                 return ret;
11210
11211         /* configure tc bandwidth */
11212         memset(&veb_bw, 0, sizeof(veb_bw));
11213         veb_bw.tc_valid_bits = tc_map;
11214         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11215         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11216                 if (tc_map & BIT_ULL(i))
11217                         veb_bw.tc_bw_share_credits[i] = 1;
11218         }
11219         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11220                                                    &veb_bw, NULL);
11221         if (ret) {
11222                 PMD_INIT_LOG(ERR,
11223                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11224                         hw->aq.asq_last_status);
11225                 return ret;
11226         }
11227
11228         memset(&ets_query, 0, sizeof(ets_query));
11229         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11230                                                    &ets_query, NULL);
11231         if (ret != I40E_SUCCESS) {
11232                 PMD_DRV_LOG(ERR,
11233                         "Failed to get switch_comp ETS configuration %u",
11234                         hw->aq.asq_last_status);
11235                 return ret;
11236         }
11237         memset(&bw_query, 0, sizeof(bw_query));
11238         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11239                                                   &bw_query, NULL);
11240         if (ret != I40E_SUCCESS) {
11241                 PMD_DRV_LOG(ERR,
11242                         "Failed to get switch_comp bandwidth configuration %u",
11243                         hw->aq.asq_last_status);
11244                 return ret;
11245         }
11246
11247         /* store and print out BW info */
11248         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11249         veb->bw_info.bw_max = ets_query.tc_bw_max;
11250         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11251         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11252         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11253                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11254                      I40E_16_BIT_WIDTH);
11255         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11256                 veb->bw_info.bw_ets_share_credits[i] =
11257                                 bw_query.tc_bw_share_credits[i];
11258                 veb->bw_info.bw_ets_credits[i] =
11259                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11260                 /* 4 bits per TC, 4th bit is reserved */
11261                 veb->bw_info.bw_ets_max[i] =
11262                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11263                                   RTE_LEN2MASK(3, uint8_t));
11264                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11265                             veb->bw_info.bw_ets_share_credits[i]);
11266                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11267                             veb->bw_info.bw_ets_credits[i]);
11268                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11269                             veb->bw_info.bw_ets_max[i]);
11270         }
11271
11272         veb->enabled_tc = tc_map;
11273
11274         return ret;
11275 }
11276
11277
11278 /*
11279  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11280  * @vsi: VSI to be configured
11281  * @tc_map: enabled TC bitmap
11282  *
11283  * Returns 0 on success, negative value on failure
11284  */
11285 static enum i40e_status_code
11286 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11287 {
11288         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11289         struct i40e_vsi_context ctxt;
11290         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11291         enum i40e_status_code ret = I40E_SUCCESS;
11292         int i;
11293
11294         /* Check if enabled_tc is same as existing or new TCs */
11295         if (vsi->enabled_tc == tc_map)
11296                 return ret;
11297
11298         /* configure tc bandwidth */
11299         memset(&bw_data, 0, sizeof(bw_data));
11300         bw_data.tc_valid_bits = tc_map;
11301         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11302         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11303                 if (tc_map & BIT_ULL(i))
11304                         bw_data.tc_bw_credits[i] = 1;
11305         }
11306         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11307         if (ret) {
11308                 PMD_INIT_LOG(ERR,
11309                         "AQ command Config VSI BW allocation per TC failed = %d",
11310                         hw->aq.asq_last_status);
11311                 goto out;
11312         }
11313         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11314                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11315
11316         /* Update Queue Pairs Mapping for currently enabled UPs */
11317         ctxt.seid = vsi->seid;
11318         ctxt.pf_num = hw->pf_id;
11319         ctxt.vf_num = 0;
11320         ctxt.uplink_seid = vsi->uplink_seid;
11321         ctxt.info = vsi->info;
11322         i40e_get_cap(hw);
11323         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11324         if (ret)
11325                 goto out;
11326
11327         /* Update the VSI after updating the VSI queue-mapping information */
11328         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11329         if (ret) {
11330                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11331                         hw->aq.asq_last_status);
11332                 goto out;
11333         }
11334         /* update the local VSI info with updated queue map */
11335         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11336                                         sizeof(vsi->info.tc_mapping));
11337         rte_memcpy(&vsi->info.queue_mapping,
11338                         &ctxt.info.queue_mapping,
11339                 sizeof(vsi->info.queue_mapping));
11340         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11341         vsi->info.valid_sections = 0;
11342
11343         /* query and update current VSI BW information */
11344         ret = i40e_vsi_get_bw_config(vsi);
11345         if (ret) {
11346                 PMD_INIT_LOG(ERR,
11347                          "Failed updating vsi bw info, err %s aq_err %s",
11348                          i40e_stat_str(hw, ret),
11349                          i40e_aq_str(hw, hw->aq.asq_last_status));
11350                 goto out;
11351         }
11352
11353         vsi->enabled_tc = tc_map;
11354
11355 out:
11356         return ret;
11357 }
11358
11359 /*
11360  * i40e_dcb_hw_configure - program the dcb setting to hw
11361  * @pf: pf the configuration is taken on
11362  * @new_cfg: new configuration
11363  * @tc_map: enabled TC bitmap
11364  *
11365  * Returns 0 on success, negative value on failure
11366  */
11367 static enum i40e_status_code
11368 i40e_dcb_hw_configure(struct i40e_pf *pf,
11369                       struct i40e_dcbx_config *new_cfg,
11370                       uint8_t tc_map)
11371 {
11372         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11373         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11374         struct i40e_vsi *main_vsi = pf->main_vsi;
11375         struct i40e_vsi_list *vsi_list;
11376         enum i40e_status_code ret;
11377         int i;
11378         uint32_t val;
11379
11380         /* Use the FW API if FW > v4.4*/
11381         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11382               (hw->aq.fw_maj_ver >= 5))) {
11383                 PMD_INIT_LOG(ERR,
11384                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11385                 return I40E_ERR_FIRMWARE_API_VERSION;
11386         }
11387
11388         /* Check if need reconfiguration */
11389         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11390                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11391                 return I40E_SUCCESS;
11392         }
11393
11394         /* Copy the new config to the current config */
11395         *old_cfg = *new_cfg;
11396         old_cfg->etsrec = old_cfg->etscfg;
11397         ret = i40e_set_dcb_config(hw);
11398         if (ret) {
11399                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11400                          i40e_stat_str(hw, ret),
11401                          i40e_aq_str(hw, hw->aq.asq_last_status));
11402                 return ret;
11403         }
11404         /* set receive Arbiter to RR mode and ETS scheme by default */
11405         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11406                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11407                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11408                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11409                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11410                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11411                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11412                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11413                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11414                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11415                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11416                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11417                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11418         }
11419         /* get local mib to check whether it is configured correctly */
11420         /* IEEE mode */
11421         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11422         /* Get Local DCB Config */
11423         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11424                                      &hw->local_dcbx_config);
11425
11426         /* if Veb is created, need to update TC of it at first */
11427         if (main_vsi->veb) {
11428                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11429                 if (ret)
11430                         PMD_INIT_LOG(WARNING,
11431                                  "Failed configuring TC for VEB seid=%d",
11432                                  main_vsi->veb->seid);
11433         }
11434         /* Update each VSI */
11435         i40e_vsi_config_tc(main_vsi, tc_map);
11436         if (main_vsi->veb) {
11437                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11438                         /* Beside main VSI and VMDQ VSIs, only enable default
11439                          * TC for other VSIs
11440                          */
11441                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11442                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11443                                                          tc_map);
11444                         else
11445                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11446                                                          I40E_DEFAULT_TCMAP);
11447                         if (ret)
11448                                 PMD_INIT_LOG(WARNING,
11449                                         "Failed configuring TC for VSI seid=%d",
11450                                         vsi_list->vsi->seid);
11451                         /* continue */
11452                 }
11453         }
11454         return I40E_SUCCESS;
11455 }
11456
11457 /*
11458  * i40e_dcb_init_configure - initial dcb config
11459  * @dev: device being configured
11460  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11461  *
11462  * Returns 0 on success, negative value on failure
11463  */
11464 int
11465 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11466 {
11467         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11468         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11469         int i, ret = 0;
11470
11471         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11472                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11473                 return -ENOTSUP;
11474         }
11475
11476         /* DCB initialization:
11477          * Update DCB configuration from the Firmware and configure
11478          * LLDP MIB change event.
11479          */
11480         if (sw_dcb == TRUE) {
11481                 if (i40e_need_stop_lldp(dev)) {
11482                         ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11483                         if (ret != I40E_SUCCESS)
11484                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11485                 }
11486
11487                 ret = i40e_init_dcb(hw);
11488                 /* If lldp agent is stopped, the return value from
11489                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11490                  * adminq status. Otherwise, it should return success.
11491                  */
11492                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11493                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11494                         memset(&hw->local_dcbx_config, 0,
11495                                 sizeof(struct i40e_dcbx_config));
11496                         /* set dcb default configuration */
11497                         hw->local_dcbx_config.etscfg.willing = 0;
11498                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11499                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11500                         hw->local_dcbx_config.etscfg.tsatable[0] =
11501                                                 I40E_IEEE_TSA_ETS;
11502                         /* all UPs mapping to TC0 */
11503                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11504                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11505                         hw->local_dcbx_config.etsrec =
11506                                 hw->local_dcbx_config.etscfg;
11507                         hw->local_dcbx_config.pfc.willing = 0;
11508                         hw->local_dcbx_config.pfc.pfccap =
11509                                                 I40E_MAX_TRAFFIC_CLASS;
11510                         /* FW needs one App to configure HW */
11511                         hw->local_dcbx_config.numapps = 1;
11512                         hw->local_dcbx_config.app[0].selector =
11513                                                 I40E_APP_SEL_ETHTYPE;
11514                         hw->local_dcbx_config.app[0].priority = 3;
11515                         hw->local_dcbx_config.app[0].protocolid =
11516                                                 I40E_APP_PROTOID_FCOE;
11517                         ret = i40e_set_dcb_config(hw);
11518                         if (ret) {
11519                                 PMD_INIT_LOG(ERR,
11520                                         "default dcb config fails. err = %d, aq_err = %d.",
11521                                         ret, hw->aq.asq_last_status);
11522                                 return -ENOSYS;
11523                         }
11524                 } else {
11525                         PMD_INIT_LOG(ERR,
11526                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11527                                 ret, hw->aq.asq_last_status);
11528                         return -ENOTSUP;
11529                 }
11530         } else {
11531                 ret = i40e_aq_start_lldp(hw, NULL);
11532                 if (ret != I40E_SUCCESS)
11533                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11534
11535                 ret = i40e_init_dcb(hw);
11536                 if (!ret) {
11537                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11538                                 PMD_INIT_LOG(ERR,
11539                                         "HW doesn't support DCBX offload.");
11540                                 return -ENOTSUP;
11541                         }
11542                 } else {
11543                         PMD_INIT_LOG(ERR,
11544                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11545                                 ret, hw->aq.asq_last_status);
11546                         return -ENOTSUP;
11547                 }
11548         }
11549         return 0;
11550 }
11551
11552 /*
11553  * i40e_dcb_setup - setup dcb related config
11554  * @dev: device being configured
11555  *
11556  * Returns 0 on success, negative value on failure
11557  */
11558 static int
11559 i40e_dcb_setup(struct rte_eth_dev *dev)
11560 {
11561         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11562         struct i40e_dcbx_config dcb_cfg;
11563         uint8_t tc_map = 0;
11564         int ret = 0;
11565
11566         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11567                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11568                 return -ENOTSUP;
11569         }
11570
11571         if (pf->vf_num != 0)
11572                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11573
11574         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11575         if (ret) {
11576                 PMD_INIT_LOG(ERR, "invalid dcb config");
11577                 return -EINVAL;
11578         }
11579         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11580         if (ret) {
11581                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11582                 return -ENOSYS;
11583         }
11584
11585         return 0;
11586 }
11587
11588 static int
11589 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11590                       struct rte_eth_dcb_info *dcb_info)
11591 {
11592         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11593         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11594         struct i40e_vsi *vsi = pf->main_vsi;
11595         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11596         uint16_t bsf, tc_mapping;
11597         int i, j = 0;
11598
11599         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11600                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11601         else
11602                 dcb_info->nb_tcs = 1;
11603         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11604                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11605         for (i = 0; i < dcb_info->nb_tcs; i++)
11606                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11607
11608         /* get queue mapping if vmdq is disabled */
11609         if (!pf->nb_cfg_vmdq_vsi) {
11610                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11611                         if (!(vsi->enabled_tc & (1 << i)))
11612                                 continue;
11613                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11614                         dcb_info->tc_queue.tc_rxq[j][i].base =
11615                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11616                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11617                         dcb_info->tc_queue.tc_txq[j][i].base =
11618                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11619                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11620                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11621                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11622                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11623                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11624                 }
11625                 return 0;
11626         }
11627
11628         /* get queue mapping if vmdq is enabled */
11629         do {
11630                 vsi = pf->vmdq[j].vsi;
11631                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11632                         if (!(vsi->enabled_tc & (1 << i)))
11633                                 continue;
11634                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11635                         dcb_info->tc_queue.tc_rxq[j][i].base =
11636                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11637                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11638                         dcb_info->tc_queue.tc_txq[j][i].base =
11639                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11640                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11641                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11642                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11643                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11644                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11645                 }
11646                 j++;
11647         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11648         return 0;
11649 }
11650
11651 static int
11652 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11653 {
11654         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11655         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11656         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11657         uint16_t msix_intr;
11658
11659         msix_intr = intr_handle->intr_vec[queue_id];
11660         if (msix_intr == I40E_MISC_VEC_ID)
11661                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11662                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11663                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11664                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11665         else
11666                 I40E_WRITE_REG(hw,
11667                                I40E_PFINT_DYN_CTLN(msix_intr -
11668                                                    I40E_RX_VEC_START),
11669                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11670                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11671                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11672
11673         I40E_WRITE_FLUSH(hw);
11674         rte_intr_enable(&pci_dev->intr_handle);
11675
11676         return 0;
11677 }
11678
11679 static int
11680 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11681 {
11682         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11683         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11684         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11685         uint16_t msix_intr;
11686
11687         msix_intr = intr_handle->intr_vec[queue_id];
11688         if (msix_intr == I40E_MISC_VEC_ID)
11689                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11690                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11691         else
11692                 I40E_WRITE_REG(hw,
11693                                I40E_PFINT_DYN_CTLN(msix_intr -
11694                                                    I40E_RX_VEC_START),
11695                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11696         I40E_WRITE_FLUSH(hw);
11697
11698         return 0;
11699 }
11700
11701 /**
11702  * This function is used to check if the register is valid.
11703  * Below is the valid registers list for X722 only:
11704  * 0x2b800--0x2bb00
11705  * 0x38700--0x38a00
11706  * 0x3d800--0x3db00
11707  * 0x208e00--0x209000
11708  * 0x20be00--0x20c000
11709  * 0x263c00--0x264000
11710  * 0x265c00--0x266000
11711  */
11712 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11713 {
11714         if ((type != I40E_MAC_X722) &&
11715             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11716              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11717              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11718              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11719              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11720              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11721              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11722                 return 0;
11723         else
11724                 return 1;
11725 }
11726
11727 static int i40e_get_regs(struct rte_eth_dev *dev,
11728                          struct rte_dev_reg_info *regs)
11729 {
11730         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11731         uint32_t *ptr_data = regs->data;
11732         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11733         const struct i40e_reg_info *reg_info;
11734
11735         if (ptr_data == NULL) {
11736                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11737                 regs->width = sizeof(uint32_t);
11738                 return 0;
11739         }
11740
11741         /* The first few registers have to be read using AQ operations */
11742         reg_idx = 0;
11743         while (i40e_regs_adminq[reg_idx].name) {
11744                 reg_info = &i40e_regs_adminq[reg_idx++];
11745                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11746                         for (arr_idx2 = 0;
11747                                         arr_idx2 <= reg_info->count2;
11748                                         arr_idx2++) {
11749                                 reg_offset = arr_idx * reg_info->stride1 +
11750                                         arr_idx2 * reg_info->stride2;
11751                                 reg_offset += reg_info->base_addr;
11752                                 ptr_data[reg_offset >> 2] =
11753                                         i40e_read_rx_ctl(hw, reg_offset);
11754                         }
11755         }
11756
11757         /* The remaining registers can be read using primitives */
11758         reg_idx = 0;
11759         while (i40e_regs_others[reg_idx].name) {
11760                 reg_info = &i40e_regs_others[reg_idx++];
11761                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11762                         for (arr_idx2 = 0;
11763                                         arr_idx2 <= reg_info->count2;
11764                                         arr_idx2++) {
11765                                 reg_offset = arr_idx * reg_info->stride1 +
11766                                         arr_idx2 * reg_info->stride2;
11767                                 reg_offset += reg_info->base_addr;
11768                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11769                                         ptr_data[reg_offset >> 2] = 0;
11770                                 else
11771                                         ptr_data[reg_offset >> 2] =
11772                                                 I40E_READ_REG(hw, reg_offset);
11773                         }
11774         }
11775
11776         return 0;
11777 }
11778
11779 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11780 {
11781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11782
11783         /* Convert word count to byte count */
11784         return hw->nvm.sr_size << 1;
11785 }
11786
11787 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11788                            struct rte_dev_eeprom_info *eeprom)
11789 {
11790         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11791         uint16_t *data = eeprom->data;
11792         uint16_t offset, length, cnt_words;
11793         int ret_code;
11794
11795         offset = eeprom->offset >> 1;
11796         length = eeprom->length >> 1;
11797         cnt_words = length;
11798
11799         if (offset > hw->nvm.sr_size ||
11800                 offset + length > hw->nvm.sr_size) {
11801                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11802                 return -EINVAL;
11803         }
11804
11805         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11806
11807         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11808         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11809                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11810                 return -EIO;
11811         }
11812
11813         return 0;
11814 }
11815
11816 static int i40e_get_module_info(struct rte_eth_dev *dev,
11817                                 struct rte_eth_dev_module_info *modinfo)
11818 {
11819         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11820         uint32_t sff8472_comp = 0;
11821         uint32_t sff8472_swap = 0;
11822         uint32_t sff8636_rev = 0;
11823         i40e_status status;
11824         uint32_t type = 0;
11825
11826         /* Check if firmware supports reading module EEPROM. */
11827         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11828                 PMD_DRV_LOG(ERR,
11829                             "Module EEPROM memory read not supported. "
11830                             "Please update the NVM image.\n");
11831                 return -EINVAL;
11832         }
11833
11834         status = i40e_update_link_info(hw);
11835         if (status)
11836                 return -EIO;
11837
11838         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11839                 PMD_DRV_LOG(ERR,
11840                             "Cannot read module EEPROM memory. "
11841                             "No module connected.\n");
11842                 return -EINVAL;
11843         }
11844
11845         type = hw->phy.link_info.module_type[0];
11846
11847         switch (type) {
11848         case I40E_MODULE_TYPE_SFP:
11849                 status = i40e_aq_get_phy_register(hw,
11850                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11851                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11852                                 I40E_MODULE_SFF_8472_COMP,
11853                                 &sff8472_comp, NULL);
11854                 if (status)
11855                         return -EIO;
11856
11857                 status = i40e_aq_get_phy_register(hw,
11858                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11859                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11860                                 I40E_MODULE_SFF_8472_SWAP,
11861                                 &sff8472_swap, NULL);
11862                 if (status)
11863                         return -EIO;
11864
11865                 /* Check if the module requires address swap to access
11866                  * the other EEPROM memory page.
11867                  */
11868                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11869                         PMD_DRV_LOG(WARNING,
11870                                     "Module address swap to access "
11871                                     "page 0xA2 is not supported.\n");
11872                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11873                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11874                 } else if (sff8472_comp == 0x00) {
11875                         /* Module is not SFF-8472 compliant */
11876                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11877                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11878                 } else {
11879                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11880                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11881                 }
11882                 break;
11883         case I40E_MODULE_TYPE_QSFP_PLUS:
11884                 /* Read from memory page 0. */
11885                 status = i40e_aq_get_phy_register(hw,
11886                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11887                                 0, 1,
11888                                 I40E_MODULE_REVISION_ADDR,
11889                                 &sff8636_rev, NULL);
11890                 if (status)
11891                         return -EIO;
11892                 /* Determine revision compliance byte */
11893                 if (sff8636_rev > 0x02) {
11894                         /* Module is SFF-8636 compliant */
11895                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11896                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11897                 } else {
11898                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11899                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11900                 }
11901                 break;
11902         case I40E_MODULE_TYPE_QSFP28:
11903                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11904                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11905                 break;
11906         default:
11907                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11908                 return -EINVAL;
11909         }
11910         return 0;
11911 }
11912
11913 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11914                                   struct rte_dev_eeprom_info *info)
11915 {
11916         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11917         bool is_sfp = false;
11918         i40e_status status;
11919         uint8_t *data;
11920         uint32_t value = 0;
11921         uint32_t i;
11922
11923         if (!info || !info->length || !info->data)
11924                 return -EINVAL;
11925
11926         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11927                 is_sfp = true;
11928
11929         data = info->data;
11930         for (i = 0; i < info->length; i++) {
11931                 u32 offset = i + info->offset;
11932                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11933
11934                 /* Check if we need to access the other memory page */
11935                 if (is_sfp) {
11936                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11937                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11938                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11939                         }
11940                 } else {
11941                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11942                                 /* Compute memory page number and offset. */
11943                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11944                                 addr++;
11945                         }
11946                 }
11947                 status = i40e_aq_get_phy_register(hw,
11948                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11949                                 addr, offset, 1, &value, NULL);
11950                 if (status)
11951                         return -EIO;
11952                 data[i] = (uint8_t)value;
11953         }
11954         return 0;
11955 }
11956
11957 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11958                                      struct rte_ether_addr *mac_addr)
11959 {
11960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11961         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11962         struct i40e_vsi *vsi = pf->main_vsi;
11963         struct i40e_mac_filter_info mac_filter;
11964         struct i40e_mac_filter *f;
11965         int ret;
11966
11967         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11968                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11969                 return -EINVAL;
11970         }
11971
11972         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11973                 if (rte_is_same_ether_addr(&pf->dev_addr,
11974                                                 &f->mac_info.mac_addr))
11975                         break;
11976         }
11977
11978         if (f == NULL) {
11979                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11980                 return -EIO;
11981         }
11982
11983         mac_filter = f->mac_info;
11984         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11985         if (ret != I40E_SUCCESS) {
11986                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11987                 return -EIO;
11988         }
11989         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11990         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11991         if (ret != I40E_SUCCESS) {
11992                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11993                 return -EIO;
11994         }
11995         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11996
11997         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11998                                         mac_addr->addr_bytes, NULL);
11999         if (ret != I40E_SUCCESS) {
12000                 PMD_DRV_LOG(ERR, "Failed to change mac");
12001                 return -EIO;
12002         }
12003
12004         return 0;
12005 }
12006
12007 static int
12008 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12009 {
12010         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12011         struct rte_eth_dev_data *dev_data = pf->dev_data;
12012         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12013         int ret = 0;
12014
12015         /* check if mtu is within the allowed range */
12016         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12017                 return -EINVAL;
12018
12019         /* mtu setting is forbidden if port is start */
12020         if (dev_data->dev_started) {
12021                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12022                             dev_data->port_id);
12023                 return -EBUSY;
12024         }
12025
12026         if (frame_size > RTE_ETHER_MAX_LEN)
12027                 dev_data->dev_conf.rxmode.offloads |=
12028                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12029         else
12030                 dev_data->dev_conf.rxmode.offloads &=
12031                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12032
12033         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12034
12035         return ret;
12036 }
12037
12038 /* Restore ethertype filter */
12039 static void
12040 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12041 {
12042         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12043         struct i40e_ethertype_filter_list
12044                 *ethertype_list = &pf->ethertype.ethertype_list;
12045         struct i40e_ethertype_filter *f;
12046         struct i40e_control_filter_stats stats;
12047         uint16_t flags;
12048
12049         TAILQ_FOREACH(f, ethertype_list, rules) {
12050                 flags = 0;
12051                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12052                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12053                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12054                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12055                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12056
12057                 memset(&stats, 0, sizeof(stats));
12058                 i40e_aq_add_rem_control_packet_filter(hw,
12059                                             f->input.mac_addr.addr_bytes,
12060                                             f->input.ether_type,
12061                                             flags, pf->main_vsi->seid,
12062                                             f->queue, 1, &stats, NULL);
12063         }
12064         PMD_DRV_LOG(INFO, "Ethertype filter:"
12065                     " mac_etype_used = %u, etype_used = %u,"
12066                     " mac_etype_free = %u, etype_free = %u",
12067                     stats.mac_etype_used, stats.etype_used,
12068                     stats.mac_etype_free, stats.etype_free);
12069 }
12070
12071 /* Restore tunnel filter */
12072 static void
12073 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12074 {
12075         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12076         struct i40e_vsi *vsi;
12077         struct i40e_pf_vf *vf;
12078         struct i40e_tunnel_filter_list
12079                 *tunnel_list = &pf->tunnel.tunnel_list;
12080         struct i40e_tunnel_filter *f;
12081         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12082         bool big_buffer = 0;
12083
12084         TAILQ_FOREACH(f, tunnel_list, rules) {
12085                 if (!f->is_to_vf)
12086                         vsi = pf->main_vsi;
12087                 else {
12088                         vf = &pf->vfs[f->vf_id];
12089                         vsi = vf->vsi;
12090                 }
12091                 memset(&cld_filter, 0, sizeof(cld_filter));
12092                 rte_ether_addr_copy((struct rte_ether_addr *)
12093                                 &f->input.outer_mac,
12094                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12095                 rte_ether_addr_copy((struct rte_ether_addr *)
12096                                 &f->input.inner_mac,
12097                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12098                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12099                 cld_filter.element.flags = f->input.flags;
12100                 cld_filter.element.tenant_id = f->input.tenant_id;
12101                 cld_filter.element.queue_number = f->queue;
12102                 rte_memcpy(cld_filter.general_fields,
12103                            f->input.general_fields,
12104                            sizeof(f->input.general_fields));
12105
12106                 if (((f->input.flags &
12107                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12108                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12109                     ((f->input.flags &
12110                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12111                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12112                     ((f->input.flags &
12113                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12114                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12115                         big_buffer = 1;
12116
12117                 if (big_buffer)
12118                         i40e_aq_add_cloud_filters_bb(hw,
12119                                         vsi->seid, &cld_filter, 1);
12120                 else
12121                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12122                                                   &cld_filter.element, 1);
12123         }
12124 }
12125
12126 /* Restore rss filter */
12127 static inline void
12128 i40e_rss_filter_restore(struct i40e_pf *pf)
12129 {
12130         struct i40e_rte_flow_rss_conf *conf =
12131                                         &pf->rss_info;
12132         if (conf->conf.queue_num)
12133                 i40e_config_rss_filter(pf, conf, TRUE);
12134 }
12135
12136 static void
12137 i40e_filter_restore(struct i40e_pf *pf)
12138 {
12139         i40e_ethertype_filter_restore(pf);
12140         i40e_tunnel_filter_restore(pf);
12141         i40e_fdir_filter_restore(pf);
12142         i40e_rss_filter_restore(pf);
12143 }
12144
12145 static bool
12146 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12147 {
12148         if (strcmp(dev->device->driver->name, drv->driver.name))
12149                 return false;
12150
12151         return true;
12152 }
12153
12154 bool
12155 is_i40e_supported(struct rte_eth_dev *dev)
12156 {
12157         return is_device_supported(dev, &rte_i40e_pmd);
12158 }
12159
12160 struct i40e_customized_pctype*
12161 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12162 {
12163         int i;
12164
12165         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12166                 if (pf->customized_pctype[i].index == index)
12167                         return &pf->customized_pctype[i];
12168         }
12169         return NULL;
12170 }
12171
12172 static int
12173 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12174                               uint32_t pkg_size, uint32_t proto_num,
12175                               struct rte_pmd_i40e_proto_info *proto,
12176                               enum rte_pmd_i40e_package_op op)
12177 {
12178         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12179         uint32_t pctype_num;
12180         struct rte_pmd_i40e_ptype_info *pctype;
12181         uint32_t buff_size;
12182         struct i40e_customized_pctype *new_pctype = NULL;
12183         uint8_t proto_id;
12184         uint8_t pctype_value;
12185         char name[64];
12186         uint32_t i, j, n;
12187         int ret;
12188
12189         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12190             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12191                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12192                 return -1;
12193         }
12194
12195         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12196                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12197                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12198         if (ret) {
12199                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12200                 return -1;
12201         }
12202         if (!pctype_num) {
12203                 PMD_DRV_LOG(INFO, "No new pctype added");
12204                 return -1;
12205         }
12206
12207         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12208         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12209         if (!pctype) {
12210                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12211                 return -1;
12212         }
12213         /* get information about new pctype list */
12214         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12215                                         (uint8_t *)pctype, buff_size,
12216                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12217         if (ret) {
12218                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12219                 rte_free(pctype);
12220                 return -1;
12221         }
12222
12223         /* Update customized pctype. */
12224         for (i = 0; i < pctype_num; i++) {
12225                 pctype_value = pctype[i].ptype_id;
12226                 memset(name, 0, sizeof(name));
12227                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12228                         proto_id = pctype[i].protocols[j];
12229                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12230                                 continue;
12231                         for (n = 0; n < proto_num; n++) {
12232                                 if (proto[n].proto_id != proto_id)
12233                                         continue;
12234                                 strlcat(name, proto[n].name, sizeof(name));
12235                                 strlcat(name, "_", sizeof(name));
12236                                 break;
12237                         }
12238                 }
12239                 name[strlen(name) - 1] = '\0';
12240                 if (!strcmp(name, "GTPC"))
12241                         new_pctype =
12242                                 i40e_find_customized_pctype(pf,
12243                                                       I40E_CUSTOMIZED_GTPC);
12244                 else if (!strcmp(name, "GTPU_IPV4"))
12245                         new_pctype =
12246                                 i40e_find_customized_pctype(pf,
12247                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12248                 else if (!strcmp(name, "GTPU_IPV6"))
12249                         new_pctype =
12250                                 i40e_find_customized_pctype(pf,
12251                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12252                 else if (!strcmp(name, "GTPU"))
12253                         new_pctype =
12254                                 i40e_find_customized_pctype(pf,
12255                                                       I40E_CUSTOMIZED_GTPU);
12256                 if (new_pctype) {
12257                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12258                                 new_pctype->pctype = pctype_value;
12259                                 new_pctype->valid = true;
12260                         } else {
12261                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12262                                 new_pctype->valid = false;
12263                         }
12264                 }
12265         }
12266
12267         rte_free(pctype);
12268         return 0;
12269 }
12270
12271 static int
12272 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12273                              uint32_t pkg_size, uint32_t proto_num,
12274                              struct rte_pmd_i40e_proto_info *proto,
12275                              enum rte_pmd_i40e_package_op op)
12276 {
12277         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12278         uint16_t port_id = dev->data->port_id;
12279         uint32_t ptype_num;
12280         struct rte_pmd_i40e_ptype_info *ptype;
12281         uint32_t buff_size;
12282         uint8_t proto_id;
12283         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12284         uint32_t i, j, n;
12285         bool in_tunnel;
12286         int ret;
12287
12288         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12289             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12290                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12291                 return -1;
12292         }
12293
12294         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12295                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12296                 return 0;
12297         }
12298
12299         /* get information about new ptype num */
12300         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12301                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12302                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12303         if (ret) {
12304                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12305                 return ret;
12306         }
12307         if (!ptype_num) {
12308                 PMD_DRV_LOG(INFO, "No new ptype added");
12309                 return -1;
12310         }
12311
12312         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12313         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12314         if (!ptype) {
12315                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12316                 return -1;
12317         }
12318
12319         /* get information about new ptype list */
12320         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12321                                         (uint8_t *)ptype, buff_size,
12322                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12323         if (ret) {
12324                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12325                 rte_free(ptype);
12326                 return ret;
12327         }
12328
12329         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12330         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12331         if (!ptype_mapping) {
12332                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12333                 rte_free(ptype);
12334                 return -1;
12335         }
12336
12337         /* Update ptype mapping table. */
12338         for (i = 0; i < ptype_num; i++) {
12339                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12340                 ptype_mapping[i].sw_ptype = 0;
12341                 in_tunnel = false;
12342                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12343                         proto_id = ptype[i].protocols[j];
12344                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12345                                 continue;
12346                         for (n = 0; n < proto_num; n++) {
12347                                 if (proto[n].proto_id != proto_id)
12348                                         continue;
12349                                 memset(name, 0, sizeof(name));
12350                                 strcpy(name, proto[n].name);
12351                                 if (!strncasecmp(name, "PPPOE", 5))
12352                                         ptype_mapping[i].sw_ptype |=
12353                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12354                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12355                                          !in_tunnel) {
12356                                         ptype_mapping[i].sw_ptype |=
12357                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12358                                         ptype_mapping[i].sw_ptype |=
12359                                                 RTE_PTYPE_L4_FRAG;
12360                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12361                                            in_tunnel) {
12362                                         ptype_mapping[i].sw_ptype |=
12363                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12364                                         ptype_mapping[i].sw_ptype |=
12365                                                 RTE_PTYPE_INNER_L4_FRAG;
12366                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12367                                         ptype_mapping[i].sw_ptype |=
12368                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12369                                         in_tunnel = true;
12370                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12371                                            !in_tunnel)
12372                                         ptype_mapping[i].sw_ptype |=
12373                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12374                                 else if (!strncasecmp(name, "IPV4", 4) &&
12375                                          in_tunnel)
12376                                         ptype_mapping[i].sw_ptype |=
12377                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12378                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12379                                          !in_tunnel) {
12380                                         ptype_mapping[i].sw_ptype |=
12381                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12382                                         ptype_mapping[i].sw_ptype |=
12383                                                 RTE_PTYPE_L4_FRAG;
12384                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12385                                            in_tunnel) {
12386                                         ptype_mapping[i].sw_ptype |=
12387                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12388                                         ptype_mapping[i].sw_ptype |=
12389                                                 RTE_PTYPE_INNER_L4_FRAG;
12390                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12391                                         ptype_mapping[i].sw_ptype |=
12392                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12393                                         in_tunnel = true;
12394                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12395                                            !in_tunnel)
12396                                         ptype_mapping[i].sw_ptype |=
12397                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12398                                 else if (!strncasecmp(name, "IPV6", 4) &&
12399                                          in_tunnel)
12400                                         ptype_mapping[i].sw_ptype |=
12401                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12402                                 else if (!strncasecmp(name, "UDP", 3) &&
12403                                          !in_tunnel)
12404                                         ptype_mapping[i].sw_ptype |=
12405                                                 RTE_PTYPE_L4_UDP;
12406                                 else if (!strncasecmp(name, "UDP", 3) &&
12407                                          in_tunnel)
12408                                         ptype_mapping[i].sw_ptype |=
12409                                                 RTE_PTYPE_INNER_L4_UDP;
12410                                 else if (!strncasecmp(name, "TCP", 3) &&
12411                                          !in_tunnel)
12412                                         ptype_mapping[i].sw_ptype |=
12413                                                 RTE_PTYPE_L4_TCP;
12414                                 else if (!strncasecmp(name, "TCP", 3) &&
12415                                          in_tunnel)
12416                                         ptype_mapping[i].sw_ptype |=
12417                                                 RTE_PTYPE_INNER_L4_TCP;
12418                                 else if (!strncasecmp(name, "SCTP", 4) &&
12419                                          !in_tunnel)
12420                                         ptype_mapping[i].sw_ptype |=
12421                                                 RTE_PTYPE_L4_SCTP;
12422                                 else if (!strncasecmp(name, "SCTP", 4) &&
12423                                          in_tunnel)
12424                                         ptype_mapping[i].sw_ptype |=
12425                                                 RTE_PTYPE_INNER_L4_SCTP;
12426                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12427                                           !strncasecmp(name, "ICMPV6", 6)) &&
12428                                          !in_tunnel)
12429                                         ptype_mapping[i].sw_ptype |=
12430                                                 RTE_PTYPE_L4_ICMP;
12431                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12432                                           !strncasecmp(name, "ICMPV6", 6)) &&
12433                                          in_tunnel)
12434                                         ptype_mapping[i].sw_ptype |=
12435                                                 RTE_PTYPE_INNER_L4_ICMP;
12436                                 else if (!strncasecmp(name, "GTPC", 4)) {
12437                                         ptype_mapping[i].sw_ptype |=
12438                                                 RTE_PTYPE_TUNNEL_GTPC;
12439                                         in_tunnel = true;
12440                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12441                                         ptype_mapping[i].sw_ptype |=
12442                                                 RTE_PTYPE_TUNNEL_GTPU;
12443                                         in_tunnel = true;
12444                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12445                                         ptype_mapping[i].sw_ptype |=
12446                                                 RTE_PTYPE_TUNNEL_GRENAT;
12447                                         in_tunnel = true;
12448                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12449                                            !strncasecmp(name, "L2TPV2", 6)) {
12450                                         ptype_mapping[i].sw_ptype |=
12451                                                 RTE_PTYPE_TUNNEL_L2TP;
12452                                         in_tunnel = true;
12453                                 }
12454
12455                                 break;
12456                         }
12457                 }
12458         }
12459
12460         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12461                                                 ptype_num, 0);
12462         if (ret)
12463                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12464
12465         rte_free(ptype_mapping);
12466         rte_free(ptype);
12467         return ret;
12468 }
12469
12470 void
12471 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12472                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12473 {
12474         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12475         uint32_t proto_num;
12476         struct rte_pmd_i40e_proto_info *proto;
12477         uint32_t buff_size;
12478         uint32_t i;
12479         int ret;
12480
12481         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12482             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12483                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12484                 return;
12485         }
12486
12487         /* get information about protocol number */
12488         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12489                                        (uint8_t *)&proto_num, sizeof(proto_num),
12490                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12491         if (ret) {
12492                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12493                 return;
12494         }
12495         if (!proto_num) {
12496                 PMD_DRV_LOG(INFO, "No new protocol added");
12497                 return;
12498         }
12499
12500         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12501         proto = rte_zmalloc("new_proto", buff_size, 0);
12502         if (!proto) {
12503                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12504                 return;
12505         }
12506
12507         /* get information about protocol list */
12508         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12509                                         (uint8_t *)proto, buff_size,
12510                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12511         if (ret) {
12512                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12513                 rte_free(proto);
12514                 return;
12515         }
12516
12517         /* Check if GTP is supported. */
12518         for (i = 0; i < proto_num; i++) {
12519                 if (!strncmp(proto[i].name, "GTP", 3)) {
12520                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12521                                 pf->gtp_support = true;
12522                         else
12523                                 pf->gtp_support = false;
12524                         break;
12525                 }
12526         }
12527
12528         /* Update customized pctype info */
12529         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12530                                             proto_num, proto, op);
12531         if (ret)
12532                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12533
12534         /* Update customized ptype info */
12535         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12536                                            proto_num, proto, op);
12537         if (ret)
12538                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12539
12540         rte_free(proto);
12541 }
12542
12543 /* Create a QinQ cloud filter
12544  *
12545  * The Fortville NIC has limited resources for tunnel filters,
12546  * so we can only reuse existing filters.
12547  *
12548  * In step 1 we define which Field Vector fields can be used for
12549  * filter types.
12550  * As we do not have the inner tag defined as a field,
12551  * we have to define it first, by reusing one of L1 entries.
12552  *
12553  * In step 2 we are replacing one of existing filter types with
12554  * a new one for QinQ.
12555  * As we reusing L1 and replacing L2, some of the default filter
12556  * types will disappear,which depends on L1 and L2 entries we reuse.
12557  *
12558  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12559  *
12560  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12561  *              later when we define the cloud filter.
12562  *      a.      Valid_flags.replace_cloud = 0
12563  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12564  *      c.      New_filter = 0x10
12565  *      d.      TR bit = 0xff (optional, not used here)
12566  *      e.      Buffer – 2 entries:
12567  *              i.      Byte 0 = 8 (outer vlan FV index).
12568  *                      Byte 1 = 0 (rsv)
12569  *                      Byte 2-3 = 0x0fff
12570  *              ii.     Byte 0 = 37 (inner vlan FV index).
12571  *                      Byte 1 =0 (rsv)
12572  *                      Byte 2-3 = 0x0fff
12573  *
12574  * Step 2:
12575  * 2.   Create cloud filter using two L1 filters entries: stag and
12576  *              new filter(outer vlan+ inner vlan)
12577  *      a.      Valid_flags.replace_cloud = 1
12578  *      b.      Old_filter = 1 (instead of outer IP)
12579  *      c.      New_filter = 0x10
12580  *      d.      Buffer – 2 entries:
12581  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12582  *                      Byte 1-3 = 0 (rsv)
12583  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12584  *                      Byte 9-11 = 0 (rsv)
12585  */
12586 static int
12587 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12588 {
12589         int ret = -ENOTSUP;
12590         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12591         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12592         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12593         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12594
12595         if (pf->support_multi_driver) {
12596                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12597                 return ret;
12598         }
12599
12600         /* Init */
12601         memset(&filter_replace, 0,
12602                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12603         memset(&filter_replace_buf, 0,
12604                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12605
12606         /* create L1 filter */
12607         filter_replace.old_filter_type =
12608                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12609         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12610         filter_replace.tr_bit = 0;
12611
12612         /* Prepare the buffer, 2 entries */
12613         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12614         filter_replace_buf.data[0] |=
12615                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12616         /* Field Vector 12b mask */
12617         filter_replace_buf.data[2] = 0xff;
12618         filter_replace_buf.data[3] = 0x0f;
12619         filter_replace_buf.data[4] =
12620                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12621         filter_replace_buf.data[4] |=
12622                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12623         /* Field Vector 12b mask */
12624         filter_replace_buf.data[6] = 0xff;
12625         filter_replace_buf.data[7] = 0x0f;
12626         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12627                         &filter_replace_buf);
12628         if (ret != I40E_SUCCESS)
12629                 return ret;
12630
12631         if (filter_replace.old_filter_type !=
12632             filter_replace.new_filter_type)
12633                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12634                             " original: 0x%x, new: 0x%x",
12635                             dev->device->name,
12636                             filter_replace.old_filter_type,
12637                             filter_replace.new_filter_type);
12638
12639         /* Apply the second L2 cloud filter */
12640         memset(&filter_replace, 0,
12641                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12642         memset(&filter_replace_buf, 0,
12643                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12644
12645         /* create L2 filter, input for L2 filter will be L1 filter  */
12646         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12647         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12648         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12649
12650         /* Prepare the buffer, 2 entries */
12651         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12652         filter_replace_buf.data[0] |=
12653                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12654         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12655         filter_replace_buf.data[4] |=
12656                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12657         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12658                         &filter_replace_buf);
12659         if (!ret && (filter_replace.old_filter_type !=
12660                      filter_replace.new_filter_type))
12661                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12662                             " original: 0x%x, new: 0x%x",
12663                             dev->device->name,
12664                             filter_replace.old_filter_type,
12665                             filter_replace.new_filter_type);
12666
12667         return ret;
12668 }
12669
12670 int
12671 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12672                    const struct rte_flow_action_rss *in)
12673 {
12674         if (in->key_len > RTE_DIM(out->key) ||
12675             in->queue_num > RTE_DIM(out->queue))
12676                 return -EINVAL;
12677         if (!in->key && in->key_len)
12678                 return -EINVAL;
12679         out->conf = (struct rte_flow_action_rss){
12680                 .func = in->func,
12681                 .level = in->level,
12682                 .types = in->types,
12683                 .key_len = in->key_len,
12684                 .queue_num = in->queue_num,
12685                 .queue = memcpy(out->queue, in->queue,
12686                                 sizeof(*in->queue) * in->queue_num),
12687         };
12688         if (in->key)
12689                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12690         return 0;
12691 }
12692
12693 int
12694 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12695                      const struct rte_flow_action_rss *with)
12696 {
12697         return (comp->func == with->func &&
12698                 comp->level == with->level &&
12699                 comp->types == with->types &&
12700                 comp->key_len == with->key_len &&
12701                 comp->queue_num == with->queue_num &&
12702                 !memcmp(comp->key, with->key, with->key_len) &&
12703                 !memcmp(comp->queue, with->queue,
12704                         sizeof(*with->queue) * with->queue_num));
12705 }
12706
12707 int
12708 i40e_config_rss_filter(struct i40e_pf *pf,
12709                 struct i40e_rte_flow_rss_conf *conf, bool add)
12710 {
12711         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12712         uint32_t i, lut = 0;
12713         uint16_t j, num;
12714         struct rte_eth_rss_conf rss_conf = {
12715                 .rss_key = conf->conf.key_len ?
12716                         (void *)(uintptr_t)conf->conf.key : NULL,
12717                 .rss_key_len = conf->conf.key_len,
12718                 .rss_hf = conf->conf.types,
12719         };
12720         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12721
12722         if (!add) {
12723                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12724                         i40e_pf_disable_rss(pf);
12725                         memset(rss_info, 0,
12726                                 sizeof(struct i40e_rte_flow_rss_conf));
12727                         return 0;
12728                 }
12729                 return -EINVAL;
12730         }
12731
12732         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12733          * It's necessary to calculate the actual PF queues that are configured.
12734          */
12735         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12736                 num = i40e_pf_calc_configured_queues_num(pf);
12737         else
12738                 num = pf->dev_data->nb_rx_queues;
12739
12740         num = RTE_MIN(num, conf->conf.queue_num);
12741         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12742                         num);
12743
12744         if (num == 0) {
12745                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12746                 return -ENOTSUP;
12747         }
12748
12749         /* Fill in redirection table */
12750         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12751                 if (j == num)
12752                         j = 0;
12753                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12754                         hw->func_caps.rss_table_entry_width) - 1));
12755                 if ((i & 3) == 3)
12756                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12757         }
12758
12759         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12760                 i40e_pf_disable_rss(pf);
12761                 return 0;
12762         }
12763         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12764                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12765                 /* Random default keys */
12766                 static uint32_t rss_key_default[] = {0x6b793944,
12767                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12768                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12769                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12770
12771                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12772                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12773                                                         sizeof(uint32_t);
12774                 PMD_DRV_LOG(INFO,
12775                         "No valid RSS key config for i40e, using default\n");
12776         }
12777
12778         i40e_hw_rss_hash_set(pf, &rss_conf);
12779
12780         if (i40e_rss_conf_init(rss_info, &conf->conf))
12781                 return -EINVAL;
12782
12783         return 0;
12784 }
12785
12786 RTE_INIT(i40e_init_log)
12787 {
12788         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12789         if (i40e_logtype_init >= 0)
12790                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12791         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12792         if (i40e_logtype_driver >= 0)
12793                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12794 }
12795
12796 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12797                               ETH_I40E_FLOATING_VEB_ARG "=1"
12798                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12799                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12800                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12801                               ETH_I40E_USE_LATEST_VEC "=0|1");