drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_eth_ctrl.h>
  28 #include <rte_tailq.h>
  29 #include <rte_hash_crc.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  47
  48 #define I40E_CLEAR_PXE_WAIT_MS     200
  49
  50 /* Maximun number of capability elements */
  51 #define I40E_MAX_CAP_ELE_NUM       128
  52
  53 /* Wait count and interval */
  54 #define I40E_CHK_Q_ENA_COUNT       1000
  55 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  56
  57 /* Maximun number of VSI */
  58 #define I40E_MAX_NUM_VSIS          (384UL)
  59
  60 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  61
  62 /* Flow control default timer */
  63 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  64
  65 /* Flow control enable fwd bit */
  66 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  67
  68 /* Receive Packet Buffer size */
  69 #define I40E_RXPBSIZE (968 * 1024)
  70
  71 /* Kilobytes shift */
  72 #define I40E_KILOSHIFT 10
  73
  74 /* Flow control default high water */
  75 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Flow control default low water */
  78 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  79
  80 /* Receive Average Packet Size in Byte*/
  81 #define I40E_PACKET_AVERAGE_SIZE 128
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  94
  95 #define I40E_FLOW_TYPES ( \
  96         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 101         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 106         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 107
 108 /* Additional timesync values. */
 109 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 110 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 111 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 112 #define I40E_PRTTSYN_TSYNENA     0x80000000
 113 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 114 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 115
 116 /**
 117  * Below are values for writing un-exposed registers suggested
 118  * by silicon experts
 119  */
 120 /* Destination MAC address */
 121 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 122 /* Source MAC address */
 123 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 124 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 125 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 126 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 127 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 128 /* Single VLAN tag in the inner L2 header */
 129 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 130 /* Source IPv4 address */
 131 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 132 /* Destination IPv4 address */
 133 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 134 /* Source IPv4 address for X722 */
 135 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 136 /* Destination IPv4 address for X722 */
 137 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 138 /* IPv4 Protocol for X722 */
 139 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 140 /* IPv4 Time to Live for X722 */
 141 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 142 /* IPv4 Type of Service (TOS) */
 143 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 144 /* IPv4 Protocol */
 145 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 146 /* IPv4 Time to Live */
 147 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 148 /* Source IPv6 address */
 149 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 150 /* Destination IPv6 address */
 151 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 152 /* IPv6 Traffic Class (TC) */
 153 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 154 /* IPv6 Next Header */
 155 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 156 /* IPv6 Hop Limit */
 157 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 158 /* Source L4 port */
 159 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 160 /* Destination L4 port */
 161 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 162 /* SCTP verification tag */
 163 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 164 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 165 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 166 /* Source port of tunneling UDP */
 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 168 /* Destination port of tunneling UDP */
 169 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 170 /* UDP Tunneling ID, NVGRE/GRE key */
 171 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 172 /* Last ether type */
 173 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 174 /* Tunneling outer destination IPv4 address */
 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 176 /* Tunneling outer destination IPv6 address */
 177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 178 /* 1st word of flex payload */
 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 180 /* 2nd word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 182 /* 3rd word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 184 /* 4th word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 186 /* 5th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 188 /* 6th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 190 /* 7th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 192 /* 8th word of flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 194 /* all 8 words flex payload */
 195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 196 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 197
 198 #define I40E_TRANSLATE_INSET 0
 199 #define I40E_TRANSLATE_REG   1
 200
 201 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 202 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 203 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 204 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 205 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 206 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 207
 208 /* PCI offset for querying capability */
 209 #define PCI_DEV_CAP_REG            0xA4
 210 /* PCI offset for enabling/disabling Extended Tag */
 211 #define PCI_DEV_CTRL_REG           0xA8
 212 /* Bit mask of Extended Tag capability */
 213 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 214 /* Bit shift of Extended Tag enable/disable */
 215 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 216 /* Bit mask of Extended Tag enable/disable */
 217 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 218
 219 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 220 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 221 static int i40e_dev_configure(struct rte_eth_dev *dev);
 222 static int i40e_dev_start(struct rte_eth_dev *dev);
 223 static void i40e_dev_stop(struct rte_eth_dev *dev);
 224 static void i40e_dev_close(struct rte_eth_dev *dev);
 225 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 226 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 227 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 228 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 229 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 230 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 232 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 233                                struct rte_eth_stats *stats);
 234 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 235                                struct rte_eth_xstat *xstats, unsigned n);
 236 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 237                                      struct rte_eth_xstat_name *xstats_names,
 238                                      unsigned limit);
 239 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 240 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 241                                             uint16_t queue_id,
 242                                             uint8_t stat_idx,
 243                                             uint8_t is_rx);
 244 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 245                                 char *fw_version, size_t fw_size);
 246 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 247                               struct rte_eth_dev_info *dev_info);
 248 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 249                                 uint16_t vlan_id,
 250                                 int on);
 251 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 252                               enum rte_vlan_type vlan_type,
 253                               uint16_t tpid);
 254 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 255 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 256                                       uint16_t queue,
 257                                       int on);
 258 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 259 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 260 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 261 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 264                               struct rte_eth_fc_conf *fc_conf);
 265 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 266                                        struct rte_eth_pfc_conf *pfc_conf);
 267 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 268                             struct ether_addr *mac_addr,
 269                             uint32_t index,
 270                             uint32_t pool);
 271 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 272 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 273                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                     uint16_t reta_size);
 275 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 276                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 277                                    uint16_t reta_size);
 278
 279 static int i40e_get_cap(struct i40e_hw *hw);
 280 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 281 static int i40e_pf_setup(struct i40e_pf *pf);
 282 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 283 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 284 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 285 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 286                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 287 static void i40e_stat_update_48(struct i40e_hw *hw,
 288                                uint32_t hireg,
 289                                uint32_t loreg,
 290                                bool offset_loaded,
 291                                uint64_t *offset,
 292                                uint64_t *stat);
 293 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 294 static void i40e_dev_interrupt_handler(void *param);
 295 static void i40e_dev_alarm_handler(void *param);
 296 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 297                                 uint32_t base, uint32_t num);
 298 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 299 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 300                         uint32_t base);
 301 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 302                         uint16_t num);
 303 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 304 static int i40e_veb_release(struct i40e_veb *veb);
 305 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 306                                                 struct i40e_vsi *vsi);
 307 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 308 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 309 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 310                                              struct i40e_macvlan_filter *mv_f,
 311                                              int num,
 312                                              uint16_t vlan);
 313 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 314 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 315                                     struct rte_eth_rss_conf *rss_conf);
 316 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 317                                       struct rte_eth_rss_conf *rss_conf);
 318 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 319                                         struct rte_eth_udp_tunnel *udp_tunnel);
 320 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 321                                         struct rte_eth_udp_tunnel *udp_tunnel);
 322 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 323 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 327                                 enum rte_filter_type filter_type,
 328                                 enum rte_filter_op filter_op,
 329                                 void *arg);
 330 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 331                                   struct rte_eth_dcb_info *dcb_info);
 332 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 333 static void i40e_configure_registers(struct i40e_hw *hw);
 334 static void i40e_hw_init(struct rte_eth_dev *dev);
 335 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 336 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 337                                                      uint16_t seid,
 338                                                      uint16_t rule_type,
 339                                                      uint16_t *entries,
 340                                                      uint16_t count,
 341                                                      uint16_t rule_id);
 342 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 343                         struct rte_eth_mirror_conf *mirror_conf,
 344                         uint8_t sw_id, uint8_t on);
 345 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 346
 347 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 348 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 349 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp,
 351                                            uint32_t flags);
 352 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 353                                            struct timespec *timestamp);
 354 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 355
 356 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 357
 358 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 359                                    struct timespec *timestamp);
 360 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 361                                     const struct timespec *timestamp);
 362
 363 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 364                                          uint16_t queue_id);
 365 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 366                                           uint16_t queue_id);
 367
 368 static int i40e_get_regs(struct rte_eth_dev *dev,
 369                          struct rte_dev_reg_info *regs);
 370
 371 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 372
 373 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 374                            struct rte_dev_eeprom_info *eeprom);
 375
 376 static int i40e_get_module_info(struct rte_eth_dev *dev,
 377                                 struct rte_eth_dev_module_info *modinfo);
 378 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 379                                   struct rte_dev_eeprom_info *info);
 380
 381 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 382                                       struct ether_addr *mac_addr);
 383
 384 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 385
 386 static int i40e_ethertype_filter_convert(
 387         const struct rte_eth_ethertype_filter *input,
 388         struct i40e_ethertype_filter *filter);
 389 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 390                                    struct i40e_ethertype_filter *filter);
 391
 392 static int i40e_tunnel_filter_convert(
 393         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 394         struct i40e_tunnel_filter *tunnel_filter);
 395 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 396                                 struct i40e_tunnel_filter *tunnel_filter);
 397 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 398
 399 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 400 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 401 static void i40e_filter_restore(struct i40e_pf *pf);
 402 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 403
 404 int i40e_logtype_init;
 405 int i40e_logtype_driver;
 406
 407 static const char *const valid_keys[] = {
 408         ETH_I40E_FLOATING_VEB_ARG,
 409         ETH_I40E_FLOATING_VEB_LIST_ARG,
 410         ETH_I40E_SUPPORT_MULTI_DRIVER,
 411         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 412         NULL};
 413
 414 static const struct rte_pci_id pci_id_i40e_map[] = {
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 435         { .vendor_id = 0, /* sentinel */ },
 436 };
 437
 438 static const struct eth_dev_ops i40e_eth_dev_ops = {
 439         .dev_configure                = i40e_dev_configure,
 440         .dev_start                    = i40e_dev_start,
 441         .dev_stop                     = i40e_dev_stop,
 442         .dev_close                    = i40e_dev_close,
 443         .dev_reset                    = i40e_dev_reset,
 444         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 445         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 446         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 447         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 448         .dev_set_link_up              = i40e_dev_set_link_up,
 449         .dev_set_link_down            = i40e_dev_set_link_down,
 450         .link_update                  = i40e_dev_link_update,
 451         .stats_get                    = i40e_dev_stats_get,
 452         .xstats_get                   = i40e_dev_xstats_get,
 453         .xstats_get_names             = i40e_dev_xstats_get_names,
 454         .stats_reset                  = i40e_dev_stats_reset,
 455         .xstats_reset                 = i40e_dev_stats_reset,
 456         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 457         .fw_version_get               = i40e_fw_version_get,
 458         .dev_infos_get                = i40e_dev_info_get,
 459         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 460         .vlan_filter_set              = i40e_vlan_filter_set,
 461         .vlan_tpid_set                = i40e_vlan_tpid_set,
 462         .vlan_offload_set             = i40e_vlan_offload_set,
 463         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 464         .vlan_pvid_set                = i40e_vlan_pvid_set,
 465         .rx_queue_start               = i40e_dev_rx_queue_start,
 466         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 467         .tx_queue_start               = i40e_dev_tx_queue_start,
 468         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 469         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 470         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 471         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 472         .rx_queue_release             = i40e_dev_rx_queue_release,
 473         .rx_queue_count               = i40e_dev_rx_queue_count,
 474         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 475         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 476         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 477         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 478         .tx_queue_release             = i40e_dev_tx_queue_release,
 479         .dev_led_on                   = i40e_dev_led_on,
 480         .dev_led_off                  = i40e_dev_led_off,
 481         .flow_ctrl_get                = i40e_flow_ctrl_get,
 482         .flow_ctrl_set                = i40e_flow_ctrl_set,
 483         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 484         .mac_addr_add                 = i40e_macaddr_add,
 485         .mac_addr_remove              = i40e_macaddr_remove,
 486         .reta_update                  = i40e_dev_rss_reta_update,
 487         .reta_query                   = i40e_dev_rss_reta_query,
 488         .rss_hash_update              = i40e_dev_rss_hash_update,
 489         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 490         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 491         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 492         .filter_ctrl                  = i40e_dev_filter_ctrl,
 493         .rxq_info_get                 = i40e_rxq_info_get,
 494         .txq_info_get                 = i40e_txq_info_get,
 495         .mirror_rule_set              = i40e_mirror_rule_set,
 496         .mirror_rule_reset            = i40e_mirror_rule_reset,
 497         .timesync_enable              = i40e_timesync_enable,
 498         .timesync_disable             = i40e_timesync_disable,
 499         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 500         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 501         .get_dcb_info                 = i40e_dev_get_dcb_info,
 502         .timesync_adjust_time         = i40e_timesync_adjust_time,
 503         .timesync_read_time           = i40e_timesync_read_time,
 504         .timesync_write_time          = i40e_timesync_write_time,
 505         .get_reg                      = i40e_get_regs,
 506         .get_eeprom_length            = i40e_get_eeprom_length,
 507         .get_eeprom                   = i40e_get_eeprom,
 508         .get_module_info              = i40e_get_module_info,
 509         .get_module_eeprom            = i40e_get_module_eeprom,
 510         .mac_addr_set                 = i40e_set_default_mac_addr,
 511         .mtu_set                      = i40e_dev_mtu_set,
 512         .tm_ops_get                   = i40e_tm_ops_get,
 513 };
 514
 515 /* store statistics names and its offset in stats structure */
 516 struct rte_i40e_xstats_name_off {
 517         char name[RTE_ETH_XSTATS_NAME_SIZE];
 518         unsigned offset;
 519 };
 520
 521 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 522         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 523         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 524         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 525         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 526         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 527                 rx_unknown_protocol)},
 528         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 529         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 530         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 531         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 532 };
 533
 534 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 535                 sizeof(rte_i40e_stats_strings[0]))
 536
 537 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 538         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 539                 tx_dropped_link_down)},
 540         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 541         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 542                 illegal_bytes)},
 543         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 544         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 545                 mac_local_faults)},
 546         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 547                 mac_remote_faults)},
 548         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 549                 rx_length_errors)},
 550         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 551         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 552         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 553         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 554         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 555         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 556                 rx_size_127)},
 557         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 558                 rx_size_255)},
 559         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_511)},
 561         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_1023)},
 563         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_1522)},
 565         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_big)},
 567         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 568                 rx_undersize)},
 569         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 570                 rx_oversize)},
 571         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 572                 mac_short_packet_dropped)},
 573         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_fragments)},
 575         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 576         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 577         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 578                 tx_size_127)},
 579         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 580                 tx_size_255)},
 581         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_511)},
 583         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_1023)},
 585         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_1522)},
 587         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_big)},
 589         {"rx_flow_director_atr_match_packets",
 590                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 591         {"rx_flow_director_sb_match_packets",
 592                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 593         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 594                 tx_lpi_status)},
 595         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 596                 rx_lpi_status)},
 597         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 598                 tx_lpi_count)},
 599         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 600                 rx_lpi_count)},
 601 };
 602
 603 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 604                 sizeof(rte_i40e_hw_port_strings[0]))
 605
 606 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 607         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 608                 priority_xon_rx)},
 609         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xoff_rx)},
 611 };
 612
 613 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 614                 sizeof(rte_i40e_rxq_prio_strings[0]))
 615
 616 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 617         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 618                 priority_xon_tx)},
 619         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xoff_tx)},
 621         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xon_2_xoff)},
 623 };
 624
 625 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 626                 sizeof(rte_i40e_txq_prio_strings[0]))
 627
 628 static int
 629 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 630         struct rte_pci_device *pci_dev)
 631 {
 632         char name[RTE_ETH_NAME_MAX_LEN];
 633         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 634         int i, retval;
 635
 636         if (pci_dev->device.devargs) {
 637                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 638                                 &eth_da);
 639                 if (retval)
 640                         return retval;
 641         }
 642
 643         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 644                 sizeof(struct i40e_adapter),
 645                 eth_dev_pci_specific_init, pci_dev,
 646                 eth_i40e_dev_init, NULL);
 647
 648         if (retval || eth_da.nb_representor_ports < 1)
 649                 return retval;
 650
 651         /* probe VF representor ports */
 652         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 653                 pci_dev->device.name);
 654
 655         if (pf_ethdev == NULL)
 656                 return -ENODEV;
 657
 658         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 659                 struct i40e_vf_representor representor = {
 660                         .vf_id = eth_da.representor_ports[i],
 661                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 662                                 pf_ethdev->data->dev_private)->switch_domain_id,
 663                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 664                                 pf_ethdev->data->dev_private)
 665                 };
 666
 667                 /* representor port net_bdf_port */
 668                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 669                         pci_dev->device.name, eth_da.representor_ports[i]);
 670
 671                 retval = rte_eth_dev_create(&pci_dev->device, name,
 672                         sizeof(struct i40e_vf_representor), NULL, NULL,
 673                         i40e_vf_representor_init, &representor);
 674
 675                 if (retval)
 676                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 677                                 "representor %s.", name);
 678         }
 679
 680         return 0;
 681 }
 682
 683 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 684 {
 685         struct rte_eth_dev *ethdev;
 686
 687         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 688         if (!ethdev)
 689                 return -ENODEV;
 690
 691
 692         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 693                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 694         else
 695                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 696 }
 697
 698 static struct rte_pci_driver rte_i40e_pmd = {
 699         .id_table = pci_id_i40e_map,
 700         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 701                      RTE_PCI_DRV_IOVA_AS_VA,
 702         .probe = eth_i40e_pci_probe,
 703         .remove = eth_i40e_pci_remove,
 704 };
 705
 706 static inline void
 707 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 708                          uint32_t reg_val)
 709 {
 710         uint32_t ori_reg_val;
 711         struct rte_eth_dev *dev;
 712
 713         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 714         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 715         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 716         if (ori_reg_val != reg_val)
 717                 PMD_DRV_LOG(WARNING,
 718                             "i40e device %s changed global register [0x%08x]."
 719                             " original: 0x%08x, new: 0x%08x",
 720                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 721 }
 722
 723 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 724 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 725 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 726
 727 #ifndef I40E_GLQF_ORT
 728 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 729 #endif
 730 #ifndef I40E_GLQF_PIT
 731 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 732 #endif
 733 #ifndef I40E_GLQF_L3_MAP
 734 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 735 #endif
 736
 737 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 738 {
 739         /*
 740          * Initialize registers for parsing packet type of QinQ
 741          * This should be removed from code once proper
 742          * configuration API is added to avoid configuration conflicts
 743          * between ports of the same device.
 744          */
 745         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 746         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 747 }
 748
 749 static inline void i40e_config_automask(struct i40e_pf *pf)
 750 {
 751         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 752         uint32_t val;
 753
 754         /* INTENA flag is not auto-cleared for interrupt */
 755         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 756         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 757                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 758
 759         /* If support multi-driver, PF will use INT0. */
 760         if (!pf->support_multi_driver)
 761                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 762
 763         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 764 }
 765
 766 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 767
 768 /*
 769  * Add a ethertype filter to drop all flow control frames transmitted
 770  * from VSIs.
 771 */
 772 static void
 773 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 774 {
 775         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 776         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 777                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 778                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 779         int ret;
 780
 781         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 782                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 783                                 pf->main_vsi_seid, 0,
 784                                 TRUE, NULL, NULL);
 785         if (ret)
 786                 PMD_INIT_LOG(ERR,
 787                         "Failed to add filter to drop flow control frames from VSIs.");
 788 }
 789
 790 static int
 791 floating_veb_list_handler(__rte_unused const char *key,
 792                           const char *floating_veb_value,
 793                           void *opaque)
 794 {
 795         int idx = 0;
 796         unsigned int count = 0;
 797         char *end = NULL;
 798         int min, max;
 799         bool *vf_floating_veb = opaque;
 800
 801         while (isblank(*floating_veb_value))
 802                 floating_veb_value++;
 803
 804         /* Reset floating VEB configuration for VFs */
 805         for (idx = 0; idx < I40E_MAX_VF; idx++)
 806                 vf_floating_veb[idx] = false;
 807
 808         min = I40E_MAX_VF;
 809         do {
 810                 while (isblank(*floating_veb_value))
 811                         floating_veb_value++;
 812                 if (*floating_veb_value == '\0')
 813                         return -1;
 814                 errno = 0;
 815                 idx = strtoul(floating_veb_value, &end, 10);
 816                 if (errno || end == NULL)
 817                         return -1;
 818                 while (isblank(*end))
 819                         end++;
 820                 if (*end == '-') {
 821                         min = idx;
 822                 } else if ((*end == ';') || (*end == '\0')) {
 823                         max = idx;
 824                         if (min == I40E_MAX_VF)
 825                                 min = idx;
 826                         if (max >= I40E_MAX_VF)
 827                                 max = I40E_MAX_VF - 1;
 828                         for (idx = min; idx <= max; idx++) {
 829                                 vf_floating_veb[idx] = true;
 830                                 count++;
 831                         }
 832                         min = I40E_MAX_VF;
 833                 } else {
 834                         return -1;
 835                 }
 836                 floating_veb_value = end + 1;
 837         } while (*end != '\0');
 838
 839         if (count == 0)
 840                 return -1;
 841
 842         return 0;
 843 }
 844
 845 static void
 846 config_vf_floating_veb(struct rte_devargs *devargs,
 847                        uint16_t floating_veb,
 848                        bool *vf_floating_veb)
 849 {
 850         struct rte_kvargs *kvlist;
 851         int i;
 852         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 853
 854         if (!floating_veb)
 855                 return;
 856         /* All the VFs attach to the floating VEB by default
 857          * when the floating VEB is enabled.
 858          */
 859         for (i = 0; i < I40E_MAX_VF; i++)
 860                 vf_floating_veb[i] = true;
 861
 862         if (devargs == NULL)
 863                 return;
 864
 865         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 866         if (kvlist == NULL)
 867                 return;
 868
 869         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 870                 rte_kvargs_free(kvlist);
 871                 return;
 872         }
 873         /* When the floating_veb_list parameter exists, all the VFs
 874          * will attach to the legacy VEB firstly, then configure VFs
 875          * to the floating VEB according to the floating_veb_list.
 876          */
 877         if (rte_kvargs_process(kvlist, floating_veb_list,
 878                                floating_veb_list_handler,
 879                                vf_floating_veb) < 0) {
 880                 rte_kvargs_free(kvlist);
 881                 return;
 882         }
 883         rte_kvargs_free(kvlist);
 884 }
 885
 886 static int
 887 i40e_check_floating_handler(__rte_unused const char *key,
 888                             const char *value,
 889                             __rte_unused void *opaque)
 890 {
 891         if (strcmp(value, "1"))
 892                 return -1;
 893
 894         return 0;
 895 }
 896
 897 static int
 898 is_floating_veb_supported(struct rte_devargs *devargs)
 899 {
 900         struct rte_kvargs *kvlist;
 901         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 902
 903         if (devargs == NULL)
 904                 return 0;
 905
 906         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 907         if (kvlist == NULL)
 908                 return 0;
 909
 910         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 911                 rte_kvargs_free(kvlist);
 912                 return 0;
 913         }
 914         /* Floating VEB is enabled when there's key-value:
 915          * enable_floating_veb=1
 916          */
 917         if (rte_kvargs_process(kvlist, floating_veb_key,
 918                                i40e_check_floating_handler, NULL) < 0) {
 919                 rte_kvargs_free(kvlist);
 920                 return 0;
 921         }
 922         rte_kvargs_free(kvlist);
 923
 924         return 1;
 925 }
 926
 927 static void
 928 config_floating_veb(struct rte_eth_dev *dev)
 929 {
 930         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 931         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 933
 934         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 935
 936         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 937                 pf->floating_veb =
 938                         is_floating_veb_supported(pci_dev->device.devargs);
 939                 config_vf_floating_veb(pci_dev->device.devargs,
 940                                        pf->floating_veb,
 941                                        pf->floating_veb_list);
 942         } else {
 943                 pf->floating_veb = false;
 944         }
 945 }
 946
 947 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 948 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 949
 950 static int
 951 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 952 {
 953         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 954         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 955         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 956         int ret;
 957
 958         struct rte_hash_parameters ethertype_hash_params = {
 959                 .name = ethertype_hash_name,
 960                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 961                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 962                 .hash_func = rte_hash_crc,
 963                 .hash_func_init_val = 0,
 964                 .socket_id = rte_socket_id(),
 965         };
 966
 967         /* Initialize ethertype filter rule list and hash */
 968         TAILQ_INIT(&ethertype_rule->ethertype_list);
 969         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 970                  "ethertype_%s", dev->device->name);
 971         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 972         if (!ethertype_rule->hash_table) {
 973                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 974                 return -EINVAL;
 975         }
 976         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 977                                        sizeof(struct i40e_ethertype_filter *) *
 978                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 979                                        0);
 980         if (!ethertype_rule->hash_map) {
 981                 PMD_INIT_LOG(ERR,
 982                              "Failed to allocate memory for ethertype hash map!");
 983                 ret = -ENOMEM;
 984                 goto err_ethertype_hash_map_alloc;
 985         }
 986
 987         return 0;
 988
 989 err_ethertype_hash_map_alloc:
 990         rte_hash_free(ethertype_rule->hash_table);
 991
 992         return ret;
 993 }
 994
 995 static int
 996 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 997 {
 998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 999         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1000         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1001         int ret;
1002
1003         struct rte_hash_parameters tunnel_hash_params = {
1004                 .name = tunnel_hash_name,
1005                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1006                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1007                 .hash_func = rte_hash_crc,
1008                 .hash_func_init_val = 0,
1009                 .socket_id = rte_socket_id(),
1010         };
1011
1012         /* Initialize tunnel filter rule list and hash */
1013         TAILQ_INIT(&tunnel_rule->tunnel_list);
1014         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1015                  "tunnel_%s", dev->device->name);
1016         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1017         if (!tunnel_rule->hash_table) {
1018                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1019                 return -EINVAL;
1020         }
1021         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1022                                     sizeof(struct i40e_tunnel_filter *) *
1023                                     I40E_MAX_TUNNEL_FILTER_NUM,
1024                                     0);
1025         if (!tunnel_rule->hash_map) {
1026                 PMD_INIT_LOG(ERR,
1027                              "Failed to allocate memory for tunnel hash map!");
1028                 ret = -ENOMEM;
1029                 goto err_tunnel_hash_map_alloc;
1030         }
1031
1032         return 0;
1033
1034 err_tunnel_hash_map_alloc:
1035         rte_hash_free(tunnel_rule->hash_table);
1036
1037         return ret;
1038 }
1039
1040 static int
1041 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1042 {
1043         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1044         struct i40e_fdir_info *fdir_info = &pf->fdir;
1045         char fdir_hash_name[RTE_HASH_NAMESIZE];
1046         int ret;
1047
1048         struct rte_hash_parameters fdir_hash_params = {
1049                 .name = fdir_hash_name,
1050                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1051                 .key_len = sizeof(struct i40e_fdir_input),
1052                 .hash_func = rte_hash_crc,
1053                 .hash_func_init_val = 0,
1054                 .socket_id = rte_socket_id(),
1055         };
1056
1057         /* Initialize flow director filter rule list and hash */
1058         TAILQ_INIT(&fdir_info->fdir_list);
1059         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1060                  "fdir_%s", dev->device->name);
1061         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1062         if (!fdir_info->hash_table) {
1063                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1064                 return -EINVAL;
1065         }
1066         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1067                                           sizeof(struct i40e_fdir_filter *) *
1068                                           I40E_MAX_FDIR_FILTER_NUM,
1069                                           0);
1070         if (!fdir_info->hash_map) {
1071                 PMD_INIT_LOG(ERR,
1072                              "Failed to allocate memory for fdir hash map!");
1073                 ret = -ENOMEM;
1074                 goto err_fdir_hash_map_alloc;
1075         }
1076         return 0;
1077
1078 err_fdir_hash_map_alloc:
1079         rte_hash_free(fdir_info->hash_table);
1080
1081         return ret;
1082 }
1083
1084 static void
1085 i40e_init_customized_info(struct i40e_pf *pf)
1086 {
1087         int i;
1088
1089         /* Initialize customized pctype */
1090         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1091                 pf->customized_pctype[i].index = i;
1092                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1093                 pf->customized_pctype[i].valid = false;
1094         }
1095
1096         pf->gtp_support = false;
1097 }
1098
1099 void
1100 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1101 {
1102         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1103         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1104         struct i40e_queue_regions *info = &pf->queue_region;
1105         uint16_t i;
1106
1107         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1108                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1109
1110         memset(info, 0, sizeof(struct i40e_queue_regions));
1111 }
1112
1113 static int
1114 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1115                                const char *value,
1116                                void *opaque)
1117 {
1118         struct i40e_pf *pf;
1119         unsigned long support_multi_driver;
1120         char *end;
1121
1122         pf = (struct i40e_pf *)opaque;
1123
1124         errno = 0;
1125         support_multi_driver = strtoul(value, &end, 10);
1126         if (errno != 0 || end == value || *end != 0) {
1127                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1128                 return -(EINVAL);
1129         }
1130
1131         if (support_multi_driver == 1 || support_multi_driver == 0)
1132                 pf->support_multi_driver = (bool)support_multi_driver;
1133         else
1134                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1135                             "enable global configuration by default."
1136                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1137         return 0;
1138 }
1139
1140 static int
1141 i40e_support_multi_driver(struct rte_eth_dev *dev)
1142 {
1143         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1144         struct rte_kvargs *kvlist;
1145         int kvargs_count;
1146
1147         /* Enable global configuration by default */
1148         pf->support_multi_driver = false;
1149
1150         if (!dev->device->devargs)
1151                 return 0;
1152
1153         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1154         if (!kvlist)
1155                 return -EINVAL;
1156
1157         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1158         if (!kvargs_count) {
1159                 rte_kvargs_free(kvlist);
1160                 return 0;
1161         }
1162
1163         if (kvargs_count > 1)
1164                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1165                             "the first invalid or last valid one is used !",
1166                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1167
1168         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1169                                i40e_parse_multi_drv_handler, pf) < 0) {
1170                 rte_kvargs_free(kvlist);
1171                 return -EINVAL;
1172         }
1173
1174         rte_kvargs_free(kvlist);
1175         return 0;
1176 }
1177
1178 static int
1179 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1180                                     uint32_t reg_addr, uint64_t reg_val,
1181                                     struct i40e_asq_cmd_details *cmd_details)
1182 {
1183         uint64_t ori_reg_val;
1184         struct rte_eth_dev *dev;
1185         int ret;
1186
1187         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1188         if (ret != I40E_SUCCESS) {
1189                 PMD_DRV_LOG(ERR,
1190                             "Fail to debug read from 0x%08x",
1191                             reg_addr);
1192                 return -EIO;
1193         }
1194         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1195
1196         if (ori_reg_val != reg_val)
1197                 PMD_DRV_LOG(WARNING,
1198                             "i40e device %s changed global register [0x%08x]."
1199                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1200                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1201
1202         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1203 }
1204
1205 #define I40E_ALARM_INTERVAL 50000 /* us */
1206
1207 static int
1208 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1209 {
1210         struct rte_pci_device *pci_dev;
1211         struct rte_intr_handle *intr_handle;
1212         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1213         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1214         struct i40e_vsi *vsi;
1215         int ret;
1216         uint32_t len;
1217         uint8_t aq_fail = 0;
1218
1219         PMD_INIT_FUNC_TRACE();
1220
1221         dev->dev_ops = &i40e_eth_dev_ops;
1222         dev->rx_pkt_burst = i40e_recv_pkts;
1223         dev->tx_pkt_burst = i40e_xmit_pkts;
1224         dev->tx_pkt_prepare = i40e_prep_pkts;
1225
1226         /* for secondary processes, we don't initialise any further as primary
1227          * has already done this work. Only check we don't need a different
1228          * RX function */
1229         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1230                 i40e_set_rx_function(dev);
1231                 i40e_set_tx_function(dev);
1232                 return 0;
1233         }
1234         i40e_set_default_ptype_table(dev);
1235         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1236         intr_handle = &pci_dev->intr_handle;
1237
1238         rte_eth_copy_pci_info(dev, pci_dev);
1239
1240         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1241         pf->adapter->eth_dev = dev;
1242         pf->dev_data = dev->data;
1243
1244         hw->back = I40E_PF_TO_ADAPTER(pf);
1245         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1246         if (!hw->hw_addr) {
1247                 PMD_INIT_LOG(ERR,
1248                         "Hardware is not available, as address is NULL");
1249                 return -ENODEV;
1250         }
1251
1252         hw->vendor_id = pci_dev->id.vendor_id;
1253         hw->device_id = pci_dev->id.device_id;
1254         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1255         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1256         hw->bus.device = pci_dev->addr.devid;
1257         hw->bus.func = pci_dev->addr.function;
1258         hw->adapter_stopped = 0;
1259
1260         /*
1261          * Switch Tag value should not be identical to either the First Tag
1262          * or Second Tag values. So set something other than common Ethertype
1263          * for internal switching.
1264          */
1265         hw->switch_tag = 0xffff;
1266
1267         /* Check if need to support multi-driver */
1268         i40e_support_multi_driver(dev);
1269
1270         /* Make sure all is clean before doing PF reset */
1271         i40e_clear_hw(hw);
1272
1273         /* Initialize the hardware */
1274         i40e_hw_init(dev);
1275
1276         /* Reset here to make sure all is clean for each PF */
1277         ret = i40e_pf_reset(hw);
1278         if (ret) {
1279                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1280                 return ret;
1281         }
1282
1283         /* Initialize the shared code (base driver) */
1284         ret = i40e_init_shared_code(hw);
1285         if (ret) {
1286                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1287                 return ret;
1288         }
1289
1290         i40e_config_automask(pf);
1291
1292         i40e_set_default_pctype_table(dev);
1293
1294         /*
1295          * To work around the NVM issue, initialize registers
1296          * for packet type of QinQ by software.
1297          * It should be removed once issues are fixed in NVM.
1298          */
1299         if (!pf->support_multi_driver)
1300                 i40e_GLQF_reg_init(hw);
1301
1302         /* Initialize the input set for filters (hash and fd) to default value */
1303         i40e_filter_input_set_init(pf);
1304
1305         /* Initialize the parameters for adminq */
1306         i40e_init_adminq_parameter(hw);
1307         ret = i40e_init_adminq(hw);
1308         if (ret != I40E_SUCCESS) {
1309                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1310                 return -EIO;
1311         }
1312         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1313                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1314                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1315                      ((hw->nvm.version >> 12) & 0xf),
1316                      ((hw->nvm.version >> 4) & 0xff),
1317                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1318
1319         /* initialise the L3_MAP register */
1320         if (!pf->support_multi_driver) {
1321                 ret = i40e_aq_debug_write_global_register(hw,
1322                                                    I40E_GLQF_L3_MAP(40),
1323                                                    0x00000028,  NULL);
1324                 if (ret)
1325                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1326                                      ret);
1327                 PMD_INIT_LOG(DEBUG,
1328                              "Global register 0x%08x is changed with 0x28",
1329                              I40E_GLQF_L3_MAP(40));
1330         }
1331
1332         /* Need the special FW version to support floating VEB */
1333         config_floating_veb(dev);
1334         /* Clear PXE mode */
1335         i40e_clear_pxe_mode(hw);
1336         i40e_dev_sync_phy_type(hw);
1337
1338         /*
1339          * On X710, performance number is far from the expectation on recent
1340          * firmware versions. The fix for this issue may not be integrated in
1341          * the following firmware version. So the workaround in software driver
1342          * is needed. It needs to modify the initial values of 3 internal only
1343          * registers. Note that the workaround can be removed when it is fixed
1344          * in firmware in the future.
1345          */
1346         i40e_configure_registers(hw);
1347
1348         /* Get hw capabilities */
1349         ret = i40e_get_cap(hw);
1350         if (ret != I40E_SUCCESS) {
1351                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1352                 goto err_get_capabilities;
1353         }
1354
1355         /* Initialize parameters for PF */
1356         ret = i40e_pf_parameter_init(dev);
1357         if (ret != 0) {
1358                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1359                 goto err_parameter_init;
1360         }
1361
1362         /* Initialize the queue management */
1363         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1364         if (ret < 0) {
1365                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1366                 goto err_qp_pool_init;
1367         }
1368         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1369                                 hw->func_caps.num_msix_vectors - 1);
1370         if (ret < 0) {
1371                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1372                 goto err_msix_pool_init;
1373         }
1374
1375         /* Initialize lan hmc */
1376         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1377                                 hw->func_caps.num_rx_qp, 0, 0);
1378         if (ret != I40E_SUCCESS) {
1379                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1380                 goto err_init_lan_hmc;
1381         }
1382
1383         /* Configure lan hmc */
1384         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1385         if (ret != I40E_SUCCESS) {
1386                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1387                 goto err_configure_lan_hmc;
1388         }
1389
1390         /* Get and check the mac address */
1391         i40e_get_mac_addr(hw, hw->mac.addr);
1392         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1393                 PMD_INIT_LOG(ERR, "mac address is not valid");
1394                 ret = -EIO;
1395                 goto err_get_mac_addr;
1396         }
1397         /* Copy the permanent MAC address */
1398         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1399                         (struct ether_addr *) hw->mac.perm_addr);
1400
1401         /* Disable flow control */
1402         hw->fc.requested_mode = I40E_FC_NONE;
1403         i40e_set_fc(hw, &aq_fail, TRUE);
1404
1405         /* Set the global registers with default ether type value */
1406         if (!pf->support_multi_driver) {
1407                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1408                                          ETHER_TYPE_VLAN);
1409                 if (ret != I40E_SUCCESS) {
1410                         PMD_INIT_LOG(ERR,
1411                                      "Failed to set the default outer "
1412                                      "VLAN ether type");
1413                         goto err_setup_pf_switch;
1414                 }
1415         }
1416
1417         /* PF setup, which includes VSI setup */
1418         ret = i40e_pf_setup(pf);
1419         if (ret) {
1420                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1421                 goto err_setup_pf_switch;
1422         }
1423
1424         /* reset all stats of the device, including pf and main vsi */
1425         i40e_dev_stats_reset(dev);
1426
1427         vsi = pf->main_vsi;
1428
1429         /* Disable double vlan by default */
1430         i40e_vsi_config_double_vlan(vsi, FALSE);
1431
1432         /* Disable S-TAG identification when floating_veb is disabled */
1433         if (!pf->floating_veb) {
1434                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1435                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1436                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1437                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1438                 }
1439         }
1440
1441         if (!vsi->max_macaddrs)
1442                 len = ETHER_ADDR_LEN;
1443         else
1444                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1445
1446         /* Should be after VSI initialized */
1447         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1448         if (!dev->data->mac_addrs) {
1449                 PMD_INIT_LOG(ERR,
1450                         "Failed to allocated memory for storing mac address");
1451                 goto err_mac_alloc;
1452         }
1453         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1454                                         &dev->data->mac_addrs[0]);
1455
1456         /* Init dcb to sw mode by default */
1457         ret = i40e_dcb_init_configure(dev, TRUE);
1458         if (ret != I40E_SUCCESS) {
1459                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1460                 pf->flags &= ~I40E_FLAG_DCB;
1461         }
1462         /* Update HW struct after DCB configuration */
1463         i40e_get_cap(hw);
1464
1465         /* initialize pf host driver to setup SRIOV resource if applicable */
1466         i40e_pf_host_init(dev);
1467
1468         /* register callback func to eal lib */
1469         rte_intr_callback_register(intr_handle,
1470                                    i40e_dev_interrupt_handler, dev);
1471
1472         /* configure and enable device interrupt */
1473         i40e_pf_config_irq0(hw, TRUE);
1474         i40e_pf_enable_irq0(hw);
1475
1476         /* enable uio intr after callback register */
1477         rte_intr_enable(intr_handle);
1478
1479         /* By default disable flexible payload in global configuration */
1480         if (!pf->support_multi_driver)
1481                 i40e_flex_payload_reg_set_default(hw);
1482
1483         /*
1484          * Add an ethertype filter to drop all flow control frames transmitted
1485          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1486          * frames to wire.
1487          */
1488         i40e_add_tx_flow_control_drop_filter(pf);
1489
1490         /* Set the max frame size to 0x2600 by default,
1491          * in case other drivers changed the default value.
1492          */
1493         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1494
1495         /* initialize mirror rule list */
1496         TAILQ_INIT(&pf->mirror_list);
1497
1498         /* initialize Traffic Manager configuration */
1499         i40e_tm_conf_init(dev);
1500
1501         /* Initialize customized information */
1502         i40e_init_customized_info(pf);
1503
1504         ret = i40e_init_ethtype_filter_list(dev);
1505         if (ret < 0)
1506                 goto err_init_ethtype_filter_list;
1507         ret = i40e_init_tunnel_filter_list(dev);
1508         if (ret < 0)
1509                 goto err_init_tunnel_filter_list;
1510         ret = i40e_init_fdir_filter_list(dev);
1511         if (ret < 0)
1512                 goto err_init_fdir_filter_list;
1513
1514         /* initialize queue region configuration */
1515         i40e_init_queue_region_conf(dev);
1516
1517         /* initialize rss configuration from rte_flow */
1518         memset(&pf->rss_info, 0,
1519                 sizeof(struct i40e_rte_flow_rss_conf));
1520
1521         return 0;
1522
1523 err_init_fdir_filter_list:
1524         rte_free(pf->tunnel.hash_table);
1525         rte_free(pf->tunnel.hash_map);
1526 err_init_tunnel_filter_list:
1527         rte_free(pf->ethertype.hash_table);
1528         rte_free(pf->ethertype.hash_map);
1529 err_init_ethtype_filter_list:
1530         rte_free(dev->data->mac_addrs);
1531 err_mac_alloc:
1532         i40e_vsi_release(pf->main_vsi);
1533 err_setup_pf_switch:
1534 err_get_mac_addr:
1535 err_configure_lan_hmc:
1536         (void)i40e_shutdown_lan_hmc(hw);
1537 err_init_lan_hmc:
1538         i40e_res_pool_destroy(&pf->msix_pool);
1539 err_msix_pool_init:
1540         i40e_res_pool_destroy(&pf->qp_pool);
1541 err_qp_pool_init:
1542 err_parameter_init:
1543 err_get_capabilities:
1544         (void)i40e_shutdown_adminq(hw);
1545
1546         return ret;
1547 }
1548
1549 static void
1550 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1551 {
1552         struct i40e_ethertype_filter *p_ethertype;
1553         struct i40e_ethertype_rule *ethertype_rule;
1554
1555         ethertype_rule = &pf->ethertype;
1556         /* Remove all ethertype filter rules and hash */
1557         if (ethertype_rule->hash_map)
1558                 rte_free(ethertype_rule->hash_map);
1559         if (ethertype_rule->hash_table)
1560                 rte_hash_free(ethertype_rule->hash_table);
1561
1562         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1563                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1564                              p_ethertype, rules);
1565                 rte_free(p_ethertype);
1566         }
1567 }
1568
1569 static void
1570 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1571 {
1572         struct i40e_tunnel_filter *p_tunnel;
1573         struct i40e_tunnel_rule *tunnel_rule;
1574
1575         tunnel_rule = &pf->tunnel;
1576         /* Remove all tunnel director rules and hash */
1577         if (tunnel_rule->hash_map)
1578                 rte_free(tunnel_rule->hash_map);
1579         if (tunnel_rule->hash_table)
1580                 rte_hash_free(tunnel_rule->hash_table);
1581
1582         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1583                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1584                 rte_free(p_tunnel);
1585         }
1586 }
1587
1588 static void
1589 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1590 {
1591         struct i40e_fdir_filter *p_fdir;
1592         struct i40e_fdir_info *fdir_info;
1593
1594         fdir_info = &pf->fdir;
1595         /* Remove all flow director rules and hash */
1596         if (fdir_info->hash_map)
1597                 rte_free(fdir_info->hash_map);
1598         if (fdir_info->hash_table)
1599                 rte_hash_free(fdir_info->hash_table);
1600
1601         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1602                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1603                 rte_free(p_fdir);
1604         }
1605 }
1606
1607 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1608 {
1609         /*
1610          * Disable by default flexible payload
1611          * for corresponding L2/L3/L4 layers.
1612          */
1613         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1614         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1615         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1616 }
1617
1618 static int
1619 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1620 {
1621         struct i40e_pf *pf;
1622         struct rte_pci_device *pci_dev;
1623         struct rte_intr_handle *intr_handle;
1624         struct i40e_hw *hw;
1625         struct i40e_filter_control_settings settings;
1626         struct rte_flow *p_flow;
1627         int ret;
1628         uint8_t aq_fail = 0;
1629         int retries = 0;
1630
1631         PMD_INIT_FUNC_TRACE();
1632
1633         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1634                 return 0;
1635
1636         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1637         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1638         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1639         intr_handle = &pci_dev->intr_handle;
1640
1641         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1642         if (ret)
1643                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1644
1645         if (hw->adapter_stopped == 0)
1646                 i40e_dev_close(dev);
1647
1648         dev->dev_ops = NULL;
1649         dev->rx_pkt_burst = NULL;
1650         dev->tx_pkt_burst = NULL;
1651
1652         /* Clear PXE mode */
1653         i40e_clear_pxe_mode(hw);
1654
1655         /* Unconfigure filter control */
1656         memset(&settings, 0, sizeof(settings));
1657         ret = i40e_set_filter_control(hw, &settings);
1658         if (ret)
1659                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1660                                         ret);
1661
1662         /* Disable flow control */
1663         hw->fc.requested_mode = I40E_FC_NONE;
1664         i40e_set_fc(hw, &aq_fail, TRUE);
1665
1666         /* uninitialize pf host driver */
1667         i40e_pf_host_uninit(dev);
1668
1669         rte_free(dev->data->mac_addrs);
1670         dev->data->mac_addrs = NULL;
1671
1672         /* disable uio intr before callback unregister */
1673         rte_intr_disable(intr_handle);
1674
1675         /* unregister callback func to eal lib */
1676         do {
1677                 ret = rte_intr_callback_unregister(intr_handle,
1678                                 i40e_dev_interrupt_handler, dev);
1679                 if (ret >= 0) {
1680                         break;
1681                 } else if (ret != -EAGAIN) {
1682                         PMD_INIT_LOG(ERR,
1683                                  "intr callback unregister failed: %d",
1684                                  ret);
1685                         return ret;
1686                 }
1687                 i40e_msec_delay(500);
1688         } while (retries++ < 5);
1689
1690         i40e_rm_ethtype_filter_list(pf);
1691         i40e_rm_tunnel_filter_list(pf);
1692         i40e_rm_fdir_filter_list(pf);
1693
1694         /* Remove all flows */
1695         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1696                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1697                 rte_free(p_flow);
1698         }
1699
1700         /* Remove all Traffic Manager configuration */
1701         i40e_tm_conf_uninit(dev);
1702
1703         return 0;
1704 }
1705
1706 static int
1707 i40e_dev_configure(struct rte_eth_dev *dev)
1708 {
1709         struct i40e_adapter *ad =
1710                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1711         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1712         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1713         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1714         int i, ret;
1715
1716         ret = i40e_dev_sync_phy_type(hw);
1717         if (ret)
1718                 return ret;
1719
1720         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1721          * bulk allocation or vector Rx preconditions we will reset it.
1722          */
1723         ad->rx_bulk_alloc_allowed = true;
1724         ad->rx_vec_allowed = true;
1725         ad->tx_simple_allowed = true;
1726         ad->tx_vec_allowed = true;
1727
1728         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1729                 ret = i40e_fdir_setup(pf);
1730                 if (ret != I40E_SUCCESS) {
1731                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1732                         return -ENOTSUP;
1733                 }
1734                 ret = i40e_fdir_configure(dev);
1735                 if (ret < 0) {
1736                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1737                         goto err;
1738                 }
1739         } else
1740                 i40e_fdir_teardown(pf);
1741
1742         ret = i40e_dev_init_vlan(dev);
1743         if (ret < 0)
1744                 goto err;
1745
1746         /* VMDQ setup.
1747          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1748          *  RSS setting have different requirements.
1749          *  General PMD driver call sequence are NIC init, configure,
1750          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1751          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1752          *  applicable. So, VMDQ setting has to be done before
1753          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1754          *  For RSS setting, it will try to calculate actual configured RX queue
1755          *  number, which will be available after rx_queue_setup(). dev_start()
1756          *  function is good to place RSS setup.
1757          */
1758         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1759                 ret = i40e_vmdq_setup(dev);
1760                 if (ret)
1761                         goto err;
1762         }
1763
1764         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1765                 ret = i40e_dcb_setup(dev);
1766                 if (ret) {
1767                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1768                         goto err_dcb;
1769                 }
1770         }
1771
1772         TAILQ_INIT(&pf->flow_list);
1773
1774         return 0;
1775
1776 err_dcb:
1777         /* need to release vmdq resource if exists */
1778         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1779                 i40e_vsi_release(pf->vmdq[i].vsi);
1780                 pf->vmdq[i].vsi = NULL;
1781         }
1782         rte_free(pf->vmdq);
1783         pf->vmdq = NULL;
1784 err:
1785         /* need to release fdir resource if exists */
1786         i40e_fdir_teardown(pf);
1787         return ret;
1788 }
1789
1790 void
1791 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1792 {
1793         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1794         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1795         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1796         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1797         uint16_t msix_vect = vsi->msix_intr;
1798         uint16_t i;
1799
1800         for (i = 0; i < vsi->nb_qps; i++) {
1801                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1802                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1803                 rte_wmb();
1804         }
1805
1806         if (vsi->type != I40E_VSI_SRIOV) {
1807                 if (!rte_intr_allow_others(intr_handle)) {
1808                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1809                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1810                         I40E_WRITE_REG(hw,
1811                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1812                                        0);
1813                 } else {
1814                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1815                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1816                         I40E_WRITE_REG(hw,
1817                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1818                                                        msix_vect - 1), 0);
1819                 }
1820         } else {
1821                 uint32_t reg;
1822                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1823                         vsi->user_param + (msix_vect - 1);
1824
1825                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1826                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1827         }
1828         I40E_WRITE_FLUSH(hw);
1829 }
1830
1831 static void
1832 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1833                        int base_queue, int nb_queue,
1834                        uint16_t itr_idx)
1835 {
1836         int i;
1837         uint32_t val;
1838         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1839         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1840
1841         /* Bind all RX queues to allocated MSIX interrupt */
1842         for (i = 0; i < nb_queue; i++) {
1843                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1844                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1845                         ((base_queue + i + 1) <<
1846                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1847                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1848                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1849
1850                 if (i == nb_queue - 1)
1851                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1852                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1853         }
1854
1855         /* Write first RX queue to Link list register as the head element */
1856         if (vsi->type != I40E_VSI_SRIOV) {
1857                 uint16_t interval =
1858                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1859
1860                 if (msix_vect == I40E_MISC_VEC_ID) {
1861                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1862                                        (base_queue <<
1863                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1864                                        (0x0 <<
1865                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1866                         I40E_WRITE_REG(hw,
1867                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1868                                        interval);
1869                 } else {
1870                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1871                                        (base_queue <<
1872                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1873                                        (0x0 <<
1874                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1875                         I40E_WRITE_REG(hw,
1876                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1877                                                        msix_vect - 1),
1878                                        interval);
1879                 }
1880         } else {
1881                 uint32_t reg;
1882
1883                 if (msix_vect == I40E_MISC_VEC_ID) {
1884                         I40E_WRITE_REG(hw,
1885                                        I40E_VPINT_LNKLST0(vsi->user_param),
1886                                        (base_queue <<
1887                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1888                                        (0x0 <<
1889                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1890                 } else {
1891                         /* num_msix_vectors_vf needs to minus irq0 */
1892                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1893                                 vsi->user_param + (msix_vect - 1);
1894
1895                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1896                                        (base_queue <<
1897                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1898                                        (0x0 <<
1899                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1900                 }
1901         }
1902
1903         I40E_WRITE_FLUSH(hw);
1904 }
1905
1906 void
1907 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1908 {
1909         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1910         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1911         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1912         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1913         uint16_t msix_vect = vsi->msix_intr;
1914         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1915         uint16_t queue_idx = 0;
1916         int record = 0;
1917         int i;
1918
1919         for (i = 0; i < vsi->nb_qps; i++) {
1920                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1921                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1922         }
1923
1924         /* VF bind interrupt */
1925         if (vsi->type == I40E_VSI_SRIOV) {
1926                 __vsi_queues_bind_intr(vsi, msix_vect,
1927                                        vsi->base_queue, vsi->nb_qps,
1928                                        itr_idx);
1929                 return;
1930         }
1931
1932         /* PF & VMDq bind interrupt */
1933         if (rte_intr_dp_is_en(intr_handle)) {
1934                 if (vsi->type == I40E_VSI_MAIN) {
1935                         queue_idx = 0;
1936                         record = 1;
1937                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1938                         struct i40e_vsi *main_vsi =
1939                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1940                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1941                         record = 1;
1942                 }
1943         }
1944
1945         for (i = 0; i < vsi->nb_used_qps; i++) {
1946                 if (nb_msix <= 1) {
1947                         if (!rte_intr_allow_others(intr_handle))
1948                                 /* allow to share MISC_VEC_ID */
1949                                 msix_vect = I40E_MISC_VEC_ID;
1950
1951                         /* no enough msix_vect, map all to one */
1952                         __vsi_queues_bind_intr(vsi, msix_vect,
1953                                                vsi->base_queue + i,
1954                                                vsi->nb_used_qps - i,
1955                                                itr_idx);
1956                         for (; !!record && i < vsi->nb_used_qps; i++)
1957                                 intr_handle->intr_vec[queue_idx + i] =
1958                                         msix_vect;
1959                         break;
1960                 }
1961                 /* 1:1 queue/msix_vect mapping */
1962                 __vsi_queues_bind_intr(vsi, msix_vect,
1963                                        vsi->base_queue + i, 1,
1964                                        itr_idx);
1965                 if (!!record)
1966                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1967
1968                 msix_vect++;
1969                 nb_msix--;
1970         }
1971 }
1972
1973 static void
1974 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1975 {
1976         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1977         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1978         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1979         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1980         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1981         uint16_t msix_intr, i;
1982
1983         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1984                 for (i = 0; i < vsi->nb_msix; i++) {
1985                         msix_intr = vsi->msix_intr + i;
1986                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1987                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1988                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1989                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1990                 }
1991         else
1992                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1993                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1994                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1995                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1996
1997         I40E_WRITE_FLUSH(hw);
1998 }
1999
2000 static void
2001 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2002 {
2003         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2004         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2005         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2006         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2007         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2008         uint16_t msix_intr, i;
2009
2010         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2011                 for (i = 0; i < vsi->nb_msix; i++) {
2012                         msix_intr = vsi->msix_intr + i;
2013                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2014                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2015                 }
2016         else
2017                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2018                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2019
2020         I40E_WRITE_FLUSH(hw);
2021 }
2022
2023 static inline uint8_t
2024 i40e_parse_link_speeds(uint16_t link_speeds)
2025 {
2026         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2027
2028         if (link_speeds & ETH_LINK_SPEED_40G)
2029                 link_speed |= I40E_LINK_SPEED_40GB;
2030         if (link_speeds & ETH_LINK_SPEED_25G)
2031                 link_speed |= I40E_LINK_SPEED_25GB;
2032         if (link_speeds & ETH_LINK_SPEED_20G)
2033                 link_speed |= I40E_LINK_SPEED_20GB;
2034         if (link_speeds & ETH_LINK_SPEED_10G)
2035                 link_speed |= I40E_LINK_SPEED_10GB;
2036         if (link_speeds & ETH_LINK_SPEED_1G)
2037                 link_speed |= I40E_LINK_SPEED_1GB;
2038         if (link_speeds & ETH_LINK_SPEED_100M)
2039                 link_speed |= I40E_LINK_SPEED_100MB;
2040
2041         return link_speed;
2042 }
2043
2044 static int
2045 i40e_phy_conf_link(struct i40e_hw *hw,
2046                    uint8_t abilities,
2047                    uint8_t force_speed,
2048                    bool is_up)
2049 {
2050         enum i40e_status_code status;
2051         struct i40e_aq_get_phy_abilities_resp phy_ab;
2052         struct i40e_aq_set_phy_config phy_conf;
2053         enum i40e_aq_phy_type cnt;
2054         uint8_t avail_speed;
2055         uint32_t phy_type_mask = 0;
2056
2057         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2058                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2059                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2060                         I40E_AQ_PHY_FLAG_LOW_POWER;
2061         int ret = -ENOTSUP;
2062
2063         /* To get phy capabilities of available speeds. */
2064         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2065                                               NULL);
2066         if (status) {
2067                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2068                                 status);
2069                 return ret;
2070         }
2071         avail_speed = phy_ab.link_speed;
2072
2073         /* To get the current phy config. */
2074         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2075                                               NULL);
2076         if (status) {
2077                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2078                                 status);
2079                 return ret;
2080         }
2081
2082         /* If link needs to go up and it is in autoneg mode the speed is OK,
2083          * no need to set up again.
2084          */
2085         if (is_up && phy_ab.phy_type != 0 &&
2086                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2087                      phy_ab.link_speed != 0)
2088                 return I40E_SUCCESS;
2089
2090         memset(&phy_conf, 0, sizeof(phy_conf));
2091
2092         /* bits 0-2 use the values from get_phy_abilities_resp */
2093         abilities &= ~mask;
2094         abilities |= phy_ab.abilities & mask;
2095
2096         phy_conf.abilities = abilities;
2097
2098         /* If link needs to go up, but the force speed is not supported,
2099          * Warn users and config the default available speeds.
2100          */
2101         if (is_up && !(force_speed & avail_speed)) {
2102                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2103                 phy_conf.link_speed = avail_speed;
2104         } else {
2105                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2106         }
2107
2108         /* PHY type mask needs to include each type except PHY type extension */
2109         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2110                 phy_type_mask |= 1 << cnt;
2111
2112         /* use get_phy_abilities_resp value for the rest */
2113         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2114         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2115                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2116                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2117         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2118         phy_conf.eee_capability = phy_ab.eee_capability;
2119         phy_conf.eeer = phy_ab.eeer_val;
2120         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2121
2122         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2123                     phy_ab.abilities, phy_ab.link_speed);
2124         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2125                     phy_conf.abilities, phy_conf.link_speed);
2126
2127         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2128         if (status)
2129                 return ret;
2130
2131         return I40E_SUCCESS;
2132 }
2133
2134 static int
2135 i40e_apply_link_speed(struct rte_eth_dev *dev)
2136 {
2137         uint8_t speed;
2138         uint8_t abilities = 0;
2139         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2140         struct rte_eth_conf *conf = &dev->data->dev_conf;
2141
2142         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2143                 conf->link_speeds = ETH_LINK_SPEED_40G |
2144                                     ETH_LINK_SPEED_25G |
2145                                     ETH_LINK_SPEED_20G |
2146                                     ETH_LINK_SPEED_10G |
2147                                     ETH_LINK_SPEED_1G |
2148                                     ETH_LINK_SPEED_100M;
2149         }
2150         speed = i40e_parse_link_speeds(conf->link_speeds);
2151         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2152                      I40E_AQ_PHY_AN_ENABLED |
2153                      I40E_AQ_PHY_LINK_ENABLED;
2154
2155         return i40e_phy_conf_link(hw, abilities, speed, true);
2156 }
2157
2158 static int
2159 i40e_dev_start(struct rte_eth_dev *dev)
2160 {
2161         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2162         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163         struct i40e_vsi *main_vsi = pf->main_vsi;
2164         int ret, i;
2165         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2166         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2167         uint32_t intr_vector = 0;
2168         struct i40e_vsi *vsi;
2169
2170         hw->adapter_stopped = 0;
2171
2172         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2173                 PMD_INIT_LOG(ERR,
2174                 "Invalid link_speeds for port %u, autonegotiation disabled",
2175                               dev->data->port_id);
2176                 return -EINVAL;
2177         }
2178
2179         rte_intr_disable(intr_handle);
2180
2181         if ((rte_intr_cap_multiple(intr_handle) ||
2182              !RTE_ETH_DEV_SRIOV(dev).active) &&
2183             dev->data->dev_conf.intr_conf.rxq != 0) {
2184                 intr_vector = dev->data->nb_rx_queues;
2185                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2186                 if (ret)
2187                         return ret;
2188         }
2189
2190         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2191                 intr_handle->intr_vec =
2192                         rte_zmalloc("intr_vec",
2193                                     dev->data->nb_rx_queues * sizeof(int),
2194                                     0);
2195                 if (!intr_handle->intr_vec) {
2196                         PMD_INIT_LOG(ERR,
2197                                 "Failed to allocate %d rx_queues intr_vec",
2198                                 dev->data->nb_rx_queues);
2199                         return -ENOMEM;
2200                 }
2201         }
2202
2203         /* Initialize VSI */
2204         ret = i40e_dev_rxtx_init(pf);
2205         if (ret != I40E_SUCCESS) {
2206                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2207                 goto err_up;
2208         }
2209
2210         /* Map queues with MSIX interrupt */
2211         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2212                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2213         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2214         i40e_vsi_enable_queues_intr(main_vsi);
2215
2216         /* Map VMDQ VSI queues with MSIX interrupt */
2217         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2218                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2219                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2220                                           I40E_ITR_INDEX_DEFAULT);
2221                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2222         }
2223
2224         /* enable FDIR MSIX interrupt */
2225         if (pf->fdir.fdir_vsi) {
2226                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2227                                           I40E_ITR_INDEX_NONE);
2228                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2229         }
2230
2231         /* Enable all queues which have been configured */
2232         ret = i40e_dev_switch_queues(pf, TRUE);
2233         if (ret != I40E_SUCCESS) {
2234                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2235                 goto err_up;
2236         }
2237
2238         /* Enable receiving broadcast packets */
2239         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2240         if (ret != I40E_SUCCESS)
2241                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2242
2243         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2244                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2245                                                 true, NULL);
2246                 if (ret != I40E_SUCCESS)
2247                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2248         }
2249
2250         /* Enable the VLAN promiscuous mode. */
2251         if (pf->vfs) {
2252                 for (i = 0; i < pf->vf_num; i++) {
2253                         vsi = pf->vfs[i].vsi;
2254                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2255                                                      true, NULL);
2256                 }
2257         }
2258
2259         /* Enable mac loopback mode */
2260         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2261             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2262                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2263                 if (ret != I40E_SUCCESS) {
2264                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2265                         goto err_up;
2266                 }
2267         }
2268
2269         /* Apply link configure */
2270         ret = i40e_apply_link_speed(dev);
2271         if (I40E_SUCCESS != ret) {
2272                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2273                 goto err_up;
2274         }
2275
2276         if (!rte_intr_allow_others(intr_handle)) {
2277                 rte_intr_callback_unregister(intr_handle,
2278                                              i40e_dev_interrupt_handler,
2279                                              (void *)dev);
2280                 /* configure and enable device interrupt */
2281                 i40e_pf_config_irq0(hw, FALSE);
2282                 i40e_pf_enable_irq0(hw);
2283
2284                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2285                         PMD_INIT_LOG(INFO,
2286                                 "lsc won't enable because of no intr multiplex");
2287         } else {
2288                 ret = i40e_aq_set_phy_int_mask(hw,
2289                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2290                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2291                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2292                 if (ret != I40E_SUCCESS)
2293                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2294
2295                 /* Call get_link_info aq commond to enable/disable LSE */
2296                 i40e_dev_link_update(dev, 0);
2297         }
2298
2299         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2300                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2301                                   i40e_dev_alarm_handler, dev);
2302         } else {
2303                 /* enable uio intr after callback register */
2304                 rte_intr_enable(intr_handle);
2305         }
2306
2307         i40e_filter_restore(pf);
2308
2309         if (pf->tm_conf.root && !pf->tm_conf.committed)
2310                 PMD_DRV_LOG(WARNING,
2311                             "please call hierarchy_commit() "
2312                             "before starting the port");
2313
2314         return I40E_SUCCESS;
2315
2316 err_up:
2317         i40e_dev_switch_queues(pf, FALSE);
2318         i40e_dev_clear_queues(dev);
2319
2320         return ret;
2321 }
2322
2323 static void
2324 i40e_dev_stop(struct rte_eth_dev *dev)
2325 {
2326         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2327         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2328         struct i40e_vsi *main_vsi = pf->main_vsi;
2329         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2330         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2331         int i;
2332
2333         if (hw->adapter_stopped == 1)
2334                 return;
2335
2336         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2337                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2338                 rte_intr_enable(intr_handle);
2339         }
2340
2341         /* Disable all queues */
2342         i40e_dev_switch_queues(pf, FALSE);
2343
2344         /* un-map queues with interrupt registers */
2345         i40e_vsi_disable_queues_intr(main_vsi);
2346         i40e_vsi_queues_unbind_intr(main_vsi);
2347
2348         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2349                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2350                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2351         }
2352
2353         if (pf->fdir.fdir_vsi) {
2354                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2355                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2356         }
2357         /* Clear all queues and release memory */
2358         i40e_dev_clear_queues(dev);
2359
2360         /* Set link down */
2361         i40e_dev_set_link_down(dev);
2362
2363         if (!rte_intr_allow_others(intr_handle))
2364                 /* resume to the default handler */
2365                 rte_intr_callback_register(intr_handle,
2366                                            i40e_dev_interrupt_handler,
2367                                            (void *)dev);
2368
2369         /* Clean datapath event and queue/vec mapping */
2370         rte_intr_efd_disable(intr_handle);
2371         if (intr_handle->intr_vec) {
2372                 rte_free(intr_handle->intr_vec);
2373                 intr_handle->intr_vec = NULL;
2374         }
2375
2376         /* reset hierarchy commit */
2377         pf->tm_conf.committed = false;
2378
2379         hw->adapter_stopped = 1;
2380 }
2381
2382 static void
2383 i40e_dev_close(struct rte_eth_dev *dev)
2384 {
2385         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2386         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2387         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2388         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2389         struct i40e_mirror_rule *p_mirror;
2390         uint32_t reg;
2391         int i;
2392         int ret;
2393
2394         PMD_INIT_FUNC_TRACE();
2395
2396         i40e_dev_stop(dev);
2397
2398         /* Remove all mirror rules */
2399         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2400                 ret = i40e_aq_del_mirror_rule(hw,
2401                                               pf->main_vsi->veb->seid,
2402                                               p_mirror->rule_type,
2403                                               p_mirror->entries,
2404                                               p_mirror->num_entries,
2405                                               p_mirror->id);
2406                 if (ret < 0)
2407                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2408                                     "status = %d, aq_err = %d.", ret,
2409                                     hw->aq.asq_last_status);
2410
2411                 /* remove mirror software resource anyway */
2412                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2413                 rte_free(p_mirror);
2414                 pf->nb_mirror_rule--;
2415         }
2416
2417         i40e_dev_free_queues(dev);
2418
2419         /* Disable interrupt */
2420         i40e_pf_disable_irq0(hw);
2421         rte_intr_disable(intr_handle);
2422
2423         i40e_fdir_teardown(pf);
2424
2425         /* shutdown and destroy the HMC */
2426         i40e_shutdown_lan_hmc(hw);
2427
2428         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2429                 i40e_vsi_release(pf->vmdq[i].vsi);
2430                 pf->vmdq[i].vsi = NULL;
2431         }
2432         rte_free(pf->vmdq);
2433         pf->vmdq = NULL;
2434
2435         /* release all the existing VSIs and VEBs */
2436         i40e_vsi_release(pf->main_vsi);
2437
2438         /* shutdown the adminq */
2439         i40e_aq_queue_shutdown(hw, true);
2440         i40e_shutdown_adminq(hw);
2441
2442         i40e_res_pool_destroy(&pf->qp_pool);
2443         i40e_res_pool_destroy(&pf->msix_pool);
2444
2445         /* Disable flexible payload in global configuration */
2446         if (!pf->support_multi_driver)
2447                 i40e_flex_payload_reg_set_default(hw);
2448
2449         /* force a PF reset to clean anything leftover */
2450         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2451         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2452                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2453         I40E_WRITE_FLUSH(hw);
2454 }
2455
2456 /*
2457  * Reset PF device only to re-initialize resources in PMD layer
2458  */
2459 static int
2460 i40e_dev_reset(struct rte_eth_dev *dev)
2461 {
2462         int ret;
2463
2464         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2465          * its VF to make them align with it. The detailed notification
2466          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2467          * To avoid unexpected behavior in VF, currently reset of PF with
2468          * SR-IOV activation is not supported. It might be supported later.
2469          */
2470         if (dev->data->sriov.active)
2471                 return -ENOTSUP;
2472
2473         ret = eth_i40e_dev_uninit(dev);
2474         if (ret)
2475                 return ret;
2476
2477         ret = eth_i40e_dev_init(dev, NULL);
2478
2479         return ret;
2480 }
2481
2482 static void
2483 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2484 {
2485         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2486         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2487         struct i40e_vsi *vsi = pf->main_vsi;
2488         int status;
2489
2490         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2491                                                      true, NULL, true);
2492         if (status != I40E_SUCCESS)
2493                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2494
2495         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2496                                                         TRUE, NULL);
2497         if (status != I40E_SUCCESS)
2498                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2499
2500 }
2501
2502 static void
2503 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2504 {
2505         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2506         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2507         struct i40e_vsi *vsi = pf->main_vsi;
2508         int status;
2509
2510         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2511                                                      false, NULL, true);
2512         if (status != I40E_SUCCESS)
2513                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2514
2515         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2516                                                         false, NULL);
2517         if (status != I40E_SUCCESS)
2518                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2519 }
2520
2521 static void
2522 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2523 {
2524         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2525         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2526         struct i40e_vsi *vsi = pf->main_vsi;
2527         int ret;
2528
2529         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2530         if (ret != I40E_SUCCESS)
2531                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2532 }
2533
2534 static void
2535 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2536 {
2537         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2538         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539         struct i40e_vsi *vsi = pf->main_vsi;
2540         int ret;
2541
2542         if (dev->data->promiscuous == 1)
2543                 return; /* must remain in all_multicast mode */
2544
2545         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2546                                 vsi->seid, FALSE, NULL);
2547         if (ret != I40E_SUCCESS)
2548                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2549 }
2550
2551 /*
2552  * Set device link up.
2553  */
2554 static int
2555 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2556 {
2557         /* re-apply link speed setting */
2558         return i40e_apply_link_speed(dev);
2559 }
2560
2561 /*
2562  * Set device link down.
2563  */
2564 static int
2565 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2566 {
2567         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2568         uint8_t abilities = 0;
2569         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570
2571         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2572         return i40e_phy_conf_link(hw, abilities, speed, false);
2573 }
2574
2575 static __rte_always_inline void
2576 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2577 {
2578 /* Link status registers and values*/
2579 #define I40E_PRTMAC_LINKSTA             0x001E2420
2580 #define I40E_REG_LINK_UP                0x40000080
2581 #define I40E_PRTMAC_MACC                0x001E24E0
2582 #define I40E_REG_MACC_25GB              0x00020000
2583 #define I40E_REG_SPEED_MASK             0x38000000
2584 #define I40E_REG_SPEED_100MB            0x00000000
2585 #define I40E_REG_SPEED_1GB              0x08000000
2586 #define I40E_REG_SPEED_10GB             0x10000000
2587 #define I40E_REG_SPEED_20GB             0x20000000
2588 #define I40E_REG_SPEED_25_40GB          0x18000000
2589         uint32_t link_speed;
2590         uint32_t reg_val;
2591
2592         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2593         link_speed = reg_val & I40E_REG_SPEED_MASK;
2594         reg_val &= I40E_REG_LINK_UP;
2595         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2596
2597         if (unlikely(link->link_status == 0))
2598                 return;
2599
2600         /* Parse the link status */
2601         switch (link_speed) {
2602         case I40E_REG_SPEED_100MB:
2603                 link->link_speed = ETH_SPEED_NUM_100M;
2604                 break;
2605         case I40E_REG_SPEED_1GB:
2606                 link->link_speed = ETH_SPEED_NUM_1G;
2607                 break;
2608         case I40E_REG_SPEED_10GB:
2609                 link->link_speed = ETH_SPEED_NUM_10G;
2610                 break;
2611         case I40E_REG_SPEED_20GB:
2612                 link->link_speed = ETH_SPEED_NUM_20G;
2613                 break;
2614         case I40E_REG_SPEED_25_40GB:
2615                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2616
2617                 if (reg_val & I40E_REG_MACC_25GB)
2618                         link->link_speed = ETH_SPEED_NUM_25G;
2619                 else
2620                         link->link_speed = ETH_SPEED_NUM_40G;
2621
2622                 break;
2623         default:
2624                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2625                 break;
2626         }
2627 }
2628
2629 static __rte_always_inline void
2630 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2631         bool enable_lse, int wait_to_complete)
2632 {
2633 #define CHECK_INTERVAL             100  /* 100ms */
2634 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2635         uint32_t rep_cnt = MAX_REPEAT_TIME;
2636         struct i40e_link_status link_status;
2637         int status;
2638
2639         memset(&link_status, 0, sizeof(link_status));
2640
2641         do {
2642                 memset(&link_status, 0, sizeof(link_status));
2643
2644                 /* Get link status information from hardware */
2645                 status = i40e_aq_get_link_info(hw, enable_lse,
2646                                                 &link_status, NULL);
2647                 if (unlikely(status != I40E_SUCCESS)) {
2648                         link->link_speed = ETH_SPEED_NUM_100M;
2649                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2650                         PMD_DRV_LOG(ERR, "Failed to get link info");
2651                         return;
2652                 }
2653
2654                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2655                 if (!wait_to_complete || link->link_status)
2656                         break;
2657
2658                 rte_delay_ms(CHECK_INTERVAL);
2659         } while (--rep_cnt);
2660
2661         /* Parse the link status */
2662         switch (link_status.link_speed) {
2663         case I40E_LINK_SPEED_100MB:
2664                 link->link_speed = ETH_SPEED_NUM_100M;
2665                 break;
2666         case I40E_LINK_SPEED_1GB:
2667                 link->link_speed = ETH_SPEED_NUM_1G;
2668                 break;
2669         case I40E_LINK_SPEED_10GB:
2670                 link->link_speed = ETH_SPEED_NUM_10G;
2671                 break;
2672         case I40E_LINK_SPEED_20GB:
2673                 link->link_speed = ETH_SPEED_NUM_20G;
2674                 break;
2675         case I40E_LINK_SPEED_25GB:
2676                 link->link_speed = ETH_SPEED_NUM_25G;
2677                 break;
2678         case I40E_LINK_SPEED_40GB:
2679                 link->link_speed = ETH_SPEED_NUM_40G;
2680                 break;
2681         default:
2682                 link->link_speed = ETH_SPEED_NUM_100M;
2683                 break;
2684         }
2685 }
2686
2687 int
2688 i40e_dev_link_update(struct rte_eth_dev *dev,
2689                      int wait_to_complete)
2690 {
2691         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2692         struct rte_eth_link link;
2693         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2694         int ret;
2695
2696         memset(&link, 0, sizeof(link));
2697
2698         /* i40e uses full duplex only */
2699         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2700         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2701                         ETH_LINK_SPEED_FIXED);
2702
2703         if (!wait_to_complete && !enable_lse)
2704                 update_link_reg(hw, &link);
2705         else
2706                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2707
2708         ret = rte_eth_linkstatus_set(dev, &link);
2709         i40e_notify_all_vfs_link_status(dev);
2710
2711         return ret;
2712 }
2713
2714 /* Get all the statistics of a VSI */
2715 void
2716 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2717 {
2718         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2719         struct i40e_eth_stats *nes = &vsi->eth_stats;
2720         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2721         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2722
2723         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2724                             vsi->offset_loaded, &oes->rx_bytes,
2725                             &nes->rx_bytes);
2726         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2727                             vsi->offset_loaded, &oes->rx_unicast,
2728                             &nes->rx_unicast);
2729         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2730                             vsi->offset_loaded, &oes->rx_multicast,
2731                             &nes->rx_multicast);
2732         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2733                             vsi->offset_loaded, &oes->rx_broadcast,
2734                             &nes->rx_broadcast);
2735         /* exclude CRC bytes */
2736         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2737                 nes->rx_broadcast) * ETHER_CRC_LEN;
2738
2739         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2740                             &oes->rx_discards, &nes->rx_discards);
2741         /* GLV_REPC not supported */
2742         /* GLV_RMPC not supported */
2743         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2744                             &oes->rx_unknown_protocol,
2745                             &nes->rx_unknown_protocol);
2746         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2747                             vsi->offset_loaded, &oes->tx_bytes,
2748                             &nes->tx_bytes);
2749         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2750                             vsi->offset_loaded, &oes->tx_unicast,
2751                             &nes->tx_unicast);
2752         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2753                             vsi->offset_loaded, &oes->tx_multicast,
2754                             &nes->tx_multicast);
2755         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2756                             vsi->offset_loaded,  &oes->tx_broadcast,
2757                             &nes->tx_broadcast);
2758         /* GLV_TDPC not supported */
2759         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2760                             &oes->tx_errors, &nes->tx_errors);
2761         vsi->offset_loaded = true;
2762
2763         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2764                     vsi->vsi_id);
2765         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2766         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2767         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2768         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2769         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2770         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2771                     nes->rx_unknown_protocol);
2772         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2773         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2774         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2775         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2776         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2777         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2778         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2779                     vsi->vsi_id);
2780 }
2781
2782 static void
2783 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2784 {
2785         unsigned int i;
2786         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2787         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2788
2789         /* Get rx/tx bytes of internal transfer packets */
2790         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2791                         I40E_GLV_GORCL(hw->port),
2792                         pf->offset_loaded,
2793                         &pf->internal_stats_offset.rx_bytes,
2794                         &pf->internal_stats.rx_bytes);
2795
2796         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2797                         I40E_GLV_GOTCL(hw->port),
2798                         pf->offset_loaded,
2799                         &pf->internal_stats_offset.tx_bytes,
2800                         &pf->internal_stats.tx_bytes);
2801         /* Get total internal rx packet count */
2802         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2803                             I40E_GLV_UPRCL(hw->port),
2804                             pf->offset_loaded,
2805                             &pf->internal_stats_offset.rx_unicast,
2806                             &pf->internal_stats.rx_unicast);
2807         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2808                             I40E_GLV_MPRCL(hw->port),
2809                             pf->offset_loaded,
2810                             &pf->internal_stats_offset.rx_multicast,
2811                             &pf->internal_stats.rx_multicast);
2812         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2813                             I40E_GLV_BPRCL(hw->port),
2814                             pf->offset_loaded,
2815                             &pf->internal_stats_offset.rx_broadcast,
2816                             &pf->internal_stats.rx_broadcast);
2817         /* Get total internal tx packet count */
2818         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2819                             I40E_GLV_UPTCL(hw->port),
2820                             pf->offset_loaded,
2821                             &pf->internal_stats_offset.tx_unicast,
2822                             &pf->internal_stats.tx_unicast);
2823         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2824                             I40E_GLV_MPTCL(hw->port),
2825                             pf->offset_loaded,
2826                             &pf->internal_stats_offset.tx_multicast,
2827                             &pf->internal_stats.tx_multicast);
2828         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2829                             I40E_GLV_BPTCL(hw->port),
2830                             pf->offset_loaded,
2831                             &pf->internal_stats_offset.tx_broadcast,
2832                             &pf->internal_stats.tx_broadcast);
2833
2834         /* exclude CRC size */
2835         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2836                 pf->internal_stats.rx_multicast +
2837                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2838
2839         /* Get statistics of struct i40e_eth_stats */
2840         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2841                             I40E_GLPRT_GORCL(hw->port),
2842                             pf->offset_loaded, &os->eth.rx_bytes,
2843                             &ns->eth.rx_bytes);
2844         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2845                             I40E_GLPRT_UPRCL(hw->port),
2846                             pf->offset_loaded, &os->eth.rx_unicast,
2847                             &ns->eth.rx_unicast);
2848         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2849                             I40E_GLPRT_MPRCL(hw->port),
2850                             pf->offset_loaded, &os->eth.rx_multicast,
2851                             &ns->eth.rx_multicast);
2852         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2853                             I40E_GLPRT_BPRCL(hw->port),
2854                             pf->offset_loaded, &os->eth.rx_broadcast,
2855                             &ns->eth.rx_broadcast);
2856         /* Workaround: CRC size should not be included in byte statistics,
2857          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2858          */
2859         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2860                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2861
2862         /* exclude internal rx bytes
2863          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2864          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2865          * value.
2866          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2867          */
2868         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2869                 ns->eth.rx_bytes = 0;
2870         else
2871                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2872
2873         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2874                 ns->eth.rx_unicast = 0;
2875         else
2876                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2877
2878         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2879                 ns->eth.rx_multicast = 0;
2880         else
2881                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2882
2883         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2884                 ns->eth.rx_broadcast = 0;
2885         else
2886                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2887
2888         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2889                             pf->offset_loaded, &os->eth.rx_discards,
2890                             &ns->eth.rx_discards);
2891         /* GLPRT_REPC not supported */
2892         /* GLPRT_RMPC not supported */
2893         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2894                             pf->offset_loaded,
2895                             &os->eth.rx_unknown_protocol,
2896                             &ns->eth.rx_unknown_protocol);
2897         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2898                             I40E_GLPRT_GOTCL(hw->port),
2899                             pf->offset_loaded, &os->eth.tx_bytes,
2900                             &ns->eth.tx_bytes);
2901         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2902                             I40E_GLPRT_UPTCL(hw->port),
2903                             pf->offset_loaded, &os->eth.tx_unicast,
2904                             &ns->eth.tx_unicast);
2905         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2906                             I40E_GLPRT_MPTCL(hw->port),
2907                             pf->offset_loaded, &os->eth.tx_multicast,
2908                             &ns->eth.tx_multicast);
2909         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2910                             I40E_GLPRT_BPTCL(hw->port),
2911                             pf->offset_loaded, &os->eth.tx_broadcast,
2912                             &ns->eth.tx_broadcast);
2913         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2914                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2915
2916         /* exclude internal tx bytes
2917          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2918          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2919          * value.
2920          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2921          */
2922         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2923                 ns->eth.tx_bytes = 0;
2924         else
2925                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2926
2927         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2928                 ns->eth.tx_unicast = 0;
2929         else
2930                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2931
2932         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2933                 ns->eth.tx_multicast = 0;
2934         else
2935                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2936
2937         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2938                 ns->eth.tx_broadcast = 0;
2939         else
2940                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2941
2942         /* GLPRT_TEPC not supported */
2943
2944         /* additional port specific stats */
2945         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2946                             pf->offset_loaded, &os->tx_dropped_link_down,
2947                             &ns->tx_dropped_link_down);
2948         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2949                             pf->offset_loaded, &os->crc_errors,
2950                             &ns->crc_errors);
2951         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2952                             pf->offset_loaded, &os->illegal_bytes,
2953                             &ns->illegal_bytes);
2954         /* GLPRT_ERRBC not supported */
2955         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2956                             pf->offset_loaded, &os->mac_local_faults,
2957                             &ns->mac_local_faults);
2958         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2959                             pf->offset_loaded, &os->mac_remote_faults,
2960                             &ns->mac_remote_faults);
2961         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2962                             pf->offset_loaded, &os->rx_length_errors,
2963                             &ns->rx_length_errors);
2964         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2965                             pf->offset_loaded, &os->link_xon_rx,
2966                             &ns->link_xon_rx);
2967         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2968                             pf->offset_loaded, &os->link_xoff_rx,
2969                             &ns->link_xoff_rx);
2970         for (i = 0; i < 8; i++) {
2971                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2972                                     pf->offset_loaded,
2973                                     &os->priority_xon_rx[i],
2974                                     &ns->priority_xon_rx[i]);
2975                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2976                                     pf->offset_loaded,
2977                                     &os->priority_xoff_rx[i],
2978                                     &ns->priority_xoff_rx[i]);
2979         }
2980         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2981                             pf->offset_loaded, &os->link_xon_tx,
2982                             &ns->link_xon_tx);
2983         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2984                             pf->offset_loaded, &os->link_xoff_tx,
2985                             &ns->link_xoff_tx);
2986         for (i = 0; i < 8; i++) {
2987                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2988                                     pf->offset_loaded,
2989                                     &os->priority_xon_tx[i],
2990                                     &ns->priority_xon_tx[i]);
2991                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2992                                     pf->offset_loaded,
2993                                     &os->priority_xoff_tx[i],
2994                                     &ns->priority_xoff_tx[i]);
2995                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2996                                     pf->offset_loaded,
2997                                     &os->priority_xon_2_xoff[i],
2998                                     &ns->priority_xon_2_xoff[i]);
2999         }
3000         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3001                             I40E_GLPRT_PRC64L(hw->port),
3002                             pf->offset_loaded, &os->rx_size_64,
3003                             &ns->rx_size_64);
3004         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3005                             I40E_GLPRT_PRC127L(hw->port),
3006                             pf->offset_loaded, &os->rx_size_127,
3007                             &ns->rx_size_127);
3008         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3009                             I40E_GLPRT_PRC255L(hw->port),
3010                             pf->offset_loaded, &os->rx_size_255,
3011                             &ns->rx_size_255);
3012         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3013                             I40E_GLPRT_PRC511L(hw->port),
3014                             pf->offset_loaded, &os->rx_size_511,
3015                             &ns->rx_size_511);
3016         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3017                             I40E_GLPRT_PRC1023L(hw->port),
3018                             pf->offset_loaded, &os->rx_size_1023,
3019                             &ns->rx_size_1023);
3020         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3021                             I40E_GLPRT_PRC1522L(hw->port),
3022                             pf->offset_loaded, &os->rx_size_1522,
3023                             &ns->rx_size_1522);
3024         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3025                             I40E_GLPRT_PRC9522L(hw->port),
3026                             pf->offset_loaded, &os->rx_size_big,
3027                             &ns->rx_size_big);
3028         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3029                             pf->offset_loaded, &os->rx_undersize,
3030                             &ns->rx_undersize);
3031         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3032                             pf->offset_loaded, &os->rx_fragments,
3033                             &ns->rx_fragments);
3034         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3035                             pf->offset_loaded, &os->rx_oversize,
3036                             &ns->rx_oversize);
3037         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3038                             pf->offset_loaded, &os->rx_jabber,
3039                             &ns->rx_jabber);
3040         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3041                             I40E_GLPRT_PTC64L(hw->port),
3042                             pf->offset_loaded, &os->tx_size_64,
3043                             &ns->tx_size_64);
3044         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3045                             I40E_GLPRT_PTC127L(hw->port),
3046                             pf->offset_loaded, &os->tx_size_127,
3047                             &ns->tx_size_127);
3048         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3049                             I40E_GLPRT_PTC255L(hw->port),
3050                             pf->offset_loaded, &os->tx_size_255,
3051                             &ns->tx_size_255);
3052         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3053                             I40E_GLPRT_PTC511L(hw->port),
3054                             pf->offset_loaded, &os->tx_size_511,
3055                             &ns->tx_size_511);
3056         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3057                             I40E_GLPRT_PTC1023L(hw->port),
3058                             pf->offset_loaded, &os->tx_size_1023,
3059                             &ns->tx_size_1023);
3060         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3061                             I40E_GLPRT_PTC1522L(hw->port),
3062                             pf->offset_loaded, &os->tx_size_1522,
3063                             &ns->tx_size_1522);
3064         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3065                             I40E_GLPRT_PTC9522L(hw->port),
3066                             pf->offset_loaded, &os->tx_size_big,
3067                             &ns->tx_size_big);
3068         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3069                            pf->offset_loaded,
3070                            &os->fd_sb_match, &ns->fd_sb_match);
3071         /* GLPRT_MSPDC not supported */
3072         /* GLPRT_XEC not supported */
3073
3074         pf->offset_loaded = true;
3075
3076         if (pf->main_vsi)
3077                 i40e_update_vsi_stats(pf->main_vsi);
3078 }
3079
3080 /* Get all statistics of a port */
3081 static int
3082 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3083 {
3084         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3085         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3086         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3087         unsigned i;
3088
3089         /* call read registers - updates values, now write them to struct */
3090         i40e_read_stats_registers(pf, hw);
3091
3092         stats->ipackets = ns->eth.rx_unicast +
3093                         ns->eth.rx_multicast +
3094                         ns->eth.rx_broadcast -
3095                         ns->eth.rx_discards -
3096                         pf->main_vsi->eth_stats.rx_discards;
3097         stats->opackets = ns->eth.tx_unicast +
3098                         ns->eth.tx_multicast +
3099                         ns->eth.tx_broadcast;
3100         stats->ibytes   = ns->eth.rx_bytes;
3101         stats->obytes   = ns->eth.tx_bytes;
3102         stats->oerrors  = ns->eth.tx_errors +
3103                         pf->main_vsi->eth_stats.tx_errors;
3104
3105         /* Rx Errors */
3106         stats->imissed  = ns->eth.rx_discards +
3107                         pf->main_vsi->eth_stats.rx_discards;
3108         stats->ierrors  = ns->crc_errors +
3109                         ns->rx_length_errors + ns->rx_undersize +
3110                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3111
3112         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3113         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3114         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3115         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3116         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3117         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3118         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3119                     ns->eth.rx_unknown_protocol);
3120         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3121         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3122         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3123         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3124         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3125         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3126
3127         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3128                     ns->tx_dropped_link_down);
3129         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3130         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3131                     ns->illegal_bytes);
3132         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3133         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3134                     ns->mac_local_faults);
3135         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3136                     ns->mac_remote_faults);
3137         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3138                     ns->rx_length_errors);
3139         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3140         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3141         for (i = 0; i < 8; i++) {
3142                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3143                                 i, ns->priority_xon_rx[i]);
3144                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3145                                 i, ns->priority_xoff_rx[i]);
3146         }
3147         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3148         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3149         for (i = 0; i < 8; i++) {
3150                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3151                                 i, ns->priority_xon_tx[i]);
3152                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3153                                 i, ns->priority_xoff_tx[i]);
3154                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3155                                 i, ns->priority_xon_2_xoff[i]);
3156         }
3157         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3158         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3159         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3160         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3161         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3162         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3163         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3164         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3165         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3166         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3167         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3168         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3169         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3170         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3171         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3172         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3173         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3174         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3175         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3176                         ns->mac_short_packet_dropped);
3177         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3178                     ns->checksum_error);
3179         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3180         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3181         return 0;
3182 }
3183
3184 /* Reset the statistics */
3185 static void
3186 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3187 {
3188         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3189         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3190
3191         /* Mark PF and VSI stats to update the offset, aka "reset" */
3192         pf->offset_loaded = false;
3193         if (pf->main_vsi)
3194                 pf->main_vsi->offset_loaded = false;
3195
3196         /* read the stats, reading current register values into offset */
3197         i40e_read_stats_registers(pf, hw);
3198 }
3199
3200 static uint32_t
3201 i40e_xstats_calc_num(void)
3202 {
3203         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3204                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3205                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3206 }
3207
3208 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3209                                      struct rte_eth_xstat_name *xstats_names,
3210                                      __rte_unused unsigned limit)
3211 {
3212         unsigned count = 0;
3213         unsigned i, prio;
3214
3215         if (xstats_names == NULL)
3216                 return i40e_xstats_calc_num();
3217
3218         /* Note: limit checked in rte_eth_xstats_names() */
3219
3220         /* Get stats from i40e_eth_stats struct */
3221         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3222                 snprintf(xstats_names[count].name,
3223                          sizeof(xstats_names[count].name),
3224                          "%s", rte_i40e_stats_strings[i].name);
3225                 count++;
3226         }
3227
3228         /* Get individiual stats from i40e_hw_port struct */
3229         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3230                 snprintf(xstats_names[count].name,
3231                         sizeof(xstats_names[count].name),
3232                          "%s", rte_i40e_hw_port_strings[i].name);
3233                 count++;
3234         }
3235
3236         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3237                 for (prio = 0; prio < 8; prio++) {
3238                         snprintf(xstats_names[count].name,
3239                                  sizeof(xstats_names[count].name),
3240                                  "rx_priority%u_%s", prio,
3241                                  rte_i40e_rxq_prio_strings[i].name);
3242                         count++;
3243                 }
3244         }
3245
3246         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3247                 for (prio = 0; prio < 8; prio++) {
3248                         snprintf(xstats_names[count].name,
3249                                  sizeof(xstats_names[count].name),
3250                                  "tx_priority%u_%s", prio,
3251                                  rte_i40e_txq_prio_strings[i].name);
3252                         count++;
3253                 }
3254         }
3255         return count;
3256 }
3257
3258 static int
3259 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3260                     unsigned n)
3261 {
3262         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3263         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3264         unsigned i, count, prio;
3265         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3266
3267         count = i40e_xstats_calc_num();
3268         if (n < count)
3269                 return count;
3270
3271         i40e_read_stats_registers(pf, hw);
3272
3273         if (xstats == NULL)
3274                 return 0;
3275
3276         count = 0;
3277
3278         /* Get stats from i40e_eth_stats struct */
3279         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3280                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3281                         rte_i40e_stats_strings[i].offset);
3282                 xstats[count].id = count;
3283                 count++;
3284         }
3285
3286         /* Get individiual stats from i40e_hw_port struct */
3287         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3288                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3289                         rte_i40e_hw_port_strings[i].offset);
3290                 xstats[count].id = count;
3291                 count++;
3292         }
3293
3294         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3295                 for (prio = 0; prio < 8; prio++) {
3296                         xstats[count].value =
3297                                 *(uint64_t *)(((char *)hw_stats) +
3298                                 rte_i40e_rxq_prio_strings[i].offset +
3299                                 (sizeof(uint64_t) * prio));
3300                         xstats[count].id = count;
3301                         count++;
3302                 }
3303         }
3304
3305         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3306                 for (prio = 0; prio < 8; prio++) {
3307                         xstats[count].value =
3308                                 *(uint64_t *)(((char *)hw_stats) +
3309                                 rte_i40e_txq_prio_strings[i].offset +
3310                                 (sizeof(uint64_t) * prio));
3311                         xstats[count].id = count;
3312                         count++;
3313                 }
3314         }
3315
3316         return count;
3317 }
3318
3319 static int
3320 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3321                                  __rte_unused uint16_t queue_id,
3322                                  __rte_unused uint8_t stat_idx,
3323                                  __rte_unused uint8_t is_rx)
3324 {
3325         PMD_INIT_FUNC_TRACE();
3326
3327         return -ENOSYS;
3328 }
3329
3330 static int
3331 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3332 {
3333         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3334         u32 full_ver;
3335         u8 ver, patch;
3336         u16 build;
3337         int ret;
3338
3339         full_ver = hw->nvm.oem_ver;
3340         ver = (u8)(full_ver >> 24);
3341         build = (u16)((full_ver >> 8) & 0xffff);
3342         patch = (u8)(full_ver & 0xff);
3343
3344         ret = snprintf(fw_version, fw_size,
3345                  "%d.%d%d 0x%08x %d.%d.%d",
3346                  ((hw->nvm.version >> 12) & 0xf),
3347                  ((hw->nvm.version >> 4) & 0xff),
3348                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3349                  ver, build, patch);
3350
3351         ret += 1; /* add the size of '\0' */
3352         if (fw_size < (u32)ret)
3353                 return ret;
3354         else
3355                 return 0;
3356 }
3357
3358 static void
3359 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3360 {
3361         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3362         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3363         struct i40e_vsi *vsi = pf->main_vsi;
3364         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3365
3366         dev_info->max_rx_queues = vsi->nb_qps;
3367         dev_info->max_tx_queues = vsi->nb_qps;
3368         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3369         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3370         dev_info->max_mac_addrs = vsi->max_macaddrs;
3371         dev_info->max_vfs = pci_dev->max_vfs;
3372         dev_info->rx_queue_offload_capa = 0;
3373         dev_info->rx_offload_capa =
3374                 DEV_RX_OFFLOAD_VLAN_STRIP |
3375                 DEV_RX_OFFLOAD_QINQ_STRIP |
3376                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3377                 DEV_RX_OFFLOAD_UDP_CKSUM |
3378                 DEV_RX_OFFLOAD_TCP_CKSUM |
3379                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3380                 DEV_RX_OFFLOAD_CRC_STRIP |
3381                 DEV_RX_OFFLOAD_KEEP_CRC |
3382                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3383                 DEV_RX_OFFLOAD_VLAN_FILTER |
3384                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3385
3386         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3387         dev_info->tx_offload_capa =
3388                 DEV_TX_OFFLOAD_VLAN_INSERT |
3389                 DEV_TX_OFFLOAD_QINQ_INSERT |
3390                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3391                 DEV_TX_OFFLOAD_UDP_CKSUM |
3392                 DEV_TX_OFFLOAD_TCP_CKSUM |
3393                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3394                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3395                 DEV_TX_OFFLOAD_TCP_TSO |
3396                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3397                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3398                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3399                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3400                 DEV_TX_OFFLOAD_MULTI_SEGS |
3401                 dev_info->tx_queue_offload_capa;
3402         dev_info->dev_capa =
3403                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3404                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3405
3406         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3407                                                 sizeof(uint32_t);
3408         dev_info->reta_size = pf->hash_lut_size;
3409         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3410
3411         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3412                 .rx_thresh = {
3413                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3414                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3415                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3416                 },
3417                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3418                 .rx_drop_en = 0,
3419                 .offloads = 0,
3420         };
3421
3422         dev_info->default_txconf = (struct rte_eth_txconf) {
3423                 .tx_thresh = {
3424                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3425                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3426                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3427                 },
3428                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3429                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3430                 .offloads = 0,
3431         };
3432
3433         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3434                 .nb_max = I40E_MAX_RING_DESC,
3435                 .nb_min = I40E_MIN_RING_DESC,
3436                 .nb_align = I40E_ALIGN_RING_DESC,
3437         };
3438
3439         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3440                 .nb_max = I40E_MAX_RING_DESC,
3441                 .nb_min = I40E_MIN_RING_DESC,
3442                 .nb_align = I40E_ALIGN_RING_DESC,
3443                 .nb_seg_max = I40E_TX_MAX_SEG,
3444                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3445         };
3446
3447         if (pf->flags & I40E_FLAG_VMDQ) {
3448                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3449                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3450                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3451                                                 pf->max_nb_vmdq_vsi;
3452                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3453                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3454                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3455         }
3456
3457         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3458                 /* For XL710 */
3459                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3460                 dev_info->default_rxportconf.nb_queues = 2;
3461                 dev_info->default_txportconf.nb_queues = 2;
3462                 if (dev->data->nb_rx_queues == 1)
3463                         dev_info->default_rxportconf.ring_size = 2048;
3464                 else
3465                         dev_info->default_rxportconf.ring_size = 1024;
3466                 if (dev->data->nb_tx_queues == 1)
3467                         dev_info->default_txportconf.ring_size = 1024;
3468                 else
3469                         dev_info->default_txportconf.ring_size = 512;
3470
3471         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3472                 /* For XXV710 */
3473                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3474                 dev_info->default_rxportconf.nb_queues = 1;
3475                 dev_info->default_txportconf.nb_queues = 1;
3476                 dev_info->default_rxportconf.ring_size = 256;
3477                 dev_info->default_txportconf.ring_size = 256;
3478         } else {
3479                 /* For X710 */
3480                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3481                 dev_info->default_rxportconf.nb_queues = 1;
3482                 dev_info->default_txportconf.nb_queues = 1;
3483                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3484                         dev_info->default_rxportconf.ring_size = 512;
3485                         dev_info->default_txportconf.ring_size = 256;
3486                 } else {
3487                         dev_info->default_rxportconf.ring_size = 256;
3488                         dev_info->default_txportconf.ring_size = 256;
3489                 }
3490         }
3491         dev_info->default_rxportconf.burst_size = 32;
3492         dev_info->default_txportconf.burst_size = 32;
3493 }
3494
3495 static int
3496 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3497 {
3498         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3499         struct i40e_vsi *vsi = pf->main_vsi;
3500         PMD_INIT_FUNC_TRACE();
3501
3502         if (on)
3503                 return i40e_vsi_add_vlan(vsi, vlan_id);
3504         else
3505                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3506 }
3507
3508 static int
3509 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3510                                 enum rte_vlan_type vlan_type,
3511                                 uint16_t tpid, int qinq)
3512 {
3513         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3514         uint64_t reg_r = 0;
3515         uint64_t reg_w = 0;
3516         uint16_t reg_id = 3;
3517         int ret;
3518
3519         if (qinq) {
3520                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3521                         reg_id = 2;
3522         }
3523
3524         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3525                                           &reg_r, NULL);
3526         if (ret != I40E_SUCCESS) {
3527                 PMD_DRV_LOG(ERR,
3528                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3529                            reg_id);
3530                 return -EIO;
3531         }
3532         PMD_DRV_LOG(DEBUG,
3533                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3534                     reg_id, reg_r);
3535
3536         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3537         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3538         if (reg_r == reg_w) {
3539                 PMD_DRV_LOG(DEBUG, "No need to write");
3540                 return 0;
3541         }
3542
3543         ret = i40e_aq_debug_write_global_register(hw,
3544                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3545                                            reg_w, NULL);
3546         if (ret != I40E_SUCCESS) {
3547                 PMD_DRV_LOG(ERR,
3548                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3549                             reg_id);
3550                 return -EIO;
3551         }
3552         PMD_DRV_LOG(DEBUG,
3553                     "Global register 0x%08x is changed with value 0x%08x",
3554                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3555
3556         return 0;
3557 }
3558
3559 static int
3560 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3561                    enum rte_vlan_type vlan_type,
3562                    uint16_t tpid)
3563 {
3564         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3565         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3566         int qinq = dev->data->dev_conf.rxmode.offloads &
3567                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3568         int ret = 0;
3569
3570         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3571              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3572             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3573                 PMD_DRV_LOG(ERR,
3574                             "Unsupported vlan type.");
3575                 return -EINVAL;
3576         }
3577
3578         if (pf->support_multi_driver) {
3579                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3580                 return -ENOTSUP;
3581         }
3582
3583         /* 802.1ad frames ability is added in NVM API 1.7*/
3584         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3585                 if (qinq) {
3586                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3587                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3588                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3589                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3590                 } else {
3591                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3592                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3593                 }
3594                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3595                 if (ret != I40E_SUCCESS) {
3596                         PMD_DRV_LOG(ERR,
3597                                     "Set switch config failed aq_err: %d",
3598                                     hw->aq.asq_last_status);
3599                         ret = -EIO;
3600                 }
3601         } else
3602                 /* If NVM API < 1.7, keep the register setting */
3603                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3604                                                       tpid, qinq);
3605
3606         return ret;
3607 }
3608
3609 static int
3610 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3611 {
3612         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3613         struct i40e_vsi *vsi = pf->main_vsi;
3614         struct rte_eth_rxmode *rxmode;
3615
3616         rxmode = &dev->data->dev_conf.rxmode;
3617         if (mask & ETH_VLAN_FILTER_MASK) {
3618                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3619                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3620                 else
3621                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3622         }
3623
3624         if (mask & ETH_VLAN_STRIP_MASK) {
3625                 /* Enable or disable VLAN stripping */
3626                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3627                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3628                 else
3629                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3630         }
3631
3632         if (mask & ETH_VLAN_EXTEND_MASK) {
3633                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3634                         i40e_vsi_config_double_vlan(vsi, TRUE);
3635                         /* Set global registers with default ethertype. */
3636                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3637                                            ETHER_TYPE_VLAN);
3638                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3639                                            ETHER_TYPE_VLAN);
3640                 }
3641                 else
3642                         i40e_vsi_config_double_vlan(vsi, FALSE);
3643         }
3644
3645         return 0;
3646 }
3647
3648 static void
3649 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3650                           __rte_unused uint16_t queue,
3651                           __rte_unused int on)
3652 {
3653         PMD_INIT_FUNC_TRACE();
3654 }
3655
3656 static int
3657 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3658 {
3659         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3660         struct i40e_vsi *vsi = pf->main_vsi;
3661         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3662         struct i40e_vsi_vlan_pvid_info info;
3663
3664         memset(&info, 0, sizeof(info));
3665         info.on = on;
3666         if (info.on)
3667                 info.config.pvid = pvid;
3668         else {
3669                 info.config.reject.tagged =
3670                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3671                 info.config.reject.untagged =
3672                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3673         }
3674
3675         return i40e_vsi_vlan_pvid_set(vsi, &info);
3676 }
3677
3678 static int
3679 i40e_dev_led_on(struct rte_eth_dev *dev)
3680 {
3681         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3682         uint32_t mode = i40e_led_get(hw);
3683
3684         if (mode == 0)
3685                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3686
3687         return 0;
3688 }
3689
3690 static int
3691 i40e_dev_led_off(struct rte_eth_dev *dev)
3692 {
3693         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3694         uint32_t mode = i40e_led_get(hw);
3695
3696         if (mode != 0)
3697                 i40e_led_set(hw, 0, false);
3698
3699         return 0;
3700 }
3701
3702 static int
3703 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3704 {
3705         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3706         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3707
3708         fc_conf->pause_time = pf->fc_conf.pause_time;
3709
3710         /* read out from register, in case they are modified by other port */
3711         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3712                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3713         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3714                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3715
3716         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3717         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3718
3719          /* Return current mode according to actual setting*/
3720         switch (hw->fc.current_mode) {
3721         case I40E_FC_FULL:
3722                 fc_conf->mode = RTE_FC_FULL;
3723                 break;
3724         case I40E_FC_TX_PAUSE:
3725                 fc_conf->mode = RTE_FC_TX_PAUSE;
3726                 break;
3727         case I40E_FC_RX_PAUSE:
3728                 fc_conf->mode = RTE_FC_RX_PAUSE;
3729                 break;
3730         case I40E_FC_NONE:
3731         default:
3732                 fc_conf->mode = RTE_FC_NONE;
3733         };
3734
3735         return 0;
3736 }
3737
3738 static int
3739 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3740 {
3741         uint32_t mflcn_reg, fctrl_reg, reg;
3742         uint32_t max_high_water;
3743         uint8_t i, aq_failure;
3744         int err;
3745         struct i40e_hw *hw;
3746         struct i40e_pf *pf;
3747         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3748                 [RTE_FC_NONE] = I40E_FC_NONE,
3749                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3750                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3751                 [RTE_FC_FULL] = I40E_FC_FULL
3752         };
3753
3754         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3755
3756         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3757         if ((fc_conf->high_water > max_high_water) ||
3758                         (fc_conf->high_water < fc_conf->low_water)) {
3759                 PMD_INIT_LOG(ERR,
3760                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3761                         max_high_water);
3762                 return -EINVAL;
3763         }
3764
3765         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3766         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3767         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3768
3769         pf->fc_conf.pause_time = fc_conf->pause_time;
3770         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3771         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3772
3773         PMD_INIT_FUNC_TRACE();
3774
3775         /* All the link flow control related enable/disable register
3776          * configuration is handle by the F/W
3777          */
3778         err = i40e_set_fc(hw, &aq_failure, true);
3779         if (err < 0)
3780                 return -ENOSYS;
3781
3782         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3783                 /* Configure flow control refresh threshold,
3784                  * the value for stat_tx_pause_refresh_timer[8]
3785                  * is used for global pause operation.
3786                  */
3787
3788                 I40E_WRITE_REG(hw,
3789                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3790                                pf->fc_conf.pause_time);
3791
3792                 /* configure the timer value included in transmitted pause
3793                  * frame,
3794                  * the value for stat_tx_pause_quanta[8] is used for global
3795                  * pause operation
3796                  */
3797                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3798                                pf->fc_conf.pause_time);
3799
3800                 fctrl_reg = I40E_READ_REG(hw,
3801                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3802
3803                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3804                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3805                 else
3806                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3807
3808                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3809                                fctrl_reg);
3810         } else {
3811                 /* Configure pause time (2 TCs per register) */
3812                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3813                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3814                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3815
3816                 /* Configure flow control refresh threshold value */
3817                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3818                                pf->fc_conf.pause_time / 2);
3819
3820                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3821
3822                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3823                  *depending on configuration
3824                  */
3825                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3826                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3827                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3828                 } else {
3829                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3830                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3831                 }
3832
3833                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3834         }
3835
3836         if (!pf->support_multi_driver) {
3837                 /* config water marker both based on the packets and bytes */
3838                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3839                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3840                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3841                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3842                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3843                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3844                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3845                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3846                                   << I40E_KILOSHIFT);
3847                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3848                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3849                                    << I40E_KILOSHIFT);
3850         } else {
3851                 PMD_DRV_LOG(ERR,
3852                             "Water marker configuration is not supported.");
3853         }
3854
3855         I40E_WRITE_FLUSH(hw);
3856
3857         return 0;
3858 }
3859
3860 static int
3861 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3862                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3863 {
3864         PMD_INIT_FUNC_TRACE();
3865
3866         return -ENOSYS;
3867 }
3868
3869 /* Add a MAC address, and update filters */
3870 static int
3871 i40e_macaddr_add(struct rte_eth_dev *dev,
3872                  struct ether_addr *mac_addr,
3873                  __rte_unused uint32_t index,
3874                  uint32_t pool)
3875 {
3876         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3877         struct i40e_mac_filter_info mac_filter;
3878         struct i40e_vsi *vsi;
3879         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3880         int ret;
3881
3882         /* If VMDQ not enabled or configured, return */
3883         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3884                           !pf->nb_cfg_vmdq_vsi)) {
3885                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3886                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3887                         pool);
3888                 return -ENOTSUP;
3889         }
3890
3891         if (pool > pf->nb_cfg_vmdq_vsi) {
3892                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3893                                 pool, pf->nb_cfg_vmdq_vsi);
3894                 return -EINVAL;
3895         }
3896
3897         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3898         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3899                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3900         else
3901                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3902
3903         if (pool == 0)
3904                 vsi = pf->main_vsi;
3905         else
3906                 vsi = pf->vmdq[pool - 1].vsi;
3907
3908         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3909         if (ret != I40E_SUCCESS) {
3910                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3911                 return -ENODEV;
3912         }
3913         return 0;
3914 }
3915
3916 /* Remove a MAC address, and update filters */
3917 static void
3918 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3919 {
3920         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3921         struct i40e_vsi *vsi;
3922         struct rte_eth_dev_data *data = dev->data;
3923         struct ether_addr *macaddr;
3924         int ret;
3925         uint32_t i;
3926         uint64_t pool_sel;
3927
3928         macaddr = &(data->mac_addrs[index]);
3929
3930         pool_sel = dev->data->mac_pool_sel[index];
3931
3932         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3933                 if (pool_sel & (1ULL << i)) {
3934                         if (i == 0)
3935                                 vsi = pf->main_vsi;
3936                         else {
3937                                 /* No VMDQ pool enabled or configured */
3938                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3939                                         (i > pf->nb_cfg_vmdq_vsi)) {
3940                                         PMD_DRV_LOG(ERR,
3941                                                 "No VMDQ pool enabled/configured");
3942                                         return;
3943                                 }
3944                                 vsi = pf->vmdq[i - 1].vsi;
3945                         }
3946                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3947
3948                         if (ret) {
3949                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3950                                 return;
3951                         }
3952                 }
3953         }
3954 }
3955
3956 /* Set perfect match or hash match of MAC and VLAN for a VF */
3957 static int
3958 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3959                  struct rte_eth_mac_filter *filter,
3960                  bool add)
3961 {
3962         struct i40e_hw *hw;
3963         struct i40e_mac_filter_info mac_filter;
3964         struct ether_addr old_mac;
3965         struct ether_addr *new_mac;
3966         struct i40e_pf_vf *vf = NULL;
3967         uint16_t vf_id;
3968         int ret;
3969
3970         if (pf == NULL) {
3971                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3972                 return -EINVAL;
3973         }
3974         hw = I40E_PF_TO_HW(pf);
3975
3976         if (filter == NULL) {
3977                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3978                 return -EINVAL;
3979         }
3980
3981         new_mac = &filter->mac_addr;
3982
3983         if (is_zero_ether_addr(new_mac)) {
3984                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3985                 return -EINVAL;
3986         }
3987
3988         vf_id = filter->dst_id;
3989
3990         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3991                 PMD_DRV_LOG(ERR, "Invalid argument.");
3992                 return -EINVAL;
3993         }
3994         vf = &pf->vfs[vf_id];
3995
3996         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3997                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3998                 return -EINVAL;
3999         }
4000
4001         if (add) {
4002                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
4003                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4004                                 ETHER_ADDR_LEN);
4005                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4006                                  ETHER_ADDR_LEN);
4007
4008                 mac_filter.filter_type = filter->filter_type;
4009                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4010                 if (ret != I40E_SUCCESS) {
4011                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4012                         return -1;
4013                 }
4014                 ether_addr_copy(new_mac, &pf->dev_addr);
4015         } else {
4016                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4017                                 ETHER_ADDR_LEN);
4018                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4019                 if (ret != I40E_SUCCESS) {
4020                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4021                         return -1;
4022                 }
4023
4024                 /* Clear device address as it has been removed */
4025                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
4026                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
4027         }
4028
4029         return 0;
4030 }
4031
4032 /* MAC filter handle */
4033 static int
4034 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4035                 void *arg)
4036 {
4037         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4038         struct rte_eth_mac_filter *filter;
4039         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4040         int ret = I40E_NOT_SUPPORTED;
4041
4042         filter = (struct rte_eth_mac_filter *)(arg);
4043
4044         switch (filter_op) {
4045         case RTE_ETH_FILTER_NOP:
4046                 ret = I40E_SUCCESS;
4047                 break;
4048         case RTE_ETH_FILTER_ADD:
4049                 i40e_pf_disable_irq0(hw);
4050                 if (filter->is_vf)
4051                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4052                 i40e_pf_enable_irq0(hw);
4053                 break;
4054         case RTE_ETH_FILTER_DELETE:
4055                 i40e_pf_disable_irq0(hw);
4056                 if (filter->is_vf)
4057                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4058                 i40e_pf_enable_irq0(hw);
4059                 break;
4060         default:
4061                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4062                 ret = I40E_ERR_PARAM;
4063                 break;
4064         }
4065
4066         return ret;
4067 }
4068
4069 static int
4070 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4071 {
4072         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4073         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4074         uint32_t reg;
4075         int ret;
4076
4077         if (!lut)
4078                 return -EINVAL;
4079
4080         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4081                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4082                                           lut, lut_size);
4083                 if (ret) {
4084                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4085                         return ret;
4086                 }
4087         } else {
4088                 uint32_t *lut_dw = (uint32_t *)lut;
4089                 uint16_t i, lut_size_dw = lut_size / 4;
4090
4091                 if (vsi->type == I40E_VSI_SRIOV) {
4092                         for (i = 0; i <= lut_size_dw; i++) {
4093                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4094                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4095                         }
4096                 } else {
4097                         for (i = 0; i < lut_size_dw; i++)
4098                                 lut_dw[i] = I40E_READ_REG(hw,
4099                                                           I40E_PFQF_HLUT(i));
4100                 }
4101         }
4102
4103         return 0;
4104 }
4105
4106 int
4107 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4108 {
4109         struct i40e_pf *pf;
4110         struct i40e_hw *hw;
4111         int ret;
4112
4113         if (!vsi || !lut)
4114                 return -EINVAL;
4115
4116         pf = I40E_VSI_TO_PF(vsi);
4117         hw = I40E_VSI_TO_HW(vsi);
4118
4119         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4120                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4121                                           lut, lut_size);
4122                 if (ret) {
4123                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4124                         return ret;
4125                 }
4126         } else {
4127                 uint32_t *lut_dw = (uint32_t *)lut;
4128                 uint16_t i, lut_size_dw = lut_size / 4;
4129
4130                 if (vsi->type == I40E_VSI_SRIOV) {
4131                         for (i = 0; i < lut_size_dw; i++)
4132                                 I40E_WRITE_REG(
4133                                         hw,
4134                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4135                                         lut_dw[i]);
4136                 } else {
4137                         for (i = 0; i < lut_size_dw; i++)
4138                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4139                                                lut_dw[i]);
4140                 }
4141                 I40E_WRITE_FLUSH(hw);
4142         }
4143
4144         return 0;
4145 }
4146
4147 static int
4148 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4149                          struct rte_eth_rss_reta_entry64 *reta_conf,
4150                          uint16_t reta_size)
4151 {
4152         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4153         uint16_t i, lut_size = pf->hash_lut_size;
4154         uint16_t idx, shift;
4155         uint8_t *lut;
4156         int ret;
4157
4158         if (reta_size != lut_size ||
4159                 reta_size > ETH_RSS_RETA_SIZE_512) {
4160                 PMD_DRV_LOG(ERR,
4161                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4162                         reta_size, lut_size);
4163                 return -EINVAL;
4164         }
4165
4166         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4167         if (!lut) {
4168                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4169                 return -ENOMEM;
4170         }
4171         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4172         if (ret)
4173                 goto out;
4174         for (i = 0; i < reta_size; i++) {
4175                 idx = i / RTE_RETA_GROUP_SIZE;
4176                 shift = i % RTE_RETA_GROUP_SIZE;
4177                 if (reta_conf[idx].mask & (1ULL << shift))
4178                         lut[i] = reta_conf[idx].reta[shift];
4179         }
4180         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4181
4182 out:
4183         rte_free(lut);
4184
4185         return ret;
4186 }
4187
4188 static int
4189 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4190                         struct rte_eth_rss_reta_entry64 *reta_conf,
4191                         uint16_t reta_size)
4192 {
4193         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4194         uint16_t i, lut_size = pf->hash_lut_size;
4195         uint16_t idx, shift;
4196         uint8_t *lut;
4197         int ret;
4198
4199         if (reta_size != lut_size ||
4200                 reta_size > ETH_RSS_RETA_SIZE_512) {
4201                 PMD_DRV_LOG(ERR,
4202                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4203                         reta_size, lut_size);
4204                 return -EINVAL;
4205         }
4206
4207         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4208         if (!lut) {
4209                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4210                 return -ENOMEM;
4211         }
4212
4213         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4214         if (ret)
4215                 goto out;
4216         for (i = 0; i < reta_size; i++) {
4217                 idx = i / RTE_RETA_GROUP_SIZE;
4218                 shift = i % RTE_RETA_GROUP_SIZE;
4219                 if (reta_conf[idx].mask & (1ULL << shift))
4220                         reta_conf[idx].reta[shift] = lut[i];
4221         }
4222
4223 out:
4224         rte_free(lut);
4225
4226         return ret;
4227 }
4228
4229 /**
4230  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4231  * @hw:   pointer to the HW structure
4232  * @mem:  pointer to mem struct to fill out
4233  * @size: size of memory requested
4234  * @alignment: what to align the allocation to
4235  **/
4236 enum i40e_status_code
4237 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4238                         struct i40e_dma_mem *mem,
4239                         u64 size,
4240                         u32 alignment)
4241 {
4242         const struct rte_memzone *mz = NULL;
4243         char z_name[RTE_MEMZONE_NAMESIZE];
4244
4245         if (!mem)
4246                 return I40E_ERR_PARAM;
4247
4248         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4249         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4250                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4251         if (!mz)
4252                 return I40E_ERR_NO_MEMORY;
4253
4254         mem->size = size;
4255         mem->va = mz->addr;
4256         mem->pa = mz->iova;
4257         mem->zone = (const void *)mz;
4258         PMD_DRV_LOG(DEBUG,
4259                 "memzone %s allocated with physical address: %"PRIu64,
4260                 mz->name, mem->pa);
4261
4262         return I40E_SUCCESS;
4263 }
4264
4265 /**
4266  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4267  * @hw:   pointer to the HW structure
4268  * @mem:  ptr to mem struct to free
4269  **/
4270 enum i40e_status_code
4271 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4272                     struct i40e_dma_mem *mem)
4273 {
4274         if (!mem)
4275                 return I40E_ERR_PARAM;
4276
4277         PMD_DRV_LOG(DEBUG,
4278                 "memzone %s to be freed with physical address: %"PRIu64,
4279                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4280         rte_memzone_free((const struct rte_memzone *)mem->zone);
4281         mem->zone = NULL;
4282         mem->va = NULL;
4283         mem->pa = (u64)0;
4284
4285         return I40E_SUCCESS;
4286 }
4287
4288 /**
4289  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4290  * @hw:   pointer to the HW structure
4291  * @mem:  pointer to mem struct to fill out
4292  * @size: size of memory requested
4293  **/
4294 enum i40e_status_code
4295 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4296                          struct i40e_virt_mem *mem,
4297                          u32 size)
4298 {
4299         if (!mem)
4300                 return I40E_ERR_PARAM;
4301
4302         mem->size = size;
4303         mem->va = rte_zmalloc("i40e", size, 0);
4304
4305         if (mem->va)
4306                 return I40E_SUCCESS;
4307         else
4308                 return I40E_ERR_NO_MEMORY;
4309 }
4310
4311 /**
4312  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4313  * @hw:   pointer to the HW structure
4314  * @mem:  pointer to mem struct to free
4315  **/
4316 enum i40e_status_code
4317 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4318                      struct i40e_virt_mem *mem)
4319 {
4320         if (!mem)
4321                 return I40E_ERR_PARAM;
4322
4323         rte_free(mem->va);
4324         mem->va = NULL;
4325
4326         return I40E_SUCCESS;
4327 }
4328
4329 void
4330 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4331 {
4332         rte_spinlock_init(&sp->spinlock);
4333 }
4334
4335 void
4336 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4337 {
4338         rte_spinlock_lock(&sp->spinlock);
4339 }
4340
4341 void
4342 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4343 {
4344         rte_spinlock_unlock(&sp->spinlock);
4345 }
4346
4347 void
4348 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4349 {
4350         return;
4351 }
4352
4353 /**
4354  * Get the hardware capabilities, which will be parsed
4355  * and saved into struct i40e_hw.
4356  */
4357 static int
4358 i40e_get_cap(struct i40e_hw *hw)
4359 {
4360         struct i40e_aqc_list_capabilities_element_resp *buf;
4361         uint16_t len, size = 0;
4362         int ret;
4363
4364         /* Calculate a huge enough buff for saving response data temporarily */
4365         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4366                                                 I40E_MAX_CAP_ELE_NUM;
4367         buf = rte_zmalloc("i40e", len, 0);
4368         if (!buf) {
4369                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4370                 return I40E_ERR_NO_MEMORY;
4371         }
4372
4373         /* Get, parse the capabilities and save it to hw */
4374         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4375                         i40e_aqc_opc_list_func_capabilities, NULL);
4376         if (ret != I40E_SUCCESS)
4377                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4378
4379         /* Free the temporary buffer after being used */
4380         rte_free(buf);
4381
4382         return ret;
4383 }
4384
4385 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4386
4387 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4388                 const char *value,
4389                 void *opaque)
4390 {
4391         struct i40e_pf *pf;
4392         unsigned long num;
4393         char *end;
4394
4395         pf = (struct i40e_pf *)opaque;
4396         RTE_SET_USED(key);
4397
4398         errno = 0;
4399         num = strtoul(value, &end, 0);
4400         if (errno != 0 || end == value || *end != 0) {
4401                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4402                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4403                 return -(EINVAL);
4404         }
4405
4406         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4407                 pf->vf_nb_qp_max = (uint16_t)num;
4408         else
4409                 /* here return 0 to make next valid same argument work */
4410                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4411                             "power of 2 and equal or less than 16 !, Now it is "
4412                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4413
4414         return 0;
4415 }
4416
4417 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4418 {
4419         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4420         struct rte_kvargs *kvlist;
4421         int kvargs_count;
4422
4423         /* set default queue number per VF as 4 */
4424         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4425
4426         if (dev->device->devargs == NULL)
4427                 return 0;
4428
4429         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4430         if (kvlist == NULL)
4431                 return -(EINVAL);
4432
4433         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4434         if (!kvargs_count) {
4435                 rte_kvargs_free(kvlist);
4436                 return 0;
4437         }
4438
4439         if (kvargs_count > 1)
4440                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4441                             "the first invalid or last valid one is used !",
4442                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4443
4444         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4445                            i40e_pf_parse_vf_queue_number_handler, pf);
4446
4447         rte_kvargs_free(kvlist);
4448
4449         return 0;
4450 }
4451
4452 static int
4453 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4454 {
4455         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4456         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4457         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4458         uint16_t qp_count = 0, vsi_count = 0;
4459
4460         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4461                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4462                 return -EINVAL;
4463         }
4464
4465         i40e_pf_config_vf_rxq_number(dev);
4466
4467         /* Add the parameter init for LFC */
4468         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4469         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4470         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4471
4472         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4473         pf->max_num_vsi = hw->func_caps.num_vsis;
4474         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4475         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4476
4477         /* FDir queue/VSI allocation */
4478         pf->fdir_qp_offset = 0;
4479         if (hw->func_caps.fd) {
4480                 pf->flags |= I40E_FLAG_FDIR;
4481                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4482         } else {
4483                 pf->fdir_nb_qps = 0;
4484         }
4485         qp_count += pf->fdir_nb_qps;
4486         vsi_count += 1;
4487
4488         /* LAN queue/VSI allocation */
4489         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4490         if (!hw->func_caps.rss) {
4491                 pf->lan_nb_qps = 1;
4492         } else {
4493                 pf->flags |= I40E_FLAG_RSS;
4494                 if (hw->mac.type == I40E_MAC_X722)
4495                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4496                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4497         }
4498         qp_count += pf->lan_nb_qps;
4499         vsi_count += 1;
4500
4501         /* VF queue/VSI allocation */
4502         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4503         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4504                 pf->flags |= I40E_FLAG_SRIOV;
4505                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4506                 pf->vf_num = pci_dev->max_vfs;
4507                 PMD_DRV_LOG(DEBUG,
4508                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4509                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4510         } else {
4511                 pf->vf_nb_qps = 0;
4512                 pf->vf_num = 0;
4513         }
4514         qp_count += pf->vf_nb_qps * pf->vf_num;
4515         vsi_count += pf->vf_num;
4516
4517         /* VMDq queue/VSI allocation */
4518         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4519         pf->vmdq_nb_qps = 0;
4520         pf->max_nb_vmdq_vsi = 0;
4521         if (hw->func_caps.vmdq) {
4522                 if (qp_count < hw->func_caps.num_tx_qp &&
4523                         vsi_count < hw->func_caps.num_vsis) {
4524                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4525                                 qp_count) / pf->vmdq_nb_qp_max;
4526
4527                         /* Limit the maximum number of VMDq vsi to the maximum
4528                          * ethdev can support
4529                          */
4530                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4531                                 hw->func_caps.num_vsis - vsi_count);
4532                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4533                                 ETH_64_POOLS);
4534                         if (pf->max_nb_vmdq_vsi) {
4535                                 pf->flags |= I40E_FLAG_VMDQ;
4536                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4537                                 PMD_DRV_LOG(DEBUG,
4538                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4539                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4540                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4541                         } else {
4542                                 PMD_DRV_LOG(INFO,
4543                                         "No enough queues left for VMDq");
4544                         }
4545                 } else {
4546                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4547                 }
4548         }
4549         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4550         vsi_count += pf->max_nb_vmdq_vsi;
4551
4552         if (hw->func_caps.dcb)
4553                 pf->flags |= I40E_FLAG_DCB;
4554
4555         if (qp_count > hw->func_caps.num_tx_qp) {
4556                 PMD_DRV_LOG(ERR,
4557                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4558                         qp_count, hw->func_caps.num_tx_qp);
4559                 return -EINVAL;
4560         }
4561         if (vsi_count > hw->func_caps.num_vsis) {
4562                 PMD_DRV_LOG(ERR,
4563                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4564                         vsi_count, hw->func_caps.num_vsis);
4565                 return -EINVAL;
4566         }
4567
4568         return 0;
4569 }
4570
4571 static int
4572 i40e_pf_get_switch_config(struct i40e_pf *pf)
4573 {
4574         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4575         struct i40e_aqc_get_switch_config_resp *switch_config;
4576         struct i40e_aqc_switch_config_element_resp *element;
4577         uint16_t start_seid = 0, num_reported;
4578         int ret;
4579
4580         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4581                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4582         if (!switch_config) {
4583                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4584                 return -ENOMEM;
4585         }
4586
4587         /* Get the switch configurations */
4588         ret = i40e_aq_get_switch_config(hw, switch_config,
4589                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4590         if (ret != I40E_SUCCESS) {
4591                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4592                 goto fail;
4593         }
4594         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4595         if (num_reported != 1) { /* The number should be 1 */
4596                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4597                 goto fail;
4598         }
4599
4600         /* Parse the switch configuration elements */
4601         element = &(switch_config->element[0]);
4602         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4603                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4604                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4605         } else
4606                 PMD_DRV_LOG(INFO, "Unknown element type");
4607
4608 fail:
4609         rte_free(switch_config);
4610
4611         return ret;
4612 }
4613
4614 static int
4615 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4616                         uint32_t num)
4617 {
4618         struct pool_entry *entry;
4619
4620         if (pool == NULL || num == 0)
4621                 return -EINVAL;
4622
4623         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4624         if (entry == NULL) {
4625                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4626                 return -ENOMEM;
4627         }
4628
4629         /* queue heap initialize */
4630         pool->num_free = num;
4631         pool->num_alloc = 0;
4632         pool->base = base;
4633         LIST_INIT(&pool->alloc_list);
4634         LIST_INIT(&pool->free_list);
4635
4636         /* Initialize element  */
4637         entry->base = 0;
4638         entry->len = num;
4639
4640         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4641         return 0;
4642 }
4643
4644 static void
4645 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4646 {
4647         struct pool_entry *entry, *next_entry;
4648
4649         if (pool == NULL)
4650                 return;
4651
4652         for (entry = LIST_FIRST(&pool->alloc_list);
4653                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4654                         entry = next_entry) {
4655                 LIST_REMOVE(entry, next);
4656                 rte_free(entry);
4657         }
4658
4659         for (entry = LIST_FIRST(&pool->free_list);
4660                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4661                         entry = next_entry) {
4662                 LIST_REMOVE(entry, next);
4663                 rte_free(entry);
4664         }
4665
4666         pool->num_free = 0;
4667         pool->num_alloc = 0;
4668         pool->base = 0;
4669         LIST_INIT(&pool->alloc_list);
4670         LIST_INIT(&pool->free_list);
4671 }
4672
4673 static int
4674 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4675                        uint32_t base)
4676 {
4677         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4678         uint32_t pool_offset;
4679         int insert;
4680
4681         if (pool == NULL) {
4682                 PMD_DRV_LOG(ERR, "Invalid parameter");
4683                 return -EINVAL;
4684         }
4685
4686         pool_offset = base - pool->base;
4687         /* Lookup in alloc list */
4688         LIST_FOREACH(entry, &pool->alloc_list, next) {
4689                 if (entry->base == pool_offset) {
4690                         valid_entry = entry;
4691                         LIST_REMOVE(entry, next);
4692                         break;
4693                 }
4694         }
4695
4696         /* Not find, return */
4697         if (valid_entry == NULL) {
4698                 PMD_DRV_LOG(ERR, "Failed to find entry");
4699                 return -EINVAL;
4700         }
4701
4702         /**
4703          * Found it, move it to free list  and try to merge.
4704          * In order to make merge easier, always sort it by qbase.
4705          * Find adjacent prev and last entries.
4706          */
4707         prev = next = NULL;
4708         LIST_FOREACH(entry, &pool->free_list, next) {
4709                 if (entry->base > valid_entry->base) {
4710                         next = entry;
4711                         break;
4712                 }
4713                 prev = entry;
4714         }
4715
4716         insert = 0;
4717         /* Try to merge with next one*/
4718         if (next != NULL) {
4719                 /* Merge with next one */
4720                 if (valid_entry->base + valid_entry->len == next->base) {
4721                         next->base = valid_entry->base;
4722                         next->len += valid_entry->len;
4723                         rte_free(valid_entry);
4724                         valid_entry = next;
4725                         insert = 1;
4726                 }
4727         }
4728
4729         if (prev != NULL) {
4730                 /* Merge with previous one */
4731                 if (prev->base + prev->len == valid_entry->base) {
4732                         prev->len += valid_entry->len;
4733                         /* If it merge with next one, remove next node */
4734                         if (insert == 1) {
4735                                 LIST_REMOVE(valid_entry, next);
4736                                 rte_free(valid_entry);
4737                         } else {
4738                                 rte_free(valid_entry);
4739                                 insert = 1;
4740                         }
4741                 }
4742         }
4743
4744         /* Not find any entry to merge, insert */
4745         if (insert == 0) {
4746                 if (prev != NULL)
4747                         LIST_INSERT_AFTER(prev, valid_entry, next);
4748                 else if (next != NULL)
4749                         LIST_INSERT_BEFORE(next, valid_entry, next);
4750                 else /* It's empty list, insert to head */
4751                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4752         }
4753
4754         pool->num_free += valid_entry->len;
4755         pool->num_alloc -= valid_entry->len;
4756
4757         return 0;
4758 }
4759
4760 static int
4761 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4762                        uint16_t num)
4763 {
4764         struct pool_entry *entry, *valid_entry;
4765
4766         if (pool == NULL || num == 0) {
4767                 PMD_DRV_LOG(ERR, "Invalid parameter");
4768                 return -EINVAL;
4769         }
4770
4771         if (pool->num_free < num) {
4772                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4773                             num, pool->num_free);
4774                 return -ENOMEM;
4775         }
4776
4777         valid_entry = NULL;
4778         /* Lookup  in free list and find most fit one */
4779         LIST_FOREACH(entry, &pool->free_list, next) {
4780                 if (entry->len >= num) {
4781                         /* Find best one */
4782                         if (entry->len == num) {
4783                                 valid_entry = entry;
4784                                 break;
4785                         }
4786                         if (valid_entry == NULL || valid_entry->len > entry->len)
4787                                 valid_entry = entry;
4788                 }
4789         }
4790
4791         /* Not find one to satisfy the request, return */
4792         if (valid_entry == NULL) {
4793                 PMD_DRV_LOG(ERR, "No valid entry found");
4794                 return -ENOMEM;
4795         }
4796         /**
4797          * The entry have equal queue number as requested,
4798          * remove it from alloc_list.
4799          */
4800         if (valid_entry->len == num) {
4801                 LIST_REMOVE(valid_entry, next);
4802         } else {
4803                 /**
4804                  * The entry have more numbers than requested,
4805                  * create a new entry for alloc_list and minus its
4806                  * queue base and number in free_list.
4807                  */
4808                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4809                 if (entry == NULL) {
4810                         PMD_DRV_LOG(ERR,
4811                                 "Failed to allocate memory for resource pool");
4812                         return -ENOMEM;
4813                 }
4814                 entry->base = valid_entry->base;
4815                 entry->len = num;
4816                 valid_entry->base += num;
4817                 valid_entry->len -= num;
4818                 valid_entry = entry;
4819         }
4820
4821         /* Insert it into alloc list, not sorted */
4822         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4823
4824         pool->num_free -= valid_entry->len;
4825         pool->num_alloc += valid_entry->len;
4826
4827         return valid_entry->base + pool->base;
4828 }
4829
4830 /**
4831  * bitmap_is_subset - Check whether src2 is subset of src1
4832  **/
4833 static inline int
4834 bitmap_is_subset(uint8_t src1, uint8_t src2)
4835 {
4836         return !((src1 ^ src2) & src2);
4837 }
4838
4839 static enum i40e_status_code
4840 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4841 {
4842         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4843
4844         /* If DCB is not supported, only default TC is supported */
4845         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4846                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4847                 return I40E_NOT_SUPPORTED;
4848         }
4849
4850         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4851                 PMD_DRV_LOG(ERR,
4852                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4853                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4854                 return I40E_NOT_SUPPORTED;
4855         }
4856         return I40E_SUCCESS;
4857 }
4858
4859 int
4860 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4861                                 struct i40e_vsi_vlan_pvid_info *info)
4862 {
4863         struct i40e_hw *hw;
4864         struct i40e_vsi_context ctxt;
4865         uint8_t vlan_flags = 0;
4866         int ret;
4867
4868         if (vsi == NULL || info == NULL) {
4869                 PMD_DRV_LOG(ERR, "invalid parameters");
4870                 return I40E_ERR_PARAM;
4871         }
4872
4873         if (info->on) {
4874                 vsi->info.pvid = info->config.pvid;
4875                 /**
4876                  * If insert pvid is enabled, only tagged pkts are
4877                  * allowed to be sent out.
4878                  */
4879                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4880                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4881         } else {
4882                 vsi->info.pvid = 0;
4883                 if (info->config.reject.tagged == 0)
4884                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4885
4886                 if (info->config.reject.untagged == 0)
4887                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4888         }
4889         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4890                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4891         vsi->info.port_vlan_flags |= vlan_flags;
4892         vsi->info.valid_sections =
4893                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4894         memset(&ctxt, 0, sizeof(ctxt));
4895         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4896         ctxt.seid = vsi->seid;
4897
4898         hw = I40E_VSI_TO_HW(vsi);
4899         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4900         if (ret != I40E_SUCCESS)
4901                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4902
4903         return ret;
4904 }
4905
4906 static int
4907 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4908 {
4909         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4910         int i, ret;
4911         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4912
4913         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4914         if (ret != I40E_SUCCESS)
4915                 return ret;
4916
4917         if (!vsi->seid) {
4918                 PMD_DRV_LOG(ERR, "seid not valid");
4919                 return -EINVAL;
4920         }
4921
4922         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4923         tc_bw_data.tc_valid_bits = enabled_tcmap;
4924         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4925                 tc_bw_data.tc_bw_credits[i] =
4926                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4927
4928         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4929         if (ret != I40E_SUCCESS) {
4930                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4931                 return ret;
4932         }
4933
4934         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4935                                         sizeof(vsi->info.qs_handle));
4936         return I40E_SUCCESS;
4937 }
4938
4939 static enum i40e_status_code
4940 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4941                                  struct i40e_aqc_vsi_properties_data *info,
4942                                  uint8_t enabled_tcmap)
4943 {
4944         enum i40e_status_code ret;
4945         int i, total_tc = 0;
4946         uint16_t qpnum_per_tc, bsf, qp_idx;
4947
4948         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4949         if (ret != I40E_SUCCESS)
4950                 return ret;
4951
4952         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4953                 if (enabled_tcmap & (1 << i))
4954                         total_tc++;
4955         if (total_tc == 0)
4956                 total_tc = 1;
4957         vsi->enabled_tc = enabled_tcmap;
4958
4959         /* Number of queues per enabled TC */
4960         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4961         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4962         bsf = rte_bsf32(qpnum_per_tc);
4963
4964         /* Adjust the queue number to actual queues that can be applied */
4965         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4966                 vsi->nb_qps = qpnum_per_tc * total_tc;
4967
4968         /**
4969          * Configure TC and queue mapping parameters, for enabled TC,
4970          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4971          * default queue will serve it.
4972          */
4973         qp_idx = 0;
4974         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4975                 if (vsi->enabled_tc & (1 << i)) {
4976                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4977                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4978                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4979                         qp_idx += qpnum_per_tc;
4980                 } else
4981                         info->tc_mapping[i] = 0;
4982         }
4983
4984         /* Associate queue number with VSI */
4985         if (vsi->type == I40E_VSI_SRIOV) {
4986                 info->mapping_flags |=
4987                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4988                 for (i = 0; i < vsi->nb_qps; i++)
4989                         info->queue_mapping[i] =
4990                                 rte_cpu_to_le_16(vsi->base_queue + i);
4991         } else {
4992                 info->mapping_flags |=
4993                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4994                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4995         }
4996         info->valid_sections |=
4997                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4998
4999         return I40E_SUCCESS;
5000 }
5001
5002 static int
5003 i40e_veb_release(struct i40e_veb *veb)
5004 {
5005         struct i40e_vsi *vsi;
5006         struct i40e_hw *hw;
5007
5008         if (veb == NULL)
5009                 return -EINVAL;
5010
5011         if (!TAILQ_EMPTY(&veb->head)) {
5012                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5013                 return -EACCES;
5014         }
5015         /* associate_vsi field is NULL for floating VEB */
5016         if (veb->associate_vsi != NULL) {
5017                 vsi = veb->associate_vsi;
5018                 hw = I40E_VSI_TO_HW(vsi);
5019
5020                 vsi->uplink_seid = veb->uplink_seid;
5021                 vsi->veb = NULL;
5022         } else {
5023                 veb->associate_pf->main_vsi->floating_veb = NULL;
5024                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5025         }
5026
5027         i40e_aq_delete_element(hw, veb->seid, NULL);
5028         rte_free(veb);
5029         return I40E_SUCCESS;
5030 }
5031
5032 /* Setup a veb */
5033 static struct i40e_veb *
5034 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5035 {
5036         struct i40e_veb *veb;
5037         int ret;
5038         struct i40e_hw *hw;
5039
5040         if (pf == NULL) {
5041                 PMD_DRV_LOG(ERR,
5042                             "veb setup failed, associated PF shouldn't null");
5043                 return NULL;
5044         }
5045         hw = I40E_PF_TO_HW(pf);
5046
5047         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5048         if (!veb) {
5049                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5050                 goto fail;
5051         }
5052
5053         veb->associate_vsi = vsi;
5054         veb->associate_pf = pf;
5055         TAILQ_INIT(&veb->head);
5056         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5057
5058         /* create floating veb if vsi is NULL */
5059         if (vsi != NULL) {
5060                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5061                                       I40E_DEFAULT_TCMAP, false,
5062                                       &veb->seid, false, NULL);
5063         } else {
5064                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5065                                       true, &veb->seid, false, NULL);
5066         }
5067
5068         if (ret != I40E_SUCCESS) {
5069                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5070                             hw->aq.asq_last_status);
5071                 goto fail;
5072         }
5073         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5074
5075         /* get statistics index */
5076         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5077                                 &veb->stats_idx, NULL, NULL, NULL);
5078         if (ret != I40E_SUCCESS) {
5079                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5080                             hw->aq.asq_last_status);
5081                 goto fail;
5082         }
5083         /* Get VEB bandwidth, to be implemented */
5084         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5085         if (vsi)
5086                 vsi->uplink_seid = veb->seid;
5087
5088         return veb;
5089 fail:
5090         rte_free(veb);
5091         return NULL;
5092 }
5093
5094 int
5095 i40e_vsi_release(struct i40e_vsi *vsi)
5096 {
5097         struct i40e_pf *pf;
5098         struct i40e_hw *hw;
5099         struct i40e_vsi_list *vsi_list;
5100         void *temp;
5101         int ret;
5102         struct i40e_mac_filter *f;
5103         uint16_t user_param;
5104
5105         if (!vsi)
5106                 return I40E_SUCCESS;
5107
5108         if (!vsi->adapter)
5109                 return -EFAULT;
5110
5111         user_param = vsi->user_param;
5112
5113         pf = I40E_VSI_TO_PF(vsi);
5114         hw = I40E_VSI_TO_HW(vsi);
5115
5116         /* VSI has child to attach, release child first */
5117         if (vsi->veb) {
5118                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5119                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5120                                 return -1;
5121                 }
5122                 i40e_veb_release(vsi->veb);
5123         }
5124
5125         if (vsi->floating_veb) {
5126                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5127                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5128                                 return -1;
5129                 }
5130         }
5131
5132         /* Remove all macvlan filters of the VSI */
5133         i40e_vsi_remove_all_macvlan_filter(vsi);
5134         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5135                 rte_free(f);
5136
5137         if (vsi->type != I40E_VSI_MAIN &&
5138             ((vsi->type != I40E_VSI_SRIOV) ||
5139             !pf->floating_veb_list[user_param])) {
5140                 /* Remove vsi from parent's sibling list */
5141                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5142                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5143                         return I40E_ERR_PARAM;
5144                 }
5145                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5146                                 &vsi->sib_vsi_list, list);
5147
5148                 /* Remove all switch element of the VSI */
5149                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5150                 if (ret != I40E_SUCCESS)
5151                         PMD_DRV_LOG(ERR, "Failed to delete element");
5152         }
5153
5154         if ((vsi->type == I40E_VSI_SRIOV) &&
5155             pf->floating_veb_list[user_param]) {
5156                 /* Remove vsi from parent's sibling list */
5157                 if (vsi->parent_vsi == NULL ||
5158                     vsi->parent_vsi->floating_veb == NULL) {
5159                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5160                         return I40E_ERR_PARAM;
5161                 }
5162                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5163                              &vsi->sib_vsi_list, list);
5164
5165                 /* Remove all switch element of the VSI */
5166                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5167                 if (ret != I40E_SUCCESS)
5168                         PMD_DRV_LOG(ERR, "Failed to delete element");
5169         }
5170
5171         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5172
5173         if (vsi->type != I40E_VSI_SRIOV)
5174                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5175         rte_free(vsi);
5176
5177         return I40E_SUCCESS;
5178 }
5179
5180 static int
5181 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5182 {
5183         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5184         struct i40e_aqc_remove_macvlan_element_data def_filter;
5185         struct i40e_mac_filter_info filter;
5186         int ret;
5187
5188         if (vsi->type != I40E_VSI_MAIN)
5189                 return I40E_ERR_CONFIG;
5190         memset(&def_filter, 0, sizeof(def_filter));
5191         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5192                                         ETH_ADDR_LEN);
5193         def_filter.vlan_tag = 0;
5194         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5195                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5196         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5197         if (ret != I40E_SUCCESS) {
5198                 struct i40e_mac_filter *f;
5199                 struct ether_addr *mac;
5200
5201                 PMD_DRV_LOG(DEBUG,
5202                             "Cannot remove the default macvlan filter");
5203                 /* It needs to add the permanent mac into mac list */
5204                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5205                 if (f == NULL) {
5206                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5207                         return I40E_ERR_NO_MEMORY;
5208                 }
5209                 mac = &f->mac_info.mac_addr;
5210                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5211                                 ETH_ADDR_LEN);
5212                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5213                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5214                 vsi->mac_num++;
5215
5216                 return ret;
5217         }
5218         rte_memcpy(&filter.mac_addr,
5219                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5220         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5221         return i40e_vsi_add_mac(vsi, &filter);
5222 }
5223
5224 /*
5225  * i40e_vsi_get_bw_config - Query VSI BW Information
5226  * @vsi: the VSI to be queried
5227  *
5228  * Returns 0 on success, negative value on failure
5229  */
5230 static enum i40e_status_code
5231 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5232 {
5233         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5234         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5235         struct i40e_hw *hw = &vsi->adapter->hw;
5236         i40e_status ret;
5237         int i;
5238         uint32_t bw_max;
5239
5240         memset(&bw_config, 0, sizeof(bw_config));
5241         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5242         if (ret != I40E_SUCCESS) {
5243                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5244                             hw->aq.asq_last_status);
5245                 return ret;
5246         }
5247
5248         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5249         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5250                                         &ets_sla_config, NULL);
5251         if (ret != I40E_SUCCESS) {
5252                 PMD_DRV_LOG(ERR,
5253                         "VSI failed to get TC bandwdith configuration %u",
5254                         hw->aq.asq_last_status);
5255                 return ret;
5256         }
5257
5258         /* store and print out BW info */
5259         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5260         vsi->bw_info.bw_max = bw_config.max_bw;
5261         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5262         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5263         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5264                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5265                      I40E_16_BIT_WIDTH);
5266         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5267                 vsi->bw_info.bw_ets_share_credits[i] =
5268                                 ets_sla_config.share_credits[i];
5269                 vsi->bw_info.bw_ets_credits[i] =
5270                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5271                 /* 4 bits per TC, 4th bit is reserved */
5272                 vsi->bw_info.bw_ets_max[i] =
5273                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5274                                   RTE_LEN2MASK(3, uint8_t));
5275                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5276                             vsi->bw_info.bw_ets_share_credits[i]);
5277                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5278                             vsi->bw_info.bw_ets_credits[i]);
5279                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5280                             vsi->bw_info.bw_ets_max[i]);
5281         }
5282
5283         return I40E_SUCCESS;
5284 }
5285
5286 /* i40e_enable_pf_lb
5287  * @pf: pointer to the pf structure
5288  *
5289  * allow loopback on pf
5290  */
5291 static inline void
5292 i40e_enable_pf_lb(struct i40e_pf *pf)
5293 {
5294         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5295         struct i40e_vsi_context ctxt;
5296         int ret;
5297
5298         /* Use the FW API if FW >= v5.0 */
5299         if (hw->aq.fw_maj_ver < 5) {
5300                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5301                 return;
5302         }
5303
5304         memset(&ctxt, 0, sizeof(ctxt));
5305         ctxt.seid = pf->main_vsi_seid;
5306         ctxt.pf_num = hw->pf_id;
5307         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5308         if (ret) {
5309                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5310                             ret, hw->aq.asq_last_status);
5311                 return;
5312         }
5313         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5314         ctxt.info.valid_sections =
5315                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5316         ctxt.info.switch_id |=
5317                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5318
5319         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5320         if (ret)
5321                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5322                             hw->aq.asq_last_status);
5323 }
5324
5325 /* Setup a VSI */
5326 struct i40e_vsi *
5327 i40e_vsi_setup(struct i40e_pf *pf,
5328                enum i40e_vsi_type type,
5329                struct i40e_vsi *uplink_vsi,
5330                uint16_t user_param)
5331 {
5332         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5333         struct i40e_vsi *vsi;
5334         struct i40e_mac_filter_info filter;
5335         int ret;
5336         struct i40e_vsi_context ctxt;
5337         struct ether_addr broadcast =
5338                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5339
5340         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5341             uplink_vsi == NULL) {
5342                 PMD_DRV_LOG(ERR,
5343                         "VSI setup failed, VSI link shouldn't be NULL");
5344                 return NULL;
5345         }
5346
5347         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5348                 PMD_DRV_LOG(ERR,
5349                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5350                 return NULL;
5351         }
5352
5353         /* two situations
5354          * 1.type is not MAIN and uplink vsi is not NULL
5355          * If uplink vsi didn't setup VEB, create one first under veb field
5356          * 2.type is SRIOV and the uplink is NULL
5357          * If floating VEB is NULL, create one veb under floating veb field
5358          */
5359
5360         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5361             uplink_vsi->veb == NULL) {
5362                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5363
5364                 if (uplink_vsi->veb == NULL) {
5365                         PMD_DRV_LOG(ERR, "VEB setup failed");
5366                         return NULL;
5367                 }
5368                 /* set ALLOWLOOPBACk on pf, when veb is created */
5369                 i40e_enable_pf_lb(pf);
5370         }
5371
5372         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5373             pf->main_vsi->floating_veb == NULL) {
5374                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5375
5376                 if (pf->main_vsi->floating_veb == NULL) {
5377                         PMD_DRV_LOG(ERR, "VEB setup failed");
5378                         return NULL;
5379                 }
5380         }
5381
5382         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5383         if (!vsi) {
5384                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5385                 return NULL;
5386         }
5387         TAILQ_INIT(&vsi->mac_list);
5388         vsi->type = type;
5389         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5390         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5391         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5392         vsi->user_param = user_param;
5393         vsi->vlan_anti_spoof_on = 0;
5394         vsi->vlan_filter_on = 0;
5395         /* Allocate queues */
5396         switch (vsi->type) {
5397         case I40E_VSI_MAIN  :
5398                 vsi->nb_qps = pf->lan_nb_qps;
5399                 break;
5400         case I40E_VSI_SRIOV :
5401                 vsi->nb_qps = pf->vf_nb_qps;
5402                 break;
5403         case I40E_VSI_VMDQ2:
5404                 vsi->nb_qps = pf->vmdq_nb_qps;
5405                 break;
5406         case I40E_VSI_FDIR:
5407                 vsi->nb_qps = pf->fdir_nb_qps;
5408                 break;
5409         default:
5410                 goto fail_mem;
5411         }
5412         /*
5413          * The filter status descriptor is reported in rx queue 0,
5414          * while the tx queue for fdir filter programming has no
5415          * such constraints, can be non-zero queues.
5416          * To simplify it, choose FDIR vsi use queue 0 pair.
5417          * To make sure it will use queue 0 pair, queue allocation
5418          * need be done before this function is called
5419          */
5420         if (type != I40E_VSI_FDIR) {
5421                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5422                         if (ret < 0) {
5423                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5424                                                 vsi->seid, ret);
5425                                 goto fail_mem;
5426                         }
5427                         vsi->base_queue = ret;
5428         } else
5429                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5430
5431         /* VF has MSIX interrupt in VF range, don't allocate here */
5432         if (type == I40E_VSI_MAIN) {
5433                 if (pf->support_multi_driver) {
5434                         /* If support multi-driver, need to use INT0 instead of
5435                          * allocating from msix pool. The Msix pool is init from
5436                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5437                          * to 1 without calling i40e_res_pool_alloc.
5438                          */
5439                         vsi->msix_intr = 0;
5440                         vsi->nb_msix = 1;
5441                 } else {
5442                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5443                                                   RTE_MIN(vsi->nb_qps,
5444                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5445                         if (ret < 0) {
5446                                 PMD_DRV_LOG(ERR,
5447                                             "VSI MAIN %d get heap failed %d",
5448                                             vsi->seid, ret);
5449                                 goto fail_queue_alloc;
5450                         }
5451                         vsi->msix_intr = ret;
5452                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5453                                                RTE_MAX_RXTX_INTR_VEC_ID);
5454                 }
5455         } else if (type != I40E_VSI_SRIOV) {
5456                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5457                 if (ret < 0) {
5458                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5459                         goto fail_queue_alloc;
5460                 }
5461                 vsi->msix_intr = ret;
5462                 vsi->nb_msix = 1;
5463         } else {
5464                 vsi->msix_intr = 0;
5465                 vsi->nb_msix = 0;
5466         }
5467
5468         /* Add VSI */
5469         if (type == I40E_VSI_MAIN) {
5470                 /* For main VSI, no need to add since it's default one */
5471                 vsi->uplink_seid = pf->mac_seid;
5472                 vsi->seid = pf->main_vsi_seid;
5473                 /* Bind queues with specific MSIX interrupt */
5474                 /**
5475                  * Needs 2 interrupt at least, one for misc cause which will
5476                  * enabled from OS side, Another for queues binding the
5477                  * interrupt from device side only.
5478                  */
5479
5480                 /* Get default VSI parameters from hardware */
5481                 memset(&ctxt, 0, sizeof(ctxt));
5482                 ctxt.seid = vsi->seid;
5483                 ctxt.pf_num = hw->pf_id;
5484                 ctxt.uplink_seid = vsi->uplink_seid;
5485                 ctxt.vf_num = 0;
5486                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5487                 if (ret != I40E_SUCCESS) {
5488                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5489                         goto fail_msix_alloc;
5490                 }
5491                 rte_memcpy(&vsi->info, &ctxt.info,
5492                         sizeof(struct i40e_aqc_vsi_properties_data));
5493                 vsi->vsi_id = ctxt.vsi_number;
5494                 vsi->info.valid_sections = 0;
5495
5496                 /* Configure tc, enabled TC0 only */
5497                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5498                         I40E_SUCCESS) {
5499                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5500                         goto fail_msix_alloc;
5501                 }
5502
5503                 /* TC, queue mapping */
5504                 memset(&ctxt, 0, sizeof(ctxt));
5505                 vsi->info.valid_sections |=
5506                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5507                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5508                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5509                 rte_memcpy(&ctxt.info, &vsi->info,
5510                         sizeof(struct i40e_aqc_vsi_properties_data));
5511                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5512                                                 I40E_DEFAULT_TCMAP);
5513                 if (ret != I40E_SUCCESS) {
5514                         PMD_DRV_LOG(ERR,
5515                                 "Failed to configure TC queue mapping");
5516                         goto fail_msix_alloc;
5517                 }
5518                 ctxt.seid = vsi->seid;
5519                 ctxt.pf_num = hw->pf_id;
5520                 ctxt.uplink_seid = vsi->uplink_seid;
5521                 ctxt.vf_num = 0;
5522
5523                 /* Update VSI parameters */
5524                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5525                 if (ret != I40E_SUCCESS) {
5526                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5527                         goto fail_msix_alloc;
5528                 }
5529
5530                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5531                                                 sizeof(vsi->info.tc_mapping));
5532                 rte_memcpy(&vsi->info.queue_mapping,
5533                                 &ctxt.info.queue_mapping,
5534                         sizeof(vsi->info.queue_mapping));
5535                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5536                 vsi->info.valid_sections = 0;
5537
5538                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5539                                 ETH_ADDR_LEN);
5540
5541                 /**
5542                  * Updating default filter settings are necessary to prevent
5543                  * reception of tagged packets.
5544                  * Some old firmware configurations load a default macvlan
5545                  * filter which accepts both tagged and untagged packets.
5546                  * The updating is to use a normal filter instead if needed.
5547                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5548                  * The firmware with correct configurations load the default
5549                  * macvlan filter which is expected and cannot be removed.
5550                  */
5551                 i40e_update_default_filter_setting(vsi);
5552                 i40e_config_qinq(hw, vsi);
5553         } else if (type == I40E_VSI_SRIOV) {
5554                 memset(&ctxt, 0, sizeof(ctxt));
5555                 /**
5556                  * For other VSI, the uplink_seid equals to uplink VSI's
5557                  * uplink_seid since they share same VEB
5558                  */
5559                 if (uplink_vsi == NULL)
5560                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5561                 else
5562                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5563                 ctxt.pf_num = hw->pf_id;
5564                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5565                 ctxt.uplink_seid = vsi->uplink_seid;
5566                 ctxt.connection_type = 0x1;
5567                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5568
5569                 /* Use the VEB configuration if FW >= v5.0 */
5570                 if (hw->aq.fw_maj_ver >= 5) {
5571                         /* Configure switch ID */
5572                         ctxt.info.valid_sections |=
5573                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5574                         ctxt.info.switch_id =
5575                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5576                 }
5577
5578                 /* Configure port/vlan */
5579                 ctxt.info.valid_sections |=
5580                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5581                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5582                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5583                                                 hw->func_caps.enabled_tcmap);
5584                 if (ret != I40E_SUCCESS) {
5585                         PMD_DRV_LOG(ERR,
5586                                 "Failed to configure TC queue mapping");
5587                         goto fail_msix_alloc;
5588                 }
5589
5590                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5591                 ctxt.info.valid_sections |=
5592                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5593                 /**
5594                  * Since VSI is not created yet, only configure parameter,
5595                  * will add vsi below.
5596                  */
5597
5598                 i40e_config_qinq(hw, vsi);
5599         } else if (type == I40E_VSI_VMDQ2) {
5600                 memset(&ctxt, 0, sizeof(ctxt));
5601                 /*
5602                  * For other VSI, the uplink_seid equals to uplink VSI's
5603                  * uplink_seid since they share same VEB
5604                  */
5605                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5606                 ctxt.pf_num = hw->pf_id;
5607                 ctxt.vf_num = 0;
5608                 ctxt.uplink_seid = vsi->uplink_seid;
5609                 ctxt.connection_type = 0x1;
5610                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5611
5612                 ctxt.info.valid_sections |=
5613                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5614                 /* user_param carries flag to enable loop back */
5615                 if (user_param) {
5616                         ctxt.info.switch_id =
5617                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5618                         ctxt.info.switch_id |=
5619                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5620                 }
5621
5622                 /* Configure port/vlan */
5623                 ctxt.info.valid_sections |=
5624                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5625                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5626                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5627                                                 I40E_DEFAULT_TCMAP);
5628                 if (ret != I40E_SUCCESS) {
5629                         PMD_DRV_LOG(ERR,
5630                                 "Failed to configure TC queue mapping");
5631                         goto fail_msix_alloc;
5632                 }
5633                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5634                 ctxt.info.valid_sections |=
5635                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5636         } else if (type == I40E_VSI_FDIR) {
5637                 memset(&ctxt, 0, sizeof(ctxt));
5638                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5639                 ctxt.pf_num = hw->pf_id;
5640                 ctxt.vf_num = 0;
5641                 ctxt.uplink_seid = vsi->uplink_seid;
5642                 ctxt.connection_type = 0x1;     /* regular data port */
5643                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5644                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5645                                                 I40E_DEFAULT_TCMAP);
5646                 if (ret != I40E_SUCCESS) {
5647                         PMD_DRV_LOG(ERR,
5648                                 "Failed to configure TC queue mapping.");
5649                         goto fail_msix_alloc;
5650                 }
5651                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5652                 ctxt.info.valid_sections |=
5653                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5654         } else {
5655                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5656                 goto fail_msix_alloc;
5657         }
5658
5659         if (vsi->type != I40E_VSI_MAIN) {
5660                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5661                 if (ret != I40E_SUCCESS) {
5662                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5663                                     hw->aq.asq_last_status);
5664                         goto fail_msix_alloc;
5665                 }
5666                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5667                 vsi->info.valid_sections = 0;
5668                 vsi->seid = ctxt.seid;
5669                 vsi->vsi_id = ctxt.vsi_number;
5670                 vsi->sib_vsi_list.vsi = vsi;
5671                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5672                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5673                                           &vsi->sib_vsi_list, list);
5674                 } else {
5675                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5676                                           &vsi->sib_vsi_list, list);
5677                 }
5678         }
5679
5680         /* MAC/VLAN configuration */
5681         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5682         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5683
5684         ret = i40e_vsi_add_mac(vsi, &filter);
5685         if (ret != I40E_SUCCESS) {
5686                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5687                 goto fail_msix_alloc;
5688         }
5689
5690         /* Get VSI BW information */
5691         i40e_vsi_get_bw_config(vsi);
5692         return vsi;
5693 fail_msix_alloc:
5694         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5695 fail_queue_alloc:
5696         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5697 fail_mem:
5698         rte_free(vsi);
5699         return NULL;
5700 }
5701
5702 /* Configure vlan filter on or off */
5703 int
5704 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5705 {
5706         int i, num;
5707         struct i40e_mac_filter *f;
5708         void *temp;
5709         struct i40e_mac_filter_info *mac_filter;
5710         enum rte_mac_filter_type desired_filter;
5711         int ret = I40E_SUCCESS;
5712
5713         if (on) {
5714                 /* Filter to match MAC and VLAN */
5715                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5716         } else {
5717                 /* Filter to match only MAC */
5718                 desired_filter = RTE_MAC_PERFECT_MATCH;
5719         }
5720
5721         num = vsi->mac_num;
5722
5723         mac_filter = rte_zmalloc("mac_filter_info_data",
5724                                  num * sizeof(*mac_filter), 0);
5725         if (mac_filter == NULL) {
5726                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5727                 return I40E_ERR_NO_MEMORY;
5728         }
5729
5730         i = 0;
5731
5732         /* Remove all existing mac */
5733         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5734                 mac_filter[i] = f->mac_info;
5735                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5736                 if (ret) {
5737                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5738                                     on ? "enable" : "disable");
5739                         goto DONE;
5740                 }
5741                 i++;
5742         }
5743
5744         /* Override with new filter */
5745         for (i = 0; i < num; i++) {
5746                 mac_filter[i].filter_type = desired_filter;
5747                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5748                 if (ret) {
5749                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5750                                     on ? "enable" : "disable");
5751                         goto DONE;
5752                 }
5753         }
5754
5755 DONE:
5756         rte_free(mac_filter);
5757         return ret;
5758 }
5759
5760 /* Configure vlan stripping on or off */
5761 int
5762 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5763 {
5764         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5765         struct i40e_vsi_context ctxt;
5766         uint8_t vlan_flags;
5767         int ret = I40E_SUCCESS;
5768
5769         /* Check if it has been already on or off */
5770         if (vsi->info.valid_sections &
5771                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5772                 if (on) {
5773                         if ((vsi->info.port_vlan_flags &
5774                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5775                                 return 0; /* already on */
5776                 } else {
5777                         if ((vsi->info.port_vlan_flags &
5778                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5779                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5780                                 return 0; /* already off */
5781                 }
5782         }
5783
5784         if (on)
5785                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5786         else
5787                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5788         vsi->info.valid_sections =
5789                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5790         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5791         vsi->info.port_vlan_flags |= vlan_flags;
5792         ctxt.seid = vsi->seid;
5793         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5794         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5795         if (ret)
5796                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5797                             on ? "enable" : "disable");
5798
5799         return ret;
5800 }
5801
5802 static int
5803 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5804 {
5805         struct rte_eth_dev_data *data = dev->data;
5806         int ret;
5807         int mask = 0;
5808
5809         /* Apply vlan offload setting */
5810         mask = ETH_VLAN_STRIP_MASK |
5811                ETH_VLAN_FILTER_MASK |
5812                ETH_VLAN_EXTEND_MASK;
5813         ret = i40e_vlan_offload_set(dev, mask);
5814         if (ret) {
5815                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5816                 return ret;
5817         }
5818
5819         /* Apply pvid setting */
5820         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5821                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5822         if (ret)
5823                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5824
5825         return ret;
5826 }
5827
5828 static int
5829 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5830 {
5831         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5832
5833         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5834 }
5835
5836 static int
5837 i40e_update_flow_control(struct i40e_hw *hw)
5838 {
5839 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5840         struct i40e_link_status link_status;
5841         uint32_t rxfc = 0, txfc = 0, reg;
5842         uint8_t an_info;
5843         int ret;
5844
5845         memset(&link_status, 0, sizeof(link_status));
5846         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5847         if (ret != I40E_SUCCESS) {
5848                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5849                 goto write_reg; /* Disable flow control */
5850         }
5851
5852         an_info = hw->phy.link_info.an_info;
5853         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5854                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5855                 ret = I40E_ERR_NOT_READY;
5856                 goto write_reg; /* Disable flow control */
5857         }
5858         /**
5859          * If link auto negotiation is enabled, flow control needs to
5860          * be configured according to it
5861          */
5862         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5863         case I40E_LINK_PAUSE_RXTX:
5864                 rxfc = 1;
5865                 txfc = 1;
5866                 hw->fc.current_mode = I40E_FC_FULL;
5867                 break;
5868         case I40E_AQ_LINK_PAUSE_RX:
5869                 rxfc = 1;
5870                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5871                 break;
5872         case I40E_AQ_LINK_PAUSE_TX:
5873                 txfc = 1;
5874                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5875                 break;
5876         default:
5877                 hw->fc.current_mode = I40E_FC_NONE;
5878                 break;
5879         }
5880
5881 write_reg:
5882         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5883                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5884         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5885         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5886         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5887         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5888
5889         return ret;
5890 }
5891
5892 /* PF setup */
5893 static int
5894 i40e_pf_setup(struct i40e_pf *pf)
5895 {
5896         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5897         struct i40e_filter_control_settings settings;
5898         struct i40e_vsi *vsi;
5899         int ret;
5900
5901         /* Clear all stats counters */
5902         pf->offset_loaded = FALSE;
5903         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5904         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5905         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5906         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5907
5908         ret = i40e_pf_get_switch_config(pf);
5909         if (ret != I40E_SUCCESS) {
5910                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5911                 return ret;
5912         }
5913
5914         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
5915         if (ret)
5916                 PMD_INIT_LOG(WARNING,
5917                         "failed to allocate switch domain for device %d", ret);
5918
5919         if (pf->flags & I40E_FLAG_FDIR) {
5920                 /* make queue allocated first, let FDIR use queue pair 0*/
5921                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5922                 if (ret != I40E_FDIR_QUEUE_ID) {
5923                         PMD_DRV_LOG(ERR,
5924                                 "queue allocation fails for FDIR: ret =%d",
5925                                 ret);
5926                         pf->flags &= ~I40E_FLAG_FDIR;
5927                 }
5928         }
5929         /*  main VSI setup */
5930         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5931         if (!vsi) {
5932                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5933                 return I40E_ERR_NOT_READY;
5934         }
5935         pf->main_vsi = vsi;
5936
5937         /* Configure filter control */
5938         memset(&settings, 0, sizeof(settings));
5939         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5940                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5941         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5942                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5943         else {
5944                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5945                         hw->func_caps.rss_table_size);
5946                 return I40E_ERR_PARAM;
5947         }
5948         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5949                 hw->func_caps.rss_table_size);
5950         pf->hash_lut_size = hw->func_caps.rss_table_size;
5951
5952         /* Enable ethtype and macvlan filters */
5953         settings.enable_ethtype = TRUE;
5954         settings.enable_macvlan = TRUE;
5955         ret = i40e_set_filter_control(hw, &settings);
5956         if (ret)
5957                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5958                                                                 ret);
5959
5960         /* Update flow control according to the auto negotiation */
5961         i40e_update_flow_control(hw);
5962
5963         return I40E_SUCCESS;
5964 }
5965
5966 int
5967 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5968 {
5969         uint32_t reg;
5970         uint16_t j;
5971
5972         /**
5973          * Set or clear TX Queue Disable flags,
5974          * which is required by hardware.
5975          */
5976         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5977         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5978
5979         /* Wait until the request is finished */
5980         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5981                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5982                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5983                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5984                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5985                                                         & 0x1))) {
5986                         break;
5987                 }
5988         }
5989         if (on) {
5990                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5991                         return I40E_SUCCESS; /* already on, skip next steps */
5992
5993                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5994                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5995         } else {
5996                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5997                         return I40E_SUCCESS; /* already off, skip next steps */
5998                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5999         }
6000         /* Write the register */
6001         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6002         /* Check the result */
6003         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6004                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6005                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6006                 if (on) {
6007                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6008                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6009                                 break;
6010                 } else {
6011                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6012                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6013                                 break;
6014                 }
6015         }
6016         /* Check if it is timeout */
6017         if (j >= I40E_CHK_Q_ENA_COUNT) {
6018                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6019                             (on ? "enable" : "disable"), q_idx);
6020                 return I40E_ERR_TIMEOUT;
6021         }
6022
6023         return I40E_SUCCESS;
6024 }
6025
6026 /* Swith on or off the tx queues */
6027 static int
6028 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6029 {
6030         struct rte_eth_dev_data *dev_data = pf->dev_data;
6031         struct i40e_tx_queue *txq;
6032         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6033         uint16_t i;
6034         int ret;
6035
6036         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6037                 txq = dev_data->tx_queues[i];
6038                 /* Don't operate the queue if not configured or
6039                  * if starting only per queue */
6040                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6041                         continue;
6042                 if (on)
6043                         ret = i40e_dev_tx_queue_start(dev, i);
6044                 else
6045                         ret = i40e_dev_tx_queue_stop(dev, i);
6046                 if ( ret != I40E_SUCCESS)
6047                         return ret;
6048         }
6049
6050         return I40E_SUCCESS;
6051 }
6052
6053 int
6054 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6055 {
6056         uint32_t reg;
6057         uint16_t j;
6058
6059         /* Wait until the request is finished */
6060         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6061                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6062                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6063                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6064                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6065                         break;
6066         }
6067
6068         if (on) {
6069                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6070                         return I40E_SUCCESS; /* Already on, skip next steps */
6071                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6072         } else {
6073                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6074                         return I40E_SUCCESS; /* Already off, skip next steps */
6075                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6076         }
6077
6078         /* Write the register */
6079         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6080         /* Check the result */
6081         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6082                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6083                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6084                 if (on) {
6085                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6086                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6087                                 break;
6088                 } else {
6089                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6090                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6091                                 break;
6092                 }
6093         }
6094
6095         /* Check if it is timeout */
6096         if (j >= I40E_CHK_Q_ENA_COUNT) {
6097                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6098                             (on ? "enable" : "disable"), q_idx);
6099                 return I40E_ERR_TIMEOUT;
6100         }
6101
6102         return I40E_SUCCESS;
6103 }
6104 /* Switch on or off the rx queues */
6105 static int
6106 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6107 {
6108         struct rte_eth_dev_data *dev_data = pf->dev_data;
6109         struct i40e_rx_queue *rxq;
6110         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6111         uint16_t i;
6112         int ret;
6113
6114         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6115                 rxq = dev_data->rx_queues[i];
6116                 /* Don't operate the queue if not configured or
6117                  * if starting only per queue */
6118                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6119                         continue;
6120                 if (on)
6121                         ret = i40e_dev_rx_queue_start(dev, i);
6122                 else
6123                         ret = i40e_dev_rx_queue_stop(dev, i);
6124                 if (ret != I40E_SUCCESS)
6125                         return ret;
6126         }
6127
6128         return I40E_SUCCESS;
6129 }
6130
6131 /* Switch on or off all the rx/tx queues */
6132 int
6133 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6134 {
6135         int ret;
6136
6137         if (on) {
6138                 /* enable rx queues before enabling tx queues */
6139                 ret = i40e_dev_switch_rx_queues(pf, on);
6140                 if (ret) {
6141                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6142                         return ret;
6143                 }
6144                 ret = i40e_dev_switch_tx_queues(pf, on);
6145         } else {
6146                 /* Stop tx queues before stopping rx queues */
6147                 ret = i40e_dev_switch_tx_queues(pf, on);
6148                 if (ret) {
6149                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6150                         return ret;
6151                 }
6152                 ret = i40e_dev_switch_rx_queues(pf, on);
6153         }
6154
6155         return ret;
6156 }
6157
6158 /* Initialize VSI for TX */
6159 static int
6160 i40e_dev_tx_init(struct i40e_pf *pf)
6161 {
6162         struct rte_eth_dev_data *data = pf->dev_data;
6163         uint16_t i;
6164         uint32_t ret = I40E_SUCCESS;
6165         struct i40e_tx_queue *txq;
6166
6167         for (i = 0; i < data->nb_tx_queues; i++) {
6168                 txq = data->tx_queues[i];
6169                 if (!txq || !txq->q_set)
6170                         continue;
6171                 ret = i40e_tx_queue_init(txq);
6172                 if (ret != I40E_SUCCESS)
6173                         break;
6174         }
6175         if (ret == I40E_SUCCESS)
6176                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6177                                      ->eth_dev);
6178
6179         return ret;
6180 }
6181
6182 /* Initialize VSI for RX */
6183 static int
6184 i40e_dev_rx_init(struct i40e_pf *pf)
6185 {
6186         struct rte_eth_dev_data *data = pf->dev_data;
6187         int ret = I40E_SUCCESS;
6188         uint16_t i;
6189         struct i40e_rx_queue *rxq;
6190
6191         i40e_pf_config_mq_rx(pf);
6192         for (i = 0; i < data->nb_rx_queues; i++) {
6193                 rxq = data->rx_queues[i];
6194                 if (!rxq || !rxq->q_set)
6195                         continue;
6196
6197                 ret = i40e_rx_queue_init(rxq);
6198                 if (ret != I40E_SUCCESS) {
6199                         PMD_DRV_LOG(ERR,
6200                                 "Failed to do RX queue initialization");
6201                         break;
6202                 }
6203         }
6204         if (ret == I40E_SUCCESS)
6205                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6206                                      ->eth_dev);
6207
6208         return ret;
6209 }
6210
6211 static int
6212 i40e_dev_rxtx_init(struct i40e_pf *pf)
6213 {
6214         int err;
6215
6216         err = i40e_dev_tx_init(pf);
6217         if (err) {
6218                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6219                 return err;
6220         }
6221         err = i40e_dev_rx_init(pf);
6222         if (err) {
6223                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6224                 return err;
6225         }
6226
6227         return err;
6228 }
6229
6230 static int
6231 i40e_vmdq_setup(struct rte_eth_dev *dev)
6232 {
6233         struct rte_eth_conf *conf = &dev->data->dev_conf;
6234         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6235         int i, err, conf_vsis, j, loop;
6236         struct i40e_vsi *vsi;
6237         struct i40e_vmdq_info *vmdq_info;
6238         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6239         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6240
6241         /*
6242          * Disable interrupt to avoid message from VF. Furthermore, it will
6243          * avoid race condition in VSI creation/destroy.
6244          */
6245         i40e_pf_disable_irq0(hw);
6246
6247         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6248                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6249                 return -ENOTSUP;
6250         }
6251
6252         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6253         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6254                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6255                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6256                         pf->max_nb_vmdq_vsi);
6257                 return -ENOTSUP;
6258         }
6259
6260         if (pf->vmdq != NULL) {
6261                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6262                 return 0;
6263         }
6264
6265         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6266                                 sizeof(*vmdq_info) * conf_vsis, 0);
6267
6268         if (pf->vmdq == NULL) {
6269                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6270                 return -ENOMEM;
6271         }
6272
6273         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6274
6275         /* Create VMDQ VSI */
6276         for (i = 0; i < conf_vsis; i++) {
6277                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6278                                 vmdq_conf->enable_loop_back);
6279                 if (vsi == NULL) {
6280                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6281                         err = -1;
6282                         goto err_vsi_setup;
6283                 }
6284                 vmdq_info = &pf->vmdq[i];
6285                 vmdq_info->pf = pf;
6286                 vmdq_info->vsi = vsi;
6287         }
6288         pf->nb_cfg_vmdq_vsi = conf_vsis;
6289
6290         /* Configure Vlan */
6291         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6292         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6293                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6294                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6295                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6296                                         vmdq_conf->pool_map[i].vlan_id, j);
6297
6298                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6299                                                 vmdq_conf->pool_map[i].vlan_id);
6300                                 if (err) {
6301                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6302                                         err = -1;
6303                                         goto err_vsi_setup;
6304                                 }
6305                         }
6306                 }
6307         }
6308
6309         i40e_pf_enable_irq0(hw);
6310
6311         return 0;
6312
6313 err_vsi_setup:
6314         for (i = 0; i < conf_vsis; i++)
6315                 if (pf->vmdq[i].vsi == NULL)
6316                         break;
6317                 else
6318                         i40e_vsi_release(pf->vmdq[i].vsi);
6319
6320         rte_free(pf->vmdq);
6321         pf->vmdq = NULL;
6322         i40e_pf_enable_irq0(hw);
6323         return err;
6324 }
6325
6326 static void
6327 i40e_stat_update_32(struct i40e_hw *hw,
6328                    uint32_t reg,
6329                    bool offset_loaded,
6330                    uint64_t *offset,
6331                    uint64_t *stat)
6332 {
6333         uint64_t new_data;
6334
6335         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6336         if (!offset_loaded)
6337                 *offset = new_data;
6338
6339         if (new_data >= *offset)
6340                 *stat = (uint64_t)(new_data - *offset);
6341         else
6342                 *stat = (uint64_t)((new_data +
6343                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6344 }
6345
6346 static void
6347 i40e_stat_update_48(struct i40e_hw *hw,
6348                    uint32_t hireg,
6349                    uint32_t loreg,
6350                    bool offset_loaded,
6351                    uint64_t *offset,
6352                    uint64_t *stat)
6353 {
6354         uint64_t new_data;
6355
6356         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6357         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6358                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6359
6360         if (!offset_loaded)
6361                 *offset = new_data;
6362
6363         if (new_data >= *offset)
6364                 *stat = new_data - *offset;
6365         else
6366                 *stat = (uint64_t)((new_data +
6367                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6368
6369         *stat &= I40E_48_BIT_MASK;
6370 }
6371
6372 /* Disable IRQ0 */
6373 void
6374 i40e_pf_disable_irq0(struct i40e_hw *hw)
6375 {
6376         /* Disable all interrupt types */
6377         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6378                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6379         I40E_WRITE_FLUSH(hw);
6380 }
6381
6382 /* Enable IRQ0 */
6383 void
6384 i40e_pf_enable_irq0(struct i40e_hw *hw)
6385 {
6386         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6387                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6388                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6389                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6390         I40E_WRITE_FLUSH(hw);
6391 }
6392
6393 static void
6394 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6395 {
6396         /* read pending request and disable first */
6397         i40e_pf_disable_irq0(hw);
6398         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6399         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6400                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6401
6402         if (no_queue)
6403                 /* Link no queues with irq0 */
6404                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6405                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6406 }
6407
6408 static void
6409 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6410 {
6411         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6412         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6413         int i;
6414         uint16_t abs_vf_id;
6415         uint32_t index, offset, val;
6416
6417         if (!pf->vfs)
6418                 return;
6419         /**
6420          * Try to find which VF trigger a reset, use absolute VF id to access
6421          * since the reg is global register.
6422          */
6423         for (i = 0; i < pf->vf_num; i++) {
6424                 abs_vf_id = hw->func_caps.vf_base_id + i;
6425                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6426                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6427                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6428                 /* VFR event occurred */
6429                 if (val & (0x1 << offset)) {
6430                         int ret;
6431
6432                         /* Clear the event first */
6433                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6434                                                         (0x1 << offset));
6435                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6436                         /**
6437                          * Only notify a VF reset event occurred,
6438                          * don't trigger another SW reset
6439                          */
6440                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6441                         if (ret != I40E_SUCCESS)
6442                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6443                 }
6444         }
6445 }
6446
6447 static void
6448 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6449 {
6450         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6451         int i;
6452
6453         for (i = 0; i < pf->vf_num; i++)
6454                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6455 }
6456
6457 static void
6458 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6459 {
6460         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6461         struct i40e_arq_event_info info;
6462         uint16_t pending, opcode;
6463         int ret;
6464
6465         info.buf_len = I40E_AQ_BUF_SZ;
6466         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6467         if (!info.msg_buf) {
6468                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6469                 return;
6470         }
6471
6472         pending = 1;
6473         while (pending) {
6474                 ret = i40e_clean_arq_element(hw, &info, &pending);
6475
6476                 if (ret != I40E_SUCCESS) {
6477                         PMD_DRV_LOG(INFO,
6478                                 "Failed to read msg from AdminQ, aq_err: %u",
6479                                 hw->aq.asq_last_status);
6480                         break;
6481                 }
6482                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6483
6484                 switch (opcode) {
6485                 case i40e_aqc_opc_send_msg_to_pf:
6486                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6487                         i40e_pf_host_handle_vf_msg(dev,
6488                                         rte_le_to_cpu_16(info.desc.retval),
6489                                         rte_le_to_cpu_32(info.desc.cookie_high),
6490                                         rte_le_to_cpu_32(info.desc.cookie_low),
6491                                         info.msg_buf,
6492                                         info.msg_len);
6493                         break;
6494                 case i40e_aqc_opc_get_link_status:
6495                         ret = i40e_dev_link_update(dev, 0);
6496                         if (!ret)
6497                                 _rte_eth_dev_callback_process(dev,
6498                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6499                         break;
6500                 default:
6501                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6502                                     opcode);
6503                         break;
6504                 }
6505         }
6506         rte_free(info.msg_buf);
6507 }
6508
6509 /**
6510  * Interrupt handler triggered by NIC  for handling
6511  * specific interrupt.
6512  *
6513  * @param handle
6514  *  Pointer to interrupt handle.
6515  * @param param
6516  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6517  *
6518  * @return
6519  *  void
6520  */
6521 static void
6522 i40e_dev_interrupt_handler(void *param)
6523 {
6524         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6525         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6526         uint32_t icr0;
6527
6528         /* Disable interrupt */
6529         i40e_pf_disable_irq0(hw);
6530
6531         /* read out interrupt causes */
6532         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6533
6534         /* No interrupt event indicated */
6535         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6536                 PMD_DRV_LOG(INFO, "No interrupt event");
6537                 goto done;
6538         }
6539         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6540                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6541         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6542                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6543         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6544                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6545         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6546                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6547         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6548                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6549         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6550                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6551         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6552                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6553
6554         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6555                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6556                 i40e_dev_handle_vfr_event(dev);
6557         }
6558         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6559                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6560                 i40e_dev_handle_aq_msg(dev);
6561         }
6562
6563 done:
6564         /* Enable interrupt */
6565         i40e_pf_enable_irq0(hw);
6566         rte_intr_enable(dev->intr_handle);
6567 }
6568
6569 static void
6570 i40e_dev_alarm_handler(void *param)
6571 {
6572         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6573         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6574         uint32_t icr0;
6575
6576         /* Disable interrupt */
6577         i40e_pf_disable_irq0(hw);
6578
6579         /* read out interrupt causes */
6580         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6581
6582         /* No interrupt event indicated */
6583         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6584                 PMD_DRV_LOG(INFO, "No interrupt event");
6585                 goto done;
6586         }
6587         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6588                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6589         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6590                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6591         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6592                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6593         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6594                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6595         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6596                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6597         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6598                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6599         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6600                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6601
6602         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6603                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6604                 i40e_dev_handle_vfr_event(dev);
6605         }
6606         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6607                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6608                 i40e_dev_handle_aq_msg(dev);
6609         }
6610
6611 done:
6612         /* Enable interrupt */
6613         i40e_pf_enable_irq0(hw);
6614         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6615                           i40e_dev_alarm_handler, dev);
6616 }
6617
6618 int
6619 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6620                          struct i40e_macvlan_filter *filter,
6621                          int total)
6622 {
6623         int ele_num, ele_buff_size;
6624         int num, actual_num, i;
6625         uint16_t flags;
6626         int ret = I40E_SUCCESS;
6627         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6628         struct i40e_aqc_add_macvlan_element_data *req_list;
6629
6630         if (filter == NULL  || total == 0)
6631                 return I40E_ERR_PARAM;
6632         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6633         ele_buff_size = hw->aq.asq_buf_size;
6634
6635         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6636         if (req_list == NULL) {
6637                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6638                 return I40E_ERR_NO_MEMORY;
6639         }
6640
6641         num = 0;
6642         do {
6643                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6644                 memset(req_list, 0, ele_buff_size);
6645
6646                 for (i = 0; i < actual_num; i++) {
6647                         rte_memcpy(req_list[i].mac_addr,
6648                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6649                         req_list[i].vlan_tag =
6650                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6651
6652                         switch (filter[num + i].filter_type) {
6653                         case RTE_MAC_PERFECT_MATCH:
6654                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6655                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6656                                 break;
6657                         case RTE_MACVLAN_PERFECT_MATCH:
6658                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6659                                 break;
6660                         case RTE_MAC_HASH_MATCH:
6661                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6662                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6663                                 break;
6664                         case RTE_MACVLAN_HASH_MATCH:
6665                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6666                                 break;
6667                         default:
6668                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6669                                 ret = I40E_ERR_PARAM;
6670                                 goto DONE;
6671                         }
6672
6673                         req_list[i].queue_number = 0;
6674
6675                         req_list[i].flags = rte_cpu_to_le_16(flags);
6676                 }
6677
6678                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6679                                                 actual_num, NULL);
6680                 if (ret != I40E_SUCCESS) {
6681                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6682                         goto DONE;
6683                 }
6684                 num += actual_num;
6685         } while (num < total);
6686
6687 DONE:
6688         rte_free(req_list);
6689         return ret;
6690 }
6691
6692 int
6693 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6694                             struct i40e_macvlan_filter *filter,
6695                             int total)
6696 {
6697         int ele_num, ele_buff_size;
6698         int num, actual_num, i;
6699         uint16_t flags;
6700         int ret = I40E_SUCCESS;
6701         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6702         struct i40e_aqc_remove_macvlan_element_data *req_list;
6703
6704         if (filter == NULL  || total == 0)
6705                 return I40E_ERR_PARAM;
6706
6707         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6708         ele_buff_size = hw->aq.asq_buf_size;
6709
6710         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6711         if (req_list == NULL) {
6712                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6713                 return I40E_ERR_NO_MEMORY;
6714         }
6715
6716         num = 0;
6717         do {
6718                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6719                 memset(req_list, 0, ele_buff_size);
6720
6721                 for (i = 0; i < actual_num; i++) {
6722                         rte_memcpy(req_list[i].mac_addr,
6723                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6724                         req_list[i].vlan_tag =
6725                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6726
6727                         switch (filter[num + i].filter_type) {
6728                         case RTE_MAC_PERFECT_MATCH:
6729                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6730                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6731                                 break;
6732                         case RTE_MACVLAN_PERFECT_MATCH:
6733                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6734                                 break;
6735                         case RTE_MAC_HASH_MATCH:
6736                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6737                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6738                                 break;
6739                         case RTE_MACVLAN_HASH_MATCH:
6740                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6741                                 break;
6742                         default:
6743                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6744                                 ret = I40E_ERR_PARAM;
6745                                 goto DONE;
6746                         }
6747                         req_list[i].flags = rte_cpu_to_le_16(flags);
6748                 }
6749
6750                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6751                                                 actual_num, NULL);
6752                 if (ret != I40E_SUCCESS) {
6753                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6754                         goto DONE;
6755                 }
6756                 num += actual_num;
6757         } while (num < total);
6758
6759 DONE:
6760         rte_free(req_list);
6761         return ret;
6762 }
6763
6764 /* Find out specific MAC filter */
6765 static struct i40e_mac_filter *
6766 i40e_find_mac_filter(struct i40e_vsi *vsi,
6767                          struct ether_addr *macaddr)
6768 {
6769         struct i40e_mac_filter *f;
6770
6771         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6772                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6773                         return f;
6774         }
6775
6776         return NULL;
6777 }
6778
6779 static bool
6780 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6781                          uint16_t vlan_id)
6782 {
6783         uint32_t vid_idx, vid_bit;
6784
6785         if (vlan_id > ETH_VLAN_ID_MAX)
6786                 return 0;
6787
6788         vid_idx = I40E_VFTA_IDX(vlan_id);
6789         vid_bit = I40E_VFTA_BIT(vlan_id);
6790
6791         if (vsi->vfta[vid_idx] & vid_bit)
6792                 return 1;
6793         else
6794                 return 0;
6795 }
6796
6797 static void
6798 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6799                        uint16_t vlan_id, bool on)
6800 {
6801         uint32_t vid_idx, vid_bit;
6802
6803         vid_idx = I40E_VFTA_IDX(vlan_id);
6804         vid_bit = I40E_VFTA_BIT(vlan_id);
6805
6806         if (on)
6807                 vsi->vfta[vid_idx] |= vid_bit;
6808         else
6809                 vsi->vfta[vid_idx] &= ~vid_bit;
6810 }
6811
6812 void
6813 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6814                      uint16_t vlan_id, bool on)
6815 {
6816         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6817         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6818         int ret;
6819
6820         if (vlan_id > ETH_VLAN_ID_MAX)
6821                 return;
6822
6823         i40e_store_vlan_filter(vsi, vlan_id, on);
6824
6825         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6826                 return;
6827
6828         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6829
6830         if (on) {
6831                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6832                                        &vlan_data, 1, NULL);
6833                 if (ret != I40E_SUCCESS)
6834                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6835         } else {
6836                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6837                                           &vlan_data, 1, NULL);
6838                 if (ret != I40E_SUCCESS)
6839                         PMD_DRV_LOG(ERR,
6840                                     "Failed to remove vlan filter");
6841         }
6842 }
6843
6844 /**
6845  * Find all vlan options for specific mac addr,
6846  * return with actual vlan found.
6847  */
6848 int
6849 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6850                            struct i40e_macvlan_filter *mv_f,
6851                            int num, struct ether_addr *addr)
6852 {
6853         int i;
6854         uint32_t j, k;
6855
6856         /**
6857          * Not to use i40e_find_vlan_filter to decrease the loop time,
6858          * although the code looks complex.
6859           */
6860         if (num < vsi->vlan_num)
6861                 return I40E_ERR_PARAM;
6862
6863         i = 0;
6864         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6865                 if (vsi->vfta[j]) {
6866                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6867                                 if (vsi->vfta[j] & (1 << k)) {
6868                                         if (i > num - 1) {
6869                                                 PMD_DRV_LOG(ERR,
6870                                                         "vlan number doesn't match");
6871                                                 return I40E_ERR_PARAM;
6872                                         }
6873                                         rte_memcpy(&mv_f[i].macaddr,
6874                                                         addr, ETH_ADDR_LEN);
6875                                         mv_f[i].vlan_id =
6876                                                 j * I40E_UINT32_BIT_SIZE + k;
6877                                         i++;
6878                                 }
6879                         }
6880                 }
6881         }
6882         return I40E_SUCCESS;
6883 }
6884
6885 static inline int
6886 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6887                            struct i40e_macvlan_filter *mv_f,
6888                            int num,
6889                            uint16_t vlan)
6890 {
6891         int i = 0;
6892         struct i40e_mac_filter *f;
6893
6894         if (num < vsi->mac_num)
6895                 return I40E_ERR_PARAM;
6896
6897         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6898                 if (i > num - 1) {
6899                         PMD_DRV_LOG(ERR, "buffer number not match");
6900                         return I40E_ERR_PARAM;
6901                 }
6902                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6903                                 ETH_ADDR_LEN);
6904                 mv_f[i].vlan_id = vlan;
6905                 mv_f[i].filter_type = f->mac_info.filter_type;
6906                 i++;
6907         }
6908
6909         return I40E_SUCCESS;
6910 }
6911
6912 static int
6913 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6914 {
6915         int i, j, num;
6916         struct i40e_mac_filter *f;
6917         struct i40e_macvlan_filter *mv_f;
6918         int ret = I40E_SUCCESS;
6919
6920         if (vsi == NULL || vsi->mac_num == 0)
6921                 return I40E_ERR_PARAM;
6922
6923         /* Case that no vlan is set */
6924         if (vsi->vlan_num == 0)
6925                 num = vsi->mac_num;
6926         else
6927                 num = vsi->mac_num * vsi->vlan_num;
6928
6929         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6930         if (mv_f == NULL) {
6931                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6932                 return I40E_ERR_NO_MEMORY;
6933         }
6934
6935         i = 0;
6936         if (vsi->vlan_num == 0) {
6937                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6938                         rte_memcpy(&mv_f[i].macaddr,
6939                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6940                         mv_f[i].filter_type = f->mac_info.filter_type;
6941                         mv_f[i].vlan_id = 0;
6942                         i++;
6943                 }
6944         } else {
6945                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6946                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6947                                         vsi->vlan_num, &f->mac_info.mac_addr);
6948                         if (ret != I40E_SUCCESS)
6949                                 goto DONE;
6950                         for (j = i; j < i + vsi->vlan_num; j++)
6951                                 mv_f[j].filter_type = f->mac_info.filter_type;
6952                         i += vsi->vlan_num;
6953                 }
6954         }
6955
6956         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6957 DONE:
6958         rte_free(mv_f);
6959
6960         return ret;
6961 }
6962
6963 int
6964 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6965 {
6966         struct i40e_macvlan_filter *mv_f;
6967         int mac_num;
6968         int ret = I40E_SUCCESS;
6969
6970         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6971                 return I40E_ERR_PARAM;
6972
6973         /* If it's already set, just return */
6974         if (i40e_find_vlan_filter(vsi,vlan))
6975                 return I40E_SUCCESS;
6976
6977         mac_num = vsi->mac_num;
6978
6979         if (mac_num == 0) {
6980                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6981                 return I40E_ERR_PARAM;
6982         }
6983
6984         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6985
6986         if (mv_f == NULL) {
6987                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6988                 return I40E_ERR_NO_MEMORY;
6989         }
6990
6991         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6992
6993         if (ret != I40E_SUCCESS)
6994                 goto DONE;
6995
6996         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6997
6998         if (ret != I40E_SUCCESS)
6999                 goto DONE;
7000
7001         i40e_set_vlan_filter(vsi, vlan, 1);
7002
7003         vsi->vlan_num++;
7004         ret = I40E_SUCCESS;
7005 DONE:
7006         rte_free(mv_f);
7007         return ret;
7008 }
7009
7010 int
7011 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7012 {
7013         struct i40e_macvlan_filter *mv_f;
7014         int mac_num;
7015         int ret = I40E_SUCCESS;
7016
7017         /**
7018          * Vlan 0 is the generic filter for untagged packets
7019          * and can't be removed.
7020          */
7021         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
7022                 return I40E_ERR_PARAM;
7023
7024         /* If can't find it, just return */
7025         if (!i40e_find_vlan_filter(vsi, vlan))
7026                 return I40E_ERR_PARAM;
7027
7028         mac_num = vsi->mac_num;
7029
7030         if (mac_num == 0) {
7031                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7032                 return I40E_ERR_PARAM;
7033         }
7034
7035         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7036
7037         if (mv_f == NULL) {
7038                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7039                 return I40E_ERR_NO_MEMORY;
7040         }
7041
7042         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7043
7044         if (ret != I40E_SUCCESS)
7045                 goto DONE;
7046
7047         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7048
7049         if (ret != I40E_SUCCESS)
7050                 goto DONE;
7051
7052         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7053         if (vsi->vlan_num == 1) {
7054                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7055                 if (ret != I40E_SUCCESS)
7056                         goto DONE;
7057
7058                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7059                 if (ret != I40E_SUCCESS)
7060                         goto DONE;
7061         }
7062
7063         i40e_set_vlan_filter(vsi, vlan, 0);
7064
7065         vsi->vlan_num--;
7066         ret = I40E_SUCCESS;
7067 DONE:
7068         rte_free(mv_f);
7069         return ret;
7070 }
7071
7072 int
7073 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7074 {
7075         struct i40e_mac_filter *f;
7076         struct i40e_macvlan_filter *mv_f;
7077         int i, vlan_num = 0;
7078         int ret = I40E_SUCCESS;
7079
7080         /* If it's add and we've config it, return */
7081         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7082         if (f != NULL)
7083                 return I40E_SUCCESS;
7084         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7085                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7086
7087                 /**
7088                  * If vlan_num is 0, that's the first time to add mac,
7089                  * set mask for vlan_id 0.
7090                  */
7091                 if (vsi->vlan_num == 0) {
7092                         i40e_set_vlan_filter(vsi, 0, 1);
7093                         vsi->vlan_num = 1;
7094                 }
7095                 vlan_num = vsi->vlan_num;
7096         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7097                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7098                 vlan_num = 1;
7099
7100         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7101         if (mv_f == NULL) {
7102                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7103                 return I40E_ERR_NO_MEMORY;
7104         }
7105
7106         for (i = 0; i < vlan_num; i++) {
7107                 mv_f[i].filter_type = mac_filter->filter_type;
7108                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7109                                 ETH_ADDR_LEN);
7110         }
7111
7112         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7113                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7114                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7115                                         &mac_filter->mac_addr);
7116                 if (ret != I40E_SUCCESS)
7117                         goto DONE;
7118         }
7119
7120         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7121         if (ret != I40E_SUCCESS)
7122                 goto DONE;
7123
7124         /* Add the mac addr into mac list */
7125         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7126         if (f == NULL) {
7127                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7128                 ret = I40E_ERR_NO_MEMORY;
7129                 goto DONE;
7130         }
7131         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7132                         ETH_ADDR_LEN);
7133         f->mac_info.filter_type = mac_filter->filter_type;
7134         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7135         vsi->mac_num++;
7136
7137         ret = I40E_SUCCESS;
7138 DONE:
7139         rte_free(mv_f);
7140
7141         return ret;
7142 }
7143
7144 int
7145 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7146 {
7147         struct i40e_mac_filter *f;
7148         struct i40e_macvlan_filter *mv_f;
7149         int i, vlan_num;
7150         enum rte_mac_filter_type filter_type;
7151         int ret = I40E_SUCCESS;
7152
7153         /* Can't find it, return an error */
7154         f = i40e_find_mac_filter(vsi, addr);
7155         if (f == NULL)
7156                 return I40E_ERR_PARAM;
7157
7158         vlan_num = vsi->vlan_num;
7159         filter_type = f->mac_info.filter_type;
7160         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7161                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7162                 if (vlan_num == 0) {
7163                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7164                         return I40E_ERR_PARAM;
7165                 }
7166         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7167                         filter_type == RTE_MAC_HASH_MATCH)
7168                 vlan_num = 1;
7169
7170         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7171         if (mv_f == NULL) {
7172                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7173                 return I40E_ERR_NO_MEMORY;
7174         }
7175
7176         for (i = 0; i < vlan_num; i++) {
7177                 mv_f[i].filter_type = filter_type;
7178                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7179                                 ETH_ADDR_LEN);
7180         }
7181         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7182                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7183                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7184                 if (ret != I40E_SUCCESS)
7185                         goto DONE;
7186         }
7187
7188         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7189         if (ret != I40E_SUCCESS)
7190                 goto DONE;
7191
7192         /* Remove the mac addr into mac list */
7193         TAILQ_REMOVE(&vsi->mac_list, f, next);
7194         rte_free(f);
7195         vsi->mac_num--;
7196
7197         ret = I40E_SUCCESS;
7198 DONE:
7199         rte_free(mv_f);
7200         return ret;
7201 }
7202
7203 /* Configure hash enable flags for RSS */
7204 uint64_t
7205 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7206 {
7207         uint64_t hena = 0;
7208         int i;
7209
7210         if (!flags)
7211                 return hena;
7212
7213         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7214                 if (flags & (1ULL << i))
7215                         hena |= adapter->pctypes_tbl[i];
7216         }
7217
7218         return hena;
7219 }
7220
7221 /* Parse the hash enable flags */
7222 uint64_t
7223 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7224 {
7225         uint64_t rss_hf = 0;
7226
7227         if (!flags)
7228                 return rss_hf;
7229         int i;
7230
7231         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7232                 if (flags & adapter->pctypes_tbl[i])
7233                         rss_hf |= (1ULL << i);
7234         }
7235         return rss_hf;
7236 }
7237
7238 /* Disable RSS */
7239 static void
7240 i40e_pf_disable_rss(struct i40e_pf *pf)
7241 {
7242         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7243
7244         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7245         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7246         I40E_WRITE_FLUSH(hw);
7247 }
7248
7249 int
7250 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7251 {
7252         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7253         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7254         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7255                            I40E_VFQF_HKEY_MAX_INDEX :
7256                            I40E_PFQF_HKEY_MAX_INDEX;
7257         int ret = 0;
7258
7259         if (!key || key_len == 0) {
7260                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7261                 return 0;
7262         } else if (key_len != (key_idx + 1) *
7263                 sizeof(uint32_t)) {
7264                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7265                 return -EINVAL;
7266         }
7267
7268         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7269                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7270                         (struct i40e_aqc_get_set_rss_key_data *)key;
7271
7272                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7273                 if (ret)
7274                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7275         } else {
7276                 uint32_t *hash_key = (uint32_t *)key;
7277                 uint16_t i;
7278
7279                 if (vsi->type == I40E_VSI_SRIOV) {
7280                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7281                                 I40E_WRITE_REG(
7282                                         hw,
7283                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7284                                         hash_key[i]);
7285
7286                 } else {
7287                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7288                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7289                                                hash_key[i]);
7290                 }
7291                 I40E_WRITE_FLUSH(hw);
7292         }
7293
7294         return ret;
7295 }
7296
7297 static int
7298 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7299 {
7300         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7301         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7302         uint32_t reg;
7303         int ret;
7304
7305         if (!key || !key_len)
7306                 return -EINVAL;
7307
7308         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7309                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7310                         (struct i40e_aqc_get_set_rss_key_data *)key);
7311                 if (ret) {
7312                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7313                         return ret;
7314                 }
7315         } else {
7316                 uint32_t *key_dw = (uint32_t *)key;
7317                 uint16_t i;
7318
7319                 if (vsi->type == I40E_VSI_SRIOV) {
7320                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7321                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7322                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7323                         }
7324                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7325                                    sizeof(uint32_t);
7326                 } else {
7327                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7328                                 reg = I40E_PFQF_HKEY(i);
7329                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7330                         }
7331                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7332                                    sizeof(uint32_t);
7333                 }
7334         }
7335         return 0;
7336 }
7337
7338 static int
7339 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7340 {
7341         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7342         uint64_t hena;
7343         int ret;
7344
7345         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7346                                rss_conf->rss_key_len);
7347         if (ret)
7348                 return ret;
7349
7350         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7351         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7352         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7353         I40E_WRITE_FLUSH(hw);
7354
7355         return 0;
7356 }
7357
7358 static int
7359 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7360                          struct rte_eth_rss_conf *rss_conf)
7361 {
7362         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7363         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7364         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7365         uint64_t hena;
7366
7367         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7368         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7369
7370         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7371                 if (rss_hf != 0) /* Enable RSS */
7372                         return -EINVAL;
7373                 return 0; /* Nothing to do */
7374         }
7375         /* RSS enabled */
7376         if (rss_hf == 0) /* Disable RSS */
7377                 return -EINVAL;
7378
7379         return i40e_hw_rss_hash_set(pf, rss_conf);
7380 }
7381
7382 static int
7383 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7384                            struct rte_eth_rss_conf *rss_conf)
7385 {
7386         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7387         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7388         uint64_t hena;
7389
7390         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7391                          &rss_conf->rss_key_len);
7392
7393         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7394         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7395         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7396
7397         return 0;
7398 }
7399
7400 static int
7401 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7402 {
7403         switch (filter_type) {
7404         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7405                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7406                 break;
7407         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7408                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7409                 break;
7410         case RTE_TUNNEL_FILTER_IMAC_TENID:
7411                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7412                 break;
7413         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7414                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7415                 break;
7416         case ETH_TUNNEL_FILTER_IMAC:
7417                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7418                 break;
7419         case ETH_TUNNEL_FILTER_OIP:
7420                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7421                 break;
7422         case ETH_TUNNEL_FILTER_IIP:
7423                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7424                 break;
7425         default:
7426                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7427                 return -EINVAL;
7428         }
7429
7430         return 0;
7431 }
7432
7433 /* Convert tunnel filter structure */
7434 static int
7435 i40e_tunnel_filter_convert(
7436         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7437         struct i40e_tunnel_filter *tunnel_filter)
7438 {
7439         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7440                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7441         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7442                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7443         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7444         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7445              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7446             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7447                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7448         else
7449                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7450         tunnel_filter->input.flags = cld_filter->element.flags;
7451         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7452         tunnel_filter->queue = cld_filter->element.queue_number;
7453         rte_memcpy(tunnel_filter->input.general_fields,
7454                    cld_filter->general_fields,
7455                    sizeof(cld_filter->general_fields));
7456
7457         return 0;
7458 }
7459
7460 /* Check if there exists the tunnel filter */
7461 struct i40e_tunnel_filter *
7462 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7463                              const struct i40e_tunnel_filter_input *input)
7464 {
7465         int ret;
7466
7467         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7468         if (ret < 0)
7469                 return NULL;
7470
7471         return tunnel_rule->hash_map[ret];
7472 }
7473
7474 /* Add a tunnel filter into the SW list */
7475 static int
7476 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7477                              struct i40e_tunnel_filter *tunnel_filter)
7478 {
7479         struct i40e_tunnel_rule *rule = &pf->tunnel;
7480         int ret;
7481
7482         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7483         if (ret < 0) {
7484                 PMD_DRV_LOG(ERR,
7485                             "Failed to insert tunnel filter to hash table %d!",
7486                             ret);
7487                 return ret;
7488         }
7489         rule->hash_map[ret] = tunnel_filter;
7490
7491         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7492
7493         return 0;
7494 }
7495
7496 /* Delete a tunnel filter from the SW list */
7497 int
7498 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7499                           struct i40e_tunnel_filter_input *input)
7500 {
7501         struct i40e_tunnel_rule *rule = &pf->tunnel;
7502         struct i40e_tunnel_filter *tunnel_filter;
7503         int ret;
7504
7505         ret = rte_hash_del_key(rule->hash_table, input);
7506         if (ret < 0) {
7507                 PMD_DRV_LOG(ERR,
7508                             "Failed to delete tunnel filter to hash table %d!",
7509                             ret);
7510                 return ret;
7511         }
7512         tunnel_filter = rule->hash_map[ret];
7513         rule->hash_map[ret] = NULL;
7514
7515         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7516         rte_free(tunnel_filter);
7517
7518         return 0;
7519 }
7520
7521 int
7522 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7523                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7524                         uint8_t add)
7525 {
7526         uint16_t ip_type;
7527         uint32_t ipv4_addr, ipv4_addr_le;
7528         uint8_t i, tun_type = 0;
7529         /* internal varialbe to convert ipv6 byte order */
7530         uint32_t convert_ipv6[4];
7531         int val, ret = 0;
7532         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7533         struct i40e_vsi *vsi = pf->main_vsi;
7534         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7535         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7536         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7537         struct i40e_tunnel_filter *tunnel, *node;
7538         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7539
7540         cld_filter = rte_zmalloc("tunnel_filter",
7541                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7542         0);
7543
7544         if (NULL == cld_filter) {
7545                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7546                 return -ENOMEM;
7547         }
7548         pfilter = cld_filter;
7549
7550         ether_addr_copy(&tunnel_filter->outer_mac,
7551                         (struct ether_addr *)&pfilter->element.outer_mac);
7552         ether_addr_copy(&tunnel_filter->inner_mac,
7553                         (struct ether_addr *)&pfilter->element.inner_mac);
7554
7555         pfilter->element.inner_vlan =
7556                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7557         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7558                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7559                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7560                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7561                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7562                                 &ipv4_addr_le,
7563                                 sizeof(pfilter->element.ipaddr.v4.data));
7564         } else {
7565                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7566                 for (i = 0; i < 4; i++) {
7567                         convert_ipv6[i] =
7568                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7569                 }
7570                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7571                            &convert_ipv6,
7572                            sizeof(pfilter->element.ipaddr.v6.data));
7573         }
7574
7575         /* check tunneled type */
7576         switch (tunnel_filter->tunnel_type) {
7577         case RTE_TUNNEL_TYPE_VXLAN:
7578                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7579                 break;
7580         case RTE_TUNNEL_TYPE_NVGRE:
7581                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7582                 break;
7583         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7584                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7585                 break;
7586         default:
7587                 /* Other tunnel types is not supported. */
7588                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7589                 rte_free(cld_filter);
7590                 return -EINVAL;
7591         }
7592
7593         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7594                                        &pfilter->element.flags);
7595         if (val < 0) {
7596                 rte_free(cld_filter);
7597                 return -EINVAL;
7598         }
7599
7600         pfilter->element.flags |= rte_cpu_to_le_16(
7601                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7602                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7603         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7604         pfilter->element.queue_number =
7605                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7606
7607         /* Check if there is the filter in SW list */
7608         memset(&check_filter, 0, sizeof(check_filter));
7609         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7610         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7611         if (add && node) {
7612                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7613                 rte_free(cld_filter);
7614                 return -EINVAL;
7615         }
7616
7617         if (!add && !node) {
7618                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7619                 rte_free(cld_filter);
7620                 return -EINVAL;
7621         }
7622
7623         if (add) {
7624                 ret = i40e_aq_add_cloud_filters(hw,
7625                                         vsi->seid, &cld_filter->element, 1);
7626                 if (ret < 0) {
7627                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7628                         rte_free(cld_filter);
7629                         return -ENOTSUP;
7630                 }
7631                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7632                 if (tunnel == NULL) {
7633                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7634                         rte_free(cld_filter);
7635                         return -ENOMEM;
7636                 }
7637
7638                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7639                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7640                 if (ret < 0)
7641                         rte_free(tunnel);
7642         } else {
7643                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7644                                                    &cld_filter->element, 1);
7645                 if (ret < 0) {
7646                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7647                         rte_free(cld_filter);
7648                         return -ENOTSUP;
7649                 }
7650                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7651         }
7652
7653         rte_free(cld_filter);
7654         return ret;
7655 }
7656
7657 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7658 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7659 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7660 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7661 #define I40E_TR_GRE_KEY_MASK                    0x400
7662 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7663 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7664
7665 static enum
7666 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7667 {
7668         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7669         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7670         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7671         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7672         enum i40e_status_code status = I40E_SUCCESS;
7673
7674         if (pf->support_multi_driver) {
7675                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7676                 return I40E_NOT_SUPPORTED;
7677         }
7678
7679         memset(&filter_replace, 0,
7680                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7681         memset(&filter_replace_buf, 0,
7682                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7683
7684         /* create L1 filter */
7685         filter_replace.old_filter_type =
7686                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7687         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7688         filter_replace.tr_bit = 0;
7689
7690         /* Prepare the buffer, 3 entries */
7691         filter_replace_buf.data[0] =
7692                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7693         filter_replace_buf.data[0] |=
7694                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7695         filter_replace_buf.data[2] = 0xFF;
7696         filter_replace_buf.data[3] = 0xFF;
7697         filter_replace_buf.data[4] =
7698                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7699         filter_replace_buf.data[4] |=
7700                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7701         filter_replace_buf.data[7] = 0xF0;
7702         filter_replace_buf.data[8]
7703                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7704         filter_replace_buf.data[8] |=
7705                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7706         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7707                 I40E_TR_GENEVE_KEY_MASK |
7708                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7709         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7710                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7711                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7712
7713         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7714                                                &filter_replace_buf);
7715         if (!status && (filter_replace.old_filter_type !=
7716                         filter_replace.new_filter_type))
7717                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7718                             " original: 0x%x, new: 0x%x",
7719                             dev->device->name,
7720                             filter_replace.old_filter_type,
7721                             filter_replace.new_filter_type);
7722
7723         return status;
7724 }
7725
7726 static enum
7727 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7728 {
7729         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7730         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7731         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7732         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7733         enum i40e_status_code status = I40E_SUCCESS;
7734
7735         if (pf->support_multi_driver) {
7736                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7737                 return I40E_NOT_SUPPORTED;
7738         }
7739
7740         /* For MPLSoUDP */
7741         memset(&filter_replace, 0,
7742                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7743         memset(&filter_replace_buf, 0,
7744                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7745         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7746                 I40E_AQC_MIRROR_CLOUD_FILTER;
7747         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7748         filter_replace.new_filter_type =
7749                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7750         /* Prepare the buffer, 2 entries */
7751         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7752         filter_replace_buf.data[0] |=
7753                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7754         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7755         filter_replace_buf.data[4] |=
7756                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7757         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7758                                                &filter_replace_buf);
7759         if (status < 0)
7760                 return status;
7761         if (filter_replace.old_filter_type !=
7762             filter_replace.new_filter_type)
7763                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7764                             " original: 0x%x, new: 0x%x",
7765                             dev->device->name,
7766                             filter_replace.old_filter_type,
7767                             filter_replace.new_filter_type);
7768
7769         /* For MPLSoGRE */
7770         memset(&filter_replace, 0,
7771                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7772         memset(&filter_replace_buf, 0,
7773                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7774
7775         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7776                 I40E_AQC_MIRROR_CLOUD_FILTER;
7777         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7778         filter_replace.new_filter_type =
7779                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7780         /* Prepare the buffer, 2 entries */
7781         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7782         filter_replace_buf.data[0] |=
7783                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7784         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7785         filter_replace_buf.data[4] |=
7786                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7787
7788         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7789                                                &filter_replace_buf);
7790         if (!status && (filter_replace.old_filter_type !=
7791                         filter_replace.new_filter_type))
7792                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7793                             " original: 0x%x, new: 0x%x",
7794                             dev->device->name,
7795                             filter_replace.old_filter_type,
7796                             filter_replace.new_filter_type);
7797
7798         return status;
7799 }
7800
7801 static enum i40e_status_code
7802 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7803 {
7804         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7805         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7806         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7807         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7808         enum i40e_status_code status = I40E_SUCCESS;
7809
7810         if (pf->support_multi_driver) {
7811                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7812                 return I40E_NOT_SUPPORTED;
7813         }
7814
7815         /* For GTP-C */
7816         memset(&filter_replace, 0,
7817                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7818         memset(&filter_replace_buf, 0,
7819                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7820         /* create L1 filter */
7821         filter_replace.old_filter_type =
7822                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7823         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7824         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7825                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7826         /* Prepare the buffer, 2 entries */
7827         filter_replace_buf.data[0] =
7828                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7829         filter_replace_buf.data[0] |=
7830                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7831         filter_replace_buf.data[2] = 0xFF;
7832         filter_replace_buf.data[3] = 0xFF;
7833         filter_replace_buf.data[4] =
7834                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7835         filter_replace_buf.data[4] |=
7836                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7837         filter_replace_buf.data[6] = 0xFF;
7838         filter_replace_buf.data[7] = 0xFF;
7839         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7840                                                &filter_replace_buf);
7841         if (status < 0)
7842                 return status;
7843         if (filter_replace.old_filter_type !=
7844             filter_replace.new_filter_type)
7845                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7846                             " original: 0x%x, new: 0x%x",
7847                             dev->device->name,
7848                             filter_replace.old_filter_type,
7849                             filter_replace.new_filter_type);
7850
7851         /* for GTP-U */
7852         memset(&filter_replace, 0,
7853                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7854         memset(&filter_replace_buf, 0,
7855                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7856         /* create L1 filter */
7857         filter_replace.old_filter_type =
7858                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7859         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7860         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7861                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7862         /* Prepare the buffer, 2 entries */
7863         filter_replace_buf.data[0] =
7864                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7865         filter_replace_buf.data[0] |=
7866                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7867         filter_replace_buf.data[2] = 0xFF;
7868         filter_replace_buf.data[3] = 0xFF;
7869         filter_replace_buf.data[4] =
7870                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7871         filter_replace_buf.data[4] |=
7872                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7873         filter_replace_buf.data[6] = 0xFF;
7874         filter_replace_buf.data[7] = 0xFF;
7875
7876         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7877                                                &filter_replace_buf);
7878         if (!status && (filter_replace.old_filter_type !=
7879                         filter_replace.new_filter_type))
7880                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7881                             " original: 0x%x, new: 0x%x",
7882                             dev->device->name,
7883                             filter_replace.old_filter_type,
7884                             filter_replace.new_filter_type);
7885
7886         return status;
7887 }
7888
7889 static enum
7890 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7891 {
7892         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7893         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7894         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7895         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7896         enum i40e_status_code status = I40E_SUCCESS;
7897
7898         if (pf->support_multi_driver) {
7899                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7900                 return I40E_NOT_SUPPORTED;
7901         }
7902
7903         /* for GTP-C */
7904         memset(&filter_replace, 0,
7905                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7906         memset(&filter_replace_buf, 0,
7907                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7908         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7909         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7910         filter_replace.new_filter_type =
7911                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7912         /* Prepare the buffer, 2 entries */
7913         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7914         filter_replace_buf.data[0] |=
7915                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7916         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7917         filter_replace_buf.data[4] |=
7918                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7919         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7920                                                &filter_replace_buf);
7921         if (status < 0)
7922                 return status;
7923         if (filter_replace.old_filter_type !=
7924             filter_replace.new_filter_type)
7925                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7926                             " original: 0x%x, new: 0x%x",
7927                             dev->device->name,
7928                             filter_replace.old_filter_type,
7929                             filter_replace.new_filter_type);
7930
7931         /* for GTP-U */
7932         memset(&filter_replace, 0,
7933                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7934         memset(&filter_replace_buf, 0,
7935                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7936         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7937         filter_replace.old_filter_type =
7938                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7939         filter_replace.new_filter_type =
7940                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7941         /* Prepare the buffer, 2 entries */
7942         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7943         filter_replace_buf.data[0] |=
7944                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7945         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7946         filter_replace_buf.data[4] |=
7947                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7948
7949         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7950                                                &filter_replace_buf);
7951         if (!status && (filter_replace.old_filter_type !=
7952                         filter_replace.new_filter_type))
7953                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7954                             " original: 0x%x, new: 0x%x",
7955                             dev->device->name,
7956                             filter_replace.old_filter_type,
7957                             filter_replace.new_filter_type);
7958
7959         return status;
7960 }
7961
7962 int
7963 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7964                       struct i40e_tunnel_filter_conf *tunnel_filter,
7965                       uint8_t add)
7966 {
7967         uint16_t ip_type;
7968         uint32_t ipv4_addr, ipv4_addr_le;
7969         uint8_t i, tun_type = 0;
7970         /* internal variable to convert ipv6 byte order */
7971         uint32_t convert_ipv6[4];
7972         int val, ret = 0;
7973         struct i40e_pf_vf *vf = NULL;
7974         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7975         struct i40e_vsi *vsi;
7976         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7977         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7978         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7979         struct i40e_tunnel_filter *tunnel, *node;
7980         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7981         uint32_t teid_le;
7982         bool big_buffer = 0;
7983
7984         cld_filter = rte_zmalloc("tunnel_filter",
7985                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7986                          0);
7987
7988         if (cld_filter == NULL) {
7989                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7990                 return -ENOMEM;
7991         }
7992         pfilter = cld_filter;
7993
7994         ether_addr_copy(&tunnel_filter->outer_mac,
7995                         (struct ether_addr *)&pfilter->element.outer_mac);
7996         ether_addr_copy(&tunnel_filter->inner_mac,
7997                         (struct ether_addr *)&pfilter->element.inner_mac);
7998
7999         pfilter->element.inner_vlan =
8000                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8001         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8002                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8003                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8004                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8005                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8006                                 &ipv4_addr_le,
8007                                 sizeof(pfilter->element.ipaddr.v4.data));
8008         } else {
8009                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8010                 for (i = 0; i < 4; i++) {
8011                         convert_ipv6[i] =
8012                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8013                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8014                 }
8015                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8016                            &convert_ipv6,
8017                            sizeof(pfilter->element.ipaddr.v6.data));
8018         }
8019
8020         /* check tunneled type */
8021         switch (tunnel_filter->tunnel_type) {
8022         case I40E_TUNNEL_TYPE_VXLAN:
8023                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8024                 break;
8025         case I40E_TUNNEL_TYPE_NVGRE:
8026                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8027                 break;
8028         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8029                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8030                 break;
8031         case I40E_TUNNEL_TYPE_MPLSoUDP:
8032                 if (!pf->mpls_replace_flag) {
8033                         i40e_replace_mpls_l1_filter(pf);
8034                         i40e_replace_mpls_cloud_filter(pf);
8035                         pf->mpls_replace_flag = 1;
8036                 }
8037                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8038                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8039                         teid_le >> 4;
8040                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8041                         (teid_le & 0xF) << 12;
8042                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8043                         0x40;
8044                 big_buffer = 1;
8045                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8046                 break;
8047         case I40E_TUNNEL_TYPE_MPLSoGRE:
8048                 if (!pf->mpls_replace_flag) {
8049                         i40e_replace_mpls_l1_filter(pf);
8050                         i40e_replace_mpls_cloud_filter(pf);
8051                         pf->mpls_replace_flag = 1;
8052                 }
8053                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8054                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8055                         teid_le >> 4;
8056                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8057                         (teid_le & 0xF) << 12;
8058                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8059                         0x0;
8060                 big_buffer = 1;
8061                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8062                 break;
8063         case I40E_TUNNEL_TYPE_GTPC:
8064                 if (!pf->gtp_replace_flag) {
8065                         i40e_replace_gtp_l1_filter(pf);
8066                         i40e_replace_gtp_cloud_filter(pf);
8067                         pf->gtp_replace_flag = 1;
8068                 }
8069                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8070                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8071                         (teid_le >> 16) & 0xFFFF;
8072                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8073                         teid_le & 0xFFFF;
8074                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8075                         0x0;
8076                 big_buffer = 1;
8077                 break;
8078         case I40E_TUNNEL_TYPE_GTPU:
8079                 if (!pf->gtp_replace_flag) {
8080                         i40e_replace_gtp_l1_filter(pf);
8081                         i40e_replace_gtp_cloud_filter(pf);
8082                         pf->gtp_replace_flag = 1;
8083                 }
8084                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8085                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8086                         (teid_le >> 16) & 0xFFFF;
8087                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8088                         teid_le & 0xFFFF;
8089                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8090                         0x0;
8091                 big_buffer = 1;
8092                 break;
8093         case I40E_TUNNEL_TYPE_QINQ:
8094                 if (!pf->qinq_replace_flag) {
8095                         ret = i40e_cloud_filter_qinq_create(pf);
8096                         if (ret < 0)
8097                                 PMD_DRV_LOG(DEBUG,
8098                                             "QinQ tunnel filter already created.");
8099                         pf->qinq_replace_flag = 1;
8100                 }
8101                 /*      Add in the General fields the values of
8102                  *      the Outer and Inner VLAN
8103                  *      Big Buffer should be set, see changes in
8104                  *      i40e_aq_add_cloud_filters
8105                  */
8106                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8107                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8108                 big_buffer = 1;
8109                 break;
8110         default:
8111                 /* Other tunnel types is not supported. */
8112                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8113                 rte_free(cld_filter);
8114                 return -EINVAL;
8115         }
8116
8117         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8118                 pfilter->element.flags =
8119                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8120         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8121                 pfilter->element.flags =
8122                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8123         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8124                 pfilter->element.flags =
8125                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8126         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8127                 pfilter->element.flags =
8128                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8129         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8130                 pfilter->element.flags |=
8131                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8132         else {
8133                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8134                                                 &pfilter->element.flags);
8135                 if (val < 0) {
8136                         rte_free(cld_filter);
8137                         return -EINVAL;
8138                 }
8139         }
8140
8141         pfilter->element.flags |= rte_cpu_to_le_16(
8142                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8143                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8144         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8145         pfilter->element.queue_number =
8146                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8147
8148         if (!tunnel_filter->is_to_vf)
8149                 vsi = pf->main_vsi;
8150         else {
8151                 if (tunnel_filter->vf_id >= pf->vf_num) {
8152                         PMD_DRV_LOG(ERR, "Invalid argument.");
8153                         rte_free(cld_filter);
8154                         return -EINVAL;
8155                 }
8156                 vf = &pf->vfs[tunnel_filter->vf_id];
8157                 vsi = vf->vsi;
8158         }
8159
8160         /* Check if there is the filter in SW list */
8161         memset(&check_filter, 0, sizeof(check_filter));
8162         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8163         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8164         check_filter.vf_id = tunnel_filter->vf_id;
8165         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8166         if (add && node) {
8167                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8168                 rte_free(cld_filter);
8169                 return -EINVAL;
8170         }
8171
8172         if (!add && !node) {
8173                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8174                 rte_free(cld_filter);
8175                 return -EINVAL;
8176         }
8177
8178         if (add) {
8179                 if (big_buffer)
8180                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
8181                                                    vsi->seid, cld_filter, 1);
8182                 else
8183                         ret = i40e_aq_add_cloud_filters(hw,
8184                                         vsi->seid, &cld_filter->element, 1);
8185                 if (ret < 0) {
8186                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8187                         rte_free(cld_filter);
8188                         return -ENOTSUP;
8189                 }
8190                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8191                 if (tunnel == NULL) {
8192                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8193                         rte_free(cld_filter);
8194                         return -ENOMEM;
8195                 }
8196
8197                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8198                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8199                 if (ret < 0)
8200                         rte_free(tunnel);
8201         } else {
8202                 if (big_buffer)
8203                         ret = i40e_aq_remove_cloud_filters_big_buffer(
8204                                 hw, vsi->seid, cld_filter, 1);
8205                 else
8206                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
8207                                                    &cld_filter->element, 1);
8208                 if (ret < 0) {
8209                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8210                         rte_free(cld_filter);
8211                         return -ENOTSUP;
8212                 }
8213                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8214         }
8215
8216         rte_free(cld_filter);
8217         return ret;
8218 }
8219
8220 static int
8221 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8222 {
8223         uint8_t i;
8224
8225         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8226                 if (pf->vxlan_ports[i] == port)
8227                         return i;
8228         }
8229
8230         return -1;
8231 }
8232
8233 static int
8234 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8235 {
8236         int  idx, ret;
8237         uint8_t filter_idx;
8238         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8239
8240         idx = i40e_get_vxlan_port_idx(pf, port);
8241
8242         /* Check if port already exists */
8243         if (idx >= 0) {
8244                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8245                 return -EINVAL;
8246         }
8247
8248         /* Now check if there is space to add the new port */
8249         idx = i40e_get_vxlan_port_idx(pf, 0);
8250         if (idx < 0) {
8251                 PMD_DRV_LOG(ERR,
8252                         "Maximum number of UDP ports reached, not adding port %d",
8253                         port);
8254                 return -ENOSPC;
8255         }
8256
8257         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8258                                         &filter_idx, NULL);
8259         if (ret < 0) {
8260                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8261                 return -1;
8262         }
8263
8264         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8265                          port,  filter_idx);
8266
8267         /* New port: add it and mark its index in the bitmap */
8268         pf->vxlan_ports[idx] = port;
8269         pf->vxlan_bitmap |= (1 << idx);
8270
8271         if (!(pf->flags & I40E_FLAG_VXLAN))
8272                 pf->flags |= I40E_FLAG_VXLAN;
8273
8274         return 0;
8275 }
8276
8277 static int
8278 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8279 {
8280         int idx;
8281         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8282
8283         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8284                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8285                 return -EINVAL;
8286         }
8287
8288         idx = i40e_get_vxlan_port_idx(pf, port);
8289
8290         if (idx < 0) {
8291                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8292                 return -EINVAL;
8293         }
8294
8295         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8296                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8297                 return -1;
8298         }
8299
8300         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8301                         port, idx);
8302
8303         pf->vxlan_ports[idx] = 0;
8304         pf->vxlan_bitmap &= ~(1 << idx);
8305
8306         if (!pf->vxlan_bitmap)
8307                 pf->flags &= ~I40E_FLAG_VXLAN;
8308
8309         return 0;
8310 }
8311
8312 /* Add UDP tunneling port */
8313 static int
8314 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8315                              struct rte_eth_udp_tunnel *udp_tunnel)
8316 {
8317         int ret = 0;
8318         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8319
8320         if (udp_tunnel == NULL)
8321                 return -EINVAL;
8322
8323         switch (udp_tunnel->prot_type) {
8324         case RTE_TUNNEL_TYPE_VXLAN:
8325                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8326                 break;
8327
8328         case RTE_TUNNEL_TYPE_GENEVE:
8329         case RTE_TUNNEL_TYPE_TEREDO:
8330                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8331                 ret = -1;
8332                 break;
8333
8334         default:
8335                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8336                 ret = -1;
8337                 break;
8338         }
8339
8340         return ret;
8341 }
8342
8343 /* Remove UDP tunneling port */
8344 static int
8345 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8346                              struct rte_eth_udp_tunnel *udp_tunnel)
8347 {
8348         int ret = 0;
8349         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8350
8351         if (udp_tunnel == NULL)
8352                 return -EINVAL;
8353
8354         switch (udp_tunnel->prot_type) {
8355         case RTE_TUNNEL_TYPE_VXLAN:
8356                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8357                 break;
8358         case RTE_TUNNEL_TYPE_GENEVE:
8359         case RTE_TUNNEL_TYPE_TEREDO:
8360                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8361                 ret = -1;
8362                 break;
8363         default:
8364                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8365                 ret = -1;
8366                 break;
8367         }
8368
8369         return ret;
8370 }
8371
8372 /* Calculate the maximum number of contiguous PF queues that are configured */
8373 static int
8374 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8375 {
8376         struct rte_eth_dev_data *data = pf->dev_data;
8377         int i, num;
8378         struct i40e_rx_queue *rxq;
8379
8380         num = 0;
8381         for (i = 0; i < pf->lan_nb_qps; i++) {
8382                 rxq = data->rx_queues[i];
8383                 if (rxq && rxq->q_set)
8384                         num++;
8385                 else
8386                         break;
8387         }
8388
8389         return num;
8390 }
8391
8392 /* Configure RSS */
8393 static int
8394 i40e_pf_config_rss(struct i40e_pf *pf)
8395 {
8396         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8397         struct rte_eth_rss_conf rss_conf;
8398         uint32_t i, lut = 0;
8399         uint16_t j, num;
8400
8401         /*
8402          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8403          * It's necessary to calculate the actual PF queues that are configured.
8404          */
8405         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8406                 num = i40e_pf_calc_configured_queues_num(pf);
8407         else
8408                 num = pf->dev_data->nb_rx_queues;
8409
8410         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8411         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8412                         num);
8413
8414         if (num == 0) {
8415                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8416                 return -ENOTSUP;
8417         }
8418
8419         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8420                 if (j == num)
8421                         j = 0;
8422                 lut = (lut << 8) | (j & ((0x1 <<
8423                         hw->func_caps.rss_table_entry_width) - 1));
8424                 if ((i & 3) == 3)
8425                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8426         }
8427
8428         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8429         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8430                 i40e_pf_disable_rss(pf);
8431                 return 0;
8432         }
8433         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8434                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8435                 /* Random default keys */
8436                 static uint32_t rss_key_default[] = {0x6b793944,
8437                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8438                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8439                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8440
8441                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8442                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8443                                                         sizeof(uint32_t);
8444         }
8445
8446         return i40e_hw_rss_hash_set(pf, &rss_conf);
8447 }
8448
8449 static int
8450 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8451                                struct rte_eth_tunnel_filter_conf *filter)
8452 {
8453         if (pf == NULL || filter == NULL) {
8454                 PMD_DRV_LOG(ERR, "Invalid parameter");
8455                 return -EINVAL;
8456         }
8457
8458         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8459                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8460                 return -EINVAL;
8461         }
8462
8463         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8464                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8465                 return -EINVAL;
8466         }
8467
8468         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8469                 (is_zero_ether_addr(&filter->outer_mac))) {
8470                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8471                 return -EINVAL;
8472         }
8473
8474         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8475                 (is_zero_ether_addr(&filter->inner_mac))) {
8476                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8477                 return -EINVAL;
8478         }
8479
8480         return 0;
8481 }
8482
8483 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8484 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8485 static int
8486 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8487 {
8488         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8489         uint32_t val, reg;
8490         int ret = -EINVAL;
8491
8492         if (pf->support_multi_driver) {
8493                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8494                 return -ENOTSUP;
8495         }
8496
8497         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8498         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8499
8500         if (len == 3) {
8501                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8502         } else if (len == 4) {
8503                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8504         } else {
8505                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8506                 return ret;
8507         }
8508
8509         if (reg != val) {
8510                 ret = i40e_aq_debug_write_global_register(hw,
8511                                                    I40E_GL_PRS_FVBM(2),
8512                                                    reg, NULL);
8513                 if (ret != 0)
8514                         return ret;
8515                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8516                             "with value 0x%08x",
8517                             I40E_GL_PRS_FVBM(2), reg);
8518         } else {
8519                 ret = 0;
8520         }
8521         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8522                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8523
8524         return ret;
8525 }
8526
8527 static int
8528 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8529 {
8530         int ret = -EINVAL;
8531
8532         if (!hw || !cfg)
8533                 return -EINVAL;
8534
8535         switch (cfg->cfg_type) {
8536         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8537                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8538                 break;
8539         default:
8540                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8541                 break;
8542         }
8543
8544         return ret;
8545 }
8546
8547 static int
8548 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8549                                enum rte_filter_op filter_op,
8550                                void *arg)
8551 {
8552         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8553         int ret = I40E_ERR_PARAM;
8554
8555         switch (filter_op) {
8556         case RTE_ETH_FILTER_SET:
8557                 ret = i40e_dev_global_config_set(hw,
8558                         (struct rte_eth_global_cfg *)arg);
8559                 break;
8560         default:
8561                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8562                 break;
8563         }
8564
8565         return ret;
8566 }
8567
8568 static int
8569 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8570                           enum rte_filter_op filter_op,
8571                           void *arg)
8572 {
8573         struct rte_eth_tunnel_filter_conf *filter;
8574         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8575         int ret = I40E_SUCCESS;
8576
8577         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8578
8579         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8580                 return I40E_ERR_PARAM;
8581
8582         switch (filter_op) {
8583         case RTE_ETH_FILTER_NOP:
8584                 if (!(pf->flags & I40E_FLAG_VXLAN))
8585                         ret = I40E_NOT_SUPPORTED;
8586                 break;
8587         case RTE_ETH_FILTER_ADD:
8588                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8589                 break;
8590         case RTE_ETH_FILTER_DELETE:
8591                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8592                 break;
8593         default:
8594                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8595                 ret = I40E_ERR_PARAM;
8596                 break;
8597         }
8598
8599         return ret;
8600 }
8601
8602 static int
8603 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8604 {
8605         int ret = 0;
8606         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8607
8608         /* RSS setup */
8609         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8610                 ret = i40e_pf_config_rss(pf);
8611         else
8612                 i40e_pf_disable_rss(pf);
8613
8614         return ret;
8615 }
8616
8617 /* Get the symmetric hash enable configurations per port */
8618 static void
8619 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8620 {
8621         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8622
8623         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8624 }
8625
8626 /* Set the symmetric hash enable configurations per port */
8627 static void
8628 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8629 {
8630         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8631
8632         if (enable > 0) {
8633                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8634                         PMD_DRV_LOG(INFO,
8635                                 "Symmetric hash has already been enabled");
8636                         return;
8637                 }
8638                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8639         } else {
8640                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8641                         PMD_DRV_LOG(INFO,
8642                                 "Symmetric hash has already been disabled");
8643                         return;
8644                 }
8645                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8646         }
8647         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8648         I40E_WRITE_FLUSH(hw);
8649 }
8650
8651 /*
8652  * Get global configurations of hash function type and symmetric hash enable
8653  * per flow type (pctype). Note that global configuration means it affects all
8654  * the ports on the same NIC.
8655  */
8656 static int
8657 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8658                                    struct rte_eth_hash_global_conf *g_cfg)
8659 {
8660         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8661         uint32_t reg;
8662         uint16_t i, j;
8663
8664         memset(g_cfg, 0, sizeof(*g_cfg));
8665         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8666         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8667                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8668         else
8669                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8670         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8671                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8672
8673         /*
8674          * As i40e supports less than 64 flow types, only first 64 bits need to
8675          * be checked.
8676          */
8677         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8678                 g_cfg->valid_bit_mask[i] = 0ULL;
8679                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8680         }
8681
8682         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8683
8684         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8685                 if (!adapter->pctypes_tbl[i])
8686                         continue;
8687                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8688                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8689                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8690                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8691                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8692                                         g_cfg->sym_hash_enable_mask[0] |=
8693                                                                 (1ULL << i);
8694                                 }
8695                         }
8696                 }
8697         }
8698
8699         return 0;
8700 }
8701
8702 static int
8703 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8704                               const struct rte_eth_hash_global_conf *g_cfg)
8705 {
8706         uint32_t i;
8707         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8708
8709         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8710                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8711                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8712                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8713                                                 g_cfg->hash_func);
8714                 return -EINVAL;
8715         }
8716
8717         /*
8718          * As i40e supports less than 64 flow types, only first 64 bits need to
8719          * be checked.
8720          */
8721         mask0 = g_cfg->valid_bit_mask[0];
8722         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8723                 if (i == 0) {
8724                         /* Check if any unsupported flow type configured */
8725                         if ((mask0 | i40e_mask) ^ i40e_mask)
8726                                 goto mask_err;
8727                 } else {
8728                         if (g_cfg->valid_bit_mask[i])
8729                                 goto mask_err;
8730                 }
8731         }
8732
8733         return 0;
8734
8735 mask_err:
8736         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8737
8738         return -EINVAL;
8739 }
8740
8741 /*
8742  * Set global configurations of hash function type and symmetric hash enable
8743  * per flow type (pctype). Note any modifying global configuration will affect
8744  * all the ports on the same NIC.
8745  */
8746 static int
8747 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8748                                    struct rte_eth_hash_global_conf *g_cfg)
8749 {
8750         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8751         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8752         int ret;
8753         uint16_t i, j;
8754         uint32_t reg;
8755         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8756
8757         if (pf->support_multi_driver) {
8758                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8759                 return -ENOTSUP;
8760         }
8761
8762         /* Check the input parameters */
8763         ret = i40e_hash_global_config_check(adapter, g_cfg);
8764         if (ret < 0)
8765                 return ret;
8766
8767         /*
8768          * As i40e supports less than 64 flow types, only first 64 bits need to
8769          * be configured.
8770          */
8771         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8772                 if (mask0 & (1UL << i)) {
8773                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8774                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8775
8776                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8777                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8778                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8779                                         i40e_write_global_rx_ctl(hw,
8780                                                           I40E_GLQF_HSYM(j),
8781                                                           reg);
8782                         }
8783                 }
8784         }
8785
8786         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8787         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8788                 /* Toeplitz */
8789                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8790                         PMD_DRV_LOG(DEBUG,
8791                                 "Hash function already set to Toeplitz");
8792                         goto out;
8793                 }
8794                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8795         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8796                 /* Simple XOR */
8797                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8798                         PMD_DRV_LOG(DEBUG,
8799                                 "Hash function already set to Simple XOR");
8800                         goto out;
8801                 }
8802                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8803         } else
8804                 /* Use the default, and keep it as it is */
8805                 goto out;
8806
8807         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8808
8809 out:
8810         I40E_WRITE_FLUSH(hw);
8811
8812         return 0;
8813 }
8814
8815 /**
8816  * Valid input sets for hash and flow director filters per PCTYPE
8817  */
8818 static uint64_t
8819 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8820                 enum rte_filter_type filter)
8821 {
8822         uint64_t valid;
8823
8824         static const uint64_t valid_hash_inset_table[] = {
8825                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8826                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8827                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8828                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8829                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8830                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8831                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8832                         I40E_INSET_FLEX_PAYLOAD,
8833                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8834                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8835                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8836                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8837                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8838                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8839                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8840                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8841                         I40E_INSET_FLEX_PAYLOAD,
8842                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8843                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8844                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8845                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8846                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8847                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8848                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8849                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8850                         I40E_INSET_FLEX_PAYLOAD,
8851                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8852                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8853                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8854                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8855                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8856                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8857                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8858                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8859                         I40E_INSET_FLEX_PAYLOAD,
8860                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8861                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8862                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8863                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8864                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8865                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8866                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8867                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8868                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8869                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8870                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8871                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8872                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8873                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8874                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8875                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8876                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8877                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8878                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8879                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8880                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8881                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8882                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8883                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8884                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8885                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8886                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8887                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8888                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8889                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8890                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8891                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8892                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8893                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8894                         I40E_INSET_FLEX_PAYLOAD,
8895                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8896                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8897                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8898                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8899                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8900                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8901                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8902                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8903                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8904                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8905                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8906                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8907                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8908                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8909                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8910                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8911                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8912                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8913                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8914                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8915                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8916                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8917                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8918                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8919                         I40E_INSET_FLEX_PAYLOAD,
8920                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8921                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8922                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8923                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8924                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8925                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8926                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8927                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8928                         I40E_INSET_FLEX_PAYLOAD,
8929                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8930                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8931                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8932                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8933                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8934                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8935                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8936                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8937                         I40E_INSET_FLEX_PAYLOAD,
8938                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8939                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8940                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8941                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8942                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8943                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8944                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8945                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8946                         I40E_INSET_FLEX_PAYLOAD,
8947                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8948                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8949                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8950                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8951                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8952                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8953                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8954                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8955                         I40E_INSET_FLEX_PAYLOAD,
8956                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8957                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8958                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8959                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8960                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8961                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8962                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8963                         I40E_INSET_FLEX_PAYLOAD,
8964                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8965                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8966                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8967                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8968                         I40E_INSET_FLEX_PAYLOAD,
8969         };
8970
8971         /**
8972          * Flow director supports only fields defined in
8973          * union rte_eth_fdir_flow.
8974          */
8975         static const uint64_t valid_fdir_inset_table[] = {
8976                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8977                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8978                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8979                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8980                 I40E_INSET_IPV4_TTL,
8981                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8982                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8983                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8984                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8985                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8986                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8987                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8988                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8989                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8990                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8991                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8992                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8993                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8994                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8995                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8996                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8997                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8998                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8999                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9000                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9001                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9002                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9003                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9004                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9005                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9006                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9007                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9008                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9009                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9010                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9011                 I40E_INSET_SCTP_VT,
9012                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9013                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9014                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9015                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9016                 I40E_INSET_IPV4_TTL,
9017                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9018                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9019                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9020                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9021                 I40E_INSET_IPV6_HOP_LIMIT,
9022                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9023                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9024                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9025                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9026                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9027                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9028                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9029                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9030                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9031                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9032                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9033                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9034                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9035                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9036                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9037                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9038                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9039                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9040                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9041                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9042                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9043                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9044                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9045                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9046                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9047                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9048                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9049                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9050                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9051                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9052                 I40E_INSET_SCTP_VT,
9053                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9054                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9055                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9056                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9057                 I40E_INSET_IPV6_HOP_LIMIT,
9058                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9059                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9060                 I40E_INSET_LAST_ETHER_TYPE,
9061         };
9062
9063         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9064                 return 0;
9065         if (filter == RTE_ETH_FILTER_HASH)
9066                 valid = valid_hash_inset_table[pctype];
9067         else
9068                 valid = valid_fdir_inset_table[pctype];
9069
9070         return valid;
9071 }
9072
9073 /**
9074  * Validate if the input set is allowed for a specific PCTYPE
9075  */
9076 int
9077 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9078                 enum rte_filter_type filter, uint64_t inset)
9079 {
9080         uint64_t valid;
9081
9082         valid = i40e_get_valid_input_set(pctype, filter);
9083         if (inset & (~valid))
9084                 return -EINVAL;
9085
9086         return 0;
9087 }
9088
9089 /* default input set fields combination per pctype */
9090 uint64_t
9091 i40e_get_default_input_set(uint16_t pctype)
9092 {
9093         static const uint64_t default_inset_table[] = {
9094                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9095                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9096                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9097                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9098                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9099                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9100                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9101                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9102                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9103                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9104                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9105                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9106                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9107                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9108                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9109                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9110                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9111                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9112                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9113                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9114                         I40E_INSET_SCTP_VT,
9115                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9116                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9117                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9118                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9119                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9120                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9121                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9122                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9123                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9124                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9125                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9126                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9127                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9128                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9129                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9130                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9131                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9132                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9133                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9134                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9135                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9136                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9137                         I40E_INSET_SCTP_VT,
9138                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9139                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9140                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9141                         I40E_INSET_LAST_ETHER_TYPE,
9142         };
9143
9144         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9145                 return 0;
9146
9147         return default_inset_table[pctype];
9148 }
9149
9150 /**
9151  * Parse the input set from index to logical bit masks
9152  */
9153 static int
9154 i40e_parse_input_set(uint64_t *inset,
9155                      enum i40e_filter_pctype pctype,
9156                      enum rte_eth_input_set_field *field,
9157                      uint16_t size)
9158 {
9159         uint16_t i, j;
9160         int ret = -EINVAL;
9161
9162         static const struct {
9163                 enum rte_eth_input_set_field field;
9164                 uint64_t inset;
9165         } inset_convert_table[] = {
9166                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9167                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9168                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9169                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9170                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9171                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9172                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9173                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9174                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9175                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9176                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9177                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9178                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9179                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9180                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9181                         I40E_INSET_IPV6_NEXT_HDR},
9182                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9183                         I40E_INSET_IPV6_HOP_LIMIT},
9184                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9185                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9186                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9187                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9188                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9189                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9190                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9191                         I40E_INSET_SCTP_VT},
9192                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9193                         I40E_INSET_TUNNEL_DMAC},
9194                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9195                         I40E_INSET_VLAN_TUNNEL},
9196                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9197                         I40E_INSET_TUNNEL_ID},
9198                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9199                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9200                         I40E_INSET_FLEX_PAYLOAD_W1},
9201                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9202                         I40E_INSET_FLEX_PAYLOAD_W2},
9203                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9204                         I40E_INSET_FLEX_PAYLOAD_W3},
9205                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9206                         I40E_INSET_FLEX_PAYLOAD_W4},
9207                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9208                         I40E_INSET_FLEX_PAYLOAD_W5},
9209                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9210                         I40E_INSET_FLEX_PAYLOAD_W6},
9211                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9212                         I40E_INSET_FLEX_PAYLOAD_W7},
9213                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9214                         I40E_INSET_FLEX_PAYLOAD_W8},
9215         };
9216
9217         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9218                 return ret;
9219
9220         /* Only one item allowed for default or all */
9221         if (size == 1) {
9222                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9223                         *inset = i40e_get_default_input_set(pctype);
9224                         return 0;
9225                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9226                         *inset = I40E_INSET_NONE;
9227                         return 0;
9228                 }
9229         }
9230
9231         for (i = 0, *inset = 0; i < size; i++) {
9232                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9233                         if (field[i] == inset_convert_table[j].field) {
9234                                 *inset |= inset_convert_table[j].inset;
9235                                 break;
9236                         }
9237                 }
9238
9239                 /* It contains unsupported input set, return immediately */
9240                 if (j == RTE_DIM(inset_convert_table))
9241                         return ret;
9242         }
9243
9244         return 0;
9245 }
9246
9247 /**
9248  * Translate the input set from bit masks to register aware bit masks
9249  * and vice versa
9250  */
9251 uint64_t
9252 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9253 {
9254         uint64_t val = 0;
9255         uint16_t i;
9256
9257         struct inset_map {
9258                 uint64_t inset;
9259                 uint64_t inset_reg;
9260         };
9261
9262         static const struct inset_map inset_map_common[] = {
9263                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9264                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9265                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9266                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9267                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9268                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9269                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9270                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9271                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9272                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9273                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9274                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9275                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9276                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9277                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9278                 {I40E_INSET_TUNNEL_DMAC,
9279                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9280                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9281                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9282                 {I40E_INSET_TUNNEL_SRC_PORT,
9283                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9284                 {I40E_INSET_TUNNEL_DST_PORT,
9285                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9286                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9287                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9288                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9289                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9290                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9291                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9292                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9293                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9294                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9295         };
9296
9297     /* some different registers map in x722*/
9298         static const struct inset_map inset_map_diff_x722[] = {
9299                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9300                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9301                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9302                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9303         };
9304
9305         static const struct inset_map inset_map_diff_not_x722[] = {
9306                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9307                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9308                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9309                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9310         };
9311
9312         if (input == 0)
9313                 return val;
9314
9315         /* Translate input set to register aware inset */
9316         if (type == I40E_MAC_X722) {
9317                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9318                         if (input & inset_map_diff_x722[i].inset)
9319                                 val |= inset_map_diff_x722[i].inset_reg;
9320                 }
9321         } else {
9322                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9323                         if (input & inset_map_diff_not_x722[i].inset)
9324                                 val |= inset_map_diff_not_x722[i].inset_reg;
9325                 }
9326         }
9327
9328         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9329                 if (input & inset_map_common[i].inset)
9330                         val |= inset_map_common[i].inset_reg;
9331         }
9332
9333         return val;
9334 }
9335
9336 int
9337 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9338 {
9339         uint8_t i, idx = 0;
9340         uint64_t inset_need_mask = inset;
9341
9342         static const struct {
9343                 uint64_t inset;
9344                 uint32_t mask;
9345         } inset_mask_map[] = {
9346                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9347                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9348                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9349                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9350                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9351                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9352                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9353                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9354         };
9355
9356         if (!inset || !mask || !nb_elem)
9357                 return 0;
9358
9359         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9360                 /* Clear the inset bit, if no MASK is required,
9361                  * for example proto + ttl
9362                  */
9363                 if ((inset & inset_mask_map[i].inset) ==
9364                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9365                         inset_need_mask &= ~inset_mask_map[i].inset;
9366                 if (!inset_need_mask)
9367                         return 0;
9368         }
9369         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9370                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9371                     inset_mask_map[i].inset) {
9372                         if (idx >= nb_elem) {
9373                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9374                                 return -EINVAL;
9375                         }
9376                         mask[idx] = inset_mask_map[i].mask;
9377                         idx++;
9378                 }
9379         }
9380
9381         return idx;
9382 }
9383
9384 void
9385 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9386 {
9387         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9388
9389         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9390         if (reg != val)
9391                 i40e_write_rx_ctl(hw, addr, val);
9392         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9393                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9394 }
9395
9396 void
9397 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9398 {
9399         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9400         struct rte_eth_dev *dev;
9401
9402         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9403         if (reg != val) {
9404                 i40e_write_rx_ctl(hw, addr, val);
9405                 PMD_DRV_LOG(WARNING,
9406                             "i40e device %s changed global register [0x%08x]."
9407                             " original: 0x%08x, new: 0x%08x",
9408                             dev->device->name, addr, reg,
9409                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9410         }
9411 }
9412
9413 static void
9414 i40e_filter_input_set_init(struct i40e_pf *pf)
9415 {
9416         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9417         enum i40e_filter_pctype pctype;
9418         uint64_t input_set, inset_reg;
9419         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9420         int num, i;
9421         uint16_t flow_type;
9422
9423         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9424              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9425                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9426
9427                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9428                         continue;
9429
9430                 input_set = i40e_get_default_input_set(pctype);
9431
9432                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9433                                                    I40E_INSET_MASK_NUM_REG);
9434                 if (num < 0)
9435                         return;
9436                 if (pf->support_multi_driver && num > 0) {
9437                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9438                         return;
9439                 }
9440                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9441                                         input_set);
9442
9443                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9444                                       (uint32_t)(inset_reg & UINT32_MAX));
9445                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9446                                      (uint32_t)((inset_reg >>
9447                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9448                 if (!pf->support_multi_driver) {
9449                         i40e_check_write_global_reg(hw,
9450                                             I40E_GLQF_HASH_INSET(0, pctype),
9451                                             (uint32_t)(inset_reg & UINT32_MAX));
9452                         i40e_check_write_global_reg(hw,
9453                                              I40E_GLQF_HASH_INSET(1, pctype),
9454                                              (uint32_t)((inset_reg >>
9455                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9456
9457                         for (i = 0; i < num; i++) {
9458                                 i40e_check_write_global_reg(hw,
9459                                                     I40E_GLQF_FD_MSK(i, pctype),
9460                                                     mask_reg[i]);
9461                                 i40e_check_write_global_reg(hw,
9462                                                   I40E_GLQF_HASH_MSK(i, pctype),
9463                                                   mask_reg[i]);
9464                         }
9465                         /*clear unused mask registers of the pctype */
9466                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9467                                 i40e_check_write_global_reg(hw,
9468                                                     I40E_GLQF_FD_MSK(i, pctype),
9469                                                     0);
9470                                 i40e_check_write_global_reg(hw,
9471                                                   I40E_GLQF_HASH_MSK(i, pctype),
9472                                                   0);
9473                         }
9474                 } else {
9475                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9476                 }
9477                 I40E_WRITE_FLUSH(hw);
9478
9479                 /* store the default input set */
9480                 if (!pf->support_multi_driver)
9481                         pf->hash_input_set[pctype] = input_set;
9482                 pf->fdir.input_set[pctype] = input_set;
9483         }
9484 }
9485
9486 int
9487 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9488                          struct rte_eth_input_set_conf *conf)
9489 {
9490         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9491         enum i40e_filter_pctype pctype;
9492         uint64_t input_set, inset_reg = 0;
9493         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9494         int ret, i, num;
9495
9496         if (!conf) {
9497                 PMD_DRV_LOG(ERR, "Invalid pointer");
9498                 return -EFAULT;
9499         }
9500         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9501             conf->op != RTE_ETH_INPUT_SET_ADD) {
9502                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9503                 return -EINVAL;
9504         }
9505
9506         if (pf->support_multi_driver) {
9507                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9508                 return -ENOTSUP;
9509         }
9510
9511         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9512         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9513                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9514                 return -EINVAL;
9515         }
9516
9517         if (hw->mac.type == I40E_MAC_X722) {
9518                 /* get translated pctype value in fd pctype register */
9519                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9520                         I40E_GLQF_FD_PCTYPES((int)pctype));
9521         }
9522
9523         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9524                                    conf->inset_size);
9525         if (ret) {
9526                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9527                 return -EINVAL;
9528         }
9529
9530         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9531                 /* get inset value in register */
9532                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9533                 inset_reg <<= I40E_32_BIT_WIDTH;
9534                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9535                 input_set |= pf->hash_input_set[pctype];
9536         }
9537         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9538                                            I40E_INSET_MASK_NUM_REG);
9539         if (num < 0)
9540                 return -EINVAL;
9541
9542         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9543
9544         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9545                                     (uint32_t)(inset_reg & UINT32_MAX));
9546         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9547                                     (uint32_t)((inset_reg >>
9548                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9549
9550         for (i = 0; i < num; i++)
9551                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9552                                             mask_reg[i]);
9553         /*clear unused mask registers of the pctype */
9554         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9555                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9556                                             0);
9557         I40E_WRITE_FLUSH(hw);
9558
9559         pf->hash_input_set[pctype] = input_set;
9560         return 0;
9561 }
9562
9563 int
9564 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9565                          struct rte_eth_input_set_conf *conf)
9566 {
9567         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9568         enum i40e_filter_pctype pctype;
9569         uint64_t input_set, inset_reg = 0;
9570         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9571         int ret, i, num;
9572
9573         if (!hw || !conf) {
9574                 PMD_DRV_LOG(ERR, "Invalid pointer");
9575                 return -EFAULT;
9576         }
9577         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9578             conf->op != RTE_ETH_INPUT_SET_ADD) {
9579                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9580                 return -EINVAL;
9581         }
9582
9583         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9584
9585         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9586                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9587                 return -EINVAL;
9588         }
9589
9590         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9591                                    conf->inset_size);
9592         if (ret) {
9593                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9594                 return -EINVAL;
9595         }
9596
9597         /* get inset value in register */
9598         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9599         inset_reg <<= I40E_32_BIT_WIDTH;
9600         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9601
9602         /* Can not change the inset reg for flex payload for fdir,
9603          * it is done by writing I40E_PRTQF_FD_FLXINSET
9604          * in i40e_set_flex_mask_on_pctype.
9605          */
9606         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9607                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9608         else
9609                 input_set |= pf->fdir.input_set[pctype];
9610         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9611                                            I40E_INSET_MASK_NUM_REG);
9612         if (num < 0)
9613                 return -EINVAL;
9614         if (pf->support_multi_driver && num > 0) {
9615                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9616                 return -ENOTSUP;
9617         }
9618
9619         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9620
9621         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9622                               (uint32_t)(inset_reg & UINT32_MAX));
9623         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9624                              (uint32_t)((inset_reg >>
9625                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9626
9627         if (!pf->support_multi_driver) {
9628                 for (i = 0; i < num; i++)
9629                         i40e_check_write_global_reg(hw,
9630                                                     I40E_GLQF_FD_MSK(i, pctype),
9631                                                     mask_reg[i]);
9632                 /*clear unused mask registers of the pctype */
9633                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9634                         i40e_check_write_global_reg(hw,
9635                                                     I40E_GLQF_FD_MSK(i, pctype),
9636                                                     0);
9637         } else {
9638                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9639         }
9640         I40E_WRITE_FLUSH(hw);
9641
9642         pf->fdir.input_set[pctype] = input_set;
9643         return 0;
9644 }
9645
9646 static int
9647 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9648 {
9649         int ret = 0;
9650
9651         if (!hw || !info) {
9652                 PMD_DRV_LOG(ERR, "Invalid pointer");
9653                 return -EFAULT;
9654         }
9655
9656         switch (info->info_type) {
9657         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9658                 i40e_get_symmetric_hash_enable_per_port(hw,
9659                                         &(info->info.enable));
9660                 break;
9661         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9662                 ret = i40e_get_hash_filter_global_config(hw,
9663                                 &(info->info.global_conf));
9664                 break;
9665         default:
9666                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9667                                                         info->info_type);
9668                 ret = -EINVAL;
9669                 break;
9670         }
9671
9672         return ret;
9673 }
9674
9675 static int
9676 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9677 {
9678         int ret = 0;
9679
9680         if (!hw || !info) {
9681                 PMD_DRV_LOG(ERR, "Invalid pointer");
9682                 return -EFAULT;
9683         }
9684
9685         switch (info->info_type) {
9686         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9687                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9688                 break;
9689         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9690                 ret = i40e_set_hash_filter_global_config(hw,
9691                                 &(info->info.global_conf));
9692                 break;
9693         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9694                 ret = i40e_hash_filter_inset_select(hw,
9695                                                &(info->info.input_set_conf));
9696                 break;
9697
9698         default:
9699                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9700                                                         info->info_type);
9701                 ret = -EINVAL;
9702                 break;
9703         }
9704
9705         return ret;
9706 }
9707
9708 /* Operations for hash function */
9709 static int
9710 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9711                       enum rte_filter_op filter_op,
9712                       void *arg)
9713 {
9714         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9715         int ret = 0;
9716
9717         switch (filter_op) {
9718         case RTE_ETH_FILTER_NOP:
9719                 break;
9720         case RTE_ETH_FILTER_GET:
9721                 ret = i40e_hash_filter_get(hw,
9722                         (struct rte_eth_hash_filter_info *)arg);
9723                 break;
9724         case RTE_ETH_FILTER_SET:
9725                 ret = i40e_hash_filter_set(hw,
9726                         (struct rte_eth_hash_filter_info *)arg);
9727                 break;
9728         default:
9729                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9730                                                                 filter_op);
9731                 ret = -ENOTSUP;
9732                 break;
9733         }
9734
9735         return ret;
9736 }
9737
9738 /* Convert ethertype filter structure */
9739 static int
9740 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9741                               struct i40e_ethertype_filter *filter)
9742 {
9743         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9744         filter->input.ether_type = input->ether_type;
9745         filter->flags = input->flags;
9746         filter->queue = input->queue;
9747
9748         return 0;
9749 }
9750
9751 /* Check if there exists the ehtertype filter */
9752 struct i40e_ethertype_filter *
9753 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9754                                 const struct i40e_ethertype_filter_input *input)
9755 {
9756         int ret;
9757
9758         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9759         if (ret < 0)
9760                 return NULL;
9761
9762         return ethertype_rule->hash_map[ret];
9763 }
9764
9765 /* Add ethertype filter in SW list */
9766 static int
9767 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9768                                 struct i40e_ethertype_filter *filter)
9769 {
9770         struct i40e_ethertype_rule *rule = &pf->ethertype;
9771         int ret;
9772
9773         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9774         if (ret < 0) {
9775                 PMD_DRV_LOG(ERR,
9776                             "Failed to insert ethertype filter"
9777                             " to hash table %d!",
9778                             ret);
9779                 return ret;
9780         }
9781         rule->hash_map[ret] = filter;
9782
9783         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9784
9785         return 0;
9786 }
9787
9788 /* Delete ethertype filter in SW list */
9789 int
9790 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9791                              struct i40e_ethertype_filter_input *input)
9792 {
9793         struct i40e_ethertype_rule *rule = &pf->ethertype;
9794         struct i40e_ethertype_filter *filter;
9795         int ret;
9796
9797         ret = rte_hash_del_key(rule->hash_table, input);
9798         if (ret < 0) {
9799                 PMD_DRV_LOG(ERR,
9800                             "Failed to delete ethertype filter"
9801                             " to hash table %d!",
9802                             ret);
9803                 return ret;
9804         }
9805         filter = rule->hash_map[ret];
9806         rule->hash_map[ret] = NULL;
9807
9808         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9809         rte_free(filter);
9810
9811         return 0;
9812 }
9813
9814 /*
9815  * Configure ethertype filter, which can director packet by filtering
9816  * with mac address and ether_type or only ether_type
9817  */
9818 int
9819 i40e_ethertype_filter_set(struct i40e_pf *pf,
9820                         struct rte_eth_ethertype_filter *filter,
9821                         bool add)
9822 {
9823         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9824         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9825         struct i40e_ethertype_filter *ethertype_filter, *node;
9826         struct i40e_ethertype_filter check_filter;
9827         struct i40e_control_filter_stats stats;
9828         uint16_t flags = 0;
9829         int ret;
9830
9831         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9832                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9833                 return -EINVAL;
9834         }
9835         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9836                 filter->ether_type == ETHER_TYPE_IPv6) {
9837                 PMD_DRV_LOG(ERR,
9838                         "unsupported ether_type(0x%04x) in control packet filter.",
9839                         filter->ether_type);
9840                 return -EINVAL;
9841         }
9842         if (filter->ether_type == ETHER_TYPE_VLAN)
9843                 PMD_DRV_LOG(WARNING,
9844                         "filter vlan ether_type in first tag is not supported.");
9845
9846         /* Check if there is the filter in SW list */
9847         memset(&check_filter, 0, sizeof(check_filter));
9848         i40e_ethertype_filter_convert(filter, &check_filter);
9849         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9850                                                &check_filter.input);
9851         if (add && node) {
9852                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9853                 return -EINVAL;
9854         }
9855
9856         if (!add && !node) {
9857                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9858                 return -EINVAL;
9859         }
9860
9861         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9862                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9863         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9864                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9865         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9866
9867         memset(&stats, 0, sizeof(stats));
9868         ret = i40e_aq_add_rem_control_packet_filter(hw,
9869                         filter->mac_addr.addr_bytes,
9870                         filter->ether_type, flags,
9871                         pf->main_vsi->seid,
9872                         filter->queue, add, &stats, NULL);
9873
9874         PMD_DRV_LOG(INFO,
9875                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9876                 ret, stats.mac_etype_used, stats.etype_used,
9877                 stats.mac_etype_free, stats.etype_free);
9878         if (ret < 0)
9879                 return -ENOSYS;
9880
9881         /* Add or delete a filter in SW list */
9882         if (add) {
9883                 ethertype_filter = rte_zmalloc("ethertype_filter",
9884                                        sizeof(*ethertype_filter), 0);
9885                 if (ethertype_filter == NULL) {
9886                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9887                         return -ENOMEM;
9888                 }
9889
9890                 rte_memcpy(ethertype_filter, &check_filter,
9891                            sizeof(check_filter));
9892                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9893                 if (ret < 0)
9894                         rte_free(ethertype_filter);
9895         } else {
9896                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9897         }
9898
9899         return ret;
9900 }
9901
9902 /*
9903  * Handle operations for ethertype filter.
9904  */
9905 static int
9906 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9907                                 enum rte_filter_op filter_op,
9908                                 void *arg)
9909 {
9910         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9911         int ret = 0;
9912
9913         if (filter_op == RTE_ETH_FILTER_NOP)
9914                 return ret;
9915
9916         if (arg == NULL) {
9917                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9918                             filter_op);
9919                 return -EINVAL;
9920         }
9921
9922         switch (filter_op) {
9923         case RTE_ETH_FILTER_ADD:
9924                 ret = i40e_ethertype_filter_set(pf,
9925                         (struct rte_eth_ethertype_filter *)arg,
9926                         TRUE);
9927                 break;
9928         case RTE_ETH_FILTER_DELETE:
9929                 ret = i40e_ethertype_filter_set(pf,
9930                         (struct rte_eth_ethertype_filter *)arg,
9931                         FALSE);
9932                 break;
9933         default:
9934                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9935                 ret = -ENOSYS;
9936                 break;
9937         }
9938         return ret;
9939 }
9940
9941 static int
9942 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9943                      enum rte_filter_type filter_type,
9944                      enum rte_filter_op filter_op,
9945                      void *arg)
9946 {
9947         int ret = 0;
9948
9949         if (dev == NULL)
9950                 return -EINVAL;
9951
9952         switch (filter_type) {
9953         case RTE_ETH_FILTER_NONE:
9954                 /* For global configuration */
9955                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9956                 break;
9957         case RTE_ETH_FILTER_HASH:
9958                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9959                 break;
9960         case RTE_ETH_FILTER_MACVLAN:
9961                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9962                 break;
9963         case RTE_ETH_FILTER_ETHERTYPE:
9964                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9965                 break;
9966         case RTE_ETH_FILTER_TUNNEL:
9967                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9968                 break;
9969         case RTE_ETH_FILTER_FDIR:
9970                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9971                 break;
9972         case RTE_ETH_FILTER_GENERIC:
9973                 if (filter_op != RTE_ETH_FILTER_GET)
9974                         return -EINVAL;
9975                 *(const void **)arg = &i40e_flow_ops;
9976                 break;
9977         default:
9978                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9979                                                         filter_type);
9980                 ret = -EINVAL;
9981                 break;
9982         }
9983
9984         return ret;
9985 }
9986
9987 /*
9988  * Check and enable Extended Tag.
9989  * Enabling Extended Tag is important for 40G performance.
9990  */
9991 static void
9992 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9993 {
9994         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9995         uint32_t buf = 0;
9996         int ret;
9997
9998         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9999                                       PCI_DEV_CAP_REG);
10000         if (ret < 0) {
10001                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10002                             PCI_DEV_CAP_REG);
10003                 return;
10004         }
10005         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10006                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10007                 return;
10008         }
10009
10010         buf = 0;
10011         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10012                                       PCI_DEV_CTRL_REG);
10013         if (ret < 0) {
10014                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10015                             PCI_DEV_CTRL_REG);
10016                 return;
10017         }
10018         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10019                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10020                 return;
10021         }
10022         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10023         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10024                                        PCI_DEV_CTRL_REG);
10025         if (ret < 0) {
10026                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10027                             PCI_DEV_CTRL_REG);
10028                 return;
10029         }
10030 }
10031
10032 /*
10033  * As some registers wouldn't be reset unless a global hardware reset,
10034  * hardware initialization is needed to put those registers into an
10035  * expected initial state.
10036  */
10037 static void
10038 i40e_hw_init(struct rte_eth_dev *dev)
10039 {
10040         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10041
10042         i40e_enable_extended_tag(dev);
10043
10044         /* clear the PF Queue Filter control register */
10045         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10046
10047         /* Disable symmetric hash per port */
10048         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10049 }
10050
10051 /*
10052  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10053  * however this function will return only one highest pctype index,
10054  * which is not quite correct. This is known problem of i40e driver
10055  * and needs to be fixed later.
10056  */
10057 enum i40e_filter_pctype
10058 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10059 {
10060         int i;
10061         uint64_t pctype_mask;
10062
10063         if (flow_type < I40E_FLOW_TYPE_MAX) {
10064                 pctype_mask = adapter->pctypes_tbl[flow_type];
10065                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10066                         if (pctype_mask & (1ULL << i))
10067                                 return (enum i40e_filter_pctype)i;
10068                 }
10069         }
10070         return I40E_FILTER_PCTYPE_INVALID;
10071 }
10072
10073 uint16_t
10074 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10075                         enum i40e_filter_pctype pctype)
10076 {
10077         uint16_t flowtype;
10078         uint64_t pctype_mask = 1ULL << pctype;
10079
10080         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10081              flowtype++) {
10082                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10083                         return flowtype;
10084         }
10085
10086         return RTE_ETH_FLOW_UNKNOWN;
10087 }
10088
10089 /*
10090  * On X710, performance number is far from the expectation on recent firmware
10091  * versions; on XL710, performance number is also far from the expectation on
10092  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10093  * mode is enabled and port MAC address is equal to the packet destination MAC
10094  * address. The fix for this issue may not be integrated in the following
10095  * firmware version. So the workaround in software driver is needed. It needs
10096  * to modify the initial values of 3 internal only registers for both X710 and
10097  * XL710. Note that the values for X710 or XL710 could be different, and the
10098  * workaround can be removed when it is fixed in firmware in the future.
10099  */
10100
10101 /* For both X710 and XL710 */
10102 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10103 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10104 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10105
10106 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10107 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10108
10109 /* For X722 */
10110 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10111 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10112
10113 /* For X710 */
10114 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10115 /* For XL710 */
10116 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10117 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10118
10119 /*
10120  * GL_SWR_PM_UP_THR:
10121  * The value is not impacted from the link speed, its value is set according
10122  * to the total number of ports for a better pipe-monitor configuration.
10123  */
10124 static bool
10125 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10126 {
10127 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10128                 .device_id = (dev),   \
10129                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10130
10131 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10132                 .device_id = (dev),   \
10133                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10134
10135         static const struct {
10136                 uint16_t device_id;
10137                 uint32_t val;
10138         } swr_pm_table[] = {
10139                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10140                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10141                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10142                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10143
10144                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10145                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10146                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10147                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10148                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10149                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10150                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10151         };
10152         uint32_t i;
10153
10154         if (value == NULL) {
10155                 PMD_DRV_LOG(ERR, "value is NULL");
10156                 return false;
10157         }
10158
10159         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10160                 if (hw->device_id == swr_pm_table[i].device_id) {
10161                         *value = swr_pm_table[i].val;
10162
10163                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10164                                     "value - 0x%08x",
10165                                     hw->device_id, *value);
10166                         return true;
10167                 }
10168         }
10169
10170         return false;
10171 }
10172
10173 static int
10174 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10175 {
10176         enum i40e_status_code status;
10177         struct i40e_aq_get_phy_abilities_resp phy_ab;
10178         int ret = -ENOTSUP;
10179         int retries = 0;
10180
10181         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10182                                               NULL);
10183
10184         while (status) {
10185                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10186                         status);
10187                 retries++;
10188                 rte_delay_us(100000);
10189                 if  (retries < 5)
10190                         status = i40e_aq_get_phy_capabilities(hw, false,
10191                                         true, &phy_ab, NULL);
10192                 else
10193                         return ret;
10194         }
10195         return 0;
10196 }
10197
10198 static void
10199 i40e_configure_registers(struct i40e_hw *hw)
10200 {
10201         static struct {
10202                 uint32_t addr;
10203                 uint64_t val;
10204         } reg_table[] = {
10205                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10206                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10207                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10208         };
10209         uint64_t reg;
10210         uint32_t i;
10211         int ret;
10212
10213         for (i = 0; i < RTE_DIM(reg_table); i++) {
10214                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10215                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10216                                 reg_table[i].val =
10217                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10218                         else /* For X710/XL710/XXV710 */
10219                                 if (hw->aq.fw_maj_ver < 6)
10220                                         reg_table[i].val =
10221                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10222                                 else
10223                                         reg_table[i].val =
10224                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10225                 }
10226
10227                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10228                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10229                                 reg_table[i].val =
10230                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10231                         else /* For X710/XL710/XXV710 */
10232                                 reg_table[i].val =
10233                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10234                 }
10235
10236                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10237                         uint32_t cfg_val;
10238
10239                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10240                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10241                                             "GL_SWR_PM_UP_THR value fixup",
10242                                             hw->device_id);
10243                                 continue;
10244                         }
10245
10246                         reg_table[i].val = cfg_val;
10247                 }
10248
10249                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10250                                                         &reg, NULL);
10251                 if (ret < 0) {
10252                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10253                                                         reg_table[i].addr);
10254                         break;
10255                 }
10256                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10257                                                 reg_table[i].addr, reg);
10258                 if (reg == reg_table[i].val)
10259                         continue;
10260
10261                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10262                                                 reg_table[i].val, NULL);
10263                 if (ret < 0) {
10264                         PMD_DRV_LOG(ERR,
10265                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10266                                 reg_table[i].val, reg_table[i].addr);
10267                         break;
10268                 }
10269                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10270                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10271         }
10272 }
10273
10274 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10275 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10276 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10277 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10278 static int
10279 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10280 {
10281         uint32_t reg;
10282         int ret;
10283
10284         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10285                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10286                 return -EINVAL;
10287         }
10288
10289         /* Configure for double VLAN RX stripping */
10290         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10291         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10292                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10293                 ret = i40e_aq_debug_write_register(hw,
10294                                                    I40E_VSI_TSR(vsi->vsi_id),
10295                                                    reg, NULL);
10296                 if (ret < 0) {
10297                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10298                                     vsi->vsi_id);
10299                         return I40E_ERR_CONFIG;
10300                 }
10301         }
10302
10303         /* Configure for double VLAN TX insertion */
10304         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10305         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10306                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10307                 ret = i40e_aq_debug_write_register(hw,
10308                                                    I40E_VSI_L2TAGSTXVALID(
10309                                                    vsi->vsi_id), reg, NULL);
10310                 if (ret < 0) {
10311                         PMD_DRV_LOG(ERR,
10312                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10313                                 vsi->vsi_id);
10314                         return I40E_ERR_CONFIG;
10315                 }
10316         }
10317
10318         return 0;
10319 }
10320
10321 /**
10322  * i40e_aq_add_mirror_rule
10323  * @hw: pointer to the hardware structure
10324  * @seid: VEB seid to add mirror rule to
10325  * @dst_id: destination vsi seid
10326  * @entries: Buffer which contains the entities to be mirrored
10327  * @count: number of entities contained in the buffer
10328  * @rule_id:the rule_id of the rule to be added
10329  *
10330  * Add a mirror rule for a given veb.
10331  *
10332  **/
10333 static enum i40e_status_code
10334 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10335                         uint16_t seid, uint16_t dst_id,
10336                         uint16_t rule_type, uint16_t *entries,
10337                         uint16_t count, uint16_t *rule_id)
10338 {
10339         struct i40e_aq_desc desc;
10340         struct i40e_aqc_add_delete_mirror_rule cmd;
10341         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10342                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10343                 &desc.params.raw;
10344         uint16_t buff_len;
10345         enum i40e_status_code status;
10346
10347         i40e_fill_default_direct_cmd_desc(&desc,
10348                                           i40e_aqc_opc_add_mirror_rule);
10349         memset(&cmd, 0, sizeof(cmd));
10350
10351         buff_len = sizeof(uint16_t) * count;
10352         desc.datalen = rte_cpu_to_le_16(buff_len);
10353         if (buff_len > 0)
10354                 desc.flags |= rte_cpu_to_le_16(
10355                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10356         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10357                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10358         cmd.num_entries = rte_cpu_to_le_16(count);
10359         cmd.seid = rte_cpu_to_le_16(seid);
10360         cmd.destination = rte_cpu_to_le_16(dst_id);
10361
10362         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10363         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10364         PMD_DRV_LOG(INFO,
10365                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10366                 hw->aq.asq_last_status, resp->rule_id,
10367                 resp->mirror_rules_used, resp->mirror_rules_free);
10368         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10369
10370         return status;
10371 }
10372
10373 /**
10374  * i40e_aq_del_mirror_rule
10375  * @hw: pointer to the hardware structure
10376  * @seid: VEB seid to add mirror rule to
10377  * @entries: Buffer which contains the entities to be mirrored
10378  * @count: number of entities contained in the buffer
10379  * @rule_id:the rule_id of the rule to be delete
10380  *
10381  * Delete a mirror rule for a given veb.
10382  *
10383  **/
10384 static enum i40e_status_code
10385 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10386                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10387                 uint16_t count, uint16_t rule_id)
10388 {
10389         struct i40e_aq_desc desc;
10390         struct i40e_aqc_add_delete_mirror_rule cmd;
10391         uint16_t buff_len = 0;
10392         enum i40e_status_code status;
10393         void *buff = NULL;
10394
10395         i40e_fill_default_direct_cmd_desc(&desc,
10396                                           i40e_aqc_opc_delete_mirror_rule);
10397         memset(&cmd, 0, sizeof(cmd));
10398         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10399                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10400                                                           I40E_AQ_FLAG_RD));
10401                 cmd.num_entries = count;
10402                 buff_len = sizeof(uint16_t) * count;
10403                 desc.datalen = rte_cpu_to_le_16(buff_len);
10404                 buff = (void *)entries;
10405         } else
10406                 /* rule id is filled in destination field for deleting mirror rule */
10407                 cmd.destination = rte_cpu_to_le_16(rule_id);
10408
10409         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10410                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10411         cmd.seid = rte_cpu_to_le_16(seid);
10412
10413         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10414         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10415
10416         return status;
10417 }
10418
10419 /**
10420  * i40e_mirror_rule_set
10421  * @dev: pointer to the hardware structure
10422  * @mirror_conf: mirror rule info
10423  * @sw_id: mirror rule's sw_id
10424  * @on: enable/disable
10425  *
10426  * set a mirror rule.
10427  *
10428  **/
10429 static int
10430 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10431                         struct rte_eth_mirror_conf *mirror_conf,
10432                         uint8_t sw_id, uint8_t on)
10433 {
10434         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10435         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10436         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10437         struct i40e_mirror_rule *parent = NULL;
10438         uint16_t seid, dst_seid, rule_id;
10439         uint16_t i, j = 0;
10440         int ret;
10441
10442         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10443
10444         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10445                 PMD_DRV_LOG(ERR,
10446                         "mirror rule can not be configured without veb or vfs.");
10447                 return -ENOSYS;
10448         }
10449         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10450                 PMD_DRV_LOG(ERR, "mirror table is full.");
10451                 return -ENOSPC;
10452         }
10453         if (mirror_conf->dst_pool > pf->vf_num) {
10454                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10455                                  mirror_conf->dst_pool);
10456                 return -EINVAL;
10457         }
10458
10459         seid = pf->main_vsi->veb->seid;
10460
10461         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10462                 if (sw_id <= it->index) {
10463                         mirr_rule = it;
10464                         break;
10465                 }
10466                 parent = it;
10467         }
10468         if (mirr_rule && sw_id == mirr_rule->index) {
10469                 if (on) {
10470                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10471                         return -EEXIST;
10472                 } else {
10473                         ret = i40e_aq_del_mirror_rule(hw, seid,
10474                                         mirr_rule->rule_type,
10475                                         mirr_rule->entries,
10476                                         mirr_rule->num_entries, mirr_rule->id);
10477                         if (ret < 0) {
10478                                 PMD_DRV_LOG(ERR,
10479                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10480                                         ret, hw->aq.asq_last_status);
10481                                 return -ENOSYS;
10482                         }
10483                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10484                         rte_free(mirr_rule);
10485                         pf->nb_mirror_rule--;
10486                         return 0;
10487                 }
10488         } else if (!on) {
10489                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10490                 return -ENOENT;
10491         }
10492
10493         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10494                                 sizeof(struct i40e_mirror_rule) , 0);
10495         if (!mirr_rule) {
10496                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10497                 return I40E_ERR_NO_MEMORY;
10498         }
10499         switch (mirror_conf->rule_type) {
10500         case ETH_MIRROR_VLAN:
10501                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10502                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10503                                 mirr_rule->entries[j] =
10504                                         mirror_conf->vlan.vlan_id[i];
10505                                 j++;
10506                         }
10507                 }
10508                 if (j == 0) {
10509                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10510                         rte_free(mirr_rule);
10511                         return -EINVAL;
10512                 }
10513                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10514                 break;
10515         case ETH_MIRROR_VIRTUAL_POOL_UP:
10516         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10517                 /* check if the specified pool bit is out of range */
10518                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10519                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10520                         rte_free(mirr_rule);
10521                         return -EINVAL;
10522                 }
10523                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10524                         if (mirror_conf->pool_mask & (1ULL << i)) {
10525                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10526                                 j++;
10527                         }
10528                 }
10529                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10530                         /* add pf vsi to entries */
10531                         mirr_rule->entries[j] = pf->main_vsi_seid;
10532                         j++;
10533                 }
10534                 if (j == 0) {
10535                         PMD_DRV_LOG(ERR, "pool is not specified.");
10536                         rte_free(mirr_rule);
10537                         return -EINVAL;
10538                 }
10539                 /* egress and ingress in aq commands means from switch but not port */
10540                 mirr_rule->rule_type =
10541                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10542                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10543                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10544                 break;
10545         case ETH_MIRROR_UPLINK_PORT:
10546                 /* egress and ingress in aq commands means from switch but not port*/
10547                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10548                 break;
10549         case ETH_MIRROR_DOWNLINK_PORT:
10550                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10551                 break;
10552         default:
10553                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10554                         mirror_conf->rule_type);
10555                 rte_free(mirr_rule);
10556                 return -EINVAL;
10557         }
10558
10559         /* If the dst_pool is equal to vf_num, consider it as PF */
10560         if (mirror_conf->dst_pool == pf->vf_num)
10561                 dst_seid = pf->main_vsi_seid;
10562         else
10563                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10564
10565         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10566                                       mirr_rule->rule_type, mirr_rule->entries,
10567                                       j, &rule_id);
10568         if (ret < 0) {
10569                 PMD_DRV_LOG(ERR,
10570                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10571                         ret, hw->aq.asq_last_status);
10572                 rte_free(mirr_rule);
10573                 return -ENOSYS;
10574         }
10575
10576         mirr_rule->index = sw_id;
10577         mirr_rule->num_entries = j;
10578         mirr_rule->id = rule_id;
10579         mirr_rule->dst_vsi_seid = dst_seid;
10580
10581         if (parent)
10582                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10583         else
10584                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10585
10586         pf->nb_mirror_rule++;
10587         return 0;
10588 }
10589
10590 /**
10591  * i40e_mirror_rule_reset
10592  * @dev: pointer to the device
10593  * @sw_id: mirror rule's sw_id
10594  *
10595  * reset a mirror rule.
10596  *
10597  **/
10598 static int
10599 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10600 {
10601         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10602         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10603         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10604         uint16_t seid;
10605         int ret;
10606
10607         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10608
10609         seid = pf->main_vsi->veb->seid;
10610
10611         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10612                 if (sw_id == it->index) {
10613                         mirr_rule = it;
10614                         break;
10615                 }
10616         }
10617         if (mirr_rule) {
10618                 ret = i40e_aq_del_mirror_rule(hw, seid,
10619                                 mirr_rule->rule_type,
10620                                 mirr_rule->entries,
10621                                 mirr_rule->num_entries, mirr_rule->id);
10622                 if (ret < 0) {
10623                         PMD_DRV_LOG(ERR,
10624                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10625                                 ret, hw->aq.asq_last_status);
10626                         return -ENOSYS;
10627                 }
10628                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10629                 rte_free(mirr_rule);
10630                 pf->nb_mirror_rule--;
10631         } else {
10632                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10633                 return -ENOENT;
10634         }
10635         return 0;
10636 }
10637
10638 static uint64_t
10639 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10640 {
10641         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10642         uint64_t systim_cycles;
10643
10644         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10645         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10646                         << 32;
10647
10648         return systim_cycles;
10649 }
10650
10651 static uint64_t
10652 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10653 {
10654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10655         uint64_t rx_tstamp;
10656
10657         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10658         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10659                         << 32;
10660
10661         return rx_tstamp;
10662 }
10663
10664 static uint64_t
10665 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10666 {
10667         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10668         uint64_t tx_tstamp;
10669
10670         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10671         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10672                         << 32;
10673
10674         return tx_tstamp;
10675 }
10676
10677 static void
10678 i40e_start_timecounters(struct rte_eth_dev *dev)
10679 {
10680         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10681         struct i40e_adapter *adapter =
10682                         (struct i40e_adapter *)dev->data->dev_private;
10683         struct rte_eth_link link;
10684         uint32_t tsync_inc_l;
10685         uint32_t tsync_inc_h;
10686
10687         /* Get current link speed. */
10688         i40e_dev_link_update(dev, 1);
10689         rte_eth_linkstatus_get(dev, &link);
10690
10691         switch (link.link_speed) {
10692         case ETH_SPEED_NUM_40G:
10693                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10694                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10695                 break;
10696         case ETH_SPEED_NUM_10G:
10697                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10698                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10699                 break;
10700         case ETH_SPEED_NUM_1G:
10701                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10702                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10703                 break;
10704         default:
10705                 tsync_inc_l = 0x0;
10706                 tsync_inc_h = 0x0;
10707         }
10708
10709         /* Set the timesync increment value. */
10710         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10711         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10712
10713         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10714         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10715         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10716
10717         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10718         adapter->systime_tc.cc_shift = 0;
10719         adapter->systime_tc.nsec_mask = 0;
10720
10721         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10722         adapter->rx_tstamp_tc.cc_shift = 0;
10723         adapter->rx_tstamp_tc.nsec_mask = 0;
10724
10725         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10726         adapter->tx_tstamp_tc.cc_shift = 0;
10727         adapter->tx_tstamp_tc.nsec_mask = 0;
10728 }
10729
10730 static int
10731 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10732 {
10733         struct i40e_adapter *adapter =
10734                         (struct i40e_adapter *)dev->data->dev_private;
10735
10736         adapter->systime_tc.nsec += delta;
10737         adapter->rx_tstamp_tc.nsec += delta;
10738         adapter->tx_tstamp_tc.nsec += delta;
10739
10740         return 0;
10741 }
10742
10743 static int
10744 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10745 {
10746         uint64_t ns;
10747         struct i40e_adapter *adapter =
10748                         (struct i40e_adapter *)dev->data->dev_private;
10749
10750         ns = rte_timespec_to_ns(ts);
10751
10752         /* Set the timecounters to a new value. */
10753         adapter->systime_tc.nsec = ns;
10754         adapter->rx_tstamp_tc.nsec = ns;
10755         adapter->tx_tstamp_tc.nsec = ns;
10756
10757         return 0;
10758 }
10759
10760 static int
10761 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10762 {
10763         uint64_t ns, systime_cycles;
10764         struct i40e_adapter *adapter =
10765                         (struct i40e_adapter *)dev->data->dev_private;
10766
10767         systime_cycles = i40e_read_systime_cyclecounter(dev);
10768         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10769         *ts = rte_ns_to_timespec(ns);
10770
10771         return 0;
10772 }
10773
10774 static int
10775 i40e_timesync_enable(struct rte_eth_dev *dev)
10776 {
10777         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10778         uint32_t tsync_ctl_l;
10779         uint32_t tsync_ctl_h;
10780
10781         /* Stop the timesync system time. */
10782         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10783         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10784         /* Reset the timesync system time value. */
10785         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10786         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10787
10788         i40e_start_timecounters(dev);
10789
10790         /* Clear timesync registers. */
10791         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10792         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10793         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10794         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10795         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10796         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10797
10798         /* Enable timestamping of PTP packets. */
10799         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10800         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10801
10802         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10803         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10804         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10805
10806         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10807         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10808
10809         return 0;
10810 }
10811
10812 static int
10813 i40e_timesync_disable(struct rte_eth_dev *dev)
10814 {
10815         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10816         uint32_t tsync_ctl_l;
10817         uint32_t tsync_ctl_h;
10818
10819         /* Disable timestamping of transmitted PTP packets. */
10820         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10821         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10822
10823         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10824         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10825
10826         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10827         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10828
10829         /* Reset the timesync increment value. */
10830         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10831         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10832
10833         return 0;
10834 }
10835
10836 static int
10837 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10838                                 struct timespec *timestamp, uint32_t flags)
10839 {
10840         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10841         struct i40e_adapter *adapter =
10842                 (struct i40e_adapter *)dev->data->dev_private;
10843
10844         uint32_t sync_status;
10845         uint32_t index = flags & 0x03;
10846         uint64_t rx_tstamp_cycles;
10847         uint64_t ns;
10848
10849         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10850         if ((sync_status & (1 << index)) == 0)
10851                 return -EINVAL;
10852
10853         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10854         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10855         *timestamp = rte_ns_to_timespec(ns);
10856
10857         return 0;
10858 }
10859
10860 static int
10861 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10862                                 struct timespec *timestamp)
10863 {
10864         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10865         struct i40e_adapter *adapter =
10866                 (struct i40e_adapter *)dev->data->dev_private;
10867
10868         uint32_t sync_status;
10869         uint64_t tx_tstamp_cycles;
10870         uint64_t ns;
10871
10872         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10873         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10874                 return -EINVAL;
10875
10876         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10877         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10878         *timestamp = rte_ns_to_timespec(ns);
10879
10880         return 0;
10881 }
10882
10883 /*
10884  * i40e_parse_dcb_configure - parse dcb configure from user
10885  * @dev: the device being configured
10886  * @dcb_cfg: pointer of the result of parse
10887  * @*tc_map: bit map of enabled traffic classes
10888  *
10889  * Returns 0 on success, negative value on failure
10890  */
10891 static int
10892 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10893                          struct i40e_dcbx_config *dcb_cfg,
10894                          uint8_t *tc_map)
10895 {
10896         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10897         uint8_t i, tc_bw, bw_lf;
10898
10899         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10900
10901         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10902         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10903                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10904                 return -EINVAL;
10905         }
10906
10907         /* assume each tc has the same bw */
10908         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10909         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10910                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10911         /* to ensure the sum of tcbw is equal to 100 */
10912         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10913         for (i = 0; i < bw_lf; i++)
10914                 dcb_cfg->etscfg.tcbwtable[i]++;
10915
10916         /* assume each tc has the same Transmission Selection Algorithm */
10917         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10918                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10919
10920         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10921                 dcb_cfg->etscfg.prioritytable[i] =
10922                                 dcb_rx_conf->dcb_tc[i];
10923
10924         /* FW needs one App to configure HW */
10925         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10926         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10927         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10928         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10929
10930         if (dcb_rx_conf->nb_tcs == 0)
10931                 *tc_map = 1; /* tc0 only */
10932         else
10933                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10934
10935         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10936                 dcb_cfg->pfc.willing = 0;
10937                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10938                 dcb_cfg->pfc.pfcenable = *tc_map;
10939         }
10940         return 0;
10941 }
10942
10943
10944 static enum i40e_status_code
10945 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10946                               struct i40e_aqc_vsi_properties_data *info,
10947                               uint8_t enabled_tcmap)
10948 {
10949         enum i40e_status_code ret;
10950         int i, total_tc = 0;
10951         uint16_t qpnum_per_tc, bsf, qp_idx;
10952         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10953         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10954         uint16_t used_queues;
10955
10956         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10957         if (ret != I40E_SUCCESS)
10958                 return ret;
10959
10960         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10961                 if (enabled_tcmap & (1 << i))
10962                         total_tc++;
10963         }
10964         if (total_tc == 0)
10965                 total_tc = 1;
10966         vsi->enabled_tc = enabled_tcmap;
10967
10968         /* different VSI has different queues assigned */
10969         if (vsi->type == I40E_VSI_MAIN)
10970                 used_queues = dev_data->nb_rx_queues -
10971                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10972         else if (vsi->type == I40E_VSI_VMDQ2)
10973                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10974         else {
10975                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10976                 return I40E_ERR_NO_AVAILABLE_VSI;
10977         }
10978
10979         qpnum_per_tc = used_queues / total_tc;
10980         /* Number of queues per enabled TC */
10981         if (qpnum_per_tc == 0) {
10982                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10983                 return I40E_ERR_INVALID_QP_ID;
10984         }
10985         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10986                                 I40E_MAX_Q_PER_TC);
10987         bsf = rte_bsf32(qpnum_per_tc);
10988
10989         /**
10990          * Configure TC and queue mapping parameters, for enabled TC,
10991          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10992          * default queue will serve it.
10993          */
10994         qp_idx = 0;
10995         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10996                 if (vsi->enabled_tc & (1 << i)) {
10997                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10998                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10999                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11000                         qp_idx += qpnum_per_tc;
11001                 } else
11002                         info->tc_mapping[i] = 0;
11003         }
11004
11005         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11006         if (vsi->type == I40E_VSI_SRIOV) {
11007                 info->mapping_flags |=
11008                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11009                 for (i = 0; i < vsi->nb_qps; i++)
11010                         info->queue_mapping[i] =
11011                                 rte_cpu_to_le_16(vsi->base_queue + i);
11012         } else {
11013                 info->mapping_flags |=
11014                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11015                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11016         }
11017         info->valid_sections |=
11018                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11019
11020         return I40E_SUCCESS;
11021 }
11022
11023 /*
11024  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11025  * @veb: VEB to be configured
11026  * @tc_map: enabled TC bitmap
11027  *
11028  * Returns 0 on success, negative value on failure
11029  */
11030 static enum i40e_status_code
11031 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11032 {
11033         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11034         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11035         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11036         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11037         enum i40e_status_code ret = I40E_SUCCESS;
11038         int i;
11039         uint32_t bw_max;
11040
11041         /* Check if enabled_tc is same as existing or new TCs */
11042         if (veb->enabled_tc == tc_map)
11043                 return ret;
11044
11045         /* configure tc bandwidth */
11046         memset(&veb_bw, 0, sizeof(veb_bw));
11047         veb_bw.tc_valid_bits = tc_map;
11048         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11049         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11050                 if (tc_map & BIT_ULL(i))
11051                         veb_bw.tc_bw_share_credits[i] = 1;
11052         }
11053         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11054                                                    &veb_bw, NULL);
11055         if (ret) {
11056                 PMD_INIT_LOG(ERR,
11057                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11058                         hw->aq.asq_last_status);
11059                 return ret;
11060         }
11061
11062         memset(&ets_query, 0, sizeof(ets_query));
11063         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11064                                                    &ets_query, NULL);
11065         if (ret != I40E_SUCCESS) {
11066                 PMD_DRV_LOG(ERR,
11067                         "Failed to get switch_comp ETS configuration %u",
11068                         hw->aq.asq_last_status);
11069                 return ret;
11070         }
11071         memset(&bw_query, 0, sizeof(bw_query));
11072         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11073                                                   &bw_query, NULL);
11074         if (ret != I40E_SUCCESS) {
11075                 PMD_DRV_LOG(ERR,
11076                         "Failed to get switch_comp bandwidth configuration %u",
11077                         hw->aq.asq_last_status);
11078                 return ret;
11079         }
11080
11081         /* store and print out BW info */
11082         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11083         veb->bw_info.bw_max = ets_query.tc_bw_max;
11084         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11085         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11086         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11087                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11088                      I40E_16_BIT_WIDTH);
11089         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11090                 veb->bw_info.bw_ets_share_credits[i] =
11091                                 bw_query.tc_bw_share_credits[i];
11092                 veb->bw_info.bw_ets_credits[i] =
11093                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11094                 /* 4 bits per TC, 4th bit is reserved */
11095                 veb->bw_info.bw_ets_max[i] =
11096                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11097                                   RTE_LEN2MASK(3, uint8_t));
11098                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11099                             veb->bw_info.bw_ets_share_credits[i]);
11100                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11101                             veb->bw_info.bw_ets_credits[i]);
11102                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11103                             veb->bw_info.bw_ets_max[i]);
11104         }
11105
11106         veb->enabled_tc = tc_map;
11107
11108         return ret;
11109 }
11110
11111
11112 /*
11113  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11114  * @vsi: VSI to be configured
11115  * @tc_map: enabled TC bitmap
11116  *
11117  * Returns 0 on success, negative value on failure
11118  */
11119 static enum i40e_status_code
11120 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11121 {
11122         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11123         struct i40e_vsi_context ctxt;
11124         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11125         enum i40e_status_code ret = I40E_SUCCESS;
11126         int i;
11127
11128         /* Check if enabled_tc is same as existing or new TCs */
11129         if (vsi->enabled_tc == tc_map)
11130                 return ret;
11131
11132         /* configure tc bandwidth */
11133         memset(&bw_data, 0, sizeof(bw_data));
11134         bw_data.tc_valid_bits = tc_map;
11135         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11136         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11137                 if (tc_map & BIT_ULL(i))
11138                         bw_data.tc_bw_credits[i] = 1;
11139         }
11140         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11141         if (ret) {
11142                 PMD_INIT_LOG(ERR,
11143                         "AQ command Config VSI BW allocation per TC failed = %d",
11144                         hw->aq.asq_last_status);
11145                 goto out;
11146         }
11147         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11148                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11149
11150         /* Update Queue Pairs Mapping for currently enabled UPs */
11151         ctxt.seid = vsi->seid;
11152         ctxt.pf_num = hw->pf_id;
11153         ctxt.vf_num = 0;
11154         ctxt.uplink_seid = vsi->uplink_seid;
11155         ctxt.info = vsi->info;
11156         i40e_get_cap(hw);
11157         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11158         if (ret)
11159                 goto out;
11160
11161         /* Update the VSI after updating the VSI queue-mapping information */
11162         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11163         if (ret) {
11164                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11165                         hw->aq.asq_last_status);
11166                 goto out;
11167         }
11168         /* update the local VSI info with updated queue map */
11169         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11170                                         sizeof(vsi->info.tc_mapping));
11171         rte_memcpy(&vsi->info.queue_mapping,
11172                         &ctxt.info.queue_mapping,
11173                 sizeof(vsi->info.queue_mapping));
11174         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11175         vsi->info.valid_sections = 0;
11176
11177         /* query and update current VSI BW information */
11178         ret = i40e_vsi_get_bw_config(vsi);
11179         if (ret) {
11180                 PMD_INIT_LOG(ERR,
11181                          "Failed updating vsi bw info, err %s aq_err %s",
11182                          i40e_stat_str(hw, ret),
11183                          i40e_aq_str(hw, hw->aq.asq_last_status));
11184                 goto out;
11185         }
11186
11187         vsi->enabled_tc = tc_map;
11188
11189 out:
11190         return ret;
11191 }
11192
11193 /*
11194  * i40e_dcb_hw_configure - program the dcb setting to hw
11195  * @pf: pf the configuration is taken on
11196  * @new_cfg: new configuration
11197  * @tc_map: enabled TC bitmap
11198  *
11199  * Returns 0 on success, negative value on failure
11200  */
11201 static enum i40e_status_code
11202 i40e_dcb_hw_configure(struct i40e_pf *pf,
11203                       struct i40e_dcbx_config *new_cfg,
11204                       uint8_t tc_map)
11205 {
11206         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11207         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11208         struct i40e_vsi *main_vsi = pf->main_vsi;
11209         struct i40e_vsi_list *vsi_list;
11210         enum i40e_status_code ret;
11211         int i;
11212         uint32_t val;
11213
11214         /* Use the FW API if FW > v4.4*/
11215         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11216               (hw->aq.fw_maj_ver >= 5))) {
11217                 PMD_INIT_LOG(ERR,
11218                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11219                 return I40E_ERR_FIRMWARE_API_VERSION;
11220         }
11221
11222         /* Check if need reconfiguration */
11223         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11224                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11225                 return I40E_SUCCESS;
11226         }
11227
11228         /* Copy the new config to the current config */
11229         *old_cfg = *new_cfg;
11230         old_cfg->etsrec = old_cfg->etscfg;
11231         ret = i40e_set_dcb_config(hw);
11232         if (ret) {
11233                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11234                          i40e_stat_str(hw, ret),
11235                          i40e_aq_str(hw, hw->aq.asq_last_status));
11236                 return ret;
11237         }
11238         /* set receive Arbiter to RR mode and ETS scheme by default */
11239         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11240                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11241                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11242                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11243                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11244                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11245                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11246                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11247                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11248                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11249                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11250                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11251                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11252         }
11253         /* get local mib to check whether it is configured correctly */
11254         /* IEEE mode */
11255         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11256         /* Get Local DCB Config */
11257         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11258                                      &hw->local_dcbx_config);
11259
11260         /* if Veb is created, need to update TC of it at first */
11261         if (main_vsi->veb) {
11262                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11263                 if (ret)
11264                         PMD_INIT_LOG(WARNING,
11265                                  "Failed configuring TC for VEB seid=%d",
11266                                  main_vsi->veb->seid);
11267         }
11268         /* Update each VSI */
11269         i40e_vsi_config_tc(main_vsi, tc_map);
11270         if (main_vsi->veb) {
11271                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11272                         /* Beside main VSI and VMDQ VSIs, only enable default
11273                          * TC for other VSIs
11274                          */
11275                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11276                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11277                                                          tc_map);
11278                         else
11279                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11280                                                          I40E_DEFAULT_TCMAP);
11281                         if (ret)
11282                                 PMD_INIT_LOG(WARNING,
11283                                         "Failed configuring TC for VSI seid=%d",
11284                                         vsi_list->vsi->seid);
11285                         /* continue */
11286                 }
11287         }
11288         return I40E_SUCCESS;
11289 }
11290
11291 /*
11292  * i40e_dcb_init_configure - initial dcb config
11293  * @dev: device being configured
11294  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11295  *
11296  * Returns 0 on success, negative value on failure
11297  */
11298 int
11299 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11300 {
11301         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11302         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11303         int i, ret = 0;
11304
11305         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11306                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11307                 return -ENOTSUP;
11308         }
11309
11310         /* DCB initialization:
11311          * Update DCB configuration from the Firmware and configure
11312          * LLDP MIB change event.
11313          */
11314         if (sw_dcb == TRUE) {
11315                 /* When using NVM 6.01 or later, the RX data path does
11316                  * not hang if the FW LLDP is stopped.
11317                  */
11318                 if (((hw->nvm.version >> 12) & 0xf) >= 6 &&
11319                     ((hw->nvm.version >> 4) & 0xff) >= 1) {
11320                         ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11321                         if (ret != I40E_SUCCESS)
11322                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11323                 }
11324
11325                 ret = i40e_init_dcb(hw);
11326                 /* If lldp agent is stopped, the return value from
11327                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11328                  * adminq status. Otherwise, it should return success.
11329                  */
11330                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11331                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11332                         memset(&hw->local_dcbx_config, 0,
11333                                 sizeof(struct i40e_dcbx_config));
11334                         /* set dcb default configuration */
11335                         hw->local_dcbx_config.etscfg.willing = 0;
11336                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11337                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11338                         hw->local_dcbx_config.etscfg.tsatable[0] =
11339                                                 I40E_IEEE_TSA_ETS;
11340                         /* all UPs mapping to TC0 */
11341                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11342                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11343                         hw->local_dcbx_config.etsrec =
11344                                 hw->local_dcbx_config.etscfg;
11345                         hw->local_dcbx_config.pfc.willing = 0;
11346                         hw->local_dcbx_config.pfc.pfccap =
11347                                                 I40E_MAX_TRAFFIC_CLASS;
11348                         /* FW needs one App to configure HW */
11349                         hw->local_dcbx_config.numapps = 1;
11350                         hw->local_dcbx_config.app[0].selector =
11351                                                 I40E_APP_SEL_ETHTYPE;
11352                         hw->local_dcbx_config.app[0].priority = 3;
11353                         hw->local_dcbx_config.app[0].protocolid =
11354                                                 I40E_APP_PROTOID_FCOE;
11355                         ret = i40e_set_dcb_config(hw);
11356                         if (ret) {
11357                                 PMD_INIT_LOG(ERR,
11358                                         "default dcb config fails. err = %d, aq_err = %d.",
11359                                         ret, hw->aq.asq_last_status);
11360                                 return -ENOSYS;
11361                         }
11362                 } else {
11363                         PMD_INIT_LOG(ERR,
11364                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11365                                 ret, hw->aq.asq_last_status);
11366                         return -ENOTSUP;
11367                 }
11368         } else {
11369                 ret = i40e_aq_start_lldp(hw, NULL);
11370                 if (ret != I40E_SUCCESS)
11371                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11372
11373                 ret = i40e_init_dcb(hw);
11374                 if (!ret) {
11375                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11376                                 PMD_INIT_LOG(ERR,
11377                                         "HW doesn't support DCBX offload.");
11378                                 return -ENOTSUP;
11379                         }
11380                 } else {
11381                         PMD_INIT_LOG(ERR,
11382                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11383                                 ret, hw->aq.asq_last_status);
11384                         return -ENOTSUP;
11385                 }
11386         }
11387         return 0;
11388 }
11389
11390 /*
11391  * i40e_dcb_setup - setup dcb related config
11392  * @dev: device being configured
11393  *
11394  * Returns 0 on success, negative value on failure
11395  */
11396 static int
11397 i40e_dcb_setup(struct rte_eth_dev *dev)
11398 {
11399         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11400         struct i40e_dcbx_config dcb_cfg;
11401         uint8_t tc_map = 0;
11402         int ret = 0;
11403
11404         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11405                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11406                 return -ENOTSUP;
11407         }
11408
11409         if (pf->vf_num != 0)
11410                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11411
11412         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11413         if (ret) {
11414                 PMD_INIT_LOG(ERR, "invalid dcb config");
11415                 return -EINVAL;
11416         }
11417         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11418         if (ret) {
11419                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11420                 return -ENOSYS;
11421         }
11422
11423         return 0;
11424 }
11425
11426 static int
11427 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11428                       struct rte_eth_dcb_info *dcb_info)
11429 {
11430         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11431         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11432         struct i40e_vsi *vsi = pf->main_vsi;
11433         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11434         uint16_t bsf, tc_mapping;
11435         int i, j = 0;
11436
11437         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11438                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11439         else
11440                 dcb_info->nb_tcs = 1;
11441         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11442                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11443         for (i = 0; i < dcb_info->nb_tcs; i++)
11444                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11445
11446         /* get queue mapping if vmdq is disabled */
11447         if (!pf->nb_cfg_vmdq_vsi) {
11448                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11449                         if (!(vsi->enabled_tc & (1 << i)))
11450                                 continue;
11451                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11452                         dcb_info->tc_queue.tc_rxq[j][i].base =
11453                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11454                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11455                         dcb_info->tc_queue.tc_txq[j][i].base =
11456                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11457                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11458                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11459                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11460                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11461                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11462                 }
11463                 return 0;
11464         }
11465
11466         /* get queue mapping if vmdq is enabled */
11467         do {
11468                 vsi = pf->vmdq[j].vsi;
11469                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11470                         if (!(vsi->enabled_tc & (1 << i)))
11471                                 continue;
11472                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11473                         dcb_info->tc_queue.tc_rxq[j][i].base =
11474                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11475                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11476                         dcb_info->tc_queue.tc_txq[j][i].base =
11477                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11478                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11479                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11480                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11481                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11482                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11483                 }
11484                 j++;
11485         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11486         return 0;
11487 }
11488
11489 static int
11490 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11491 {
11492         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11493         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11494         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11495         uint16_t msix_intr;
11496
11497         msix_intr = intr_handle->intr_vec[queue_id];
11498         if (msix_intr == I40E_MISC_VEC_ID)
11499                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11500                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11501                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11502                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11503         else
11504                 I40E_WRITE_REG(hw,
11505                                I40E_PFINT_DYN_CTLN(msix_intr -
11506                                                    I40E_RX_VEC_START),
11507                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11508                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11509                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11510
11511         I40E_WRITE_FLUSH(hw);
11512         rte_intr_enable(&pci_dev->intr_handle);
11513
11514         return 0;
11515 }
11516
11517 static int
11518 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11519 {
11520         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11521         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11522         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11523         uint16_t msix_intr;
11524
11525         msix_intr = intr_handle->intr_vec[queue_id];
11526         if (msix_intr == I40E_MISC_VEC_ID)
11527                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11528                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11529         else
11530                 I40E_WRITE_REG(hw,
11531                                I40E_PFINT_DYN_CTLN(msix_intr -
11532                                                    I40E_RX_VEC_START),
11533                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11534         I40E_WRITE_FLUSH(hw);
11535
11536         return 0;
11537 }
11538
11539 static int i40e_get_regs(struct rte_eth_dev *dev,
11540                          struct rte_dev_reg_info *regs)
11541 {
11542         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11543         uint32_t *ptr_data = regs->data;
11544         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11545         const struct i40e_reg_info *reg_info;
11546
11547         if (ptr_data == NULL) {
11548                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11549                 regs->width = sizeof(uint32_t);
11550                 return 0;
11551         }
11552
11553         /* The first few registers have to be read using AQ operations */
11554         reg_idx = 0;
11555         while (i40e_regs_adminq[reg_idx].name) {
11556                 reg_info = &i40e_regs_adminq[reg_idx++];
11557                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11558                         for (arr_idx2 = 0;
11559                                         arr_idx2 <= reg_info->count2;
11560                                         arr_idx2++) {
11561                                 reg_offset = arr_idx * reg_info->stride1 +
11562                                         arr_idx2 * reg_info->stride2;
11563                                 reg_offset += reg_info->base_addr;
11564                                 ptr_data[reg_offset >> 2] =
11565                                         i40e_read_rx_ctl(hw, reg_offset);
11566                         }
11567         }
11568
11569         /* The remaining registers can be read using primitives */
11570         reg_idx = 0;
11571         while (i40e_regs_others[reg_idx].name) {
11572                 reg_info = &i40e_regs_others[reg_idx++];
11573                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11574                         for (arr_idx2 = 0;
11575                                         arr_idx2 <= reg_info->count2;
11576                                         arr_idx2++) {
11577                                 reg_offset = arr_idx * reg_info->stride1 +
11578                                         arr_idx2 * reg_info->stride2;
11579                                 reg_offset += reg_info->base_addr;
11580                                 ptr_data[reg_offset >> 2] =
11581                                         I40E_READ_REG(hw, reg_offset);
11582                         }
11583         }
11584
11585         return 0;
11586 }
11587
11588 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11589 {
11590         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11591
11592         /* Convert word count to byte count */
11593         return hw->nvm.sr_size << 1;
11594 }
11595
11596 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11597                            struct rte_dev_eeprom_info *eeprom)
11598 {
11599         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11600         uint16_t *data = eeprom->data;
11601         uint16_t offset, length, cnt_words;
11602         int ret_code;
11603
11604         offset = eeprom->offset >> 1;
11605         length = eeprom->length >> 1;
11606         cnt_words = length;
11607
11608         if (offset > hw->nvm.sr_size ||
11609                 offset + length > hw->nvm.sr_size) {
11610                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11611                 return -EINVAL;
11612         }
11613
11614         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11615
11616         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11617         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11618                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11619                 return -EIO;
11620         }
11621
11622         return 0;
11623 }
11624
11625 static int i40e_get_module_info(struct rte_eth_dev *dev,
11626                                 struct rte_eth_dev_module_info *modinfo)
11627 {
11628         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11629         uint32_t sff8472_comp = 0;
11630         uint32_t sff8472_swap = 0;
11631         uint32_t sff8636_rev = 0;
11632         i40e_status status;
11633         uint32_t type = 0;
11634
11635         /* Check if firmware supports reading module EEPROM. */
11636         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11637                 PMD_DRV_LOG(ERR,
11638                             "Module EEPROM memory read not supported. "
11639                             "Please update the NVM image.\n");
11640                 return -EINVAL;
11641         }
11642
11643         status = i40e_update_link_info(hw);
11644         if (status)
11645                 return -EIO;
11646
11647         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11648                 PMD_DRV_LOG(ERR,
11649                             "Cannot read module EEPROM memory. "
11650                             "No module connected.\n");
11651                 return -EINVAL;
11652         }
11653
11654         type = hw->phy.link_info.module_type[0];
11655
11656         switch (type) {
11657         case I40E_MODULE_TYPE_SFP:
11658                 status = i40e_aq_get_phy_register(hw,
11659                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11660                                 I40E_I2C_EEPROM_DEV_ADDR,
11661                                 I40E_MODULE_SFF_8472_COMP,
11662                                 &sff8472_comp, NULL);
11663                 if (status)
11664                         return -EIO;
11665
11666                 status = i40e_aq_get_phy_register(hw,
11667                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11668                                 I40E_I2C_EEPROM_DEV_ADDR,
11669                                 I40E_MODULE_SFF_8472_SWAP,
11670                                 &sff8472_swap, NULL);
11671                 if (status)
11672                         return -EIO;
11673
11674                 /* Check if the module requires address swap to access
11675                  * the other EEPROM memory page.
11676                  */
11677                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11678                         PMD_DRV_LOG(WARNING,
11679                                     "Module address swap to access "
11680                                     "page 0xA2 is not supported.\n");
11681                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11682                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11683                 } else if (sff8472_comp == 0x00) {
11684                         /* Module is not SFF-8472 compliant */
11685                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11686                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11687                 } else {
11688                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11689                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11690                 }
11691                 break;
11692         case I40E_MODULE_TYPE_QSFP_PLUS:
11693                 /* Read from memory page 0. */
11694                 status = i40e_aq_get_phy_register(hw,
11695                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11696                                 0,
11697                                 I40E_MODULE_REVISION_ADDR,
11698                                 &sff8636_rev, NULL);
11699                 if (status)
11700                         return -EIO;
11701                 /* Determine revision compliance byte */
11702                 if (sff8636_rev > 0x02) {
11703                         /* Module is SFF-8636 compliant */
11704                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11705                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11706                 } else {
11707                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11708                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11709                 }
11710                 break;
11711         case I40E_MODULE_TYPE_QSFP28:
11712                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11713                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11714                 break;
11715         default:
11716                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11717                 return -EINVAL;
11718         }
11719         return 0;
11720 }
11721
11722 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11723                                   struct rte_dev_eeprom_info *info)
11724 {
11725         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11726         bool is_sfp = false;
11727         i40e_status status;
11728         uint8_t *data = info->data;
11729         uint32_t value = 0;
11730         uint32_t i;
11731
11732         if (!info || !info->length || !data)
11733                 return -EINVAL;
11734
11735         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11736                 is_sfp = true;
11737
11738         for (i = 0; i < info->length; i++) {
11739                 u32 offset = i + info->offset;
11740                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11741
11742                 /* Check if we need to access the other memory page */
11743                 if (is_sfp) {
11744                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11745                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11746                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11747                         }
11748                 } else {
11749                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11750                                 /* Compute memory page number and offset. */
11751                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11752                                 addr++;
11753                         }
11754                 }
11755                 status = i40e_aq_get_phy_register(hw,
11756                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11757                                 addr, offset, &value, NULL);
11758                 if (status)
11759                         return -EIO;
11760                 data[i] = (uint8_t)value;
11761         }
11762         return 0;
11763 }
11764
11765 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11766                                      struct ether_addr *mac_addr)
11767 {
11768         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11769         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11770         struct i40e_vsi *vsi = pf->main_vsi;
11771         struct i40e_mac_filter_info mac_filter;
11772         struct i40e_mac_filter *f;
11773         int ret;
11774
11775         if (!is_valid_assigned_ether_addr(mac_addr)) {
11776                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11777                 return -EINVAL;
11778         }
11779
11780         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11781                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11782                         break;
11783         }
11784
11785         if (f == NULL) {
11786                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11787                 return -EIO;
11788         }
11789
11790         mac_filter = f->mac_info;
11791         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11792         if (ret != I40E_SUCCESS) {
11793                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11794                 return -EIO;
11795         }
11796         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11797         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11798         if (ret != I40E_SUCCESS) {
11799                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11800                 return -EIO;
11801         }
11802         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11803
11804         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11805                                         mac_addr->addr_bytes, NULL);
11806         if (ret != I40E_SUCCESS) {
11807                 PMD_DRV_LOG(ERR, "Failed to change mac");
11808                 return -EIO;
11809         }
11810
11811         return 0;
11812 }
11813
11814 static int
11815 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11816 {
11817         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11818         struct rte_eth_dev_data *dev_data = pf->dev_data;
11819         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11820         int ret = 0;
11821
11822         /* check if mtu is within the allowed range */
11823         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11824                 return -EINVAL;
11825
11826         /* mtu setting is forbidden if port is start */
11827         if (dev_data->dev_started) {
11828                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11829                             dev_data->port_id);
11830                 return -EBUSY;
11831         }
11832
11833         if (frame_size > ETHER_MAX_LEN)
11834                 dev_data->dev_conf.rxmode.offloads |=
11835                         DEV_RX_OFFLOAD_JUMBO_FRAME;
11836         else
11837                 dev_data->dev_conf.rxmode.offloads &=
11838                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11839
11840         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11841
11842         return ret;
11843 }
11844
11845 /* Restore ethertype filter */
11846 static void
11847 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11848 {
11849         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11850         struct i40e_ethertype_filter_list
11851                 *ethertype_list = &pf->ethertype.ethertype_list;
11852         struct i40e_ethertype_filter *f;
11853         struct i40e_control_filter_stats stats;
11854         uint16_t flags;
11855
11856         TAILQ_FOREACH(f, ethertype_list, rules) {
11857                 flags = 0;
11858                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11859                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11860                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11861                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11862                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11863
11864                 memset(&stats, 0, sizeof(stats));
11865                 i40e_aq_add_rem_control_packet_filter(hw,
11866                                             f->input.mac_addr.addr_bytes,
11867                                             f->input.ether_type,
11868                                             flags, pf->main_vsi->seid,
11869                                             f->queue, 1, &stats, NULL);
11870         }
11871         PMD_DRV_LOG(INFO, "Ethertype filter:"
11872                     " mac_etype_used = %u, etype_used = %u,"
11873                     " mac_etype_free = %u, etype_free = %u",
11874                     stats.mac_etype_used, stats.etype_used,
11875                     stats.mac_etype_free, stats.etype_free);
11876 }
11877
11878 /* Restore tunnel filter */
11879 static void
11880 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11881 {
11882         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11883         struct i40e_vsi *vsi;
11884         struct i40e_pf_vf *vf;
11885         struct i40e_tunnel_filter_list
11886                 *tunnel_list = &pf->tunnel.tunnel_list;
11887         struct i40e_tunnel_filter *f;
11888         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11889         bool big_buffer = 0;
11890
11891         TAILQ_FOREACH(f, tunnel_list, rules) {
11892                 if (!f->is_to_vf)
11893                         vsi = pf->main_vsi;
11894                 else {
11895                         vf = &pf->vfs[f->vf_id];
11896                         vsi = vf->vsi;
11897                 }
11898                 memset(&cld_filter, 0, sizeof(cld_filter));
11899                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11900                         (struct ether_addr *)&cld_filter.element.outer_mac);
11901                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11902                         (struct ether_addr *)&cld_filter.element.inner_mac);
11903                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11904                 cld_filter.element.flags = f->input.flags;
11905                 cld_filter.element.tenant_id = f->input.tenant_id;
11906                 cld_filter.element.queue_number = f->queue;
11907                 rte_memcpy(cld_filter.general_fields,
11908                            f->input.general_fields,
11909                            sizeof(f->input.general_fields));
11910
11911                 if (((f->input.flags &
11912                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11913                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11914                     ((f->input.flags &
11915                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11916                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11917                     ((f->input.flags &
11918                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11919                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11920                         big_buffer = 1;
11921
11922                 if (big_buffer)
11923                         i40e_aq_add_cloud_filters_big_buffer(hw,
11924                                              vsi->seid, &cld_filter, 1);
11925                 else
11926                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11927                                                   &cld_filter.element, 1);
11928         }
11929 }
11930
11931 /* Restore rss filter */
11932 static inline void
11933 i40e_rss_filter_restore(struct i40e_pf *pf)
11934 {
11935         struct i40e_rte_flow_rss_conf *conf =
11936                                         &pf->rss_info;
11937         if (conf->conf.queue_num)
11938                 i40e_config_rss_filter(pf, conf, TRUE);
11939 }
11940
11941 static void
11942 i40e_filter_restore(struct i40e_pf *pf)
11943 {
11944         i40e_ethertype_filter_restore(pf);
11945         i40e_tunnel_filter_restore(pf);
11946         i40e_fdir_filter_restore(pf);
11947         i40e_rss_filter_restore(pf);
11948 }
11949
11950 static bool
11951 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11952 {
11953         if (strcmp(dev->device->driver->name, drv->driver.name))
11954                 return false;
11955
11956         return true;
11957 }
11958
11959 bool
11960 is_i40e_supported(struct rte_eth_dev *dev)
11961 {
11962         return is_device_supported(dev, &rte_i40e_pmd);
11963 }
11964
11965 struct i40e_customized_pctype*
11966 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11967 {
11968         int i;
11969
11970         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11971                 if (pf->customized_pctype[i].index == index)
11972                         return &pf->customized_pctype[i];
11973         }
11974         return NULL;
11975 }
11976
11977 static int
11978 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11979                               uint32_t pkg_size, uint32_t proto_num,
11980                               struct rte_pmd_i40e_proto_info *proto,
11981                               enum rte_pmd_i40e_package_op op)
11982 {
11983         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11984         uint32_t pctype_num;
11985         struct rte_pmd_i40e_ptype_info *pctype;
11986         uint32_t buff_size;
11987         struct i40e_customized_pctype *new_pctype = NULL;
11988         uint8_t proto_id;
11989         uint8_t pctype_value;
11990         char name[64];
11991         uint32_t i, j, n;
11992         int ret;
11993
11994         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11995             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11996                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11997                 return -1;
11998         }
11999
12000         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12001                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12002                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12003         if (ret) {
12004                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12005                 return -1;
12006         }
12007         if (!pctype_num) {
12008                 PMD_DRV_LOG(INFO, "No new pctype added");
12009                 return -1;
12010         }
12011
12012         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12013         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12014         if (!pctype) {
12015                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12016                 return -1;
12017         }
12018         /* get information about new pctype list */
12019         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12020                                         (uint8_t *)pctype, buff_size,
12021                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12022         if (ret) {
12023                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12024                 rte_free(pctype);
12025                 return -1;
12026         }
12027
12028         /* Update customized pctype. */
12029         for (i = 0; i < pctype_num; i++) {
12030                 pctype_value = pctype[i].ptype_id;
12031                 memset(name, 0, sizeof(name));
12032                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12033                         proto_id = pctype[i].protocols[j];
12034                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12035                                 continue;
12036                         for (n = 0; n < proto_num; n++) {
12037                                 if (proto[n].proto_id != proto_id)
12038                                         continue;
12039                                 strcat(name, proto[n].name);
12040                                 strcat(name, "_");
12041                                 break;
12042                         }
12043                 }
12044                 name[strlen(name) - 1] = '\0';
12045                 if (!strcmp(name, "GTPC"))
12046                         new_pctype =
12047                                 i40e_find_customized_pctype(pf,
12048                                                       I40E_CUSTOMIZED_GTPC);
12049                 else if (!strcmp(name, "GTPU_IPV4"))
12050                         new_pctype =
12051                                 i40e_find_customized_pctype(pf,
12052                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12053                 else if (!strcmp(name, "GTPU_IPV6"))
12054                         new_pctype =
12055                                 i40e_find_customized_pctype(pf,
12056                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12057                 else if (!strcmp(name, "GTPU"))
12058                         new_pctype =
12059                                 i40e_find_customized_pctype(pf,
12060                                                       I40E_CUSTOMIZED_GTPU);
12061                 if (new_pctype) {
12062                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12063                                 new_pctype->pctype = pctype_value;
12064                                 new_pctype->valid = true;
12065                         } else {
12066                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12067                                 new_pctype->valid = false;
12068                         }
12069                 }
12070         }
12071
12072         rte_free(pctype);
12073         return 0;
12074 }
12075
12076 static int
12077 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12078                              uint32_t pkg_size, uint32_t proto_num,
12079                              struct rte_pmd_i40e_proto_info *proto,
12080                              enum rte_pmd_i40e_package_op op)
12081 {
12082         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12083         uint16_t port_id = dev->data->port_id;
12084         uint32_t ptype_num;
12085         struct rte_pmd_i40e_ptype_info *ptype;
12086         uint32_t buff_size;
12087         uint8_t proto_id;
12088         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12089         uint32_t i, j, n;
12090         bool in_tunnel;
12091         int ret;
12092
12093         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12094             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12095                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12096                 return -1;
12097         }
12098
12099         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12100                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12101                 return 0;
12102         }
12103
12104         /* get information about new ptype num */
12105         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12106                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12107                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12108         if (ret) {
12109                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12110                 return ret;
12111         }
12112         if (!ptype_num) {
12113                 PMD_DRV_LOG(INFO, "No new ptype added");
12114                 return -1;
12115         }
12116
12117         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12118         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12119         if (!ptype) {
12120                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12121                 return -1;
12122         }
12123
12124         /* get information about new ptype list */
12125         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12126                                         (uint8_t *)ptype, buff_size,
12127                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12128         if (ret) {
12129                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12130                 rte_free(ptype);
12131                 return ret;
12132         }
12133
12134         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12135         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12136         if (!ptype_mapping) {
12137                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12138                 rte_free(ptype);
12139                 return -1;
12140         }
12141
12142         /* Update ptype mapping table. */
12143         for (i = 0; i < ptype_num; i++) {
12144                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12145                 ptype_mapping[i].sw_ptype = 0;
12146                 in_tunnel = false;
12147                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12148                         proto_id = ptype[i].protocols[j];
12149                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12150                                 continue;
12151                         for (n = 0; n < proto_num; n++) {
12152                                 if (proto[n].proto_id != proto_id)
12153                                         continue;
12154                                 memset(name, 0, sizeof(name));
12155                                 strcpy(name, proto[n].name);
12156                                 if (!strncasecmp(name, "PPPOE", 5))
12157                                         ptype_mapping[i].sw_ptype |=
12158                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12159                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12160                                          !in_tunnel) {
12161                                         ptype_mapping[i].sw_ptype |=
12162                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12163                                         ptype_mapping[i].sw_ptype |=
12164                                                 RTE_PTYPE_L4_FRAG;
12165                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12166                                            in_tunnel) {
12167                                         ptype_mapping[i].sw_ptype |=
12168                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12169                                         ptype_mapping[i].sw_ptype |=
12170                                                 RTE_PTYPE_INNER_L4_FRAG;
12171                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12172                                         ptype_mapping[i].sw_ptype |=
12173                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12174                                         in_tunnel = true;
12175                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12176                                            !in_tunnel)
12177                                         ptype_mapping[i].sw_ptype |=
12178                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12179                                 else if (!strncasecmp(name, "IPV4", 4) &&
12180                                          in_tunnel)
12181                                         ptype_mapping[i].sw_ptype |=
12182                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12183                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12184                                          !in_tunnel) {
12185                                         ptype_mapping[i].sw_ptype |=
12186                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12187                                         ptype_mapping[i].sw_ptype |=
12188                                                 RTE_PTYPE_L4_FRAG;
12189                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12190                                            in_tunnel) {
12191                                         ptype_mapping[i].sw_ptype |=
12192                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12193                                         ptype_mapping[i].sw_ptype |=
12194                                                 RTE_PTYPE_INNER_L4_FRAG;
12195                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12196                                         ptype_mapping[i].sw_ptype |=
12197                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12198                                         in_tunnel = true;
12199                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12200                                            !in_tunnel)
12201                                         ptype_mapping[i].sw_ptype |=
12202                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12203                                 else if (!strncasecmp(name, "IPV6", 4) &&
12204                                          in_tunnel)
12205                                         ptype_mapping[i].sw_ptype |=
12206                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12207                                 else if (!strncasecmp(name, "UDP", 3) &&
12208                                          !in_tunnel)
12209                                         ptype_mapping[i].sw_ptype |=
12210                                                 RTE_PTYPE_L4_UDP;
12211                                 else if (!strncasecmp(name, "UDP", 3) &&
12212                                          in_tunnel)
12213                                         ptype_mapping[i].sw_ptype |=
12214                                                 RTE_PTYPE_INNER_L4_UDP;
12215                                 else if (!strncasecmp(name, "TCP", 3) &&
12216                                          !in_tunnel)
12217                                         ptype_mapping[i].sw_ptype |=
12218                                                 RTE_PTYPE_L4_TCP;
12219                                 else if (!strncasecmp(name, "TCP", 3) &&
12220                                          in_tunnel)
12221                                         ptype_mapping[i].sw_ptype |=
12222                                                 RTE_PTYPE_INNER_L4_TCP;
12223                                 else if (!strncasecmp(name, "SCTP", 4) &&
12224                                          !in_tunnel)
12225                                         ptype_mapping[i].sw_ptype |=
12226                                                 RTE_PTYPE_L4_SCTP;
12227                                 else if (!strncasecmp(name, "SCTP", 4) &&
12228                                          in_tunnel)
12229                                         ptype_mapping[i].sw_ptype |=
12230                                                 RTE_PTYPE_INNER_L4_SCTP;
12231                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12232                                           !strncasecmp(name, "ICMPV6", 6)) &&
12233                                          !in_tunnel)
12234                                         ptype_mapping[i].sw_ptype |=
12235                                                 RTE_PTYPE_L4_ICMP;
12236                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12237                                           !strncasecmp(name, "ICMPV6", 6)) &&
12238                                          in_tunnel)
12239                                         ptype_mapping[i].sw_ptype |=
12240                                                 RTE_PTYPE_INNER_L4_ICMP;
12241                                 else if (!strncasecmp(name, "GTPC", 4)) {
12242                                         ptype_mapping[i].sw_ptype |=
12243                                                 RTE_PTYPE_TUNNEL_GTPC;
12244                                         in_tunnel = true;
12245                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12246                                         ptype_mapping[i].sw_ptype |=
12247                                                 RTE_PTYPE_TUNNEL_GTPU;
12248                                         in_tunnel = true;
12249                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12250                                         ptype_mapping[i].sw_ptype |=
12251                                                 RTE_PTYPE_TUNNEL_GRENAT;
12252                                         in_tunnel = true;
12253                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12254                                            !strncasecmp(name, "L2TPV2", 6)) {
12255                                         ptype_mapping[i].sw_ptype |=
12256                                                 RTE_PTYPE_TUNNEL_L2TP;
12257                                         in_tunnel = true;
12258                                 }
12259
12260                                 break;
12261                         }
12262                 }
12263         }
12264
12265         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12266                                                 ptype_num, 0);
12267         if (ret)
12268                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12269
12270         rte_free(ptype_mapping);
12271         rte_free(ptype);
12272         return ret;
12273 }
12274
12275 void
12276 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12277                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12278 {
12279         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12280         uint32_t proto_num;
12281         struct rte_pmd_i40e_proto_info *proto;
12282         uint32_t buff_size;
12283         uint32_t i;
12284         int ret;
12285
12286         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12287             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12288                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12289                 return;
12290         }
12291
12292         /* get information about protocol number */
12293         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12294                                        (uint8_t *)&proto_num, sizeof(proto_num),
12295                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12296         if (ret) {
12297                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12298                 return;
12299         }
12300         if (!proto_num) {
12301                 PMD_DRV_LOG(INFO, "No new protocol added");
12302                 return;
12303         }
12304
12305         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12306         proto = rte_zmalloc("new_proto", buff_size, 0);
12307         if (!proto) {
12308                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12309                 return;
12310         }
12311
12312         /* get information about protocol list */
12313         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12314                                         (uint8_t *)proto, buff_size,
12315                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12316         if (ret) {
12317                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12318                 rte_free(proto);
12319                 return;
12320         }
12321
12322         /* Check if GTP is supported. */
12323         for (i = 0; i < proto_num; i++) {
12324                 if (!strncmp(proto[i].name, "GTP", 3)) {
12325                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12326                                 pf->gtp_support = true;
12327                         else
12328                                 pf->gtp_support = false;
12329                         break;
12330                 }
12331         }
12332
12333         /* Update customized pctype info */
12334         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12335                                             proto_num, proto, op);
12336         if (ret)
12337                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12338
12339         /* Update customized ptype info */
12340         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12341                                            proto_num, proto, op);
12342         if (ret)
12343                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12344
12345         rte_free(proto);
12346 }
12347
12348 /* Create a QinQ cloud filter
12349  *
12350  * The Fortville NIC has limited resources for tunnel filters,
12351  * so we can only reuse existing filters.
12352  *
12353  * In step 1 we define which Field Vector fields can be used for
12354  * filter types.
12355  * As we do not have the inner tag defined as a field,
12356  * we have to define it first, by reusing one of L1 entries.
12357  *
12358  * In step 2 we are replacing one of existing filter types with
12359  * a new one for QinQ.
12360  * As we reusing L1 and replacing L2, some of the default filter
12361  * types will disappear,which depends on L1 and L2 entries we reuse.
12362  *
12363  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12364  *
12365  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12366  *              later when we define the cloud filter.
12367  *      a.      Valid_flags.replace_cloud = 0
12368  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12369  *      c.      New_filter = 0x10
12370  *      d.      TR bit = 0xff (optional, not used here)
12371  *      e.      Buffer – 2 entries:
12372  *              i.      Byte 0 = 8 (outer vlan FV index).
12373  *                      Byte 1 = 0 (rsv)
12374  *                      Byte 2-3 = 0x0fff
12375  *              ii.     Byte 0 = 37 (inner vlan FV index).
12376  *                      Byte 1 =0 (rsv)
12377  *                      Byte 2-3 = 0x0fff
12378  *
12379  * Step 2:
12380  * 2.   Create cloud filter using two L1 filters entries: stag and
12381  *              new filter(outer vlan+ inner vlan)
12382  *      a.      Valid_flags.replace_cloud = 1
12383  *      b.      Old_filter = 1 (instead of outer IP)
12384  *      c.      New_filter = 0x10
12385  *      d.      Buffer – 2 entries:
12386  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12387  *                      Byte 1-3 = 0 (rsv)
12388  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12389  *                      Byte 9-11 = 0 (rsv)
12390  */
12391 static int
12392 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12393 {
12394         int ret = -ENOTSUP;
12395         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12396         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12397         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12398         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12399
12400         if (pf->support_multi_driver) {
12401                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12402                 return ret;
12403         }
12404
12405         /* Init */
12406         memset(&filter_replace, 0,
12407                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12408         memset(&filter_replace_buf, 0,
12409                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12410
12411         /* create L1 filter */
12412         filter_replace.old_filter_type =
12413                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12414         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12415         filter_replace.tr_bit = 0;
12416
12417         /* Prepare the buffer, 2 entries */
12418         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12419         filter_replace_buf.data[0] |=
12420                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12421         /* Field Vector 12b mask */
12422         filter_replace_buf.data[2] = 0xff;
12423         filter_replace_buf.data[3] = 0x0f;
12424         filter_replace_buf.data[4] =
12425                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12426         filter_replace_buf.data[4] |=
12427                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12428         /* Field Vector 12b mask */
12429         filter_replace_buf.data[6] = 0xff;
12430         filter_replace_buf.data[7] = 0x0f;
12431         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12432                         &filter_replace_buf);
12433         if (ret != I40E_SUCCESS)
12434                 return ret;
12435
12436         if (filter_replace.old_filter_type !=
12437             filter_replace.new_filter_type)
12438                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12439                             " original: 0x%x, new: 0x%x",
12440                             dev->device->name,
12441                             filter_replace.old_filter_type,
12442                             filter_replace.new_filter_type);
12443
12444         /* Apply the second L2 cloud filter */
12445         memset(&filter_replace, 0,
12446                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12447         memset(&filter_replace_buf, 0,
12448                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12449
12450         /* create L2 filter, input for L2 filter will be L1 filter  */
12451         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12452         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12453         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12454
12455         /* Prepare the buffer, 2 entries */
12456         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12457         filter_replace_buf.data[0] |=
12458                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12459         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12460         filter_replace_buf.data[4] |=
12461                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12462         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12463                         &filter_replace_buf);
12464         if (!ret && (filter_replace.old_filter_type !=
12465                      filter_replace.new_filter_type))
12466                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12467                             " original: 0x%x, new: 0x%x",
12468                             dev->device->name,
12469                             filter_replace.old_filter_type,
12470                             filter_replace.new_filter_type);
12471
12472         return ret;
12473 }
12474
12475 int
12476 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12477                    const struct rte_flow_action_rss *in)
12478 {
12479         if (in->key_len > RTE_DIM(out->key) ||
12480             in->queue_num > RTE_DIM(out->queue))
12481                 return -EINVAL;
12482         out->conf = (struct rte_flow_action_rss){
12483                 .func = in->func,
12484                 .level = in->level,
12485                 .types = in->types,
12486                 .key_len = in->key_len,
12487                 .queue_num = in->queue_num,
12488                 .key = memcpy(out->key, in->key, in->key_len),
12489                 .queue = memcpy(out->queue, in->queue,
12490                                 sizeof(*in->queue) * in->queue_num),
12491         };
12492         return 0;
12493 }
12494
12495 int
12496 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12497                      const struct rte_flow_action_rss *with)
12498 {
12499         return (comp->func == with->func &&
12500                 comp->level == with->level &&
12501                 comp->types == with->types &&
12502                 comp->key_len == with->key_len &&
12503                 comp->queue_num == with->queue_num &&
12504                 !memcmp(comp->key, with->key, with->key_len) &&
12505                 !memcmp(comp->queue, with->queue,
12506                         sizeof(*with->queue) * with->queue_num));
12507 }
12508
12509 int
12510 i40e_config_rss_filter(struct i40e_pf *pf,
12511                 struct i40e_rte_flow_rss_conf *conf, bool add)
12512 {
12513         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12514         uint32_t i, lut = 0;
12515         uint16_t j, num;
12516         struct rte_eth_rss_conf rss_conf = {
12517                 .rss_key = conf->conf.key_len ?
12518                         (void *)(uintptr_t)conf->conf.key : NULL,
12519                 .rss_key_len = conf->conf.key_len,
12520                 .rss_hf = conf->conf.types,
12521         };
12522         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12523
12524         if (!add) {
12525                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12526                         i40e_pf_disable_rss(pf);
12527                         memset(rss_info, 0,
12528                                 sizeof(struct i40e_rte_flow_rss_conf));
12529                         return 0;
12530                 }
12531                 return -EINVAL;
12532         }
12533
12534         if (rss_info->conf.queue_num)
12535                 return -EINVAL;
12536
12537         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12538          * It's necessary to calculate the actual PF queues that are configured.
12539          */
12540         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12541                 num = i40e_pf_calc_configured_queues_num(pf);
12542         else
12543                 num = pf->dev_data->nb_rx_queues;
12544
12545         num = RTE_MIN(num, conf->conf.queue_num);
12546         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12547                         num);
12548
12549         if (num == 0) {
12550                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12551                 return -ENOTSUP;
12552         }
12553
12554         /* Fill in redirection table */
12555         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12556                 if (j == num)
12557                         j = 0;
12558                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12559                         hw->func_caps.rss_table_entry_width) - 1));
12560                 if ((i & 3) == 3)
12561                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12562         }
12563
12564         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12565                 i40e_pf_disable_rss(pf);
12566                 return 0;
12567         }
12568         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12569                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12570                 /* Random default keys */
12571                 static uint32_t rss_key_default[] = {0x6b793944,
12572                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12573                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12574                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12575
12576                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12577                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12578                                                         sizeof(uint32_t);
12579         }
12580
12581         i40e_hw_rss_hash_set(pf, &rss_conf);
12582
12583         if (i40e_rss_conf_init(rss_info, &conf->conf))
12584                 return -EINVAL;
12585
12586         return 0;
12587 }
12588
12589 RTE_INIT(i40e_init_log)
12590 {
12591         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12592         if (i40e_logtype_init >= 0)
12593                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12594         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12595         if (i40e_logtype_driver >= 0)
12596                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12597 }
12598
12599 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12600                               ETH_I40E_FLOATING_VEB_ARG "=1"
12601                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12602                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12603                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");