drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64
  65 /* Maximun number of MAC addresses */
  66 #define I40E_NUM_MACADDR_MAX       64
  67 #define I40E_CLEAR_PXE_WAIT_MS     200
  68
  69 /* Maximun number of capability elements */
  70 #define I40E_MAX_CAP_ELE_NUM       128
  71
  72 /* Wait count and inteval */
  73 #define I40E_CHK_Q_ENA_COUNT       1000
  74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  75
  76 /* Maximun number of VSI */
  77 #define I40E_MAX_NUM_VSIS          (384UL)
  78
  79 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  80
  81 /* Flow control default timer */
  82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  83
  84 /* Flow control default high water */
  85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  86
  87 /* Flow control default low water */
  88 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Receive Average Packet Size in Byte*/
 100 #define I40E_PACKET_AVERAGE_SIZE 128
 101
 102 /* Mask of PF interrupt causes */
 103 #define I40E_PFINT_ICR0_ENA_MASK ( \
 104                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 105                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 106                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 107                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 108                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 110                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 114
 115 #define I40E_FLOW_TYPES ( \
 116         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 127
 128 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 129 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 130 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 131 #define I40E_PRTTSYN_TSYNENA  0x80000000
 132 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 133
 134 #define I40E_MAX_PERCENT            100
 135 #define I40E_DEFAULT_DCB_APP_NUM    1
 136 #define I40E_DEFAULT_DCB_APP_PRIO   3
 137
 138 #define I40E_PRTQF_FD_INSET(_i, _j)  (0x00250000 + ((_i) * 64 + (_j) * 32))
 139 #define I40E_GLQF_FD_MSK(_i, _j)     (0x00267200 + ((_i) * 4 + (_j) * 8))
 140 #define I40E_GLQF_FD_MSK_FIELD       0x0000FFFF
 141 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))
 142 #define I40E_GLQF_HASH_MSK(_i, _j)   (0x00267A00 + ((_i) * 4 + (_j) * 8))
 143 #define I40E_GLQF_HASH_MSK_FIELD      0x0000FFFF
 144
 145 #define I40E_INSET_NONE            0x00000000000000000ULL
 146
 147 /* bit0 ~ bit 7 */
 148 #define I40E_INSET_DMAC            0x0000000000000001ULL
 149 #define I40E_INSET_SMAC            0x0000000000000002ULL
 150 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 151 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 152 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 153
 154 /* bit 8 ~ bit 15 */
 155 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 156 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 157 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 158 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 159 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 160 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 161 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 162
 163 /* bit 16 ~ bit 31 */
 164 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 165 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 166 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 167 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 168 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 169 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 170 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 171 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 172
 173 /* bit 32 ~ bit 47, tunnel fields */
 174 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 175 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 176 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 177 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 178 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 179 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 180
 181 /* bit 48 ~ bit 55 */
 182 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 183
 184 /* bit 56 ~ bit 63, Flex Payload */
 185 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 191 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 192 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 193 #define I40E_INSET_FLEX_PAYLOAD \
 194         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 195         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W3 | \
 196         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 197         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 198
 199 /**
 200  * Below are values for writing un-exposed registers suggested
 201  * by silicon experts
 202  */
 203 /* Destination MAC address */
 204 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 205 /* Source MAC address */
 206 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 207 /* VLAN tag in the outer L2 header */
 208 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000000800000ULL
 209 /* VLAN tag in the inner L2 header */
 210 #define I40E_REG_INSET_L2_INNER_VLAN             0x0000000001000000ULL
 211 /* Source IPv4 address */
 212 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 213 /* Destination IPv4 address */
 214 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 215 /* IPv4 Type of Service (TOS) */
 216 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 217 /* IPv4 Protocol */
 218 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 219 /* Source IPv6 address */
 220 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 221 /* Destination IPv6 address */
 222 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 223 /* IPv6 Traffic Class (TC) */
 224 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 225 /* IPv6 Next Header */
 226 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 227 /* Source L4 port */
 228 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 229 /* Destination L4 port */
 230 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 231 /* SCTP verification tag */
 232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 235 /* Source port of tunneling UDP */
 236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 237 /* Destination port of tunneling UDP */
 238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 239 /* UDP Tunneling ID, NVGRE/GRE key */
 240 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 241 /* Last ether type */
 242 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 243 /* Tunneling outer destination IPv4 address */
 244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 245 /* Tunneling outer destination IPv6 address */
 246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 247 /* 1st word of flex payload */
 248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 249 /* 2nd word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 251 /* 3rd word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 253 /* 4th word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 255 /* 5th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 257 /* 6th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 259 /* 7th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 261 /* 8th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 263
 264 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 265
 266 #define I40E_TRANSLATE_INSET 0
 267 #define I40E_TRANSLATE_REG   1
 268
 269 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 270 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 271 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 272 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 273
 274 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 275 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 276 static int i40e_dev_configure(struct rte_eth_dev *dev);
 277 static int i40e_dev_start(struct rte_eth_dev *dev);
 278 static void i40e_dev_stop(struct rte_eth_dev *dev);
 279 static void i40e_dev_close(struct rte_eth_dev *dev);
 280 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 281 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 282 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 283 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 284 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 285 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 286 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 287                                struct rte_eth_stats *stats);
 288 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 289                                struct rte_eth_xstats *xstats, unsigned n);
 290 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 291 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 292                                             uint16_t queue_id,
 293                                             uint8_t stat_idx,
 294                                             uint8_t is_rx);
 295 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 296                               struct rte_eth_dev_info *dev_info);
 297 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 298                                 uint16_t vlan_id,
 299                                 int on);
 300 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 301 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 302 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 303                                       uint16_t queue,
 304                                       int on);
 305 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 306 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 307 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 308 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 309                               struct rte_eth_fc_conf *fc_conf);
 310 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 311                               struct rte_eth_fc_conf *fc_conf);
 312 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 313                                        struct rte_eth_pfc_conf *pfc_conf);
 314 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 315                           struct ether_addr *mac_addr,
 316                           uint32_t index,
 317                           uint32_t pool);
 318 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 319 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 320                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 321                                     uint16_t reta_size);
 322 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 323                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 324                                    uint16_t reta_size);
 325
 326 static int i40e_get_cap(struct i40e_hw *hw);
 327 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 328 static int i40e_pf_setup(struct i40e_pf *pf);
 329 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 330 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 331 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 332 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 333 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 334                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 335 static void i40e_stat_update_48(struct i40e_hw *hw,
 336                                uint32_t hireg,
 337                                uint32_t loreg,
 338                                bool offset_loaded,
 339                                uint64_t *offset,
 340                                uint64_t *stat);
 341 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 342 static void i40e_dev_interrupt_handler(
 343                 __rte_unused struct rte_intr_handle *handle, void *param);
 344 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 345                                 uint32_t base, uint32_t num);
 346 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 347 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 348                         uint32_t base);
 349 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 350                         uint16_t num);
 351 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 352 static int i40e_veb_release(struct i40e_veb *veb);
 353 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 354                                                 struct i40e_vsi *vsi);
 355 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 356 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 357 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 358                                              struct i40e_macvlan_filter *mv_f,
 359                                              int num,
 360                                              struct ether_addr *addr);
 361 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 362                                              struct i40e_macvlan_filter *mv_f,
 363                                              int num,
 364                                              uint16_t vlan);
 365 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 366 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 367                                     struct rte_eth_rss_conf *rss_conf);
 368 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 369                                       struct rte_eth_rss_conf *rss_conf);
 370 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 371                                 struct rte_eth_udp_tunnel *udp_tunnel);
 372 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 373                                 struct rte_eth_udp_tunnel *udp_tunnel);
 374 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 375                         struct rte_eth_ethertype_filter *filter,
 376                         bool add);
 377 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 378                                 enum rte_filter_op filter_op,
 379                                 void *arg);
 380 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 381                                 enum rte_filter_type filter_type,
 382                                 enum rte_filter_op filter_op,
 383                                 void *arg);
 384 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 385                                   struct rte_eth_dcb_info *dcb_info);
 386 static void i40e_configure_registers(struct i40e_hw *hw);
 387 static void i40e_hw_init(struct i40e_hw *hw);
 388 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 389 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 390                         struct rte_eth_mirror_conf *mirror_conf,
 391                         uint8_t sw_id, uint8_t on);
 392 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 393
 394 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 395 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 396 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 397                                            struct timespec *timestamp,
 398                                            uint32_t flags);
 399 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 400                                            struct timespec *timestamp);
 401 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 402 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 403                                          uint16_t queue_id);
 404 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 405                                           uint16_t queue_id);
 406
 407 static const struct rte_pci_id pci_id_i40e_map[] = {
 408 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 409 #include "rte_pci_dev_ids.h"
 410 { .vendor_id = 0, /* sentinel */ },
 411 };
 412
 413 static const struct eth_dev_ops i40e_eth_dev_ops = {
 414         .dev_configure                = i40e_dev_configure,
 415         .dev_start                    = i40e_dev_start,
 416         .dev_stop                     = i40e_dev_stop,
 417         .dev_close                    = i40e_dev_close,
 418         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 419         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 420         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 421         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 422         .dev_set_link_up              = i40e_dev_set_link_up,
 423         .dev_set_link_down            = i40e_dev_set_link_down,
 424         .link_update                  = i40e_dev_link_update,
 425         .stats_get                    = i40e_dev_stats_get,
 426         .xstats_get                   = i40e_dev_xstats_get,
 427         .stats_reset                  = i40e_dev_stats_reset,
 428         .xstats_reset                 = i40e_dev_stats_reset,
 429         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 430         .dev_infos_get                = i40e_dev_info_get,
 431         .vlan_filter_set              = i40e_vlan_filter_set,
 432         .vlan_tpid_set                = i40e_vlan_tpid_set,
 433         .vlan_offload_set             = i40e_vlan_offload_set,
 434         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 435         .vlan_pvid_set                = i40e_vlan_pvid_set,
 436         .rx_queue_start               = i40e_dev_rx_queue_start,
 437         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 438         .tx_queue_start               = i40e_dev_tx_queue_start,
 439         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 440         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 441         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 442         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 443         .rx_queue_release             = i40e_dev_rx_queue_release,
 444         .rx_queue_count               = i40e_dev_rx_queue_count,
 445         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 446         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 447         .tx_queue_release             = i40e_dev_tx_queue_release,
 448         .dev_led_on                   = i40e_dev_led_on,
 449         .dev_led_off                  = i40e_dev_led_off,
 450         .flow_ctrl_get                = i40e_flow_ctrl_get,
 451         .flow_ctrl_set                = i40e_flow_ctrl_set,
 452         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 453         .mac_addr_add                 = i40e_macaddr_add,
 454         .mac_addr_remove              = i40e_macaddr_remove,
 455         .reta_update                  = i40e_dev_rss_reta_update,
 456         .reta_query                   = i40e_dev_rss_reta_query,
 457         .rss_hash_update              = i40e_dev_rss_hash_update,
 458         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 459         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 460         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 461         .filter_ctrl                  = i40e_dev_filter_ctrl,
 462         .rxq_info_get                 = i40e_rxq_info_get,
 463         .txq_info_get                 = i40e_txq_info_get,
 464         .mirror_rule_set              = i40e_mirror_rule_set,
 465         .mirror_rule_reset            = i40e_mirror_rule_reset,
 466         .timesync_enable              = i40e_timesync_enable,
 467         .timesync_disable             = i40e_timesync_disable,
 468         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 469         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 470         .get_dcb_info                 = i40e_dev_get_dcb_info,
 471 };
 472
 473 /* store statistics names and its offset in stats structure */
 474 struct rte_i40e_xstats_name_off {
 475         char name[RTE_ETH_XSTATS_NAME_SIZE];
 476         unsigned offset;
 477 };
 478
 479 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 480         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 481         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 482         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 483         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 484         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 485                 rx_unknown_protocol)},
 486         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 487         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 488         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 489         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 490 };
 491
 492 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 493                 sizeof(rte_i40e_stats_strings[0]))
 494
 495 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 496         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 497                 tx_dropped_link_down)},
 498         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 499         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 500                 illegal_bytes)},
 501         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 502         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 503                 mac_local_faults)},
 504         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 505                 mac_remote_faults)},
 506         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 507                 rx_length_errors)},
 508         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 509         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 510         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 511         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 512         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 513         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 514                 rx_size_127)},
 515         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 516                 rx_size_255)},
 517         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 518                 rx_size_511)},
 519         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 520                 rx_size_1023)},
 521         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 522                 rx_size_1522)},
 523         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 524                 rx_size_big)},
 525         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 526                 rx_undersize)},
 527         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 528                 rx_oversize)},
 529         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 530                 mac_short_packet_dropped)},
 531         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 532                 rx_fragments)},
 533         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 534         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 535         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 536                 tx_size_127)},
 537         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 538                 tx_size_255)},
 539         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 540                 tx_size_511)},
 541         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 542                 tx_size_1023)},
 543         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 544                 tx_size_1522)},
 545         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 546                 tx_size_big)},
 547         {"rx_flow_director_atr_match_packets",
 548                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 549         {"rx_flow_director_sb_match_packets",
 550                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 551         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 552                 tx_lpi_status)},
 553         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 554                 rx_lpi_status)},
 555         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 556                 tx_lpi_count)},
 557         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 558                 rx_lpi_count)},
 559 };
 560
 561 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 562                 sizeof(rte_i40e_hw_port_strings[0]))
 563
 564 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 565         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 566                 priority_xon_rx)},
 567         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 568                 priority_xoff_rx)},
 569 };
 570
 571 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 572                 sizeof(rte_i40e_rxq_prio_strings[0]))
 573
 574 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 575         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 576                 priority_xon_tx)},
 577         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 578                 priority_xoff_tx)},
 579         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 580                 priority_xon_2_xoff)},
 581 };
 582
 583 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 584                 sizeof(rte_i40e_txq_prio_strings[0]))
 585
 586 static struct eth_driver rte_i40e_pmd = {
 587         .pci_drv = {
 588                 .name = "rte_i40e_pmd",
 589                 .id_table = pci_id_i40e_map,
 590                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 591                         RTE_PCI_DRV_DETACHABLE,
 592         },
 593         .eth_dev_init = eth_i40e_dev_init,
 594         .eth_dev_uninit = eth_i40e_dev_uninit,
 595         .dev_private_size = sizeof(struct i40e_adapter),
 596 };
 597
 598 static inline int
 599 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 600                                      struct rte_eth_link *link)
 601 {
 602         struct rte_eth_link *dst = link;
 603         struct rte_eth_link *src = &(dev->data->dev_link);
 604
 605         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 606                                         *(uint64_t *)src) == 0)
 607                 return -1;
 608
 609         return 0;
 610 }
 611
 612 static inline int
 613 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 614                                       struct rte_eth_link *link)
 615 {
 616         struct rte_eth_link *dst = &(dev->data->dev_link);
 617         struct rte_eth_link *src = link;
 618
 619         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 620                                         *(uint64_t *)src) == 0)
 621                 return -1;
 622
 623         return 0;
 624 }
 625
 626 /*
 627  * Driver initialization routine.
 628  * Invoked once at EAL init time.
 629  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 630  */
 631 static int
 632 rte_i40e_pmd_init(const char *name __rte_unused,
 633                   const char *params __rte_unused)
 634 {
 635         PMD_INIT_FUNC_TRACE();
 636         rte_eth_driver_register(&rte_i40e_pmd);
 637
 638         return 0;
 639 }
 640
 641 static struct rte_driver rte_i40e_driver = {
 642         .type = PMD_PDEV,
 643         .init = rte_i40e_pmd_init,
 644 };
 645
 646 PMD_REGISTER_DRIVER(rte_i40e_driver);
 647
 648 /*
 649  * Initialize registers for flexible payload, which should be set by NVM.
 650  * This should be removed from code once it is fixed in NVM.
 651  */
 652 #ifndef I40E_GLQF_ORT
 653 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 654 #endif
 655 #ifndef I40E_GLQF_PIT
 656 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 657 #endif
 658
 659 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 660 {
 661         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 662         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 663         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 664         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 665         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 666         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 667         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 668         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 669         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 670         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 671
 672         /* GLQF_PIT Registers */
 673         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 674         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 675 }
 676
 677 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 678
 679 /*
 680  * Add a ethertype filter to drop all flow control frames transmitted
 681  * from VSIs.
 682 */
 683 static void
 684 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 685 {
 686         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 687         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 688                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 689                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 690         int ret;
 691
 692         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 693                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 694                                 pf->main_vsi_seid, 0,
 695                                 TRUE, NULL, NULL);
 696         if (ret)
 697                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 698                                   " frames from VSIs.");
 699 }
 700
 701 static int
 702 eth_i40e_dev_init(struct rte_eth_dev *dev)
 703 {
 704         struct rte_pci_device *pci_dev;
 705         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 706         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 707         struct i40e_vsi *vsi;
 708         int ret;
 709         uint32_t len;
 710         uint8_t aq_fail = 0;
 711
 712         PMD_INIT_FUNC_TRACE();
 713
 714         dev->dev_ops = &i40e_eth_dev_ops;
 715         dev->rx_pkt_burst = i40e_recv_pkts;
 716         dev->tx_pkt_burst = i40e_xmit_pkts;
 717
 718         /* for secondary processes, we don't initialise any further as primary
 719          * has already done this work. Only check we don't need a different
 720          * RX function */
 721         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 722                 i40e_set_rx_function(dev);
 723                 i40e_set_tx_function(dev);
 724                 return 0;
 725         }
 726         pci_dev = dev->pci_dev;
 727
 728         rte_eth_copy_pci_info(dev, pci_dev);
 729
 730         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 731         pf->adapter->eth_dev = dev;
 732         pf->dev_data = dev->data;
 733
 734         hw->back = I40E_PF_TO_ADAPTER(pf);
 735         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 736         if (!hw->hw_addr) {
 737                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 738                              "as address is NULL");
 739                 return -ENODEV;
 740         }
 741
 742         hw->vendor_id = pci_dev->id.vendor_id;
 743         hw->device_id = pci_dev->id.device_id;
 744         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 745         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 746         hw->bus.device = pci_dev->addr.devid;
 747         hw->bus.func = pci_dev->addr.function;
 748         hw->adapter_stopped = 0;
 749
 750         /* Make sure all is clean before doing PF reset */
 751         i40e_clear_hw(hw);
 752
 753         /* Initialize the hardware */
 754         i40e_hw_init(hw);
 755
 756         /* Reset here to make sure all is clean for each PF */
 757         ret = i40e_pf_reset(hw);
 758         if (ret) {
 759                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 760                 return ret;
 761         }
 762
 763         /* Initialize the shared code (base driver) */
 764         ret = i40e_init_shared_code(hw);
 765         if (ret) {
 766                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 767                 return ret;
 768         }
 769
 770         /*
 771          * To work around the NVM issue,initialize registers
 772          * for flexible payload by software.
 773          * It should be removed once issues are fixed in NVM.
 774          */
 775         i40e_flex_payload_reg_init(hw);
 776
 777         /* Initialize the parameters for adminq */
 778         i40e_init_adminq_parameter(hw);
 779         ret = i40e_init_adminq(hw);
 780         if (ret != I40E_SUCCESS) {
 781                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 782                 return -EIO;
 783         }
 784         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 785                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 786                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 787                      ((hw->nvm.version >> 12) & 0xf),
 788                      ((hw->nvm.version >> 4) & 0xff),
 789                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 790
 791         /* Clear PXE mode */
 792         i40e_clear_pxe_mode(hw);
 793
 794         /*
 795          * On X710, performance number is far from the expectation on recent
 796          * firmware versions. The fix for this issue may not be integrated in
 797          * the following firmware version. So the workaround in software driver
 798          * is needed. It needs to modify the initial values of 3 internal only
 799          * registers. Note that the workaround can be removed when it is fixed
 800          * in firmware in the future.
 801          */
 802         i40e_configure_registers(hw);
 803
 804         /* Get hw capabilities */
 805         ret = i40e_get_cap(hw);
 806         if (ret != I40E_SUCCESS) {
 807                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 808                 goto err_get_capabilities;
 809         }
 810
 811         /* Initialize parameters for PF */
 812         ret = i40e_pf_parameter_init(dev);
 813         if (ret != 0) {
 814                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 815                 goto err_parameter_init;
 816         }
 817
 818         /* Initialize the queue management */
 819         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 820         if (ret < 0) {
 821                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 822                 goto err_qp_pool_init;
 823         }
 824         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 825                                 hw->func_caps.num_msix_vectors - 1);
 826         if (ret < 0) {
 827                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 828                 goto err_msix_pool_init;
 829         }
 830
 831         /* Initialize lan hmc */
 832         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 833                                 hw->func_caps.num_rx_qp, 0, 0);
 834         if (ret != I40E_SUCCESS) {
 835                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 836                 goto err_init_lan_hmc;
 837         }
 838
 839         /* Configure lan hmc */
 840         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 841         if (ret != I40E_SUCCESS) {
 842                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 843                 goto err_configure_lan_hmc;
 844         }
 845
 846         /* Get and check the mac address */
 847         i40e_get_mac_addr(hw, hw->mac.addr);
 848         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 849                 PMD_INIT_LOG(ERR, "mac address is not valid");
 850                 ret = -EIO;
 851                 goto err_get_mac_addr;
 852         }
 853         /* Copy the permanent MAC address */
 854         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 855                         (struct ether_addr *) hw->mac.perm_addr);
 856
 857         /* Disable flow control */
 858         hw->fc.requested_mode = I40E_FC_NONE;
 859         i40e_set_fc(hw, &aq_fail, TRUE);
 860
 861         /* PF setup, which includes VSI setup */
 862         ret = i40e_pf_setup(pf);
 863         if (ret) {
 864                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 865                 goto err_setup_pf_switch;
 866         }
 867
 868         vsi = pf->main_vsi;
 869
 870         /* Disable double vlan by default */
 871         i40e_vsi_config_double_vlan(vsi, FALSE);
 872
 873         if (!vsi->max_macaddrs)
 874                 len = ETHER_ADDR_LEN;
 875         else
 876                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 877
 878         /* Should be after VSI initialized */
 879         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 880         if (!dev->data->mac_addrs) {
 881                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 882                                         "for storing mac address");
 883                 goto err_mac_alloc;
 884         }
 885         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 886                                         &dev->data->mac_addrs[0]);
 887
 888         /* initialize pf host driver to setup SRIOV resource if applicable */
 889         i40e_pf_host_init(dev);
 890
 891         /* register callback func to eal lib */
 892         rte_intr_callback_register(&(pci_dev->intr_handle),
 893                 i40e_dev_interrupt_handler, (void *)dev);
 894
 895         /* configure and enable device interrupt */
 896         i40e_pf_config_irq0(hw, TRUE);
 897         i40e_pf_enable_irq0(hw);
 898
 899         /* enable uio intr after callback register */
 900         rte_intr_enable(&(pci_dev->intr_handle));
 901         /*
 902          * Add an ethertype filter to drop all flow control frames transmitted
 903          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 904          * frames to wire.
 905          */
 906         i40e_add_tx_flow_control_drop_filter(pf);
 907
 908         /* initialize mirror rule list */
 909         TAILQ_INIT(&pf->mirror_list);
 910
 911         /* Init dcb to sw mode by default */
 912         ret = i40e_dcb_init_configure(dev, TRUE);
 913         if (ret != I40E_SUCCESS) {
 914                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 915                 pf->flags &= ~I40E_FLAG_DCB;
 916         }
 917
 918         return 0;
 919
 920 err_mac_alloc:
 921         i40e_vsi_release(pf->main_vsi);
 922 err_setup_pf_switch:
 923 err_get_mac_addr:
 924 err_configure_lan_hmc:
 925         (void)i40e_shutdown_lan_hmc(hw);
 926 err_init_lan_hmc:
 927         i40e_res_pool_destroy(&pf->msix_pool);
 928 err_msix_pool_init:
 929         i40e_res_pool_destroy(&pf->qp_pool);
 930 err_qp_pool_init:
 931 err_parameter_init:
 932 err_get_capabilities:
 933         (void)i40e_shutdown_adminq(hw);
 934
 935         return ret;
 936 }
 937
 938 static int
 939 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 940 {
 941         struct rte_pci_device *pci_dev;
 942         struct i40e_hw *hw;
 943         struct i40e_filter_control_settings settings;
 944         int ret;
 945         uint8_t aq_fail = 0;
 946
 947         PMD_INIT_FUNC_TRACE();
 948
 949         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 950                 return 0;
 951
 952         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 953         pci_dev = dev->pci_dev;
 954
 955         if (hw->adapter_stopped == 0)
 956                 i40e_dev_close(dev);
 957
 958         dev->dev_ops = NULL;
 959         dev->rx_pkt_burst = NULL;
 960         dev->tx_pkt_burst = NULL;
 961
 962         /* Disable LLDP */
 963         ret = i40e_aq_stop_lldp(hw, true, NULL);
 964         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 965                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 966
 967         /* Clear PXE mode */
 968         i40e_clear_pxe_mode(hw);
 969
 970         /* Unconfigure filter control */
 971         memset(&settings, 0, sizeof(settings));
 972         ret = i40e_set_filter_control(hw, &settings);
 973         if (ret)
 974                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 975                                         ret);
 976
 977         /* Disable flow control */
 978         hw->fc.requested_mode = I40E_FC_NONE;
 979         i40e_set_fc(hw, &aq_fail, TRUE);
 980
 981         /* uninitialize pf host driver */
 982         i40e_pf_host_uninit(dev);
 983
 984         rte_free(dev->data->mac_addrs);
 985         dev->data->mac_addrs = NULL;
 986
 987         /* disable uio intr before callback unregister */
 988         rte_intr_disable(&(pci_dev->intr_handle));
 989
 990         /* register callback func to eal lib */
 991         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 992                 i40e_dev_interrupt_handler, (void *)dev);
 993
 994         return 0;
 995 }
 996
 997 static int
 998 i40e_dev_configure(struct rte_eth_dev *dev)
 999 {
1000         struct i40e_adapter *ad =
1001                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1002         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1003         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1004         int i, ret;
1005
1006         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1007          * bulk allocation or vector Rx preconditions we will reset it.
1008          */
1009         ad->rx_bulk_alloc_allowed = true;
1010         ad->rx_vec_allowed = true;
1011         ad->tx_simple_allowed = true;
1012         ad->tx_vec_allowed = true;
1013
1014         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1015                 ret = i40e_fdir_setup(pf);
1016                 if (ret != I40E_SUCCESS) {
1017                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1018                         return -ENOTSUP;
1019                 }
1020                 ret = i40e_fdir_configure(dev);
1021                 if (ret < 0) {
1022                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1023                         goto err;
1024                 }
1025         } else
1026                 i40e_fdir_teardown(pf);
1027
1028         ret = i40e_dev_init_vlan(dev);
1029         if (ret < 0)
1030                 goto err;
1031
1032         /* VMDQ setup.
1033          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1034          *  RSS setting have different requirements.
1035          *  General PMD driver call sequence are NIC init, configure,
1036          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1037          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1038          *  applicable. So, VMDQ setting has to be done before
1039          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1040          *  For RSS setting, it will try to calculate actual configured RX queue
1041          *  number, which will be available after rx_queue_setup(). dev_start()
1042          *  function is good to place RSS setup.
1043          */
1044         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1045                 ret = i40e_vmdq_setup(dev);
1046                 if (ret)
1047                         goto err;
1048         }
1049
1050         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1051                 ret = i40e_dcb_setup(dev);
1052                 if (ret) {
1053                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1054                         goto err_dcb;
1055                 }
1056         }
1057
1058         return 0;
1059
1060 err_dcb:
1061         /* need to release vmdq resource if exists */
1062         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1063                 i40e_vsi_release(pf->vmdq[i].vsi);
1064                 pf->vmdq[i].vsi = NULL;
1065         }
1066         rte_free(pf->vmdq);
1067         pf->vmdq = NULL;
1068 err:
1069         /* need to release fdir resource if exists */
1070         i40e_fdir_teardown(pf);
1071         return ret;
1072 }
1073
1074 void
1075 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1076 {
1077         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1078         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1079         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1080         uint16_t msix_vect = vsi->msix_intr;
1081         uint16_t i;
1082
1083         for (i = 0; i < vsi->nb_qps; i++) {
1084                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1085                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1086                 rte_wmb();
1087         }
1088
1089         if (vsi->type != I40E_VSI_SRIOV) {
1090                 if (!rte_intr_allow_others(intr_handle)) {
1091                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1092                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1093                         I40E_WRITE_REG(hw,
1094                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1095                                        0);
1096                 } else {
1097                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1098                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1099                         I40E_WRITE_REG(hw,
1100                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1101                                                        msix_vect - 1), 0);
1102                 }
1103         } else {
1104                 uint32_t reg;
1105                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1106                         vsi->user_param + (msix_vect - 1);
1107
1108                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1109                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1110         }
1111         I40E_WRITE_FLUSH(hw);
1112 }
1113
1114 static void
1115 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1116                        int base_queue, int nb_queue)
1117 {
1118         int i;
1119         uint32_t val;
1120         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1121
1122         /* Bind all RX queues to allocated MSIX interrupt */
1123         for (i = 0; i < nb_queue; i++) {
1124                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1125                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1126                         ((base_queue + i + 1) <<
1127                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1128                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1129                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1130
1131                 if (i == nb_queue - 1)
1132                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1133                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1134         }
1135
1136         /* Write first RX queue to Link list register as the head element */
1137         if (vsi->type != I40E_VSI_SRIOV) {
1138                 uint16_t interval =
1139                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1140
1141                 if (msix_vect == I40E_MISC_VEC_ID) {
1142                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1143                                        (base_queue <<
1144                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1145                                        (0x0 <<
1146                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1147                         I40E_WRITE_REG(hw,
1148                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1149                                        interval);
1150                 } else {
1151                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1152                                        (base_queue <<
1153                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1154                                        (0x0 <<
1155                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1156                         I40E_WRITE_REG(hw,
1157                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1158                                                        msix_vect - 1),
1159                                        interval);
1160                 }
1161         } else {
1162                 uint32_t reg;
1163
1164                 if (msix_vect == I40E_MISC_VEC_ID) {
1165                         I40E_WRITE_REG(hw,
1166                                        I40E_VPINT_LNKLST0(vsi->user_param),
1167                                        (base_queue <<
1168                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1169                                        (0x0 <<
1170                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1171                 } else {
1172                         /* num_msix_vectors_vf needs to minus irq0 */
1173                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1174                                 vsi->user_param + (msix_vect - 1);
1175
1176                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1177                                        (base_queue <<
1178                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1179                                        (0x0 <<
1180                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1181                 }
1182         }
1183
1184         I40E_WRITE_FLUSH(hw);
1185 }
1186
1187 void
1188 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1189 {
1190         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1191         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1192         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1193         uint16_t msix_vect = vsi->msix_intr;
1194         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1195         uint16_t queue_idx = 0;
1196         int record = 0;
1197         uint32_t val;
1198         int i;
1199
1200         for (i = 0; i < vsi->nb_qps; i++) {
1201                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1202                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1203         }
1204
1205         /* INTENA flag is not auto-cleared for interrupt */
1206         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1207         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1208                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1209                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1210         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1211
1212         /* VF bind interrupt */
1213         if (vsi->type == I40E_VSI_SRIOV) {
1214                 __vsi_queues_bind_intr(vsi, msix_vect,
1215                                        vsi->base_queue, vsi->nb_qps);
1216                 return;
1217         }
1218
1219         /* PF & VMDq bind interrupt */
1220         if (rte_intr_dp_is_en(intr_handle)) {
1221                 if (vsi->type == I40E_VSI_MAIN) {
1222                         queue_idx = 0;
1223                         record = 1;
1224                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1225                         struct i40e_vsi *main_vsi =
1226                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1227                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1228                         record = 1;
1229                 }
1230         }
1231
1232         for (i = 0; i < vsi->nb_used_qps; i++) {
1233                 if (nb_msix <= 1) {
1234                         if (!rte_intr_allow_others(intr_handle))
1235                                 /* allow to share MISC_VEC_ID */
1236                                 msix_vect = I40E_MISC_VEC_ID;
1237
1238                         /* no enough msix_vect, map all to one */
1239                         __vsi_queues_bind_intr(vsi, msix_vect,
1240                                                vsi->base_queue + i,
1241                                                vsi->nb_used_qps - i);
1242                         for (; !!record && i < vsi->nb_used_qps; i++)
1243                                 intr_handle->intr_vec[queue_idx + i] =
1244                                         msix_vect;
1245                         break;
1246                 }
1247                 /* 1:1 queue/msix_vect mapping */
1248                 __vsi_queues_bind_intr(vsi, msix_vect,
1249                                        vsi->base_queue + i, 1);
1250                 if (!!record)
1251                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1252
1253                 msix_vect++;
1254                 nb_msix--;
1255         }
1256 }
1257
1258 static void
1259 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1260 {
1261         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1262         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1263         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1264         uint16_t interval = i40e_calc_itr_interval(\
1265                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1266         uint16_t msix_intr, i;
1267
1268         if (rte_intr_allow_others(intr_handle))
1269                 for (i = 0; i < vsi->nb_msix; i++) {
1270                         msix_intr = vsi->msix_intr + i;
1271                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1272                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1273                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1274                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1275                                 (interval <<
1276                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1277                 }
1278         else
1279                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1280                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1281                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1282                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1283                                (interval <<
1284                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1285
1286         I40E_WRITE_FLUSH(hw);
1287 }
1288
1289 static void
1290 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1291 {
1292         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1293         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1294         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1295         uint16_t msix_intr, i;
1296
1297         if (rte_intr_allow_others(intr_handle))
1298                 for (i = 0; i < vsi->nb_msix; i++) {
1299                         msix_intr = vsi->msix_intr + i;
1300                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1301                                        0);
1302                 }
1303         else
1304                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1305
1306         I40E_WRITE_FLUSH(hw);
1307 }
1308
1309 static inline uint8_t
1310 i40e_parse_link_speed(uint16_t eth_link_speed)
1311 {
1312         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1313
1314         switch (eth_link_speed) {
1315         case ETH_LINK_SPEED_40G:
1316                 link_speed = I40E_LINK_SPEED_40GB;
1317                 break;
1318         case ETH_LINK_SPEED_20G:
1319                 link_speed = I40E_LINK_SPEED_20GB;
1320                 break;
1321         case ETH_LINK_SPEED_10G:
1322                 link_speed = I40E_LINK_SPEED_10GB;
1323                 break;
1324         case ETH_LINK_SPEED_1000:
1325                 link_speed = I40E_LINK_SPEED_1GB;
1326                 break;
1327         case ETH_LINK_SPEED_100:
1328                 link_speed = I40E_LINK_SPEED_100MB;
1329                 break;
1330         }
1331
1332         return link_speed;
1333 }
1334
1335 static int
1336 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
1337 {
1338         enum i40e_status_code status;
1339         struct i40e_aq_get_phy_abilities_resp phy_ab;
1340         struct i40e_aq_set_phy_config phy_conf;
1341         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1342                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1343                         I40E_AQ_PHY_FLAG_LOW_POWER;
1344         const uint8_t advt = I40E_LINK_SPEED_40GB |
1345                         I40E_LINK_SPEED_10GB |
1346                         I40E_LINK_SPEED_1GB |
1347                         I40E_LINK_SPEED_100MB;
1348         int ret = -ENOTSUP;
1349
1350         /* Skip it on 40G interfaces, as a workaround for the link issue */
1351         if (i40e_is_40G_device(hw->device_id))
1352                 return I40E_SUCCESS;
1353
1354         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1355                                               NULL);
1356         if (status)
1357                 return ret;
1358
1359         memset(&phy_conf, 0, sizeof(phy_conf));
1360
1361         /* bits 0-2 use the values from get_phy_abilities_resp */
1362         abilities &= ~mask;
1363         abilities |= phy_ab.abilities & mask;
1364
1365         /* update ablities and speed */
1366         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1367                 phy_conf.link_speed = advt;
1368         else
1369                 phy_conf.link_speed = force_speed;
1370
1371         phy_conf.abilities = abilities;
1372
1373         /* use get_phy_abilities_resp value for the rest */
1374         phy_conf.phy_type = phy_ab.phy_type;
1375         phy_conf.eee_capability = phy_ab.eee_capability;
1376         phy_conf.eeer = phy_ab.eeer_val;
1377         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1378
1379         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1380                     phy_ab.abilities, phy_ab.link_speed);
1381         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1382                     phy_conf.abilities, phy_conf.link_speed);
1383
1384         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1385         if (status)
1386                 return ret;
1387
1388         return I40E_SUCCESS;
1389 }
1390
1391 static int
1392 i40e_apply_link_speed(struct rte_eth_dev *dev)
1393 {
1394         uint8_t speed;
1395         uint8_t abilities = 0;
1396         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397         struct rte_eth_conf *conf = &dev->data->dev_conf;
1398
1399         speed = i40e_parse_link_speed(conf->link_speed);
1400         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1401         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1402                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1403         else
1404                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1405
1406         return i40e_phy_conf_link(hw, abilities, speed);
1407 }
1408
1409 static int
1410 i40e_dev_start(struct rte_eth_dev *dev)
1411 {
1412         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1413         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1414         struct i40e_vsi *main_vsi = pf->main_vsi;
1415         int ret, i;
1416         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1417         uint32_t intr_vector = 0;
1418
1419         hw->adapter_stopped = 0;
1420
1421         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1422                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1423                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1424                              dev->data->dev_conf.link_duplex,
1425                              dev->data->port_id);
1426                 return -EINVAL;
1427         }
1428
1429         rte_intr_disable(intr_handle);
1430
1431         if ((rte_intr_cap_multiple(intr_handle) ||
1432              !RTE_ETH_DEV_SRIOV(dev).active) &&
1433             dev->data->dev_conf.intr_conf.rxq != 0) {
1434                 intr_vector = dev->data->nb_rx_queues;
1435                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1436                         return -1;
1437         }
1438
1439         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1440                 intr_handle->intr_vec =
1441                         rte_zmalloc("intr_vec",
1442                                     dev->data->nb_rx_queues * sizeof(int),
1443                                     0);
1444                 if (!intr_handle->intr_vec) {
1445                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1446                                      " intr_vec\n", dev->data->nb_rx_queues);
1447                         return -ENOMEM;
1448                 }
1449         }
1450
1451         /* Initialize VSI */
1452         ret = i40e_dev_rxtx_init(pf);
1453         if (ret != I40E_SUCCESS) {
1454                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1455                 goto err_up;
1456         }
1457
1458         /* Map queues with MSIX interrupt */
1459         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1460                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1461         i40e_vsi_queues_bind_intr(main_vsi);
1462         i40e_vsi_enable_queues_intr(main_vsi);
1463
1464         /* Map VMDQ VSI queues with MSIX interrupt */
1465         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1466                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1467                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1468                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1469         }
1470
1471         /* enable FDIR MSIX interrupt */
1472         if (pf->fdir.fdir_vsi) {
1473                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1474                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1475         }
1476
1477         /* Enable all queues which have been configured */
1478         ret = i40e_dev_switch_queues(pf, TRUE);
1479         if (ret != I40E_SUCCESS) {
1480                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1481                 goto err_up;
1482         }
1483
1484         /* Enable receiving broadcast packets */
1485         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1486         if (ret != I40E_SUCCESS)
1487                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1488
1489         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1490                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1491                                                 true, NULL);
1492                 if (ret != I40E_SUCCESS)
1493                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1494         }
1495
1496         /* Apply link configure */
1497         ret = i40e_apply_link_speed(dev);
1498         if (I40E_SUCCESS != ret) {
1499                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1500                 goto err_up;
1501         }
1502
1503         if (!rte_intr_allow_others(intr_handle)) {
1504                 rte_intr_callback_unregister(intr_handle,
1505                                              i40e_dev_interrupt_handler,
1506                                              (void *)dev);
1507                 /* configure and enable device interrupt */
1508                 i40e_pf_config_irq0(hw, FALSE);
1509                 i40e_pf_enable_irq0(hw);
1510
1511                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1512                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1513                                      " no intr multiplex\n");
1514         }
1515
1516         /* enable uio intr after callback register */
1517         rte_intr_enable(intr_handle);
1518
1519         return I40E_SUCCESS;
1520
1521 err_up:
1522         i40e_dev_switch_queues(pf, FALSE);
1523         i40e_dev_clear_queues(dev);
1524
1525         return ret;
1526 }
1527
1528 static void
1529 i40e_dev_stop(struct rte_eth_dev *dev)
1530 {
1531         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1532         struct i40e_vsi *main_vsi = pf->main_vsi;
1533         struct i40e_mirror_rule *p_mirror;
1534         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1535         int i;
1536
1537         /* Disable all queues */
1538         i40e_dev_switch_queues(pf, FALSE);
1539
1540         /* un-map queues with interrupt registers */
1541         i40e_vsi_disable_queues_intr(main_vsi);
1542         i40e_vsi_queues_unbind_intr(main_vsi);
1543
1544         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1545                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1546                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1547         }
1548
1549         if (pf->fdir.fdir_vsi) {
1550                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1551                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1552         }
1553         /* Clear all queues and release memory */
1554         i40e_dev_clear_queues(dev);
1555
1556         /* Set link down */
1557         i40e_dev_set_link_down(dev);
1558
1559         /* Remove all mirror rules */
1560         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1561                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1562                 rte_free(p_mirror);
1563         }
1564         pf->nb_mirror_rule = 0;
1565
1566         if (!rte_intr_allow_others(intr_handle))
1567                 /* resume to the default handler */
1568                 rte_intr_callback_register(intr_handle,
1569                                            i40e_dev_interrupt_handler,
1570                                            (void *)dev);
1571
1572         /* Clean datapath event and queue/vec mapping */
1573         rte_intr_efd_disable(intr_handle);
1574         if (intr_handle->intr_vec) {
1575                 rte_free(intr_handle->intr_vec);
1576                 intr_handle->intr_vec = NULL;
1577         }
1578 }
1579
1580 static void
1581 i40e_dev_close(struct rte_eth_dev *dev)
1582 {
1583         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1584         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585         uint32_t reg;
1586         int i;
1587
1588         PMD_INIT_FUNC_TRACE();
1589
1590         i40e_dev_stop(dev);
1591         hw->adapter_stopped = 1;
1592         i40e_dev_free_queues(dev);
1593
1594         /* Disable interrupt */
1595         i40e_pf_disable_irq0(hw);
1596         rte_intr_disable(&(dev->pci_dev->intr_handle));
1597
1598         /* shutdown and destroy the HMC */
1599         i40e_shutdown_lan_hmc(hw);
1600
1601         /* release all the existing VSIs and VEBs */
1602         i40e_fdir_teardown(pf);
1603         i40e_vsi_release(pf->main_vsi);
1604
1605         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1606                 i40e_vsi_release(pf->vmdq[i].vsi);
1607                 pf->vmdq[i].vsi = NULL;
1608         }
1609
1610         rte_free(pf->vmdq);
1611         pf->vmdq = NULL;
1612
1613         /* shutdown the adminq */
1614         i40e_aq_queue_shutdown(hw, true);
1615         i40e_shutdown_adminq(hw);
1616
1617         i40e_res_pool_destroy(&pf->qp_pool);
1618         i40e_res_pool_destroy(&pf->msix_pool);
1619
1620         /* force a PF reset to clean anything leftover */
1621         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1622         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1623                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1624         I40E_WRITE_FLUSH(hw);
1625 }
1626
1627 static void
1628 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1629 {
1630         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1631         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1632         struct i40e_vsi *vsi = pf->main_vsi;
1633         int status;
1634
1635         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1636                                                         true, NULL);
1637         if (status != I40E_SUCCESS)
1638                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1639
1640         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1641                                                         TRUE, NULL);
1642         if (status != I40E_SUCCESS)
1643                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1644
1645 }
1646
1647 static void
1648 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1649 {
1650         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1651         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1652         struct i40e_vsi *vsi = pf->main_vsi;
1653         int status;
1654
1655         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1656                                                         false, NULL);
1657         if (status != I40E_SUCCESS)
1658                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1659
1660         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1661                                                         false, NULL);
1662         if (status != I40E_SUCCESS)
1663                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1664 }
1665
1666 static void
1667 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1668 {
1669         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1670         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1671         struct i40e_vsi *vsi = pf->main_vsi;
1672         int ret;
1673
1674         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1675         if (ret != I40E_SUCCESS)
1676                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1677 }
1678
1679 static void
1680 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1681 {
1682         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1683         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1684         struct i40e_vsi *vsi = pf->main_vsi;
1685         int ret;
1686
1687         if (dev->data->promiscuous == 1)
1688                 return; /* must remain in all_multicast mode */
1689
1690         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1691                                 vsi->seid, FALSE, NULL);
1692         if (ret != I40E_SUCCESS)
1693                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1694 }
1695
1696 /*
1697  * Set device link up.
1698  */
1699 static int
1700 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1701 {
1702         /* re-apply link speed setting */
1703         return i40e_apply_link_speed(dev);
1704 }
1705
1706 /*
1707  * Set device link down.
1708  */
1709 static int
1710 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1711 {
1712         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1713         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1714         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1715
1716         return i40e_phy_conf_link(hw, abilities, speed);
1717 }
1718
1719 int
1720 i40e_dev_link_update(struct rte_eth_dev *dev,
1721                      int wait_to_complete)
1722 {
1723 #define CHECK_INTERVAL 100  /* 100ms */
1724 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1725         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726         struct i40e_link_status link_status;
1727         struct rte_eth_link link, old;
1728         int status;
1729         unsigned rep_cnt = MAX_REPEAT_TIME;
1730
1731         memset(&link, 0, sizeof(link));
1732         memset(&old, 0, sizeof(old));
1733         memset(&link_status, 0, sizeof(link_status));
1734         rte_i40e_dev_atomic_read_link_status(dev, &old);
1735
1736         do {
1737                 /* Get link status information from hardware */
1738                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1739                 if (status != I40E_SUCCESS) {
1740                         link.link_speed = ETH_LINK_SPEED_100;
1741                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1742                         PMD_DRV_LOG(ERR, "Failed to get link info");
1743                         goto out;
1744                 }
1745
1746                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1747                 if (!wait_to_complete)
1748                         break;
1749
1750                 rte_delay_ms(CHECK_INTERVAL);
1751         } while (!link.link_status && rep_cnt--);
1752
1753         if (!link.link_status)
1754                 goto out;
1755
1756         /* i40e uses full duplex only */
1757         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1758
1759         /* Parse the link status */
1760         switch (link_status.link_speed) {
1761         case I40E_LINK_SPEED_100MB:
1762                 link.link_speed = ETH_LINK_SPEED_100;
1763                 break;
1764         case I40E_LINK_SPEED_1GB:
1765                 link.link_speed = ETH_LINK_SPEED_1000;
1766                 break;
1767         case I40E_LINK_SPEED_10GB:
1768                 link.link_speed = ETH_LINK_SPEED_10G;
1769                 break;
1770         case I40E_LINK_SPEED_20GB:
1771                 link.link_speed = ETH_LINK_SPEED_20G;
1772                 break;
1773         case I40E_LINK_SPEED_40GB:
1774                 link.link_speed = ETH_LINK_SPEED_40G;
1775                 break;
1776         default:
1777                 link.link_speed = ETH_LINK_SPEED_100;
1778                 break;
1779         }
1780
1781 out:
1782         rte_i40e_dev_atomic_write_link_status(dev, &link);
1783         if (link.link_status == old.link_status)
1784                 return -1;
1785
1786         return 0;
1787 }
1788
1789 /* Get all the statistics of a VSI */
1790 void
1791 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1792 {
1793         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1794         struct i40e_eth_stats *nes = &vsi->eth_stats;
1795         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1796         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1797
1798         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1799                             vsi->offset_loaded, &oes->rx_bytes,
1800                             &nes->rx_bytes);
1801         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1802                             vsi->offset_loaded, &oes->rx_unicast,
1803                             &nes->rx_unicast);
1804         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1805                             vsi->offset_loaded, &oes->rx_multicast,
1806                             &nes->rx_multicast);
1807         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1808                             vsi->offset_loaded, &oes->rx_broadcast,
1809                             &nes->rx_broadcast);
1810         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1811                             &oes->rx_discards, &nes->rx_discards);
1812         /* GLV_REPC not supported */
1813         /* GLV_RMPC not supported */
1814         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1815                             &oes->rx_unknown_protocol,
1816                             &nes->rx_unknown_protocol);
1817         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1818                             vsi->offset_loaded, &oes->tx_bytes,
1819                             &nes->tx_bytes);
1820         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1821                             vsi->offset_loaded, &oes->tx_unicast,
1822                             &nes->tx_unicast);
1823         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1824                             vsi->offset_loaded, &oes->tx_multicast,
1825                             &nes->tx_multicast);
1826         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1827                             vsi->offset_loaded,  &oes->tx_broadcast,
1828                             &nes->tx_broadcast);
1829         /* GLV_TDPC not supported */
1830         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1831                             &oes->tx_errors, &nes->tx_errors);
1832         vsi->offset_loaded = true;
1833
1834         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1835                     vsi->vsi_id);
1836         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1837         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1838         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1839         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1840         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1841         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1842                     nes->rx_unknown_protocol);
1843         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1844         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1845         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1846         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1847         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1848         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1849         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1850                     vsi->vsi_id);
1851 }
1852
1853 static void
1854 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1855 {
1856         unsigned int i;
1857         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1858         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1859         /* Get statistics of struct i40e_eth_stats */
1860         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1861                             I40E_GLPRT_GORCL(hw->port),
1862                             pf->offset_loaded, &os->eth.rx_bytes,
1863                             &ns->eth.rx_bytes);
1864         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1865                             I40E_GLPRT_UPRCL(hw->port),
1866                             pf->offset_loaded, &os->eth.rx_unicast,
1867                             &ns->eth.rx_unicast);
1868         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1869                             I40E_GLPRT_MPRCL(hw->port),
1870                             pf->offset_loaded, &os->eth.rx_multicast,
1871                             &ns->eth.rx_multicast);
1872         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1873                             I40E_GLPRT_BPRCL(hw->port),
1874                             pf->offset_loaded, &os->eth.rx_broadcast,
1875                             &ns->eth.rx_broadcast);
1876         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1877                             pf->offset_loaded, &os->eth.rx_discards,
1878                             &ns->eth.rx_discards);
1879         /* GLPRT_REPC not supported */
1880         /* GLPRT_RMPC not supported */
1881         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1882                             pf->offset_loaded,
1883                             &os->eth.rx_unknown_protocol,
1884                             &ns->eth.rx_unknown_protocol);
1885         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1886                             I40E_GLPRT_GOTCL(hw->port),
1887                             pf->offset_loaded, &os->eth.tx_bytes,
1888                             &ns->eth.tx_bytes);
1889         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1890                             I40E_GLPRT_UPTCL(hw->port),
1891                             pf->offset_loaded, &os->eth.tx_unicast,
1892                             &ns->eth.tx_unicast);
1893         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1894                             I40E_GLPRT_MPTCL(hw->port),
1895                             pf->offset_loaded, &os->eth.tx_multicast,
1896                             &ns->eth.tx_multicast);
1897         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1898                             I40E_GLPRT_BPTCL(hw->port),
1899                             pf->offset_loaded, &os->eth.tx_broadcast,
1900                             &ns->eth.tx_broadcast);
1901         /* GLPRT_TEPC not supported */
1902
1903         /* additional port specific stats */
1904         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1905                             pf->offset_loaded, &os->tx_dropped_link_down,
1906                             &ns->tx_dropped_link_down);
1907         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1908                             pf->offset_loaded, &os->crc_errors,
1909                             &ns->crc_errors);
1910         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1911                             pf->offset_loaded, &os->illegal_bytes,
1912                             &ns->illegal_bytes);
1913         /* GLPRT_ERRBC not supported */
1914         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1915                             pf->offset_loaded, &os->mac_local_faults,
1916                             &ns->mac_local_faults);
1917         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1918                             pf->offset_loaded, &os->mac_remote_faults,
1919                             &ns->mac_remote_faults);
1920         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1921                             pf->offset_loaded, &os->rx_length_errors,
1922                             &ns->rx_length_errors);
1923         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1924                             pf->offset_loaded, &os->link_xon_rx,
1925                             &ns->link_xon_rx);
1926         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1927                             pf->offset_loaded, &os->link_xoff_rx,
1928                             &ns->link_xoff_rx);
1929         for (i = 0; i < 8; i++) {
1930                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1931                                     pf->offset_loaded,
1932                                     &os->priority_xon_rx[i],
1933                                     &ns->priority_xon_rx[i]);
1934                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1935                                     pf->offset_loaded,
1936                                     &os->priority_xoff_rx[i],
1937                                     &ns->priority_xoff_rx[i]);
1938         }
1939         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1940                             pf->offset_loaded, &os->link_xon_tx,
1941                             &ns->link_xon_tx);
1942         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1943                             pf->offset_loaded, &os->link_xoff_tx,
1944                             &ns->link_xoff_tx);
1945         for (i = 0; i < 8; i++) {
1946                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1947                                     pf->offset_loaded,
1948                                     &os->priority_xon_tx[i],
1949                                     &ns->priority_xon_tx[i]);
1950                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1951                                     pf->offset_loaded,
1952                                     &os->priority_xoff_tx[i],
1953                                     &ns->priority_xoff_tx[i]);
1954                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1955                                     pf->offset_loaded,
1956                                     &os->priority_xon_2_xoff[i],
1957                                     &ns->priority_xon_2_xoff[i]);
1958         }
1959         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1960                             I40E_GLPRT_PRC64L(hw->port),
1961                             pf->offset_loaded, &os->rx_size_64,
1962                             &ns->rx_size_64);
1963         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1964                             I40E_GLPRT_PRC127L(hw->port),
1965                             pf->offset_loaded, &os->rx_size_127,
1966                             &ns->rx_size_127);
1967         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1968                             I40E_GLPRT_PRC255L(hw->port),
1969                             pf->offset_loaded, &os->rx_size_255,
1970                             &ns->rx_size_255);
1971         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1972                             I40E_GLPRT_PRC511L(hw->port),
1973                             pf->offset_loaded, &os->rx_size_511,
1974                             &ns->rx_size_511);
1975         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1976                             I40E_GLPRT_PRC1023L(hw->port),
1977                             pf->offset_loaded, &os->rx_size_1023,
1978                             &ns->rx_size_1023);
1979         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1980                             I40E_GLPRT_PRC1522L(hw->port),
1981                             pf->offset_loaded, &os->rx_size_1522,
1982                             &ns->rx_size_1522);
1983         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1984                             I40E_GLPRT_PRC9522L(hw->port),
1985                             pf->offset_loaded, &os->rx_size_big,
1986                             &ns->rx_size_big);
1987         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1988                             pf->offset_loaded, &os->rx_undersize,
1989                             &ns->rx_undersize);
1990         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1991                             pf->offset_loaded, &os->rx_fragments,
1992                             &ns->rx_fragments);
1993         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1994                             pf->offset_loaded, &os->rx_oversize,
1995                             &ns->rx_oversize);
1996         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1997                             pf->offset_loaded, &os->rx_jabber,
1998                             &ns->rx_jabber);
1999         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2000                             I40E_GLPRT_PTC64L(hw->port),
2001                             pf->offset_loaded, &os->tx_size_64,
2002                             &ns->tx_size_64);
2003         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2004                             I40E_GLPRT_PTC127L(hw->port),
2005                             pf->offset_loaded, &os->tx_size_127,
2006                             &ns->tx_size_127);
2007         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2008                             I40E_GLPRT_PTC255L(hw->port),
2009                             pf->offset_loaded, &os->tx_size_255,
2010                             &ns->tx_size_255);
2011         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2012                             I40E_GLPRT_PTC511L(hw->port),
2013                             pf->offset_loaded, &os->tx_size_511,
2014                             &ns->tx_size_511);
2015         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2016                             I40E_GLPRT_PTC1023L(hw->port),
2017                             pf->offset_loaded, &os->tx_size_1023,
2018                             &ns->tx_size_1023);
2019         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2020                             I40E_GLPRT_PTC1522L(hw->port),
2021                             pf->offset_loaded, &os->tx_size_1522,
2022                             &ns->tx_size_1522);
2023         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2024                             I40E_GLPRT_PTC9522L(hw->port),
2025                             pf->offset_loaded, &os->tx_size_big,
2026                             &ns->tx_size_big);
2027         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2028                            pf->offset_loaded,
2029                            &os->fd_sb_match, &ns->fd_sb_match);
2030         /* GLPRT_MSPDC not supported */
2031         /* GLPRT_XEC not supported */
2032
2033         pf->offset_loaded = true;
2034
2035         if (pf->main_vsi)
2036                 i40e_update_vsi_stats(pf->main_vsi);
2037 }
2038
2039 /* Get all statistics of a port */
2040 static void
2041 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2042 {
2043         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2044         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2046         unsigned i;
2047
2048         /* call read registers - updates values, now write them to struct */
2049         i40e_read_stats_registers(pf, hw);
2050
2051         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2052                         pf->main_vsi->eth_stats.rx_multicast +
2053                         pf->main_vsi->eth_stats.rx_broadcast -
2054                         pf->main_vsi->eth_stats.rx_discards;
2055         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2056                         pf->main_vsi->eth_stats.tx_multicast +
2057                         pf->main_vsi->eth_stats.tx_broadcast;
2058         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
2059         stats->obytes   = pf->main_vsi->eth_stats.tx_bytes;
2060         stats->oerrors  = ns->eth.tx_errors +
2061                         pf->main_vsi->eth_stats.tx_errors;
2062         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2063
2064         /* Rx Errors */
2065         stats->imissed  = ns->eth.rx_discards +
2066                         pf->main_vsi->eth_stats.rx_discards;
2067         stats->ierrors  = ns->crc_errors +
2068                         ns->rx_length_errors + ns->rx_undersize +
2069                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
2070                         stats->imissed;
2071
2072         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2073         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2074         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2075         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2076         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2077         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2078         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2079                     ns->eth.rx_unknown_protocol);
2080         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2081         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2082         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2083         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2084         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2085         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2086
2087         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2088                     ns->tx_dropped_link_down);
2089         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2090         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2091                     ns->illegal_bytes);
2092         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2093         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2094                     ns->mac_local_faults);
2095         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2096                     ns->mac_remote_faults);
2097         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2098                     ns->rx_length_errors);
2099         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2100         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2101         for (i = 0; i < 8; i++) {
2102                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2103                                 i, ns->priority_xon_rx[i]);
2104                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2105                                 i, ns->priority_xoff_rx[i]);
2106         }
2107         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2108         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2109         for (i = 0; i < 8; i++) {
2110                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2111                                 i, ns->priority_xon_tx[i]);
2112                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2113                                 i, ns->priority_xoff_tx[i]);
2114                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2115                                 i, ns->priority_xon_2_xoff[i]);
2116         }
2117         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2118         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2119         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2120         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2121         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2122         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2123         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2124         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2125         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2126         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2127         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2128         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2129         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2130         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2131         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2132         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2133         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2134         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2135         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2136                         ns->mac_short_packet_dropped);
2137         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2138                     ns->checksum_error);
2139         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2140         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2141 }
2142
2143 /* Reset the statistics */
2144 static void
2145 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2146 {
2147         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2148         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149
2150         /* Mark PF and VSI stats to update the offset, aka "reset" */
2151         pf->offset_loaded = false;
2152         if (pf->main_vsi)
2153                 pf->main_vsi->offset_loaded = false;
2154
2155         /* read the stats, reading current register values into offset */
2156         i40e_read_stats_registers(pf, hw);
2157 }
2158
2159 static uint32_t
2160 i40e_xstats_calc_num(void)
2161 {
2162         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2163                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2164                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2165 }
2166
2167 static int
2168 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2169                     unsigned n)
2170 {
2171         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2172         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173         unsigned i, count, prio;
2174         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2175
2176         count = i40e_xstats_calc_num();
2177         if (n < count)
2178                 return count;
2179
2180         i40e_read_stats_registers(pf, hw);
2181
2182         if (xstats == NULL)
2183                 return 0;
2184
2185         count = 0;
2186
2187         /* Get stats from i40e_eth_stats struct */
2188         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2189                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2190                          "%s", rte_i40e_stats_strings[i].name);
2191                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2192                         rte_i40e_stats_strings[i].offset);
2193                 count++;
2194         }
2195
2196         /* Get individiual stats from i40e_hw_port struct */
2197         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2198                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2199                          "%s", rte_i40e_hw_port_strings[i].name);
2200                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2201                                 rte_i40e_hw_port_strings[i].offset);
2202                 count++;
2203         }
2204
2205         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2206                 for (prio = 0; prio < 8; prio++) {
2207                         snprintf(xstats[count].name,
2208                                  sizeof(xstats[count].name),
2209                                  "rx_priority%u_%s", prio,
2210                                  rte_i40e_rxq_prio_strings[i].name);
2211                         xstats[count].value =
2212                                 *(uint64_t *)(((char *)hw_stats) +
2213                                 rte_i40e_rxq_prio_strings[i].offset +
2214                                 (sizeof(uint64_t) * prio));
2215                         count++;
2216                 }
2217         }
2218
2219         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2220                 for (prio = 0; prio < 8; prio++) {
2221                         snprintf(xstats[count].name,
2222                                  sizeof(xstats[count].name),
2223                                  "tx_priority%u_%s", prio,
2224                                  rte_i40e_txq_prio_strings[i].name);
2225                         xstats[count].value =
2226                                 *(uint64_t *)(((char *)hw_stats) +
2227                                 rte_i40e_txq_prio_strings[i].offset +
2228                                 (sizeof(uint64_t) * prio));
2229                         count++;
2230                 }
2231         }
2232
2233         return count;
2234 }
2235
2236 static int
2237 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2238                                  __rte_unused uint16_t queue_id,
2239                                  __rte_unused uint8_t stat_idx,
2240                                  __rte_unused uint8_t is_rx)
2241 {
2242         PMD_INIT_FUNC_TRACE();
2243
2244         return -ENOSYS;
2245 }
2246
2247 static void
2248 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2249 {
2250         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2251         struct i40e_vsi *vsi = pf->main_vsi;
2252
2253         dev_info->max_rx_queues = vsi->nb_qps;
2254         dev_info->max_tx_queues = vsi->nb_qps;
2255         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2256         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2257         dev_info->max_mac_addrs = vsi->max_macaddrs;
2258         dev_info->max_vfs = dev->pci_dev->max_vfs;
2259         dev_info->rx_offload_capa =
2260                 DEV_RX_OFFLOAD_VLAN_STRIP |
2261                 DEV_RX_OFFLOAD_QINQ_STRIP |
2262                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2263                 DEV_RX_OFFLOAD_UDP_CKSUM |
2264                 DEV_RX_OFFLOAD_TCP_CKSUM;
2265         dev_info->tx_offload_capa =
2266                 DEV_TX_OFFLOAD_VLAN_INSERT |
2267                 DEV_TX_OFFLOAD_QINQ_INSERT |
2268                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2269                 DEV_TX_OFFLOAD_UDP_CKSUM |
2270                 DEV_TX_OFFLOAD_TCP_CKSUM |
2271                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2272                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2273                 DEV_TX_OFFLOAD_TCP_TSO;
2274         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2275                                                 sizeof(uint32_t);
2276         dev_info->reta_size = pf->hash_lut_size;
2277         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2278
2279         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2280                 .rx_thresh = {
2281                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2282                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2283                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2284                 },
2285                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2286                 .rx_drop_en = 0,
2287         };
2288
2289         dev_info->default_txconf = (struct rte_eth_txconf) {
2290                 .tx_thresh = {
2291                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2292                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2293                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2294                 },
2295                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2296                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2297                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2298                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2299         };
2300
2301         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2302                 .nb_max = I40E_MAX_RING_DESC,
2303                 .nb_min = I40E_MIN_RING_DESC,
2304                 .nb_align = I40E_ALIGN_RING_DESC,
2305         };
2306
2307         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2308                 .nb_max = I40E_MAX_RING_DESC,
2309                 .nb_min = I40E_MIN_RING_DESC,
2310                 .nb_align = I40E_ALIGN_RING_DESC,
2311         };
2312
2313         if (pf->flags & I40E_FLAG_VMDQ) {
2314                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2315                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2316                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2317                                                 pf->max_nb_vmdq_vsi;
2318                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2319                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2320                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2321         }
2322 }
2323
2324 static int
2325 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2326 {
2327         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2328         struct i40e_vsi *vsi = pf->main_vsi;
2329         PMD_INIT_FUNC_TRACE();
2330
2331         if (on)
2332                 return i40e_vsi_add_vlan(vsi, vlan_id);
2333         else
2334                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2335 }
2336
2337 static void
2338 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2339                    __rte_unused uint16_t tpid)
2340 {
2341         PMD_INIT_FUNC_TRACE();
2342 }
2343
2344 static void
2345 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2346 {
2347         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2348         struct i40e_vsi *vsi = pf->main_vsi;
2349
2350         if (mask & ETH_VLAN_STRIP_MASK) {
2351                 /* Enable or disable VLAN stripping */
2352                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2353                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2354                 else
2355                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2356         }
2357
2358         if (mask & ETH_VLAN_EXTEND_MASK) {
2359                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2360                         i40e_vsi_config_double_vlan(vsi, TRUE);
2361                 else
2362                         i40e_vsi_config_double_vlan(vsi, FALSE);
2363         }
2364 }
2365
2366 static void
2367 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2368                           __rte_unused uint16_t queue,
2369                           __rte_unused int on)
2370 {
2371         PMD_INIT_FUNC_TRACE();
2372 }
2373
2374 static int
2375 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2376 {
2377         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2378         struct i40e_vsi *vsi = pf->main_vsi;
2379         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2380         struct i40e_vsi_vlan_pvid_info info;
2381
2382         memset(&info, 0, sizeof(info));
2383         info.on = on;
2384         if (info.on)
2385                 info.config.pvid = pvid;
2386         else {
2387                 info.config.reject.tagged =
2388                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2389                 info.config.reject.untagged =
2390                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2391         }
2392
2393         return i40e_vsi_vlan_pvid_set(vsi, &info);
2394 }
2395
2396 static int
2397 i40e_dev_led_on(struct rte_eth_dev *dev)
2398 {
2399         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400         uint32_t mode = i40e_led_get(hw);
2401
2402         if (mode == 0)
2403                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2404
2405         return 0;
2406 }
2407
2408 static int
2409 i40e_dev_led_off(struct rte_eth_dev *dev)
2410 {
2411         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2412         uint32_t mode = i40e_led_get(hw);
2413
2414         if (mode != 0)
2415                 i40e_led_set(hw, 0, false);
2416
2417         return 0;
2418 }
2419
2420 static int
2421 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2422 {
2423         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2424         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2425
2426         fc_conf->pause_time = pf->fc_conf.pause_time;
2427         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2428         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2429
2430          /* Return current mode according to actual setting*/
2431         switch (hw->fc.current_mode) {
2432         case I40E_FC_FULL:
2433                 fc_conf->mode = RTE_FC_FULL;
2434                 break;
2435         case I40E_FC_TX_PAUSE:
2436                 fc_conf->mode = RTE_FC_TX_PAUSE;
2437                 break;
2438         case I40E_FC_RX_PAUSE:
2439                 fc_conf->mode = RTE_FC_RX_PAUSE;
2440                 break;
2441         case I40E_FC_NONE:
2442         default:
2443                 fc_conf->mode = RTE_FC_NONE;
2444         };
2445
2446         return 0;
2447 }
2448
2449 static int
2450 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2451 {
2452         uint32_t mflcn_reg, fctrl_reg, reg;
2453         uint32_t max_high_water;
2454         uint8_t i, aq_failure;
2455         int err;
2456         struct i40e_hw *hw;
2457         struct i40e_pf *pf;
2458         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2459                 [RTE_FC_NONE] = I40E_FC_NONE,
2460                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2461                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2462                 [RTE_FC_FULL] = I40E_FC_FULL
2463         };
2464
2465         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2466
2467         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2468         if ((fc_conf->high_water > max_high_water) ||
2469                         (fc_conf->high_water < fc_conf->low_water)) {
2470                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2471                         "High_water must <= %d.", max_high_water);
2472                 return -EINVAL;
2473         }
2474
2475         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2477         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2478
2479         pf->fc_conf.pause_time = fc_conf->pause_time;
2480         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2481         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2482
2483         PMD_INIT_FUNC_TRACE();
2484
2485         /* All the link flow control related enable/disable register
2486          * configuration is handle by the F/W
2487          */
2488         err = i40e_set_fc(hw, &aq_failure, true);
2489         if (err < 0)
2490                 return -ENOSYS;
2491
2492         if (i40e_is_40G_device(hw->device_id)) {
2493                 /* Configure flow control refresh threshold,
2494                  * the value for stat_tx_pause_refresh_timer[8]
2495                  * is used for global pause operation.
2496                  */
2497
2498                 I40E_WRITE_REG(hw,
2499                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2500                                pf->fc_conf.pause_time);
2501
2502                 /* configure the timer value included in transmitted pause
2503                  * frame,
2504                  * the value for stat_tx_pause_quanta[8] is used for global
2505                  * pause operation
2506                  */
2507                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2508                                pf->fc_conf.pause_time);
2509
2510                 fctrl_reg = I40E_READ_REG(hw,
2511                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2512
2513                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2514                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2515                 else
2516                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2517
2518                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2519                                fctrl_reg);
2520         } else {
2521                 /* Configure pause time (2 TCs per register) */
2522                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2523                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2524                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2525
2526                 /* Configure flow control refresh threshold value */
2527                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2528                                pf->fc_conf.pause_time / 2);
2529
2530                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2531
2532                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2533                  *depending on configuration
2534                  */
2535                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2536                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2537                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2538                 } else {
2539                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2540                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2541                 }
2542
2543                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2544         }
2545
2546         /* config the water marker both based on the packets and bytes */
2547         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2548                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2549                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2550         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2551                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2552                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2553         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2554                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2555                        << I40E_KILOSHIFT);
2556         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2557                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2558                        << I40E_KILOSHIFT);
2559
2560         I40E_WRITE_FLUSH(hw);
2561
2562         return 0;
2563 }
2564
2565 static int
2566 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2567                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2568 {
2569         PMD_INIT_FUNC_TRACE();
2570
2571         return -ENOSYS;
2572 }
2573
2574 /* Add a MAC address, and update filters */
2575 static void
2576 i40e_macaddr_add(struct rte_eth_dev *dev,
2577                  struct ether_addr *mac_addr,
2578                  __rte_unused uint32_t index,
2579                  uint32_t pool)
2580 {
2581         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2582         struct i40e_mac_filter_info mac_filter;
2583         struct i40e_vsi *vsi;
2584         int ret;
2585
2586         /* If VMDQ not enabled or configured, return */
2587         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2588                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2589                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2590                         pool);
2591                 return;
2592         }
2593
2594         if (pool > pf->nb_cfg_vmdq_vsi) {
2595                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2596                                 pool, pf->nb_cfg_vmdq_vsi);
2597                 return;
2598         }
2599
2600         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2601         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2602
2603         if (pool == 0)
2604                 vsi = pf->main_vsi;
2605         else
2606                 vsi = pf->vmdq[pool - 1].vsi;
2607
2608         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2609         if (ret != I40E_SUCCESS) {
2610                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2611                 return;
2612         }
2613 }
2614
2615 /* Remove a MAC address, and update filters */
2616 static void
2617 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2618 {
2619         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2620         struct i40e_vsi *vsi;
2621         struct rte_eth_dev_data *data = dev->data;
2622         struct ether_addr *macaddr;
2623         int ret;
2624         uint32_t i;
2625         uint64_t pool_sel;
2626
2627         macaddr = &(data->mac_addrs[index]);
2628
2629         pool_sel = dev->data->mac_pool_sel[index];
2630
2631         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2632                 if (pool_sel & (1ULL << i)) {
2633                         if (i == 0)
2634                                 vsi = pf->main_vsi;
2635                         else {
2636                                 /* No VMDQ pool enabled or configured */
2637                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2638                                         (i > pf->nb_cfg_vmdq_vsi)) {
2639                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2640                                                         "/configured");
2641                                         return;
2642                                 }
2643                                 vsi = pf->vmdq[i - 1].vsi;
2644                         }
2645                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2646
2647                         if (ret) {
2648                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2649                                 return;
2650                         }
2651                 }
2652         }
2653 }
2654
2655 /* Set perfect match or hash match of MAC and VLAN for a VF */
2656 static int
2657 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2658                  struct rte_eth_mac_filter *filter,
2659                  bool add)
2660 {
2661         struct i40e_hw *hw;
2662         struct i40e_mac_filter_info mac_filter;
2663         struct ether_addr old_mac;
2664         struct ether_addr *new_mac;
2665         struct i40e_pf_vf *vf = NULL;
2666         uint16_t vf_id;
2667         int ret;
2668
2669         if (pf == NULL) {
2670                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2671                 return -EINVAL;
2672         }
2673         hw = I40E_PF_TO_HW(pf);
2674
2675         if (filter == NULL) {
2676                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2677                 return -EINVAL;
2678         }
2679
2680         new_mac = &filter->mac_addr;
2681
2682         if (is_zero_ether_addr(new_mac)) {
2683                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2684                 return -EINVAL;
2685         }
2686
2687         vf_id = filter->dst_id;
2688
2689         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2690                 PMD_DRV_LOG(ERR, "Invalid argument.");
2691                 return -EINVAL;
2692         }
2693         vf = &pf->vfs[vf_id];
2694
2695         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2696                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2697                 return -EINVAL;
2698         }
2699
2700         if (add) {
2701                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2702                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2703                                 ETHER_ADDR_LEN);
2704                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2705                                  ETHER_ADDR_LEN);
2706
2707                 mac_filter.filter_type = filter->filter_type;
2708                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2709                 if (ret != I40E_SUCCESS) {
2710                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2711                         return -1;
2712                 }
2713                 ether_addr_copy(new_mac, &pf->dev_addr);
2714         } else {
2715                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2716                                 ETHER_ADDR_LEN);
2717                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2718                 if (ret != I40E_SUCCESS) {
2719                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2720                         return -1;
2721                 }
2722
2723                 /* Clear device address as it has been removed */
2724                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2725                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2726         }
2727
2728         return 0;
2729 }
2730
2731 /* MAC filter handle */
2732 static int
2733 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2734                 void *arg)
2735 {
2736         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2737         struct rte_eth_mac_filter *filter;
2738         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2739         int ret = I40E_NOT_SUPPORTED;
2740
2741         filter = (struct rte_eth_mac_filter *)(arg);
2742
2743         switch (filter_op) {
2744         case RTE_ETH_FILTER_NOP:
2745                 ret = I40E_SUCCESS;
2746                 break;
2747         case RTE_ETH_FILTER_ADD:
2748                 i40e_pf_disable_irq0(hw);
2749                 if (filter->is_vf)
2750                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2751                 i40e_pf_enable_irq0(hw);
2752                 break;
2753         case RTE_ETH_FILTER_DELETE:
2754                 i40e_pf_disable_irq0(hw);
2755                 if (filter->is_vf)
2756                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2757                 i40e_pf_enable_irq0(hw);
2758                 break;
2759         default:
2760                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2761                 ret = I40E_ERR_PARAM;
2762                 break;
2763         }
2764
2765         return ret;
2766 }
2767
2768 static int
2769 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2770 {
2771         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2772         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2773         int ret;
2774
2775         if (!lut)
2776                 return -EINVAL;
2777
2778         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2779                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2780                                           lut, lut_size);
2781                 if (ret) {
2782                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2783                         return ret;
2784                 }
2785         } else {
2786                 uint32_t *lut_dw = (uint32_t *)lut;
2787                 uint16_t i, lut_size_dw = lut_size / 4;
2788
2789                 for (i = 0; i < lut_size_dw; i++)
2790                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2791         }
2792
2793         return 0;
2794 }
2795
2796 static int
2797 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2798 {
2799         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2800         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2801         int ret;
2802
2803         if (!vsi || !lut)
2804                 return -EINVAL;
2805
2806         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2807                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2808                                           lut, lut_size);
2809                 if (ret) {
2810                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2811                         return ret;
2812                 }
2813         } else {
2814                 uint32_t *lut_dw = (uint32_t *)lut;
2815                 uint16_t i, lut_size_dw = lut_size / 4;
2816
2817                 for (i = 0; i < lut_size_dw; i++)
2818                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2819                 I40E_WRITE_FLUSH(hw);
2820         }
2821
2822         return 0;
2823 }
2824
2825 static int
2826 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2827                          struct rte_eth_rss_reta_entry64 *reta_conf,
2828                          uint16_t reta_size)
2829 {
2830         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2831         uint16_t i, lut_size = pf->hash_lut_size;
2832         uint16_t idx, shift;
2833         uint8_t *lut;
2834         int ret;
2835
2836         if (reta_size != lut_size ||
2837                 reta_size > ETH_RSS_RETA_SIZE_512) {
2838                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2839                         "(%d) doesn't match the number hardware can supported "
2840                                         "(%d)\n", reta_size, lut_size);
2841                 return -EINVAL;
2842         }
2843
2844         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2845         if (!lut) {
2846                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2847                 return -ENOMEM;
2848         }
2849         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2850         if (ret)
2851                 goto out;
2852         for (i = 0; i < reta_size; i++) {
2853                 idx = i / RTE_RETA_GROUP_SIZE;
2854                 shift = i % RTE_RETA_GROUP_SIZE;
2855                 if (reta_conf[idx].mask & (1ULL << shift))
2856                         lut[i] = reta_conf[idx].reta[shift];
2857         }
2858         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2859
2860 out:
2861         rte_free(lut);
2862
2863         return ret;
2864 }
2865
2866 static int
2867 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2868                         struct rte_eth_rss_reta_entry64 *reta_conf,
2869                         uint16_t reta_size)
2870 {
2871         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2872         uint16_t i, lut_size = pf->hash_lut_size;
2873         uint16_t idx, shift;
2874         uint8_t *lut;
2875         int ret;
2876
2877         if (reta_size != lut_size ||
2878                 reta_size > ETH_RSS_RETA_SIZE_512) {
2879                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2880                         "(%d) doesn't match the number hardware can supported "
2881                                         "(%d)\n", reta_size, lut_size);
2882                 return -EINVAL;
2883         }
2884
2885         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2886         if (!lut) {
2887                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2888                 return -ENOMEM;
2889         }
2890
2891         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2892         if (ret)
2893                 goto out;
2894         for (i = 0; i < reta_size; i++) {
2895                 idx = i / RTE_RETA_GROUP_SIZE;
2896                 shift = i % RTE_RETA_GROUP_SIZE;
2897                 if (reta_conf[idx].mask & (1ULL << shift))
2898                         reta_conf[idx].reta[shift] = lut[i];
2899         }
2900
2901 out:
2902         rte_free(lut);
2903
2904         return ret;
2905 }
2906
2907 /**
2908  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2909  * @hw:   pointer to the HW structure
2910  * @mem:  pointer to mem struct to fill out
2911  * @size: size of memory requested
2912  * @alignment: what to align the allocation to
2913  **/
2914 enum i40e_status_code
2915 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2916                         struct i40e_dma_mem *mem,
2917                         u64 size,
2918                         u32 alignment)
2919 {
2920         const struct rte_memzone *mz = NULL;
2921         char z_name[RTE_MEMZONE_NAMESIZE];
2922
2923         if (!mem)
2924                 return I40E_ERR_PARAM;
2925
2926         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
2927 #ifdef RTE_LIBRTE_XEN_DOM0
2928         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2929                                          alignment, RTE_PGSIZE_2M);
2930 #else
2931         mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2932                                          alignment);
2933 #endif
2934         if (!mz)
2935                 return I40E_ERR_NO_MEMORY;
2936
2937         mem->size = size;
2938         mem->va = mz->addr;
2939 #ifdef RTE_LIBRTE_XEN_DOM0
2940         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2941 #else
2942         mem->pa = mz->phys_addr;
2943 #endif
2944         mem->zone = (const void *)mz;
2945         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
2946                     "%"PRIu64, mz->name, mem->pa);
2947
2948         return I40E_SUCCESS;
2949 }
2950
2951 /**
2952  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2953  * @hw:   pointer to the HW structure
2954  * @mem:  ptr to mem struct to free
2955  **/
2956 enum i40e_status_code
2957 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2958                     struct i40e_dma_mem *mem)
2959 {
2960         if (!mem)
2961                 return I40E_ERR_PARAM;
2962
2963         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
2964                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
2965                     mem->pa);
2966         rte_memzone_free((const struct rte_memzone *)mem->zone);
2967         mem->zone = NULL;
2968         mem->va = NULL;
2969         mem->pa = (u64)0;
2970
2971         return I40E_SUCCESS;
2972 }
2973
2974 /**
2975  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2976  * @hw:   pointer to the HW structure
2977  * @mem:  pointer to mem struct to fill out
2978  * @size: size of memory requested
2979  **/
2980 enum i40e_status_code
2981 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2982                          struct i40e_virt_mem *mem,
2983                          u32 size)
2984 {
2985         if (!mem)
2986                 return I40E_ERR_PARAM;
2987
2988         mem->size = size;
2989         mem->va = rte_zmalloc("i40e", size, 0);
2990
2991         if (mem->va)
2992                 return I40E_SUCCESS;
2993         else
2994                 return I40E_ERR_NO_MEMORY;
2995 }
2996
2997 /**
2998  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2999  * @hw:   pointer to the HW structure
3000  * @mem:  pointer to mem struct to free
3001  **/
3002 enum i40e_status_code
3003 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3004                      struct i40e_virt_mem *mem)
3005 {
3006         if (!mem)
3007                 return I40E_ERR_PARAM;
3008
3009         rte_free(mem->va);
3010         mem->va = NULL;
3011
3012         return I40E_SUCCESS;
3013 }
3014
3015 void
3016 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3017 {
3018         rte_spinlock_init(&sp->spinlock);
3019 }
3020
3021 void
3022 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3023 {
3024         rte_spinlock_lock(&sp->spinlock);
3025 }
3026
3027 void
3028 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3029 {
3030         rte_spinlock_unlock(&sp->spinlock);
3031 }
3032
3033 void
3034 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3035 {
3036         return;
3037 }
3038
3039 /**
3040  * Get the hardware capabilities, which will be parsed
3041  * and saved into struct i40e_hw.
3042  */
3043 static int
3044 i40e_get_cap(struct i40e_hw *hw)
3045 {
3046         struct i40e_aqc_list_capabilities_element_resp *buf;
3047         uint16_t len, size = 0;
3048         int ret;
3049
3050         /* Calculate a huge enough buff for saving response data temporarily */
3051         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3052                                                 I40E_MAX_CAP_ELE_NUM;
3053         buf = rte_zmalloc("i40e", len, 0);
3054         if (!buf) {
3055                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3056                 return I40E_ERR_NO_MEMORY;
3057         }
3058
3059         /* Get, parse the capabilities and save it to hw */
3060         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3061                         i40e_aqc_opc_list_func_capabilities, NULL);
3062         if (ret != I40E_SUCCESS)
3063                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3064
3065         /* Free the temporary buffer after being used */
3066         rte_free(buf);
3067
3068         return ret;
3069 }
3070
3071 static int
3072 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3073 {
3074         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3075         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3076         uint16_t qp_count = 0, vsi_count = 0;
3077
3078         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3079                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3080                 return -EINVAL;
3081         }
3082         /* Add the parameter init for LFC */
3083         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3084         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3085         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3086
3087         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3088         pf->max_num_vsi = hw->func_caps.num_vsis;
3089         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3090         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3091         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3092
3093         /* FDir queue/VSI allocation */
3094         pf->fdir_qp_offset = 0;
3095         if (hw->func_caps.fd) {
3096                 pf->flags |= I40E_FLAG_FDIR;
3097                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3098         } else {
3099                 pf->fdir_nb_qps = 0;
3100         }
3101         qp_count += pf->fdir_nb_qps;
3102         vsi_count += 1;
3103
3104         /* LAN queue/VSI allocation */
3105         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3106         if (!hw->func_caps.rss) {
3107                 pf->lan_nb_qps = 1;
3108         } else {
3109                 pf->flags |= I40E_FLAG_RSS;
3110                 if (hw->mac.type == I40E_MAC_X722)
3111                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3112                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3113         }
3114         qp_count += pf->lan_nb_qps;
3115         vsi_count += 1;
3116
3117         /* VF queue/VSI allocation */
3118         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3119         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3120                 pf->flags |= I40E_FLAG_SRIOV;
3121                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3122                 pf->vf_num = dev->pci_dev->max_vfs;
3123                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3124                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3125                             pf->vf_nb_qps * pf->vf_num);
3126         } else {
3127                 pf->vf_nb_qps = 0;
3128                 pf->vf_num = 0;
3129         }
3130         qp_count += pf->vf_nb_qps * pf->vf_num;
3131         vsi_count += pf->vf_num;
3132
3133         /* VMDq queue/VSI allocation */
3134         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3135         pf->vmdq_nb_qps = 0;
3136         pf->max_nb_vmdq_vsi = 0;
3137         if (hw->func_caps.vmdq) {
3138                 if (qp_count < hw->func_caps.num_tx_qp &&
3139                         vsi_count < hw->func_caps.num_vsis) {
3140                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3141                                 qp_count) / pf->vmdq_nb_qp_max;
3142
3143                         /* Limit the maximum number of VMDq vsi to the maximum
3144                          * ethdev can support
3145                          */
3146                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3147                                 hw->func_caps.num_vsis - vsi_count);
3148                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3149                                 ETH_64_POOLS);
3150                         if (pf->max_nb_vmdq_vsi) {
3151                                 pf->flags |= I40E_FLAG_VMDQ;
3152                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3153                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3154                                             "per VMDQ VSI, in total %u queues",
3155                                             pf->max_nb_vmdq_vsi,
3156                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3157                                             pf->max_nb_vmdq_vsi);
3158                         } else {
3159                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3160                                             "VMDq");
3161                         }
3162                 } else {
3163                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3164                 }
3165         }
3166         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3167         vsi_count += pf->max_nb_vmdq_vsi;
3168
3169         if (hw->func_caps.dcb)
3170                 pf->flags |= I40E_FLAG_DCB;
3171
3172         if (qp_count > hw->func_caps.num_tx_qp) {
3173                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3174                             "the hardware maximum %u", qp_count,
3175                             hw->func_caps.num_tx_qp);
3176                 return -EINVAL;
3177         }
3178         if (vsi_count > hw->func_caps.num_vsis) {
3179                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3180                             "the hardware maximum %u", vsi_count,
3181                             hw->func_caps.num_vsis);
3182                 return -EINVAL;
3183         }
3184
3185         return 0;
3186 }
3187
3188 static int
3189 i40e_pf_get_switch_config(struct i40e_pf *pf)
3190 {
3191         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3192         struct i40e_aqc_get_switch_config_resp *switch_config;
3193         struct i40e_aqc_switch_config_element_resp *element;
3194         uint16_t start_seid = 0, num_reported;
3195         int ret;
3196
3197         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3198                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3199         if (!switch_config) {
3200                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3201                 return -ENOMEM;
3202         }
3203
3204         /* Get the switch configurations */
3205         ret = i40e_aq_get_switch_config(hw, switch_config,
3206                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3207         if (ret != I40E_SUCCESS) {
3208                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3209                 goto fail;
3210         }
3211         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3212         if (num_reported != 1) { /* The number should be 1 */
3213                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3214                 goto fail;
3215         }
3216
3217         /* Parse the switch configuration elements */
3218         element = &(switch_config->element[0]);
3219         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3220                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3221                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3222         } else
3223                 PMD_DRV_LOG(INFO, "Unknown element type");
3224
3225 fail:
3226         rte_free(switch_config);
3227
3228         return ret;
3229 }
3230
3231 static int
3232 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3233                         uint32_t num)
3234 {
3235         struct pool_entry *entry;
3236
3237         if (pool == NULL || num == 0)
3238                 return -EINVAL;
3239
3240         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3241         if (entry == NULL) {
3242                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3243                 return -ENOMEM;
3244         }
3245
3246         /* queue heap initialize */
3247         pool->num_free = num;
3248         pool->num_alloc = 0;
3249         pool->base = base;
3250         LIST_INIT(&pool->alloc_list);
3251         LIST_INIT(&pool->free_list);
3252
3253         /* Initialize element  */
3254         entry->base = 0;
3255         entry->len = num;
3256
3257         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3258         return 0;
3259 }
3260
3261 static void
3262 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3263 {
3264         struct pool_entry *entry;
3265
3266         if (pool == NULL)
3267                 return;
3268
3269         LIST_FOREACH(entry, &pool->alloc_list, next) {
3270                 LIST_REMOVE(entry, next);
3271                 rte_free(entry);
3272         }
3273
3274         LIST_FOREACH(entry, &pool->free_list, next) {
3275                 LIST_REMOVE(entry, next);
3276                 rte_free(entry);
3277         }
3278
3279         pool->num_free = 0;
3280         pool->num_alloc = 0;
3281         pool->base = 0;
3282         LIST_INIT(&pool->alloc_list);
3283         LIST_INIT(&pool->free_list);
3284 }
3285
3286 static int
3287 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3288                        uint32_t base)
3289 {
3290         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3291         uint32_t pool_offset;
3292         int insert;
3293
3294         if (pool == NULL) {
3295                 PMD_DRV_LOG(ERR, "Invalid parameter");
3296                 return -EINVAL;
3297         }
3298
3299         pool_offset = base - pool->base;
3300         /* Lookup in alloc list */
3301         LIST_FOREACH(entry, &pool->alloc_list, next) {
3302                 if (entry->base == pool_offset) {
3303                         valid_entry = entry;
3304                         LIST_REMOVE(entry, next);
3305                         break;
3306                 }
3307         }
3308
3309         /* Not find, return */
3310         if (valid_entry == NULL) {
3311                 PMD_DRV_LOG(ERR, "Failed to find entry");
3312                 return -EINVAL;
3313         }
3314
3315         /**
3316          * Found it, move it to free list  and try to merge.
3317          * In order to make merge easier, always sort it by qbase.
3318          * Find adjacent prev and last entries.
3319          */
3320         prev = next = NULL;
3321         LIST_FOREACH(entry, &pool->free_list, next) {
3322                 if (entry->base > valid_entry->base) {
3323                         next = entry;
3324                         break;
3325                 }
3326                 prev = entry;
3327         }
3328
3329         insert = 0;
3330         /* Try to merge with next one*/
3331         if (next != NULL) {
3332                 /* Merge with next one */
3333                 if (valid_entry->base + valid_entry->len == next->base) {
3334                         next->base = valid_entry->base;
3335                         next->len += valid_entry->len;
3336                         rte_free(valid_entry);
3337                         valid_entry = next;
3338                         insert = 1;
3339                 }
3340         }
3341
3342         if (prev != NULL) {
3343                 /* Merge with previous one */
3344                 if (prev->base + prev->len == valid_entry->base) {
3345                         prev->len += valid_entry->len;
3346                         /* If it merge with next one, remove next node */
3347                         if (insert == 1) {
3348                                 LIST_REMOVE(valid_entry, next);
3349                                 rte_free(valid_entry);
3350                         } else {
3351                                 rte_free(valid_entry);
3352                                 insert = 1;
3353                         }
3354                 }
3355         }
3356
3357         /* Not find any entry to merge, insert */
3358         if (insert == 0) {
3359                 if (prev != NULL)
3360                         LIST_INSERT_AFTER(prev, valid_entry, next);
3361                 else if (next != NULL)
3362                         LIST_INSERT_BEFORE(next, valid_entry, next);
3363                 else /* It's empty list, insert to head */
3364                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3365         }
3366
3367         pool->num_free += valid_entry->len;
3368         pool->num_alloc -= valid_entry->len;
3369
3370         return 0;
3371 }
3372
3373 static int
3374 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3375                        uint16_t num)
3376 {
3377         struct pool_entry *entry, *valid_entry;
3378
3379         if (pool == NULL || num == 0) {
3380                 PMD_DRV_LOG(ERR, "Invalid parameter");
3381                 return -EINVAL;
3382         }
3383
3384         if (pool->num_free < num) {
3385                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3386                             num, pool->num_free);
3387                 return -ENOMEM;
3388         }
3389
3390         valid_entry = NULL;
3391         /* Lookup  in free list and find most fit one */
3392         LIST_FOREACH(entry, &pool->free_list, next) {
3393                 if (entry->len >= num) {
3394                         /* Find best one */
3395                         if (entry->len == num) {
3396                                 valid_entry = entry;
3397                                 break;
3398                         }
3399                         if (valid_entry == NULL || valid_entry->len > entry->len)
3400                                 valid_entry = entry;
3401                 }
3402         }
3403
3404         /* Not find one to satisfy the request, return */
3405         if (valid_entry == NULL) {
3406                 PMD_DRV_LOG(ERR, "No valid entry found");
3407                 return -ENOMEM;
3408         }
3409         /**
3410          * The entry have equal queue number as requested,
3411          * remove it from alloc_list.
3412          */
3413         if (valid_entry->len == num) {
3414                 LIST_REMOVE(valid_entry, next);
3415         } else {
3416                 /**
3417                  * The entry have more numbers than requested,
3418                  * create a new entry for alloc_list and minus its
3419                  * queue base and number in free_list.
3420                  */
3421                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3422                 if (entry == NULL) {
3423                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3424                                     "resource pool");
3425                         return -ENOMEM;
3426                 }
3427                 entry->base = valid_entry->base;
3428                 entry->len = num;
3429                 valid_entry->base += num;
3430                 valid_entry->len -= num;
3431                 valid_entry = entry;
3432         }
3433
3434         /* Insert it into alloc list, not sorted */
3435         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3436
3437         pool->num_free -= valid_entry->len;
3438         pool->num_alloc += valid_entry->len;
3439
3440         return (valid_entry->base + pool->base);
3441 }
3442
3443 /**
3444  * bitmap_is_subset - Check whether src2 is subset of src1
3445  **/
3446 static inline int
3447 bitmap_is_subset(uint8_t src1, uint8_t src2)
3448 {
3449         return !((src1 ^ src2) & src2);
3450 }
3451
3452 static enum i40e_status_code
3453 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3454 {
3455         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3456
3457         /* If DCB is not supported, only default TC is supported */
3458         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3459                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3460                 return I40E_NOT_SUPPORTED;
3461         }
3462
3463         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3464                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3465                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3466                             enabled_tcmap);
3467                 return I40E_NOT_SUPPORTED;
3468         }
3469         return I40E_SUCCESS;
3470 }
3471
3472 int
3473 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3474                                 struct i40e_vsi_vlan_pvid_info *info)
3475 {
3476         struct i40e_hw *hw;
3477         struct i40e_vsi_context ctxt;
3478         uint8_t vlan_flags = 0;
3479         int ret;
3480
3481         if (vsi == NULL || info == NULL) {
3482                 PMD_DRV_LOG(ERR, "invalid parameters");
3483                 return I40E_ERR_PARAM;
3484         }
3485
3486         if (info->on) {
3487                 vsi->info.pvid = info->config.pvid;
3488                 /**
3489                  * If insert pvid is enabled, only tagged pkts are
3490                  * allowed to be sent out.
3491                  */
3492                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3493                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3494         } else {
3495                 vsi->info.pvid = 0;
3496                 if (info->config.reject.tagged == 0)
3497                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3498
3499                 if (info->config.reject.untagged == 0)
3500                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3501         }
3502         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3503                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3504         vsi->info.port_vlan_flags |= vlan_flags;
3505         vsi->info.valid_sections =
3506                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3507         memset(&ctxt, 0, sizeof(ctxt));
3508         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3509         ctxt.seid = vsi->seid;
3510
3511         hw = I40E_VSI_TO_HW(vsi);
3512         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3513         if (ret != I40E_SUCCESS)
3514                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3515
3516         return ret;
3517 }
3518
3519 static int
3520 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3521 {
3522         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3523         int i, ret;
3524         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3525
3526         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3527         if (ret != I40E_SUCCESS)
3528                 return ret;
3529
3530         if (!vsi->seid) {
3531                 PMD_DRV_LOG(ERR, "seid not valid");
3532                 return -EINVAL;
3533         }
3534
3535         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3536         tc_bw_data.tc_valid_bits = enabled_tcmap;
3537         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3538                 tc_bw_data.tc_bw_credits[i] =
3539                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3540
3541         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3542         if (ret != I40E_SUCCESS) {
3543                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3544                 return ret;
3545         }
3546
3547         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3548                                         sizeof(vsi->info.qs_handle));
3549         return I40E_SUCCESS;
3550 }
3551
3552 static enum i40e_status_code
3553 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3554                                  struct i40e_aqc_vsi_properties_data *info,
3555                                  uint8_t enabled_tcmap)
3556 {
3557         enum i40e_status_code ret;
3558         int i, total_tc = 0;
3559         uint16_t qpnum_per_tc, bsf, qp_idx;
3560
3561         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3562         if (ret != I40E_SUCCESS)
3563                 return ret;
3564
3565         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3566                 if (enabled_tcmap & (1 << i))
3567                         total_tc++;
3568         vsi->enabled_tc = enabled_tcmap;
3569
3570         /* Number of queues per enabled TC */
3571         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3572         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3573         bsf = rte_bsf32(qpnum_per_tc);
3574
3575         /* Adjust the queue number to actual queues that can be applied */
3576         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3577                 vsi->nb_qps = qpnum_per_tc * total_tc;
3578
3579         /**
3580          * Configure TC and queue mapping parameters, for enabled TC,
3581          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3582          * default queue will serve it.
3583          */
3584         qp_idx = 0;
3585         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3586                 if (vsi->enabled_tc & (1 << i)) {
3587                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3588                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3589                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3590                         qp_idx += qpnum_per_tc;
3591                 } else
3592                         info->tc_mapping[i] = 0;
3593         }
3594
3595         /* Associate queue number with VSI */
3596         if (vsi->type == I40E_VSI_SRIOV) {
3597                 info->mapping_flags |=
3598                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3599                 for (i = 0; i < vsi->nb_qps; i++)
3600                         info->queue_mapping[i] =
3601                                 rte_cpu_to_le_16(vsi->base_queue + i);
3602         } else {
3603                 info->mapping_flags |=
3604                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3605                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3606         }
3607         info->valid_sections |=
3608                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3609
3610         return I40E_SUCCESS;
3611 }
3612
3613 static int
3614 i40e_veb_release(struct i40e_veb *veb)
3615 {
3616         struct i40e_vsi *vsi;
3617         struct i40e_hw *hw;
3618
3619         if (veb == NULL || veb->associate_vsi == NULL)
3620                 return -EINVAL;
3621
3622         if (!TAILQ_EMPTY(&veb->head)) {
3623                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3624                 return -EACCES;
3625         }
3626
3627         vsi = veb->associate_vsi;
3628         hw = I40E_VSI_TO_HW(vsi);
3629
3630         vsi->uplink_seid = veb->uplink_seid;
3631         i40e_aq_delete_element(hw, veb->seid, NULL);
3632         rte_free(veb);
3633         vsi->veb = NULL;
3634         return I40E_SUCCESS;
3635 }
3636
3637 /* Setup a veb */
3638 static struct i40e_veb *
3639 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3640 {
3641         struct i40e_veb *veb;
3642         int ret;
3643         struct i40e_hw *hw;
3644
3645         if (NULL == pf || vsi == NULL) {
3646                 PMD_DRV_LOG(ERR, "veb setup failed, "
3647                             "associated VSI shouldn't null");
3648                 return NULL;
3649         }
3650         hw = I40E_PF_TO_HW(pf);
3651
3652         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3653         if (!veb) {
3654                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3655                 goto fail;
3656         }
3657
3658         veb->associate_vsi = vsi;
3659         TAILQ_INIT(&veb->head);
3660         veb->uplink_seid = vsi->uplink_seid;
3661
3662         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3663                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3664
3665         if (ret != I40E_SUCCESS) {
3666                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3667                             hw->aq.asq_last_status);
3668                 goto fail;
3669         }
3670
3671         /* get statistics index */
3672         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3673                                 &veb->stats_idx, NULL, NULL, NULL);
3674         if (ret != I40E_SUCCESS) {
3675                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3676                             hw->aq.asq_last_status);
3677                 goto fail;
3678         }
3679
3680         /* Get VEB bandwidth, to be implemented */
3681         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3682         vsi->uplink_seid = veb->seid;
3683
3684         return veb;
3685 fail:
3686         rte_free(veb);
3687         return NULL;
3688 }
3689
3690 int
3691 i40e_vsi_release(struct i40e_vsi *vsi)
3692 {
3693         struct i40e_pf *pf;
3694         struct i40e_hw *hw;
3695         struct i40e_vsi_list *vsi_list;
3696         int ret;
3697         struct i40e_mac_filter *f;
3698
3699         if (!vsi)
3700                 return I40E_SUCCESS;
3701
3702         pf = I40E_VSI_TO_PF(vsi);
3703         hw = I40E_VSI_TO_HW(vsi);
3704
3705         /* VSI has child to attach, release child first */
3706         if (vsi->veb) {
3707                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3708                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3709                                 return -1;
3710                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3711                 }
3712                 i40e_veb_release(vsi->veb);
3713         }
3714
3715         /* Remove all macvlan filters of the VSI */
3716         i40e_vsi_remove_all_macvlan_filter(vsi);
3717         TAILQ_FOREACH(f, &vsi->mac_list, next)
3718                 rte_free(f);
3719
3720         if (vsi->type != I40E_VSI_MAIN) {
3721                 /* Remove vsi from parent's sibling list */
3722                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3723                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3724                         return I40E_ERR_PARAM;
3725                 }
3726                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3727                                 &vsi->sib_vsi_list, list);
3728
3729                 /* Remove all switch element of the VSI */
3730                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3731                 if (ret != I40E_SUCCESS)
3732                         PMD_DRV_LOG(ERR, "Failed to delete element");
3733         }
3734         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3735
3736         if (vsi->type != I40E_VSI_SRIOV)
3737                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3738         rte_free(vsi);
3739
3740         return I40E_SUCCESS;
3741 }
3742
3743 static int
3744 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3745 {
3746         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3747         struct i40e_aqc_remove_macvlan_element_data def_filter;
3748         struct i40e_mac_filter_info filter;
3749         int ret;
3750
3751         if (vsi->type != I40E_VSI_MAIN)
3752                 return I40E_ERR_CONFIG;
3753         memset(&def_filter, 0, sizeof(def_filter));
3754         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3755                                         ETH_ADDR_LEN);
3756         def_filter.vlan_tag = 0;
3757         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3758                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3759         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3760         if (ret != I40E_SUCCESS) {
3761                 struct i40e_mac_filter *f;
3762                 struct ether_addr *mac;
3763
3764                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3765                             "macvlan filter");
3766                 /* It needs to add the permanent mac into mac list */
3767                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3768                 if (f == NULL) {
3769                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3770                         return I40E_ERR_NO_MEMORY;
3771                 }
3772                 mac = &f->mac_info.mac_addr;
3773                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3774                                 ETH_ADDR_LEN);
3775                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3776                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3777                 vsi->mac_num++;
3778
3779                 return ret;
3780         }
3781         (void)rte_memcpy(&filter.mac_addr,
3782                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3783         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3784         return i40e_vsi_add_mac(vsi, &filter);
3785 }
3786
3787 static int
3788 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3789 {
3790         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3791         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3792         struct i40e_hw *hw = &vsi->adapter->hw;
3793         i40e_status ret;
3794         int i;
3795
3796         memset(&bw_config, 0, sizeof(bw_config));
3797         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3798         if (ret != I40E_SUCCESS) {
3799                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3800                             hw->aq.asq_last_status);
3801                 return ret;
3802         }
3803
3804         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3805         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3806                                         &ets_sla_config, NULL);
3807         if (ret != I40E_SUCCESS) {
3808                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3809                             "configuration %u", hw->aq.asq_last_status);
3810                 return ret;
3811         }
3812
3813         /* Not store the info yet, just print out */
3814         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3815         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3816         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3817                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3818                             ets_sla_config.share_credits[i]);
3819                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3820                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3821                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3822                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3823                             (i * 4));
3824         }
3825
3826         return 0;
3827 }
3828
3829 /* Setup a VSI */
3830 struct i40e_vsi *
3831 i40e_vsi_setup(struct i40e_pf *pf,
3832                enum i40e_vsi_type type,
3833                struct i40e_vsi *uplink_vsi,
3834                uint16_t user_param)
3835 {
3836         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3837         struct i40e_vsi *vsi;
3838         struct i40e_mac_filter_info filter;
3839         int ret;
3840         struct i40e_vsi_context ctxt;
3841         struct ether_addr broadcast =
3842                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3843
3844         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3845                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3846                             "VSI link shouldn't be NULL");
3847                 return NULL;
3848         }
3849
3850         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3851                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3852                             "uplink VSI should be NULL");
3853                 return NULL;
3854         }
3855
3856         /* If uplink vsi didn't setup VEB, create one first */
3857         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3858                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3859
3860                 if (NULL == uplink_vsi->veb) {
3861                         PMD_DRV_LOG(ERR, "VEB setup failed");
3862                         return NULL;
3863                 }
3864         }
3865
3866         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3867         if (!vsi) {
3868                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3869                 return NULL;
3870         }
3871         TAILQ_INIT(&vsi->mac_list);
3872         vsi->type = type;
3873         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3874         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3875         vsi->parent_vsi = uplink_vsi;
3876         vsi->user_param = user_param;
3877         /* Allocate queues */
3878         switch (vsi->type) {
3879         case I40E_VSI_MAIN  :
3880                 vsi->nb_qps = pf->lan_nb_qps;
3881                 break;
3882         case I40E_VSI_SRIOV :
3883                 vsi->nb_qps = pf->vf_nb_qps;
3884                 break;
3885         case I40E_VSI_VMDQ2:
3886                 vsi->nb_qps = pf->vmdq_nb_qps;
3887                 break;
3888         case I40E_VSI_FDIR:
3889                 vsi->nb_qps = pf->fdir_nb_qps;
3890                 break;
3891         default:
3892                 goto fail_mem;
3893         }
3894         /*
3895          * The filter status descriptor is reported in rx queue 0,
3896          * while the tx queue for fdir filter programming has no
3897          * such constraints, can be non-zero queues.
3898          * To simplify it, choose FDIR vsi use queue 0 pair.
3899          * To make sure it will use queue 0 pair, queue allocation
3900          * need be done before this function is called
3901          */
3902         if (type != I40E_VSI_FDIR) {
3903                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3904                         if (ret < 0) {
3905                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3906                                                 vsi->seid, ret);
3907                                 goto fail_mem;
3908                         }
3909                         vsi->base_queue = ret;
3910         } else
3911                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3912
3913         /* VF has MSIX interrupt in VF range, don't allocate here */
3914         if (type == I40E_VSI_MAIN) {
3915                 ret = i40e_res_pool_alloc(&pf->msix_pool,
3916                                           RTE_MIN(vsi->nb_qps,
3917                                                   RTE_MAX_RXTX_INTR_VEC_ID));
3918                 if (ret < 0) {
3919                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
3920                                     vsi->seid, ret);
3921                         goto fail_queue_alloc;
3922                 }
3923                 vsi->msix_intr = ret;
3924                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
3925         } else if (type != I40E_VSI_SRIOV) {
3926                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3927                 if (ret < 0) {
3928                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3929                         goto fail_queue_alloc;
3930                 }
3931                 vsi->msix_intr = ret;
3932                 vsi->nb_msix = 1;
3933         } else {
3934                 vsi->msix_intr = 0;
3935                 vsi->nb_msix = 0;
3936         }
3937
3938         /* Add VSI */
3939         if (type == I40E_VSI_MAIN) {
3940                 /* For main VSI, no need to add since it's default one */
3941                 vsi->uplink_seid = pf->mac_seid;
3942                 vsi->seid = pf->main_vsi_seid;
3943                 /* Bind queues with specific MSIX interrupt */
3944                 /**
3945                  * Needs 2 interrupt at least, one for misc cause which will
3946                  * enabled from OS side, Another for queues binding the
3947                  * interrupt from device side only.
3948                  */
3949
3950                 /* Get default VSI parameters from hardware */
3951                 memset(&ctxt, 0, sizeof(ctxt));
3952                 ctxt.seid = vsi->seid;
3953                 ctxt.pf_num = hw->pf_id;
3954                 ctxt.uplink_seid = vsi->uplink_seid;
3955                 ctxt.vf_num = 0;
3956                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3957                 if (ret != I40E_SUCCESS) {
3958                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3959                         goto fail_msix_alloc;
3960                 }
3961                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3962                         sizeof(struct i40e_aqc_vsi_properties_data));
3963                 vsi->vsi_id = ctxt.vsi_number;
3964                 vsi->info.valid_sections = 0;
3965
3966                 /* Configure tc, enabled TC0 only */
3967                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3968                         I40E_SUCCESS) {
3969                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3970                         goto fail_msix_alloc;
3971                 }
3972
3973                 /* TC, queue mapping */
3974                 memset(&ctxt, 0, sizeof(ctxt));
3975                 vsi->info.valid_sections |=
3976                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3977                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3978                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3979                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3980                         sizeof(struct i40e_aqc_vsi_properties_data));
3981                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3982                                                 I40E_DEFAULT_TCMAP);
3983                 if (ret != I40E_SUCCESS) {
3984                         PMD_DRV_LOG(ERR, "Failed to configure "
3985                                     "TC queue mapping");
3986                         goto fail_msix_alloc;
3987                 }
3988                 ctxt.seid = vsi->seid;
3989                 ctxt.pf_num = hw->pf_id;
3990                 ctxt.uplink_seid = vsi->uplink_seid;
3991                 ctxt.vf_num = 0;
3992
3993                 /* Update VSI parameters */
3994                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3995                 if (ret != I40E_SUCCESS) {
3996                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3997                         goto fail_msix_alloc;
3998                 }
3999
4000                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4001                                                 sizeof(vsi->info.tc_mapping));
4002                 (void)rte_memcpy(&vsi->info.queue_mapping,
4003                                 &ctxt.info.queue_mapping,
4004                         sizeof(vsi->info.queue_mapping));
4005                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4006                 vsi->info.valid_sections = 0;
4007
4008                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4009                                 ETH_ADDR_LEN);
4010
4011                 /**
4012                  * Updating default filter settings are necessary to prevent
4013                  * reception of tagged packets.
4014                  * Some old firmware configurations load a default macvlan
4015                  * filter which accepts both tagged and untagged packets.
4016                  * The updating is to use a normal filter instead if needed.
4017                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4018                  * The firmware with correct configurations load the default
4019                  * macvlan filter which is expected and cannot be removed.
4020                  */
4021                 i40e_update_default_filter_setting(vsi);
4022                 i40e_config_qinq(hw, vsi);
4023         } else if (type == I40E_VSI_SRIOV) {
4024                 memset(&ctxt, 0, sizeof(ctxt));
4025                 /**
4026                  * For other VSI, the uplink_seid equals to uplink VSI's
4027                  * uplink_seid since they share same VEB
4028                  */
4029                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4030                 ctxt.pf_num = hw->pf_id;
4031                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4032                 ctxt.uplink_seid = vsi->uplink_seid;
4033                 ctxt.connection_type = 0x1;
4034                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4035
4036                 /**
4037                  * Do not configure switch ID to enable VEB switch by
4038                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
4039                  * if the source mac address of packet sent from VF is not
4040                  * listed in the VEB's mac table, the VEB will switch the
4041                  * packet back to the VF. Need to enable it when HW issue
4042                  * is fixed.
4043                  */
4044
4045                 /* Configure port/vlan */
4046                 ctxt.info.valid_sections |=
4047                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4048                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4049                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4050                                                 I40E_DEFAULT_TCMAP);
4051                 if (ret != I40E_SUCCESS) {
4052                         PMD_DRV_LOG(ERR, "Failed to configure "
4053                                     "TC queue mapping");
4054                         goto fail_msix_alloc;
4055                 }
4056                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4057                 ctxt.info.valid_sections |=
4058                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4059                 /**
4060                  * Since VSI is not created yet, only configure parameter,
4061                  * will add vsi below.
4062                  */
4063
4064                 i40e_config_qinq(hw, vsi);
4065         } else if (type == I40E_VSI_VMDQ2) {
4066                 memset(&ctxt, 0, sizeof(ctxt));
4067                 /*
4068                  * For other VSI, the uplink_seid equals to uplink VSI's
4069                  * uplink_seid since they share same VEB
4070                  */
4071                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4072                 ctxt.pf_num = hw->pf_id;
4073                 ctxt.vf_num = 0;
4074                 ctxt.uplink_seid = vsi->uplink_seid;
4075                 ctxt.connection_type = 0x1;
4076                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4077
4078                 ctxt.info.valid_sections |=
4079                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4080                 /* user_param carries flag to enable loop back */
4081                 if (user_param) {
4082                         ctxt.info.switch_id =
4083                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4084                         ctxt.info.switch_id |=
4085                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4086                 }
4087
4088                 /* Configure port/vlan */
4089                 ctxt.info.valid_sections |=
4090                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4091                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4092                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4093                                                 I40E_DEFAULT_TCMAP);
4094                 if (ret != I40E_SUCCESS) {
4095                         PMD_DRV_LOG(ERR, "Failed to configure "
4096                                         "TC queue mapping");
4097                         goto fail_msix_alloc;
4098                 }
4099                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4100                 ctxt.info.valid_sections |=
4101                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4102         } else if (type == I40E_VSI_FDIR) {
4103                 memset(&ctxt, 0, sizeof(ctxt));
4104                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4105                 ctxt.pf_num = hw->pf_id;
4106                 ctxt.vf_num = 0;
4107                 ctxt.uplink_seid = vsi->uplink_seid;
4108                 ctxt.connection_type = 0x1;     /* regular data port */
4109                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4110                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4111                                                 I40E_DEFAULT_TCMAP);
4112                 if (ret != I40E_SUCCESS) {
4113                         PMD_DRV_LOG(ERR, "Failed to configure "
4114                                         "TC queue mapping.");
4115                         goto fail_msix_alloc;
4116                 }
4117                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4118                 ctxt.info.valid_sections |=
4119                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4120         } else {
4121                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4122                 goto fail_msix_alloc;
4123         }
4124
4125         if (vsi->type != I40E_VSI_MAIN) {
4126                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4127                 if (ret != I40E_SUCCESS) {
4128                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4129                                     hw->aq.asq_last_status);
4130                         goto fail_msix_alloc;
4131                 }
4132                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4133                 vsi->info.valid_sections = 0;
4134                 vsi->seid = ctxt.seid;
4135                 vsi->vsi_id = ctxt.vsi_number;
4136                 vsi->sib_vsi_list.vsi = vsi;
4137                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4138                                 &vsi->sib_vsi_list, list);
4139         }
4140
4141         /* MAC/VLAN configuration */
4142         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4143         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4144
4145         ret = i40e_vsi_add_mac(vsi, &filter);
4146         if (ret != I40E_SUCCESS) {
4147                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4148                 goto fail_msix_alloc;
4149         }
4150
4151         /* Get VSI BW information */
4152         i40e_vsi_dump_bw_config(vsi);
4153         return vsi;
4154 fail_msix_alloc:
4155         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4156 fail_queue_alloc:
4157         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4158 fail_mem:
4159         rte_free(vsi);
4160         return NULL;
4161 }
4162
4163 /* Configure vlan stripping on or off */
4164 int
4165 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4166 {
4167         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4168         struct i40e_vsi_context ctxt;
4169         uint8_t vlan_flags;
4170         int ret = I40E_SUCCESS;
4171
4172         /* Check if it has been already on or off */
4173         if (vsi->info.valid_sections &
4174                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4175                 if (on) {
4176                         if ((vsi->info.port_vlan_flags &
4177                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4178                                 return 0; /* already on */
4179                 } else {
4180                         if ((vsi->info.port_vlan_flags &
4181                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4182                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4183                                 return 0; /* already off */
4184                 }
4185         }
4186
4187         if (on)
4188                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4189         else
4190                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4191         vsi->info.valid_sections =
4192                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4193         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4194         vsi->info.port_vlan_flags |= vlan_flags;
4195         ctxt.seid = vsi->seid;
4196         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4197         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4198         if (ret)
4199                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4200                             on ? "enable" : "disable");
4201
4202         return ret;
4203 }
4204
4205 static int
4206 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4207 {
4208         struct rte_eth_dev_data *data = dev->data;
4209         int ret;
4210
4211         /* Apply vlan offload setting */
4212         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
4213
4214         /* Apply double-vlan setting, not implemented yet */
4215
4216         /* Apply pvid setting */
4217         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4218                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4219         if (ret)
4220                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4221
4222         return ret;
4223 }
4224
4225 static int
4226 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4227 {
4228         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4229
4230         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4231 }
4232
4233 static int
4234 i40e_update_flow_control(struct i40e_hw *hw)
4235 {
4236 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4237         struct i40e_link_status link_status;
4238         uint32_t rxfc = 0, txfc = 0, reg;
4239         uint8_t an_info;
4240         int ret;
4241
4242         memset(&link_status, 0, sizeof(link_status));
4243         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4244         if (ret != I40E_SUCCESS) {
4245                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4246                 goto write_reg; /* Disable flow control */
4247         }
4248
4249         an_info = hw->phy.link_info.an_info;
4250         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4251                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4252                 ret = I40E_ERR_NOT_READY;
4253                 goto write_reg; /* Disable flow control */
4254         }
4255         /**
4256          * If link auto negotiation is enabled, flow control needs to
4257          * be configured according to it
4258          */
4259         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4260         case I40E_LINK_PAUSE_RXTX:
4261                 rxfc = 1;
4262                 txfc = 1;
4263                 hw->fc.current_mode = I40E_FC_FULL;
4264                 break;
4265         case I40E_AQ_LINK_PAUSE_RX:
4266                 rxfc = 1;
4267                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4268                 break;
4269         case I40E_AQ_LINK_PAUSE_TX:
4270                 txfc = 1;
4271                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4272                 break;
4273         default:
4274                 hw->fc.current_mode = I40E_FC_NONE;
4275                 break;
4276         }
4277
4278 write_reg:
4279         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4280                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4281         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4282         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4283         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4284         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4285
4286         return ret;
4287 }
4288
4289 /* PF setup */
4290 static int
4291 i40e_pf_setup(struct i40e_pf *pf)
4292 {
4293         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4294         struct i40e_filter_control_settings settings;
4295         struct i40e_vsi *vsi;
4296         int ret;
4297
4298         /* Clear all stats counters */
4299         pf->offset_loaded = FALSE;
4300         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4301         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4302
4303         ret = i40e_pf_get_switch_config(pf);
4304         if (ret != I40E_SUCCESS) {
4305                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4306                 return ret;
4307         }
4308         if (pf->flags & I40E_FLAG_FDIR) {
4309                 /* make queue allocated first, let FDIR use queue pair 0*/
4310                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4311                 if (ret != I40E_FDIR_QUEUE_ID) {
4312                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4313                                     " ret =%d", ret);
4314                         pf->flags &= ~I40E_FLAG_FDIR;
4315                 }
4316         }
4317         /*  main VSI setup */
4318         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4319         if (!vsi) {
4320                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4321                 return I40E_ERR_NOT_READY;
4322         }
4323         pf->main_vsi = vsi;
4324
4325         /* Configure filter control */
4326         memset(&settings, 0, sizeof(settings));
4327         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4328                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4329         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4330                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4331         else {
4332                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4333                                                 hw->func_caps.rss_table_size);
4334                 return I40E_ERR_PARAM;
4335         }
4336         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4337                         "size: %u\n", hw->func_caps.rss_table_size);
4338         pf->hash_lut_size = hw->func_caps.rss_table_size;
4339
4340         /* Enable ethtype and macvlan filters */
4341         settings.enable_ethtype = TRUE;
4342         settings.enable_macvlan = TRUE;
4343         ret = i40e_set_filter_control(hw, &settings);
4344         if (ret)
4345                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4346                                                                 ret);
4347
4348         /* Update flow control according to the auto negotiation */
4349         i40e_update_flow_control(hw);
4350
4351         return I40E_SUCCESS;
4352 }
4353
4354 int
4355 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4356 {
4357         uint32_t reg;
4358         uint16_t j;
4359
4360         /**
4361          * Set or clear TX Queue Disable flags,
4362          * which is required by hardware.
4363          */
4364         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4365         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4366
4367         /* Wait until the request is finished */
4368         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4369                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4370                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4371                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4372                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4373                                                         & 0x1))) {
4374                         break;
4375                 }
4376         }
4377         if (on) {
4378                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4379                         return I40E_SUCCESS; /* already on, skip next steps */
4380
4381                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4382                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4383         } else {
4384                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4385                         return I40E_SUCCESS; /* already off, skip next steps */
4386                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4387         }
4388         /* Write the register */
4389         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4390         /* Check the result */
4391         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4392                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4393                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4394                 if (on) {
4395                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4396                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4397                                 break;
4398                 } else {
4399                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4400                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4401                                 break;
4402                 }
4403         }
4404         /* Check if it is timeout */
4405         if (j >= I40E_CHK_Q_ENA_COUNT) {
4406                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4407                             (on ? "enable" : "disable"), q_idx);
4408                 return I40E_ERR_TIMEOUT;
4409         }
4410
4411         return I40E_SUCCESS;
4412 }
4413
4414 /* Swith on or off the tx queues */
4415 static int
4416 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4417 {
4418         struct rte_eth_dev_data *dev_data = pf->dev_data;
4419         struct i40e_tx_queue *txq;
4420         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4421         uint16_t i;
4422         int ret;
4423
4424         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4425                 txq = dev_data->tx_queues[i];
4426                 /* Don't operate the queue if not configured or
4427                  * if starting only per queue */
4428                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4429                         continue;
4430                 if (on)
4431                         ret = i40e_dev_tx_queue_start(dev, i);
4432                 else
4433                         ret = i40e_dev_tx_queue_stop(dev, i);
4434                 if ( ret != I40E_SUCCESS)
4435                         return ret;
4436         }
4437
4438         return I40E_SUCCESS;
4439 }
4440
4441 int
4442 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4443 {
4444         uint32_t reg;
4445         uint16_t j;
4446
4447         /* Wait until the request is finished */
4448         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4449                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4450                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4451                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4452                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4453                         break;
4454         }
4455
4456         if (on) {
4457                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4458                         return I40E_SUCCESS; /* Already on, skip next steps */
4459                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4460         } else {
4461                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4462                         return I40E_SUCCESS; /* Already off, skip next steps */
4463                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4464         }
4465
4466         /* Write the register */
4467         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4468         /* Check the result */
4469         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4470                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4471                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4472                 if (on) {
4473                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4474                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4475                                 break;
4476                 } else {
4477                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4478                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4479                                 break;
4480                 }
4481         }
4482
4483         /* Check if it is timeout */
4484         if (j >= I40E_CHK_Q_ENA_COUNT) {
4485                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4486                             (on ? "enable" : "disable"), q_idx);
4487                 return I40E_ERR_TIMEOUT;
4488         }
4489
4490         return I40E_SUCCESS;
4491 }
4492 /* Switch on or off the rx queues */
4493 static int
4494 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4495 {
4496         struct rte_eth_dev_data *dev_data = pf->dev_data;
4497         struct i40e_rx_queue *rxq;
4498         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4499         uint16_t i;
4500         int ret;
4501
4502         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4503                 rxq = dev_data->rx_queues[i];
4504                 /* Don't operate the queue if not configured or
4505                  * if starting only per queue */
4506                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4507                         continue;
4508                 if (on)
4509                         ret = i40e_dev_rx_queue_start(dev, i);
4510                 else
4511                         ret = i40e_dev_rx_queue_stop(dev, i);
4512                 if (ret != I40E_SUCCESS)
4513                         return ret;
4514         }
4515
4516         return I40E_SUCCESS;
4517 }
4518
4519 /* Switch on or off all the rx/tx queues */
4520 int
4521 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4522 {
4523         int ret;
4524
4525         if (on) {
4526                 /* enable rx queues before enabling tx queues */
4527                 ret = i40e_dev_switch_rx_queues(pf, on);
4528                 if (ret) {
4529                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4530                         return ret;
4531                 }
4532                 ret = i40e_dev_switch_tx_queues(pf, on);
4533         } else {
4534                 /* Stop tx queues before stopping rx queues */
4535                 ret = i40e_dev_switch_tx_queues(pf, on);
4536                 if (ret) {
4537                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4538                         return ret;
4539                 }
4540                 ret = i40e_dev_switch_rx_queues(pf, on);
4541         }
4542
4543         return ret;
4544 }
4545
4546 /* Initialize VSI for TX */
4547 static int
4548 i40e_dev_tx_init(struct i40e_pf *pf)
4549 {
4550         struct rte_eth_dev_data *data = pf->dev_data;
4551         uint16_t i;
4552         uint32_t ret = I40E_SUCCESS;
4553         struct i40e_tx_queue *txq;
4554
4555         for (i = 0; i < data->nb_tx_queues; i++) {
4556                 txq = data->tx_queues[i];
4557                 if (!txq || !txq->q_set)
4558                         continue;
4559                 ret = i40e_tx_queue_init(txq);
4560                 if (ret != I40E_SUCCESS)
4561                         break;
4562         }
4563         if (ret == I40E_SUCCESS)
4564                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4565                                      ->eth_dev);
4566
4567         return ret;
4568 }
4569
4570 /* Initialize VSI for RX */
4571 static int
4572 i40e_dev_rx_init(struct i40e_pf *pf)
4573 {
4574         struct rte_eth_dev_data *data = pf->dev_data;
4575         int ret = I40E_SUCCESS;
4576         uint16_t i;
4577         struct i40e_rx_queue *rxq;
4578
4579         i40e_pf_config_mq_rx(pf);
4580         for (i = 0; i < data->nb_rx_queues; i++) {
4581                 rxq = data->rx_queues[i];
4582                 if (!rxq || !rxq->q_set)
4583                         continue;
4584
4585                 ret = i40e_rx_queue_init(rxq);
4586                 if (ret != I40E_SUCCESS) {
4587                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4588                                     "initialization");
4589                         break;
4590                 }
4591         }
4592         if (ret == I40E_SUCCESS)
4593                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4594                                      ->eth_dev);
4595
4596         return ret;
4597 }
4598
4599 static int
4600 i40e_dev_rxtx_init(struct i40e_pf *pf)
4601 {
4602         int err;
4603
4604         err = i40e_dev_tx_init(pf);
4605         if (err) {
4606                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4607                 return err;
4608         }
4609         err = i40e_dev_rx_init(pf);
4610         if (err) {
4611                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4612                 return err;
4613         }
4614
4615         return err;
4616 }
4617
4618 static int
4619 i40e_vmdq_setup(struct rte_eth_dev *dev)
4620 {
4621         struct rte_eth_conf *conf = &dev->data->dev_conf;
4622         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4623         int i, err, conf_vsis, j, loop;
4624         struct i40e_vsi *vsi;
4625         struct i40e_vmdq_info *vmdq_info;
4626         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4627         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4628
4629         /*
4630          * Disable interrupt to avoid message from VF. Furthermore, it will
4631          * avoid race condition in VSI creation/destroy.
4632          */
4633         i40e_pf_disable_irq0(hw);
4634
4635         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4636                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4637                 return -ENOTSUP;
4638         }
4639
4640         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4641         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4642                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4643                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4644                         pf->max_nb_vmdq_vsi);
4645                 return -ENOTSUP;
4646         }
4647
4648         if (pf->vmdq != NULL) {
4649                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4650                 return 0;
4651         }
4652
4653         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4654                                 sizeof(*vmdq_info) * conf_vsis, 0);
4655
4656         if (pf->vmdq == NULL) {
4657                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4658                 return -ENOMEM;
4659         }
4660
4661         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4662
4663         /* Create VMDQ VSI */
4664         for (i = 0; i < conf_vsis; i++) {
4665                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4666                                 vmdq_conf->enable_loop_back);
4667                 if (vsi == NULL) {
4668                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4669                         err = -1;
4670                         goto err_vsi_setup;
4671                 }
4672                 vmdq_info = &pf->vmdq[i];
4673                 vmdq_info->pf = pf;
4674                 vmdq_info->vsi = vsi;
4675         }
4676         pf->nb_cfg_vmdq_vsi = conf_vsis;
4677
4678         /* Configure Vlan */
4679         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4680         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4681                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4682                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4683                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4684                                         vmdq_conf->pool_map[i].vlan_id, j);
4685
4686                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4687                                                 vmdq_conf->pool_map[i].vlan_id);
4688                                 if (err) {
4689                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4690                                         err = -1;
4691                                         goto err_vsi_setup;
4692                                 }
4693                         }
4694                 }
4695         }
4696
4697         i40e_pf_enable_irq0(hw);
4698
4699         return 0;
4700
4701 err_vsi_setup:
4702         for (i = 0; i < conf_vsis; i++)
4703                 if (pf->vmdq[i].vsi == NULL)
4704                         break;
4705                 else
4706                         i40e_vsi_release(pf->vmdq[i].vsi);
4707
4708         rte_free(pf->vmdq);
4709         pf->vmdq = NULL;
4710         i40e_pf_enable_irq0(hw);
4711         return err;
4712 }
4713
4714 static void
4715 i40e_stat_update_32(struct i40e_hw *hw,
4716                    uint32_t reg,
4717                    bool offset_loaded,
4718                    uint64_t *offset,
4719                    uint64_t *stat)
4720 {
4721         uint64_t new_data;
4722
4723         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4724         if (!offset_loaded)
4725                 *offset = new_data;
4726
4727         if (new_data >= *offset)
4728                 *stat = (uint64_t)(new_data - *offset);
4729         else
4730                 *stat = (uint64_t)((new_data +
4731                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4732 }
4733
4734 static void
4735 i40e_stat_update_48(struct i40e_hw *hw,
4736                    uint32_t hireg,
4737                    uint32_t loreg,
4738                    bool offset_loaded,
4739                    uint64_t *offset,
4740                    uint64_t *stat)
4741 {
4742         uint64_t new_data;
4743
4744         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4745         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4746                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4747
4748         if (!offset_loaded)
4749                 *offset = new_data;
4750
4751         if (new_data >= *offset)
4752                 *stat = new_data - *offset;
4753         else
4754                 *stat = (uint64_t)((new_data +
4755                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4756
4757         *stat &= I40E_48_BIT_MASK;
4758 }
4759
4760 /* Disable IRQ0 */
4761 void
4762 i40e_pf_disable_irq0(struct i40e_hw *hw)
4763 {
4764         /* Disable all interrupt types */
4765         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4766         I40E_WRITE_FLUSH(hw);
4767 }
4768
4769 /* Enable IRQ0 */
4770 void
4771 i40e_pf_enable_irq0(struct i40e_hw *hw)
4772 {
4773         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4774                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4775                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4776                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4777         I40E_WRITE_FLUSH(hw);
4778 }
4779
4780 static void
4781 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4782 {
4783         /* read pending request and disable first */
4784         i40e_pf_disable_irq0(hw);
4785         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4786         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4787                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4788
4789         if (no_queue)
4790                 /* Link no queues with irq0 */
4791                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4792                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4793 }
4794
4795 static void
4796 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4797 {
4798         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4799         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4800         int i;
4801         uint16_t abs_vf_id;
4802         uint32_t index, offset, val;
4803
4804         if (!pf->vfs)
4805                 return;
4806         /**
4807          * Try to find which VF trigger a reset, use absolute VF id to access
4808          * since the reg is global register.
4809          */
4810         for (i = 0; i < pf->vf_num; i++) {
4811                 abs_vf_id = hw->func_caps.vf_base_id + i;
4812                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4813                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4814                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4815                 /* VFR event occured */
4816                 if (val & (0x1 << offset)) {
4817                         int ret;
4818
4819                         /* Clear the event first */
4820                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4821                                                         (0x1 << offset));
4822                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4823                         /**
4824                          * Only notify a VF reset event occured,
4825                          * don't trigger another SW reset
4826                          */
4827                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4828                         if (ret != I40E_SUCCESS)
4829                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4830                 }
4831         }
4832 }
4833
4834 static void
4835 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4836 {
4837         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4838         struct i40e_arq_event_info info;
4839         uint16_t pending, opcode;
4840         int ret;
4841
4842         info.buf_len = I40E_AQ_BUF_SZ;
4843         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4844         if (!info.msg_buf) {
4845                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4846                 return;
4847         }
4848
4849         pending = 1;
4850         while (pending) {
4851                 ret = i40e_clean_arq_element(hw, &info, &pending);
4852
4853                 if (ret != I40E_SUCCESS) {
4854                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4855                                     "aq_err: %u", hw->aq.asq_last_status);
4856                         break;
4857                 }
4858                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4859
4860                 switch (opcode) {
4861                 case i40e_aqc_opc_send_msg_to_pf:
4862                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4863                         i40e_pf_host_handle_vf_msg(dev,
4864                                         rte_le_to_cpu_16(info.desc.retval),
4865                                         rte_le_to_cpu_32(info.desc.cookie_high),
4866                                         rte_le_to_cpu_32(info.desc.cookie_low),
4867                                         info.msg_buf,
4868                                         info.msg_len);
4869                         break;
4870                 default:
4871                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4872                                     opcode);
4873                         break;
4874                 }
4875         }
4876         rte_free(info.msg_buf);
4877 }
4878
4879 /*
4880  * Interrupt handler is registered as the alarm callback for handling LSC
4881  * interrupt in a definite of time, in order to wait the NIC into a stable
4882  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4883  * no need for link down interrupt.
4884  */
4885 static void
4886 i40e_dev_interrupt_delayed_handler(void *param)
4887 {
4888         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4889         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4890         uint32_t icr0;
4891
4892         /* read interrupt causes again */
4893         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4894
4895 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4896         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4897                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4898         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4899                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4900         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4901                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4902         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4903                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4904         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4905                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4906                                                                 "state\n");
4907         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4908                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4909         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4910                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4911 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4912
4913         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4914                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4915                 i40e_dev_handle_vfr_event(dev);
4916         }
4917         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4918                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4919                 i40e_dev_handle_aq_msg(dev);
4920         }
4921
4922         /* handle the link up interrupt in an alarm callback */
4923         i40e_dev_link_update(dev, 0);
4924         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4925
4926         i40e_pf_enable_irq0(hw);
4927         rte_intr_enable(&(dev->pci_dev->intr_handle));
4928 }
4929
4930 /**
4931  * Interrupt handler triggered by NIC  for handling
4932  * specific interrupt.
4933  *
4934  * @param handle
4935  *  Pointer to interrupt handle.
4936  * @param param
4937  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4938  *
4939  * @return
4940  *  void
4941  */
4942 static void
4943 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4944                            void *param)
4945 {
4946         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4947         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4948         uint32_t icr0;
4949
4950         /* Disable interrupt */
4951         i40e_pf_disable_irq0(hw);
4952
4953         /* read out interrupt causes */
4954         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4955
4956         /* No interrupt event indicated */
4957         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4958                 PMD_DRV_LOG(INFO, "No interrupt event");
4959                 goto done;
4960         }
4961 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4962         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4963                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4964         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4965                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4966         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4967                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4968         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4969                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4970         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4971                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4972         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4973                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4974         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4975                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4976 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4977
4978         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4979                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4980                 i40e_dev_handle_vfr_event(dev);
4981         }
4982         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4983                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4984                 i40e_dev_handle_aq_msg(dev);
4985         }
4986
4987         /* Link Status Change interrupt */
4988         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4989 #define I40E_US_PER_SECOND 1000000
4990                 struct rte_eth_link link;
4991
4992                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4993                 memset(&link, 0, sizeof(link));
4994                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4995                 i40e_dev_link_update(dev, 0);
4996
4997                 /*
4998                  * For link up interrupt, it needs to wait 1 second to let the
4999                  * hardware be a stable state. Otherwise several consecutive
5000                  * interrupts can be observed.
5001                  * For link down interrupt, no need to wait.
5002                  */
5003                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5004                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5005                         return;
5006                 else
5007                         _rte_eth_dev_callback_process(dev,
5008                                 RTE_ETH_EVENT_INTR_LSC);
5009         }
5010
5011 done:
5012         /* Enable interrupt */
5013         i40e_pf_enable_irq0(hw);
5014         rte_intr_enable(&(dev->pci_dev->intr_handle));
5015 }
5016
5017 static int
5018 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5019                          struct i40e_macvlan_filter *filter,
5020                          int total)
5021 {
5022         int ele_num, ele_buff_size;
5023         int num, actual_num, i;
5024         uint16_t flags;
5025         int ret = I40E_SUCCESS;
5026         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5027         struct i40e_aqc_add_macvlan_element_data *req_list;
5028
5029         if (filter == NULL  || total == 0)
5030                 return I40E_ERR_PARAM;
5031         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5032         ele_buff_size = hw->aq.asq_buf_size;
5033
5034         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5035         if (req_list == NULL) {
5036                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5037                 return I40E_ERR_NO_MEMORY;
5038         }
5039
5040         num = 0;
5041         do {
5042                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5043                 memset(req_list, 0, ele_buff_size);
5044
5045                 for (i = 0; i < actual_num; i++) {
5046                         (void)rte_memcpy(req_list[i].mac_addr,
5047                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5048                         req_list[i].vlan_tag =
5049                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5050
5051                         switch (filter[num + i].filter_type) {
5052                         case RTE_MAC_PERFECT_MATCH:
5053                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5054                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5055                                 break;
5056                         case RTE_MACVLAN_PERFECT_MATCH:
5057                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5058                                 break;
5059                         case RTE_MAC_HASH_MATCH:
5060                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5061                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5062                                 break;
5063                         case RTE_MACVLAN_HASH_MATCH:
5064                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5065                                 break;
5066                         default:
5067                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5068                                 ret = I40E_ERR_PARAM;
5069                                 goto DONE;
5070                         }
5071
5072                         req_list[i].queue_number = 0;
5073
5074                         req_list[i].flags = rte_cpu_to_le_16(flags);
5075                 }
5076
5077                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5078                                                 actual_num, NULL);
5079                 if (ret != I40E_SUCCESS) {
5080                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5081                         goto DONE;
5082                 }
5083                 num += actual_num;
5084         } while (num < total);
5085
5086 DONE:
5087         rte_free(req_list);
5088         return ret;
5089 }
5090
5091 static int
5092 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5093                             struct i40e_macvlan_filter *filter,
5094                             int total)
5095 {
5096         int ele_num, ele_buff_size;
5097         int num, actual_num, i;
5098         uint16_t flags;
5099         int ret = I40E_SUCCESS;
5100         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5101         struct i40e_aqc_remove_macvlan_element_data *req_list;
5102
5103         if (filter == NULL  || total == 0)
5104                 return I40E_ERR_PARAM;
5105
5106         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5107         ele_buff_size = hw->aq.asq_buf_size;
5108
5109         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5110         if (req_list == NULL) {
5111                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5112                 return I40E_ERR_NO_MEMORY;
5113         }
5114
5115         num = 0;
5116         do {
5117                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5118                 memset(req_list, 0, ele_buff_size);
5119
5120                 for (i = 0; i < actual_num; i++) {
5121                         (void)rte_memcpy(req_list[i].mac_addr,
5122                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5123                         req_list[i].vlan_tag =
5124                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5125
5126                         switch (filter[num + i].filter_type) {
5127                         case RTE_MAC_PERFECT_MATCH:
5128                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5129                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5130                                 break;
5131                         case RTE_MACVLAN_PERFECT_MATCH:
5132                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5133                                 break;
5134                         case RTE_MAC_HASH_MATCH:
5135                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5136                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5137                                 break;
5138                         case RTE_MACVLAN_HASH_MATCH:
5139                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5140                                 break;
5141                         default:
5142                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5143                                 ret = I40E_ERR_PARAM;
5144                                 goto DONE;
5145                         }
5146                         req_list[i].flags = rte_cpu_to_le_16(flags);
5147                 }
5148
5149                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5150                                                 actual_num, NULL);
5151                 if (ret != I40E_SUCCESS) {
5152                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5153                         goto DONE;
5154                 }
5155                 num += actual_num;
5156         } while (num < total);
5157
5158 DONE:
5159         rte_free(req_list);
5160         return ret;
5161 }
5162
5163 /* Find out specific MAC filter */
5164 static struct i40e_mac_filter *
5165 i40e_find_mac_filter(struct i40e_vsi *vsi,
5166                          struct ether_addr *macaddr)
5167 {
5168         struct i40e_mac_filter *f;
5169
5170         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5171                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5172                         return f;
5173         }
5174
5175         return NULL;
5176 }
5177
5178 static bool
5179 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5180                          uint16_t vlan_id)
5181 {
5182         uint32_t vid_idx, vid_bit;
5183
5184         if (vlan_id > ETH_VLAN_ID_MAX)
5185                 return 0;
5186
5187         vid_idx = I40E_VFTA_IDX(vlan_id);
5188         vid_bit = I40E_VFTA_BIT(vlan_id);
5189
5190         if (vsi->vfta[vid_idx] & vid_bit)
5191                 return 1;
5192         else
5193                 return 0;
5194 }
5195
5196 static void
5197 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5198                          uint16_t vlan_id, bool on)
5199 {
5200         uint32_t vid_idx, vid_bit;
5201
5202         if (vlan_id > ETH_VLAN_ID_MAX)
5203                 return;
5204
5205         vid_idx = I40E_VFTA_IDX(vlan_id);
5206         vid_bit = I40E_VFTA_BIT(vlan_id);
5207
5208         if (on)
5209                 vsi->vfta[vid_idx] |= vid_bit;
5210         else
5211                 vsi->vfta[vid_idx] &= ~vid_bit;
5212 }
5213
5214 /**
5215  * Find all vlan options for specific mac addr,
5216  * return with actual vlan found.
5217  */
5218 static inline int
5219 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5220                            struct i40e_macvlan_filter *mv_f,
5221                            int num, struct ether_addr *addr)
5222 {
5223         int i;
5224         uint32_t j, k;
5225
5226         /**
5227          * Not to use i40e_find_vlan_filter to decrease the loop time,
5228          * although the code looks complex.
5229           */
5230         if (num < vsi->vlan_num)
5231                 return I40E_ERR_PARAM;
5232
5233         i = 0;
5234         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5235                 if (vsi->vfta[j]) {
5236                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5237                                 if (vsi->vfta[j] & (1 << k)) {
5238                                         if (i > num - 1) {
5239                                                 PMD_DRV_LOG(ERR, "vlan number "
5240                                                             "not match");
5241                                                 return I40E_ERR_PARAM;
5242                                         }
5243                                         (void)rte_memcpy(&mv_f[i].macaddr,
5244                                                         addr, ETH_ADDR_LEN);
5245                                         mv_f[i].vlan_id =
5246                                                 j * I40E_UINT32_BIT_SIZE + k;
5247                                         i++;
5248                                 }
5249                         }
5250                 }
5251         }
5252         return I40E_SUCCESS;
5253 }
5254
5255 static inline int
5256 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5257                            struct i40e_macvlan_filter *mv_f,
5258                            int num,
5259                            uint16_t vlan)
5260 {
5261         int i = 0;
5262         struct i40e_mac_filter *f;
5263
5264         if (num < vsi->mac_num)
5265                 return I40E_ERR_PARAM;
5266
5267         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5268                 if (i > num - 1) {
5269                         PMD_DRV_LOG(ERR, "buffer number not match");
5270                         return I40E_ERR_PARAM;
5271                 }
5272                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5273                                 ETH_ADDR_LEN);
5274                 mv_f[i].vlan_id = vlan;
5275                 mv_f[i].filter_type = f->mac_info.filter_type;
5276                 i++;
5277         }
5278
5279         return I40E_SUCCESS;
5280 }
5281
5282 static int
5283 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5284 {
5285         int i, num;
5286         struct i40e_mac_filter *f;
5287         struct i40e_macvlan_filter *mv_f;
5288         int ret = I40E_SUCCESS;
5289
5290         if (vsi == NULL || vsi->mac_num == 0)
5291                 return I40E_ERR_PARAM;
5292
5293         /* Case that no vlan is set */
5294         if (vsi->vlan_num == 0)
5295                 num = vsi->mac_num;
5296         else
5297                 num = vsi->mac_num * vsi->vlan_num;
5298
5299         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5300         if (mv_f == NULL) {
5301                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5302                 return I40E_ERR_NO_MEMORY;
5303         }
5304
5305         i = 0;
5306         if (vsi->vlan_num == 0) {
5307                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5308                         (void)rte_memcpy(&mv_f[i].macaddr,
5309                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5310                         mv_f[i].vlan_id = 0;
5311                         i++;
5312                 }
5313         } else {
5314                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5315                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5316                                         vsi->vlan_num, &f->mac_info.mac_addr);
5317                         if (ret != I40E_SUCCESS)
5318                                 goto DONE;
5319                         i += vsi->vlan_num;
5320                 }
5321         }
5322
5323         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5324 DONE:
5325         rte_free(mv_f);
5326
5327         return ret;
5328 }
5329
5330 int
5331 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5332 {
5333         struct i40e_macvlan_filter *mv_f;
5334         int mac_num;
5335         int ret = I40E_SUCCESS;
5336
5337         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5338                 return I40E_ERR_PARAM;
5339
5340         /* If it's already set, just return */
5341         if (i40e_find_vlan_filter(vsi,vlan))
5342                 return I40E_SUCCESS;
5343
5344         mac_num = vsi->mac_num;
5345
5346         if (mac_num == 0) {
5347                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5348                 return I40E_ERR_PARAM;
5349         }
5350
5351         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5352
5353         if (mv_f == NULL) {
5354                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5355                 return I40E_ERR_NO_MEMORY;
5356         }
5357
5358         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5359
5360         if (ret != I40E_SUCCESS)
5361                 goto DONE;
5362
5363         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5364
5365         if (ret != I40E_SUCCESS)
5366                 goto DONE;
5367
5368         i40e_set_vlan_filter(vsi, vlan, 1);
5369
5370         vsi->vlan_num++;
5371         ret = I40E_SUCCESS;
5372 DONE:
5373         rte_free(mv_f);
5374         return ret;
5375 }
5376
5377 int
5378 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5379 {
5380         struct i40e_macvlan_filter *mv_f;
5381         int mac_num;
5382         int ret = I40E_SUCCESS;
5383
5384         /**
5385          * Vlan 0 is the generic filter for untagged packets
5386          * and can't be removed.
5387          */
5388         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5389                 return I40E_ERR_PARAM;
5390
5391         /* If can't find it, just return */
5392         if (!i40e_find_vlan_filter(vsi, vlan))
5393                 return I40E_ERR_PARAM;
5394
5395         mac_num = vsi->mac_num;
5396
5397         if (mac_num == 0) {
5398                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5399                 return I40E_ERR_PARAM;
5400         }
5401
5402         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5403
5404         if (mv_f == NULL) {
5405                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5406                 return I40E_ERR_NO_MEMORY;
5407         }
5408
5409         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5410
5411         if (ret != I40E_SUCCESS)
5412                 goto DONE;
5413
5414         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5415
5416         if (ret != I40E_SUCCESS)
5417                 goto DONE;
5418
5419         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5420         if (vsi->vlan_num == 1) {
5421                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5422                 if (ret != I40E_SUCCESS)
5423                         goto DONE;
5424
5425                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5426                 if (ret != I40E_SUCCESS)
5427                         goto DONE;
5428         }
5429
5430         i40e_set_vlan_filter(vsi, vlan, 0);
5431
5432         vsi->vlan_num--;
5433         ret = I40E_SUCCESS;
5434 DONE:
5435         rte_free(mv_f);
5436         return ret;
5437 }
5438
5439 int
5440 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5441 {
5442         struct i40e_mac_filter *f;
5443         struct i40e_macvlan_filter *mv_f;
5444         int i, vlan_num = 0;
5445         int ret = I40E_SUCCESS;
5446
5447         /* If it's add and we've config it, return */
5448         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5449         if (f != NULL)
5450                 return I40E_SUCCESS;
5451         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5452                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5453
5454                 /**
5455                  * If vlan_num is 0, that's the first time to add mac,
5456                  * set mask for vlan_id 0.
5457                  */
5458                 if (vsi->vlan_num == 0) {
5459                         i40e_set_vlan_filter(vsi, 0, 1);
5460                         vsi->vlan_num = 1;
5461                 }
5462                 vlan_num = vsi->vlan_num;
5463         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5464                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5465                 vlan_num = 1;
5466
5467         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5468         if (mv_f == NULL) {
5469                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5470                 return I40E_ERR_NO_MEMORY;
5471         }
5472
5473         for (i = 0; i < vlan_num; i++) {
5474                 mv_f[i].filter_type = mac_filter->filter_type;
5475                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5476                                 ETH_ADDR_LEN);
5477         }
5478
5479         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5480                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5481                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5482                                         &mac_filter->mac_addr);
5483                 if (ret != I40E_SUCCESS)
5484                         goto DONE;
5485         }
5486
5487         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5488         if (ret != I40E_SUCCESS)
5489                 goto DONE;
5490
5491         /* Add the mac addr into mac list */
5492         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5493         if (f == NULL) {
5494                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5495                 ret = I40E_ERR_NO_MEMORY;
5496                 goto DONE;
5497         }
5498         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5499                         ETH_ADDR_LEN);
5500         f->mac_info.filter_type = mac_filter->filter_type;
5501         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5502         vsi->mac_num++;
5503
5504         ret = I40E_SUCCESS;
5505 DONE:
5506         rte_free(mv_f);
5507
5508         return ret;
5509 }
5510
5511 int
5512 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5513 {
5514         struct i40e_mac_filter *f;
5515         struct i40e_macvlan_filter *mv_f;
5516         int i, vlan_num;
5517         enum rte_mac_filter_type filter_type;
5518         int ret = I40E_SUCCESS;
5519
5520         /* Can't find it, return an error */
5521         f = i40e_find_mac_filter(vsi, addr);
5522         if (f == NULL)
5523                 return I40E_ERR_PARAM;
5524
5525         vlan_num = vsi->vlan_num;
5526         filter_type = f->mac_info.filter_type;
5527         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5528                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5529                 if (vlan_num == 0) {
5530                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5531                         return I40E_ERR_PARAM;
5532                 }
5533         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5534                         filter_type == RTE_MAC_HASH_MATCH)
5535                 vlan_num = 1;
5536
5537         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5538         if (mv_f == NULL) {
5539                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5540                 return I40E_ERR_NO_MEMORY;
5541         }
5542
5543         for (i = 0; i < vlan_num; i++) {
5544                 mv_f[i].filter_type = filter_type;
5545                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5546                                 ETH_ADDR_LEN);
5547         }
5548         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5549                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5550                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5551                 if (ret != I40E_SUCCESS)
5552                         goto DONE;
5553         }
5554
5555         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5556         if (ret != I40E_SUCCESS)
5557                 goto DONE;
5558
5559         /* Remove the mac addr into mac list */
5560         TAILQ_REMOVE(&vsi->mac_list, f, next);
5561         rte_free(f);
5562         vsi->mac_num--;
5563
5564         ret = I40E_SUCCESS;
5565 DONE:
5566         rte_free(mv_f);
5567         return ret;
5568 }
5569
5570 /* Configure hash enable flags for RSS */
5571 uint64_t
5572 i40e_config_hena(uint64_t flags)
5573 {
5574         uint64_t hena = 0;
5575
5576         if (!flags)
5577                 return hena;
5578
5579         if (flags & ETH_RSS_FRAG_IPV4)
5580                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5581         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5582                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5583         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5584                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5585         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5586                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5587         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5588                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5589         if (flags & ETH_RSS_FRAG_IPV6)
5590                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5591         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5592                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5593         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5594                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5595         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5596                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5597         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5598                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5599         if (flags & ETH_RSS_L2_PAYLOAD)
5600                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5601
5602         return hena;
5603 }
5604
5605 /* Parse the hash enable flags */
5606 uint64_t
5607 i40e_parse_hena(uint64_t flags)
5608 {
5609         uint64_t rss_hf = 0;
5610
5611         if (!flags)
5612                 return rss_hf;
5613         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5614                 rss_hf |= ETH_RSS_FRAG_IPV4;
5615         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5616                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5617         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5618                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5619         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5620                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5621         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5622                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5623         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5624                 rss_hf |= ETH_RSS_FRAG_IPV6;
5625         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5626                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5627         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5628                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5629         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5630                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5631         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5632                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5633         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5634                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5635
5636         return rss_hf;
5637 }
5638
5639 /* Disable RSS */
5640 static void
5641 i40e_pf_disable_rss(struct i40e_pf *pf)
5642 {
5643         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5644         uint64_t hena;
5645
5646         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5647         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5648         hena &= ~I40E_RSS_HENA_ALL;
5649         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5650         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5651         I40E_WRITE_FLUSH(hw);
5652 }
5653
5654 static int
5655 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5656 {
5657         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5658         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5659         int ret = 0;
5660
5661         if (!key || key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) *
5662                 sizeof(uint32_t)))
5663                 return -EINVAL;
5664
5665         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5666                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5667                         (struct i40e_aqc_get_set_rss_key_data *)key;
5668
5669                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5670                 if (ret)
5671                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5672                                      "via AQ");
5673         } else {
5674                 uint32_t *hash_key = (uint32_t *)key;
5675                 uint16_t i;
5676
5677                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5678                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5679                 I40E_WRITE_FLUSH(hw);
5680         }
5681
5682         return ret;
5683 }
5684
5685 static int
5686 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5687 {
5688         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5689         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5690         int ret;
5691
5692         if (!key || !key_len)
5693                 return -EINVAL;
5694
5695         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5696                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5697                         (struct i40e_aqc_get_set_rss_key_data *)key);
5698                 if (ret) {
5699                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5700                         return ret;
5701                 }
5702         } else {
5703                 uint32_t *key_dw = (uint32_t *)key;
5704                 uint16_t i;
5705
5706                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5707                         key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5708         }
5709         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5710
5711         return 0;
5712 }
5713
5714 static int
5715 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5716 {
5717         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5718         uint64_t rss_hf;
5719         uint64_t hena;
5720         int ret;
5721
5722         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5723                                rss_conf->rss_key_len);
5724         if (ret)
5725                 return ret;
5726
5727         rss_hf = rss_conf->rss_hf;
5728         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5729         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5730         hena &= ~I40E_RSS_HENA_ALL;
5731         hena |= i40e_config_hena(rss_hf);
5732         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5733         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5734         I40E_WRITE_FLUSH(hw);
5735
5736         return 0;
5737 }
5738
5739 static int
5740 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5741                          struct rte_eth_rss_conf *rss_conf)
5742 {
5743         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5744         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5745         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5746         uint64_t hena;
5747
5748         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5749         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5750         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5751                 if (rss_hf != 0) /* Enable RSS */
5752                         return -EINVAL;
5753                 return 0; /* Nothing to do */
5754         }
5755         /* RSS enabled */
5756         if (rss_hf == 0) /* Disable RSS */
5757                 return -EINVAL;
5758
5759         return i40e_hw_rss_hash_set(pf, rss_conf);
5760 }
5761
5762 static int
5763 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5764                            struct rte_eth_rss_conf *rss_conf)
5765 {
5766         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5767         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5768         uint64_t hena;
5769
5770         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5771                          &rss_conf->rss_key_len);
5772
5773         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5774         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5775         rss_conf->rss_hf = i40e_parse_hena(hena);
5776
5777         return 0;
5778 }
5779
5780 static int
5781 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5782 {
5783         switch (filter_type) {
5784         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5785                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5786                 break;
5787         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5788                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5789                 break;
5790         case RTE_TUNNEL_FILTER_IMAC_TENID:
5791                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5792                 break;
5793         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5794                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5795                 break;
5796         case ETH_TUNNEL_FILTER_IMAC:
5797                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5798                 break;
5799         default:
5800                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5801                 return -EINVAL;
5802         }
5803
5804         return 0;
5805 }
5806
5807 static int
5808 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5809                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5810                         uint8_t add)
5811 {
5812         uint16_t ip_type;
5813         uint8_t tun_type = 0;
5814         int val, ret = 0;
5815         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5816         struct i40e_vsi *vsi = pf->main_vsi;
5817         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5818         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5819
5820         cld_filter = rte_zmalloc("tunnel_filter",
5821                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5822                 0);
5823
5824         if (NULL == cld_filter) {
5825                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5826                 return -EINVAL;
5827         }
5828         pfilter = cld_filter;
5829
5830         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5831                         sizeof(struct ether_addr));
5832         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5833                         sizeof(struct ether_addr));
5834
5835         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5836         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5837                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5838                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5839                                 &tunnel_filter->ip_addr,
5840                                 sizeof(pfilter->ipaddr.v4.data));
5841         } else {
5842                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5843                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5844                                 &tunnel_filter->ip_addr,
5845                                 sizeof(pfilter->ipaddr.v6.data));
5846         }
5847
5848         /* check tunneled type */
5849         switch (tunnel_filter->tunnel_type) {
5850         case RTE_TUNNEL_TYPE_VXLAN:
5851                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5852                 break;
5853         case RTE_TUNNEL_TYPE_NVGRE:
5854                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5855                 break;
5856         default:
5857                 /* Other tunnel types is not supported. */
5858                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5859                 rte_free(cld_filter);
5860                 return -EINVAL;
5861         }
5862
5863         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5864                                                 &pfilter->flags);
5865         if (val < 0) {
5866                 rte_free(cld_filter);
5867                 return -EINVAL;
5868         }
5869
5870         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5871                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5872         pfilter->tenant_id = tunnel_filter->tenant_id;
5873         pfilter->queue_number = tunnel_filter->queue_id;
5874
5875         if (add)
5876                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5877         else
5878                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5879                                                 cld_filter, 1);
5880
5881         rte_free(cld_filter);
5882         return ret;
5883 }
5884
5885 static int
5886 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5887 {
5888         uint8_t i;
5889
5890         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5891                 if (pf->vxlan_ports[i] == port)
5892                         return i;
5893         }
5894
5895         return -1;
5896 }
5897
5898 static int
5899 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5900 {
5901         int  idx, ret;
5902         uint8_t filter_idx;
5903         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5904
5905         idx = i40e_get_vxlan_port_idx(pf, port);
5906
5907         /* Check if port already exists */
5908         if (idx >= 0) {
5909                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5910                 return -EINVAL;
5911         }
5912
5913         /* Now check if there is space to add the new port */
5914         idx = i40e_get_vxlan_port_idx(pf, 0);
5915         if (idx < 0) {
5916                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5917                         "not adding port %d", port);
5918                 return -ENOSPC;
5919         }
5920
5921         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5922                                         &filter_idx, NULL);
5923         if (ret < 0) {
5924                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5925                 return -1;
5926         }
5927
5928         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5929                          port,  filter_idx);
5930
5931         /* New port: add it and mark its index in the bitmap */
5932         pf->vxlan_ports[idx] = port;
5933         pf->vxlan_bitmap |= (1 << idx);
5934
5935         if (!(pf->flags & I40E_FLAG_VXLAN))
5936                 pf->flags |= I40E_FLAG_VXLAN;
5937
5938         return 0;
5939 }
5940
5941 static int
5942 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5943 {
5944         int idx;
5945         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5946
5947         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5948                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5949                 return -EINVAL;
5950         }
5951
5952         idx = i40e_get_vxlan_port_idx(pf, port);
5953
5954         if (idx < 0) {
5955                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5956                 return -EINVAL;
5957         }
5958
5959         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5960                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5961                 return -1;
5962         }
5963
5964         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5965                         port, idx);
5966
5967         pf->vxlan_ports[idx] = 0;
5968         pf->vxlan_bitmap &= ~(1 << idx);
5969
5970         if (!pf->vxlan_bitmap)
5971                 pf->flags &= ~I40E_FLAG_VXLAN;
5972
5973         return 0;
5974 }
5975
5976 /* Add UDP tunneling port */
5977 static int
5978 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5979                         struct rte_eth_udp_tunnel *udp_tunnel)
5980 {
5981         int ret = 0;
5982         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5983
5984         if (udp_tunnel == NULL)
5985                 return -EINVAL;
5986
5987         switch (udp_tunnel->prot_type) {
5988         case RTE_TUNNEL_TYPE_VXLAN:
5989                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5990                 break;
5991
5992         case RTE_TUNNEL_TYPE_GENEVE:
5993         case RTE_TUNNEL_TYPE_TEREDO:
5994                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5995                 ret = -1;
5996                 break;
5997
5998         default:
5999                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6000                 ret = -1;
6001                 break;
6002         }
6003
6004         return ret;
6005 }
6006
6007 /* Remove UDP tunneling port */
6008 static int
6009 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
6010                         struct rte_eth_udp_tunnel *udp_tunnel)
6011 {
6012         int ret = 0;
6013         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6014
6015         if (udp_tunnel == NULL)
6016                 return -EINVAL;
6017
6018         switch (udp_tunnel->prot_type) {
6019         case RTE_TUNNEL_TYPE_VXLAN:
6020                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6021                 break;
6022         case RTE_TUNNEL_TYPE_GENEVE:
6023         case RTE_TUNNEL_TYPE_TEREDO:
6024                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6025                 ret = -1;
6026                 break;
6027         default:
6028                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6029                 ret = -1;
6030                 break;
6031         }
6032
6033         return ret;
6034 }
6035
6036 /* Calculate the maximum number of contiguous PF queues that are configured */
6037 static int
6038 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6039 {
6040         struct rte_eth_dev_data *data = pf->dev_data;
6041         int i, num;
6042         struct i40e_rx_queue *rxq;
6043
6044         num = 0;
6045         for (i = 0; i < pf->lan_nb_qps; i++) {
6046                 rxq = data->rx_queues[i];
6047                 if (rxq && rxq->q_set)
6048                         num++;
6049                 else
6050                         break;
6051         }
6052
6053         return num;
6054 }
6055
6056 /* Configure RSS */
6057 static int
6058 i40e_pf_config_rss(struct i40e_pf *pf)
6059 {
6060         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6061         struct rte_eth_rss_conf rss_conf;
6062         uint32_t i, lut = 0;
6063         uint16_t j, num;
6064
6065         /*
6066          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6067          * It's necessary to calulate the actual PF queues that are configured.
6068          */
6069         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6070                 num = i40e_pf_calc_configured_queues_num(pf);
6071         else
6072                 num = pf->dev_data->nb_rx_queues;
6073
6074         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6075         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6076                         num);
6077
6078         if (num == 0) {
6079                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6080                 return -ENOTSUP;
6081         }
6082
6083         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6084                 if (j == num)
6085                         j = 0;
6086                 lut = (lut << 8) | (j & ((0x1 <<
6087                         hw->func_caps.rss_table_entry_width) - 1));
6088                 if ((i & 3) == 3)
6089                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6090         }
6091
6092         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6093         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6094                 i40e_pf_disable_rss(pf);
6095                 return 0;
6096         }
6097         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6098                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6099                 /* Random default keys */
6100                 static uint32_t rss_key_default[] = {0x6b793944,
6101                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6102                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6103                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6104
6105                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6106                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6107                                                         sizeof(uint32_t);
6108         }
6109
6110         return i40e_hw_rss_hash_set(pf, &rss_conf);
6111 }
6112
6113 static int
6114 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6115                                struct rte_eth_tunnel_filter_conf *filter)
6116 {
6117         if (pf == NULL || filter == NULL) {
6118                 PMD_DRV_LOG(ERR, "Invalid parameter");
6119                 return -EINVAL;
6120         }
6121
6122         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6123                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6124                 return -EINVAL;
6125         }
6126
6127         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6128                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6129                 return -EINVAL;
6130         }
6131
6132         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6133                 (is_zero_ether_addr(filter->outer_mac))) {
6134                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6135                 return -EINVAL;
6136         }
6137
6138         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6139                 (is_zero_ether_addr(filter->inner_mac))) {
6140                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6141                 return -EINVAL;
6142         }
6143
6144         return 0;
6145 }
6146
6147 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6148 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6149 static int
6150 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6151 {
6152         uint32_t val, reg;
6153         int ret = -EINVAL;
6154
6155         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6156         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6157
6158         if (len == 3) {
6159                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6160         } else if (len == 4) {
6161                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6162         } else {
6163                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6164                 return ret;
6165         }
6166
6167         if (reg != val) {
6168                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6169                                                    reg, NULL);
6170                 if (ret != 0)
6171                         return ret;
6172         } else {
6173                 ret = 0;
6174         }
6175         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6176                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6177
6178         return ret;
6179 }
6180
6181 static int
6182 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6183 {
6184         int ret = -EINVAL;
6185
6186         if (!hw || !cfg)
6187                 return -EINVAL;
6188
6189         switch (cfg->cfg_type) {
6190         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6191                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6192                 break;
6193         default:
6194                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6195                 break;
6196         }
6197
6198         return ret;
6199 }
6200
6201 static int
6202 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6203                                enum rte_filter_op filter_op,
6204                                void *arg)
6205 {
6206         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6207         int ret = I40E_ERR_PARAM;
6208
6209         switch (filter_op) {
6210         case RTE_ETH_FILTER_SET:
6211                 ret = i40e_dev_global_config_set(hw,
6212                         (struct rte_eth_global_cfg *)arg);
6213                 break;
6214         default:
6215                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6216                 break;
6217         }
6218
6219         return ret;
6220 }
6221
6222 static int
6223 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6224                           enum rte_filter_op filter_op,
6225                           void *arg)
6226 {
6227         struct rte_eth_tunnel_filter_conf *filter;
6228         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6229         int ret = I40E_SUCCESS;
6230
6231         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6232
6233         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6234                 return I40E_ERR_PARAM;
6235
6236         switch (filter_op) {
6237         case RTE_ETH_FILTER_NOP:
6238                 if (!(pf->flags & I40E_FLAG_VXLAN))
6239                         ret = I40E_NOT_SUPPORTED;
6240                 break;
6241         case RTE_ETH_FILTER_ADD:
6242                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6243                 break;
6244         case RTE_ETH_FILTER_DELETE:
6245                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6246                 break;
6247         default:
6248                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6249                 ret = I40E_ERR_PARAM;
6250                 break;
6251         }
6252
6253         return ret;
6254 }
6255
6256 static int
6257 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6258 {
6259         int ret = 0;
6260         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6261
6262         /* RSS setup */
6263         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6264                 ret = i40e_pf_config_rss(pf);
6265         else
6266                 i40e_pf_disable_rss(pf);
6267
6268         return ret;
6269 }
6270
6271 /* Get the symmetric hash enable configurations per port */
6272 static void
6273 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6274 {
6275         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6276
6277         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6278 }
6279
6280 /* Set the symmetric hash enable configurations per port */
6281 static void
6282 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6283 {
6284         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6285
6286         if (enable > 0) {
6287                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6288                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6289                                                         "been enabled");
6290                         return;
6291                 }
6292                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6293         } else {
6294                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6295                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6296                                                         "been disabled");
6297                         return;
6298                 }
6299                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6300         }
6301         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
6302         I40E_WRITE_FLUSH(hw);
6303 }
6304
6305 /*
6306  * Get global configurations of hash function type and symmetric hash enable
6307  * per flow type (pctype). Note that global configuration means it affects all
6308  * the ports on the same NIC.
6309  */
6310 static int
6311 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6312                                    struct rte_eth_hash_global_conf *g_cfg)
6313 {
6314         uint32_t reg, mask = I40E_FLOW_TYPES;
6315         uint16_t i;
6316         enum i40e_filter_pctype pctype;
6317
6318         memset(g_cfg, 0, sizeof(*g_cfg));
6319         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6320         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6321                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6322         else
6323                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6324         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6325                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6326
6327         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6328                 if (!(mask & (1UL << i)))
6329                         continue;
6330                 mask &= ~(1UL << i);
6331                 /* Bit set indicats the coresponding flow type is supported */
6332                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6333                 pctype = i40e_flowtype_to_pctype(i);
6334                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
6335                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6336                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6337         }
6338
6339         return 0;
6340 }
6341
6342 static int
6343 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6344 {
6345         uint32_t i;
6346         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6347
6348         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6349                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6350                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6351                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6352                                                 g_cfg->hash_func);
6353                 return -EINVAL;
6354         }
6355
6356         /*
6357          * As i40e supports less than 32 flow types, only first 32 bits need to
6358          * be checked.
6359          */
6360         mask0 = g_cfg->valid_bit_mask[0];
6361         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6362                 if (i == 0) {
6363                         /* Check if any unsupported flow type configured */
6364                         if ((mask0 | i40e_mask) ^ i40e_mask)
6365                                 goto mask_err;
6366                 } else {
6367                         if (g_cfg->valid_bit_mask[i])
6368                                 goto mask_err;
6369                 }
6370         }
6371
6372         return 0;
6373
6374 mask_err:
6375         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6376
6377         return -EINVAL;
6378 }
6379
6380 /*
6381  * Set global configurations of hash function type and symmetric hash enable
6382  * per flow type (pctype). Note any modifying global configuration will affect
6383  * all the ports on the same NIC.
6384  */
6385 static int
6386 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6387                                    struct rte_eth_hash_global_conf *g_cfg)
6388 {
6389         int ret;
6390         uint16_t i;
6391         uint32_t reg;
6392         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6393         enum i40e_filter_pctype pctype;
6394
6395         /* Check the input parameters */
6396         ret = i40e_hash_global_config_check(g_cfg);
6397         if (ret < 0)
6398                 return ret;
6399
6400         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6401                 if (!(mask0 & (1UL << i)))
6402                         continue;
6403                 mask0 &= ~(1UL << i);
6404                 pctype = i40e_flowtype_to_pctype(i);
6405                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6406                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6407                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
6408         }
6409
6410         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6411         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6412                 /* Toeplitz */
6413                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6414                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6415                                                                 "Toeplitz");
6416                         goto out;
6417                 }
6418                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6419         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6420                 /* Simple XOR */
6421                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6422                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6423                                                         "Simple XOR");
6424                         goto out;
6425                 }
6426                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6427         } else
6428                 /* Use the default, and keep it as it is */
6429                 goto out;
6430
6431         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6432
6433 out:
6434         I40E_WRITE_FLUSH(hw);
6435
6436         return 0;
6437 }
6438
6439 /**
6440  * Valid input sets for hash and flow director filters per PCTYPE
6441  */
6442 static uint64_t
6443 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6444                 enum rte_filter_type filter)
6445 {
6446         uint64_t valid;
6447
6448         static const uint64_t valid_hash_inset_table[] = {
6449                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6450                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6451                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6452                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6453                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6454                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6455                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6456                         I40E_INSET_FLEX_PAYLOAD,
6457                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6458                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6459                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6460                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6461                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6462                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6463                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6464                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6465                         I40E_INSET_FLEX_PAYLOAD,
6466                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6467                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6468                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6469                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6470                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6471                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6472                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6473                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6474                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6475                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6476                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6477                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6478                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6479                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6480                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6481                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6482                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6483                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6484                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6485                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6486                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6487                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6488                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6489                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6490                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6491                         I40E_INSET_FLEX_PAYLOAD,
6492                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6493                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6494                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6495                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6496                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6497                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6498                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6499                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6500                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6501                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6502                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6503                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6504                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6505                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6506                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6507                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6508                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6509                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6510                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6511                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6512                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6513                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6514                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6515                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6516                         I40E_INSET_FLEX_PAYLOAD,
6517                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6518                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6519                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6520                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6521                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6522                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6523                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6524                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6525                         I40E_INSET_FLEX_PAYLOAD,
6526                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6527                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6528                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6529                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6530                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6531                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6532                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6533                         I40E_INSET_FLEX_PAYLOAD,
6534                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6535                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6536                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6537                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6538                         I40E_INSET_FLEX_PAYLOAD,
6539         };
6540
6541         /**
6542          * Flow director supports only fields defined in
6543          * union rte_eth_fdir_flow.
6544          */
6545         static const uint64_t valid_fdir_inset_table[] = {
6546                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6547                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6548                 I40E_INSET_FLEX_PAYLOAD,
6549                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6550                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6551                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6552                 I40E_INSET_FLEX_PAYLOAD,
6553                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6554                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6555                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6556                 I40E_INSET_FLEX_PAYLOAD,
6557                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6558                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6559                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6560                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6561                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6562                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6563                 I40E_INSET_FLEX_PAYLOAD,
6564                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6565                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6566                 I40E_INSET_FLEX_PAYLOAD,
6567                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6568                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6569                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6570                 I40E_INSET_FLEX_PAYLOAD,
6571                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6572                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6573                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6574                 I40E_INSET_FLEX_PAYLOAD,
6575                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6576                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6577                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6578                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6579                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6580                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6581                 I40E_INSET_FLEX_PAYLOAD,
6582                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6583                 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6584         };
6585
6586         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6587                 return 0;
6588         if (filter == RTE_ETH_FILTER_HASH)
6589                 valid = valid_hash_inset_table[pctype];
6590         else
6591                 valid = valid_fdir_inset_table[pctype];
6592
6593         return valid;
6594 }
6595
6596 /**
6597  * Validate if the input set is allowed for a specific PCTYPE
6598  */
6599 static int
6600 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6601                 enum rte_filter_type filter, uint64_t inset)
6602 {
6603         uint64_t valid;
6604
6605         valid = i40e_get_valid_input_set(pctype, filter);
6606         if (inset & (~valid))
6607                 return -EINVAL;
6608
6609         return 0;
6610 }
6611
6612 /* default input set fields combination per pctype */
6613 static uint64_t
6614 i40e_get_default_input_set(uint16_t pctype)
6615 {
6616         static const uint64_t default_inset_table[] = {
6617                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6618                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6619                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6620                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6621                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6622                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6623                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6624                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6625                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6626                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6627                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6628                         I40E_INSET_SCTP_VT,
6629                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6630                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6631                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6632                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6633                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6634                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6635                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6636                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6637                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6638                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6639                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6640                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6641                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6642                         I40E_INSET_SCTP_VT,
6643                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6644                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6645                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6646                         I40E_INSET_LAST_ETHER_TYPE,
6647         };
6648
6649         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6650                 return 0;
6651
6652         return default_inset_table[pctype];
6653 }
6654
6655 /**
6656  * Parse the input set from index to logical bit masks
6657  */
6658 static int
6659 i40e_parse_input_set(uint64_t *inset,
6660                      enum i40e_filter_pctype pctype,
6661                      enum rte_eth_input_set_field *field,
6662                      uint16_t size)
6663 {
6664         uint16_t i, j;
6665         int ret = -EINVAL;
6666
6667         static const struct {
6668                 enum rte_eth_input_set_field field;
6669                 uint64_t inset;
6670         } inset_convert_table[] = {
6671                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6672                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6673                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6674                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6675                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6676                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6677                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6678                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6679                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6680                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6681                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6682                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6683                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6684                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6685                         I40E_INSET_IPV6_NEXT_HDR},
6686                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6687                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6688                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6689                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6690                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6691                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6692                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6693                         I40E_INSET_SCTP_VT},
6694                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6695                         I40E_INSET_TUNNEL_DMAC},
6696                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6697                         I40E_INSET_VLAN_TUNNEL},
6698                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6699                         I40E_INSET_TUNNEL_ID},
6700                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6701                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6702                         I40E_INSET_FLEX_PAYLOAD_W1},
6703                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6704                         I40E_INSET_FLEX_PAYLOAD_W2},
6705                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6706                         I40E_INSET_FLEX_PAYLOAD_W3},
6707                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6708                         I40E_INSET_FLEX_PAYLOAD_W4},
6709                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6710                         I40E_INSET_FLEX_PAYLOAD_W5},
6711                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6712                         I40E_INSET_FLEX_PAYLOAD_W6},
6713                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6714                         I40E_INSET_FLEX_PAYLOAD_W7},
6715                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6716                         I40E_INSET_FLEX_PAYLOAD_W8},
6717         };
6718
6719         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6720                 return ret;
6721
6722         /* Only one item allowed for default or all */
6723         if (size == 1) {
6724                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6725                         *inset = i40e_get_default_input_set(pctype);
6726                         return 0;
6727                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6728                         *inset = I40E_INSET_NONE;
6729                         return 0;
6730                 }
6731         }
6732
6733         for (i = 0, *inset = 0; i < size; i++) {
6734                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6735                         if (field[i] == inset_convert_table[j].field) {
6736                                 *inset |= inset_convert_table[j].inset;
6737                                 break;
6738                         }
6739                 }
6740
6741                 /* It contains unsupported input set, return immediately */
6742                 if (j == RTE_DIM(inset_convert_table))
6743                         return ret;
6744         }
6745
6746         return 0;
6747 }
6748
6749 /**
6750  * Translate the input set from bit masks to register aware bit masks
6751  * and vice versa
6752  */
6753 static uint64_t
6754 i40e_translate_input_set_reg(uint64_t input)
6755 {
6756         uint64_t val = 0;
6757         uint16_t i;
6758
6759         static const struct {
6760                 uint64_t inset;
6761                 uint64_t inset_reg;
6762         } inset_map[] = {
6763                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6764                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6765                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6766                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6767                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6768                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6769                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6770                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6771                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6772                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6773                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6774                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6775                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6776                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6777                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6778                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6779                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6780                 {I40E_INSET_TUNNEL_DMAC,
6781                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6782                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6783                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6784                 {I40E_INSET_TUNNEL_SRC_PORT,
6785                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6786                 {I40E_INSET_TUNNEL_DST_PORT,
6787                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6788                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6789                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6790                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6791                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6792                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6793                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6794                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6795                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6796                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6797         };
6798
6799         if (input == 0)
6800                 return val;
6801
6802         /* Translate input set to register aware inset */
6803         for (i = 0; i < RTE_DIM(inset_map); i++) {
6804                 if (input & inset_map[i].inset)
6805                         val |= inset_map[i].inset_reg;
6806         }
6807
6808         return val;
6809 }
6810
6811 static uint8_t
6812 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6813 {
6814         uint8_t i, idx = 0;
6815
6816         static const struct {
6817                 uint64_t inset;
6818                 uint32_t mask;
6819         } inset_mask_map[] = {
6820                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6821                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6822                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6823                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6824         };
6825
6826         if (!inset || !mask || !nb_elem)
6827                 return 0;
6828
6829         if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6830                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6831                         mask[i] = 0;
6832                 return I40E_INSET_MASK_NUM_REG;
6833         }
6834
6835         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6836                 if (idx >= nb_elem)
6837                         break;
6838                 if (inset & inset_mask_map[i].inset) {
6839                         mask[idx] = inset_mask_map[i].mask;
6840                         idx++;
6841                 }
6842         }
6843
6844         return idx;
6845 }
6846
6847 static uint64_t
6848 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
6849                             enum i40e_filter_pctype pctype)
6850 {
6851         uint64_t reg = 0;
6852
6853         if (filter == RTE_ETH_FILTER_HASH) {
6854                 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
6855                 reg <<= I40E_32_BIT_WIDTH;
6856                 reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
6857         } else if (filter == RTE_ETH_FILTER_FDIR) {
6858                 reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
6859                 reg <<= I40E_32_BIT_WIDTH;
6860                 reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
6861         }
6862
6863         return reg;
6864 }
6865
6866 static void
6867 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
6868 {
6869         uint32_t reg = I40E_READ_REG(hw, addr);
6870
6871         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
6872         if (reg != val)
6873                 I40E_WRITE_REG(hw, addr, val);
6874         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
6875                     (uint32_t)I40E_READ_REG(hw, addr));
6876 }
6877
6878 static int
6879 i40e_set_hash_inset_mask(struct i40e_hw *hw,
6880                          enum i40e_filter_pctype pctype,
6881                          enum rte_filter_input_set_op op,
6882                          uint32_t *mask_reg,
6883                          uint8_t num)
6884 {
6885         uint32_t reg;
6886         uint8_t i;
6887
6888         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6889                 return -EINVAL;
6890
6891         if (op == RTE_ETH_INPUT_SET_SELECT) {
6892                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6893                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6894                                              0);
6895                         if (i >= num)
6896                                 continue;
6897                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6898                                              mask_reg[i]);
6899                 }
6900         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6901                 uint8_t j, count = 0;
6902
6903                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6904                         reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
6905                         if (reg & I40E_GLQF_HASH_MSK_FIELD)
6906                                 count++;
6907                 }
6908                 if (count + num > I40E_INSET_MASK_NUM_REG)
6909                         return -EINVAL;
6910
6911                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6912                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6913                                              mask_reg[j]);
6914         }
6915
6916         return 0;
6917 }
6918
6919 static int
6920 i40e_set_fd_inset_mask(struct i40e_hw *hw,
6921                        enum i40e_filter_pctype pctype,
6922                        enum rte_filter_input_set_op op,
6923                        uint32_t *mask_reg,
6924                        uint8_t num)
6925 {
6926         uint32_t reg;
6927         uint8_t i;
6928
6929         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6930                 return -EINVAL;
6931
6932         if (op == RTE_ETH_INPUT_SET_SELECT) {
6933                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6934                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6935                                              0);
6936                         if (i >= num)
6937                                 continue;
6938                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6939                                              mask_reg[i]);
6940                 }
6941         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6942                 uint8_t j, count = 0;
6943
6944                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6945                         reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
6946                         if (reg & I40E_GLQF_FD_MSK_FIELD)
6947                                 count++;
6948                 }
6949                 if (count + num > I40E_INSET_MASK_NUM_REG)
6950                         return -EINVAL;
6951
6952                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6953                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6954                                              mask_reg[j]);
6955         }
6956
6957         return 0;
6958 }
6959
6960 int
6961 i40e_filter_inset_select(struct i40e_hw *hw,
6962                          struct rte_eth_input_set_conf *conf,
6963                          enum rte_filter_type filter)
6964 {
6965         enum i40e_filter_pctype pctype;
6966         uint64_t inset_reg = 0, input_set;
6967         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
6968         uint8_t num;
6969         int ret;
6970
6971         if (!hw || !conf) {
6972                 PMD_DRV_LOG(ERR, "Invalid pointer");
6973                 return -EFAULT;
6974         }
6975
6976         pctype = i40e_flowtype_to_pctype(conf->flow_type);
6977         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
6978                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
6979                             conf->flow_type);
6980                 return -EINVAL;
6981         }
6982         if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
6983                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6984                 return -EINVAL;
6985         }
6986
6987         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
6988                                    conf->inset_size);
6989         if (ret) {
6990                 PMD_DRV_LOG(ERR, "Failed to parse input set");
6991                 return -EINVAL;
6992         }
6993         if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
6994                 PMD_DRV_LOG(ERR, "Invalid input set");
6995                 return -EINVAL;
6996         }
6997
6998         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
6999                 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
7000         } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
7001                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7002                 return -EINVAL;
7003         }
7004         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7005                                            I40E_INSET_MASK_NUM_REG);
7006         inset_reg |= i40e_translate_input_set_reg(input_set);
7007
7008         if (filter == RTE_ETH_FILTER_HASH) {
7009                 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
7010                                                num);
7011                 if (ret)
7012                         return -EINVAL;
7013
7014                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7015                                       (uint32_t)(inset_reg & UINT32_MAX));
7016                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7017                                      (uint32_t)((inset_reg >>
7018                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7019         } else if (filter == RTE_ETH_FILTER_FDIR) {
7020                 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
7021                                              num);
7022                 if (ret)
7023                         return -EINVAL;
7024
7025                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7026                                       (uint32_t)(inset_reg & UINT32_MAX));
7027                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7028                                      (uint32_t)((inset_reg >>
7029                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7030         } else {
7031                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7032                 return -EINVAL;
7033         }
7034         I40E_WRITE_FLUSH(hw);
7035
7036         return 0;
7037 }
7038
7039 static int
7040 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7041 {
7042         int ret = 0;
7043
7044         if (!hw || !info) {
7045                 PMD_DRV_LOG(ERR, "Invalid pointer");
7046                 return -EFAULT;
7047         }
7048
7049         switch (info->info_type) {
7050         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7051                 i40e_get_symmetric_hash_enable_per_port(hw,
7052                                         &(info->info.enable));
7053                 break;
7054         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7055                 ret = i40e_get_hash_filter_global_config(hw,
7056                                 &(info->info.global_conf));
7057                 break;
7058         default:
7059                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7060                                                         info->info_type);
7061                 ret = -EINVAL;
7062                 break;
7063         }
7064
7065         return ret;
7066 }
7067
7068 static int
7069 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7070 {
7071         int ret = 0;
7072
7073         if (!hw || !info) {
7074                 PMD_DRV_LOG(ERR, "Invalid pointer");
7075                 return -EFAULT;
7076         }
7077
7078         switch (info->info_type) {
7079         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7080                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7081                 break;
7082         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7083                 ret = i40e_set_hash_filter_global_config(hw,
7084                                 &(info->info.global_conf));
7085                 break;
7086         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7087                 ret = i40e_filter_inset_select(hw,
7088                                                &(info->info.input_set_conf),
7089                                                RTE_ETH_FILTER_HASH);
7090                 break;
7091
7092         default:
7093                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7094                                                         info->info_type);
7095                 ret = -EINVAL;
7096                 break;
7097         }
7098
7099         return ret;
7100 }
7101
7102 /* Operations for hash function */
7103 static int
7104 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7105                       enum rte_filter_op filter_op,
7106                       void *arg)
7107 {
7108         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7109         int ret = 0;
7110
7111         switch (filter_op) {
7112         case RTE_ETH_FILTER_NOP:
7113                 break;
7114         case RTE_ETH_FILTER_GET:
7115                 ret = i40e_hash_filter_get(hw,
7116                         (struct rte_eth_hash_filter_info *)arg);
7117                 break;
7118         case RTE_ETH_FILTER_SET:
7119                 ret = i40e_hash_filter_set(hw,
7120                         (struct rte_eth_hash_filter_info *)arg);
7121                 break;
7122         default:
7123                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7124                                                                 filter_op);
7125                 ret = -ENOTSUP;
7126                 break;
7127         }
7128
7129         return ret;
7130 }
7131
7132 /*
7133  * Configure ethertype filter, which can director packet by filtering
7134  * with mac address and ether_type or only ether_type
7135  */
7136 static int
7137 i40e_ethertype_filter_set(struct i40e_pf *pf,
7138                         struct rte_eth_ethertype_filter *filter,
7139                         bool add)
7140 {
7141         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7142         struct i40e_control_filter_stats stats;
7143         uint16_t flags = 0;
7144         int ret;
7145
7146         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7147                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7148                 return -EINVAL;
7149         }
7150         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7151                 filter->ether_type == ETHER_TYPE_IPv6) {
7152                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7153                         " control packet filter.", filter->ether_type);
7154                 return -EINVAL;
7155         }
7156         if (filter->ether_type == ETHER_TYPE_VLAN)
7157                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7158                         " not supported.");
7159
7160         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7161                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7162         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7163                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7164         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7165
7166         memset(&stats, 0, sizeof(stats));
7167         ret = i40e_aq_add_rem_control_packet_filter(hw,
7168                         filter->mac_addr.addr_bytes,
7169                         filter->ether_type, flags,
7170                         pf->main_vsi->seid,
7171                         filter->queue, add, &stats, NULL);
7172
7173         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7174                          " mac_etype_used = %u, etype_used = %u,"
7175                          " mac_etype_free = %u, etype_free = %u\n",
7176                          ret, stats.mac_etype_used, stats.etype_used,
7177                          stats.mac_etype_free, stats.etype_free);
7178         if (ret < 0)
7179                 return -ENOSYS;
7180         return 0;
7181 }
7182
7183 /*
7184  * Handle operations for ethertype filter.
7185  */
7186 static int
7187 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7188                                 enum rte_filter_op filter_op,
7189                                 void *arg)
7190 {
7191         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7192         int ret = 0;
7193
7194         if (filter_op == RTE_ETH_FILTER_NOP)
7195                 return ret;
7196
7197         if (arg == NULL) {
7198                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7199                             filter_op);
7200                 return -EINVAL;
7201         }
7202
7203         switch (filter_op) {
7204         case RTE_ETH_FILTER_ADD:
7205                 ret = i40e_ethertype_filter_set(pf,
7206                         (struct rte_eth_ethertype_filter *)arg,
7207                         TRUE);
7208                 break;
7209         case RTE_ETH_FILTER_DELETE:
7210                 ret = i40e_ethertype_filter_set(pf,
7211                         (struct rte_eth_ethertype_filter *)arg,
7212                         FALSE);
7213                 break;
7214         default:
7215                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7216                 ret = -ENOSYS;
7217                 break;
7218         }
7219         return ret;
7220 }
7221
7222 static int
7223 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7224                      enum rte_filter_type filter_type,
7225                      enum rte_filter_op filter_op,
7226                      void *arg)
7227 {
7228         int ret = 0;
7229
7230         if (dev == NULL)
7231                 return -EINVAL;
7232
7233         switch (filter_type) {
7234         case RTE_ETH_FILTER_NONE:
7235                 /* For global configuration */
7236                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7237                 break;
7238         case RTE_ETH_FILTER_HASH:
7239                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7240                 break;
7241         case RTE_ETH_FILTER_MACVLAN:
7242                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7243                 break;
7244         case RTE_ETH_FILTER_ETHERTYPE:
7245                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7246                 break;
7247         case RTE_ETH_FILTER_TUNNEL:
7248                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7249                 break;
7250         case RTE_ETH_FILTER_FDIR:
7251                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7252                 break;
7253         default:
7254                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7255                                                         filter_type);
7256                 ret = -EINVAL;
7257                 break;
7258         }
7259
7260         return ret;
7261 }
7262
7263 /*
7264  * As some registers wouldn't be reset unless a global hardware reset,
7265  * hardware initialization is needed to put those registers into an
7266  * expected initial state.
7267  */
7268 static void
7269 i40e_hw_init(struct i40e_hw *hw)
7270 {
7271         /* clear the PF Queue Filter control register */
7272         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
7273
7274         /* Disable symmetric hash per port */
7275         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7276 }
7277
7278 enum i40e_filter_pctype
7279 i40e_flowtype_to_pctype(uint16_t flow_type)
7280 {
7281         static const enum i40e_filter_pctype pctype_table[] = {
7282                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7283                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7284                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7285                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7286                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7287                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7288                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7289                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7290                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7291                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7292                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7293                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7294                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7295                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7296                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7297                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7298                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7299                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7300                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7301         };
7302
7303         return pctype_table[flow_type];
7304 }
7305
7306 uint16_t
7307 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7308 {
7309         static const uint16_t flowtype_table[] = {
7310                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7311                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7312                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7313                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7314                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7315                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7316                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7317                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7318                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7319                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7320                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7321                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7322                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7323                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7324                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7325                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7326                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7327                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7328                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7329         };
7330
7331         return flowtype_table[pctype];
7332 }
7333
7334 /*
7335  * On X710, performance number is far from the expectation on recent firmware
7336  * versions; on XL710, performance number is also far from the expectation on
7337  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7338  * mode is enabled and port MAC address is equal to the packet destination MAC
7339  * address. The fix for this issue may not be integrated in the following
7340  * firmware version. So the workaround in software driver is needed. It needs
7341  * to modify the initial values of 3 internal only registers for both X710 and
7342  * XL710. Note that the values for X710 or XL710 could be different, and the
7343  * workaround can be removed when it is fixed in firmware in the future.
7344  */
7345
7346 /* For both X710 and XL710 */
7347 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7348 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7349
7350 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7351 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7352
7353 /* For X710 */
7354 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7355 /* For XL710 */
7356 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7357 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7358
7359 static void
7360 i40e_configure_registers(struct i40e_hw *hw)
7361 {
7362         static struct {
7363                 uint32_t addr;
7364                 uint64_t val;
7365         } reg_table[] = {
7366                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7367                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7368                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7369         };
7370         uint64_t reg;
7371         uint32_t i;
7372         int ret;
7373
7374         for (i = 0; i < RTE_DIM(reg_table); i++) {
7375                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7376                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7377                                 reg_table[i].val =
7378                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7379                         else /* For X710 */
7380                                 reg_table[i].val =
7381                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7382                 }
7383
7384                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7385                                                         &reg, NULL);
7386                 if (ret < 0) {
7387                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7388                                                         reg_table[i].addr);
7389                         break;
7390                 }
7391                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7392                                                 reg_table[i].addr, reg);
7393                 if (reg == reg_table[i].val)
7394                         continue;
7395
7396                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7397                                                 reg_table[i].val, NULL);
7398                 if (ret < 0) {
7399                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7400                                 "address of 0x%"PRIx32, reg_table[i].val,
7401                                                         reg_table[i].addr);
7402                         break;
7403                 }
7404                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7405                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7406         }
7407 }
7408
7409 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7410 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7411 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7412 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7413 static int
7414 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7415 {
7416         uint32_t reg;
7417         int ret;
7418
7419         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7420                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7421                 return -EINVAL;
7422         }
7423
7424         /* Configure for double VLAN RX stripping */
7425         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7426         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7427                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7428                 ret = i40e_aq_debug_write_register(hw,
7429                                                    I40E_VSI_TSR(vsi->vsi_id),
7430                                                    reg, NULL);
7431                 if (ret < 0) {
7432                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7433                                     vsi->vsi_id);
7434                         return I40E_ERR_CONFIG;
7435                 }
7436         }
7437
7438         /* Configure for double VLAN TX insertion */
7439         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7440         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7441                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7442                 ret = i40e_aq_debug_write_register(hw,
7443                                                    I40E_VSI_L2TAGSTXVALID(
7444                                                    vsi->vsi_id), reg, NULL);
7445                 if (ret < 0) {
7446                         PMD_DRV_LOG(ERR, "Failed to update "
7447                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7448                         return I40E_ERR_CONFIG;
7449                 }
7450         }
7451
7452         return 0;
7453 }
7454
7455 /**
7456  * i40e_aq_add_mirror_rule
7457  * @hw: pointer to the hardware structure
7458  * @seid: VEB seid to add mirror rule to
7459  * @dst_id: destination vsi seid
7460  * @entries: Buffer which contains the entities to be mirrored
7461  * @count: number of entities contained in the buffer
7462  * @rule_id:the rule_id of the rule to be added
7463  *
7464  * Add a mirror rule for a given veb.
7465  *
7466  **/
7467 static enum i40e_status_code
7468 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7469                         uint16_t seid, uint16_t dst_id,
7470                         uint16_t rule_type, uint16_t *entries,
7471                         uint16_t count, uint16_t *rule_id)
7472 {
7473         struct i40e_aq_desc desc;
7474         struct i40e_aqc_add_delete_mirror_rule cmd;
7475         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7476                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7477                 &desc.params.raw;
7478         uint16_t buff_len;
7479         enum i40e_status_code status;
7480
7481         i40e_fill_default_direct_cmd_desc(&desc,
7482                                           i40e_aqc_opc_add_mirror_rule);
7483         memset(&cmd, 0, sizeof(cmd));
7484
7485         buff_len = sizeof(uint16_t) * count;
7486         desc.datalen = rte_cpu_to_le_16(buff_len);
7487         if (buff_len > 0)
7488                 desc.flags |= rte_cpu_to_le_16(
7489                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7490         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7491                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7492         cmd.num_entries = rte_cpu_to_le_16(count);
7493         cmd.seid = rte_cpu_to_le_16(seid);
7494         cmd.destination = rte_cpu_to_le_16(dst_id);
7495
7496         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7497         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7498         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7499                          "rule_id = %u"
7500                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7501                          hw->aq.asq_last_status, resp->rule_id,
7502                          resp->mirror_rules_used, resp->mirror_rules_free);
7503         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7504
7505         return status;
7506 }
7507
7508 /**
7509  * i40e_aq_del_mirror_rule
7510  * @hw: pointer to the hardware structure
7511  * @seid: VEB seid to add mirror rule to
7512  * @entries: Buffer which contains the entities to be mirrored
7513  * @count: number of entities contained in the buffer
7514  * @rule_id:the rule_id of the rule to be delete
7515  *
7516  * Delete a mirror rule for a given veb.
7517  *
7518  **/
7519 static enum i40e_status_code
7520 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7521                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7522                 uint16_t count, uint16_t rule_id)
7523 {
7524         struct i40e_aq_desc desc;
7525         struct i40e_aqc_add_delete_mirror_rule cmd;
7526         uint16_t buff_len = 0;
7527         enum i40e_status_code status;
7528         void *buff = NULL;
7529
7530         i40e_fill_default_direct_cmd_desc(&desc,
7531                                           i40e_aqc_opc_delete_mirror_rule);
7532         memset(&cmd, 0, sizeof(cmd));
7533         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7534                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7535                                                           I40E_AQ_FLAG_RD));
7536                 cmd.num_entries = count;
7537                 buff_len = sizeof(uint16_t) * count;
7538                 desc.datalen = rte_cpu_to_le_16(buff_len);
7539                 buff = (void *)entries;
7540         } else
7541                 /* rule id is filled in destination field for deleting mirror rule */
7542                 cmd.destination = rte_cpu_to_le_16(rule_id);
7543
7544         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7545                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7546         cmd.seid = rte_cpu_to_le_16(seid);
7547
7548         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7549         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7550
7551         return status;
7552 }
7553
7554 /**
7555  * i40e_mirror_rule_set
7556  * @dev: pointer to the hardware structure
7557  * @mirror_conf: mirror rule info
7558  * @sw_id: mirror rule's sw_id
7559  * @on: enable/disable
7560  *
7561  * set a mirror rule.
7562  *
7563  **/
7564 static int
7565 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7566                         struct rte_eth_mirror_conf *mirror_conf,
7567                         uint8_t sw_id, uint8_t on)
7568 {
7569         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7570         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7571         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7572         struct i40e_mirror_rule *parent = NULL;
7573         uint16_t seid, dst_seid, rule_id;
7574         uint16_t i, j = 0;
7575         int ret;
7576
7577         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7578
7579         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7580                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7581                         " without veb or vfs.");
7582                 return -ENOSYS;
7583         }
7584         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7585                 PMD_DRV_LOG(ERR, "mirror table is full.");
7586                 return -ENOSPC;
7587         }
7588         if (mirror_conf->dst_pool > pf->vf_num) {
7589                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7590                                  mirror_conf->dst_pool);
7591                 return -EINVAL;
7592         }
7593
7594         seid = pf->main_vsi->veb->seid;
7595
7596         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7597                 if (sw_id <= it->index) {
7598                         mirr_rule = it;
7599                         break;
7600                 }
7601                 parent = it;
7602         }
7603         if (mirr_rule && sw_id == mirr_rule->index) {
7604                 if (on) {
7605                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7606                         return -EEXIST;
7607                 } else {
7608                         ret = i40e_aq_del_mirror_rule(hw, seid,
7609                                         mirr_rule->rule_type,
7610                                         mirr_rule->entries,
7611                                         mirr_rule->num_entries, mirr_rule->id);
7612                         if (ret < 0) {
7613                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7614                                                    " ret = %d, aq_err = %d.",
7615                                                    ret, hw->aq.asq_last_status);
7616                                 return -ENOSYS;
7617                         }
7618                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7619                         rte_free(mirr_rule);
7620                         pf->nb_mirror_rule--;
7621                         return 0;
7622                 }
7623         } else if (!on) {
7624                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7625                 return -ENOENT;
7626         }
7627
7628         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7629                                 sizeof(struct i40e_mirror_rule) , 0);
7630         if (!mirr_rule) {
7631                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7632                 return I40E_ERR_NO_MEMORY;
7633         }
7634         switch (mirror_conf->rule_type) {
7635         case ETH_MIRROR_VLAN:
7636                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7637                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7638                                 mirr_rule->entries[j] =
7639                                         mirror_conf->vlan.vlan_id[i];
7640                                 j++;
7641                         }
7642                 }
7643                 if (j == 0) {
7644                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7645                         rte_free(mirr_rule);
7646                         return -EINVAL;
7647                 }
7648                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7649                 break;
7650         case ETH_MIRROR_VIRTUAL_POOL_UP:
7651         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7652                 /* check if the specified pool bit is out of range */
7653                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7654                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7655                         rte_free(mirr_rule);
7656                         return -EINVAL;
7657                 }
7658                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7659                         if (mirror_conf->pool_mask & (1ULL << i)) {
7660                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7661                                 j++;
7662                         }
7663                 }
7664                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7665                         /* add pf vsi to entries */
7666                         mirr_rule->entries[j] = pf->main_vsi_seid;
7667                         j++;
7668                 }
7669                 if (j == 0) {
7670                         PMD_DRV_LOG(ERR, "pool is not specified.");
7671                         rte_free(mirr_rule);
7672                         return -EINVAL;
7673                 }
7674                 /* egress and ingress in aq commands means from switch but not port */
7675                 mirr_rule->rule_type =
7676                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7677                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7678                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7679                 break;
7680         case ETH_MIRROR_UPLINK_PORT:
7681                 /* egress and ingress in aq commands means from switch but not port*/
7682                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7683                 break;
7684         case ETH_MIRROR_DOWNLINK_PORT:
7685                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7686                 break;
7687         default:
7688                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7689                         mirror_conf->rule_type);
7690                 rte_free(mirr_rule);
7691                 return -EINVAL;
7692         }
7693
7694         /* If the dst_pool is equal to vf_num, consider it as PF */
7695         if (mirror_conf->dst_pool == pf->vf_num)
7696                 dst_seid = pf->main_vsi_seid;
7697         else
7698                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7699
7700         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7701                                       mirr_rule->rule_type, mirr_rule->entries,
7702                                       j, &rule_id);
7703         if (ret < 0) {
7704                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7705                                    " ret = %d, aq_err = %d.",
7706                                    ret, hw->aq.asq_last_status);
7707                 rte_free(mirr_rule);
7708                 return -ENOSYS;
7709         }
7710
7711         mirr_rule->index = sw_id;
7712         mirr_rule->num_entries = j;
7713         mirr_rule->id = rule_id;
7714         mirr_rule->dst_vsi_seid = dst_seid;
7715
7716         if (parent)
7717                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7718         else
7719                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7720
7721         pf->nb_mirror_rule++;
7722         return 0;
7723 }
7724
7725 /**
7726  * i40e_mirror_rule_reset
7727  * @dev: pointer to the device
7728  * @sw_id: mirror rule's sw_id
7729  *
7730  * reset a mirror rule.
7731  *
7732  **/
7733 static int
7734 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7735 {
7736         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7737         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7738         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7739         uint16_t seid;
7740         int ret;
7741
7742         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7743
7744         seid = pf->main_vsi->veb->seid;
7745
7746         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7747                 if (sw_id == it->index) {
7748                         mirr_rule = it;
7749                         break;
7750                 }
7751         }
7752         if (mirr_rule) {
7753                 ret = i40e_aq_del_mirror_rule(hw, seid,
7754                                 mirr_rule->rule_type,
7755                                 mirr_rule->entries,
7756                                 mirr_rule->num_entries, mirr_rule->id);
7757                 if (ret < 0) {
7758                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7759                                            " status = %d, aq_err = %d.",
7760                                            ret, hw->aq.asq_last_status);
7761                         return -ENOSYS;
7762                 }
7763                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7764                 rte_free(mirr_rule);
7765                 pf->nb_mirror_rule--;
7766         } else {
7767                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7768                 return -ENOENT;
7769         }
7770         return 0;
7771 }
7772
7773 static int
7774 i40e_timesync_enable(struct rte_eth_dev *dev)
7775 {
7776         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7777         struct rte_eth_link *link = &dev->data->dev_link;
7778         uint32_t tsync_ctl_l;
7779         uint32_t tsync_ctl_h;
7780         uint32_t tsync_inc_l;
7781         uint32_t tsync_inc_h;
7782
7783         switch (link->link_speed) {
7784         case ETH_LINK_SPEED_40G:
7785                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
7786                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
7787                 break;
7788         case ETH_LINK_SPEED_10G:
7789                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
7790                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
7791                 break;
7792         case ETH_LINK_SPEED_1000:
7793                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
7794                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
7795                 break;
7796         default:
7797                 tsync_inc_l = 0x0;
7798                 tsync_inc_h = 0x0;
7799         }
7800
7801         /* Clear timesync registers. */
7802         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7803         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7804         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
7805         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
7806         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
7807         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
7808         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7809
7810         /* Set the timesync increment value. */
7811         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
7812         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
7813
7814         /* Enable timestamping of PTP packets. */
7815         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7816         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
7817
7818         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7819         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
7820         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
7821
7822         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7823         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7824
7825         return 0;
7826 }
7827
7828 static int
7829 i40e_timesync_disable(struct rte_eth_dev *dev)
7830 {
7831         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7832         uint32_t tsync_ctl_l;
7833         uint32_t tsync_ctl_h;
7834
7835         /* Disable timestamping of transmitted PTP packets. */
7836         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7837         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
7838
7839         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7840         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
7841
7842         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7843         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7844
7845         /* Set the timesync increment value. */
7846         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7847         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7848
7849         return 0;
7850 }
7851
7852 static int
7853 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7854                                 struct timespec *timestamp, uint32_t flags)
7855 {
7856         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7857         uint32_t sync_status;
7858         uint32_t rx_stmpl;
7859         uint32_t rx_stmph;
7860         uint32_t index = flags & 0x03;
7861
7862         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
7863         if ((sync_status & (1 << index)) == 0)
7864                 return -EINVAL;
7865
7866         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7867         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
7868
7869         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
7870         timestamp->tv_nsec = 0;
7871
7872         return  0;
7873 }
7874
7875 static int
7876 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7877                                 struct timespec *timestamp)
7878 {
7879         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7880         uint32_t sync_status;
7881         uint32_t tx_stmpl;
7882         uint32_t tx_stmph;
7883
7884         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7885         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
7886                 return -EINVAL;
7887
7888         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
7889         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7890
7891         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
7892         timestamp->tv_nsec = 0;
7893
7894         return  0;
7895 }
7896
7897 /*
7898  * i40e_parse_dcb_configure - parse dcb configure from user
7899  * @dev: the device being configured
7900  * @dcb_cfg: pointer of the result of parse
7901  * @*tc_map: bit map of enabled traffic classes
7902  *
7903  * Returns 0 on success, negative value on failure
7904  */
7905 static int
7906 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
7907                          struct i40e_dcbx_config *dcb_cfg,
7908                          uint8_t *tc_map)
7909 {
7910         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
7911         uint8_t i, tc_bw, bw_lf;
7912
7913         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
7914
7915         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7916         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
7917                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
7918                 return -EINVAL;
7919         }
7920
7921         /* assume each tc has the same bw */
7922         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
7923         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7924                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
7925         /* to ensure the sum of tcbw is equal to 100 */
7926         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
7927         for (i = 0; i < bw_lf; i++)
7928                 dcb_cfg->etscfg.tcbwtable[i]++;
7929
7930         /* assume each tc has the same Transmission Selection Algorithm */
7931         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7932                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
7933
7934         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
7935                 dcb_cfg->etscfg.prioritytable[i] =
7936                                 dcb_rx_conf->dcb_tc[i];
7937
7938         /* FW needs one App to configure HW */
7939         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
7940         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
7941         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
7942         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
7943
7944         if (dcb_rx_conf->nb_tcs == 0)
7945                 *tc_map = 1; /* tc0 only */
7946         else
7947                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
7948
7949         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
7950                 dcb_cfg->pfc.willing = 0;
7951                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
7952                 dcb_cfg->pfc.pfcenable = *tc_map;
7953         }
7954         return 0;
7955 }
7956
7957 /*
7958  * i40e_vsi_get_bw_info - Query VSI BW Information
7959  * @vsi: the VSI being queried
7960  *
7961  * Returns 0 on success, negative value on failure
7962  */
7963 static enum i40e_status_code
7964 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
7965 {
7966         struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
7967         struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
7968         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7969         enum i40e_status_code ret;
7970         int i;
7971         uint32_t tc_bw_max;
7972
7973         /* Get the VSI level BW configuration */
7974         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
7975         if (ret) {
7976                 PMD_INIT_LOG(ERR,
7977                          "couldn't get PF vsi bw config, err %s aq_err %s\n",
7978                          i40e_stat_str(hw, ret),
7979                          i40e_aq_str(hw, hw->aq.asq_last_status));
7980                 return ret;
7981         }
7982
7983         /* Get the VSI level BW configuration per TC */
7984         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
7985                                                   NULL);
7986         if (ret) {
7987                 PMD_INIT_LOG(ERR,
7988                          "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
7989                          i40e_stat_str(hw, ret),
7990                          i40e_aq_str(hw, hw->aq.asq_last_status));
7991                 return ret;
7992         }
7993
7994         if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
7995                 PMD_INIT_LOG(WARNING,
7996                          "Enabled TCs mismatch from querying VSI BW info"
7997                          " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
7998                          bw_ets_config.tc_valid_bits);
7999                 /* Still continuing */
8000         }
8001
8002         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
8003         vsi->bw_info.bw_max_quanta = bw_config.max_bw;
8004         tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
8005                     (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
8006         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8007                 vsi->bw_info.bw_ets_share_credits[i] =
8008                                 bw_ets_config.share_credits[i];
8009                 vsi->bw_info.bw_ets_limit_credits[i] =
8010                                 rte_le_to_cpu_16(bw_ets_config.credits[i]);
8011                 /* 3 bits out of 4 for each TC */
8012                 vsi->bw_info.bw_ets_max_quanta[i] =
8013                         (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
8014                 PMD_INIT_LOG(DEBUG,
8015                          "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
8016                          __func__, vsi->seid, i, bw_config.qs_handles[i]);
8017         }
8018
8019         return ret;
8020 }
8021
8022 static enum i40e_status_code
8023 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8024                               struct i40e_aqc_vsi_properties_data *info,
8025                               uint8_t enabled_tcmap)
8026 {
8027         enum i40e_status_code ret;
8028         int i, total_tc = 0;
8029         uint16_t qpnum_per_tc, bsf, qp_idx;
8030         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8031
8032         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8033         if (ret != I40E_SUCCESS)
8034                 return ret;
8035
8036         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8037                 if (enabled_tcmap & (1 << i))
8038                         total_tc++;
8039         }
8040         if (total_tc == 0)
8041                 total_tc = 1;
8042         vsi->enabled_tc = enabled_tcmap;
8043
8044         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
8045         /* Number of queues per enabled TC */
8046         if (qpnum_per_tc == 0) {
8047                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8048                 return I40E_ERR_INVALID_QP_ID;
8049         }
8050         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8051                                 I40E_MAX_Q_PER_TC);
8052         bsf = rte_bsf32(qpnum_per_tc);
8053
8054         /**
8055          * Configure TC and queue mapping parameters, for enabled TC,
8056          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8057          * default queue will serve it.
8058          */
8059         qp_idx = 0;
8060         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8061                 if (vsi->enabled_tc & (1 << i)) {
8062                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8063                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8064                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8065                         qp_idx += qpnum_per_tc;
8066                 } else
8067                         info->tc_mapping[i] = 0;
8068         }
8069
8070         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8071         if (vsi->type == I40E_VSI_SRIOV) {
8072                 info->mapping_flags |=
8073                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8074                 for (i = 0; i < vsi->nb_qps; i++)
8075                         info->queue_mapping[i] =
8076                                 rte_cpu_to_le_16(vsi->base_queue + i);
8077         } else {
8078                 info->mapping_flags |=
8079                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8080                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8081         }
8082         info->valid_sections |=
8083                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8084
8085         return I40E_SUCCESS;
8086 }
8087
8088 /*
8089  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8090  * @vsi: VSI to be configured
8091  * @tc_map: enabled TC bitmap
8092  *
8093  * Returns 0 on success, negative value on failure
8094  */
8095 static enum i40e_status_code
8096 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
8097 {
8098         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8099         struct i40e_vsi_context ctxt;
8100         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8101         enum i40e_status_code ret = I40E_SUCCESS;
8102         int i;
8103
8104         /* Check if enabled_tc is same as existing or new TCs */
8105         if (vsi->enabled_tc == tc_map)
8106                 return ret;
8107
8108         /* configure tc bandwidth */
8109         memset(&bw_data, 0, sizeof(bw_data));
8110         bw_data.tc_valid_bits = tc_map;
8111         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8112         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8113                 if (tc_map & BIT_ULL(i))
8114                         bw_data.tc_bw_credits[i] = 1;
8115         }
8116         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8117         if (ret) {
8118                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8119                         " per TC failed = %d",
8120                         hw->aq.asq_last_status);
8121                 goto out;
8122         }
8123         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8124                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8125
8126         /* Update Queue Pairs Mapping for currently enabled UPs */
8127         ctxt.seid = vsi->seid;
8128         ctxt.pf_num = hw->pf_id;
8129         ctxt.vf_num = 0;
8130         ctxt.uplink_seid = vsi->uplink_seid;
8131         ctxt.info = vsi->info;
8132         i40e_get_cap(hw);
8133         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8134         if (ret)
8135                 goto out;
8136
8137         /* Update the VSI after updating the VSI queue-mapping information */
8138         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8139         if (ret) {
8140                 PMD_INIT_LOG(ERR, "Failed to configure "
8141                             "TC queue mapping = %d",
8142                             hw->aq.asq_last_status);
8143                 goto out;
8144         }
8145         /* update the local VSI info with updated queue map */
8146         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8147                                         sizeof(vsi->info.tc_mapping));
8148         (void)rte_memcpy(&vsi->info.queue_mapping,
8149                         &ctxt.info.queue_mapping,
8150                 sizeof(vsi->info.queue_mapping));
8151         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8152         vsi->info.valid_sections = 0;
8153
8154         /* Update current VSI BW information */
8155         ret = i40e_vsi_get_bw_info(vsi);
8156         if (ret) {
8157                 PMD_INIT_LOG(ERR,
8158                          "Failed updating vsi bw info, err %s aq_err %s",
8159                          i40e_stat_str(hw, ret),
8160                          i40e_aq_str(hw, hw->aq.asq_last_status));
8161                 goto out;
8162         }
8163
8164         vsi->enabled_tc = tc_map;
8165
8166 out:
8167         return ret;
8168 }
8169
8170 /*
8171  * i40e_dcb_hw_configure - program the dcb setting to hw
8172  * @pf: pf the configuration is taken on
8173  * @new_cfg: new configuration
8174  * @tc_map: enabled TC bitmap
8175  *
8176  * Returns 0 on success, negative value on failure
8177  */
8178 static enum i40e_status_code
8179 i40e_dcb_hw_configure(struct i40e_pf *pf,
8180                       struct i40e_dcbx_config *new_cfg,
8181                       uint8_t tc_map)
8182 {
8183         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8184         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8185         struct i40e_vsi *main_vsi = pf->main_vsi;
8186         struct i40e_vsi_list *vsi_list;
8187         enum i40e_status_code ret;
8188         int i;
8189         uint32_t val;
8190
8191         /* Use the FW API if FW > v4.4*/
8192         if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
8193                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8194                                   " to configure DCB");
8195                 return I40E_ERR_FIRMWARE_API_VERSION;
8196         }
8197
8198         /* Check if need reconfiguration */
8199         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8200                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8201                 return I40E_SUCCESS;
8202         }
8203
8204         /* Copy the new config to the current config */
8205         *old_cfg = *new_cfg;
8206         old_cfg->etsrec = old_cfg->etscfg;
8207         ret = i40e_set_dcb_config(hw);
8208         if (ret) {
8209                 PMD_INIT_LOG(ERR,
8210                          "Set DCB Config failed, err %s aq_err %s\n",
8211                          i40e_stat_str(hw, ret),
8212                          i40e_aq_str(hw, hw->aq.asq_last_status));
8213                 return ret;
8214         }
8215         /* set receive Arbiter to RR mode and ETS scheme by default */
8216         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8217                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8218                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8219                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8220                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8221                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8222                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8223                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8224                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8225                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8226                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8227                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8228                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8229         }
8230         /* get local mib to check whether it is configured correctly */
8231         /* IEEE mode */
8232         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8233         /* Get Local DCB Config */
8234         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8235                                      &hw->local_dcbx_config);
8236
8237         /* Update each VSI */
8238         i40e_vsi_config_tc(main_vsi, tc_map);
8239         if (main_vsi->veb) {
8240                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8241                         /* Beside main VSI, only enable default
8242                          * TC for other VSIs
8243                          */
8244                         ret = i40e_vsi_config_tc(vsi_list->vsi,
8245                                                 I40E_DEFAULT_TCMAP);
8246                         if (ret)
8247                                 PMD_INIT_LOG(WARNING,
8248                                          "Failed configuring TC for VSI seid=%d\n",
8249                                          vsi_list->vsi->seid);
8250                         /* continue */
8251                 }
8252         }
8253         return I40E_SUCCESS;
8254 }
8255
8256 /*
8257  * i40e_dcb_init_configure - initial dcb config
8258  * @dev: device being configured
8259  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8260  *
8261  * Returns 0 on success, negative value on failure
8262  */
8263 static int
8264 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8265 {
8266         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8267         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8268         int ret = 0;
8269
8270         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8271                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8272                 return -ENOTSUP;
8273         }
8274
8275         /* DCB initialization:
8276          * Update DCB configuration from the Firmware and configure
8277          * LLDP MIB change event.
8278          */
8279         if (sw_dcb == TRUE) {
8280                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8281                 if (ret != I40E_SUCCESS)
8282                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8283
8284                 ret = i40e_init_dcb(hw);
8285                 /* if sw_dcb, lldp agent is stopped, the return from
8286                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8287                  * adminq status.
8288                  */
8289                 if (ret != I40E_SUCCESS &&
8290                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8291                         memset(&hw->local_dcbx_config, 0,
8292                                 sizeof(struct i40e_dcbx_config));
8293                         /* set dcb default configuration */
8294                         hw->local_dcbx_config.etscfg.willing = 0;
8295                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8296                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8297                         hw->local_dcbx_config.etscfg.tsatable[0] =
8298                                                 I40E_IEEE_TSA_ETS;
8299                         hw->local_dcbx_config.etsrec =
8300                                 hw->local_dcbx_config.etscfg;
8301                         hw->local_dcbx_config.pfc.willing = 0;
8302                         hw->local_dcbx_config.pfc.pfccap =
8303                                                 I40E_MAX_TRAFFIC_CLASS;
8304                         /* FW needs one App to configure HW */
8305                         hw->local_dcbx_config.numapps = 1;
8306                         hw->local_dcbx_config.app[0].selector =
8307                                                 I40E_APP_SEL_ETHTYPE;
8308                         hw->local_dcbx_config.app[0].priority = 3;
8309                         hw->local_dcbx_config.app[0].protocolid =
8310                                                 I40E_APP_PROTOID_FCOE;
8311                         ret = i40e_set_dcb_config(hw);
8312                         if (ret) {
8313                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8314                                         " err = %d, aq_err = %d.", ret,
8315                                           hw->aq.asq_last_status);
8316                                 return -ENOSYS;
8317                         }
8318                 } else {
8319                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8320                                           " aq_err = %d.", ret,
8321                                           hw->aq.asq_last_status);
8322                         return -ENOTSUP;
8323                 }
8324         } else {
8325                 ret = i40e_aq_start_lldp(hw, NULL);
8326                 if (ret != I40E_SUCCESS)
8327                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8328
8329                 ret = i40e_init_dcb(hw);
8330                 if (!ret) {
8331                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8332                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8333                                                   " DCBX offload.");
8334                                 return -ENOTSUP;
8335                         }
8336                 } else {
8337                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8338                                           " aq_err = %d.", ret,
8339                                           hw->aq.asq_last_status);
8340                         return -ENOTSUP;
8341                 }
8342         }
8343         return 0;
8344 }
8345
8346 /*
8347  * i40e_dcb_setup - setup dcb related config
8348  * @dev: device being configured
8349  *
8350  * Returns 0 on success, negative value on failure
8351  */
8352 static int
8353 i40e_dcb_setup(struct rte_eth_dev *dev)
8354 {
8355         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8356         struct i40e_dcbx_config dcb_cfg;
8357         uint8_t tc_map = 0;
8358         int ret = 0;
8359
8360         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8361                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8362                 return -ENOTSUP;
8363         }
8364
8365         if (pf->vf_num != 0 ||
8366             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8367                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8368
8369         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8370         if (ret) {
8371                 PMD_INIT_LOG(ERR, "invalid dcb config");
8372                 return -EINVAL;
8373         }
8374         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8375         if (ret) {
8376                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8377                 return -ENOSYS;
8378         }
8379
8380         return 0;
8381 }
8382
8383 static int
8384 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8385                       struct rte_eth_dcb_info *dcb_info)
8386 {
8387         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8388         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8389         struct i40e_vsi *vsi = pf->main_vsi;
8390         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8391         uint16_t bsf, tc_mapping;
8392         int i;
8393
8394         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8395                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8396         else
8397                 dcb_info->nb_tcs = 1;
8398         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8399                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8400         for (i = 0; i < dcb_info->nb_tcs; i++)
8401                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8402
8403         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8404                 if (vsi->enabled_tc & (1 << i)) {
8405                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8406                         /* only main vsi support multi TCs */
8407                         dcb_info->tc_queue.tc_rxq[0][i].base =
8408                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8409                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8410                         dcb_info->tc_queue.tc_txq[0][i].base =
8411                                 dcb_info->tc_queue.tc_rxq[0][i].base;
8412                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8413                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8414                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8415                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8416                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
8417                 }
8418         }
8419
8420         return 0;
8421 }
8422
8423 static int
8424 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8425 {
8426         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8427         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8428         uint16_t interval =
8429                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8430         uint16_t msix_intr;
8431
8432         msix_intr = intr_handle->intr_vec[queue_id];
8433         if (msix_intr == I40E_MISC_VEC_ID)
8434                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8435                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8436                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8437                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8438                                (interval <<
8439                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8440         else
8441                 I40E_WRITE_REG(hw,
8442                                I40E_PFINT_DYN_CTLN(msix_intr -
8443                                                    I40E_RX_VEC_START),
8444                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8445                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8446                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8447                                (interval <<
8448                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8449
8450         I40E_WRITE_FLUSH(hw);
8451         rte_intr_enable(&dev->pci_dev->intr_handle);
8452
8453         return 0;
8454 }
8455
8456 static int
8457 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8458 {
8459         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8460         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8461         uint16_t msix_intr;
8462
8463         msix_intr = intr_handle->intr_vec[queue_id];
8464         if (msix_intr == I40E_MISC_VEC_ID)
8465                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8466         else
8467                 I40E_WRITE_REG(hw,
8468                                I40E_PFINT_DYN_CTLN(msix_intr -
8469                                                    I40E_RX_VEC_START),
8470                                0);
8471         I40E_WRITE_FLUSH(hw);
8472
8473         return 0;
8474 }