drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_eal.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memzone.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memcpy.h>
  24 #include <rte_alarm.h>
  25 #include <rte_dev.h>
  26 #include <rte_eth_ctrl.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44
  45 #define I40E_CLEAR_PXE_WAIT_MS     200
  46
  47 /* Maximun number of capability elements */
  48 #define I40E_MAX_CAP_ELE_NUM       128
  49
  50 /* Wait count and interval */
  51 #define I40E_CHK_Q_ENA_COUNT       1000
  52 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  53
  54 /* Maximun number of VSI */
  55 #define I40E_MAX_NUM_VSIS          (384UL)
  56
  57 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  58
  59 /* Flow control default timer */
  60 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  61
  62 /* Flow control enable fwd bit */
  63 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  64
  65 /* Receive Packet Buffer size */
  66 #define I40E_RXPBSIZE (968 * 1024)
  67
  68 /* Kilobytes shift */
  69 #define I40E_KILOSHIFT 10
  70
  71 /* Flow control default high water */
  72 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  73
  74 /* Flow control default low water */
  75 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Receive Average Packet Size in Byte*/
  78 #define I40E_PACKET_AVERAGE_SIZE 128
  79
  80 /* Mask of PF interrupt causes */
  81 #define I40E_PFINT_ICR0_ENA_MASK ( \
  82                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  83                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  84                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  85                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  86                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  91
  92 #define I40E_FLOW_TYPES ( \
  93         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  94         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  98         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 103         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 104
 105 /* Additional timesync values. */
 106 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 107 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 108 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 109 #define I40E_PRTTSYN_TSYNENA     0x80000000
 110 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 111 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 /**
 114  * Below are values for writing un-exposed registers suggested
 115  * by silicon experts
 116  */
 117 /* Destination MAC address */
 118 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 119 /* Source MAC address */
 120 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 121 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 122 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 123 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 124 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 125 /* Single VLAN tag in the inner L2 header */
 126 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 127 /* Source IPv4 address */
 128 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 129 /* Destination IPv4 address */
 130 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 131 /* Source IPv4 address for X722 */
 132 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 133 /* Destination IPv4 address for X722 */
 134 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 135 /* IPv4 Protocol for X722 */
 136 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 137 /* IPv4 Time to Live for X722 */
 138 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 139 /* IPv4 Type of Service (TOS) */
 140 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 141 /* IPv4 Protocol */
 142 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 143 /* IPv4 Time to Live */
 144 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 145 /* Source IPv6 address */
 146 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 147 /* Destination IPv6 address */
 148 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 149 /* IPv6 Traffic Class (TC) */
 150 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 151 /* IPv6 Next Header */
 152 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 153 /* IPv6 Hop Limit */
 154 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 155 /* Source L4 port */
 156 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 157 /* Destination L4 port */
 158 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 159 /* SCTP verification tag */
 160 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 161 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 162 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 163 /* Source port of tunneling UDP */
 164 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 165 /* Destination port of tunneling UDP */
 166 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 167 /* UDP Tunneling ID, NVGRE/GRE key */
 168 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 169 /* Last ether type */
 170 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 171 /* Tunneling outer destination IPv4 address */
 172 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 173 /* Tunneling outer destination IPv6 address */
 174 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 175 /* 1st word of flex payload */
 176 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 177 /* 2nd word of flex payload */
 178 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 179 /* 3rd word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 181 /* 4th word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 183 /* 5th word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 185 /* 6th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 187 /* 7th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 189 /* 8th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 191 /* all 8 words flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 193 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 194
 195 #define I40E_TRANSLATE_INSET 0
 196 #define I40E_TRANSLATE_REG   1
 197
 198 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 199 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 200 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 201 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 202 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 203 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 204
 205 /* PCI offset for querying capability */
 206 #define PCI_DEV_CAP_REG            0xA4
 207 /* PCI offset for enabling/disabling Extended Tag */
 208 #define PCI_DEV_CTRL_REG           0xA8
 209 /* Bit mask of Extended Tag capability */
 210 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 211 /* Bit shift of Extended Tag enable/disable */
 212 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 213 /* Bit mask of Extended Tag enable/disable */
 214 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 215
 216 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 217 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 218 static int i40e_dev_configure(struct rte_eth_dev *dev);
 219 static int i40e_dev_start(struct rte_eth_dev *dev);
 220 static void i40e_dev_stop(struct rte_eth_dev *dev);
 221 static void i40e_dev_close(struct rte_eth_dev *dev);
 222 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 223 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 225 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 227 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 229 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 230                                struct rte_eth_stats *stats);
 231 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 232                                struct rte_eth_xstat *xstats, unsigned n);
 233 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 234                                      struct rte_eth_xstat_name *xstats_names,
 235                                      unsigned limit);
 236 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 237 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 238                                             uint16_t queue_id,
 239                                             uint8_t stat_idx,
 240                                             uint8_t is_rx);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 244                               struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 293                                 uint32_t base, uint32_t num);
 294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 296                         uint32_t base);
 297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 298                         uint16_t num);
 299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 300 static int i40e_veb_release(struct i40e_veb *veb);
 301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 302                                                 struct i40e_vsi *vsi);
 303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 306                                              struct i40e_macvlan_filter *mv_f,
 307                                              int num,
 308                                              uint16_t vlan);
 309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 311                                     struct rte_eth_rss_conf *rss_conf);
 312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 313                                       struct rte_eth_rss_conf *rss_conf);
 314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 315                                         struct rte_eth_udp_tunnel *udp_tunnel);
 316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 317                                         struct rte_eth_udp_tunnel *udp_tunnel);
 318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 320                                 enum rte_filter_op filter_op,
 321                                 void *arg);
 322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                                 enum rte_filter_type filter_type,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 327                                   struct rte_eth_dcb_info *dcb_info);
 328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 329 static void i40e_configure_registers(struct i40e_hw *hw);
 330 static void i40e_hw_init(struct rte_eth_dev *dev);
 331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 333                                                      uint16_t seid,
 334                                                      uint16_t rule_type,
 335                                                      uint16_t *entries,
 336                                                      uint16_t count,
 337                                                      uint16_t rule_id);
 338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 339                         struct rte_eth_mirror_conf *mirror_conf,
 340                         uint8_t sw_id, uint8_t on);
 341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 342
 343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                            struct timespec *timestamp,
 347                                            uint32_t flags);
 348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp);
 350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 351
 352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 353
 354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 355                                    struct timespec *timestamp);
 356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 357                                     const struct timespec *timestamp);
 358
 359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 360                                          uint16_t queue_id);
 361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 362                                           uint16_t queue_id);
 363
 364 static int i40e_get_regs(struct rte_eth_dev *dev,
 365                          struct rte_dev_reg_info *regs);
 366
 367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 368
 369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 370                            struct rte_dev_eeprom_info *eeprom);
 371
 372 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 373                                       struct ether_addr *mac_addr);
 374
 375 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 376
 377 static int i40e_ethertype_filter_convert(
 378         const struct rte_eth_ethertype_filter *input,
 379         struct i40e_ethertype_filter *filter);
 380 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 381                                    struct i40e_ethertype_filter *filter);
 382
 383 static int i40e_tunnel_filter_convert(
 384         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 385         struct i40e_tunnel_filter *tunnel_filter);
 386 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 387                                 struct i40e_tunnel_filter *tunnel_filter);
 388 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 389
 390 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 391 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 392 static void i40e_filter_restore(struct i40e_pf *pf);
 393 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 394
 395 int i40e_logtype_init;
 396 int i40e_logtype_driver;
 397
 398 static const struct rte_pci_id pci_id_i40e_map[] = {
 399         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 400         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 401         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 402         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 403         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 404         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 419         { .vendor_id = 0, /* sentinel */ },
 420 };
 421
 422 static const struct eth_dev_ops i40e_eth_dev_ops = {
 423         .dev_configure                = i40e_dev_configure,
 424         .dev_start                    = i40e_dev_start,
 425         .dev_stop                     = i40e_dev_stop,
 426         .dev_close                    = i40e_dev_close,
 427         .dev_reset                    = i40e_dev_reset,
 428         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 429         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 430         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 431         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 432         .dev_set_link_up              = i40e_dev_set_link_up,
 433         .dev_set_link_down            = i40e_dev_set_link_down,
 434         .link_update                  = i40e_dev_link_update,
 435         .stats_get                    = i40e_dev_stats_get,
 436         .xstats_get                   = i40e_dev_xstats_get,
 437         .xstats_get_names             = i40e_dev_xstats_get_names,
 438         .stats_reset                  = i40e_dev_stats_reset,
 439         .xstats_reset                 = i40e_dev_stats_reset,
 440         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 441         .fw_version_get               = i40e_fw_version_get,
 442         .dev_infos_get                = i40e_dev_info_get,
 443         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 444         .vlan_filter_set              = i40e_vlan_filter_set,
 445         .vlan_tpid_set                = i40e_vlan_tpid_set,
 446         .vlan_offload_set             = i40e_vlan_offload_set,
 447         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 448         .vlan_pvid_set                = i40e_vlan_pvid_set,
 449         .rx_queue_start               = i40e_dev_rx_queue_start,
 450         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 451         .tx_queue_start               = i40e_dev_tx_queue_start,
 452         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 453         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 454         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 455         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 456         .rx_queue_release             = i40e_dev_rx_queue_release,
 457         .rx_queue_count               = i40e_dev_rx_queue_count,
 458         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 459         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 460         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 461         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 462         .tx_queue_release             = i40e_dev_tx_queue_release,
 463         .dev_led_on                   = i40e_dev_led_on,
 464         .dev_led_off                  = i40e_dev_led_off,
 465         .flow_ctrl_get                = i40e_flow_ctrl_get,
 466         .flow_ctrl_set                = i40e_flow_ctrl_set,
 467         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 468         .mac_addr_add                 = i40e_macaddr_add,
 469         .mac_addr_remove              = i40e_macaddr_remove,
 470         .reta_update                  = i40e_dev_rss_reta_update,
 471         .reta_query                   = i40e_dev_rss_reta_query,
 472         .rss_hash_update              = i40e_dev_rss_hash_update,
 473         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 474         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 475         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 476         .filter_ctrl                  = i40e_dev_filter_ctrl,
 477         .rxq_info_get                 = i40e_rxq_info_get,
 478         .txq_info_get                 = i40e_txq_info_get,
 479         .mirror_rule_set              = i40e_mirror_rule_set,
 480         .mirror_rule_reset            = i40e_mirror_rule_reset,
 481         .timesync_enable              = i40e_timesync_enable,
 482         .timesync_disable             = i40e_timesync_disable,
 483         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 484         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 485         .get_dcb_info                 = i40e_dev_get_dcb_info,
 486         .timesync_adjust_time         = i40e_timesync_adjust_time,
 487         .timesync_read_time           = i40e_timesync_read_time,
 488         .timesync_write_time          = i40e_timesync_write_time,
 489         .get_reg                      = i40e_get_regs,
 490         .get_eeprom_length            = i40e_get_eeprom_length,
 491         .get_eeprom                   = i40e_get_eeprom,
 492         .mac_addr_set                 = i40e_set_default_mac_addr,
 493         .mtu_set                      = i40e_dev_mtu_set,
 494         .tm_ops_get                   = i40e_tm_ops_get,
 495 };
 496
 497 /* store statistics names and its offset in stats structure */
 498 struct rte_i40e_xstats_name_off {
 499         char name[RTE_ETH_XSTATS_NAME_SIZE];
 500         unsigned offset;
 501 };
 502
 503 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 504         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 505         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 506         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 507         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 508         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 509                 rx_unknown_protocol)},
 510         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 511         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 512         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 513         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 514 };
 515
 516 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 517                 sizeof(rte_i40e_stats_strings[0]))
 518
 519 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 520         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 521                 tx_dropped_link_down)},
 522         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 523         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 524                 illegal_bytes)},
 525         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 526         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 527                 mac_local_faults)},
 528         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 529                 mac_remote_faults)},
 530         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 531                 rx_length_errors)},
 532         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 533         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 534         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 535         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 536         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 537         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 538                 rx_size_127)},
 539         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 540                 rx_size_255)},
 541         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 542                 rx_size_511)},
 543         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 544                 rx_size_1023)},
 545         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 546                 rx_size_1522)},
 547         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 548                 rx_size_big)},
 549         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 550                 rx_undersize)},
 551         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 552                 rx_oversize)},
 553         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 554                 mac_short_packet_dropped)},
 555         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 556                 rx_fragments)},
 557         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 558         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 559         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 tx_size_127)},
 561         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 tx_size_255)},
 563         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 tx_size_511)},
 565         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 tx_size_1023)},
 567         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 tx_size_1522)},
 569         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 tx_size_big)},
 571         {"rx_flow_director_atr_match_packets",
 572                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 573         {"rx_flow_director_sb_match_packets",
 574                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 575         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 576                 tx_lpi_status)},
 577         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 578                 rx_lpi_status)},
 579         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 580                 tx_lpi_count)},
 581         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 582                 rx_lpi_count)},
 583 };
 584
 585 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 586                 sizeof(rte_i40e_hw_port_strings[0]))
 587
 588 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 589         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 590                 priority_xon_rx)},
 591         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 592                 priority_xoff_rx)},
 593 };
 594
 595 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 596                 sizeof(rte_i40e_rxq_prio_strings[0]))
 597
 598 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 599         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 600                 priority_xon_tx)},
 601         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 602                 priority_xoff_tx)},
 603         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 604                 priority_xon_2_xoff)},
 605 };
 606
 607 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 608                 sizeof(rte_i40e_txq_prio_strings[0]))
 609
 610 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 611         struct rte_pci_device *pci_dev)
 612 {
 613         return rte_eth_dev_pci_generic_probe(pci_dev,
 614                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 615 }
 616
 617 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 618 {
 619         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 620 }
 621
 622 static struct rte_pci_driver rte_i40e_pmd = {
 623         .id_table = pci_id_i40e_map,
 624         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 625                      RTE_PCI_DRV_IOVA_AS_VA,
 626         .probe = eth_i40e_pci_probe,
 627         .remove = eth_i40e_pci_remove,
 628 };
 629
 630 static inline int
 631 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 632                                      struct rte_eth_link *link)
 633 {
 634         struct rte_eth_link *dst = link;
 635         struct rte_eth_link *src = &(dev->data->dev_link);
 636
 637         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 638                                         *(uint64_t *)src) == 0)
 639                 return -1;
 640
 641         return 0;
 642 }
 643
 644 static inline int
 645 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 646                                       struct rte_eth_link *link)
 647 {
 648         struct rte_eth_link *dst = &(dev->data->dev_link);
 649         struct rte_eth_link *src = link;
 650
 651         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 652                                         *(uint64_t *)src) == 0)
 653                 return -1;
 654
 655         return 0;
 656 }
 657
 658 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 659 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 660 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 661
 662 #ifndef I40E_GLQF_ORT
 663 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 664 #endif
 665 #ifndef I40E_GLQF_PIT
 666 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 667 #endif
 668 #ifndef I40E_GLQF_L3_MAP
 669 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 670 #endif
 671
 672 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 673 {
 674         /*
 675          * Force global configuration for flexible payload
 676          * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
 677          * This should be removed from code once proper
 678          * configuration API is added to avoid configuration conflicts
 679          * between ports of the same device.
 680          */
 681         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 682         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 683         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 684
 685         /*
 686          * Initialize registers for parsing packet type of QinQ
 687          * This should be removed from code once proper
 688          * configuration API is added to avoid configuration conflicts
 689          * between ports of the same device.
 690          */
 691         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 692         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 693 }
 694
 695 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 696
 697 /*
 698  * Add a ethertype filter to drop all flow control frames transmitted
 699  * from VSIs.
 700 */
 701 static void
 702 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 703 {
 704         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 705         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 706                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 707                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 708         int ret;
 709
 710         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 711                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 712                                 pf->main_vsi_seid, 0,
 713                                 TRUE, NULL, NULL);
 714         if (ret)
 715                 PMD_INIT_LOG(ERR,
 716                         "Failed to add filter to drop flow control frames from VSIs.");
 717 }
 718
 719 static int
 720 floating_veb_list_handler(__rte_unused const char *key,
 721                           const char *floating_veb_value,
 722                           void *opaque)
 723 {
 724         int idx = 0;
 725         unsigned int count = 0;
 726         char *end = NULL;
 727         int min, max;
 728         bool *vf_floating_veb = opaque;
 729
 730         while (isblank(*floating_veb_value))
 731                 floating_veb_value++;
 732
 733         /* Reset floating VEB configuration for VFs */
 734         for (idx = 0; idx < I40E_MAX_VF; idx++)
 735                 vf_floating_veb[idx] = false;
 736
 737         min = I40E_MAX_VF;
 738         do {
 739                 while (isblank(*floating_veb_value))
 740                         floating_veb_value++;
 741                 if (*floating_veb_value == '\0')
 742                         return -1;
 743                 errno = 0;
 744                 idx = strtoul(floating_veb_value, &end, 10);
 745                 if (errno || end == NULL)
 746                         return -1;
 747                 while (isblank(*end))
 748                         end++;
 749                 if (*end == '-') {
 750                         min = idx;
 751                 } else if ((*end == ';') || (*end == '\0')) {
 752                         max = idx;
 753                         if (min == I40E_MAX_VF)
 754                                 min = idx;
 755                         if (max >= I40E_MAX_VF)
 756                                 max = I40E_MAX_VF - 1;
 757                         for (idx = min; idx <= max; idx++) {
 758                                 vf_floating_veb[idx] = true;
 759                                 count++;
 760                         }
 761                         min = I40E_MAX_VF;
 762                 } else {
 763                         return -1;
 764                 }
 765                 floating_veb_value = end + 1;
 766         } while (*end != '\0');
 767
 768         if (count == 0)
 769                 return -1;
 770
 771         return 0;
 772 }
 773
 774 static void
 775 config_vf_floating_veb(struct rte_devargs *devargs,
 776                        uint16_t floating_veb,
 777                        bool *vf_floating_veb)
 778 {
 779         struct rte_kvargs *kvlist;
 780         int i;
 781         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 782
 783         if (!floating_veb)
 784                 return;
 785         /* All the VFs attach to the floating VEB by default
 786          * when the floating VEB is enabled.
 787          */
 788         for (i = 0; i < I40E_MAX_VF; i++)
 789                 vf_floating_veb[i] = true;
 790
 791         if (devargs == NULL)
 792                 return;
 793
 794         kvlist = rte_kvargs_parse(devargs->args, NULL);
 795         if (kvlist == NULL)
 796                 return;
 797
 798         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 799                 rte_kvargs_free(kvlist);
 800                 return;
 801         }
 802         /* When the floating_veb_list parameter exists, all the VFs
 803          * will attach to the legacy VEB firstly, then configure VFs
 804          * to the floating VEB according to the floating_veb_list.
 805          */
 806         if (rte_kvargs_process(kvlist, floating_veb_list,
 807                                floating_veb_list_handler,
 808                                vf_floating_veb) < 0) {
 809                 rte_kvargs_free(kvlist);
 810                 return;
 811         }
 812         rte_kvargs_free(kvlist);
 813 }
 814
 815 static int
 816 i40e_check_floating_handler(__rte_unused const char *key,
 817                             const char *value,
 818                             __rte_unused void *opaque)
 819 {
 820         if (strcmp(value, "1"))
 821                 return -1;
 822
 823         return 0;
 824 }
 825
 826 static int
 827 is_floating_veb_supported(struct rte_devargs *devargs)
 828 {
 829         struct rte_kvargs *kvlist;
 830         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 831
 832         if (devargs == NULL)
 833                 return 0;
 834
 835         kvlist = rte_kvargs_parse(devargs->args, NULL);
 836         if (kvlist == NULL)
 837                 return 0;
 838
 839         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 840                 rte_kvargs_free(kvlist);
 841                 return 0;
 842         }
 843         /* Floating VEB is enabled when there's key-value:
 844          * enable_floating_veb=1
 845          */
 846         if (rte_kvargs_process(kvlist, floating_veb_key,
 847                                i40e_check_floating_handler, NULL) < 0) {
 848                 rte_kvargs_free(kvlist);
 849                 return 0;
 850         }
 851         rte_kvargs_free(kvlist);
 852
 853         return 1;
 854 }
 855
 856 static void
 857 config_floating_veb(struct rte_eth_dev *dev)
 858 {
 859         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 860         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 861         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 862
 863         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 864
 865         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 866                 pf->floating_veb =
 867                         is_floating_veb_supported(pci_dev->device.devargs);
 868                 config_vf_floating_veb(pci_dev->device.devargs,
 869                                        pf->floating_veb,
 870                                        pf->floating_veb_list);
 871         } else {
 872                 pf->floating_veb = false;
 873         }
 874 }
 875
 876 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 877 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 878
 879 static int
 880 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 881 {
 882         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 883         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 884         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 885         int ret;
 886
 887         struct rte_hash_parameters ethertype_hash_params = {
 888                 .name = ethertype_hash_name,
 889                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 890                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 891                 .hash_func = rte_hash_crc,
 892                 .hash_func_init_val = 0,
 893                 .socket_id = rte_socket_id(),
 894         };
 895
 896         /* Initialize ethertype filter rule list and hash */
 897         TAILQ_INIT(&ethertype_rule->ethertype_list);
 898         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 899                  "ethertype_%s", dev->device->name);
 900         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 901         if (!ethertype_rule->hash_table) {
 902                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 903                 return -EINVAL;
 904         }
 905         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 906                                        sizeof(struct i40e_ethertype_filter *) *
 907                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 908                                        0);
 909         if (!ethertype_rule->hash_map) {
 910                 PMD_INIT_LOG(ERR,
 911                              "Failed to allocate memory for ethertype hash map!");
 912                 ret = -ENOMEM;
 913                 goto err_ethertype_hash_map_alloc;
 914         }
 915
 916         return 0;
 917
 918 err_ethertype_hash_map_alloc:
 919         rte_hash_free(ethertype_rule->hash_table);
 920
 921         return ret;
 922 }
 923
 924 static int
 925 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 926 {
 927         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 928         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 929         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 930         int ret;
 931
 932         struct rte_hash_parameters tunnel_hash_params = {
 933                 .name = tunnel_hash_name,
 934                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 935                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 936                 .hash_func = rte_hash_crc,
 937                 .hash_func_init_val = 0,
 938                 .socket_id = rte_socket_id(),
 939         };
 940
 941         /* Initialize tunnel filter rule list and hash */
 942         TAILQ_INIT(&tunnel_rule->tunnel_list);
 943         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 944                  "tunnel_%s", dev->device->name);
 945         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 946         if (!tunnel_rule->hash_table) {
 947                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 948                 return -EINVAL;
 949         }
 950         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 951                                     sizeof(struct i40e_tunnel_filter *) *
 952                                     I40E_MAX_TUNNEL_FILTER_NUM,
 953                                     0);
 954         if (!tunnel_rule->hash_map) {
 955                 PMD_INIT_LOG(ERR,
 956                              "Failed to allocate memory for tunnel hash map!");
 957                 ret = -ENOMEM;
 958                 goto err_tunnel_hash_map_alloc;
 959         }
 960
 961         return 0;
 962
 963 err_tunnel_hash_map_alloc:
 964         rte_hash_free(tunnel_rule->hash_table);
 965
 966         return ret;
 967 }
 968
 969 static int
 970 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 971 {
 972         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 973         struct i40e_fdir_info *fdir_info = &pf->fdir;
 974         char fdir_hash_name[RTE_HASH_NAMESIZE];
 975         int ret;
 976
 977         struct rte_hash_parameters fdir_hash_params = {
 978                 .name = fdir_hash_name,
 979                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 980                 .key_len = sizeof(struct i40e_fdir_input),
 981                 .hash_func = rte_hash_crc,
 982                 .hash_func_init_val = 0,
 983                 .socket_id = rte_socket_id(),
 984         };
 985
 986         /* Initialize flow director filter rule list and hash */
 987         TAILQ_INIT(&fdir_info->fdir_list);
 988         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 989                  "fdir_%s", dev->device->name);
 990         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 991         if (!fdir_info->hash_table) {
 992                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 993                 return -EINVAL;
 994         }
 995         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
 996                                           sizeof(struct i40e_fdir_filter *) *
 997                                           I40E_MAX_FDIR_FILTER_NUM,
 998                                           0);
 999         if (!fdir_info->hash_map) {
1000                 PMD_INIT_LOG(ERR,
1001                              "Failed to allocate memory for fdir hash map!");
1002                 ret = -ENOMEM;
1003                 goto err_fdir_hash_map_alloc;
1004         }
1005         return 0;
1006
1007 err_fdir_hash_map_alloc:
1008         rte_hash_free(fdir_info->hash_table);
1009
1010         return ret;
1011 }
1012
1013 static void
1014 i40e_init_customized_info(struct i40e_pf *pf)
1015 {
1016         int i;
1017
1018         /* Initialize customized pctype */
1019         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1020                 pf->customized_pctype[i].index = i;
1021                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1022                 pf->customized_pctype[i].valid = false;
1023         }
1024
1025         pf->gtp_support = false;
1026 }
1027
1028 void
1029 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1030 {
1031         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1033         struct i40e_queue_regions *info = &pf->queue_region;
1034         uint16_t i;
1035
1036         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1037                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1038
1039         memset(info, 0, sizeof(struct i40e_queue_regions));
1040 }
1041
1042 static int
1043 eth_i40e_dev_init(struct rte_eth_dev *dev)
1044 {
1045         struct rte_pci_device *pci_dev;
1046         struct rte_intr_handle *intr_handle;
1047         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1048         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1049         struct i40e_vsi *vsi;
1050         int ret;
1051         uint32_t len;
1052         uint8_t aq_fail = 0;
1053
1054         PMD_INIT_FUNC_TRACE();
1055
1056         dev->dev_ops = &i40e_eth_dev_ops;
1057         dev->rx_pkt_burst = i40e_recv_pkts;
1058         dev->tx_pkt_burst = i40e_xmit_pkts;
1059         dev->tx_pkt_prepare = i40e_prep_pkts;
1060
1061         /* for secondary processes, we don't initialise any further as primary
1062          * has already done this work. Only check we don't need a different
1063          * RX function */
1064         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1065                 i40e_set_rx_function(dev);
1066                 i40e_set_tx_function(dev);
1067                 return 0;
1068         }
1069         i40e_set_default_ptype_table(dev);
1070         i40e_set_default_pctype_table(dev);
1071         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1072         intr_handle = &pci_dev->intr_handle;
1073
1074         rte_eth_copy_pci_info(dev, pci_dev);
1075
1076         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1077         pf->adapter->eth_dev = dev;
1078         pf->dev_data = dev->data;
1079
1080         hw->back = I40E_PF_TO_ADAPTER(pf);
1081         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1082         if (!hw->hw_addr) {
1083                 PMD_INIT_LOG(ERR,
1084                         "Hardware is not available, as address is NULL");
1085                 return -ENODEV;
1086         }
1087
1088         hw->vendor_id = pci_dev->id.vendor_id;
1089         hw->device_id = pci_dev->id.device_id;
1090         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1091         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1092         hw->bus.device = pci_dev->addr.devid;
1093         hw->bus.func = pci_dev->addr.function;
1094         hw->adapter_stopped = 0;
1095
1096         /* Make sure all is clean before doing PF reset */
1097         i40e_clear_hw(hw);
1098
1099         /* Initialize the hardware */
1100         i40e_hw_init(dev);
1101
1102         /* Reset here to make sure all is clean for each PF */
1103         ret = i40e_pf_reset(hw);
1104         if (ret) {
1105                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1106                 return ret;
1107         }
1108
1109         /* Initialize the shared code (base driver) */
1110         ret = i40e_init_shared_code(hw);
1111         if (ret) {
1112                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1113                 return ret;
1114         }
1115
1116         /*
1117          * To work around the NVM issue, initialize registers
1118          * for flexible payload and packet type of QinQ by
1119          * software. It should be removed once issues are fixed
1120          * in NVM.
1121          */
1122         i40e_GLQF_reg_init(hw);
1123
1124         /* Initialize the input set for filters (hash and fd) to default value */
1125         i40e_filter_input_set_init(pf);
1126
1127         /* Initialize the parameters for adminq */
1128         i40e_init_adminq_parameter(hw);
1129         ret = i40e_init_adminq(hw);
1130         if (ret != I40E_SUCCESS) {
1131                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1132                 return -EIO;
1133         }
1134         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1135                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1136                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1137                      ((hw->nvm.version >> 12) & 0xf),
1138                      ((hw->nvm.version >> 4) & 0xff),
1139                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1140
1141         /* initialise the L3_MAP register */
1142         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1143                                    0x00000028,  NULL);
1144         if (ret)
1145                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1146
1147         /* Need the special FW version to support floating VEB */
1148         config_floating_veb(dev);
1149         /* Clear PXE mode */
1150         i40e_clear_pxe_mode(hw);
1151         i40e_dev_sync_phy_type(hw);
1152
1153         /*
1154          * On X710, performance number is far from the expectation on recent
1155          * firmware versions. The fix for this issue may not be integrated in
1156          * the following firmware version. So the workaround in software driver
1157          * is needed. It needs to modify the initial values of 3 internal only
1158          * registers. Note that the workaround can be removed when it is fixed
1159          * in firmware in the future.
1160          */
1161         i40e_configure_registers(hw);
1162
1163         /* Get hw capabilities */
1164         ret = i40e_get_cap(hw);
1165         if (ret != I40E_SUCCESS) {
1166                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1167                 goto err_get_capabilities;
1168         }
1169
1170         /* Initialize parameters for PF */
1171         ret = i40e_pf_parameter_init(dev);
1172         if (ret != 0) {
1173                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1174                 goto err_parameter_init;
1175         }
1176
1177         /* Initialize the queue management */
1178         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1179         if (ret < 0) {
1180                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1181                 goto err_qp_pool_init;
1182         }
1183         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1184                                 hw->func_caps.num_msix_vectors - 1);
1185         if (ret < 0) {
1186                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1187                 goto err_msix_pool_init;
1188         }
1189
1190         /* Initialize lan hmc */
1191         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1192                                 hw->func_caps.num_rx_qp, 0, 0);
1193         if (ret != I40E_SUCCESS) {
1194                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1195                 goto err_init_lan_hmc;
1196         }
1197
1198         /* Configure lan hmc */
1199         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1200         if (ret != I40E_SUCCESS) {
1201                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1202                 goto err_configure_lan_hmc;
1203         }
1204
1205         /* Get and check the mac address */
1206         i40e_get_mac_addr(hw, hw->mac.addr);
1207         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1208                 PMD_INIT_LOG(ERR, "mac address is not valid");
1209                 ret = -EIO;
1210                 goto err_get_mac_addr;
1211         }
1212         /* Copy the permanent MAC address */
1213         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1214                         (struct ether_addr *) hw->mac.perm_addr);
1215
1216         /* Disable flow control */
1217         hw->fc.requested_mode = I40E_FC_NONE;
1218         i40e_set_fc(hw, &aq_fail, TRUE);
1219
1220         /* Set the global registers with default ether type value */
1221         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1222         if (ret != I40E_SUCCESS) {
1223                 PMD_INIT_LOG(ERR,
1224                         "Failed to set the default outer VLAN ether type");
1225                 goto err_setup_pf_switch;
1226         }
1227
1228         /* PF setup, which includes VSI setup */
1229         ret = i40e_pf_setup(pf);
1230         if (ret) {
1231                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1232                 goto err_setup_pf_switch;
1233         }
1234
1235         /* reset all stats of the device, including pf and main vsi */
1236         i40e_dev_stats_reset(dev);
1237
1238         vsi = pf->main_vsi;
1239
1240         /* Disable double vlan by default */
1241         i40e_vsi_config_double_vlan(vsi, FALSE);
1242
1243         /* Disable S-TAG identification when floating_veb is disabled */
1244         if (!pf->floating_veb) {
1245                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1246                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1247                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1248                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1249                 }
1250         }
1251
1252         if (!vsi->max_macaddrs)
1253                 len = ETHER_ADDR_LEN;
1254         else
1255                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1256
1257         /* Should be after VSI initialized */
1258         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1259         if (!dev->data->mac_addrs) {
1260                 PMD_INIT_LOG(ERR,
1261                         "Failed to allocated memory for storing mac address");
1262                 goto err_mac_alloc;
1263         }
1264         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1265                                         &dev->data->mac_addrs[0]);
1266
1267         /* Init dcb to sw mode by default */
1268         ret = i40e_dcb_init_configure(dev, TRUE);
1269         if (ret != I40E_SUCCESS) {
1270                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1271                 pf->flags &= ~I40E_FLAG_DCB;
1272         }
1273         /* Update HW struct after DCB configuration */
1274         i40e_get_cap(hw);
1275
1276         /* initialize pf host driver to setup SRIOV resource if applicable */
1277         i40e_pf_host_init(dev);
1278
1279         /* register callback func to eal lib */
1280         rte_intr_callback_register(intr_handle,
1281                                    i40e_dev_interrupt_handler, dev);
1282
1283         /* configure and enable device interrupt */
1284         i40e_pf_config_irq0(hw, TRUE);
1285         i40e_pf_enable_irq0(hw);
1286
1287         /* enable uio intr after callback register */
1288         rte_intr_enable(intr_handle);
1289         /*
1290          * Add an ethertype filter to drop all flow control frames transmitted
1291          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1292          * frames to wire.
1293          */
1294         i40e_add_tx_flow_control_drop_filter(pf);
1295
1296         /* Set the max frame size to 0x2600 by default,
1297          * in case other drivers changed the default value.
1298          */
1299         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1300
1301         /* initialize mirror rule list */
1302         TAILQ_INIT(&pf->mirror_list);
1303
1304         /* initialize Traffic Manager configuration */
1305         i40e_tm_conf_init(dev);
1306
1307         /* Initialize customized information */
1308         i40e_init_customized_info(pf);
1309
1310         ret = i40e_init_ethtype_filter_list(dev);
1311         if (ret < 0)
1312                 goto err_init_ethtype_filter_list;
1313         ret = i40e_init_tunnel_filter_list(dev);
1314         if (ret < 0)
1315                 goto err_init_tunnel_filter_list;
1316         ret = i40e_init_fdir_filter_list(dev);
1317         if (ret < 0)
1318                 goto err_init_fdir_filter_list;
1319
1320         /* initialize queue region configuration */
1321         i40e_init_queue_region_conf(dev);
1322
1323         return 0;
1324
1325 err_init_fdir_filter_list:
1326         rte_free(pf->tunnel.hash_table);
1327         rte_free(pf->tunnel.hash_map);
1328 err_init_tunnel_filter_list:
1329         rte_free(pf->ethertype.hash_table);
1330         rte_free(pf->ethertype.hash_map);
1331 err_init_ethtype_filter_list:
1332         rte_free(dev->data->mac_addrs);
1333 err_mac_alloc:
1334         i40e_vsi_release(pf->main_vsi);
1335 err_setup_pf_switch:
1336 err_get_mac_addr:
1337 err_configure_lan_hmc:
1338         (void)i40e_shutdown_lan_hmc(hw);
1339 err_init_lan_hmc:
1340         i40e_res_pool_destroy(&pf->msix_pool);
1341 err_msix_pool_init:
1342         i40e_res_pool_destroy(&pf->qp_pool);
1343 err_qp_pool_init:
1344 err_parameter_init:
1345 err_get_capabilities:
1346         (void)i40e_shutdown_adminq(hw);
1347
1348         return ret;
1349 }
1350
1351 static void
1352 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1353 {
1354         struct i40e_ethertype_filter *p_ethertype;
1355         struct i40e_ethertype_rule *ethertype_rule;
1356
1357         ethertype_rule = &pf->ethertype;
1358         /* Remove all ethertype filter rules and hash */
1359         if (ethertype_rule->hash_map)
1360                 rte_free(ethertype_rule->hash_map);
1361         if (ethertype_rule->hash_table)
1362                 rte_hash_free(ethertype_rule->hash_table);
1363
1364         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1365                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1366                              p_ethertype, rules);
1367                 rte_free(p_ethertype);
1368         }
1369 }
1370
1371 static void
1372 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1373 {
1374         struct i40e_tunnel_filter *p_tunnel;
1375         struct i40e_tunnel_rule *tunnel_rule;
1376
1377         tunnel_rule = &pf->tunnel;
1378         /* Remove all tunnel director rules and hash */
1379         if (tunnel_rule->hash_map)
1380                 rte_free(tunnel_rule->hash_map);
1381         if (tunnel_rule->hash_table)
1382                 rte_hash_free(tunnel_rule->hash_table);
1383
1384         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1385                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1386                 rte_free(p_tunnel);
1387         }
1388 }
1389
1390 static void
1391 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1392 {
1393         struct i40e_fdir_filter *p_fdir;
1394         struct i40e_fdir_info *fdir_info;
1395
1396         fdir_info = &pf->fdir;
1397         /* Remove all flow director rules and hash */
1398         if (fdir_info->hash_map)
1399                 rte_free(fdir_info->hash_map);
1400         if (fdir_info->hash_table)
1401                 rte_hash_free(fdir_info->hash_table);
1402
1403         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1404                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1405                 rte_free(p_fdir);
1406         }
1407 }
1408
1409 static int
1410 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1411 {
1412         struct i40e_pf *pf;
1413         struct rte_pci_device *pci_dev;
1414         struct rte_intr_handle *intr_handle;
1415         struct i40e_hw *hw;
1416         struct i40e_filter_control_settings settings;
1417         struct rte_flow *p_flow;
1418         int ret;
1419         uint8_t aq_fail = 0;
1420
1421         PMD_INIT_FUNC_TRACE();
1422
1423         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1424                 return 0;
1425
1426         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1427         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1429         intr_handle = &pci_dev->intr_handle;
1430
1431         if (hw->adapter_stopped == 0)
1432                 i40e_dev_close(dev);
1433
1434         dev->dev_ops = NULL;
1435         dev->rx_pkt_burst = NULL;
1436         dev->tx_pkt_burst = NULL;
1437
1438         /* Clear PXE mode */
1439         i40e_clear_pxe_mode(hw);
1440
1441         /* Unconfigure filter control */
1442         memset(&settings, 0, sizeof(settings));
1443         ret = i40e_set_filter_control(hw, &settings);
1444         if (ret)
1445                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1446                                         ret);
1447
1448         /* Disable flow control */
1449         hw->fc.requested_mode = I40E_FC_NONE;
1450         i40e_set_fc(hw, &aq_fail, TRUE);
1451
1452         /* uninitialize pf host driver */
1453         i40e_pf_host_uninit(dev);
1454
1455         rte_free(dev->data->mac_addrs);
1456         dev->data->mac_addrs = NULL;
1457
1458         /* disable uio intr before callback unregister */
1459         rte_intr_disable(intr_handle);
1460
1461         /* register callback func to eal lib */
1462         rte_intr_callback_unregister(intr_handle,
1463                                      i40e_dev_interrupt_handler, dev);
1464
1465         i40e_rm_ethtype_filter_list(pf);
1466         i40e_rm_tunnel_filter_list(pf);
1467         i40e_rm_fdir_filter_list(pf);
1468
1469         /* Remove all flows */
1470         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1471                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1472                 rte_free(p_flow);
1473         }
1474
1475         /* Remove all Traffic Manager configuration */
1476         i40e_tm_conf_uninit(dev);
1477
1478         return 0;
1479 }
1480
1481 static int
1482 i40e_dev_configure(struct rte_eth_dev *dev)
1483 {
1484         struct i40e_adapter *ad =
1485                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1486         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1487         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1488         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1489         int i, ret;
1490
1491         ret = i40e_dev_sync_phy_type(hw);
1492         if (ret)
1493                 return ret;
1494
1495         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1496          * bulk allocation or vector Rx preconditions we will reset it.
1497          */
1498         ad->rx_bulk_alloc_allowed = true;
1499         ad->rx_vec_allowed = true;
1500         ad->tx_simple_allowed = true;
1501         ad->tx_vec_allowed = true;
1502
1503         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1504                 ret = i40e_fdir_setup(pf);
1505                 if (ret != I40E_SUCCESS) {
1506                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1507                         return -ENOTSUP;
1508                 }
1509                 ret = i40e_fdir_configure(dev);
1510                 if (ret < 0) {
1511                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1512                         goto err;
1513                 }
1514         } else
1515                 i40e_fdir_teardown(pf);
1516
1517         ret = i40e_dev_init_vlan(dev);
1518         if (ret < 0)
1519                 goto err;
1520
1521         /* VMDQ setup.
1522          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1523          *  RSS setting have different requirements.
1524          *  General PMD driver call sequence are NIC init, configure,
1525          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1526          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1527          *  applicable. So, VMDQ setting has to be done before
1528          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1529          *  For RSS setting, it will try to calculate actual configured RX queue
1530          *  number, which will be available after rx_queue_setup(). dev_start()
1531          *  function is good to place RSS setup.
1532          */
1533         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1534                 ret = i40e_vmdq_setup(dev);
1535                 if (ret)
1536                         goto err;
1537         }
1538
1539         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1540                 ret = i40e_dcb_setup(dev);
1541                 if (ret) {
1542                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1543                         goto err_dcb;
1544                 }
1545         }
1546
1547         TAILQ_INIT(&pf->flow_list);
1548
1549         return 0;
1550
1551 err_dcb:
1552         /* need to release vmdq resource if exists */
1553         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1554                 i40e_vsi_release(pf->vmdq[i].vsi);
1555                 pf->vmdq[i].vsi = NULL;
1556         }
1557         rte_free(pf->vmdq);
1558         pf->vmdq = NULL;
1559 err:
1560         /* need to release fdir resource if exists */
1561         i40e_fdir_teardown(pf);
1562         return ret;
1563 }
1564
1565 void
1566 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1567 {
1568         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1569         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1570         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1571         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1572         uint16_t msix_vect = vsi->msix_intr;
1573         uint16_t i;
1574
1575         for (i = 0; i < vsi->nb_qps; i++) {
1576                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1577                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1578                 rte_wmb();
1579         }
1580
1581         if (vsi->type != I40E_VSI_SRIOV) {
1582                 if (!rte_intr_allow_others(intr_handle)) {
1583                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1584                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1585                         I40E_WRITE_REG(hw,
1586                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1587                                        0);
1588                 } else {
1589                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1590                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1591                         I40E_WRITE_REG(hw,
1592                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1593                                                        msix_vect - 1), 0);
1594                 }
1595         } else {
1596                 uint32_t reg;
1597                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1598                         vsi->user_param + (msix_vect - 1);
1599
1600                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1601                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1602         }
1603         I40E_WRITE_FLUSH(hw);
1604 }
1605
1606 static void
1607 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1608                        int base_queue, int nb_queue,
1609                        uint16_t itr_idx)
1610 {
1611         int i;
1612         uint32_t val;
1613         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1614
1615         /* Bind all RX queues to allocated MSIX interrupt */
1616         for (i = 0; i < nb_queue; i++) {
1617                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1618                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1619                         ((base_queue + i + 1) <<
1620                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1621                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1622                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1623
1624                 if (i == nb_queue - 1)
1625                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1626                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1627         }
1628
1629         /* Write first RX queue to Link list register as the head element */
1630         if (vsi->type != I40E_VSI_SRIOV) {
1631                 uint16_t interval =
1632                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1633
1634                 if (msix_vect == I40E_MISC_VEC_ID) {
1635                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1636                                        (base_queue <<
1637                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1638                                        (0x0 <<
1639                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1640                         I40E_WRITE_REG(hw,
1641                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1642                                        interval);
1643                 } else {
1644                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1645                                        (base_queue <<
1646                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1647                                        (0x0 <<
1648                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1649                         I40E_WRITE_REG(hw,
1650                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1651                                                        msix_vect - 1),
1652                                        interval);
1653                 }
1654         } else {
1655                 uint32_t reg;
1656
1657                 if (msix_vect == I40E_MISC_VEC_ID) {
1658                         I40E_WRITE_REG(hw,
1659                                        I40E_VPINT_LNKLST0(vsi->user_param),
1660                                        (base_queue <<
1661                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1662                                        (0x0 <<
1663                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1664                 } else {
1665                         /* num_msix_vectors_vf needs to minus irq0 */
1666                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1667                                 vsi->user_param + (msix_vect - 1);
1668
1669                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1670                                        (base_queue <<
1671                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1672                                        (0x0 <<
1673                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1674                 }
1675         }
1676
1677         I40E_WRITE_FLUSH(hw);
1678 }
1679
1680 void
1681 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1682 {
1683         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1684         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1685         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1686         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1687         uint16_t msix_vect = vsi->msix_intr;
1688         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1689         uint16_t queue_idx = 0;
1690         int record = 0;
1691         uint32_t val;
1692         int i;
1693
1694         for (i = 0; i < vsi->nb_qps; i++) {
1695                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1696                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1697         }
1698
1699         /* INTENA flag is not auto-cleared for interrupt */
1700         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1701         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1702                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1703                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1704         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1705
1706         /* VF bind interrupt */
1707         if (vsi->type == I40E_VSI_SRIOV) {
1708                 __vsi_queues_bind_intr(vsi, msix_vect,
1709                                        vsi->base_queue, vsi->nb_qps,
1710                                        itr_idx);
1711                 return;
1712         }
1713
1714         /* PF & VMDq bind interrupt */
1715         if (rte_intr_dp_is_en(intr_handle)) {
1716                 if (vsi->type == I40E_VSI_MAIN) {
1717                         queue_idx = 0;
1718                         record = 1;
1719                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1720                         struct i40e_vsi *main_vsi =
1721                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1722                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1723                         record = 1;
1724                 }
1725         }
1726
1727         for (i = 0; i < vsi->nb_used_qps; i++) {
1728                 if (nb_msix <= 1) {
1729                         if (!rte_intr_allow_others(intr_handle))
1730                                 /* allow to share MISC_VEC_ID */
1731                                 msix_vect = I40E_MISC_VEC_ID;
1732
1733                         /* no enough msix_vect, map all to one */
1734                         __vsi_queues_bind_intr(vsi, msix_vect,
1735                                                vsi->base_queue + i,
1736                                                vsi->nb_used_qps - i,
1737                                                itr_idx);
1738                         for (; !!record && i < vsi->nb_used_qps; i++)
1739                                 intr_handle->intr_vec[queue_idx + i] =
1740                                         msix_vect;
1741                         break;
1742                 }
1743                 /* 1:1 queue/msix_vect mapping */
1744                 __vsi_queues_bind_intr(vsi, msix_vect,
1745                                        vsi->base_queue + i, 1,
1746                                        itr_idx);
1747                 if (!!record)
1748                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1749
1750                 msix_vect++;
1751                 nb_msix--;
1752         }
1753 }
1754
1755 static void
1756 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1757 {
1758         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1759         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1760         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1761         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1762         uint16_t interval = i40e_calc_itr_interval(\
1763                 RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1764         uint16_t msix_intr, i;
1765
1766         if (rte_intr_allow_others(intr_handle))
1767                 for (i = 0; i < vsi->nb_msix; i++) {
1768                         msix_intr = vsi->msix_intr + i;
1769                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1770                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1771                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1772                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1773                                 (interval <<
1774                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1775                 }
1776         else
1777                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1778                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1779                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1780                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1781                                (interval <<
1782                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1783
1784         I40E_WRITE_FLUSH(hw);
1785 }
1786
1787 static void
1788 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1789 {
1790         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1791         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1792         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1793         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1794         uint16_t msix_intr, i;
1795
1796         if (rte_intr_allow_others(intr_handle))
1797                 for (i = 0; i < vsi->nb_msix; i++) {
1798                         msix_intr = vsi->msix_intr + i;
1799                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1800                                        0);
1801                 }
1802         else
1803                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1804
1805         I40E_WRITE_FLUSH(hw);
1806 }
1807
1808 static inline uint8_t
1809 i40e_parse_link_speeds(uint16_t link_speeds)
1810 {
1811         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1812
1813         if (link_speeds & ETH_LINK_SPEED_40G)
1814                 link_speed |= I40E_LINK_SPEED_40GB;
1815         if (link_speeds & ETH_LINK_SPEED_25G)
1816                 link_speed |= I40E_LINK_SPEED_25GB;
1817         if (link_speeds & ETH_LINK_SPEED_20G)
1818                 link_speed |= I40E_LINK_SPEED_20GB;
1819         if (link_speeds & ETH_LINK_SPEED_10G)
1820                 link_speed |= I40E_LINK_SPEED_10GB;
1821         if (link_speeds & ETH_LINK_SPEED_1G)
1822                 link_speed |= I40E_LINK_SPEED_1GB;
1823         if (link_speeds & ETH_LINK_SPEED_100M)
1824                 link_speed |= I40E_LINK_SPEED_100MB;
1825
1826         return link_speed;
1827 }
1828
1829 static int
1830 i40e_phy_conf_link(struct i40e_hw *hw,
1831                    uint8_t abilities,
1832                    uint8_t force_speed,
1833                    bool is_up)
1834 {
1835         enum i40e_status_code status;
1836         struct i40e_aq_get_phy_abilities_resp phy_ab;
1837         struct i40e_aq_set_phy_config phy_conf;
1838         enum i40e_aq_phy_type cnt;
1839         uint32_t phy_type_mask = 0;
1840
1841         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1842                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1843                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1844                         I40E_AQ_PHY_FLAG_LOW_POWER;
1845         const uint8_t advt = I40E_LINK_SPEED_40GB |
1846                         I40E_LINK_SPEED_25GB |
1847                         I40E_LINK_SPEED_10GB |
1848                         I40E_LINK_SPEED_1GB |
1849                         I40E_LINK_SPEED_100MB;
1850         int ret = -ENOTSUP;
1851
1852
1853         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1854                                               NULL);
1855         if (status)
1856                 return ret;
1857
1858         /* If link already up, no need to set up again */
1859         if (is_up && phy_ab.phy_type != 0)
1860                 return I40E_SUCCESS;
1861
1862         memset(&phy_conf, 0, sizeof(phy_conf));
1863
1864         /* bits 0-2 use the values from get_phy_abilities_resp */
1865         abilities &= ~mask;
1866         abilities |= phy_ab.abilities & mask;
1867
1868         /* update ablities and speed */
1869         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1870                 phy_conf.link_speed = advt;
1871         else
1872                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1873
1874         phy_conf.abilities = abilities;
1875
1876
1877
1878         /* To enable link, phy_type mask needs to include each type */
1879         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1880                 phy_type_mask |= 1 << cnt;
1881
1882         /* use get_phy_abilities_resp value for the rest */
1883         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1884         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1885                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1886                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1887         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1888         phy_conf.eee_capability = phy_ab.eee_capability;
1889         phy_conf.eeer = phy_ab.eeer_val;
1890         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1891
1892         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1893                     phy_ab.abilities, phy_ab.link_speed);
1894         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1895                     phy_conf.abilities, phy_conf.link_speed);
1896
1897         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1898         if (status)
1899                 return ret;
1900
1901         return I40E_SUCCESS;
1902 }
1903
1904 static int
1905 i40e_apply_link_speed(struct rte_eth_dev *dev)
1906 {
1907         uint8_t speed;
1908         uint8_t abilities = 0;
1909         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910         struct rte_eth_conf *conf = &dev->data->dev_conf;
1911
1912         speed = i40e_parse_link_speeds(conf->link_speeds);
1913         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1914         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1915                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1916         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1917
1918         return i40e_phy_conf_link(hw, abilities, speed, true);
1919 }
1920
1921 static int
1922 i40e_dev_start(struct rte_eth_dev *dev)
1923 {
1924         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1925         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926         struct i40e_vsi *main_vsi = pf->main_vsi;
1927         int ret, i;
1928         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1929         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1930         uint32_t intr_vector = 0;
1931         struct i40e_vsi *vsi;
1932
1933         hw->adapter_stopped = 0;
1934
1935         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1936                 PMD_INIT_LOG(ERR,
1937                 "Invalid link_speeds for port %u, autonegotiation disabled",
1938                               dev->data->port_id);
1939                 return -EINVAL;
1940         }
1941
1942         rte_intr_disable(intr_handle);
1943
1944         if ((rte_intr_cap_multiple(intr_handle) ||
1945              !RTE_ETH_DEV_SRIOV(dev).active) &&
1946             dev->data->dev_conf.intr_conf.rxq != 0) {
1947                 intr_vector = dev->data->nb_rx_queues;
1948                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1949                 if (ret)
1950                         return ret;
1951         }
1952
1953         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1954                 intr_handle->intr_vec =
1955                         rte_zmalloc("intr_vec",
1956                                     dev->data->nb_rx_queues * sizeof(int),
1957                                     0);
1958                 if (!intr_handle->intr_vec) {
1959                         PMD_INIT_LOG(ERR,
1960                                 "Failed to allocate %d rx_queues intr_vec",
1961                                 dev->data->nb_rx_queues);
1962                         return -ENOMEM;
1963                 }
1964         }
1965
1966         /* Initialize VSI */
1967         ret = i40e_dev_rxtx_init(pf);
1968         if (ret != I40E_SUCCESS) {
1969                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1970                 goto err_up;
1971         }
1972
1973         /* Map queues with MSIX interrupt */
1974         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1975                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1976         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1977         i40e_vsi_enable_queues_intr(main_vsi);
1978
1979         /* Map VMDQ VSI queues with MSIX interrupt */
1980         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1981                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1982                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1983                                           I40E_ITR_INDEX_DEFAULT);
1984                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1985         }
1986
1987         /* enable FDIR MSIX interrupt */
1988         if (pf->fdir.fdir_vsi) {
1989                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
1990                                           I40E_ITR_INDEX_NONE);
1991                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1992         }
1993
1994         /* Enable all queues which have been configured */
1995         ret = i40e_dev_switch_queues(pf, TRUE);
1996         if (ret != I40E_SUCCESS) {
1997                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1998                 goto err_up;
1999         }
2000
2001         /* Enable receiving broadcast packets */
2002         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2003         if (ret != I40E_SUCCESS)
2004                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2005
2006         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2007                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2008                                                 true, NULL);
2009                 if (ret != I40E_SUCCESS)
2010                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2011         }
2012
2013         /* Enable the VLAN promiscuous mode. */
2014         if (pf->vfs) {
2015                 for (i = 0; i < pf->vf_num; i++) {
2016                         vsi = pf->vfs[i].vsi;
2017                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2018                                                      true, NULL);
2019                 }
2020         }
2021
2022         /* Enable mac loopback mode */
2023         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2024             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2025                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2026                 if (ret != I40E_SUCCESS) {
2027                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2028                         goto err_up;
2029                 }
2030         }
2031
2032         /* Apply link configure */
2033         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2034                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2035                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2036                                 ETH_LINK_SPEED_40G)) {
2037                 PMD_DRV_LOG(ERR, "Invalid link setting");
2038                 goto err_up;
2039         }
2040         ret = i40e_apply_link_speed(dev);
2041         if (I40E_SUCCESS != ret) {
2042                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2043                 goto err_up;
2044         }
2045
2046         if (!rte_intr_allow_others(intr_handle)) {
2047                 rte_intr_callback_unregister(intr_handle,
2048                                              i40e_dev_interrupt_handler,
2049                                              (void *)dev);
2050                 /* configure and enable device interrupt */
2051                 i40e_pf_config_irq0(hw, FALSE);
2052                 i40e_pf_enable_irq0(hw);
2053
2054                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2055                         PMD_INIT_LOG(INFO,
2056                                 "lsc won't enable because of no intr multiplex");
2057         } else {
2058                 ret = i40e_aq_set_phy_int_mask(hw,
2059                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2060                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2061                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2062                 if (ret != I40E_SUCCESS)
2063                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2064
2065                 /* Call get_link_info aq commond to enable/disable LSE */
2066                 i40e_dev_link_update(dev, 0);
2067         }
2068
2069         /* enable uio intr after callback register */
2070         rte_intr_enable(intr_handle);
2071
2072         i40e_filter_restore(pf);
2073
2074         if (pf->tm_conf.root && !pf->tm_conf.committed)
2075                 PMD_DRV_LOG(WARNING,
2076                             "please call hierarchy_commit() "
2077                             "before starting the port");
2078
2079         return I40E_SUCCESS;
2080
2081 err_up:
2082         i40e_dev_switch_queues(pf, FALSE);
2083         i40e_dev_clear_queues(dev);
2084
2085         return ret;
2086 }
2087
2088 static void
2089 i40e_dev_stop(struct rte_eth_dev *dev)
2090 {
2091         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2092         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2093         struct i40e_vsi *main_vsi = pf->main_vsi;
2094         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2095         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2096         int i;
2097
2098         if (hw->adapter_stopped == 1)
2099                 return;
2100         /* Disable all queues */
2101         i40e_dev_switch_queues(pf, FALSE);
2102
2103         /* un-map queues with interrupt registers */
2104         i40e_vsi_disable_queues_intr(main_vsi);
2105         i40e_vsi_queues_unbind_intr(main_vsi);
2106
2107         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2108                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2109                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2110         }
2111
2112         if (pf->fdir.fdir_vsi) {
2113                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2114                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2115         }
2116         /* Clear all queues and release memory */
2117         i40e_dev_clear_queues(dev);
2118
2119         /* Set link down */
2120         i40e_dev_set_link_down(dev);
2121
2122         if (!rte_intr_allow_others(intr_handle))
2123                 /* resume to the default handler */
2124                 rte_intr_callback_register(intr_handle,
2125                                            i40e_dev_interrupt_handler,
2126                                            (void *)dev);
2127
2128         /* Clean datapath event and queue/vec mapping */
2129         rte_intr_efd_disable(intr_handle);
2130         if (intr_handle->intr_vec) {
2131                 rte_free(intr_handle->intr_vec);
2132                 intr_handle->intr_vec = NULL;
2133         }
2134
2135         /* reset hierarchy commit */
2136         pf->tm_conf.committed = false;
2137
2138         /* Remove all the queue region configuration */
2139         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
2140
2141         hw->adapter_stopped = 1;
2142 }
2143
2144 static void
2145 i40e_dev_close(struct rte_eth_dev *dev)
2146 {
2147         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2148         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2150         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2151         struct i40e_mirror_rule *p_mirror;
2152         uint32_t reg;
2153         int i;
2154         int ret;
2155
2156         PMD_INIT_FUNC_TRACE();
2157
2158         i40e_dev_stop(dev);
2159
2160         /* Remove all mirror rules */
2161         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2162                 ret = i40e_aq_del_mirror_rule(hw,
2163                                               pf->main_vsi->veb->seid,
2164                                               p_mirror->rule_type,
2165                                               p_mirror->entries,
2166                                               p_mirror->num_entries,
2167                                               p_mirror->id);
2168                 if (ret < 0)
2169                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2170                                     "status = %d, aq_err = %d.", ret,
2171                                     hw->aq.asq_last_status);
2172
2173                 /* remove mirror software resource anyway */
2174                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2175                 rte_free(p_mirror);
2176                 pf->nb_mirror_rule--;
2177         }
2178
2179         i40e_dev_free_queues(dev);
2180
2181         /* Disable interrupt */
2182         i40e_pf_disable_irq0(hw);
2183         rte_intr_disable(intr_handle);
2184
2185         /* shutdown and destroy the HMC */
2186         i40e_shutdown_lan_hmc(hw);
2187
2188         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2189                 i40e_vsi_release(pf->vmdq[i].vsi);
2190                 pf->vmdq[i].vsi = NULL;
2191         }
2192         rte_free(pf->vmdq);
2193         pf->vmdq = NULL;
2194
2195         /* release all the existing VSIs and VEBs */
2196         i40e_fdir_teardown(pf);
2197         i40e_vsi_release(pf->main_vsi);
2198
2199         /* shutdown the adminq */
2200         i40e_aq_queue_shutdown(hw, true);
2201         i40e_shutdown_adminq(hw);
2202
2203         i40e_res_pool_destroy(&pf->qp_pool);
2204         i40e_res_pool_destroy(&pf->msix_pool);
2205
2206         /* force a PF reset to clean anything leftover */
2207         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2208         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2209                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2210         I40E_WRITE_FLUSH(hw);
2211 }
2212
2213 /*
2214  * Reset PF device only to re-initialize resources in PMD layer
2215  */
2216 static int
2217 i40e_dev_reset(struct rte_eth_dev *dev)
2218 {
2219         int ret;
2220
2221         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2222          * its VF to make them align with it. The detailed notification
2223          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2224          * To avoid unexpected behavior in VF, currently reset of PF with
2225          * SR-IOV activation is not supported. It might be supported later.
2226          */
2227         if (dev->data->sriov.active)
2228                 return -ENOTSUP;
2229
2230         ret = eth_i40e_dev_uninit(dev);
2231         if (ret)
2232                 return ret;
2233
2234         ret = eth_i40e_dev_init(dev);
2235
2236         return ret;
2237 }
2238
2239 static void
2240 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2241 {
2242         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2243         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2244         struct i40e_vsi *vsi = pf->main_vsi;
2245         int status;
2246
2247         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2248                                                      true, NULL, true);
2249         if (status != I40E_SUCCESS)
2250                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2251
2252         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2253                                                         TRUE, NULL);
2254         if (status != I40E_SUCCESS)
2255                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2256
2257 }
2258
2259 static void
2260 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2261 {
2262         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2263         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2264         struct i40e_vsi *vsi = pf->main_vsi;
2265         int status;
2266
2267         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2268                                                      false, NULL, true);
2269         if (status != I40E_SUCCESS)
2270                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2271
2272         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2273                                                         false, NULL);
2274         if (status != I40E_SUCCESS)
2275                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2276 }
2277
2278 static void
2279 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2280 {
2281         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2282         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2283         struct i40e_vsi *vsi = pf->main_vsi;
2284         int ret;
2285
2286         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2287         if (ret != I40E_SUCCESS)
2288                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2289 }
2290
2291 static void
2292 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2293 {
2294         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2295         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2296         struct i40e_vsi *vsi = pf->main_vsi;
2297         int ret;
2298
2299         if (dev->data->promiscuous == 1)
2300                 return; /* must remain in all_multicast mode */
2301
2302         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2303                                 vsi->seid, FALSE, NULL);
2304         if (ret != I40E_SUCCESS)
2305                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2306 }
2307
2308 /*
2309  * Set device link up.
2310  */
2311 static int
2312 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2313 {
2314         /* re-apply link speed setting */
2315         return i40e_apply_link_speed(dev);
2316 }
2317
2318 /*
2319  * Set device link down.
2320  */
2321 static int
2322 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2323 {
2324         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2325         uint8_t abilities = 0;
2326         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2327
2328         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2329         return i40e_phy_conf_link(hw, abilities, speed, false);
2330 }
2331
2332 int
2333 i40e_dev_link_update(struct rte_eth_dev *dev,
2334                      int wait_to_complete)
2335 {
2336 #define CHECK_INTERVAL 100  /* 100ms */
2337 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2338         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2339         struct i40e_link_status link_status;
2340         struct rte_eth_link link, old;
2341         int status;
2342         unsigned rep_cnt = MAX_REPEAT_TIME;
2343         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2344
2345         memset(&link, 0, sizeof(link));
2346         memset(&old, 0, sizeof(old));
2347         memset(&link_status, 0, sizeof(link_status));
2348         rte_i40e_dev_atomic_read_link_status(dev, &old);
2349
2350         do {
2351                 /* Get link status information from hardware */
2352                 status = i40e_aq_get_link_info(hw, enable_lse,
2353                                                 &link_status, NULL);
2354                 if (status != I40E_SUCCESS) {
2355                         link.link_speed = ETH_SPEED_NUM_100M;
2356                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2357                         PMD_DRV_LOG(ERR, "Failed to get link info");
2358                         goto out;
2359                 }
2360
2361                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2362                 if (!wait_to_complete || link.link_status)
2363                         break;
2364
2365                 rte_delay_ms(CHECK_INTERVAL);
2366         } while (--rep_cnt);
2367
2368         if (!link.link_status)
2369                 goto out;
2370
2371         /* i40e uses full duplex only */
2372         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2373
2374         /* Parse the link status */
2375         switch (link_status.link_speed) {
2376         case I40E_LINK_SPEED_100MB:
2377                 link.link_speed = ETH_SPEED_NUM_100M;
2378                 break;
2379         case I40E_LINK_SPEED_1GB:
2380                 link.link_speed = ETH_SPEED_NUM_1G;
2381                 break;
2382         case I40E_LINK_SPEED_10GB:
2383                 link.link_speed = ETH_SPEED_NUM_10G;
2384                 break;
2385         case I40E_LINK_SPEED_20GB:
2386                 link.link_speed = ETH_SPEED_NUM_20G;
2387                 break;
2388         case I40E_LINK_SPEED_25GB:
2389                 link.link_speed = ETH_SPEED_NUM_25G;
2390                 break;
2391         case I40E_LINK_SPEED_40GB:
2392                 link.link_speed = ETH_SPEED_NUM_40G;
2393                 break;
2394         default:
2395                 link.link_speed = ETH_SPEED_NUM_100M;
2396                 break;
2397         }
2398
2399         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2400                         ETH_LINK_SPEED_FIXED);
2401
2402 out:
2403         rte_i40e_dev_atomic_write_link_status(dev, &link);
2404         if (link.link_status == old.link_status)
2405                 return -1;
2406
2407         i40e_notify_all_vfs_link_status(dev);
2408
2409         return 0;
2410 }
2411
2412 /* Get all the statistics of a VSI */
2413 void
2414 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2415 {
2416         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2417         struct i40e_eth_stats *nes = &vsi->eth_stats;
2418         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2419         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2420
2421         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2422                             vsi->offset_loaded, &oes->rx_bytes,
2423                             &nes->rx_bytes);
2424         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2425                             vsi->offset_loaded, &oes->rx_unicast,
2426                             &nes->rx_unicast);
2427         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2428                             vsi->offset_loaded, &oes->rx_multicast,
2429                             &nes->rx_multicast);
2430         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2431                             vsi->offset_loaded, &oes->rx_broadcast,
2432                             &nes->rx_broadcast);
2433         /* exclude CRC bytes */
2434         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2435                 nes->rx_broadcast) * ETHER_CRC_LEN;
2436
2437         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2438                             &oes->rx_discards, &nes->rx_discards);
2439         /* GLV_REPC not supported */
2440         /* GLV_RMPC not supported */
2441         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2442                             &oes->rx_unknown_protocol,
2443                             &nes->rx_unknown_protocol);
2444         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2445                             vsi->offset_loaded, &oes->tx_bytes,
2446                             &nes->tx_bytes);
2447         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2448                             vsi->offset_loaded, &oes->tx_unicast,
2449                             &nes->tx_unicast);
2450         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2451                             vsi->offset_loaded, &oes->tx_multicast,
2452                             &nes->tx_multicast);
2453         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2454                             vsi->offset_loaded,  &oes->tx_broadcast,
2455                             &nes->tx_broadcast);
2456         /* GLV_TDPC not supported */
2457         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2458                             &oes->tx_errors, &nes->tx_errors);
2459         vsi->offset_loaded = true;
2460
2461         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2462                     vsi->vsi_id);
2463         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2464         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2465         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2466         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2467         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2468         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2469                     nes->rx_unknown_protocol);
2470         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2471         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2472         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2473         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2474         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2475         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2476         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2477                     vsi->vsi_id);
2478 }
2479
2480 static void
2481 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2482 {
2483         unsigned int i;
2484         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2485         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2486
2487         /* Get rx/tx bytes of internal transfer packets */
2488         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2489                         I40E_GLV_GORCL(hw->port),
2490                         pf->offset_loaded,
2491                         &pf->internal_stats_offset.rx_bytes,
2492                         &pf->internal_stats.rx_bytes);
2493
2494         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2495                         I40E_GLV_GOTCL(hw->port),
2496                         pf->offset_loaded,
2497                         &pf->internal_stats_offset.tx_bytes,
2498                         &pf->internal_stats.tx_bytes);
2499         /* Get total internal rx packet count */
2500         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2501                             I40E_GLV_UPRCL(hw->port),
2502                             pf->offset_loaded,
2503                             &pf->internal_stats_offset.rx_unicast,
2504                             &pf->internal_stats.rx_unicast);
2505         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2506                             I40E_GLV_MPRCL(hw->port),
2507                             pf->offset_loaded,
2508                             &pf->internal_stats_offset.rx_multicast,
2509                             &pf->internal_stats.rx_multicast);
2510         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2511                             I40E_GLV_BPRCL(hw->port),
2512                             pf->offset_loaded,
2513                             &pf->internal_stats_offset.rx_broadcast,
2514                             &pf->internal_stats.rx_broadcast);
2515
2516         /* exclude CRC size */
2517         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2518                 pf->internal_stats.rx_multicast +
2519                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2520
2521         /* Get statistics of struct i40e_eth_stats */
2522         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2523                             I40E_GLPRT_GORCL(hw->port),
2524                             pf->offset_loaded, &os->eth.rx_bytes,
2525                             &ns->eth.rx_bytes);
2526         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2527                             I40E_GLPRT_UPRCL(hw->port),
2528                             pf->offset_loaded, &os->eth.rx_unicast,
2529                             &ns->eth.rx_unicast);
2530         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2531                             I40E_GLPRT_MPRCL(hw->port),
2532                             pf->offset_loaded, &os->eth.rx_multicast,
2533                             &ns->eth.rx_multicast);
2534         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2535                             I40E_GLPRT_BPRCL(hw->port),
2536                             pf->offset_loaded, &os->eth.rx_broadcast,
2537                             &ns->eth.rx_broadcast);
2538         /* Workaround: CRC size should not be included in byte statistics,
2539          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2540          */
2541         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2542                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2543
2544         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2545          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2546          * value.
2547          */
2548         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2549                 ns->eth.rx_bytes = 0;
2550         /* exlude internal rx bytes */
2551         else
2552                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2553
2554         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2555                             pf->offset_loaded, &os->eth.rx_discards,
2556                             &ns->eth.rx_discards);
2557         /* GLPRT_REPC not supported */
2558         /* GLPRT_RMPC not supported */
2559         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2560                             pf->offset_loaded,
2561                             &os->eth.rx_unknown_protocol,
2562                             &ns->eth.rx_unknown_protocol);
2563         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2564                             I40E_GLPRT_GOTCL(hw->port),
2565                             pf->offset_loaded, &os->eth.tx_bytes,
2566                             &ns->eth.tx_bytes);
2567         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2568                             I40E_GLPRT_UPTCL(hw->port),
2569                             pf->offset_loaded, &os->eth.tx_unicast,
2570                             &ns->eth.tx_unicast);
2571         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2572                             I40E_GLPRT_MPTCL(hw->port),
2573                             pf->offset_loaded, &os->eth.tx_multicast,
2574                             &ns->eth.tx_multicast);
2575         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2576                             I40E_GLPRT_BPTCL(hw->port),
2577                             pf->offset_loaded, &os->eth.tx_broadcast,
2578                             &ns->eth.tx_broadcast);
2579         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2580                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2581
2582         /* exclude internal tx bytes */
2583         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2584                 ns->eth.tx_bytes = 0;
2585         else
2586                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2587
2588         /* GLPRT_TEPC not supported */
2589
2590         /* additional port specific stats */
2591         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2592                             pf->offset_loaded, &os->tx_dropped_link_down,
2593                             &ns->tx_dropped_link_down);
2594         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2595                             pf->offset_loaded, &os->crc_errors,
2596                             &ns->crc_errors);
2597         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2598                             pf->offset_loaded, &os->illegal_bytes,
2599                             &ns->illegal_bytes);
2600         /* GLPRT_ERRBC not supported */
2601         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2602                             pf->offset_loaded, &os->mac_local_faults,
2603                             &ns->mac_local_faults);
2604         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2605                             pf->offset_loaded, &os->mac_remote_faults,
2606                             &ns->mac_remote_faults);
2607         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2608                             pf->offset_loaded, &os->rx_length_errors,
2609                             &ns->rx_length_errors);
2610         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2611                             pf->offset_loaded, &os->link_xon_rx,
2612                             &ns->link_xon_rx);
2613         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2614                             pf->offset_loaded, &os->link_xoff_rx,
2615                             &ns->link_xoff_rx);
2616         for (i = 0; i < 8; i++) {
2617                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2618                                     pf->offset_loaded,
2619                                     &os->priority_xon_rx[i],
2620                                     &ns->priority_xon_rx[i]);
2621                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2622                                     pf->offset_loaded,
2623                                     &os->priority_xoff_rx[i],
2624                                     &ns->priority_xoff_rx[i]);
2625         }
2626         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2627                             pf->offset_loaded, &os->link_xon_tx,
2628                             &ns->link_xon_tx);
2629         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2630                             pf->offset_loaded, &os->link_xoff_tx,
2631                             &ns->link_xoff_tx);
2632         for (i = 0; i < 8; i++) {
2633                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2634                                     pf->offset_loaded,
2635                                     &os->priority_xon_tx[i],
2636                                     &ns->priority_xon_tx[i]);
2637                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2638                                     pf->offset_loaded,
2639                                     &os->priority_xoff_tx[i],
2640                                     &ns->priority_xoff_tx[i]);
2641                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2642                                     pf->offset_loaded,
2643                                     &os->priority_xon_2_xoff[i],
2644                                     &ns->priority_xon_2_xoff[i]);
2645         }
2646         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2647                             I40E_GLPRT_PRC64L(hw->port),
2648                             pf->offset_loaded, &os->rx_size_64,
2649                             &ns->rx_size_64);
2650         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2651                             I40E_GLPRT_PRC127L(hw->port),
2652                             pf->offset_loaded, &os->rx_size_127,
2653                             &ns->rx_size_127);
2654         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2655                             I40E_GLPRT_PRC255L(hw->port),
2656                             pf->offset_loaded, &os->rx_size_255,
2657                             &ns->rx_size_255);
2658         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2659                             I40E_GLPRT_PRC511L(hw->port),
2660                             pf->offset_loaded, &os->rx_size_511,
2661                             &ns->rx_size_511);
2662         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2663                             I40E_GLPRT_PRC1023L(hw->port),
2664                             pf->offset_loaded, &os->rx_size_1023,
2665                             &ns->rx_size_1023);
2666         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2667                             I40E_GLPRT_PRC1522L(hw->port),
2668                             pf->offset_loaded, &os->rx_size_1522,
2669                             &ns->rx_size_1522);
2670         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2671                             I40E_GLPRT_PRC9522L(hw->port),
2672                             pf->offset_loaded, &os->rx_size_big,
2673                             &ns->rx_size_big);
2674         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2675                             pf->offset_loaded, &os->rx_undersize,
2676                             &ns->rx_undersize);
2677         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2678                             pf->offset_loaded, &os->rx_fragments,
2679                             &ns->rx_fragments);
2680         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2681                             pf->offset_loaded, &os->rx_oversize,
2682                             &ns->rx_oversize);
2683         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2684                             pf->offset_loaded, &os->rx_jabber,
2685                             &ns->rx_jabber);
2686         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2687                             I40E_GLPRT_PTC64L(hw->port),
2688                             pf->offset_loaded, &os->tx_size_64,
2689                             &ns->tx_size_64);
2690         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2691                             I40E_GLPRT_PTC127L(hw->port),
2692                             pf->offset_loaded, &os->tx_size_127,
2693                             &ns->tx_size_127);
2694         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2695                             I40E_GLPRT_PTC255L(hw->port),
2696                             pf->offset_loaded, &os->tx_size_255,
2697                             &ns->tx_size_255);
2698         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2699                             I40E_GLPRT_PTC511L(hw->port),
2700                             pf->offset_loaded, &os->tx_size_511,
2701                             &ns->tx_size_511);
2702         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2703                             I40E_GLPRT_PTC1023L(hw->port),
2704                             pf->offset_loaded, &os->tx_size_1023,
2705                             &ns->tx_size_1023);
2706         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2707                             I40E_GLPRT_PTC1522L(hw->port),
2708                             pf->offset_loaded, &os->tx_size_1522,
2709                             &ns->tx_size_1522);
2710         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2711                             I40E_GLPRT_PTC9522L(hw->port),
2712                             pf->offset_loaded, &os->tx_size_big,
2713                             &ns->tx_size_big);
2714         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2715                            pf->offset_loaded,
2716                            &os->fd_sb_match, &ns->fd_sb_match);
2717         /* GLPRT_MSPDC not supported */
2718         /* GLPRT_XEC not supported */
2719
2720         pf->offset_loaded = true;
2721
2722         if (pf->main_vsi)
2723                 i40e_update_vsi_stats(pf->main_vsi);
2724 }
2725
2726 /* Get all statistics of a port */
2727 static int
2728 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2729 {
2730         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2731         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2732         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2733         unsigned i;
2734
2735         /* call read registers - updates values, now write them to struct */
2736         i40e_read_stats_registers(pf, hw);
2737
2738         stats->ipackets = ns->eth.rx_unicast +
2739                         ns->eth.rx_multicast +
2740                         ns->eth.rx_broadcast -
2741                         ns->eth.rx_discards -
2742                         pf->main_vsi->eth_stats.rx_discards;
2743         stats->opackets = ns->eth.tx_unicast +
2744                         ns->eth.tx_multicast +
2745                         ns->eth.tx_broadcast;
2746         stats->ibytes   = ns->eth.rx_bytes;
2747         stats->obytes   = ns->eth.tx_bytes;
2748         stats->oerrors  = ns->eth.tx_errors +
2749                         pf->main_vsi->eth_stats.tx_errors;
2750
2751         /* Rx Errors */
2752         stats->imissed  = ns->eth.rx_discards +
2753                         pf->main_vsi->eth_stats.rx_discards;
2754         stats->ierrors  = ns->crc_errors +
2755                         ns->rx_length_errors + ns->rx_undersize +
2756                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2757
2758         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2759         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2760         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2761         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2762         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2763         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2764         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2765                     ns->eth.rx_unknown_protocol);
2766         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2767         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2768         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2769         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2770         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2771         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2772
2773         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2774                     ns->tx_dropped_link_down);
2775         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2776         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2777                     ns->illegal_bytes);
2778         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2779         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2780                     ns->mac_local_faults);
2781         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2782                     ns->mac_remote_faults);
2783         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2784                     ns->rx_length_errors);
2785         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2786         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2787         for (i = 0; i < 8; i++) {
2788                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2789                                 i, ns->priority_xon_rx[i]);
2790                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2791                                 i, ns->priority_xoff_rx[i]);
2792         }
2793         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2794         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2795         for (i = 0; i < 8; i++) {
2796                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2797                                 i, ns->priority_xon_tx[i]);
2798                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2799                                 i, ns->priority_xoff_tx[i]);
2800                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2801                                 i, ns->priority_xon_2_xoff[i]);
2802         }
2803         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2804         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2805         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2806         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2807         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2808         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2809         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2810         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2811         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2812         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2813         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2814         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2815         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2816         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2817         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2818         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2819         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2820         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2821         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2822                         ns->mac_short_packet_dropped);
2823         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2824                     ns->checksum_error);
2825         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2826         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2827         return 0;
2828 }
2829
2830 /* Reset the statistics */
2831 static void
2832 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2833 {
2834         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2835         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2836
2837         /* Mark PF and VSI stats to update the offset, aka "reset" */
2838         pf->offset_loaded = false;
2839         if (pf->main_vsi)
2840                 pf->main_vsi->offset_loaded = false;
2841
2842         /* read the stats, reading current register values into offset */
2843         i40e_read_stats_registers(pf, hw);
2844 }
2845
2846 static uint32_t
2847 i40e_xstats_calc_num(void)
2848 {
2849         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2850                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2851                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2852 }
2853
2854 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2855                                      struct rte_eth_xstat_name *xstats_names,
2856                                      __rte_unused unsigned limit)
2857 {
2858         unsigned count = 0;
2859         unsigned i, prio;
2860
2861         if (xstats_names == NULL)
2862                 return i40e_xstats_calc_num();
2863
2864         /* Note: limit checked in rte_eth_xstats_names() */
2865
2866         /* Get stats from i40e_eth_stats struct */
2867         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2868                 snprintf(xstats_names[count].name,
2869                          sizeof(xstats_names[count].name),
2870                          "%s", rte_i40e_stats_strings[i].name);
2871                 count++;
2872         }
2873
2874         /* Get individiual stats from i40e_hw_port struct */
2875         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2876                 snprintf(xstats_names[count].name,
2877                         sizeof(xstats_names[count].name),
2878                          "%s", rte_i40e_hw_port_strings[i].name);
2879                 count++;
2880         }
2881
2882         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2883                 for (prio = 0; prio < 8; prio++) {
2884                         snprintf(xstats_names[count].name,
2885                                  sizeof(xstats_names[count].name),
2886                                  "rx_priority%u_%s", prio,
2887                                  rte_i40e_rxq_prio_strings[i].name);
2888                         count++;
2889                 }
2890         }
2891
2892         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2893                 for (prio = 0; prio < 8; prio++) {
2894                         snprintf(xstats_names[count].name,
2895                                  sizeof(xstats_names[count].name),
2896                                  "tx_priority%u_%s", prio,
2897                                  rte_i40e_txq_prio_strings[i].name);
2898                         count++;
2899                 }
2900         }
2901         return count;
2902 }
2903
2904 static int
2905 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2906                     unsigned n)
2907 {
2908         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2909         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2910         unsigned i, count, prio;
2911         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2912
2913         count = i40e_xstats_calc_num();
2914         if (n < count)
2915                 return count;
2916
2917         i40e_read_stats_registers(pf, hw);
2918
2919         if (xstats == NULL)
2920                 return 0;
2921
2922         count = 0;
2923
2924         /* Get stats from i40e_eth_stats struct */
2925         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2926                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2927                         rte_i40e_stats_strings[i].offset);
2928                 xstats[count].id = count;
2929                 count++;
2930         }
2931
2932         /* Get individiual stats from i40e_hw_port struct */
2933         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2934                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2935                         rte_i40e_hw_port_strings[i].offset);
2936                 xstats[count].id = count;
2937                 count++;
2938         }
2939
2940         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2941                 for (prio = 0; prio < 8; prio++) {
2942                         xstats[count].value =
2943                                 *(uint64_t *)(((char *)hw_stats) +
2944                                 rte_i40e_rxq_prio_strings[i].offset +
2945                                 (sizeof(uint64_t) * prio));
2946                         xstats[count].id = count;
2947                         count++;
2948                 }
2949         }
2950
2951         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2952                 for (prio = 0; prio < 8; prio++) {
2953                         xstats[count].value =
2954                                 *(uint64_t *)(((char *)hw_stats) +
2955                                 rte_i40e_txq_prio_strings[i].offset +
2956                                 (sizeof(uint64_t) * prio));
2957                         xstats[count].id = count;
2958                         count++;
2959                 }
2960         }
2961
2962         return count;
2963 }
2964
2965 static int
2966 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2967                                  __rte_unused uint16_t queue_id,
2968                                  __rte_unused uint8_t stat_idx,
2969                                  __rte_unused uint8_t is_rx)
2970 {
2971         PMD_INIT_FUNC_TRACE();
2972
2973         return -ENOSYS;
2974 }
2975
2976 static int
2977 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2978 {
2979         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2980         u32 full_ver;
2981         u8 ver, patch;
2982         u16 build;
2983         int ret;
2984
2985         full_ver = hw->nvm.oem_ver;
2986         ver = (u8)(full_ver >> 24);
2987         build = (u16)((full_ver >> 8) & 0xffff);
2988         patch = (u8)(full_ver & 0xff);
2989
2990         ret = snprintf(fw_version, fw_size,
2991                  "%d.%d%d 0x%08x %d.%d.%d",
2992                  ((hw->nvm.version >> 12) & 0xf),
2993                  ((hw->nvm.version >> 4) & 0xff),
2994                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2995                  ver, build, patch);
2996
2997         ret += 1; /* add the size of '\0' */
2998         if (fw_size < (u32)ret)
2999                 return ret;
3000         else
3001                 return 0;
3002 }
3003
3004 static void
3005 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3006 {
3007         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3008         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3009         struct i40e_vsi *vsi = pf->main_vsi;
3010         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3011
3012         dev_info->pci_dev = pci_dev;
3013         dev_info->max_rx_queues = vsi->nb_qps;
3014         dev_info->max_tx_queues = vsi->nb_qps;
3015         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3016         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3017         dev_info->max_mac_addrs = vsi->max_macaddrs;
3018         dev_info->max_vfs = pci_dev->max_vfs;
3019         dev_info->rx_offload_capa =
3020                 DEV_RX_OFFLOAD_VLAN_STRIP |
3021                 DEV_RX_OFFLOAD_QINQ_STRIP |
3022                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3023                 DEV_RX_OFFLOAD_UDP_CKSUM |
3024                 DEV_RX_OFFLOAD_TCP_CKSUM;
3025         dev_info->tx_offload_capa =
3026                 DEV_TX_OFFLOAD_VLAN_INSERT |
3027                 DEV_TX_OFFLOAD_QINQ_INSERT |
3028                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3029                 DEV_TX_OFFLOAD_UDP_CKSUM |
3030                 DEV_TX_OFFLOAD_TCP_CKSUM |
3031                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3032                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3033                 DEV_TX_OFFLOAD_TCP_TSO |
3034                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3035                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3036                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3037                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3038         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3039                                                 sizeof(uint32_t);
3040         dev_info->reta_size = pf->hash_lut_size;
3041         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3042
3043         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3044                 .rx_thresh = {
3045                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3046                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3047                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3048                 },
3049                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3050                 .rx_drop_en = 0,
3051         };
3052
3053         dev_info->default_txconf = (struct rte_eth_txconf) {
3054                 .tx_thresh = {
3055                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3056                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3057                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3058                 },
3059                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3060                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3061                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3062                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3063         };
3064
3065         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3066                 .nb_max = I40E_MAX_RING_DESC,
3067                 .nb_min = I40E_MIN_RING_DESC,
3068                 .nb_align = I40E_ALIGN_RING_DESC,
3069         };
3070
3071         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3072                 .nb_max = I40E_MAX_RING_DESC,
3073                 .nb_min = I40E_MIN_RING_DESC,
3074                 .nb_align = I40E_ALIGN_RING_DESC,
3075                 .nb_seg_max = I40E_TX_MAX_SEG,
3076                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3077         };
3078
3079         if (pf->flags & I40E_FLAG_VMDQ) {
3080                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3081                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3082                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3083                                                 pf->max_nb_vmdq_vsi;
3084                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3085                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3086                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3087         }
3088
3089         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3090                 /* For XL710 */
3091                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3092         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3093                 /* For XXV710 */
3094                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3095         else
3096                 /* For X710 */
3097                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3098 }
3099
3100 static int
3101 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3102 {
3103         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3104         struct i40e_vsi *vsi = pf->main_vsi;
3105         PMD_INIT_FUNC_TRACE();
3106
3107         if (on)
3108                 return i40e_vsi_add_vlan(vsi, vlan_id);
3109         else
3110                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3111 }
3112
3113 static int
3114 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3115                                 enum rte_vlan_type vlan_type,
3116                                 uint16_t tpid, int qinq)
3117 {
3118         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3119         uint64_t reg_r = 0;
3120         uint64_t reg_w = 0;
3121         uint16_t reg_id = 3;
3122         int ret;
3123
3124         if (qinq) {
3125                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3126                         reg_id = 2;
3127         }
3128
3129         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3130                                           &reg_r, NULL);
3131         if (ret != I40E_SUCCESS) {
3132                 PMD_DRV_LOG(ERR,
3133                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3134                            reg_id);
3135                 return -EIO;
3136         }
3137         PMD_DRV_LOG(DEBUG,
3138                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3139                     reg_id, reg_r);
3140
3141         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3142         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3143         if (reg_r == reg_w) {
3144                 PMD_DRV_LOG(DEBUG, "No need to write");
3145                 return 0;
3146         }
3147
3148         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3149                                            reg_w, NULL);
3150         if (ret != I40E_SUCCESS) {
3151                 PMD_DRV_LOG(ERR,
3152                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3153                             reg_id);
3154                 return -EIO;
3155         }
3156         PMD_DRV_LOG(DEBUG,
3157                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3158                     reg_w, reg_id);
3159
3160         return 0;
3161 }
3162
3163 static int
3164 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3165                    enum rte_vlan_type vlan_type,
3166                    uint16_t tpid)
3167 {
3168         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3169         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3170         int ret = 0;
3171
3172         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3173              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3174             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3175                 PMD_DRV_LOG(ERR,
3176                             "Unsupported vlan type.");
3177                 return -EINVAL;
3178         }
3179         /* 802.1ad frames ability is added in NVM API 1.7*/
3180         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3181                 if (qinq) {
3182                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3183                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3184                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3185                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3186                 } else {
3187                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3188                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3189                 }
3190                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3191                 if (ret != I40E_SUCCESS) {
3192                         PMD_DRV_LOG(ERR,
3193                                     "Set switch config failed aq_err: %d",
3194                                     hw->aq.asq_last_status);
3195                         ret = -EIO;
3196                 }
3197         } else
3198                 /* If NVM API < 1.7, keep the register setting */
3199                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3200                                                       tpid, qinq);
3201
3202         return ret;
3203 }
3204
3205 static int
3206 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3207 {
3208         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3209         struct i40e_vsi *vsi = pf->main_vsi;
3210
3211         if (mask & ETH_VLAN_FILTER_MASK) {
3212                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3213                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3214                 else
3215                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3216         }
3217
3218         if (mask & ETH_VLAN_STRIP_MASK) {
3219                 /* Enable or disable VLAN stripping */
3220                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3221                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3222                 else
3223                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3224         }
3225
3226         if (mask & ETH_VLAN_EXTEND_MASK) {
3227                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3228                         i40e_vsi_config_double_vlan(vsi, TRUE);
3229                         /* Set global registers with default ethertype. */
3230                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3231                                            ETHER_TYPE_VLAN);
3232                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3233                                            ETHER_TYPE_VLAN);
3234                 }
3235                 else
3236                         i40e_vsi_config_double_vlan(vsi, FALSE);
3237         }
3238
3239         return 0;
3240 }
3241
3242 static void
3243 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3244                           __rte_unused uint16_t queue,
3245                           __rte_unused int on)
3246 {
3247         PMD_INIT_FUNC_TRACE();
3248 }
3249
3250 static int
3251 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3252 {
3253         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3254         struct i40e_vsi *vsi = pf->main_vsi;
3255         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3256         struct i40e_vsi_vlan_pvid_info info;
3257
3258         memset(&info, 0, sizeof(info));
3259         info.on = on;
3260         if (info.on)
3261                 info.config.pvid = pvid;
3262         else {
3263                 info.config.reject.tagged =
3264                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3265                 info.config.reject.untagged =
3266                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3267         }
3268
3269         return i40e_vsi_vlan_pvid_set(vsi, &info);
3270 }
3271
3272 static int
3273 i40e_dev_led_on(struct rte_eth_dev *dev)
3274 {
3275         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3276         uint32_t mode = i40e_led_get(hw);
3277
3278         if (mode == 0)
3279                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3280
3281         return 0;
3282 }
3283
3284 static int
3285 i40e_dev_led_off(struct rte_eth_dev *dev)
3286 {
3287         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288         uint32_t mode = i40e_led_get(hw);
3289
3290         if (mode != 0)
3291                 i40e_led_set(hw, 0, false);
3292
3293         return 0;
3294 }
3295
3296 static int
3297 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3298 {
3299         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3301
3302         fc_conf->pause_time = pf->fc_conf.pause_time;
3303
3304         /* read out from register, in case they are modified by other port */
3305         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3306                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3307         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3308                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3309
3310         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3311         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3312
3313          /* Return current mode according to actual setting*/
3314         switch (hw->fc.current_mode) {
3315         case I40E_FC_FULL:
3316                 fc_conf->mode = RTE_FC_FULL;
3317                 break;
3318         case I40E_FC_TX_PAUSE:
3319                 fc_conf->mode = RTE_FC_TX_PAUSE;
3320                 break;
3321         case I40E_FC_RX_PAUSE:
3322                 fc_conf->mode = RTE_FC_RX_PAUSE;
3323                 break;
3324         case I40E_FC_NONE:
3325         default:
3326                 fc_conf->mode = RTE_FC_NONE;
3327         };
3328
3329         return 0;
3330 }
3331
3332 static int
3333 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3334 {
3335         uint32_t mflcn_reg, fctrl_reg, reg;
3336         uint32_t max_high_water;
3337         uint8_t i, aq_failure;
3338         int err;
3339         struct i40e_hw *hw;
3340         struct i40e_pf *pf;
3341         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3342                 [RTE_FC_NONE] = I40E_FC_NONE,
3343                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3344                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3345                 [RTE_FC_FULL] = I40E_FC_FULL
3346         };
3347
3348         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3349
3350         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3351         if ((fc_conf->high_water > max_high_water) ||
3352                         (fc_conf->high_water < fc_conf->low_water)) {
3353                 PMD_INIT_LOG(ERR,
3354                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3355                         max_high_water);
3356                 return -EINVAL;
3357         }
3358
3359         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3361         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3362
3363         pf->fc_conf.pause_time = fc_conf->pause_time;
3364         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3365         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3366
3367         PMD_INIT_FUNC_TRACE();
3368
3369         /* All the link flow control related enable/disable register
3370          * configuration is handle by the F/W
3371          */
3372         err = i40e_set_fc(hw, &aq_failure, true);
3373         if (err < 0)
3374                 return -ENOSYS;
3375
3376         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3377                 /* Configure flow control refresh threshold,
3378                  * the value for stat_tx_pause_refresh_timer[8]
3379                  * is used for global pause operation.
3380                  */
3381
3382                 I40E_WRITE_REG(hw,
3383                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3384                                pf->fc_conf.pause_time);
3385
3386                 /* configure the timer value included in transmitted pause
3387                  * frame,
3388                  * the value for stat_tx_pause_quanta[8] is used for global
3389                  * pause operation
3390                  */
3391                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3392                                pf->fc_conf.pause_time);
3393
3394                 fctrl_reg = I40E_READ_REG(hw,
3395                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3396
3397                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3398                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3399                 else
3400                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3401
3402                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3403                                fctrl_reg);
3404         } else {
3405                 /* Configure pause time (2 TCs per register) */
3406                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3407                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3408                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3409
3410                 /* Configure flow control refresh threshold value */
3411                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3412                                pf->fc_conf.pause_time / 2);
3413
3414                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3415
3416                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3417                  *depending on configuration
3418                  */
3419                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3420                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3421                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3422                 } else {
3423                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3424                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3425                 }
3426
3427                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3428         }
3429
3430         /* config the water marker both based on the packets and bytes */
3431         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3432                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3433                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3434         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3435                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3436                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3437         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3438                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3439                        << I40E_KILOSHIFT);
3440         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3441                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3442                        << I40E_KILOSHIFT);
3443
3444         I40E_WRITE_FLUSH(hw);
3445
3446         return 0;
3447 }
3448
3449 static int
3450 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3451                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3452 {
3453         PMD_INIT_FUNC_TRACE();
3454
3455         return -ENOSYS;
3456 }
3457
3458 /* Add a MAC address, and update filters */
3459 static int
3460 i40e_macaddr_add(struct rte_eth_dev *dev,
3461                  struct ether_addr *mac_addr,
3462                  __rte_unused uint32_t index,
3463                  uint32_t pool)
3464 {
3465         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3466         struct i40e_mac_filter_info mac_filter;
3467         struct i40e_vsi *vsi;
3468         int ret;
3469
3470         /* If VMDQ not enabled or configured, return */
3471         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3472                           !pf->nb_cfg_vmdq_vsi)) {
3473                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3474                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3475                         pool);
3476                 return -ENOTSUP;
3477         }
3478
3479         if (pool > pf->nb_cfg_vmdq_vsi) {
3480                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3481                                 pool, pf->nb_cfg_vmdq_vsi);
3482                 return -EINVAL;
3483         }
3484
3485         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3486         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3487                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3488         else
3489                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3490
3491         if (pool == 0)
3492                 vsi = pf->main_vsi;
3493         else
3494                 vsi = pf->vmdq[pool - 1].vsi;
3495
3496         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3497         if (ret != I40E_SUCCESS) {
3498                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3499                 return -ENODEV;
3500         }
3501         return 0;
3502 }
3503
3504 /* Remove a MAC address, and update filters */
3505 static void
3506 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3507 {
3508         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3509         struct i40e_vsi *vsi;
3510         struct rte_eth_dev_data *data = dev->data;
3511         struct ether_addr *macaddr;
3512         int ret;
3513         uint32_t i;
3514         uint64_t pool_sel;
3515
3516         macaddr = &(data->mac_addrs[index]);
3517
3518         pool_sel = dev->data->mac_pool_sel[index];
3519
3520         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3521                 if (pool_sel & (1ULL << i)) {
3522                         if (i == 0)
3523                                 vsi = pf->main_vsi;
3524                         else {
3525                                 /* No VMDQ pool enabled or configured */
3526                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3527                                         (i > pf->nb_cfg_vmdq_vsi)) {
3528                                         PMD_DRV_LOG(ERR,
3529                                                 "No VMDQ pool enabled/configured");
3530                                         return;
3531                                 }
3532                                 vsi = pf->vmdq[i - 1].vsi;
3533                         }
3534                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3535
3536                         if (ret) {
3537                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3538                                 return;
3539                         }
3540                 }
3541         }
3542 }
3543
3544 /* Set perfect match or hash match of MAC and VLAN for a VF */
3545 static int
3546 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3547                  struct rte_eth_mac_filter *filter,
3548                  bool add)
3549 {
3550         struct i40e_hw *hw;
3551         struct i40e_mac_filter_info mac_filter;
3552         struct ether_addr old_mac;
3553         struct ether_addr *new_mac;
3554         struct i40e_pf_vf *vf = NULL;
3555         uint16_t vf_id;
3556         int ret;
3557
3558         if (pf == NULL) {
3559                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3560                 return -EINVAL;
3561         }
3562         hw = I40E_PF_TO_HW(pf);
3563
3564         if (filter == NULL) {
3565                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3566                 return -EINVAL;
3567         }
3568
3569         new_mac = &filter->mac_addr;
3570
3571         if (is_zero_ether_addr(new_mac)) {
3572                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3573                 return -EINVAL;
3574         }
3575
3576         vf_id = filter->dst_id;
3577
3578         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3579                 PMD_DRV_LOG(ERR, "Invalid argument.");
3580                 return -EINVAL;
3581         }
3582         vf = &pf->vfs[vf_id];
3583
3584         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3585                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3586                 return -EINVAL;
3587         }
3588
3589         if (add) {
3590                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3591                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3592                                 ETHER_ADDR_LEN);
3593                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3594                                  ETHER_ADDR_LEN);
3595
3596                 mac_filter.filter_type = filter->filter_type;
3597                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3598                 if (ret != I40E_SUCCESS) {
3599                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3600                         return -1;
3601                 }
3602                 ether_addr_copy(new_mac, &pf->dev_addr);
3603         } else {
3604                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3605                                 ETHER_ADDR_LEN);
3606                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3607                 if (ret != I40E_SUCCESS) {
3608                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3609                         return -1;
3610                 }
3611
3612                 /* Clear device address as it has been removed */
3613                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3614                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3615         }
3616
3617         return 0;
3618 }
3619
3620 /* MAC filter handle */
3621 static int
3622 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3623                 void *arg)
3624 {
3625         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3626         struct rte_eth_mac_filter *filter;
3627         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3628         int ret = I40E_NOT_SUPPORTED;
3629
3630         filter = (struct rte_eth_mac_filter *)(arg);
3631
3632         switch (filter_op) {
3633         case RTE_ETH_FILTER_NOP:
3634                 ret = I40E_SUCCESS;
3635                 break;
3636         case RTE_ETH_FILTER_ADD:
3637                 i40e_pf_disable_irq0(hw);
3638                 if (filter->is_vf)
3639                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3640                 i40e_pf_enable_irq0(hw);
3641                 break;
3642         case RTE_ETH_FILTER_DELETE:
3643                 i40e_pf_disable_irq0(hw);
3644                 if (filter->is_vf)
3645                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3646                 i40e_pf_enable_irq0(hw);
3647                 break;
3648         default:
3649                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3650                 ret = I40E_ERR_PARAM;
3651                 break;
3652         }
3653
3654         return ret;
3655 }
3656
3657 static int
3658 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3659 {
3660         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3661         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3662         int ret;
3663
3664         if (!lut)
3665                 return -EINVAL;
3666
3667         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3668                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3669                                           lut, lut_size);
3670                 if (ret) {
3671                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3672                         return ret;
3673                 }
3674         } else {
3675                 uint32_t *lut_dw = (uint32_t *)lut;
3676                 uint16_t i, lut_size_dw = lut_size / 4;
3677
3678                 for (i = 0; i < lut_size_dw; i++)
3679                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3680         }
3681
3682         return 0;
3683 }
3684
3685 static int
3686 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3687 {
3688         struct i40e_pf *pf;
3689         struct i40e_hw *hw;
3690         int ret;
3691
3692         if (!vsi || !lut)
3693                 return -EINVAL;
3694
3695         pf = I40E_VSI_TO_PF(vsi);
3696         hw = I40E_VSI_TO_HW(vsi);
3697
3698         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3699                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3700                                           lut, lut_size);
3701                 if (ret) {
3702                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3703                         return ret;
3704                 }
3705         } else {
3706                 uint32_t *lut_dw = (uint32_t *)lut;
3707                 uint16_t i, lut_size_dw = lut_size / 4;
3708
3709                 for (i = 0; i < lut_size_dw; i++)
3710                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3711                 I40E_WRITE_FLUSH(hw);
3712         }
3713
3714         return 0;
3715 }
3716
3717 static int
3718 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3719                          struct rte_eth_rss_reta_entry64 *reta_conf,
3720                          uint16_t reta_size)
3721 {
3722         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3723         uint16_t i, lut_size = pf->hash_lut_size;
3724         uint16_t idx, shift;
3725         uint8_t *lut;
3726         int ret;
3727
3728         if (reta_size != lut_size ||
3729                 reta_size > ETH_RSS_RETA_SIZE_512) {
3730                 PMD_DRV_LOG(ERR,
3731                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3732                         reta_size, lut_size);
3733                 return -EINVAL;
3734         }
3735
3736         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3737         if (!lut) {
3738                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3739                 return -ENOMEM;
3740         }
3741         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3742         if (ret)
3743                 goto out;
3744         for (i = 0; i < reta_size; i++) {
3745                 idx = i / RTE_RETA_GROUP_SIZE;
3746                 shift = i % RTE_RETA_GROUP_SIZE;
3747                 if (reta_conf[idx].mask & (1ULL << shift))
3748                         lut[i] = reta_conf[idx].reta[shift];
3749         }
3750         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3751
3752 out:
3753         rte_free(lut);
3754
3755         return ret;
3756 }
3757
3758 static int
3759 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3760                         struct rte_eth_rss_reta_entry64 *reta_conf,
3761                         uint16_t reta_size)
3762 {
3763         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3764         uint16_t i, lut_size = pf->hash_lut_size;
3765         uint16_t idx, shift;
3766         uint8_t *lut;
3767         int ret;
3768
3769         if (reta_size != lut_size ||
3770                 reta_size > ETH_RSS_RETA_SIZE_512) {
3771                 PMD_DRV_LOG(ERR,
3772                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3773                         reta_size, lut_size);
3774                 return -EINVAL;
3775         }
3776
3777         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3778         if (!lut) {
3779                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3780                 return -ENOMEM;
3781         }
3782
3783         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3784         if (ret)
3785                 goto out;
3786         for (i = 0; i < reta_size; i++) {
3787                 idx = i / RTE_RETA_GROUP_SIZE;
3788                 shift = i % RTE_RETA_GROUP_SIZE;
3789                 if (reta_conf[idx].mask & (1ULL << shift))
3790                         reta_conf[idx].reta[shift] = lut[i];
3791         }
3792
3793 out:
3794         rte_free(lut);
3795
3796         return ret;
3797 }
3798
3799 /**
3800  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3801  * @hw:   pointer to the HW structure
3802  * @mem:  pointer to mem struct to fill out
3803  * @size: size of memory requested
3804  * @alignment: what to align the allocation to
3805  **/
3806 enum i40e_status_code
3807 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3808                         struct i40e_dma_mem *mem,
3809                         u64 size,
3810                         u32 alignment)
3811 {
3812         const struct rte_memzone *mz = NULL;
3813         char z_name[RTE_MEMZONE_NAMESIZE];
3814
3815         if (!mem)
3816                 return I40E_ERR_PARAM;
3817
3818         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3819         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3820                                          alignment, RTE_PGSIZE_2M);
3821         if (!mz)
3822                 return I40E_ERR_NO_MEMORY;
3823
3824         mem->size = size;
3825         mem->va = mz->addr;
3826         mem->pa = mz->iova;
3827         mem->zone = (const void *)mz;
3828         PMD_DRV_LOG(DEBUG,
3829                 "memzone %s allocated with physical address: %"PRIu64,
3830                 mz->name, mem->pa);
3831
3832         return I40E_SUCCESS;
3833 }
3834
3835 /**
3836  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3837  * @hw:   pointer to the HW structure
3838  * @mem:  ptr to mem struct to free
3839  **/
3840 enum i40e_status_code
3841 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3842                     struct i40e_dma_mem *mem)
3843 {
3844         if (!mem)
3845                 return I40E_ERR_PARAM;
3846
3847         PMD_DRV_LOG(DEBUG,
3848                 "memzone %s to be freed with physical address: %"PRIu64,
3849                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3850         rte_memzone_free((const struct rte_memzone *)mem->zone);
3851         mem->zone = NULL;
3852         mem->va = NULL;
3853         mem->pa = (u64)0;
3854
3855         return I40E_SUCCESS;
3856 }
3857
3858 /**
3859  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3860  * @hw:   pointer to the HW structure
3861  * @mem:  pointer to mem struct to fill out
3862  * @size: size of memory requested
3863  **/
3864 enum i40e_status_code
3865 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3866                          struct i40e_virt_mem *mem,
3867                          u32 size)
3868 {
3869         if (!mem)
3870                 return I40E_ERR_PARAM;
3871
3872         mem->size = size;
3873         mem->va = rte_zmalloc("i40e", size, 0);
3874
3875         if (mem->va)
3876                 return I40E_SUCCESS;
3877         else
3878                 return I40E_ERR_NO_MEMORY;
3879 }
3880
3881 /**
3882  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3883  * @hw:   pointer to the HW structure
3884  * @mem:  pointer to mem struct to free
3885  **/
3886 enum i40e_status_code
3887 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3888                      struct i40e_virt_mem *mem)
3889 {
3890         if (!mem)
3891                 return I40E_ERR_PARAM;
3892
3893         rte_free(mem->va);
3894         mem->va = NULL;
3895
3896         return I40E_SUCCESS;
3897 }
3898
3899 void
3900 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3901 {
3902         rte_spinlock_init(&sp->spinlock);
3903 }
3904
3905 void
3906 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3907 {
3908         rte_spinlock_lock(&sp->spinlock);
3909 }
3910
3911 void
3912 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3913 {
3914         rte_spinlock_unlock(&sp->spinlock);
3915 }
3916
3917 void
3918 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3919 {
3920         return;
3921 }
3922
3923 /**
3924  * Get the hardware capabilities, which will be parsed
3925  * and saved into struct i40e_hw.
3926  */
3927 static int
3928 i40e_get_cap(struct i40e_hw *hw)
3929 {
3930         struct i40e_aqc_list_capabilities_element_resp *buf;
3931         uint16_t len, size = 0;
3932         int ret;
3933
3934         /* Calculate a huge enough buff for saving response data temporarily */
3935         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3936                                                 I40E_MAX_CAP_ELE_NUM;
3937         buf = rte_zmalloc("i40e", len, 0);
3938         if (!buf) {
3939                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3940                 return I40E_ERR_NO_MEMORY;
3941         }
3942
3943         /* Get, parse the capabilities and save it to hw */
3944         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3945                         i40e_aqc_opc_list_func_capabilities, NULL);
3946         if (ret != I40E_SUCCESS)
3947                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3948
3949         /* Free the temporary buffer after being used */
3950         rte_free(buf);
3951
3952         return ret;
3953 }
3954
3955 static int
3956 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3957 {
3958         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3959         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3960         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3961         uint16_t qp_count = 0, vsi_count = 0;
3962
3963         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3964                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3965                 return -EINVAL;
3966         }
3967         /* Add the parameter init for LFC */
3968         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3969         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3970         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3971
3972         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3973         pf->max_num_vsi = hw->func_caps.num_vsis;
3974         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3975         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3976         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3977
3978         /* FDir queue/VSI allocation */
3979         pf->fdir_qp_offset = 0;
3980         if (hw->func_caps.fd) {
3981                 pf->flags |= I40E_FLAG_FDIR;
3982                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3983         } else {
3984                 pf->fdir_nb_qps = 0;
3985         }
3986         qp_count += pf->fdir_nb_qps;
3987         vsi_count += 1;
3988
3989         /* LAN queue/VSI allocation */
3990         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3991         if (!hw->func_caps.rss) {
3992                 pf->lan_nb_qps = 1;
3993         } else {
3994                 pf->flags |= I40E_FLAG_RSS;
3995                 if (hw->mac.type == I40E_MAC_X722)
3996                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3997                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3998         }
3999         qp_count += pf->lan_nb_qps;
4000         vsi_count += 1;
4001
4002         /* VF queue/VSI allocation */
4003         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4004         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4005                 pf->flags |= I40E_FLAG_SRIOV;
4006                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4007                 pf->vf_num = pci_dev->max_vfs;
4008                 PMD_DRV_LOG(DEBUG,
4009                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4010                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4011         } else {
4012                 pf->vf_nb_qps = 0;
4013                 pf->vf_num = 0;
4014         }
4015         qp_count += pf->vf_nb_qps * pf->vf_num;
4016         vsi_count += pf->vf_num;
4017
4018         /* VMDq queue/VSI allocation */
4019         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4020         pf->vmdq_nb_qps = 0;
4021         pf->max_nb_vmdq_vsi = 0;
4022         if (hw->func_caps.vmdq) {
4023                 if (qp_count < hw->func_caps.num_tx_qp &&
4024                         vsi_count < hw->func_caps.num_vsis) {
4025                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4026                                 qp_count) / pf->vmdq_nb_qp_max;
4027
4028                         /* Limit the maximum number of VMDq vsi to the maximum
4029                          * ethdev can support
4030                          */
4031                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4032                                 hw->func_caps.num_vsis - vsi_count);
4033                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4034                                 ETH_64_POOLS);
4035                         if (pf->max_nb_vmdq_vsi) {
4036                                 pf->flags |= I40E_FLAG_VMDQ;
4037                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4038                                 PMD_DRV_LOG(DEBUG,
4039                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4040                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4041                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4042                         } else {
4043                                 PMD_DRV_LOG(INFO,
4044                                         "No enough queues left for VMDq");
4045                         }
4046                 } else {
4047                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4048                 }
4049         }
4050         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4051         vsi_count += pf->max_nb_vmdq_vsi;
4052
4053         if (hw->func_caps.dcb)
4054                 pf->flags |= I40E_FLAG_DCB;
4055
4056         if (qp_count > hw->func_caps.num_tx_qp) {
4057                 PMD_DRV_LOG(ERR,
4058                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4059                         qp_count, hw->func_caps.num_tx_qp);
4060                 return -EINVAL;
4061         }
4062         if (vsi_count > hw->func_caps.num_vsis) {
4063                 PMD_DRV_LOG(ERR,
4064                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4065                         vsi_count, hw->func_caps.num_vsis);
4066                 return -EINVAL;
4067         }
4068
4069         return 0;
4070 }
4071
4072 static int
4073 i40e_pf_get_switch_config(struct i40e_pf *pf)
4074 {
4075         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4076         struct i40e_aqc_get_switch_config_resp *switch_config;
4077         struct i40e_aqc_switch_config_element_resp *element;
4078         uint16_t start_seid = 0, num_reported;
4079         int ret;
4080
4081         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4082                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4083         if (!switch_config) {
4084                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4085                 return -ENOMEM;
4086         }
4087
4088         /* Get the switch configurations */
4089         ret = i40e_aq_get_switch_config(hw, switch_config,
4090                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4091         if (ret != I40E_SUCCESS) {
4092                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4093                 goto fail;
4094         }
4095         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4096         if (num_reported != 1) { /* The number should be 1 */
4097                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4098                 goto fail;
4099         }
4100
4101         /* Parse the switch configuration elements */
4102         element = &(switch_config->element[0]);
4103         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4104                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4105                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4106         } else
4107                 PMD_DRV_LOG(INFO, "Unknown element type");
4108
4109 fail:
4110         rte_free(switch_config);
4111
4112         return ret;
4113 }
4114
4115 static int
4116 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4117                         uint32_t num)
4118 {
4119         struct pool_entry *entry;
4120
4121         if (pool == NULL || num == 0)
4122                 return -EINVAL;
4123
4124         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4125         if (entry == NULL) {
4126                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4127                 return -ENOMEM;
4128         }
4129
4130         /* queue heap initialize */
4131         pool->num_free = num;
4132         pool->num_alloc = 0;
4133         pool->base = base;
4134         LIST_INIT(&pool->alloc_list);
4135         LIST_INIT(&pool->free_list);
4136
4137         /* Initialize element  */
4138         entry->base = 0;
4139         entry->len = num;
4140
4141         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4142         return 0;
4143 }
4144
4145 static void
4146 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4147 {
4148         struct pool_entry *entry, *next_entry;
4149
4150         if (pool == NULL)
4151                 return;
4152
4153         for (entry = LIST_FIRST(&pool->alloc_list);
4154                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4155                         entry = next_entry) {
4156                 LIST_REMOVE(entry, next);
4157                 rte_free(entry);
4158         }
4159
4160         for (entry = LIST_FIRST(&pool->free_list);
4161                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4162                         entry = next_entry) {
4163                 LIST_REMOVE(entry, next);
4164                 rte_free(entry);
4165         }
4166
4167         pool->num_free = 0;
4168         pool->num_alloc = 0;
4169         pool->base = 0;
4170         LIST_INIT(&pool->alloc_list);
4171         LIST_INIT(&pool->free_list);
4172 }
4173
4174 static int
4175 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4176                        uint32_t base)
4177 {
4178         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4179         uint32_t pool_offset;
4180         int insert;
4181
4182         if (pool == NULL) {
4183                 PMD_DRV_LOG(ERR, "Invalid parameter");
4184                 return -EINVAL;
4185         }
4186
4187         pool_offset = base - pool->base;
4188         /* Lookup in alloc list */
4189         LIST_FOREACH(entry, &pool->alloc_list, next) {
4190                 if (entry->base == pool_offset) {
4191                         valid_entry = entry;
4192                         LIST_REMOVE(entry, next);
4193                         break;
4194                 }
4195         }
4196
4197         /* Not find, return */
4198         if (valid_entry == NULL) {
4199                 PMD_DRV_LOG(ERR, "Failed to find entry");
4200                 return -EINVAL;
4201         }
4202
4203         /**
4204          * Found it, move it to free list  and try to merge.
4205          * In order to make merge easier, always sort it by qbase.
4206          * Find adjacent prev and last entries.
4207          */
4208         prev = next = NULL;
4209         LIST_FOREACH(entry, &pool->free_list, next) {
4210                 if (entry->base > valid_entry->base) {
4211                         next = entry;
4212                         break;
4213                 }
4214                 prev = entry;
4215         }
4216
4217         insert = 0;
4218         /* Try to merge with next one*/
4219         if (next != NULL) {
4220                 /* Merge with next one */
4221                 if (valid_entry->base + valid_entry->len == next->base) {
4222                         next->base = valid_entry->base;
4223                         next->len += valid_entry->len;
4224                         rte_free(valid_entry);
4225                         valid_entry = next;
4226                         insert = 1;
4227                 }
4228         }
4229
4230         if (prev != NULL) {
4231                 /* Merge with previous one */
4232                 if (prev->base + prev->len == valid_entry->base) {
4233                         prev->len += valid_entry->len;
4234                         /* If it merge with next one, remove next node */
4235                         if (insert == 1) {
4236                                 LIST_REMOVE(valid_entry, next);
4237                                 rte_free(valid_entry);
4238                         } else {
4239                                 rte_free(valid_entry);
4240                                 insert = 1;
4241                         }
4242                 }
4243         }
4244
4245         /* Not find any entry to merge, insert */
4246         if (insert == 0) {
4247                 if (prev != NULL)
4248                         LIST_INSERT_AFTER(prev, valid_entry, next);
4249                 else if (next != NULL)
4250                         LIST_INSERT_BEFORE(next, valid_entry, next);
4251                 else /* It's empty list, insert to head */
4252                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4253         }
4254
4255         pool->num_free += valid_entry->len;
4256         pool->num_alloc -= valid_entry->len;
4257
4258         return 0;
4259 }
4260
4261 static int
4262 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4263                        uint16_t num)
4264 {
4265         struct pool_entry *entry, *valid_entry;
4266
4267         if (pool == NULL || num == 0) {
4268                 PMD_DRV_LOG(ERR, "Invalid parameter");
4269                 return -EINVAL;
4270         }
4271
4272         if (pool->num_free < num) {
4273                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4274                             num, pool->num_free);
4275                 return -ENOMEM;
4276         }
4277
4278         valid_entry = NULL;
4279         /* Lookup  in free list and find most fit one */
4280         LIST_FOREACH(entry, &pool->free_list, next) {
4281                 if (entry->len >= num) {
4282                         /* Find best one */
4283                         if (entry->len == num) {
4284                                 valid_entry = entry;
4285                                 break;
4286                         }
4287                         if (valid_entry == NULL || valid_entry->len > entry->len)
4288                                 valid_entry = entry;
4289                 }
4290         }
4291
4292         /* Not find one to satisfy the request, return */
4293         if (valid_entry == NULL) {
4294                 PMD_DRV_LOG(ERR, "No valid entry found");
4295                 return -ENOMEM;
4296         }
4297         /**
4298          * The entry have equal queue number as requested,
4299          * remove it from alloc_list.
4300          */
4301         if (valid_entry->len == num) {
4302                 LIST_REMOVE(valid_entry, next);
4303         } else {
4304                 /**
4305                  * The entry have more numbers than requested,
4306                  * create a new entry for alloc_list and minus its
4307                  * queue base and number in free_list.
4308                  */
4309                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4310                 if (entry == NULL) {
4311                         PMD_DRV_LOG(ERR,
4312                                 "Failed to allocate memory for resource pool");
4313                         return -ENOMEM;
4314                 }
4315                 entry->base = valid_entry->base;
4316                 entry->len = num;
4317                 valid_entry->base += num;
4318                 valid_entry->len -= num;
4319                 valid_entry = entry;
4320         }
4321
4322         /* Insert it into alloc list, not sorted */
4323         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4324
4325         pool->num_free -= valid_entry->len;
4326         pool->num_alloc += valid_entry->len;
4327
4328         return valid_entry->base + pool->base;
4329 }
4330
4331 /**
4332  * bitmap_is_subset - Check whether src2 is subset of src1
4333  **/
4334 static inline int
4335 bitmap_is_subset(uint8_t src1, uint8_t src2)
4336 {
4337         return !((src1 ^ src2) & src2);
4338 }
4339
4340 static enum i40e_status_code
4341 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4342 {
4343         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4344
4345         /* If DCB is not supported, only default TC is supported */
4346         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4347                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4348                 return I40E_NOT_SUPPORTED;
4349         }
4350
4351         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4352                 PMD_DRV_LOG(ERR,
4353                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4354                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4355                 return I40E_NOT_SUPPORTED;
4356         }
4357         return I40E_SUCCESS;
4358 }
4359
4360 int
4361 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4362                                 struct i40e_vsi_vlan_pvid_info *info)
4363 {
4364         struct i40e_hw *hw;
4365         struct i40e_vsi_context ctxt;
4366         uint8_t vlan_flags = 0;
4367         int ret;
4368
4369         if (vsi == NULL || info == NULL) {
4370                 PMD_DRV_LOG(ERR, "invalid parameters");
4371                 return I40E_ERR_PARAM;
4372         }
4373
4374         if (info->on) {
4375                 vsi->info.pvid = info->config.pvid;
4376                 /**
4377                  * If insert pvid is enabled, only tagged pkts are
4378                  * allowed to be sent out.
4379                  */
4380                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4381                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4382         } else {
4383                 vsi->info.pvid = 0;
4384                 if (info->config.reject.tagged == 0)
4385                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4386
4387                 if (info->config.reject.untagged == 0)
4388                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4389         }
4390         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4391                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4392         vsi->info.port_vlan_flags |= vlan_flags;
4393         vsi->info.valid_sections =
4394                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4395         memset(&ctxt, 0, sizeof(ctxt));
4396         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4397         ctxt.seid = vsi->seid;
4398
4399         hw = I40E_VSI_TO_HW(vsi);
4400         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4401         if (ret != I40E_SUCCESS)
4402                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4403
4404         return ret;
4405 }
4406
4407 static int
4408 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4409 {
4410         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4411         int i, ret;
4412         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4413
4414         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4415         if (ret != I40E_SUCCESS)
4416                 return ret;
4417
4418         if (!vsi->seid) {
4419                 PMD_DRV_LOG(ERR, "seid not valid");
4420                 return -EINVAL;
4421         }
4422
4423         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4424         tc_bw_data.tc_valid_bits = enabled_tcmap;
4425         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4426                 tc_bw_data.tc_bw_credits[i] =
4427                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4428
4429         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4430         if (ret != I40E_SUCCESS) {
4431                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4432                 return ret;
4433         }
4434
4435         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4436                                         sizeof(vsi->info.qs_handle));
4437         return I40E_SUCCESS;
4438 }
4439
4440 static enum i40e_status_code
4441 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4442                                  struct i40e_aqc_vsi_properties_data *info,
4443                                  uint8_t enabled_tcmap)
4444 {
4445         enum i40e_status_code ret;
4446         int i, total_tc = 0;
4447         uint16_t qpnum_per_tc, bsf, qp_idx;
4448
4449         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4450         if (ret != I40E_SUCCESS)
4451                 return ret;
4452
4453         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4454                 if (enabled_tcmap & (1 << i))
4455                         total_tc++;
4456         if (total_tc == 0)
4457                 total_tc = 1;
4458         vsi->enabled_tc = enabled_tcmap;
4459
4460         /* Number of queues per enabled TC */
4461         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4462         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4463         bsf = rte_bsf32(qpnum_per_tc);
4464
4465         /* Adjust the queue number to actual queues that can be applied */
4466         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4467                 vsi->nb_qps = qpnum_per_tc * total_tc;
4468
4469         /**
4470          * Configure TC and queue mapping parameters, for enabled TC,
4471          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4472          * default queue will serve it.
4473          */
4474         qp_idx = 0;
4475         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4476                 if (vsi->enabled_tc & (1 << i)) {
4477                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4478                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4479                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4480                         qp_idx += qpnum_per_tc;
4481                 } else
4482                         info->tc_mapping[i] = 0;
4483         }
4484
4485         /* Associate queue number with VSI */
4486         if (vsi->type == I40E_VSI_SRIOV) {
4487                 info->mapping_flags |=
4488                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4489                 for (i = 0; i < vsi->nb_qps; i++)
4490                         info->queue_mapping[i] =
4491                                 rte_cpu_to_le_16(vsi->base_queue + i);
4492         } else {
4493                 info->mapping_flags |=
4494                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4495                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4496         }
4497         info->valid_sections |=
4498                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4499
4500         return I40E_SUCCESS;
4501 }
4502
4503 static int
4504 i40e_veb_release(struct i40e_veb *veb)
4505 {
4506         struct i40e_vsi *vsi;
4507         struct i40e_hw *hw;
4508
4509         if (veb == NULL)
4510                 return -EINVAL;
4511
4512         if (!TAILQ_EMPTY(&veb->head)) {
4513                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4514                 return -EACCES;
4515         }
4516         /* associate_vsi field is NULL for floating VEB */
4517         if (veb->associate_vsi != NULL) {
4518                 vsi = veb->associate_vsi;
4519                 hw = I40E_VSI_TO_HW(vsi);
4520
4521                 vsi->uplink_seid = veb->uplink_seid;
4522                 vsi->veb = NULL;
4523         } else {
4524                 veb->associate_pf->main_vsi->floating_veb = NULL;
4525                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4526         }
4527
4528         i40e_aq_delete_element(hw, veb->seid, NULL);
4529         rte_free(veb);
4530         return I40E_SUCCESS;
4531 }
4532
4533 /* Setup a veb */
4534 static struct i40e_veb *
4535 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4536 {
4537         struct i40e_veb *veb;
4538         int ret;
4539         struct i40e_hw *hw;
4540
4541         if (pf == NULL) {
4542                 PMD_DRV_LOG(ERR,
4543                             "veb setup failed, associated PF shouldn't null");
4544                 return NULL;
4545         }
4546         hw = I40E_PF_TO_HW(pf);
4547
4548         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4549         if (!veb) {
4550                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4551                 goto fail;
4552         }
4553
4554         veb->associate_vsi = vsi;
4555         veb->associate_pf = pf;
4556         TAILQ_INIT(&veb->head);
4557         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4558
4559         /* create floating veb if vsi is NULL */
4560         if (vsi != NULL) {
4561                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4562                                       I40E_DEFAULT_TCMAP, false,
4563                                       &veb->seid, false, NULL);
4564         } else {
4565                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4566                                       true, &veb->seid, false, NULL);
4567         }
4568
4569         if (ret != I40E_SUCCESS) {
4570                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4571                             hw->aq.asq_last_status);
4572                 goto fail;
4573         }
4574         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4575
4576         /* get statistics index */
4577         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4578                                 &veb->stats_idx, NULL, NULL, NULL);
4579         if (ret != I40E_SUCCESS) {
4580                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4581                             hw->aq.asq_last_status);
4582                 goto fail;
4583         }
4584         /* Get VEB bandwidth, to be implemented */
4585         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4586         if (vsi)
4587                 vsi->uplink_seid = veb->seid;
4588
4589         return veb;
4590 fail:
4591         rte_free(veb);
4592         return NULL;
4593 }
4594
4595 int
4596 i40e_vsi_release(struct i40e_vsi *vsi)
4597 {
4598         struct i40e_pf *pf;
4599         struct i40e_hw *hw;
4600         struct i40e_vsi_list *vsi_list;
4601         void *temp;
4602         int ret;
4603         struct i40e_mac_filter *f;
4604         uint16_t user_param;
4605
4606         if (!vsi)
4607                 return I40E_SUCCESS;
4608
4609         if (!vsi->adapter)
4610                 return -EFAULT;
4611
4612         user_param = vsi->user_param;
4613
4614         pf = I40E_VSI_TO_PF(vsi);
4615         hw = I40E_VSI_TO_HW(vsi);
4616
4617         /* VSI has child to attach, release child first */
4618         if (vsi->veb) {
4619                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4620                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4621                                 return -1;
4622                 }
4623                 i40e_veb_release(vsi->veb);
4624         }
4625
4626         if (vsi->floating_veb) {
4627                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4628                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4629                                 return -1;
4630                 }
4631         }
4632
4633         /* Remove all macvlan filters of the VSI */
4634         i40e_vsi_remove_all_macvlan_filter(vsi);
4635         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4636                 rte_free(f);
4637
4638         if (vsi->type != I40E_VSI_MAIN &&
4639             ((vsi->type != I40E_VSI_SRIOV) ||
4640             !pf->floating_veb_list[user_param])) {
4641                 /* Remove vsi from parent's sibling list */
4642                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4643                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4644                         return I40E_ERR_PARAM;
4645                 }
4646                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4647                                 &vsi->sib_vsi_list, list);
4648
4649                 /* Remove all switch element of the VSI */
4650                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4651                 if (ret != I40E_SUCCESS)
4652                         PMD_DRV_LOG(ERR, "Failed to delete element");
4653         }
4654
4655         if ((vsi->type == I40E_VSI_SRIOV) &&
4656             pf->floating_veb_list[user_param]) {
4657                 /* Remove vsi from parent's sibling list */
4658                 if (vsi->parent_vsi == NULL ||
4659                     vsi->parent_vsi->floating_veb == NULL) {
4660                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4661                         return I40E_ERR_PARAM;
4662                 }
4663                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4664                              &vsi->sib_vsi_list, list);
4665
4666                 /* Remove all switch element of the VSI */
4667                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4668                 if (ret != I40E_SUCCESS)
4669                         PMD_DRV_LOG(ERR, "Failed to delete element");
4670         }
4671
4672         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4673
4674         if (vsi->type != I40E_VSI_SRIOV)
4675                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4676         rte_free(vsi);
4677
4678         return I40E_SUCCESS;
4679 }
4680
4681 static int
4682 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4683 {
4684         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4685         struct i40e_aqc_remove_macvlan_element_data def_filter;
4686         struct i40e_mac_filter_info filter;
4687         int ret;
4688
4689         if (vsi->type != I40E_VSI_MAIN)
4690                 return I40E_ERR_CONFIG;
4691         memset(&def_filter, 0, sizeof(def_filter));
4692         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4693                                         ETH_ADDR_LEN);
4694         def_filter.vlan_tag = 0;
4695         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4696                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4697         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4698         if (ret != I40E_SUCCESS) {
4699                 struct i40e_mac_filter *f;
4700                 struct ether_addr *mac;
4701
4702                 PMD_DRV_LOG(DEBUG,
4703                             "Cannot remove the default macvlan filter");
4704                 /* It needs to add the permanent mac into mac list */
4705                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4706                 if (f == NULL) {
4707                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4708                         return I40E_ERR_NO_MEMORY;
4709                 }
4710                 mac = &f->mac_info.mac_addr;
4711                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4712                                 ETH_ADDR_LEN);
4713                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4714                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4715                 vsi->mac_num++;
4716
4717                 return ret;
4718         }
4719         rte_memcpy(&filter.mac_addr,
4720                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4721         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4722         return i40e_vsi_add_mac(vsi, &filter);
4723 }
4724
4725 /*
4726  * i40e_vsi_get_bw_config - Query VSI BW Information
4727  * @vsi: the VSI to be queried
4728  *
4729  * Returns 0 on success, negative value on failure
4730  */
4731 static enum i40e_status_code
4732 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4733 {
4734         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4735         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4736         struct i40e_hw *hw = &vsi->adapter->hw;
4737         i40e_status ret;
4738         int i;
4739         uint32_t bw_max;
4740
4741         memset(&bw_config, 0, sizeof(bw_config));
4742         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4743         if (ret != I40E_SUCCESS) {
4744                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4745                             hw->aq.asq_last_status);
4746                 return ret;
4747         }
4748
4749         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4750         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4751                                         &ets_sla_config, NULL);
4752         if (ret != I40E_SUCCESS) {
4753                 PMD_DRV_LOG(ERR,
4754                         "VSI failed to get TC bandwdith configuration %u",
4755                         hw->aq.asq_last_status);
4756                 return ret;
4757         }
4758
4759         /* store and print out BW info */
4760         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4761         vsi->bw_info.bw_max = bw_config.max_bw;
4762         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4763         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4764         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4765                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4766                      I40E_16_BIT_WIDTH);
4767         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4768                 vsi->bw_info.bw_ets_share_credits[i] =
4769                                 ets_sla_config.share_credits[i];
4770                 vsi->bw_info.bw_ets_credits[i] =
4771                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4772                 /* 4 bits per TC, 4th bit is reserved */
4773                 vsi->bw_info.bw_ets_max[i] =
4774                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4775                                   RTE_LEN2MASK(3, uint8_t));
4776                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4777                             vsi->bw_info.bw_ets_share_credits[i]);
4778                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4779                             vsi->bw_info.bw_ets_credits[i]);
4780                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4781                             vsi->bw_info.bw_ets_max[i]);
4782         }
4783
4784         return I40E_SUCCESS;
4785 }
4786
4787 /* i40e_enable_pf_lb
4788  * @pf: pointer to the pf structure
4789  *
4790  * allow loopback on pf
4791  */
4792 static inline void
4793 i40e_enable_pf_lb(struct i40e_pf *pf)
4794 {
4795         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4796         struct i40e_vsi_context ctxt;
4797         int ret;
4798
4799         /* Use the FW API if FW >= v5.0 */
4800         if (hw->aq.fw_maj_ver < 5) {
4801                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4802                 return;
4803         }
4804
4805         memset(&ctxt, 0, sizeof(ctxt));
4806         ctxt.seid = pf->main_vsi_seid;
4807         ctxt.pf_num = hw->pf_id;
4808         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4809         if (ret) {
4810                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4811                             ret, hw->aq.asq_last_status);
4812                 return;
4813         }
4814         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4815         ctxt.info.valid_sections =
4816                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4817         ctxt.info.switch_id |=
4818                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4819
4820         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4821         if (ret)
4822                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4823                             hw->aq.asq_last_status);
4824 }
4825
4826 /* Setup a VSI */
4827 struct i40e_vsi *
4828 i40e_vsi_setup(struct i40e_pf *pf,
4829                enum i40e_vsi_type type,
4830                struct i40e_vsi *uplink_vsi,
4831                uint16_t user_param)
4832 {
4833         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4834         struct i40e_vsi *vsi;
4835         struct i40e_mac_filter_info filter;
4836         int ret;
4837         struct i40e_vsi_context ctxt;
4838         struct ether_addr broadcast =
4839                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4840
4841         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4842             uplink_vsi == NULL) {
4843                 PMD_DRV_LOG(ERR,
4844                         "VSI setup failed, VSI link shouldn't be NULL");
4845                 return NULL;
4846         }
4847
4848         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4849                 PMD_DRV_LOG(ERR,
4850                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4851                 return NULL;
4852         }
4853
4854         /* two situations
4855          * 1.type is not MAIN and uplink vsi is not NULL
4856          * If uplink vsi didn't setup VEB, create one first under veb field
4857          * 2.type is SRIOV and the uplink is NULL
4858          * If floating VEB is NULL, create one veb under floating veb field
4859          */
4860
4861         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4862             uplink_vsi->veb == NULL) {
4863                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4864
4865                 if (uplink_vsi->veb == NULL) {
4866                         PMD_DRV_LOG(ERR, "VEB setup failed");
4867                         return NULL;
4868                 }
4869                 /* set ALLOWLOOPBACk on pf, when veb is created */
4870                 i40e_enable_pf_lb(pf);
4871         }
4872
4873         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4874             pf->main_vsi->floating_veb == NULL) {
4875                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4876
4877                 if (pf->main_vsi->floating_veb == NULL) {
4878                         PMD_DRV_LOG(ERR, "VEB setup failed");
4879                         return NULL;
4880                 }
4881         }
4882
4883         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4884         if (!vsi) {
4885                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4886                 return NULL;
4887         }
4888         TAILQ_INIT(&vsi->mac_list);
4889         vsi->type = type;
4890         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4891         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4892         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4893         vsi->user_param = user_param;
4894         vsi->vlan_anti_spoof_on = 0;
4895         vsi->vlan_filter_on = 0;
4896         /* Allocate queues */
4897         switch (vsi->type) {
4898         case I40E_VSI_MAIN  :
4899                 vsi->nb_qps = pf->lan_nb_qps;
4900                 break;
4901         case I40E_VSI_SRIOV :
4902                 vsi->nb_qps = pf->vf_nb_qps;
4903                 break;
4904         case I40E_VSI_VMDQ2:
4905                 vsi->nb_qps = pf->vmdq_nb_qps;
4906                 break;
4907         case I40E_VSI_FDIR:
4908                 vsi->nb_qps = pf->fdir_nb_qps;
4909                 break;
4910         default:
4911                 goto fail_mem;
4912         }
4913         /*
4914          * The filter status descriptor is reported in rx queue 0,
4915          * while the tx queue for fdir filter programming has no
4916          * such constraints, can be non-zero queues.
4917          * To simplify it, choose FDIR vsi use queue 0 pair.
4918          * To make sure it will use queue 0 pair, queue allocation
4919          * need be done before this function is called
4920          */
4921         if (type != I40E_VSI_FDIR) {
4922                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4923                         if (ret < 0) {
4924                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4925                                                 vsi->seid, ret);
4926                                 goto fail_mem;
4927                         }
4928                         vsi->base_queue = ret;
4929         } else
4930                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4931
4932         /* VF has MSIX interrupt in VF range, don't allocate here */
4933         if (type == I40E_VSI_MAIN) {
4934                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4935                                           RTE_MIN(vsi->nb_qps,
4936                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4937                 if (ret < 0) {
4938                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4939                                     vsi->seid, ret);
4940                         goto fail_queue_alloc;
4941                 }
4942                 vsi->msix_intr = ret;
4943                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4944         } else if (type != I40E_VSI_SRIOV) {
4945                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4946                 if (ret < 0) {
4947                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4948                         goto fail_queue_alloc;
4949                 }
4950                 vsi->msix_intr = ret;
4951                 vsi->nb_msix = 1;
4952         } else {
4953                 vsi->msix_intr = 0;
4954                 vsi->nb_msix = 0;
4955         }
4956
4957         /* Add VSI */
4958         if (type == I40E_VSI_MAIN) {
4959                 /* For main VSI, no need to add since it's default one */
4960                 vsi->uplink_seid = pf->mac_seid;
4961                 vsi->seid = pf->main_vsi_seid;
4962                 /* Bind queues with specific MSIX interrupt */
4963                 /**
4964                  * Needs 2 interrupt at least, one for misc cause which will
4965                  * enabled from OS side, Another for queues binding the
4966                  * interrupt from device side only.
4967                  */
4968
4969                 /* Get default VSI parameters from hardware */
4970                 memset(&ctxt, 0, sizeof(ctxt));
4971                 ctxt.seid = vsi->seid;
4972                 ctxt.pf_num = hw->pf_id;
4973                 ctxt.uplink_seid = vsi->uplink_seid;
4974                 ctxt.vf_num = 0;
4975                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4976                 if (ret != I40E_SUCCESS) {
4977                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4978                         goto fail_msix_alloc;
4979                 }
4980                 rte_memcpy(&vsi->info, &ctxt.info,
4981                         sizeof(struct i40e_aqc_vsi_properties_data));
4982                 vsi->vsi_id = ctxt.vsi_number;
4983                 vsi->info.valid_sections = 0;
4984
4985                 /* Configure tc, enabled TC0 only */
4986                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4987                         I40E_SUCCESS) {
4988                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4989                         goto fail_msix_alloc;
4990                 }
4991
4992                 /* TC, queue mapping */
4993                 memset(&ctxt, 0, sizeof(ctxt));
4994                 vsi->info.valid_sections |=
4995                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4996                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4997                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4998                 rte_memcpy(&ctxt.info, &vsi->info,
4999                         sizeof(struct i40e_aqc_vsi_properties_data));
5000                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5001                                                 I40E_DEFAULT_TCMAP);
5002                 if (ret != I40E_SUCCESS) {
5003                         PMD_DRV_LOG(ERR,
5004                                 "Failed to configure TC queue mapping");
5005                         goto fail_msix_alloc;
5006                 }
5007                 ctxt.seid = vsi->seid;
5008                 ctxt.pf_num = hw->pf_id;
5009                 ctxt.uplink_seid = vsi->uplink_seid;
5010                 ctxt.vf_num = 0;
5011
5012                 /* Update VSI parameters */
5013                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5014                 if (ret != I40E_SUCCESS) {
5015                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5016                         goto fail_msix_alloc;
5017                 }
5018
5019                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5020                                                 sizeof(vsi->info.tc_mapping));
5021                 rte_memcpy(&vsi->info.queue_mapping,
5022                                 &ctxt.info.queue_mapping,
5023                         sizeof(vsi->info.queue_mapping));
5024                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5025                 vsi->info.valid_sections = 0;
5026
5027                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5028                                 ETH_ADDR_LEN);
5029
5030                 /**
5031                  * Updating default filter settings are necessary to prevent
5032                  * reception of tagged packets.
5033                  * Some old firmware configurations load a default macvlan
5034                  * filter which accepts both tagged and untagged packets.
5035                  * The updating is to use a normal filter instead if needed.
5036                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5037                  * The firmware with correct configurations load the default
5038                  * macvlan filter which is expected and cannot be removed.
5039                  */
5040                 i40e_update_default_filter_setting(vsi);
5041                 i40e_config_qinq(hw, vsi);
5042         } else if (type == I40E_VSI_SRIOV) {
5043                 memset(&ctxt, 0, sizeof(ctxt));
5044                 /**
5045                  * For other VSI, the uplink_seid equals to uplink VSI's
5046                  * uplink_seid since they share same VEB
5047                  */
5048                 if (uplink_vsi == NULL)
5049                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5050                 else
5051                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5052                 ctxt.pf_num = hw->pf_id;
5053                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5054                 ctxt.uplink_seid = vsi->uplink_seid;
5055                 ctxt.connection_type = 0x1;
5056                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5057
5058                 /* Use the VEB configuration if FW >= v5.0 */
5059                 if (hw->aq.fw_maj_ver >= 5) {
5060                         /* Configure switch ID */
5061                         ctxt.info.valid_sections |=
5062                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5063                         ctxt.info.switch_id =
5064                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5065                 }
5066
5067                 /* Configure port/vlan */
5068                 ctxt.info.valid_sections |=
5069                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5070                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5071                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5072                                                 hw->func_caps.enabled_tcmap);
5073                 if (ret != I40E_SUCCESS) {
5074                         PMD_DRV_LOG(ERR,
5075                                 "Failed to configure TC queue mapping");
5076                         goto fail_msix_alloc;
5077                 }
5078
5079                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5080                 ctxt.info.valid_sections |=
5081                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5082                 /**
5083                  * Since VSI is not created yet, only configure parameter,
5084                  * will add vsi below.
5085                  */
5086
5087                 i40e_config_qinq(hw, vsi);
5088         } else if (type == I40E_VSI_VMDQ2) {
5089                 memset(&ctxt, 0, sizeof(ctxt));
5090                 /*
5091                  * For other VSI, the uplink_seid equals to uplink VSI's
5092                  * uplink_seid since they share same VEB
5093                  */
5094                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5095                 ctxt.pf_num = hw->pf_id;
5096                 ctxt.vf_num = 0;
5097                 ctxt.uplink_seid = vsi->uplink_seid;
5098                 ctxt.connection_type = 0x1;
5099                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5100
5101                 ctxt.info.valid_sections |=
5102                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5103                 /* user_param carries flag to enable loop back */
5104                 if (user_param) {
5105                         ctxt.info.switch_id =
5106                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5107                         ctxt.info.switch_id |=
5108                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5109                 }
5110
5111                 /* Configure port/vlan */
5112                 ctxt.info.valid_sections |=
5113                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5114                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5115                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5116                                                 I40E_DEFAULT_TCMAP);
5117                 if (ret != I40E_SUCCESS) {
5118                         PMD_DRV_LOG(ERR,
5119                                 "Failed to configure TC queue mapping");
5120                         goto fail_msix_alloc;
5121                 }
5122                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5123                 ctxt.info.valid_sections |=
5124                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5125         } else if (type == I40E_VSI_FDIR) {
5126                 memset(&ctxt, 0, sizeof(ctxt));
5127                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5128                 ctxt.pf_num = hw->pf_id;
5129                 ctxt.vf_num = 0;
5130                 ctxt.uplink_seid = vsi->uplink_seid;
5131                 ctxt.connection_type = 0x1;     /* regular data port */
5132                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5133                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5134                                                 I40E_DEFAULT_TCMAP);
5135                 if (ret != I40E_SUCCESS) {
5136                         PMD_DRV_LOG(ERR,
5137                                 "Failed to configure TC queue mapping.");
5138                         goto fail_msix_alloc;
5139                 }
5140                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5141                 ctxt.info.valid_sections |=
5142                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5143         } else {
5144                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5145                 goto fail_msix_alloc;
5146         }
5147
5148         if (vsi->type != I40E_VSI_MAIN) {
5149                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5150                 if (ret != I40E_SUCCESS) {
5151                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5152                                     hw->aq.asq_last_status);
5153                         goto fail_msix_alloc;
5154                 }
5155                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5156                 vsi->info.valid_sections = 0;
5157                 vsi->seid = ctxt.seid;
5158                 vsi->vsi_id = ctxt.vsi_number;
5159                 vsi->sib_vsi_list.vsi = vsi;
5160                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5161                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5162                                           &vsi->sib_vsi_list, list);
5163                 } else {
5164                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5165                                           &vsi->sib_vsi_list, list);
5166                 }
5167         }
5168
5169         /* MAC/VLAN configuration */
5170         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5171         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5172
5173         ret = i40e_vsi_add_mac(vsi, &filter);
5174         if (ret != I40E_SUCCESS) {
5175                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5176                 goto fail_msix_alloc;
5177         }
5178
5179         /* Get VSI BW information */
5180         i40e_vsi_get_bw_config(vsi);
5181         return vsi;
5182 fail_msix_alloc:
5183         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5184 fail_queue_alloc:
5185         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5186 fail_mem:
5187         rte_free(vsi);
5188         return NULL;
5189 }
5190
5191 /* Configure vlan filter on or off */
5192 int
5193 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5194 {
5195         int i, num;
5196         struct i40e_mac_filter *f;
5197         void *temp;
5198         struct i40e_mac_filter_info *mac_filter;
5199         enum rte_mac_filter_type desired_filter;
5200         int ret = I40E_SUCCESS;
5201
5202         if (on) {
5203                 /* Filter to match MAC and VLAN */
5204                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5205         } else {
5206                 /* Filter to match only MAC */
5207                 desired_filter = RTE_MAC_PERFECT_MATCH;
5208         }
5209
5210         num = vsi->mac_num;
5211
5212         mac_filter = rte_zmalloc("mac_filter_info_data",
5213                                  num * sizeof(*mac_filter), 0);
5214         if (mac_filter == NULL) {
5215                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5216                 return I40E_ERR_NO_MEMORY;
5217         }
5218
5219         i = 0;
5220
5221         /* Remove all existing mac */
5222         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5223                 mac_filter[i] = f->mac_info;
5224                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5225                 if (ret) {
5226                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5227                                     on ? "enable" : "disable");
5228                         goto DONE;
5229                 }
5230                 i++;
5231         }
5232
5233         /* Override with new filter */
5234         for (i = 0; i < num; i++) {
5235                 mac_filter[i].filter_type = desired_filter;
5236                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5237                 if (ret) {
5238                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5239                                     on ? "enable" : "disable");
5240                         goto DONE;
5241                 }
5242         }
5243
5244 DONE:
5245         rte_free(mac_filter);
5246         return ret;
5247 }
5248
5249 /* Configure vlan stripping on or off */
5250 int
5251 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5252 {
5253         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5254         struct i40e_vsi_context ctxt;
5255         uint8_t vlan_flags;
5256         int ret = I40E_SUCCESS;
5257
5258         /* Check if it has been already on or off */
5259         if (vsi->info.valid_sections &
5260                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5261                 if (on) {
5262                         if ((vsi->info.port_vlan_flags &
5263                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5264                                 return 0; /* already on */
5265                 } else {
5266                         if ((vsi->info.port_vlan_flags &
5267                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5268                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5269                                 return 0; /* already off */
5270                 }
5271         }
5272
5273         if (on)
5274                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5275         else
5276                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5277         vsi->info.valid_sections =
5278                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5279         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5280         vsi->info.port_vlan_flags |= vlan_flags;
5281         ctxt.seid = vsi->seid;
5282         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5283         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5284         if (ret)
5285                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5286                             on ? "enable" : "disable");
5287
5288         return ret;
5289 }
5290
5291 static int
5292 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5293 {
5294         struct rte_eth_dev_data *data = dev->data;
5295         int ret;
5296         int mask = 0;
5297
5298         /* Apply vlan offload setting */
5299         mask = ETH_VLAN_STRIP_MASK |
5300                ETH_VLAN_FILTER_MASK |
5301                ETH_VLAN_EXTEND_MASK;
5302         ret = i40e_vlan_offload_set(dev, mask);
5303         if (ret) {
5304                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5305                 return ret;
5306         }
5307
5308         /* Apply pvid setting */
5309         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5310                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5311         if (ret)
5312                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5313
5314         return ret;
5315 }
5316
5317 static int
5318 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5319 {
5320         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5321
5322         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5323 }
5324
5325 static int
5326 i40e_update_flow_control(struct i40e_hw *hw)
5327 {
5328 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5329         struct i40e_link_status link_status;
5330         uint32_t rxfc = 0, txfc = 0, reg;
5331         uint8_t an_info;
5332         int ret;
5333
5334         memset(&link_status, 0, sizeof(link_status));
5335         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5336         if (ret != I40E_SUCCESS) {
5337                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5338                 goto write_reg; /* Disable flow control */
5339         }
5340
5341         an_info = hw->phy.link_info.an_info;
5342         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5343                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5344                 ret = I40E_ERR_NOT_READY;
5345                 goto write_reg; /* Disable flow control */
5346         }
5347         /**
5348          * If link auto negotiation is enabled, flow control needs to
5349          * be configured according to it
5350          */
5351         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5352         case I40E_LINK_PAUSE_RXTX:
5353                 rxfc = 1;
5354                 txfc = 1;
5355                 hw->fc.current_mode = I40E_FC_FULL;
5356                 break;
5357         case I40E_AQ_LINK_PAUSE_RX:
5358                 rxfc = 1;
5359                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5360                 break;
5361         case I40E_AQ_LINK_PAUSE_TX:
5362                 txfc = 1;
5363                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5364                 break;
5365         default:
5366                 hw->fc.current_mode = I40E_FC_NONE;
5367                 break;
5368         }
5369
5370 write_reg:
5371         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5372                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5373         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5374         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5375         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5376         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5377
5378         return ret;
5379 }
5380
5381 /* PF setup */
5382 static int
5383 i40e_pf_setup(struct i40e_pf *pf)
5384 {
5385         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5386         struct i40e_filter_control_settings settings;
5387         struct i40e_vsi *vsi;
5388         int ret;
5389
5390         /* Clear all stats counters */
5391         pf->offset_loaded = FALSE;
5392         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5393         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5394         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5395         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5396
5397         ret = i40e_pf_get_switch_config(pf);
5398         if (ret != I40E_SUCCESS) {
5399                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5400                 return ret;
5401         }
5402         if (pf->flags & I40E_FLAG_FDIR) {
5403                 /* make queue allocated first, let FDIR use queue pair 0*/
5404                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5405                 if (ret != I40E_FDIR_QUEUE_ID) {
5406                         PMD_DRV_LOG(ERR,
5407                                 "queue allocation fails for FDIR: ret =%d",
5408                                 ret);
5409                         pf->flags &= ~I40E_FLAG_FDIR;
5410                 }
5411         }
5412         /*  main VSI setup */
5413         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5414         if (!vsi) {
5415                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5416                 return I40E_ERR_NOT_READY;
5417         }
5418         pf->main_vsi = vsi;
5419
5420         /* Configure filter control */
5421         memset(&settings, 0, sizeof(settings));
5422         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5423                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5424         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5425                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5426         else {
5427                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5428                         hw->func_caps.rss_table_size);
5429                 return I40E_ERR_PARAM;
5430         }
5431         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5432                 hw->func_caps.rss_table_size);
5433         pf->hash_lut_size = hw->func_caps.rss_table_size;
5434
5435         /* Enable ethtype and macvlan filters */
5436         settings.enable_ethtype = TRUE;
5437         settings.enable_macvlan = TRUE;
5438         ret = i40e_set_filter_control(hw, &settings);
5439         if (ret)
5440                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5441                                                                 ret);
5442
5443         /* Update flow control according to the auto negotiation */
5444         i40e_update_flow_control(hw);
5445
5446         return I40E_SUCCESS;
5447 }
5448
5449 int
5450 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5451 {
5452         uint32_t reg;
5453         uint16_t j;
5454
5455         /**
5456          * Set or clear TX Queue Disable flags,
5457          * which is required by hardware.
5458          */
5459         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5460         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5461
5462         /* Wait until the request is finished */
5463         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5464                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5465                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5466                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5467                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5468                                                         & 0x1))) {
5469                         break;
5470                 }
5471         }
5472         if (on) {
5473                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5474                         return I40E_SUCCESS; /* already on, skip next steps */
5475
5476                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5477                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5478         } else {
5479                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5480                         return I40E_SUCCESS; /* already off, skip next steps */
5481                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5482         }
5483         /* Write the register */
5484         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5485         /* Check the result */
5486         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5487                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5488                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5489                 if (on) {
5490                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5491                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5492                                 break;
5493                 } else {
5494                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5495                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5496                                 break;
5497                 }
5498         }
5499         /* Check if it is timeout */
5500         if (j >= I40E_CHK_Q_ENA_COUNT) {
5501                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5502                             (on ? "enable" : "disable"), q_idx);
5503                 return I40E_ERR_TIMEOUT;
5504         }
5505
5506         return I40E_SUCCESS;
5507 }
5508
5509 /* Swith on or off the tx queues */
5510 static int
5511 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5512 {
5513         struct rte_eth_dev_data *dev_data = pf->dev_data;
5514         struct i40e_tx_queue *txq;
5515         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5516         uint16_t i;
5517         int ret;
5518
5519         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5520                 txq = dev_data->tx_queues[i];
5521                 /* Don't operate the queue if not configured or
5522                  * if starting only per queue */
5523                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5524                         continue;
5525                 if (on)
5526                         ret = i40e_dev_tx_queue_start(dev, i);
5527                 else
5528                         ret = i40e_dev_tx_queue_stop(dev, i);
5529                 if ( ret != I40E_SUCCESS)
5530                         return ret;
5531         }
5532
5533         return I40E_SUCCESS;
5534 }
5535
5536 int
5537 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5538 {
5539         uint32_t reg;
5540         uint16_t j;
5541
5542         /* Wait until the request is finished */
5543         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5544                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5545                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5546                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5547                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5548                         break;
5549         }
5550
5551         if (on) {
5552                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5553                         return I40E_SUCCESS; /* Already on, skip next steps */
5554                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5555         } else {
5556                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5557                         return I40E_SUCCESS; /* Already off, skip next steps */
5558                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5559         }
5560
5561         /* Write the register */
5562         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5563         /* Check the result */
5564         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5565                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5566                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5567                 if (on) {
5568                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5569                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5570                                 break;
5571                 } else {
5572                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5573                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5574                                 break;
5575                 }
5576         }
5577
5578         /* Check if it is timeout */
5579         if (j >= I40E_CHK_Q_ENA_COUNT) {
5580                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5581                             (on ? "enable" : "disable"), q_idx);
5582                 return I40E_ERR_TIMEOUT;
5583         }
5584
5585         return I40E_SUCCESS;
5586 }
5587 /* Switch on or off the rx queues */
5588 static int
5589 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5590 {
5591         struct rte_eth_dev_data *dev_data = pf->dev_data;
5592         struct i40e_rx_queue *rxq;
5593         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5594         uint16_t i;
5595         int ret;
5596
5597         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5598                 rxq = dev_data->rx_queues[i];
5599                 /* Don't operate the queue if not configured or
5600                  * if starting only per queue */
5601                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5602                         continue;
5603                 if (on)
5604                         ret = i40e_dev_rx_queue_start(dev, i);
5605                 else
5606                         ret = i40e_dev_rx_queue_stop(dev, i);
5607                 if (ret != I40E_SUCCESS)
5608                         return ret;
5609         }
5610
5611         return I40E_SUCCESS;
5612 }
5613
5614 /* Switch on or off all the rx/tx queues */
5615 int
5616 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5617 {
5618         int ret;
5619
5620         if (on) {
5621                 /* enable rx queues before enabling tx queues */
5622                 ret = i40e_dev_switch_rx_queues(pf, on);
5623                 if (ret) {
5624                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5625                         return ret;
5626                 }
5627                 ret = i40e_dev_switch_tx_queues(pf, on);
5628         } else {
5629                 /* Stop tx queues before stopping rx queues */
5630                 ret = i40e_dev_switch_tx_queues(pf, on);
5631                 if (ret) {
5632                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5633                         return ret;
5634                 }
5635                 ret = i40e_dev_switch_rx_queues(pf, on);
5636         }
5637
5638         return ret;
5639 }
5640
5641 /* Initialize VSI for TX */
5642 static int
5643 i40e_dev_tx_init(struct i40e_pf *pf)
5644 {
5645         struct rte_eth_dev_data *data = pf->dev_data;
5646         uint16_t i;
5647         uint32_t ret = I40E_SUCCESS;
5648         struct i40e_tx_queue *txq;
5649
5650         for (i = 0; i < data->nb_tx_queues; i++) {
5651                 txq = data->tx_queues[i];
5652                 if (!txq || !txq->q_set)
5653                         continue;
5654                 ret = i40e_tx_queue_init(txq);
5655                 if (ret != I40E_SUCCESS)
5656                         break;
5657         }
5658         if (ret == I40E_SUCCESS)
5659                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5660                                      ->eth_dev);
5661
5662         return ret;
5663 }
5664
5665 /* Initialize VSI for RX */
5666 static int
5667 i40e_dev_rx_init(struct i40e_pf *pf)
5668 {
5669         struct rte_eth_dev_data *data = pf->dev_data;
5670         int ret = I40E_SUCCESS;
5671         uint16_t i;
5672         struct i40e_rx_queue *rxq;
5673
5674         i40e_pf_config_mq_rx(pf);
5675         for (i = 0; i < data->nb_rx_queues; i++) {
5676                 rxq = data->rx_queues[i];
5677                 if (!rxq || !rxq->q_set)
5678                         continue;
5679
5680                 ret = i40e_rx_queue_init(rxq);
5681                 if (ret != I40E_SUCCESS) {
5682                         PMD_DRV_LOG(ERR,
5683                                 "Failed to do RX queue initialization");
5684                         break;
5685                 }
5686         }
5687         if (ret == I40E_SUCCESS)
5688                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5689                                      ->eth_dev);
5690
5691         return ret;
5692 }
5693
5694 static int
5695 i40e_dev_rxtx_init(struct i40e_pf *pf)
5696 {
5697         int err;
5698
5699         err = i40e_dev_tx_init(pf);
5700         if (err) {
5701                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5702                 return err;
5703         }
5704         err = i40e_dev_rx_init(pf);
5705         if (err) {
5706                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5707                 return err;
5708         }
5709
5710         return err;
5711 }
5712
5713 static int
5714 i40e_vmdq_setup(struct rte_eth_dev *dev)
5715 {
5716         struct rte_eth_conf *conf = &dev->data->dev_conf;
5717         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5718         int i, err, conf_vsis, j, loop;
5719         struct i40e_vsi *vsi;
5720         struct i40e_vmdq_info *vmdq_info;
5721         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5722         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5723
5724         /*
5725          * Disable interrupt to avoid message from VF. Furthermore, it will
5726          * avoid race condition in VSI creation/destroy.
5727          */
5728         i40e_pf_disable_irq0(hw);
5729
5730         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5731                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5732                 return -ENOTSUP;
5733         }
5734
5735         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5736         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5737                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5738                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5739                         pf->max_nb_vmdq_vsi);
5740                 return -ENOTSUP;
5741         }
5742
5743         if (pf->vmdq != NULL) {
5744                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5745                 return 0;
5746         }
5747
5748         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5749                                 sizeof(*vmdq_info) * conf_vsis, 0);
5750
5751         if (pf->vmdq == NULL) {
5752                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5753                 return -ENOMEM;
5754         }
5755
5756         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5757
5758         /* Create VMDQ VSI */
5759         for (i = 0; i < conf_vsis; i++) {
5760                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5761                                 vmdq_conf->enable_loop_back);
5762                 if (vsi == NULL) {
5763                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5764                         err = -1;
5765                         goto err_vsi_setup;
5766                 }
5767                 vmdq_info = &pf->vmdq[i];
5768                 vmdq_info->pf = pf;
5769                 vmdq_info->vsi = vsi;
5770         }
5771         pf->nb_cfg_vmdq_vsi = conf_vsis;
5772
5773         /* Configure Vlan */
5774         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5775         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5776                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5777                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5778                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5779                                         vmdq_conf->pool_map[i].vlan_id, j);
5780
5781                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5782                                                 vmdq_conf->pool_map[i].vlan_id);
5783                                 if (err) {
5784                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5785                                         err = -1;
5786                                         goto err_vsi_setup;
5787                                 }
5788                         }
5789                 }
5790         }
5791
5792         i40e_pf_enable_irq0(hw);
5793
5794         return 0;
5795
5796 err_vsi_setup:
5797         for (i = 0; i < conf_vsis; i++)
5798                 if (pf->vmdq[i].vsi == NULL)
5799                         break;
5800                 else
5801                         i40e_vsi_release(pf->vmdq[i].vsi);
5802
5803         rte_free(pf->vmdq);
5804         pf->vmdq = NULL;
5805         i40e_pf_enable_irq0(hw);
5806         return err;
5807 }
5808
5809 static void
5810 i40e_stat_update_32(struct i40e_hw *hw,
5811                    uint32_t reg,
5812                    bool offset_loaded,
5813                    uint64_t *offset,
5814                    uint64_t *stat)
5815 {
5816         uint64_t new_data;
5817
5818         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5819         if (!offset_loaded)
5820                 *offset = new_data;
5821
5822         if (new_data >= *offset)
5823                 *stat = (uint64_t)(new_data - *offset);
5824         else
5825                 *stat = (uint64_t)((new_data +
5826                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5827 }
5828
5829 static void
5830 i40e_stat_update_48(struct i40e_hw *hw,
5831                    uint32_t hireg,
5832                    uint32_t loreg,
5833                    bool offset_loaded,
5834                    uint64_t *offset,
5835                    uint64_t *stat)
5836 {
5837         uint64_t new_data;
5838
5839         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5840         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5841                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5842
5843         if (!offset_loaded)
5844                 *offset = new_data;
5845
5846         if (new_data >= *offset)
5847                 *stat = new_data - *offset;
5848         else
5849                 *stat = (uint64_t)((new_data +
5850                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5851
5852         *stat &= I40E_48_BIT_MASK;
5853 }
5854
5855 /* Disable IRQ0 */
5856 void
5857 i40e_pf_disable_irq0(struct i40e_hw *hw)
5858 {
5859         /* Disable all interrupt types */
5860         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5861         I40E_WRITE_FLUSH(hw);
5862 }
5863
5864 /* Enable IRQ0 */
5865 void
5866 i40e_pf_enable_irq0(struct i40e_hw *hw)
5867 {
5868         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5869                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5870                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5871                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5872         I40E_WRITE_FLUSH(hw);
5873 }
5874
5875 static void
5876 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5877 {
5878         /* read pending request and disable first */
5879         i40e_pf_disable_irq0(hw);
5880         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5881         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5882                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5883
5884         if (no_queue)
5885                 /* Link no queues with irq0 */
5886                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5887                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5888 }
5889
5890 static void
5891 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5892 {
5893         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5894         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5895         int i;
5896         uint16_t abs_vf_id;
5897         uint32_t index, offset, val;
5898
5899         if (!pf->vfs)
5900                 return;
5901         /**
5902          * Try to find which VF trigger a reset, use absolute VF id to access
5903          * since the reg is global register.
5904          */
5905         for (i = 0; i < pf->vf_num; i++) {
5906                 abs_vf_id = hw->func_caps.vf_base_id + i;
5907                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5908                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5909                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5910                 /* VFR event occurred */
5911                 if (val & (0x1 << offset)) {
5912                         int ret;
5913
5914                         /* Clear the event first */
5915                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5916                                                         (0x1 << offset));
5917                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5918                         /**
5919                          * Only notify a VF reset event occurred,
5920                          * don't trigger another SW reset
5921                          */
5922                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5923                         if (ret != I40E_SUCCESS)
5924                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5925                 }
5926         }
5927 }
5928
5929 static void
5930 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5931 {
5932         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5933         int i;
5934
5935         for (i = 0; i < pf->vf_num; i++)
5936                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5937 }
5938
5939 static void
5940 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5941 {
5942         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5943         struct i40e_arq_event_info info;
5944         uint16_t pending, opcode;
5945         int ret;
5946
5947         info.buf_len = I40E_AQ_BUF_SZ;
5948         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5949         if (!info.msg_buf) {
5950                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5951                 return;
5952         }
5953
5954         pending = 1;
5955         while (pending) {
5956                 ret = i40e_clean_arq_element(hw, &info, &pending);
5957
5958                 if (ret != I40E_SUCCESS) {
5959                         PMD_DRV_LOG(INFO,
5960                                 "Failed to read msg from AdminQ, aq_err: %u",
5961                                 hw->aq.asq_last_status);
5962                         break;
5963                 }
5964                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5965
5966                 switch (opcode) {
5967                 case i40e_aqc_opc_send_msg_to_pf:
5968                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5969                         i40e_pf_host_handle_vf_msg(dev,
5970                                         rte_le_to_cpu_16(info.desc.retval),
5971                                         rte_le_to_cpu_32(info.desc.cookie_high),
5972                                         rte_le_to_cpu_32(info.desc.cookie_low),
5973                                         info.msg_buf,
5974                                         info.msg_len);
5975                         break;
5976                 case i40e_aqc_opc_get_link_status:
5977                         ret = i40e_dev_link_update(dev, 0);
5978                         if (!ret)
5979                                 _rte_eth_dev_callback_process(dev,
5980                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5981                         break;
5982                 default:
5983                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5984                                     opcode);
5985                         break;
5986                 }
5987         }
5988         rte_free(info.msg_buf);
5989 }
5990
5991 /**
5992  * Interrupt handler triggered by NIC  for handling
5993  * specific interrupt.
5994  *
5995  * @param handle
5996  *  Pointer to interrupt handle.
5997  * @param param
5998  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5999  *
6000  * @return
6001  *  void
6002  */
6003 static void
6004 i40e_dev_interrupt_handler(void *param)
6005 {
6006         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6007         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6008         uint32_t icr0;
6009
6010         /* Disable interrupt */
6011         i40e_pf_disable_irq0(hw);
6012
6013         /* read out interrupt causes */
6014         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6015
6016         /* No interrupt event indicated */
6017         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6018                 PMD_DRV_LOG(INFO, "No interrupt event");
6019                 goto done;
6020         }
6021         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6022                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6023         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6024                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6025         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6026                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6027         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6028                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6029         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6030                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6031         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6032                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6033         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6034                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6035
6036         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6037                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6038                 i40e_dev_handle_vfr_event(dev);
6039         }
6040         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6041                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6042                 i40e_dev_handle_aq_msg(dev);
6043         }
6044
6045 done:
6046         /* Enable interrupt */
6047         i40e_pf_enable_irq0(hw);
6048         rte_intr_enable(dev->intr_handle);
6049 }
6050
6051 int
6052 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6053                          struct i40e_macvlan_filter *filter,
6054                          int total)
6055 {
6056         int ele_num, ele_buff_size;
6057         int num, actual_num, i;
6058         uint16_t flags;
6059         int ret = I40E_SUCCESS;
6060         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6061         struct i40e_aqc_add_macvlan_element_data *req_list;
6062
6063         if (filter == NULL  || total == 0)
6064                 return I40E_ERR_PARAM;
6065         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6066         ele_buff_size = hw->aq.asq_buf_size;
6067
6068         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6069         if (req_list == NULL) {
6070                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6071                 return I40E_ERR_NO_MEMORY;
6072         }
6073
6074         num = 0;
6075         do {
6076                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6077                 memset(req_list, 0, ele_buff_size);
6078
6079                 for (i = 0; i < actual_num; i++) {
6080                         rte_memcpy(req_list[i].mac_addr,
6081                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6082                         req_list[i].vlan_tag =
6083                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6084
6085                         switch (filter[num + i].filter_type) {
6086                         case RTE_MAC_PERFECT_MATCH:
6087                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6088                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6089                                 break;
6090                         case RTE_MACVLAN_PERFECT_MATCH:
6091                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6092                                 break;
6093                         case RTE_MAC_HASH_MATCH:
6094                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6095                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6096                                 break;
6097                         case RTE_MACVLAN_HASH_MATCH:
6098                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6099                                 break;
6100                         default:
6101                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6102                                 ret = I40E_ERR_PARAM;
6103                                 goto DONE;
6104                         }
6105
6106                         req_list[i].queue_number = 0;
6107
6108                         req_list[i].flags = rte_cpu_to_le_16(flags);
6109                 }
6110
6111                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6112                                                 actual_num, NULL);
6113                 if (ret != I40E_SUCCESS) {
6114                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6115                         goto DONE;
6116                 }
6117                 num += actual_num;
6118         } while (num < total);
6119
6120 DONE:
6121         rte_free(req_list);
6122         return ret;
6123 }
6124
6125 int
6126 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6127                             struct i40e_macvlan_filter *filter,
6128                             int total)
6129 {
6130         int ele_num, ele_buff_size;
6131         int num, actual_num, i;
6132         uint16_t flags;
6133         int ret = I40E_SUCCESS;
6134         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6135         struct i40e_aqc_remove_macvlan_element_data *req_list;
6136
6137         if (filter == NULL  || total == 0)
6138                 return I40E_ERR_PARAM;
6139
6140         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6141         ele_buff_size = hw->aq.asq_buf_size;
6142
6143         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6144         if (req_list == NULL) {
6145                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6146                 return I40E_ERR_NO_MEMORY;
6147         }
6148
6149         num = 0;
6150         do {
6151                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6152                 memset(req_list, 0, ele_buff_size);
6153
6154                 for (i = 0; i < actual_num; i++) {
6155                         rte_memcpy(req_list[i].mac_addr,
6156                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6157                         req_list[i].vlan_tag =
6158                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6159
6160                         switch (filter[num + i].filter_type) {
6161                         case RTE_MAC_PERFECT_MATCH:
6162                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6163                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6164                                 break;
6165                         case RTE_MACVLAN_PERFECT_MATCH:
6166                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6167                                 break;
6168                         case RTE_MAC_HASH_MATCH:
6169                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6170                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6171                                 break;
6172                         case RTE_MACVLAN_HASH_MATCH:
6173                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6174                                 break;
6175                         default:
6176                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6177                                 ret = I40E_ERR_PARAM;
6178                                 goto DONE;
6179                         }
6180                         req_list[i].flags = rte_cpu_to_le_16(flags);
6181                 }
6182
6183                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6184                                                 actual_num, NULL);
6185                 if (ret != I40E_SUCCESS) {
6186                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6187                         goto DONE;
6188                 }
6189                 num += actual_num;
6190         } while (num < total);
6191
6192 DONE:
6193         rte_free(req_list);
6194         return ret;
6195 }
6196
6197 /* Find out specific MAC filter */
6198 static struct i40e_mac_filter *
6199 i40e_find_mac_filter(struct i40e_vsi *vsi,
6200                          struct ether_addr *macaddr)
6201 {
6202         struct i40e_mac_filter *f;
6203
6204         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6205                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6206                         return f;
6207         }
6208
6209         return NULL;
6210 }
6211
6212 static bool
6213 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6214                          uint16_t vlan_id)
6215 {
6216         uint32_t vid_idx, vid_bit;
6217
6218         if (vlan_id > ETH_VLAN_ID_MAX)
6219                 return 0;
6220
6221         vid_idx = I40E_VFTA_IDX(vlan_id);
6222         vid_bit = I40E_VFTA_BIT(vlan_id);
6223
6224         if (vsi->vfta[vid_idx] & vid_bit)
6225                 return 1;
6226         else
6227                 return 0;
6228 }
6229
6230 static void
6231 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6232                        uint16_t vlan_id, bool on)
6233 {
6234         uint32_t vid_idx, vid_bit;
6235
6236         vid_idx = I40E_VFTA_IDX(vlan_id);
6237         vid_bit = I40E_VFTA_BIT(vlan_id);
6238
6239         if (on)
6240                 vsi->vfta[vid_idx] |= vid_bit;
6241         else
6242                 vsi->vfta[vid_idx] &= ~vid_bit;
6243 }
6244
6245 void
6246 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6247                      uint16_t vlan_id, bool on)
6248 {
6249         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6250         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6251         int ret;
6252
6253         if (vlan_id > ETH_VLAN_ID_MAX)
6254                 return;
6255
6256         i40e_store_vlan_filter(vsi, vlan_id, on);
6257
6258         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6259                 return;
6260
6261         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6262
6263         if (on) {
6264                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6265                                        &vlan_data, 1, NULL);
6266                 if (ret != I40E_SUCCESS)
6267                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6268         } else {
6269                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6270                                           &vlan_data, 1, NULL);
6271                 if (ret != I40E_SUCCESS)
6272                         PMD_DRV_LOG(ERR,
6273                                     "Failed to remove vlan filter");
6274         }
6275 }
6276
6277 /**
6278  * Find all vlan options for specific mac addr,
6279  * return with actual vlan found.
6280  */
6281 int
6282 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6283                            struct i40e_macvlan_filter *mv_f,
6284                            int num, struct ether_addr *addr)
6285 {
6286         int i;
6287         uint32_t j, k;
6288
6289         /**
6290          * Not to use i40e_find_vlan_filter to decrease the loop time,
6291          * although the code looks complex.
6292           */
6293         if (num < vsi->vlan_num)
6294                 return I40E_ERR_PARAM;
6295
6296         i = 0;
6297         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6298                 if (vsi->vfta[j]) {
6299                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6300                                 if (vsi->vfta[j] & (1 << k)) {
6301                                         if (i > num - 1) {
6302                                                 PMD_DRV_LOG(ERR,
6303                                                         "vlan number doesn't match");
6304                                                 return I40E_ERR_PARAM;
6305                                         }
6306                                         rte_memcpy(&mv_f[i].macaddr,
6307                                                         addr, ETH_ADDR_LEN);
6308                                         mv_f[i].vlan_id =
6309                                                 j * I40E_UINT32_BIT_SIZE + k;
6310                                         i++;
6311                                 }
6312                         }
6313                 }
6314         }
6315         return I40E_SUCCESS;
6316 }
6317
6318 static inline int
6319 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6320                            struct i40e_macvlan_filter *mv_f,
6321                            int num,
6322                            uint16_t vlan)
6323 {
6324         int i = 0;
6325         struct i40e_mac_filter *f;
6326
6327         if (num < vsi->mac_num)
6328                 return I40E_ERR_PARAM;
6329
6330         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6331                 if (i > num - 1) {
6332                         PMD_DRV_LOG(ERR, "buffer number not match");
6333                         return I40E_ERR_PARAM;
6334                 }
6335                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6336                                 ETH_ADDR_LEN);
6337                 mv_f[i].vlan_id = vlan;
6338                 mv_f[i].filter_type = f->mac_info.filter_type;
6339                 i++;
6340         }
6341
6342         return I40E_SUCCESS;
6343 }
6344
6345 static int
6346 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6347 {
6348         int i, j, num;
6349         struct i40e_mac_filter *f;
6350         struct i40e_macvlan_filter *mv_f;
6351         int ret = I40E_SUCCESS;
6352
6353         if (vsi == NULL || vsi->mac_num == 0)
6354                 return I40E_ERR_PARAM;
6355
6356         /* Case that no vlan is set */
6357         if (vsi->vlan_num == 0)
6358                 num = vsi->mac_num;
6359         else
6360                 num = vsi->mac_num * vsi->vlan_num;
6361
6362         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6363         if (mv_f == NULL) {
6364                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6365                 return I40E_ERR_NO_MEMORY;
6366         }
6367
6368         i = 0;
6369         if (vsi->vlan_num == 0) {
6370                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6371                         rte_memcpy(&mv_f[i].macaddr,
6372                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6373                         mv_f[i].filter_type = f->mac_info.filter_type;
6374                         mv_f[i].vlan_id = 0;
6375                         i++;
6376                 }
6377         } else {
6378                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6379                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6380                                         vsi->vlan_num, &f->mac_info.mac_addr);
6381                         if (ret != I40E_SUCCESS)
6382                                 goto DONE;
6383                         for (j = i; j < i + vsi->vlan_num; j++)
6384                                 mv_f[j].filter_type = f->mac_info.filter_type;
6385                         i += vsi->vlan_num;
6386                 }
6387         }
6388
6389         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6390 DONE:
6391         rte_free(mv_f);
6392
6393         return ret;
6394 }
6395
6396 int
6397 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6398 {
6399         struct i40e_macvlan_filter *mv_f;
6400         int mac_num;
6401         int ret = I40E_SUCCESS;
6402
6403         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6404                 return I40E_ERR_PARAM;
6405
6406         /* If it's already set, just return */
6407         if (i40e_find_vlan_filter(vsi,vlan))
6408                 return I40E_SUCCESS;
6409
6410         mac_num = vsi->mac_num;
6411
6412         if (mac_num == 0) {
6413                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6414                 return I40E_ERR_PARAM;
6415         }
6416
6417         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6418
6419         if (mv_f == NULL) {
6420                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6421                 return I40E_ERR_NO_MEMORY;
6422         }
6423
6424         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6425
6426         if (ret != I40E_SUCCESS)
6427                 goto DONE;
6428
6429         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6430
6431         if (ret != I40E_SUCCESS)
6432                 goto DONE;
6433
6434         i40e_set_vlan_filter(vsi, vlan, 1);
6435
6436         vsi->vlan_num++;
6437         ret = I40E_SUCCESS;
6438 DONE:
6439         rte_free(mv_f);
6440         return ret;
6441 }
6442
6443 int
6444 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6445 {
6446         struct i40e_macvlan_filter *mv_f;
6447         int mac_num;
6448         int ret = I40E_SUCCESS;
6449
6450         /**
6451          * Vlan 0 is the generic filter for untagged packets
6452          * and can't be removed.
6453          */
6454         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6455                 return I40E_ERR_PARAM;
6456
6457         /* If can't find it, just return */
6458         if (!i40e_find_vlan_filter(vsi, vlan))
6459                 return I40E_ERR_PARAM;
6460
6461         mac_num = vsi->mac_num;
6462
6463         if (mac_num == 0) {
6464                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6465                 return I40E_ERR_PARAM;
6466         }
6467
6468         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6469
6470         if (mv_f == NULL) {
6471                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6472                 return I40E_ERR_NO_MEMORY;
6473         }
6474
6475         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6476
6477         if (ret != I40E_SUCCESS)
6478                 goto DONE;
6479
6480         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6481
6482         if (ret != I40E_SUCCESS)
6483                 goto DONE;
6484
6485         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6486         if (vsi->vlan_num == 1) {
6487                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6488                 if (ret != I40E_SUCCESS)
6489                         goto DONE;
6490
6491                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6492                 if (ret != I40E_SUCCESS)
6493                         goto DONE;
6494         }
6495
6496         i40e_set_vlan_filter(vsi, vlan, 0);
6497
6498         vsi->vlan_num--;
6499         ret = I40E_SUCCESS;
6500 DONE:
6501         rte_free(mv_f);
6502         return ret;
6503 }
6504
6505 int
6506 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6507 {
6508         struct i40e_mac_filter *f;
6509         struct i40e_macvlan_filter *mv_f;
6510         int i, vlan_num = 0;
6511         int ret = I40E_SUCCESS;
6512
6513         /* If it's add and we've config it, return */
6514         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6515         if (f != NULL)
6516                 return I40E_SUCCESS;
6517         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6518                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6519
6520                 /**
6521                  * If vlan_num is 0, that's the first time to add mac,
6522                  * set mask for vlan_id 0.
6523                  */
6524                 if (vsi->vlan_num == 0) {
6525                         i40e_set_vlan_filter(vsi, 0, 1);
6526                         vsi->vlan_num = 1;
6527                 }
6528                 vlan_num = vsi->vlan_num;
6529         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6530                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6531                 vlan_num = 1;
6532
6533         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6534         if (mv_f == NULL) {
6535                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6536                 return I40E_ERR_NO_MEMORY;
6537         }
6538
6539         for (i = 0; i < vlan_num; i++) {
6540                 mv_f[i].filter_type = mac_filter->filter_type;
6541                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6542                                 ETH_ADDR_LEN);
6543         }
6544
6545         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6546                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6547                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6548                                         &mac_filter->mac_addr);
6549                 if (ret != I40E_SUCCESS)
6550                         goto DONE;
6551         }
6552
6553         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6554         if (ret != I40E_SUCCESS)
6555                 goto DONE;
6556
6557         /* Add the mac addr into mac list */
6558         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6559         if (f == NULL) {
6560                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6561                 ret = I40E_ERR_NO_MEMORY;
6562                 goto DONE;
6563         }
6564         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6565                         ETH_ADDR_LEN);
6566         f->mac_info.filter_type = mac_filter->filter_type;
6567         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6568         vsi->mac_num++;
6569
6570         ret = I40E_SUCCESS;
6571 DONE:
6572         rte_free(mv_f);
6573
6574         return ret;
6575 }
6576
6577 int
6578 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6579 {
6580         struct i40e_mac_filter *f;
6581         struct i40e_macvlan_filter *mv_f;
6582         int i, vlan_num;
6583         enum rte_mac_filter_type filter_type;
6584         int ret = I40E_SUCCESS;
6585
6586         /* Can't find it, return an error */
6587         f = i40e_find_mac_filter(vsi, addr);
6588         if (f == NULL)
6589                 return I40E_ERR_PARAM;
6590
6591         vlan_num = vsi->vlan_num;
6592         filter_type = f->mac_info.filter_type;
6593         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6594                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6595                 if (vlan_num == 0) {
6596                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6597                         return I40E_ERR_PARAM;
6598                 }
6599         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6600                         filter_type == RTE_MAC_HASH_MATCH)
6601                 vlan_num = 1;
6602
6603         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6604         if (mv_f == NULL) {
6605                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6606                 return I40E_ERR_NO_MEMORY;
6607         }
6608
6609         for (i = 0; i < vlan_num; i++) {
6610                 mv_f[i].filter_type = filter_type;
6611                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6612                                 ETH_ADDR_LEN);
6613         }
6614         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6615                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6616                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6617                 if (ret != I40E_SUCCESS)
6618                         goto DONE;
6619         }
6620
6621         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6622         if (ret != I40E_SUCCESS)
6623                 goto DONE;
6624
6625         /* Remove the mac addr into mac list */
6626         TAILQ_REMOVE(&vsi->mac_list, f, next);
6627         rte_free(f);
6628         vsi->mac_num--;
6629
6630         ret = I40E_SUCCESS;
6631 DONE:
6632         rte_free(mv_f);
6633         return ret;
6634 }
6635
6636 /* Configure hash enable flags for RSS */
6637 uint64_t
6638 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6639 {
6640         uint64_t hena = 0;
6641         int i;
6642
6643         if (!flags)
6644                 return hena;
6645
6646         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6647                 if (flags & (1ULL << i))
6648                         hena |= adapter->pctypes_tbl[i];
6649         }
6650
6651         return hena;
6652 }
6653
6654 /* Parse the hash enable flags */
6655 uint64_t
6656 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6657 {
6658         uint64_t rss_hf = 0;
6659
6660         if (!flags)
6661                 return rss_hf;
6662         int i;
6663
6664         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6665                 if (flags & adapter->pctypes_tbl[i])
6666                         rss_hf |= (1ULL << i);
6667         }
6668         return rss_hf;
6669 }
6670
6671 /* Disable RSS */
6672 static void
6673 i40e_pf_disable_rss(struct i40e_pf *pf)
6674 {
6675         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6676
6677         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6678         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6679         I40E_WRITE_FLUSH(hw);
6680 }
6681
6682 static int
6683 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6684 {
6685         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6686         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6687         int ret = 0;
6688
6689         if (!key || key_len == 0) {
6690                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6691                 return 0;
6692         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6693                 sizeof(uint32_t)) {
6694                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6695                 return -EINVAL;
6696         }
6697
6698         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6699                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6700                         (struct i40e_aqc_get_set_rss_key_data *)key;
6701
6702                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6703                 if (ret)
6704                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6705         } else {
6706                 uint32_t *hash_key = (uint32_t *)key;
6707                 uint16_t i;
6708
6709                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6710                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6711                 I40E_WRITE_FLUSH(hw);
6712         }
6713
6714         return ret;
6715 }
6716
6717 static int
6718 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6719 {
6720         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6721         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6722         int ret;
6723
6724         if (!key || !key_len)
6725                 return -EINVAL;
6726
6727         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6728                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6729                         (struct i40e_aqc_get_set_rss_key_data *)key);
6730                 if (ret) {
6731                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6732                         return ret;
6733                 }
6734         } else {
6735                 uint32_t *key_dw = (uint32_t *)key;
6736                 uint16_t i;
6737
6738                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6739                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6740         }
6741         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6742
6743         return 0;
6744 }
6745
6746 static int
6747 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6748 {
6749         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6750         uint64_t hena;
6751         int ret;
6752
6753         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6754                                rss_conf->rss_key_len);
6755         if (ret)
6756                 return ret;
6757
6758         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6759         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6760         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6761         I40E_WRITE_FLUSH(hw);
6762
6763         return 0;
6764 }
6765
6766 static int
6767 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6768                          struct rte_eth_rss_conf *rss_conf)
6769 {
6770         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6771         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6772         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6773         uint64_t hena;
6774
6775         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6776         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6777
6778         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6779                 if (rss_hf != 0) /* Enable RSS */
6780                         return -EINVAL;
6781                 return 0; /* Nothing to do */
6782         }
6783         /* RSS enabled */
6784         if (rss_hf == 0) /* Disable RSS */
6785                 return -EINVAL;
6786
6787         return i40e_hw_rss_hash_set(pf, rss_conf);
6788 }
6789
6790 static int
6791 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6792                            struct rte_eth_rss_conf *rss_conf)
6793 {
6794         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6795         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6796         uint64_t hena;
6797
6798         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6799                          &rss_conf->rss_key_len);
6800
6801         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6802         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6803         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6804
6805         return 0;
6806 }
6807
6808 static int
6809 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6810 {
6811         switch (filter_type) {
6812         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6813                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6814                 break;
6815         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6816                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6817                 break;
6818         case RTE_TUNNEL_FILTER_IMAC_TENID:
6819                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6820                 break;
6821         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6822                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6823                 break;
6824         case ETH_TUNNEL_FILTER_IMAC:
6825                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6826                 break;
6827         case ETH_TUNNEL_FILTER_OIP:
6828                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6829                 break;
6830         case ETH_TUNNEL_FILTER_IIP:
6831                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6832                 break;
6833         default:
6834                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6835                 return -EINVAL;
6836         }
6837
6838         return 0;
6839 }
6840
6841 /* Convert tunnel filter structure */
6842 static int
6843 i40e_tunnel_filter_convert(
6844         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6845         struct i40e_tunnel_filter *tunnel_filter)
6846 {
6847         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6848                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6849         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6850                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6851         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6852         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6853              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6854             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6855                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6856         else
6857                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6858         tunnel_filter->input.flags = cld_filter->element.flags;
6859         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6860         tunnel_filter->queue = cld_filter->element.queue_number;
6861         rte_memcpy(tunnel_filter->input.general_fields,
6862                    cld_filter->general_fields,
6863                    sizeof(cld_filter->general_fields));
6864
6865         return 0;
6866 }
6867
6868 /* Check if there exists the tunnel filter */
6869 struct i40e_tunnel_filter *
6870 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6871                              const struct i40e_tunnel_filter_input *input)
6872 {
6873         int ret;
6874
6875         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6876         if (ret < 0)
6877                 return NULL;
6878
6879         return tunnel_rule->hash_map[ret];
6880 }
6881
6882 /* Add a tunnel filter into the SW list */
6883 static int
6884 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6885                              struct i40e_tunnel_filter *tunnel_filter)
6886 {
6887         struct i40e_tunnel_rule *rule = &pf->tunnel;
6888         int ret;
6889
6890         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6891         if (ret < 0) {
6892                 PMD_DRV_LOG(ERR,
6893                             "Failed to insert tunnel filter to hash table %d!",
6894                             ret);
6895                 return ret;
6896         }
6897         rule->hash_map[ret] = tunnel_filter;
6898
6899         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6900
6901         return 0;
6902 }
6903
6904 /* Delete a tunnel filter from the SW list */
6905 int
6906 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6907                           struct i40e_tunnel_filter_input *input)
6908 {
6909         struct i40e_tunnel_rule *rule = &pf->tunnel;
6910         struct i40e_tunnel_filter *tunnel_filter;
6911         int ret;
6912
6913         ret = rte_hash_del_key(rule->hash_table, input);
6914         if (ret < 0) {
6915                 PMD_DRV_LOG(ERR,
6916                             "Failed to delete tunnel filter to hash table %d!",
6917                             ret);
6918                 return ret;
6919         }
6920         tunnel_filter = rule->hash_map[ret];
6921         rule->hash_map[ret] = NULL;
6922
6923         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6924         rte_free(tunnel_filter);
6925
6926         return 0;
6927 }
6928
6929 int
6930 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6931                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6932                         uint8_t add)
6933 {
6934         uint16_t ip_type;
6935         uint32_t ipv4_addr, ipv4_addr_le;
6936         uint8_t i, tun_type = 0;
6937         /* internal varialbe to convert ipv6 byte order */
6938         uint32_t convert_ipv6[4];
6939         int val, ret = 0;
6940         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6941         struct i40e_vsi *vsi = pf->main_vsi;
6942         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6943         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6944         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6945         struct i40e_tunnel_filter *tunnel, *node;
6946         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6947
6948         cld_filter = rte_zmalloc("tunnel_filter",
6949                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6950         0);
6951
6952         if (NULL == cld_filter) {
6953                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6954                 return -ENOMEM;
6955         }
6956         pfilter = cld_filter;
6957
6958         ether_addr_copy(&tunnel_filter->outer_mac,
6959                         (struct ether_addr *)&pfilter->element.outer_mac);
6960         ether_addr_copy(&tunnel_filter->inner_mac,
6961                         (struct ether_addr *)&pfilter->element.inner_mac);
6962
6963         pfilter->element.inner_vlan =
6964                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6965         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6966                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6967                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6968                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
6969                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6970                                 &ipv4_addr_le,
6971                                 sizeof(pfilter->element.ipaddr.v4.data));
6972         } else {
6973                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6974                 for (i = 0; i < 4; i++) {
6975                         convert_ipv6[i] =
6976                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6977                 }
6978                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6979                            &convert_ipv6,
6980                            sizeof(pfilter->element.ipaddr.v6.data));
6981         }
6982
6983         /* check tunneled type */
6984         switch (tunnel_filter->tunnel_type) {
6985         case RTE_TUNNEL_TYPE_VXLAN:
6986                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6987                 break;
6988         case RTE_TUNNEL_TYPE_NVGRE:
6989                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6990                 break;
6991         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6992                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6993                 break;
6994         default:
6995                 /* Other tunnel types is not supported. */
6996                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6997                 rte_free(cld_filter);
6998                 return -EINVAL;
6999         }
7000
7001         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7002                                        &pfilter->element.flags);
7003         if (val < 0) {
7004                 rte_free(cld_filter);
7005                 return -EINVAL;
7006         }
7007
7008         pfilter->element.flags |= rte_cpu_to_le_16(
7009                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7010                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7011         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7012         pfilter->element.queue_number =
7013                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7014
7015         /* Check if there is the filter in SW list */
7016         memset(&check_filter, 0, sizeof(check_filter));
7017         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7018         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7019         if (add && node) {
7020                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7021                 return -EINVAL;
7022         }
7023
7024         if (!add && !node) {
7025                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7026                 return -EINVAL;
7027         }
7028
7029         if (add) {
7030                 ret = i40e_aq_add_cloud_filters(hw,
7031                                         vsi->seid, &cld_filter->element, 1);
7032                 if (ret < 0) {
7033                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7034                         return -ENOTSUP;
7035                 }
7036                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7037                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7038                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7039         } else {
7040                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7041                                                    &cld_filter->element, 1);
7042                 if (ret < 0) {
7043                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7044                         return -ENOTSUP;
7045                 }
7046                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7047         }
7048
7049         rte_free(cld_filter);
7050         return ret;
7051 }
7052
7053 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7054 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7055 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7056 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7057 #define I40E_TR_GRE_KEY_MASK                    0x400
7058 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7059 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7060
7061 static enum
7062 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7063 {
7064         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7065         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7066         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7067         enum i40e_status_code status = I40E_SUCCESS;
7068
7069         memset(&filter_replace, 0,
7070                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7071         memset(&filter_replace_buf, 0,
7072                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7073
7074         /* create L1 filter */
7075         filter_replace.old_filter_type =
7076                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7077         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7078         filter_replace.tr_bit = 0;
7079
7080         /* Prepare the buffer, 3 entries */
7081         filter_replace_buf.data[0] =
7082                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7083         filter_replace_buf.data[0] |=
7084                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7085         filter_replace_buf.data[2] = 0xFF;
7086         filter_replace_buf.data[3] = 0xFF;
7087         filter_replace_buf.data[4] =
7088                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7089         filter_replace_buf.data[4] |=
7090                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7091         filter_replace_buf.data[7] = 0xF0;
7092         filter_replace_buf.data[8]
7093                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7094         filter_replace_buf.data[8] |=
7095                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7096         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7097                 I40E_TR_GENEVE_KEY_MASK |
7098                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7099         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7100                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7101                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7102
7103         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7104                                                &filter_replace_buf);
7105         return status;
7106 }
7107
7108 static enum
7109 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7110 {
7111         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7112         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7113         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7114         enum i40e_status_code status = I40E_SUCCESS;
7115
7116         /* For MPLSoUDP */
7117         memset(&filter_replace, 0,
7118                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7119         memset(&filter_replace_buf, 0,
7120                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7121         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7122                 I40E_AQC_MIRROR_CLOUD_FILTER;
7123         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7124         filter_replace.new_filter_type =
7125                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7126         /* Prepare the buffer, 2 entries */
7127         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7128         filter_replace_buf.data[0] |=
7129                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7130         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7131         filter_replace_buf.data[4] |=
7132                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7133         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7134                                                &filter_replace_buf);
7135         if (status < 0)
7136                 return status;
7137
7138         /* For MPLSoGRE */
7139         memset(&filter_replace, 0,
7140                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7141         memset(&filter_replace_buf, 0,
7142                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7143
7144         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7145                 I40E_AQC_MIRROR_CLOUD_FILTER;
7146         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7147         filter_replace.new_filter_type =
7148                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7149         /* Prepare the buffer, 2 entries */
7150         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7151         filter_replace_buf.data[0] |=
7152                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7153         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7154         filter_replace_buf.data[4] |=
7155                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7156
7157         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7158                                                &filter_replace_buf);
7159         return status;
7160 }
7161
7162 static enum i40e_status_code
7163 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7164 {
7165         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7166         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7167         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7168         enum i40e_status_code status = I40E_SUCCESS;
7169
7170         /* For GTP-C */
7171         memset(&filter_replace, 0,
7172                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7173         memset(&filter_replace_buf, 0,
7174                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7175         /* create L1 filter */
7176         filter_replace.old_filter_type =
7177                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7178         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7179         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7180                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7181         /* Prepare the buffer, 2 entries */
7182         filter_replace_buf.data[0] =
7183                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7184         filter_replace_buf.data[0] |=
7185                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7186         filter_replace_buf.data[2] = 0xFF;
7187         filter_replace_buf.data[3] = 0xFF;
7188         filter_replace_buf.data[4] =
7189                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7190         filter_replace_buf.data[4] |=
7191                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7192         filter_replace_buf.data[6] = 0xFF;
7193         filter_replace_buf.data[7] = 0xFF;
7194         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7195                                                &filter_replace_buf);
7196         if (status < 0)
7197                 return status;
7198
7199         /* for GTP-U */
7200         memset(&filter_replace, 0,
7201                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7202         memset(&filter_replace_buf, 0,
7203                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7204         /* create L1 filter */
7205         filter_replace.old_filter_type =
7206                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7207         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7208         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7209                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7210         /* Prepare the buffer, 2 entries */
7211         filter_replace_buf.data[0] =
7212                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7213         filter_replace_buf.data[0] |=
7214                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7215         filter_replace_buf.data[2] = 0xFF;
7216         filter_replace_buf.data[3] = 0xFF;
7217         filter_replace_buf.data[4] =
7218                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7219         filter_replace_buf.data[4] |=
7220                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7221         filter_replace_buf.data[6] = 0xFF;
7222         filter_replace_buf.data[7] = 0xFF;
7223
7224         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7225                                                &filter_replace_buf);
7226         return status;
7227 }
7228
7229 static enum
7230 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7231 {
7232         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7233         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7234         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7235         enum i40e_status_code status = I40E_SUCCESS;
7236
7237         /* for GTP-C */
7238         memset(&filter_replace, 0,
7239                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7240         memset(&filter_replace_buf, 0,
7241                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7242         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7243         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7244         filter_replace.new_filter_type =
7245                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7246         /* Prepare the buffer, 2 entries */
7247         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7248         filter_replace_buf.data[0] |=
7249                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7250         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7251         filter_replace_buf.data[4] |=
7252                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7253         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7254                                                &filter_replace_buf);
7255         if (status < 0)
7256                 return status;
7257
7258         /* for GTP-U */
7259         memset(&filter_replace, 0,
7260                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7261         memset(&filter_replace_buf, 0,
7262                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7263         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7264         filter_replace.old_filter_type =
7265                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7266         filter_replace.new_filter_type =
7267                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7268         /* Prepare the buffer, 2 entries */
7269         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7270         filter_replace_buf.data[0] |=
7271                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7272         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7273         filter_replace_buf.data[4] |=
7274                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7275
7276         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7277                                                &filter_replace_buf);
7278         return status;
7279 }
7280
7281 int
7282 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7283                       struct i40e_tunnel_filter_conf *tunnel_filter,
7284                       uint8_t add)
7285 {
7286         uint16_t ip_type;
7287         uint32_t ipv4_addr, ipv4_addr_le;
7288         uint8_t i, tun_type = 0;
7289         /* internal variable to convert ipv6 byte order */
7290         uint32_t convert_ipv6[4];
7291         int val, ret = 0;
7292         struct i40e_pf_vf *vf = NULL;
7293         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7294         struct i40e_vsi *vsi;
7295         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7296         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7297         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7298         struct i40e_tunnel_filter *tunnel, *node;
7299         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7300         uint32_t teid_le;
7301         bool big_buffer = 0;
7302
7303         cld_filter = rte_zmalloc("tunnel_filter",
7304                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7305                          0);
7306
7307         if (cld_filter == NULL) {
7308                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7309                 return -ENOMEM;
7310         }
7311         pfilter = cld_filter;
7312
7313         ether_addr_copy(&tunnel_filter->outer_mac,
7314                         (struct ether_addr *)&pfilter->element.outer_mac);
7315         ether_addr_copy(&tunnel_filter->inner_mac,
7316                         (struct ether_addr *)&pfilter->element.inner_mac);
7317
7318         pfilter->element.inner_vlan =
7319                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7320         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7321                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7322                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7323                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7324                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7325                                 &ipv4_addr_le,
7326                                 sizeof(pfilter->element.ipaddr.v4.data));
7327         } else {
7328                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7329                 for (i = 0; i < 4; i++) {
7330                         convert_ipv6[i] =
7331                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7332                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7333                 }
7334                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7335                            &convert_ipv6,
7336                            sizeof(pfilter->element.ipaddr.v6.data));
7337         }
7338
7339         /* check tunneled type */
7340         switch (tunnel_filter->tunnel_type) {
7341         case I40E_TUNNEL_TYPE_VXLAN:
7342                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7343                 break;
7344         case I40E_TUNNEL_TYPE_NVGRE:
7345                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7346                 break;
7347         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7348                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7349                 break;
7350         case I40E_TUNNEL_TYPE_MPLSoUDP:
7351                 if (!pf->mpls_replace_flag) {
7352                         i40e_replace_mpls_l1_filter(pf);
7353                         i40e_replace_mpls_cloud_filter(pf);
7354                         pf->mpls_replace_flag = 1;
7355                 }
7356                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7357                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7358                         teid_le >> 4;
7359                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7360                         (teid_le & 0xF) << 12;
7361                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7362                         0x40;
7363                 big_buffer = 1;
7364                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7365                 break;
7366         case I40E_TUNNEL_TYPE_MPLSoGRE:
7367                 if (!pf->mpls_replace_flag) {
7368                         i40e_replace_mpls_l1_filter(pf);
7369                         i40e_replace_mpls_cloud_filter(pf);
7370                         pf->mpls_replace_flag = 1;
7371                 }
7372                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7373                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7374                         teid_le >> 4;
7375                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7376                         (teid_le & 0xF) << 12;
7377                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7378                         0x0;
7379                 big_buffer = 1;
7380                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7381                 break;
7382         case I40E_TUNNEL_TYPE_GTPC:
7383                 if (!pf->gtp_replace_flag) {
7384                         i40e_replace_gtp_l1_filter(pf);
7385                         i40e_replace_gtp_cloud_filter(pf);
7386                         pf->gtp_replace_flag = 1;
7387                 }
7388                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7389                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7390                         (teid_le >> 16) & 0xFFFF;
7391                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7392                         teid_le & 0xFFFF;
7393                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7394                         0x0;
7395                 big_buffer = 1;
7396                 break;
7397         case I40E_TUNNEL_TYPE_GTPU:
7398                 if (!pf->gtp_replace_flag) {
7399                         i40e_replace_gtp_l1_filter(pf);
7400                         i40e_replace_gtp_cloud_filter(pf);
7401                         pf->gtp_replace_flag = 1;
7402                 }
7403                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7404                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7405                         (teid_le >> 16) & 0xFFFF;
7406                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7407                         teid_le & 0xFFFF;
7408                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7409                         0x0;
7410                 big_buffer = 1;
7411                 break;
7412         case I40E_TUNNEL_TYPE_QINQ:
7413                 if (!pf->qinq_replace_flag) {
7414                         ret = i40e_cloud_filter_qinq_create(pf);
7415                         if (ret < 0)
7416                                 PMD_DRV_LOG(DEBUG,
7417                                             "QinQ tunnel filter already created.");
7418                         pf->qinq_replace_flag = 1;
7419                 }
7420                 /*      Add in the General fields the values of
7421                  *      the Outer and Inner VLAN
7422                  *      Big Buffer should be set, see changes in
7423                  *      i40e_aq_add_cloud_filters
7424                  */
7425                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7426                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7427                 big_buffer = 1;
7428                 break;
7429         default:
7430                 /* Other tunnel types is not supported. */
7431                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7432                 rte_free(cld_filter);
7433                 return -EINVAL;
7434         }
7435
7436         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7437                 pfilter->element.flags =
7438                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7439         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7440                 pfilter->element.flags =
7441                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7442         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7443                 pfilter->element.flags =
7444                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7445         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7446                 pfilter->element.flags =
7447                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7448         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7449                 pfilter->element.flags |=
7450                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7451         else {
7452                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7453                                                 &pfilter->element.flags);
7454                 if (val < 0) {
7455                         rte_free(cld_filter);
7456                         return -EINVAL;
7457                 }
7458         }
7459
7460         pfilter->element.flags |= rte_cpu_to_le_16(
7461                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7462                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7463         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7464         pfilter->element.queue_number =
7465                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7466
7467         if (!tunnel_filter->is_to_vf)
7468                 vsi = pf->main_vsi;
7469         else {
7470                 if (tunnel_filter->vf_id >= pf->vf_num) {
7471                         PMD_DRV_LOG(ERR, "Invalid argument.");
7472                         return -EINVAL;
7473                 }
7474                 vf = &pf->vfs[tunnel_filter->vf_id];
7475                 vsi = vf->vsi;
7476         }
7477
7478         /* Check if there is the filter in SW list */
7479         memset(&check_filter, 0, sizeof(check_filter));
7480         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7481         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7482         check_filter.vf_id = tunnel_filter->vf_id;
7483         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7484         if (add && node) {
7485                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7486                 return -EINVAL;
7487         }
7488
7489         if (!add && !node) {
7490                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7491                 return -EINVAL;
7492         }
7493
7494         if (add) {
7495                 if (big_buffer)
7496                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7497                                                    vsi->seid, cld_filter, 1);
7498                 else
7499                         ret = i40e_aq_add_cloud_filters(hw,
7500                                         vsi->seid, &cld_filter->element, 1);
7501                 if (ret < 0) {
7502                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7503                         return -ENOTSUP;
7504                 }
7505                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7506                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7507                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7508         } else {
7509                 if (big_buffer)
7510                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7511                                 hw, vsi->seid, cld_filter, 1);
7512                 else
7513                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7514                                                    &cld_filter->element, 1);
7515                 if (ret < 0) {
7516                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7517                         return -ENOTSUP;
7518                 }
7519                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7520         }
7521
7522         rte_free(cld_filter);
7523         return ret;
7524 }
7525
7526 static int
7527 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7528 {
7529         uint8_t i;
7530
7531         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7532                 if (pf->vxlan_ports[i] == port)
7533                         return i;
7534         }
7535
7536         return -1;
7537 }
7538
7539 static int
7540 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7541 {
7542         int  idx, ret;
7543         uint8_t filter_idx;
7544         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7545
7546         idx = i40e_get_vxlan_port_idx(pf, port);
7547
7548         /* Check if port already exists */
7549         if (idx >= 0) {
7550                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7551                 return -EINVAL;
7552         }
7553
7554         /* Now check if there is space to add the new port */
7555         idx = i40e_get_vxlan_port_idx(pf, 0);
7556         if (idx < 0) {
7557                 PMD_DRV_LOG(ERR,
7558                         "Maximum number of UDP ports reached, not adding port %d",
7559                         port);
7560                 return -ENOSPC;
7561         }
7562
7563         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7564                                         &filter_idx, NULL);
7565         if (ret < 0) {
7566                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7567                 return -1;
7568         }
7569
7570         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7571                          port,  filter_idx);
7572
7573         /* New port: add it and mark its index in the bitmap */
7574         pf->vxlan_ports[idx] = port;
7575         pf->vxlan_bitmap |= (1 << idx);
7576
7577         if (!(pf->flags & I40E_FLAG_VXLAN))
7578                 pf->flags |= I40E_FLAG_VXLAN;
7579
7580         return 0;
7581 }
7582
7583 static int
7584 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7585 {
7586         int idx;
7587         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7588
7589         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7590                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7591                 return -EINVAL;
7592         }
7593
7594         idx = i40e_get_vxlan_port_idx(pf, port);
7595
7596         if (idx < 0) {
7597                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7598                 return -EINVAL;
7599         }
7600
7601         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7602                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7603                 return -1;
7604         }
7605
7606         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7607                         port, idx);
7608
7609         pf->vxlan_ports[idx] = 0;
7610         pf->vxlan_bitmap &= ~(1 << idx);
7611
7612         if (!pf->vxlan_bitmap)
7613                 pf->flags &= ~I40E_FLAG_VXLAN;
7614
7615         return 0;
7616 }
7617
7618 /* Add UDP tunneling port */
7619 static int
7620 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7621                              struct rte_eth_udp_tunnel *udp_tunnel)
7622 {
7623         int ret = 0;
7624         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7625
7626         if (udp_tunnel == NULL)
7627                 return -EINVAL;
7628
7629         switch (udp_tunnel->prot_type) {
7630         case RTE_TUNNEL_TYPE_VXLAN:
7631                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7632                 break;
7633
7634         case RTE_TUNNEL_TYPE_GENEVE:
7635         case RTE_TUNNEL_TYPE_TEREDO:
7636                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7637                 ret = -1;
7638                 break;
7639
7640         default:
7641                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7642                 ret = -1;
7643                 break;
7644         }
7645
7646         return ret;
7647 }
7648
7649 /* Remove UDP tunneling port */
7650 static int
7651 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7652                              struct rte_eth_udp_tunnel *udp_tunnel)
7653 {
7654         int ret = 0;
7655         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7656
7657         if (udp_tunnel == NULL)
7658                 return -EINVAL;
7659
7660         switch (udp_tunnel->prot_type) {
7661         case RTE_TUNNEL_TYPE_VXLAN:
7662                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7663                 break;
7664         case RTE_TUNNEL_TYPE_GENEVE:
7665         case RTE_TUNNEL_TYPE_TEREDO:
7666                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7667                 ret = -1;
7668                 break;
7669         default:
7670                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7671                 ret = -1;
7672                 break;
7673         }
7674
7675         return ret;
7676 }
7677
7678 /* Calculate the maximum number of contiguous PF queues that are configured */
7679 static int
7680 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7681 {
7682         struct rte_eth_dev_data *data = pf->dev_data;
7683         int i, num;
7684         struct i40e_rx_queue *rxq;
7685
7686         num = 0;
7687         for (i = 0; i < pf->lan_nb_qps; i++) {
7688                 rxq = data->rx_queues[i];
7689                 if (rxq && rxq->q_set)
7690                         num++;
7691                 else
7692                         break;
7693         }
7694
7695         return num;
7696 }
7697
7698 /* Configure RSS */
7699 static int
7700 i40e_pf_config_rss(struct i40e_pf *pf)
7701 {
7702         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7703         struct rte_eth_rss_conf rss_conf;
7704         uint32_t i, lut = 0;
7705         uint16_t j, num;
7706
7707         /*
7708          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7709          * It's necessary to calculate the actual PF queues that are configured.
7710          */
7711         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7712                 num = i40e_pf_calc_configured_queues_num(pf);
7713         else
7714                 num = pf->dev_data->nb_rx_queues;
7715
7716         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7717         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7718                         num);
7719
7720         if (num == 0) {
7721                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7722                 return -ENOTSUP;
7723         }
7724
7725         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7726                 if (j == num)
7727                         j = 0;
7728                 lut = (lut << 8) | (j & ((0x1 <<
7729                         hw->func_caps.rss_table_entry_width) - 1));
7730                 if ((i & 3) == 3)
7731                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7732         }
7733
7734         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7735         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7736                 i40e_pf_disable_rss(pf);
7737                 return 0;
7738         }
7739         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7740                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7741                 /* Random default keys */
7742                 static uint32_t rss_key_default[] = {0x6b793944,
7743                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7744                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7745                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7746
7747                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7748                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7749                                                         sizeof(uint32_t);
7750         }
7751
7752         return i40e_hw_rss_hash_set(pf, &rss_conf);
7753 }
7754
7755 static int
7756 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7757                                struct rte_eth_tunnel_filter_conf *filter)
7758 {
7759         if (pf == NULL || filter == NULL) {
7760                 PMD_DRV_LOG(ERR, "Invalid parameter");
7761                 return -EINVAL;
7762         }
7763
7764         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7765                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7766                 return -EINVAL;
7767         }
7768
7769         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7770                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7771                 return -EINVAL;
7772         }
7773
7774         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7775                 (is_zero_ether_addr(&filter->outer_mac))) {
7776                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7777                 return -EINVAL;
7778         }
7779
7780         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7781                 (is_zero_ether_addr(&filter->inner_mac))) {
7782                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7783                 return -EINVAL;
7784         }
7785
7786         return 0;
7787 }
7788
7789 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7790 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7791 static int
7792 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7793 {
7794         uint32_t val, reg;
7795         int ret = -EINVAL;
7796
7797         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7798         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7799
7800         if (len == 3) {
7801                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7802         } else if (len == 4) {
7803                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7804         } else {
7805                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7806                 return ret;
7807         }
7808
7809         if (reg != val) {
7810                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7811                                                    reg, NULL);
7812                 if (ret != 0)
7813                         return ret;
7814         } else {
7815                 ret = 0;
7816         }
7817         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7818                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7819
7820         return ret;
7821 }
7822
7823 static int
7824 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7825 {
7826         int ret = -EINVAL;
7827
7828         if (!hw || !cfg)
7829                 return -EINVAL;
7830
7831         switch (cfg->cfg_type) {
7832         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7833                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7834                 break;
7835         default:
7836                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7837                 break;
7838         }
7839
7840         return ret;
7841 }
7842
7843 static int
7844 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7845                                enum rte_filter_op filter_op,
7846                                void *arg)
7847 {
7848         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7849         int ret = I40E_ERR_PARAM;
7850
7851         switch (filter_op) {
7852         case RTE_ETH_FILTER_SET:
7853                 ret = i40e_dev_global_config_set(hw,
7854                         (struct rte_eth_global_cfg *)arg);
7855                 break;
7856         default:
7857                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7858                 break;
7859         }
7860
7861         return ret;
7862 }
7863
7864 static int
7865 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7866                           enum rte_filter_op filter_op,
7867                           void *arg)
7868 {
7869         struct rte_eth_tunnel_filter_conf *filter;
7870         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7871         int ret = I40E_SUCCESS;
7872
7873         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7874
7875         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7876                 return I40E_ERR_PARAM;
7877
7878         switch (filter_op) {
7879         case RTE_ETH_FILTER_NOP:
7880                 if (!(pf->flags & I40E_FLAG_VXLAN))
7881                         ret = I40E_NOT_SUPPORTED;
7882                 break;
7883         case RTE_ETH_FILTER_ADD:
7884                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7885                 break;
7886         case RTE_ETH_FILTER_DELETE:
7887                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7888                 break;
7889         default:
7890                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7891                 ret = I40E_ERR_PARAM;
7892                 break;
7893         }
7894
7895         return ret;
7896 }
7897
7898 static int
7899 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7900 {
7901         int ret = 0;
7902         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7903
7904         /* RSS setup */
7905         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7906                 ret = i40e_pf_config_rss(pf);
7907         else
7908                 i40e_pf_disable_rss(pf);
7909
7910         return ret;
7911 }
7912
7913 /* Get the symmetric hash enable configurations per port */
7914 static void
7915 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7916 {
7917         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7918
7919         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7920 }
7921
7922 /* Set the symmetric hash enable configurations per port */
7923 static void
7924 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7925 {
7926         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7927
7928         if (enable > 0) {
7929                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7930                         PMD_DRV_LOG(INFO,
7931                                 "Symmetric hash has already been enabled");
7932                         return;
7933                 }
7934                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7935         } else {
7936                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7937                         PMD_DRV_LOG(INFO,
7938                                 "Symmetric hash has already been disabled");
7939                         return;
7940                 }
7941                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7942         }
7943         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7944         I40E_WRITE_FLUSH(hw);
7945 }
7946
7947 /*
7948  * Get global configurations of hash function type and symmetric hash enable
7949  * per flow type (pctype). Note that global configuration means it affects all
7950  * the ports on the same NIC.
7951  */
7952 static int
7953 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7954                                    struct rte_eth_hash_global_conf *g_cfg)
7955 {
7956         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
7957         uint32_t reg;
7958         uint16_t i, j;
7959
7960         memset(g_cfg, 0, sizeof(*g_cfg));
7961         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7962         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7963                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7964         else
7965                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7966         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7967                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7968
7969         /*
7970          * We work only with lowest 32 bits which is not correct, but to work
7971          * properly the valid_bit_mask size should be increased up to 64 bits
7972          * and this will brake ABI. This modification will be done in next
7973          * release
7974          */
7975         g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
7976
7977         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
7978                 if (!adapter->pctypes_tbl[i])
7979                         continue;
7980                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
7981                      j < I40E_FILTER_PCTYPE_MAX; j++) {
7982                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
7983                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
7984                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
7985                                         g_cfg->sym_hash_enable_mask[0] |=
7986                                                                 (1UL << i);
7987                                 }
7988                         }
7989                 }
7990         }
7991
7992         return 0;
7993 }
7994
7995 static int
7996 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
7997                               const struct rte_eth_hash_global_conf *g_cfg)
7998 {
7999         uint32_t i;
8000         uint32_t mask0, i40e_mask = adapter->flow_types_mask;
8001
8002         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8003                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8004                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8005                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8006                                                 g_cfg->hash_func);
8007                 return -EINVAL;
8008         }
8009
8010         /*
8011          * As i40e supports less than 32 flow types, only first 32 bits need to
8012          * be checked.
8013          */
8014         mask0 = g_cfg->valid_bit_mask[0];
8015         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8016                 if (i == 0) {
8017                         /* Check if any unsupported flow type configured */
8018                         if ((mask0 | i40e_mask) ^ i40e_mask)
8019                                 goto mask_err;
8020                 } else {
8021                         if (g_cfg->valid_bit_mask[i])
8022                                 goto mask_err;
8023                 }
8024         }
8025
8026         return 0;
8027
8028 mask_err:
8029         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8030
8031         return -EINVAL;
8032 }
8033
8034 /*
8035  * Set global configurations of hash function type and symmetric hash enable
8036  * per flow type (pctype). Note any modifying global configuration will affect
8037  * all the ports on the same NIC.
8038  */
8039 static int
8040 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8041                                    struct rte_eth_hash_global_conf *g_cfg)
8042 {
8043         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8044         int ret;
8045         uint16_t i, j;
8046         uint32_t reg;
8047         /*
8048          * We work only with lowest 32 bits which is not correct, but to work
8049          * properly the valid_bit_mask size should be increased up to 64 bits
8050          * and this will brake ABI. This modification will be done in next
8051          * release
8052          */
8053         uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8054                                         (uint32_t)adapter->flow_types_mask;
8055
8056         /* Check the input parameters */
8057         ret = i40e_hash_global_config_check(adapter, g_cfg);
8058         if (ret < 0)
8059                 return ret;
8060
8061         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8062                 if (mask0 & (1UL << i)) {
8063                         reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8064                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8065
8066                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8067                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8068                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8069                                         i40e_write_rx_ctl(hw,
8070                                                           I40E_GLQF_HSYM(j),
8071                                                           reg);
8072                         }
8073                 }
8074         }
8075
8076         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8077         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8078                 /* Toeplitz */
8079                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8080                         PMD_DRV_LOG(DEBUG,
8081                                 "Hash function already set to Toeplitz");
8082                         goto out;
8083                 }
8084                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8085         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8086                 /* Simple XOR */
8087                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8088                         PMD_DRV_LOG(DEBUG,
8089                                 "Hash function already set to Simple XOR");
8090                         goto out;
8091                 }
8092                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8093         } else
8094                 /* Use the default, and keep it as it is */
8095                 goto out;
8096
8097         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8098
8099 out:
8100         I40E_WRITE_FLUSH(hw);
8101
8102         return 0;
8103 }
8104
8105 /**
8106  * Valid input sets for hash and flow director filters per PCTYPE
8107  */
8108 static uint64_t
8109 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8110                 enum rte_filter_type filter)
8111 {
8112         uint64_t valid;
8113
8114         static const uint64_t valid_hash_inset_table[] = {
8115                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8116                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8117                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8118                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8119                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8120                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8121                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8122                         I40E_INSET_FLEX_PAYLOAD,
8123                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8124                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8125                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8126                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8127                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8128                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8129                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8130                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8131                         I40E_INSET_FLEX_PAYLOAD,
8132                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8133                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8134                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8135                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8136                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8137                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8138                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8139                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8140                         I40E_INSET_FLEX_PAYLOAD,
8141                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8142                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8143                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8144                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8145                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8146                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8147                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8148                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8149                         I40E_INSET_FLEX_PAYLOAD,
8150                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8151                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8152                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8153                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8154                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8155                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8156                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8157                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8158                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8159                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8160                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8161                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8162                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8163                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8164                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8165                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8166                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8167                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8168                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8169                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8170                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8171                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8172                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8173                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8174                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8175                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8176                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8177                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8178                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8179                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8180                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8181                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8182                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8183                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8184                         I40E_INSET_FLEX_PAYLOAD,
8185                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8186                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8187                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8188                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8189                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8190                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8191                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8192                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8193                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8194                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8195                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8196                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8197                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8198                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8199                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8200                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8201                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8202                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8203                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8204                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8205                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8206                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8207                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8208                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8209                         I40E_INSET_FLEX_PAYLOAD,
8210                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8211                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8212                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8213                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8214                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8215                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8216                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8217                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8218                         I40E_INSET_FLEX_PAYLOAD,
8219                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8220                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8221                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8222                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8223                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8224                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8225                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8226                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8227                         I40E_INSET_FLEX_PAYLOAD,
8228                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8229                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8230                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8231                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8232                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8233                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8234                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8235                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8236                         I40E_INSET_FLEX_PAYLOAD,
8237                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8238                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8239                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8240                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8241                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8242                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8243                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8244                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8245                         I40E_INSET_FLEX_PAYLOAD,
8246                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8247                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8248                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8249                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8250                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8251                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8252                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8253                         I40E_INSET_FLEX_PAYLOAD,
8254                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8255                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8256                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8257                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8258                         I40E_INSET_FLEX_PAYLOAD,
8259         };
8260
8261         /**
8262          * Flow director supports only fields defined in
8263          * union rte_eth_fdir_flow.
8264          */
8265         static const uint64_t valid_fdir_inset_table[] = {
8266                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8267                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8268                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8269                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8270                 I40E_INSET_IPV4_TTL,
8271                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8272                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8273                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8274                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8275                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8276                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8277                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8278                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8279                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8280                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8281                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8282                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8283                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8284                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8285                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8286                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8287                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8288                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8289                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8290                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8291                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8292                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8293                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8294                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8295                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8296                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8297                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8298                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8299                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8300                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8301                 I40E_INSET_SCTP_VT,
8302                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8303                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8304                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8305                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8306                 I40E_INSET_IPV4_TTL,
8307                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8308                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8309                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8310                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8311                 I40E_INSET_IPV6_HOP_LIMIT,
8312                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8313                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8314                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8315                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8316                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8317                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8318                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8319                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8320                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8321                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8322                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8323                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8324                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8325                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8326                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8327                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8328                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8329                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8330                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8331                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8332                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8333                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8334                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8335                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8336                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8337                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8338                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8339                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8340                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8341                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8342                 I40E_INSET_SCTP_VT,
8343                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8344                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8345                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8346                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8347                 I40E_INSET_IPV6_HOP_LIMIT,
8348                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8349                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8350                 I40E_INSET_LAST_ETHER_TYPE,
8351         };
8352
8353         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8354                 return 0;
8355         if (filter == RTE_ETH_FILTER_HASH)
8356                 valid = valid_hash_inset_table[pctype];
8357         else
8358                 valid = valid_fdir_inset_table[pctype];
8359
8360         return valid;
8361 }
8362
8363 /**
8364  * Validate if the input set is allowed for a specific PCTYPE
8365  */
8366 int
8367 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8368                 enum rte_filter_type filter, uint64_t inset)
8369 {
8370         uint64_t valid;
8371
8372         valid = i40e_get_valid_input_set(pctype, filter);
8373         if (inset & (~valid))
8374                 return -EINVAL;
8375
8376         return 0;
8377 }
8378
8379 /* default input set fields combination per pctype */
8380 uint64_t
8381 i40e_get_default_input_set(uint16_t pctype)
8382 {
8383         static const uint64_t default_inset_table[] = {
8384                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8385                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8386                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8387                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8388                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8389                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8390                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8391                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8392                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8393                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8394                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8395                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8396                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8397                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8398                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8399                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8400                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8401                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8402                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8403                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8404                         I40E_INSET_SCTP_VT,
8405                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8406                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8407                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8408                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8409                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8410                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8411                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8412                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8413                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8414                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8415                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8416                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8417                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8418                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8419                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8420                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8421                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8422                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8423                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8424                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8425                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8426                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8427                         I40E_INSET_SCTP_VT,
8428                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8429                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8430                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8431                         I40E_INSET_LAST_ETHER_TYPE,
8432         };
8433
8434         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8435                 return 0;
8436
8437         return default_inset_table[pctype];
8438 }
8439
8440 /**
8441  * Parse the input set from index to logical bit masks
8442  */
8443 static int
8444 i40e_parse_input_set(uint64_t *inset,
8445                      enum i40e_filter_pctype pctype,
8446                      enum rte_eth_input_set_field *field,
8447                      uint16_t size)
8448 {
8449         uint16_t i, j;
8450         int ret = -EINVAL;
8451
8452         static const struct {
8453                 enum rte_eth_input_set_field field;
8454                 uint64_t inset;
8455         } inset_convert_table[] = {
8456                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8457                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8458                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8459                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8460                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8461                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8462                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8463                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8464                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8465                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8466                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8467                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8468                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8469                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8470                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8471                         I40E_INSET_IPV6_NEXT_HDR},
8472                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8473                         I40E_INSET_IPV6_HOP_LIMIT},
8474                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8475                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8476                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8477                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8478                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8479                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8480                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8481                         I40E_INSET_SCTP_VT},
8482                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8483                         I40E_INSET_TUNNEL_DMAC},
8484                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8485                         I40E_INSET_VLAN_TUNNEL},
8486                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8487                         I40E_INSET_TUNNEL_ID},
8488                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8489                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8490                         I40E_INSET_FLEX_PAYLOAD_W1},
8491                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8492                         I40E_INSET_FLEX_PAYLOAD_W2},
8493                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8494                         I40E_INSET_FLEX_PAYLOAD_W3},
8495                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8496                         I40E_INSET_FLEX_PAYLOAD_W4},
8497                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8498                         I40E_INSET_FLEX_PAYLOAD_W5},
8499                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8500                         I40E_INSET_FLEX_PAYLOAD_W6},
8501                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8502                         I40E_INSET_FLEX_PAYLOAD_W7},
8503                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8504                         I40E_INSET_FLEX_PAYLOAD_W8},
8505         };
8506
8507         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8508                 return ret;
8509
8510         /* Only one item allowed for default or all */
8511         if (size == 1) {
8512                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8513                         *inset = i40e_get_default_input_set(pctype);
8514                         return 0;
8515                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8516                         *inset = I40E_INSET_NONE;
8517                         return 0;
8518                 }
8519         }
8520
8521         for (i = 0, *inset = 0; i < size; i++) {
8522                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8523                         if (field[i] == inset_convert_table[j].field) {
8524                                 *inset |= inset_convert_table[j].inset;
8525                                 break;
8526                         }
8527                 }
8528
8529                 /* It contains unsupported input set, return immediately */
8530                 if (j == RTE_DIM(inset_convert_table))
8531                         return ret;
8532         }
8533
8534         return 0;
8535 }
8536
8537 /**
8538  * Translate the input set from bit masks to register aware bit masks
8539  * and vice versa
8540  */
8541 uint64_t
8542 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8543 {
8544         uint64_t val = 0;
8545         uint16_t i;
8546
8547         struct inset_map {
8548                 uint64_t inset;
8549                 uint64_t inset_reg;
8550         };
8551
8552         static const struct inset_map inset_map_common[] = {
8553                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8554                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8555                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8556                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8557                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8558                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8559                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8560                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8561                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8562                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8563                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8564                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8565                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8566                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8567                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8568                 {I40E_INSET_TUNNEL_DMAC,
8569                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8570                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8571                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8572                 {I40E_INSET_TUNNEL_SRC_PORT,
8573                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8574                 {I40E_INSET_TUNNEL_DST_PORT,
8575                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8576                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8577                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8578                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8579                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8580                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8581                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8582                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8583                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8584                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8585         };
8586
8587     /* some different registers map in x722*/
8588         static const struct inset_map inset_map_diff_x722[] = {
8589                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8590                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8591                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8592                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8593         };
8594
8595         static const struct inset_map inset_map_diff_not_x722[] = {
8596                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8597                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8598                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8599                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8600         };
8601
8602         if (input == 0)
8603                 return val;
8604
8605         /* Translate input set to register aware inset */
8606         if (type == I40E_MAC_X722) {
8607                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8608                         if (input & inset_map_diff_x722[i].inset)
8609                                 val |= inset_map_diff_x722[i].inset_reg;
8610                 }
8611         } else {
8612                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8613                         if (input & inset_map_diff_not_x722[i].inset)
8614                                 val |= inset_map_diff_not_x722[i].inset_reg;
8615                 }
8616         }
8617
8618         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8619                 if (input & inset_map_common[i].inset)
8620                         val |= inset_map_common[i].inset_reg;
8621         }
8622
8623         return val;
8624 }
8625
8626 int
8627 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8628 {
8629         uint8_t i, idx = 0;
8630         uint64_t inset_need_mask = inset;
8631
8632         static const struct {
8633                 uint64_t inset;
8634                 uint32_t mask;
8635         } inset_mask_map[] = {
8636                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8637                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8638                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8639                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8640                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8641                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8642                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8643                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8644         };
8645
8646         if (!inset || !mask || !nb_elem)
8647                 return 0;
8648
8649         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8650                 /* Clear the inset bit, if no MASK is required,
8651                  * for example proto + ttl
8652                  */
8653                 if ((inset & inset_mask_map[i].inset) ==
8654                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8655                         inset_need_mask &= ~inset_mask_map[i].inset;
8656                 if (!inset_need_mask)
8657                         return 0;
8658         }
8659         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8660                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8661                     inset_mask_map[i].inset) {
8662                         if (idx >= nb_elem) {
8663                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8664                                 return -EINVAL;
8665                         }
8666                         mask[idx] = inset_mask_map[i].mask;
8667                         idx++;
8668                 }
8669         }
8670
8671         return idx;
8672 }
8673
8674 void
8675 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8676 {
8677         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8678
8679         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8680         if (reg != val)
8681                 i40e_write_rx_ctl(hw, addr, val);
8682         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8683                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8684 }
8685
8686 static void
8687 i40e_filter_input_set_init(struct i40e_pf *pf)
8688 {
8689         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8690         enum i40e_filter_pctype pctype;
8691         uint64_t input_set, inset_reg;
8692         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8693         int num, i;
8694         uint16_t flow_type;
8695
8696         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8697              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8698                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8699
8700                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8701                         continue;
8702
8703                 input_set = i40e_get_default_input_set(pctype);
8704
8705                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8706                                                    I40E_INSET_MASK_NUM_REG);
8707                 if (num < 0)
8708                         return;
8709                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8710                                         input_set);
8711
8712                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8713                                       (uint32_t)(inset_reg & UINT32_MAX));
8714                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8715                                      (uint32_t)((inset_reg >>
8716                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8717                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8718                                       (uint32_t)(inset_reg & UINT32_MAX));
8719                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8720                                      (uint32_t)((inset_reg >>
8721                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8722
8723                 for (i = 0; i < num; i++) {
8724                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8725                                              mask_reg[i]);
8726                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8727                                              mask_reg[i]);
8728                 }
8729                 /*clear unused mask registers of the pctype */
8730                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8731                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8732                                              0);
8733                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8734                                              0);
8735                 }
8736                 I40E_WRITE_FLUSH(hw);
8737
8738                 /* store the default input set */
8739                 pf->hash_input_set[pctype] = input_set;
8740                 pf->fdir.input_set[pctype] = input_set;
8741         }
8742 }
8743
8744 int
8745 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8746                          struct rte_eth_input_set_conf *conf)
8747 {
8748         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8749         enum i40e_filter_pctype pctype;
8750         uint64_t input_set, inset_reg = 0;
8751         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8752         int ret, i, num;
8753
8754         if (!conf) {
8755                 PMD_DRV_LOG(ERR, "Invalid pointer");
8756                 return -EFAULT;
8757         }
8758         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8759             conf->op != RTE_ETH_INPUT_SET_ADD) {
8760                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8761                 return -EINVAL;
8762         }
8763
8764         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8765         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8766                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8767                 return -EINVAL;
8768         }
8769
8770         if (hw->mac.type == I40E_MAC_X722) {
8771                 /* get translated pctype value in fd pctype register */
8772                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8773                         I40E_GLQF_FD_PCTYPES((int)pctype));
8774         }
8775
8776         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8777                                    conf->inset_size);
8778         if (ret) {
8779                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8780                 return -EINVAL;
8781         }
8782
8783         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8784                 /* get inset value in register */
8785                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8786                 inset_reg <<= I40E_32_BIT_WIDTH;
8787                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8788                 input_set |= pf->hash_input_set[pctype];
8789         }
8790         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8791                                            I40E_INSET_MASK_NUM_REG);
8792         if (num < 0)
8793                 return -EINVAL;
8794
8795         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8796
8797         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8798                               (uint32_t)(inset_reg & UINT32_MAX));
8799         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8800                              (uint32_t)((inset_reg >>
8801                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8802
8803         for (i = 0; i < num; i++)
8804                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8805                                      mask_reg[i]);
8806         /*clear unused mask registers of the pctype */
8807         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8808                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8809                                      0);
8810         I40E_WRITE_FLUSH(hw);
8811
8812         pf->hash_input_set[pctype] = input_set;
8813         return 0;
8814 }
8815
8816 int
8817 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8818                          struct rte_eth_input_set_conf *conf)
8819 {
8820         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8821         enum i40e_filter_pctype pctype;
8822         uint64_t input_set, inset_reg = 0;
8823         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8824         int ret, i, num;
8825
8826         if (!hw || !conf) {
8827                 PMD_DRV_LOG(ERR, "Invalid pointer");
8828                 return -EFAULT;
8829         }
8830         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8831             conf->op != RTE_ETH_INPUT_SET_ADD) {
8832                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8833                 return -EINVAL;
8834         }
8835
8836         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8837
8838         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8839                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8840                 return -EINVAL;
8841         }
8842
8843         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8844                                    conf->inset_size);
8845         if (ret) {
8846                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8847                 return -EINVAL;
8848         }
8849
8850         /* get inset value in register */
8851         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8852         inset_reg <<= I40E_32_BIT_WIDTH;
8853         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8854
8855         /* Can not change the inset reg for flex payload for fdir,
8856          * it is done by writing I40E_PRTQF_FD_FLXINSET
8857          * in i40e_set_flex_mask_on_pctype.
8858          */
8859         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8860                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8861         else
8862                 input_set |= pf->fdir.input_set[pctype];
8863         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8864                                            I40E_INSET_MASK_NUM_REG);
8865         if (num < 0)
8866                 return -EINVAL;
8867
8868         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8869
8870         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8871                               (uint32_t)(inset_reg & UINT32_MAX));
8872         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8873                              (uint32_t)((inset_reg >>
8874                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8875
8876         for (i = 0; i < num; i++)
8877                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8878                                      mask_reg[i]);
8879         /*clear unused mask registers of the pctype */
8880         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8881                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8882                                      0);
8883         I40E_WRITE_FLUSH(hw);
8884
8885         pf->fdir.input_set[pctype] = input_set;
8886         return 0;
8887 }
8888
8889 static int
8890 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8891 {
8892         int ret = 0;
8893
8894         if (!hw || !info) {
8895                 PMD_DRV_LOG(ERR, "Invalid pointer");
8896                 return -EFAULT;
8897         }
8898
8899         switch (info->info_type) {
8900         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8901                 i40e_get_symmetric_hash_enable_per_port(hw,
8902                                         &(info->info.enable));
8903                 break;
8904         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8905                 ret = i40e_get_hash_filter_global_config(hw,
8906                                 &(info->info.global_conf));
8907                 break;
8908         default:
8909                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8910                                                         info->info_type);
8911                 ret = -EINVAL;
8912                 break;
8913         }
8914
8915         return ret;
8916 }
8917
8918 static int
8919 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8920 {
8921         int ret = 0;
8922
8923         if (!hw || !info) {
8924                 PMD_DRV_LOG(ERR, "Invalid pointer");
8925                 return -EFAULT;
8926         }
8927
8928         switch (info->info_type) {
8929         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8930                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8931                 break;
8932         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8933                 ret = i40e_set_hash_filter_global_config(hw,
8934                                 &(info->info.global_conf));
8935                 break;
8936         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8937                 ret = i40e_hash_filter_inset_select(hw,
8938                                                &(info->info.input_set_conf));
8939                 break;
8940
8941         default:
8942                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8943                                                         info->info_type);
8944                 ret = -EINVAL;
8945                 break;
8946         }
8947
8948         return ret;
8949 }
8950
8951 /* Operations for hash function */
8952 static int
8953 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8954                       enum rte_filter_op filter_op,
8955                       void *arg)
8956 {
8957         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8958         int ret = 0;
8959
8960         switch (filter_op) {
8961         case RTE_ETH_FILTER_NOP:
8962                 break;
8963         case RTE_ETH_FILTER_GET:
8964                 ret = i40e_hash_filter_get(hw,
8965                         (struct rte_eth_hash_filter_info *)arg);
8966                 break;
8967         case RTE_ETH_FILTER_SET:
8968                 ret = i40e_hash_filter_set(hw,
8969                         (struct rte_eth_hash_filter_info *)arg);
8970                 break;
8971         default:
8972                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8973                                                                 filter_op);
8974                 ret = -ENOTSUP;
8975                 break;
8976         }
8977
8978         return ret;
8979 }
8980
8981 /* Convert ethertype filter structure */
8982 static int
8983 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8984                               struct i40e_ethertype_filter *filter)
8985 {
8986         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8987         filter->input.ether_type = input->ether_type;
8988         filter->flags = input->flags;
8989         filter->queue = input->queue;
8990
8991         return 0;
8992 }
8993
8994 /* Check if there exists the ehtertype filter */
8995 struct i40e_ethertype_filter *
8996 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8997                                 const struct i40e_ethertype_filter_input *input)
8998 {
8999         int ret;
9000
9001         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9002         if (ret < 0)
9003                 return NULL;
9004
9005         return ethertype_rule->hash_map[ret];
9006 }
9007
9008 /* Add ethertype filter in SW list */
9009 static int
9010 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9011                                 struct i40e_ethertype_filter *filter)
9012 {
9013         struct i40e_ethertype_rule *rule = &pf->ethertype;
9014         int ret;
9015
9016         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9017         if (ret < 0) {
9018                 PMD_DRV_LOG(ERR,
9019                             "Failed to insert ethertype filter"
9020                             " to hash table %d!",
9021                             ret);
9022                 return ret;
9023         }
9024         rule->hash_map[ret] = filter;
9025
9026         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9027
9028         return 0;
9029 }
9030
9031 /* Delete ethertype filter in SW list */
9032 int
9033 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9034                              struct i40e_ethertype_filter_input *input)
9035 {
9036         struct i40e_ethertype_rule *rule = &pf->ethertype;
9037         struct i40e_ethertype_filter *filter;
9038         int ret;
9039
9040         ret = rte_hash_del_key(rule->hash_table, input);
9041         if (ret < 0) {
9042                 PMD_DRV_LOG(ERR,
9043                             "Failed to delete ethertype filter"
9044                             " to hash table %d!",
9045                             ret);
9046                 return ret;
9047         }
9048         filter = rule->hash_map[ret];
9049         rule->hash_map[ret] = NULL;
9050
9051         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9052         rte_free(filter);
9053
9054         return 0;
9055 }
9056
9057 /*
9058  * Configure ethertype filter, which can director packet by filtering
9059  * with mac address and ether_type or only ether_type
9060  */
9061 int
9062 i40e_ethertype_filter_set(struct i40e_pf *pf,
9063                         struct rte_eth_ethertype_filter *filter,
9064                         bool add)
9065 {
9066         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9067         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9068         struct i40e_ethertype_filter *ethertype_filter, *node;
9069         struct i40e_ethertype_filter check_filter;
9070         struct i40e_control_filter_stats stats;
9071         uint16_t flags = 0;
9072         int ret;
9073
9074         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9075                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9076                 return -EINVAL;
9077         }
9078         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9079                 filter->ether_type == ETHER_TYPE_IPv6) {
9080                 PMD_DRV_LOG(ERR,
9081                         "unsupported ether_type(0x%04x) in control packet filter.",
9082                         filter->ether_type);
9083                 return -EINVAL;
9084         }
9085         if (filter->ether_type == ETHER_TYPE_VLAN)
9086                 PMD_DRV_LOG(WARNING,
9087                         "filter vlan ether_type in first tag is not supported.");
9088
9089         /* Check if there is the filter in SW list */
9090         memset(&check_filter, 0, sizeof(check_filter));
9091         i40e_ethertype_filter_convert(filter, &check_filter);
9092         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9093                                                &check_filter.input);
9094         if (add && node) {
9095                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9096                 return -EINVAL;
9097         }
9098
9099         if (!add && !node) {
9100                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9101                 return -EINVAL;
9102         }
9103
9104         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9105                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9106         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9107                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9108         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9109
9110         memset(&stats, 0, sizeof(stats));
9111         ret = i40e_aq_add_rem_control_packet_filter(hw,
9112                         filter->mac_addr.addr_bytes,
9113                         filter->ether_type, flags,
9114                         pf->main_vsi->seid,
9115                         filter->queue, add, &stats, NULL);
9116
9117         PMD_DRV_LOG(INFO,
9118                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9119                 ret, stats.mac_etype_used, stats.etype_used,
9120                 stats.mac_etype_free, stats.etype_free);
9121         if (ret < 0)
9122                 return -ENOSYS;
9123
9124         /* Add or delete a filter in SW list */
9125         if (add) {
9126                 ethertype_filter = rte_zmalloc("ethertype_filter",
9127                                        sizeof(*ethertype_filter), 0);
9128                 rte_memcpy(ethertype_filter, &check_filter,
9129                            sizeof(check_filter));
9130                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9131         } else {
9132                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9133         }
9134
9135         return ret;
9136 }
9137
9138 /*
9139  * Handle operations for ethertype filter.
9140  */
9141 static int
9142 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9143                                 enum rte_filter_op filter_op,
9144                                 void *arg)
9145 {
9146         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9147         int ret = 0;
9148
9149         if (filter_op == RTE_ETH_FILTER_NOP)
9150                 return ret;
9151
9152         if (arg == NULL) {
9153                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9154                             filter_op);
9155                 return -EINVAL;
9156         }
9157
9158         switch (filter_op) {
9159         case RTE_ETH_FILTER_ADD:
9160                 ret = i40e_ethertype_filter_set(pf,
9161                         (struct rte_eth_ethertype_filter *)arg,
9162                         TRUE);
9163                 break;
9164         case RTE_ETH_FILTER_DELETE:
9165                 ret = i40e_ethertype_filter_set(pf,
9166                         (struct rte_eth_ethertype_filter *)arg,
9167                         FALSE);
9168                 break;
9169         default:
9170                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9171                 ret = -ENOSYS;
9172                 break;
9173         }
9174         return ret;
9175 }
9176
9177 static int
9178 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9179                      enum rte_filter_type filter_type,
9180                      enum rte_filter_op filter_op,
9181                      void *arg)
9182 {
9183         int ret = 0;
9184
9185         if (dev == NULL)
9186                 return -EINVAL;
9187
9188         switch (filter_type) {
9189         case RTE_ETH_FILTER_NONE:
9190                 /* For global configuration */
9191                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9192                 break;
9193         case RTE_ETH_FILTER_HASH:
9194                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9195                 break;
9196         case RTE_ETH_FILTER_MACVLAN:
9197                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9198                 break;
9199         case RTE_ETH_FILTER_ETHERTYPE:
9200                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9201                 break;
9202         case RTE_ETH_FILTER_TUNNEL:
9203                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9204                 break;
9205         case RTE_ETH_FILTER_FDIR:
9206                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9207                 break;
9208         case RTE_ETH_FILTER_GENERIC:
9209                 if (filter_op != RTE_ETH_FILTER_GET)
9210                         return -EINVAL;
9211                 *(const void **)arg = &i40e_flow_ops;
9212                 break;
9213         default:
9214                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9215                                                         filter_type);
9216                 ret = -EINVAL;
9217                 break;
9218         }
9219
9220         return ret;
9221 }
9222
9223 /*
9224  * Check and enable Extended Tag.
9225  * Enabling Extended Tag is important for 40G performance.
9226  */
9227 static void
9228 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9229 {
9230         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9231         uint32_t buf = 0;
9232         int ret;
9233
9234         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9235                                       PCI_DEV_CAP_REG);
9236         if (ret < 0) {
9237                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9238                             PCI_DEV_CAP_REG);
9239                 return;
9240         }
9241         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9242                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9243                 return;
9244         }
9245
9246         buf = 0;
9247         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9248                                       PCI_DEV_CTRL_REG);
9249         if (ret < 0) {
9250                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9251                             PCI_DEV_CTRL_REG);
9252                 return;
9253         }
9254         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9255                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9256                 return;
9257         }
9258         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9259         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9260                                        PCI_DEV_CTRL_REG);
9261         if (ret < 0) {
9262                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9263                             PCI_DEV_CTRL_REG);
9264                 return;
9265         }
9266 }
9267
9268 /*
9269  * As some registers wouldn't be reset unless a global hardware reset,
9270  * hardware initialization is needed to put those registers into an
9271  * expected initial state.
9272  */
9273 static void
9274 i40e_hw_init(struct rte_eth_dev *dev)
9275 {
9276         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9277
9278         i40e_enable_extended_tag(dev);
9279
9280         /* clear the PF Queue Filter control register */
9281         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9282
9283         /* Disable symmetric hash per port */
9284         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9285 }
9286
9287 /*
9288  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9289  * however this function will return only one highest pctype index,
9290  * which is not quite correct. This is known problem of i40e driver
9291  * and needs to be fixed later.
9292  */
9293 enum i40e_filter_pctype
9294 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9295 {
9296         int i;
9297         uint64_t pctype_mask;
9298
9299         if (flow_type < I40E_FLOW_TYPE_MAX) {
9300                 pctype_mask = adapter->pctypes_tbl[flow_type];
9301                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9302                         if (pctype_mask & (1ULL << i))
9303                                 return (enum i40e_filter_pctype)i;
9304                 }
9305         }
9306         return I40E_FILTER_PCTYPE_INVALID;
9307 }
9308
9309 uint16_t
9310 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9311                         enum i40e_filter_pctype pctype)
9312 {
9313         uint16_t flowtype;
9314         uint64_t pctype_mask = 1ULL << pctype;
9315
9316         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9317              flowtype++) {
9318                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9319                         return flowtype;
9320         }
9321
9322         return RTE_ETH_FLOW_UNKNOWN;
9323 }
9324
9325 /*
9326  * On X710, performance number is far from the expectation on recent firmware
9327  * versions; on XL710, performance number is also far from the expectation on
9328  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9329  * mode is enabled and port MAC address is equal to the packet destination MAC
9330  * address. The fix for this issue may not be integrated in the following
9331  * firmware version. So the workaround in software driver is needed. It needs
9332  * to modify the initial values of 3 internal only registers for both X710 and
9333  * XL710. Note that the values for X710 or XL710 could be different, and the
9334  * workaround can be removed when it is fixed in firmware in the future.
9335  */
9336
9337 /* For both X710 and XL710 */
9338 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9339 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9340 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9341
9342 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9343 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9344
9345 /* For X722 */
9346 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9347 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9348
9349 /* For X710 */
9350 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9351 /* For XL710 */
9352 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9353 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9354
9355 static int
9356 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9357 {
9358         enum i40e_status_code status;
9359         struct i40e_aq_get_phy_abilities_resp phy_ab;
9360         int ret = -ENOTSUP;
9361         int retries = 0;
9362
9363         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9364                                               NULL);
9365
9366         while (status) {
9367                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9368                         status);
9369                 retries++;
9370                 rte_delay_us(100000);
9371                 if  (retries < 5)
9372                         status = i40e_aq_get_phy_capabilities(hw, false,
9373                                         true, &phy_ab, NULL);
9374                 else
9375                         return ret;
9376         }
9377         return 0;
9378 }
9379
9380 static void
9381 i40e_configure_registers(struct i40e_hw *hw)
9382 {
9383         static struct {
9384                 uint32_t addr;
9385                 uint64_t val;
9386         } reg_table[] = {
9387                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9388                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9389                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9390         };
9391         uint64_t reg;
9392         uint32_t i;
9393         int ret;
9394
9395         for (i = 0; i < RTE_DIM(reg_table); i++) {
9396                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9397                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9398                                 reg_table[i].val =
9399                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9400                         else /* For X710/XL710/XXV710 */
9401                                 if (hw->aq.fw_maj_ver < 6)
9402                                         reg_table[i].val =
9403                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9404                                 else
9405                                         reg_table[i].val =
9406                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9407                 }
9408
9409                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9410                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9411                                 reg_table[i].val =
9412                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9413                         else /* For X710/XL710/XXV710 */
9414                                 reg_table[i].val =
9415                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9416                 }
9417
9418                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9419                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9420                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9421                                 reg_table[i].val =
9422                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9423                         else /* For X710 */
9424                                 reg_table[i].val =
9425                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9426                 }
9427
9428                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9429                                                         &reg, NULL);
9430                 if (ret < 0) {
9431                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9432                                                         reg_table[i].addr);
9433                         break;
9434                 }
9435                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9436                                                 reg_table[i].addr, reg);
9437                 if (reg == reg_table[i].val)
9438                         continue;
9439
9440                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9441                                                 reg_table[i].val, NULL);
9442                 if (ret < 0) {
9443                         PMD_DRV_LOG(ERR,
9444                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9445                                 reg_table[i].val, reg_table[i].addr);
9446                         break;
9447                 }
9448                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9449                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9450         }
9451 }
9452
9453 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9454 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9455 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9456 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9457 static int
9458 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9459 {
9460         uint32_t reg;
9461         int ret;
9462
9463         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9464                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9465                 return -EINVAL;
9466         }
9467
9468         /* Configure for double VLAN RX stripping */
9469         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9470         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9471                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9472                 ret = i40e_aq_debug_write_register(hw,
9473                                                    I40E_VSI_TSR(vsi->vsi_id),
9474                                                    reg, NULL);
9475                 if (ret < 0) {
9476                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9477                                     vsi->vsi_id);
9478                         return I40E_ERR_CONFIG;
9479                 }
9480         }
9481
9482         /* Configure for double VLAN TX insertion */
9483         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9484         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9485                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9486                 ret = i40e_aq_debug_write_register(hw,
9487                                                    I40E_VSI_L2TAGSTXVALID(
9488                                                    vsi->vsi_id), reg, NULL);
9489                 if (ret < 0) {
9490                         PMD_DRV_LOG(ERR,
9491                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9492                                 vsi->vsi_id);
9493                         return I40E_ERR_CONFIG;
9494                 }
9495         }
9496
9497         return 0;
9498 }
9499
9500 /**
9501  * i40e_aq_add_mirror_rule
9502  * @hw: pointer to the hardware structure
9503  * @seid: VEB seid to add mirror rule to
9504  * @dst_id: destination vsi seid
9505  * @entries: Buffer which contains the entities to be mirrored
9506  * @count: number of entities contained in the buffer
9507  * @rule_id:the rule_id of the rule to be added
9508  *
9509  * Add a mirror rule for a given veb.
9510  *
9511  **/
9512 static enum i40e_status_code
9513 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9514                         uint16_t seid, uint16_t dst_id,
9515                         uint16_t rule_type, uint16_t *entries,
9516                         uint16_t count, uint16_t *rule_id)
9517 {
9518         struct i40e_aq_desc desc;
9519         struct i40e_aqc_add_delete_mirror_rule cmd;
9520         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9521                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9522                 &desc.params.raw;
9523         uint16_t buff_len;
9524         enum i40e_status_code status;
9525
9526         i40e_fill_default_direct_cmd_desc(&desc,
9527                                           i40e_aqc_opc_add_mirror_rule);
9528         memset(&cmd, 0, sizeof(cmd));
9529
9530         buff_len = sizeof(uint16_t) * count;
9531         desc.datalen = rte_cpu_to_le_16(buff_len);
9532         if (buff_len > 0)
9533                 desc.flags |= rte_cpu_to_le_16(
9534                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9535         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9536                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9537         cmd.num_entries = rte_cpu_to_le_16(count);
9538         cmd.seid = rte_cpu_to_le_16(seid);
9539         cmd.destination = rte_cpu_to_le_16(dst_id);
9540
9541         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9542         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9543         PMD_DRV_LOG(INFO,
9544                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9545                 hw->aq.asq_last_status, resp->rule_id,
9546                 resp->mirror_rules_used, resp->mirror_rules_free);
9547         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9548
9549         return status;
9550 }
9551
9552 /**
9553  * i40e_aq_del_mirror_rule
9554  * @hw: pointer to the hardware structure
9555  * @seid: VEB seid to add mirror rule to
9556  * @entries: Buffer which contains the entities to be mirrored
9557  * @count: number of entities contained in the buffer
9558  * @rule_id:the rule_id of the rule to be delete
9559  *
9560  * Delete a mirror rule for a given veb.
9561  *
9562  **/
9563 static enum i40e_status_code
9564 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9565                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9566                 uint16_t count, uint16_t rule_id)
9567 {
9568         struct i40e_aq_desc desc;
9569         struct i40e_aqc_add_delete_mirror_rule cmd;
9570         uint16_t buff_len = 0;
9571         enum i40e_status_code status;
9572         void *buff = NULL;
9573
9574         i40e_fill_default_direct_cmd_desc(&desc,
9575                                           i40e_aqc_opc_delete_mirror_rule);
9576         memset(&cmd, 0, sizeof(cmd));
9577         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9578                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9579                                                           I40E_AQ_FLAG_RD));
9580                 cmd.num_entries = count;
9581                 buff_len = sizeof(uint16_t) * count;
9582                 desc.datalen = rte_cpu_to_le_16(buff_len);
9583                 buff = (void *)entries;
9584         } else
9585                 /* rule id is filled in destination field for deleting mirror rule */
9586                 cmd.destination = rte_cpu_to_le_16(rule_id);
9587
9588         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9589                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9590         cmd.seid = rte_cpu_to_le_16(seid);
9591
9592         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9593         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9594
9595         return status;
9596 }
9597
9598 /**
9599  * i40e_mirror_rule_set
9600  * @dev: pointer to the hardware structure
9601  * @mirror_conf: mirror rule info
9602  * @sw_id: mirror rule's sw_id
9603  * @on: enable/disable
9604  *
9605  * set a mirror rule.
9606  *
9607  **/
9608 static int
9609 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9610                         struct rte_eth_mirror_conf *mirror_conf,
9611                         uint8_t sw_id, uint8_t on)
9612 {
9613         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9614         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9615         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9616         struct i40e_mirror_rule *parent = NULL;
9617         uint16_t seid, dst_seid, rule_id;
9618         uint16_t i, j = 0;
9619         int ret;
9620
9621         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9622
9623         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9624                 PMD_DRV_LOG(ERR,
9625                         "mirror rule can not be configured without veb or vfs.");
9626                 return -ENOSYS;
9627         }
9628         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9629                 PMD_DRV_LOG(ERR, "mirror table is full.");
9630                 return -ENOSPC;
9631         }
9632         if (mirror_conf->dst_pool > pf->vf_num) {
9633                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9634                                  mirror_conf->dst_pool);
9635                 return -EINVAL;
9636         }
9637
9638         seid = pf->main_vsi->veb->seid;
9639
9640         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9641                 if (sw_id <= it->index) {
9642                         mirr_rule = it;
9643                         break;
9644                 }
9645                 parent = it;
9646         }
9647         if (mirr_rule && sw_id == mirr_rule->index) {
9648                 if (on) {
9649                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9650                         return -EEXIST;
9651                 } else {
9652                         ret = i40e_aq_del_mirror_rule(hw, seid,
9653                                         mirr_rule->rule_type,
9654                                         mirr_rule->entries,
9655                                         mirr_rule->num_entries, mirr_rule->id);
9656                         if (ret < 0) {
9657                                 PMD_DRV_LOG(ERR,
9658                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9659                                         ret, hw->aq.asq_last_status);
9660                                 return -ENOSYS;
9661                         }
9662                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9663                         rte_free(mirr_rule);
9664                         pf->nb_mirror_rule--;
9665                         return 0;
9666                 }
9667         } else if (!on) {
9668                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9669                 return -ENOENT;
9670         }
9671
9672         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9673                                 sizeof(struct i40e_mirror_rule) , 0);
9674         if (!mirr_rule) {
9675                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9676                 return I40E_ERR_NO_MEMORY;
9677         }
9678         switch (mirror_conf->rule_type) {
9679         case ETH_MIRROR_VLAN:
9680                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9681                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9682                                 mirr_rule->entries[j] =
9683                                         mirror_conf->vlan.vlan_id[i];
9684                                 j++;
9685                         }
9686                 }
9687                 if (j == 0) {
9688                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9689                         rte_free(mirr_rule);
9690                         return -EINVAL;
9691                 }
9692                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9693                 break;
9694         case ETH_MIRROR_VIRTUAL_POOL_UP:
9695         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9696                 /* check if the specified pool bit is out of range */
9697                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9698                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9699                         rte_free(mirr_rule);
9700                         return -EINVAL;
9701                 }
9702                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9703                         if (mirror_conf->pool_mask & (1ULL << i)) {
9704                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9705                                 j++;
9706                         }
9707                 }
9708                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9709                         /* add pf vsi to entries */
9710                         mirr_rule->entries[j] = pf->main_vsi_seid;
9711                         j++;
9712                 }
9713                 if (j == 0) {
9714                         PMD_DRV_LOG(ERR, "pool is not specified.");
9715                         rte_free(mirr_rule);
9716                         return -EINVAL;
9717                 }
9718                 /* egress and ingress in aq commands means from switch but not port */
9719                 mirr_rule->rule_type =
9720                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9721                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9722                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9723                 break;
9724         case ETH_MIRROR_UPLINK_PORT:
9725                 /* egress and ingress in aq commands means from switch but not port*/
9726                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9727                 break;
9728         case ETH_MIRROR_DOWNLINK_PORT:
9729                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9730                 break;
9731         default:
9732                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9733                         mirror_conf->rule_type);
9734                 rte_free(mirr_rule);
9735                 return -EINVAL;
9736         }
9737
9738         /* If the dst_pool is equal to vf_num, consider it as PF */
9739         if (mirror_conf->dst_pool == pf->vf_num)
9740                 dst_seid = pf->main_vsi_seid;
9741         else
9742                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9743
9744         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9745                                       mirr_rule->rule_type, mirr_rule->entries,
9746                                       j, &rule_id);
9747         if (ret < 0) {
9748                 PMD_DRV_LOG(ERR,
9749                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9750                         ret, hw->aq.asq_last_status);
9751                 rte_free(mirr_rule);
9752                 return -ENOSYS;
9753         }
9754
9755         mirr_rule->index = sw_id;
9756         mirr_rule->num_entries = j;
9757         mirr_rule->id = rule_id;
9758         mirr_rule->dst_vsi_seid = dst_seid;
9759
9760         if (parent)
9761                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9762         else
9763                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9764
9765         pf->nb_mirror_rule++;
9766         return 0;
9767 }
9768
9769 /**
9770  * i40e_mirror_rule_reset
9771  * @dev: pointer to the device
9772  * @sw_id: mirror rule's sw_id
9773  *
9774  * reset a mirror rule.
9775  *
9776  **/
9777 static int
9778 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9779 {
9780         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9782         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9783         uint16_t seid;
9784         int ret;
9785
9786         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9787
9788         seid = pf->main_vsi->veb->seid;
9789
9790         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9791                 if (sw_id == it->index) {
9792                         mirr_rule = it;
9793                         break;
9794                 }
9795         }
9796         if (mirr_rule) {
9797                 ret = i40e_aq_del_mirror_rule(hw, seid,
9798                                 mirr_rule->rule_type,
9799                                 mirr_rule->entries,
9800                                 mirr_rule->num_entries, mirr_rule->id);
9801                 if (ret < 0) {
9802                         PMD_DRV_LOG(ERR,
9803                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9804                                 ret, hw->aq.asq_last_status);
9805                         return -ENOSYS;
9806                 }
9807                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9808                 rte_free(mirr_rule);
9809                 pf->nb_mirror_rule--;
9810         } else {
9811                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9812                 return -ENOENT;
9813         }
9814         return 0;
9815 }
9816
9817 static uint64_t
9818 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9819 {
9820         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9821         uint64_t systim_cycles;
9822
9823         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9824         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9825                         << 32;
9826
9827         return systim_cycles;
9828 }
9829
9830 static uint64_t
9831 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9832 {
9833         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9834         uint64_t rx_tstamp;
9835
9836         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9837         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9838                         << 32;
9839
9840         return rx_tstamp;
9841 }
9842
9843 static uint64_t
9844 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9845 {
9846         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9847         uint64_t tx_tstamp;
9848
9849         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9850         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9851                         << 32;
9852
9853         return tx_tstamp;
9854 }
9855
9856 static void
9857 i40e_start_timecounters(struct rte_eth_dev *dev)
9858 {
9859         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9860         struct i40e_adapter *adapter =
9861                         (struct i40e_adapter *)dev->data->dev_private;
9862         struct rte_eth_link link;
9863         uint32_t tsync_inc_l;
9864         uint32_t tsync_inc_h;
9865
9866         /* Get current link speed. */
9867         memset(&link, 0, sizeof(link));
9868         i40e_dev_link_update(dev, 1);
9869         rte_i40e_dev_atomic_read_link_status(dev, &link);
9870
9871         switch (link.link_speed) {
9872         case ETH_SPEED_NUM_40G:
9873                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9874                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9875                 break;
9876         case ETH_SPEED_NUM_10G:
9877                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9878                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9879                 break;
9880         case ETH_SPEED_NUM_1G:
9881                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9882                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9883                 break;
9884         default:
9885                 tsync_inc_l = 0x0;
9886                 tsync_inc_h = 0x0;
9887         }
9888
9889         /* Set the timesync increment value. */
9890         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9891         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9892
9893         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9894         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9895         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9896
9897         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9898         adapter->systime_tc.cc_shift = 0;
9899         adapter->systime_tc.nsec_mask = 0;
9900
9901         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9902         adapter->rx_tstamp_tc.cc_shift = 0;
9903         adapter->rx_tstamp_tc.nsec_mask = 0;
9904
9905         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9906         adapter->tx_tstamp_tc.cc_shift = 0;
9907         adapter->tx_tstamp_tc.nsec_mask = 0;
9908 }
9909
9910 static int
9911 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9912 {
9913         struct i40e_adapter *adapter =
9914                         (struct i40e_adapter *)dev->data->dev_private;
9915
9916         adapter->systime_tc.nsec += delta;
9917         adapter->rx_tstamp_tc.nsec += delta;
9918         adapter->tx_tstamp_tc.nsec += delta;
9919
9920         return 0;
9921 }
9922
9923 static int
9924 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9925 {
9926         uint64_t ns;
9927         struct i40e_adapter *adapter =
9928                         (struct i40e_adapter *)dev->data->dev_private;
9929
9930         ns = rte_timespec_to_ns(ts);
9931
9932         /* Set the timecounters to a new value. */
9933         adapter->systime_tc.nsec = ns;
9934         adapter->rx_tstamp_tc.nsec = ns;
9935         adapter->tx_tstamp_tc.nsec = ns;
9936
9937         return 0;
9938 }
9939
9940 static int
9941 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9942 {
9943         uint64_t ns, systime_cycles;
9944         struct i40e_adapter *adapter =
9945                         (struct i40e_adapter *)dev->data->dev_private;
9946
9947         systime_cycles = i40e_read_systime_cyclecounter(dev);
9948         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9949         *ts = rte_ns_to_timespec(ns);
9950
9951         return 0;
9952 }
9953
9954 static int
9955 i40e_timesync_enable(struct rte_eth_dev *dev)
9956 {
9957         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9958         uint32_t tsync_ctl_l;
9959         uint32_t tsync_ctl_h;
9960
9961         /* Stop the timesync system time. */
9962         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9963         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9964         /* Reset the timesync system time value. */
9965         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9966         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9967
9968         i40e_start_timecounters(dev);
9969
9970         /* Clear timesync registers. */
9971         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9972         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9973         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9974         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9975         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9976         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9977
9978         /* Enable timestamping of PTP packets. */
9979         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9980         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9981
9982         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9983         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9984         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9985
9986         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9987         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9988
9989         return 0;
9990 }
9991
9992 static int
9993 i40e_timesync_disable(struct rte_eth_dev *dev)
9994 {
9995         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9996         uint32_t tsync_ctl_l;
9997         uint32_t tsync_ctl_h;
9998
9999         /* Disable timestamping of transmitted PTP packets. */
10000         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10001         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10002
10003         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10004         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10005
10006         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10007         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10008
10009         /* Reset the timesync increment value. */
10010         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10011         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10012
10013         return 0;
10014 }
10015
10016 static int
10017 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10018                                 struct timespec *timestamp, uint32_t flags)
10019 {
10020         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10021         struct i40e_adapter *adapter =
10022                 (struct i40e_adapter *)dev->data->dev_private;
10023
10024         uint32_t sync_status;
10025         uint32_t index = flags & 0x03;
10026         uint64_t rx_tstamp_cycles;
10027         uint64_t ns;
10028
10029         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10030         if ((sync_status & (1 << index)) == 0)
10031                 return -EINVAL;
10032
10033         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10034         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10035         *timestamp = rte_ns_to_timespec(ns);
10036
10037         return 0;
10038 }
10039
10040 static int
10041 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10042                                 struct timespec *timestamp)
10043 {
10044         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10045         struct i40e_adapter *adapter =
10046                 (struct i40e_adapter *)dev->data->dev_private;
10047
10048         uint32_t sync_status;
10049         uint64_t tx_tstamp_cycles;
10050         uint64_t ns;
10051
10052         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10053         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10054                 return -EINVAL;
10055
10056         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10057         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10058         *timestamp = rte_ns_to_timespec(ns);
10059
10060         return 0;
10061 }
10062
10063 /*
10064  * i40e_parse_dcb_configure - parse dcb configure from user
10065  * @dev: the device being configured
10066  * @dcb_cfg: pointer of the result of parse
10067  * @*tc_map: bit map of enabled traffic classes
10068  *
10069  * Returns 0 on success, negative value on failure
10070  */
10071 static int
10072 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10073                          struct i40e_dcbx_config *dcb_cfg,
10074                          uint8_t *tc_map)
10075 {
10076         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10077         uint8_t i, tc_bw, bw_lf;
10078
10079         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10080
10081         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10082         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10083                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10084                 return -EINVAL;
10085         }
10086
10087         /* assume each tc has the same bw */
10088         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10089         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10090                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10091         /* to ensure the sum of tcbw is equal to 100 */
10092         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10093         for (i = 0; i < bw_lf; i++)
10094                 dcb_cfg->etscfg.tcbwtable[i]++;
10095
10096         /* assume each tc has the same Transmission Selection Algorithm */
10097         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10098                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10099
10100         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10101                 dcb_cfg->etscfg.prioritytable[i] =
10102                                 dcb_rx_conf->dcb_tc[i];
10103
10104         /* FW needs one App to configure HW */
10105         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10106         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10107         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10108         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10109
10110         if (dcb_rx_conf->nb_tcs == 0)
10111                 *tc_map = 1; /* tc0 only */
10112         else
10113                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10114
10115         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10116                 dcb_cfg->pfc.willing = 0;
10117                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10118                 dcb_cfg->pfc.pfcenable = *tc_map;
10119         }
10120         return 0;
10121 }
10122
10123
10124 static enum i40e_status_code
10125 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10126                               struct i40e_aqc_vsi_properties_data *info,
10127                               uint8_t enabled_tcmap)
10128 {
10129         enum i40e_status_code ret;
10130         int i, total_tc = 0;
10131         uint16_t qpnum_per_tc, bsf, qp_idx;
10132         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10133         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10134         uint16_t used_queues;
10135
10136         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10137         if (ret != I40E_SUCCESS)
10138                 return ret;
10139
10140         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10141                 if (enabled_tcmap & (1 << i))
10142                         total_tc++;
10143         }
10144         if (total_tc == 0)
10145                 total_tc = 1;
10146         vsi->enabled_tc = enabled_tcmap;
10147
10148         /* different VSI has different queues assigned */
10149         if (vsi->type == I40E_VSI_MAIN)
10150                 used_queues = dev_data->nb_rx_queues -
10151                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10152         else if (vsi->type == I40E_VSI_VMDQ2)
10153                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10154         else {
10155                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10156                 return I40E_ERR_NO_AVAILABLE_VSI;
10157         }
10158
10159         qpnum_per_tc = used_queues / total_tc;
10160         /* Number of queues per enabled TC */
10161         if (qpnum_per_tc == 0) {
10162                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10163                 return I40E_ERR_INVALID_QP_ID;
10164         }
10165         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10166                                 I40E_MAX_Q_PER_TC);
10167         bsf = rte_bsf32(qpnum_per_tc);
10168
10169         /**
10170          * Configure TC and queue mapping parameters, for enabled TC,
10171          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10172          * default queue will serve it.
10173          */
10174         qp_idx = 0;
10175         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10176                 if (vsi->enabled_tc & (1 << i)) {
10177                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10178                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10179                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10180                         qp_idx += qpnum_per_tc;
10181                 } else
10182                         info->tc_mapping[i] = 0;
10183         }
10184
10185         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10186         if (vsi->type == I40E_VSI_SRIOV) {
10187                 info->mapping_flags |=
10188                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10189                 for (i = 0; i < vsi->nb_qps; i++)
10190                         info->queue_mapping[i] =
10191                                 rte_cpu_to_le_16(vsi->base_queue + i);
10192         } else {
10193                 info->mapping_flags |=
10194                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10195                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10196         }
10197         info->valid_sections |=
10198                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10199
10200         return I40E_SUCCESS;
10201 }
10202
10203 /*
10204  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10205  * @veb: VEB to be configured
10206  * @tc_map: enabled TC bitmap
10207  *
10208  * Returns 0 on success, negative value on failure
10209  */
10210 static enum i40e_status_code
10211 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10212 {
10213         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10214         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10215         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10216         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10217         enum i40e_status_code ret = I40E_SUCCESS;
10218         int i;
10219         uint32_t bw_max;
10220
10221         /* Check if enabled_tc is same as existing or new TCs */
10222         if (veb->enabled_tc == tc_map)
10223                 return ret;
10224
10225         /* configure tc bandwidth */
10226         memset(&veb_bw, 0, sizeof(veb_bw));
10227         veb_bw.tc_valid_bits = tc_map;
10228         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10229         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10230                 if (tc_map & BIT_ULL(i))
10231                         veb_bw.tc_bw_share_credits[i] = 1;
10232         }
10233         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10234                                                    &veb_bw, NULL);
10235         if (ret) {
10236                 PMD_INIT_LOG(ERR,
10237                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10238                         hw->aq.asq_last_status);
10239                 return ret;
10240         }
10241
10242         memset(&ets_query, 0, sizeof(ets_query));
10243         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10244                                                    &ets_query, NULL);
10245         if (ret != I40E_SUCCESS) {
10246                 PMD_DRV_LOG(ERR,
10247                         "Failed to get switch_comp ETS configuration %u",
10248                         hw->aq.asq_last_status);
10249                 return ret;
10250         }
10251         memset(&bw_query, 0, sizeof(bw_query));
10252         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10253                                                   &bw_query, NULL);
10254         if (ret != I40E_SUCCESS) {
10255                 PMD_DRV_LOG(ERR,
10256                         "Failed to get switch_comp bandwidth configuration %u",
10257                         hw->aq.asq_last_status);
10258                 return ret;
10259         }
10260
10261         /* store and print out BW info */
10262         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10263         veb->bw_info.bw_max = ets_query.tc_bw_max;
10264         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10265         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10266         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10267                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10268                      I40E_16_BIT_WIDTH);
10269         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10270                 veb->bw_info.bw_ets_share_credits[i] =
10271                                 bw_query.tc_bw_share_credits[i];
10272                 veb->bw_info.bw_ets_credits[i] =
10273                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10274                 /* 4 bits per TC, 4th bit is reserved */
10275                 veb->bw_info.bw_ets_max[i] =
10276                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10277                                   RTE_LEN2MASK(3, uint8_t));
10278                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10279                             veb->bw_info.bw_ets_share_credits[i]);
10280                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10281                             veb->bw_info.bw_ets_credits[i]);
10282                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10283                             veb->bw_info.bw_ets_max[i]);
10284         }
10285
10286         veb->enabled_tc = tc_map;
10287
10288         return ret;
10289 }
10290
10291
10292 /*
10293  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10294  * @vsi: VSI to be configured
10295  * @tc_map: enabled TC bitmap
10296  *
10297  * Returns 0 on success, negative value on failure
10298  */
10299 static enum i40e_status_code
10300 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10301 {
10302         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10303         struct i40e_vsi_context ctxt;
10304         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10305         enum i40e_status_code ret = I40E_SUCCESS;
10306         int i;
10307
10308         /* Check if enabled_tc is same as existing or new TCs */
10309         if (vsi->enabled_tc == tc_map)
10310                 return ret;
10311
10312         /* configure tc bandwidth */
10313         memset(&bw_data, 0, sizeof(bw_data));
10314         bw_data.tc_valid_bits = tc_map;
10315         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10316         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10317                 if (tc_map & BIT_ULL(i))
10318                         bw_data.tc_bw_credits[i] = 1;
10319         }
10320         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10321         if (ret) {
10322                 PMD_INIT_LOG(ERR,
10323                         "AQ command Config VSI BW allocation per TC failed = %d",
10324                         hw->aq.asq_last_status);
10325                 goto out;
10326         }
10327         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10328                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10329
10330         /* Update Queue Pairs Mapping for currently enabled UPs */
10331         ctxt.seid = vsi->seid;
10332         ctxt.pf_num = hw->pf_id;
10333         ctxt.vf_num = 0;
10334         ctxt.uplink_seid = vsi->uplink_seid;
10335         ctxt.info = vsi->info;
10336         i40e_get_cap(hw);
10337         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10338         if (ret)
10339                 goto out;
10340
10341         /* Update the VSI after updating the VSI queue-mapping information */
10342         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10343         if (ret) {
10344                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10345                         hw->aq.asq_last_status);
10346                 goto out;
10347         }
10348         /* update the local VSI info with updated queue map */
10349         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10350                                         sizeof(vsi->info.tc_mapping));
10351         rte_memcpy(&vsi->info.queue_mapping,
10352                         &ctxt.info.queue_mapping,
10353                 sizeof(vsi->info.queue_mapping));
10354         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10355         vsi->info.valid_sections = 0;
10356
10357         /* query and update current VSI BW information */
10358         ret = i40e_vsi_get_bw_config(vsi);
10359         if (ret) {
10360                 PMD_INIT_LOG(ERR,
10361                          "Failed updating vsi bw info, err %s aq_err %s",
10362                          i40e_stat_str(hw, ret),
10363                          i40e_aq_str(hw, hw->aq.asq_last_status));
10364                 goto out;
10365         }
10366
10367         vsi->enabled_tc = tc_map;
10368
10369 out:
10370         return ret;
10371 }
10372
10373 /*
10374  * i40e_dcb_hw_configure - program the dcb setting to hw
10375  * @pf: pf the configuration is taken on
10376  * @new_cfg: new configuration
10377  * @tc_map: enabled TC bitmap
10378  *
10379  * Returns 0 on success, negative value on failure
10380  */
10381 static enum i40e_status_code
10382 i40e_dcb_hw_configure(struct i40e_pf *pf,
10383                       struct i40e_dcbx_config *new_cfg,
10384                       uint8_t tc_map)
10385 {
10386         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10387         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10388         struct i40e_vsi *main_vsi = pf->main_vsi;
10389         struct i40e_vsi_list *vsi_list;
10390         enum i40e_status_code ret;
10391         int i;
10392         uint32_t val;
10393
10394         /* Use the FW API if FW > v4.4*/
10395         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10396               (hw->aq.fw_maj_ver >= 5))) {
10397                 PMD_INIT_LOG(ERR,
10398                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10399                 return I40E_ERR_FIRMWARE_API_VERSION;
10400         }
10401
10402         /* Check if need reconfiguration */
10403         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10404                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10405                 return I40E_SUCCESS;
10406         }
10407
10408         /* Copy the new config to the current config */
10409         *old_cfg = *new_cfg;
10410         old_cfg->etsrec = old_cfg->etscfg;
10411         ret = i40e_set_dcb_config(hw);
10412         if (ret) {
10413                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10414                          i40e_stat_str(hw, ret),
10415                          i40e_aq_str(hw, hw->aq.asq_last_status));
10416                 return ret;
10417         }
10418         /* set receive Arbiter to RR mode and ETS scheme by default */
10419         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10420                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10421                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10422                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10423                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10424                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10425                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10426                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10427                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10428                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10429                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10430                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10431                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10432         }
10433         /* get local mib to check whether it is configured correctly */
10434         /* IEEE mode */
10435         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10436         /* Get Local DCB Config */
10437         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10438                                      &hw->local_dcbx_config);
10439
10440         /* if Veb is created, need to update TC of it at first */
10441         if (main_vsi->veb) {
10442                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10443                 if (ret)
10444                         PMD_INIT_LOG(WARNING,
10445                                  "Failed configuring TC for VEB seid=%d",
10446                                  main_vsi->veb->seid);
10447         }
10448         /* Update each VSI */
10449         i40e_vsi_config_tc(main_vsi, tc_map);
10450         if (main_vsi->veb) {
10451                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10452                         /* Beside main VSI and VMDQ VSIs, only enable default
10453                          * TC for other VSIs
10454                          */
10455                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10456                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10457                                                          tc_map);
10458                         else
10459                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10460                                                          I40E_DEFAULT_TCMAP);
10461                         if (ret)
10462                                 PMD_INIT_LOG(WARNING,
10463                                         "Failed configuring TC for VSI seid=%d",
10464                                         vsi_list->vsi->seid);
10465                         /* continue */
10466                 }
10467         }
10468         return I40E_SUCCESS;
10469 }
10470
10471 /*
10472  * i40e_dcb_init_configure - initial dcb config
10473  * @dev: device being configured
10474  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10475  *
10476  * Returns 0 on success, negative value on failure
10477  */
10478 int
10479 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10480 {
10481         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10482         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10483         int i, ret = 0;
10484
10485         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10486                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10487                 return -ENOTSUP;
10488         }
10489
10490         /* DCB initialization:
10491          * Update DCB configuration from the Firmware and configure
10492          * LLDP MIB change event.
10493          */
10494         if (sw_dcb == TRUE) {
10495                 ret = i40e_init_dcb(hw);
10496                 /* If lldp agent is stopped, the return value from
10497                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10498                  * adminq status. Otherwise, it should return success.
10499                  */
10500                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10501                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10502                         memset(&hw->local_dcbx_config, 0,
10503                                 sizeof(struct i40e_dcbx_config));
10504                         /* set dcb default configuration */
10505                         hw->local_dcbx_config.etscfg.willing = 0;
10506                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10507                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10508                         hw->local_dcbx_config.etscfg.tsatable[0] =
10509                                                 I40E_IEEE_TSA_ETS;
10510                         /* all UPs mapping to TC0 */
10511                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10512                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10513                         hw->local_dcbx_config.etsrec =
10514                                 hw->local_dcbx_config.etscfg;
10515                         hw->local_dcbx_config.pfc.willing = 0;
10516                         hw->local_dcbx_config.pfc.pfccap =
10517                                                 I40E_MAX_TRAFFIC_CLASS;
10518                         /* FW needs one App to configure HW */
10519                         hw->local_dcbx_config.numapps = 1;
10520                         hw->local_dcbx_config.app[0].selector =
10521                                                 I40E_APP_SEL_ETHTYPE;
10522                         hw->local_dcbx_config.app[0].priority = 3;
10523                         hw->local_dcbx_config.app[0].protocolid =
10524                                                 I40E_APP_PROTOID_FCOE;
10525                         ret = i40e_set_dcb_config(hw);
10526                         if (ret) {
10527                                 PMD_INIT_LOG(ERR,
10528                                         "default dcb config fails. err = %d, aq_err = %d.",
10529                                         ret, hw->aq.asq_last_status);
10530                                 return -ENOSYS;
10531                         }
10532                 } else {
10533                         PMD_INIT_LOG(ERR,
10534                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10535                                 ret, hw->aq.asq_last_status);
10536                         return -ENOTSUP;
10537                 }
10538         } else {
10539                 ret = i40e_aq_start_lldp(hw, NULL);
10540                 if (ret != I40E_SUCCESS)
10541                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10542
10543                 ret = i40e_init_dcb(hw);
10544                 if (!ret) {
10545                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10546                                 PMD_INIT_LOG(ERR,
10547                                         "HW doesn't support DCBX offload.");
10548                                 return -ENOTSUP;
10549                         }
10550                 } else {
10551                         PMD_INIT_LOG(ERR,
10552                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10553                                 ret, hw->aq.asq_last_status);
10554                         return -ENOTSUP;
10555                 }
10556         }
10557         return 0;
10558 }
10559
10560 /*
10561  * i40e_dcb_setup - setup dcb related config
10562  * @dev: device being configured
10563  *
10564  * Returns 0 on success, negative value on failure
10565  */
10566 static int
10567 i40e_dcb_setup(struct rte_eth_dev *dev)
10568 {
10569         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10570         struct i40e_dcbx_config dcb_cfg;
10571         uint8_t tc_map = 0;
10572         int ret = 0;
10573
10574         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10575                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10576                 return -ENOTSUP;
10577         }
10578
10579         if (pf->vf_num != 0)
10580                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10581
10582         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10583         if (ret) {
10584                 PMD_INIT_LOG(ERR, "invalid dcb config");
10585                 return -EINVAL;
10586         }
10587         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10588         if (ret) {
10589                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10590                 return -ENOSYS;
10591         }
10592
10593         return 0;
10594 }
10595
10596 static int
10597 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10598                       struct rte_eth_dcb_info *dcb_info)
10599 {
10600         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10601         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10602         struct i40e_vsi *vsi = pf->main_vsi;
10603         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10604         uint16_t bsf, tc_mapping;
10605         int i, j = 0;
10606
10607         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10608                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10609         else
10610                 dcb_info->nb_tcs = 1;
10611         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10612                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10613         for (i = 0; i < dcb_info->nb_tcs; i++)
10614                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10615
10616         /* get queue mapping if vmdq is disabled */
10617         if (!pf->nb_cfg_vmdq_vsi) {
10618                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10619                         if (!(vsi->enabled_tc & (1 << i)))
10620                                 continue;
10621                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10622                         dcb_info->tc_queue.tc_rxq[j][i].base =
10623                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10624                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10625                         dcb_info->tc_queue.tc_txq[j][i].base =
10626                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10627                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10628                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10629                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10630                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10631                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10632                 }
10633                 return 0;
10634         }
10635
10636         /* get queue mapping if vmdq is enabled */
10637         do {
10638                 vsi = pf->vmdq[j].vsi;
10639                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10640                         if (!(vsi->enabled_tc & (1 << i)))
10641                                 continue;
10642                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10643                         dcb_info->tc_queue.tc_rxq[j][i].base =
10644                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10645                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10646                         dcb_info->tc_queue.tc_txq[j][i].base =
10647                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10648                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10649                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10650                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10651                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10652                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10653                 }
10654                 j++;
10655         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10656         return 0;
10657 }
10658
10659 static int
10660 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10661 {
10662         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10663         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10664         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10665         uint16_t interval =
10666                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
10667         uint16_t msix_intr;
10668
10669         msix_intr = intr_handle->intr_vec[queue_id];
10670         if (msix_intr == I40E_MISC_VEC_ID)
10671                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10672                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10673                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10674                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10675                                (interval <<
10676                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10677         else
10678                 I40E_WRITE_REG(hw,
10679                                I40E_PFINT_DYN_CTLN(msix_intr -
10680                                                    I40E_RX_VEC_START),
10681                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10682                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10683                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10684                                (interval <<
10685                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10686
10687         I40E_WRITE_FLUSH(hw);
10688         rte_intr_enable(&pci_dev->intr_handle);
10689
10690         return 0;
10691 }
10692
10693 static int
10694 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10695 {
10696         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10697         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10698         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10699         uint16_t msix_intr;
10700
10701         msix_intr = intr_handle->intr_vec[queue_id];
10702         if (msix_intr == I40E_MISC_VEC_ID)
10703                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10704         else
10705                 I40E_WRITE_REG(hw,
10706                                I40E_PFINT_DYN_CTLN(msix_intr -
10707                                                    I40E_RX_VEC_START),
10708                                0);
10709         I40E_WRITE_FLUSH(hw);
10710
10711         return 0;
10712 }
10713
10714 static int i40e_get_regs(struct rte_eth_dev *dev,
10715                          struct rte_dev_reg_info *regs)
10716 {
10717         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10718         uint32_t *ptr_data = regs->data;
10719         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10720         const struct i40e_reg_info *reg_info;
10721
10722         if (ptr_data == NULL) {
10723                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10724                 regs->width = sizeof(uint32_t);
10725                 return 0;
10726         }
10727
10728         /* The first few registers have to be read using AQ operations */
10729         reg_idx = 0;
10730         while (i40e_regs_adminq[reg_idx].name) {
10731                 reg_info = &i40e_regs_adminq[reg_idx++];
10732                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10733                         for (arr_idx2 = 0;
10734                                         arr_idx2 <= reg_info->count2;
10735                                         arr_idx2++) {
10736                                 reg_offset = arr_idx * reg_info->stride1 +
10737                                         arr_idx2 * reg_info->stride2;
10738                                 reg_offset += reg_info->base_addr;
10739                                 ptr_data[reg_offset >> 2] =
10740                                         i40e_read_rx_ctl(hw, reg_offset);
10741                         }
10742         }
10743
10744         /* The remaining registers can be read using primitives */
10745         reg_idx = 0;
10746         while (i40e_regs_others[reg_idx].name) {
10747                 reg_info = &i40e_regs_others[reg_idx++];
10748                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10749                         for (arr_idx2 = 0;
10750                                         arr_idx2 <= reg_info->count2;
10751                                         arr_idx2++) {
10752                                 reg_offset = arr_idx * reg_info->stride1 +
10753                                         arr_idx2 * reg_info->stride2;
10754                                 reg_offset += reg_info->base_addr;
10755                                 ptr_data[reg_offset >> 2] =
10756                                         I40E_READ_REG(hw, reg_offset);
10757                         }
10758         }
10759
10760         return 0;
10761 }
10762
10763 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10764 {
10765         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10766
10767         /* Convert word count to byte count */
10768         return hw->nvm.sr_size << 1;
10769 }
10770
10771 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10772                            struct rte_dev_eeprom_info *eeprom)
10773 {
10774         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10775         uint16_t *data = eeprom->data;
10776         uint16_t offset, length, cnt_words;
10777         int ret_code;
10778
10779         offset = eeprom->offset >> 1;
10780         length = eeprom->length >> 1;
10781         cnt_words = length;
10782
10783         if (offset > hw->nvm.sr_size ||
10784                 offset + length > hw->nvm.sr_size) {
10785                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10786                 return -EINVAL;
10787         }
10788
10789         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10790
10791         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10792         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10793                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10794                 return -EIO;
10795         }
10796
10797         return 0;
10798 }
10799
10800 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10801                                       struct ether_addr *mac_addr)
10802 {
10803         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10804
10805         if (!is_valid_assigned_ether_addr(mac_addr)) {
10806                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10807                 return;
10808         }
10809
10810         /* Flags: 0x3 updates port address */
10811         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10812 }
10813
10814 static int
10815 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10816 {
10817         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10818         struct rte_eth_dev_data *dev_data = pf->dev_data;
10819         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10820         int ret = 0;
10821
10822         /* check if mtu is within the allowed range */
10823         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10824                 return -EINVAL;
10825
10826         /* mtu setting is forbidden if port is start */
10827         if (dev_data->dev_started) {
10828                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10829                             dev_data->port_id);
10830                 return -EBUSY;
10831         }
10832
10833         if (frame_size > ETHER_MAX_LEN)
10834                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10835         else
10836                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10837
10838         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10839
10840         return ret;
10841 }
10842
10843 /* Restore ethertype filter */
10844 static void
10845 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10846 {
10847         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10848         struct i40e_ethertype_filter_list
10849                 *ethertype_list = &pf->ethertype.ethertype_list;
10850         struct i40e_ethertype_filter *f;
10851         struct i40e_control_filter_stats stats;
10852         uint16_t flags;
10853
10854         TAILQ_FOREACH(f, ethertype_list, rules) {
10855                 flags = 0;
10856                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10857                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10858                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10859                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10860                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10861
10862                 memset(&stats, 0, sizeof(stats));
10863                 i40e_aq_add_rem_control_packet_filter(hw,
10864                                             f->input.mac_addr.addr_bytes,
10865                                             f->input.ether_type,
10866                                             flags, pf->main_vsi->seid,
10867                                             f->queue, 1, &stats, NULL);
10868         }
10869         PMD_DRV_LOG(INFO, "Ethertype filter:"
10870                     " mac_etype_used = %u, etype_used = %u,"
10871                     " mac_etype_free = %u, etype_free = %u",
10872                     stats.mac_etype_used, stats.etype_used,
10873                     stats.mac_etype_free, stats.etype_free);
10874 }
10875
10876 /* Restore tunnel filter */
10877 static void
10878 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10879 {
10880         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10881         struct i40e_vsi *vsi;
10882         struct i40e_pf_vf *vf;
10883         struct i40e_tunnel_filter_list
10884                 *tunnel_list = &pf->tunnel.tunnel_list;
10885         struct i40e_tunnel_filter *f;
10886         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10887         bool big_buffer = 0;
10888
10889         TAILQ_FOREACH(f, tunnel_list, rules) {
10890                 if (!f->is_to_vf)
10891                         vsi = pf->main_vsi;
10892                 else {
10893                         vf = &pf->vfs[f->vf_id];
10894                         vsi = vf->vsi;
10895                 }
10896                 memset(&cld_filter, 0, sizeof(cld_filter));
10897                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10898                         (struct ether_addr *)&cld_filter.element.outer_mac);
10899                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10900                         (struct ether_addr *)&cld_filter.element.inner_mac);
10901                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10902                 cld_filter.element.flags = f->input.flags;
10903                 cld_filter.element.tenant_id = f->input.tenant_id;
10904                 cld_filter.element.queue_number = f->queue;
10905                 rte_memcpy(cld_filter.general_fields,
10906                            f->input.general_fields,
10907                            sizeof(f->input.general_fields));
10908
10909                 if (((f->input.flags &
10910                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
10911                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
10912                     ((f->input.flags &
10913                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
10914                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
10915                     ((f->input.flags &
10916                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
10917                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
10918                         big_buffer = 1;
10919
10920                 if (big_buffer)
10921                         i40e_aq_add_cloud_filters_big_buffer(hw,
10922                                              vsi->seid, &cld_filter, 1);
10923                 else
10924                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10925                                                   &cld_filter.element, 1);
10926         }
10927 }
10928
10929 static void
10930 i40e_filter_restore(struct i40e_pf *pf)
10931 {
10932         i40e_ethertype_filter_restore(pf);
10933         i40e_tunnel_filter_restore(pf);
10934         i40e_fdir_filter_restore(pf);
10935 }
10936
10937 static bool
10938 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10939 {
10940         if (strcmp(dev->device->driver->name, drv->driver.name))
10941                 return false;
10942
10943         return true;
10944 }
10945
10946 bool
10947 is_i40e_supported(struct rte_eth_dev *dev)
10948 {
10949         return is_device_supported(dev, &rte_i40e_pmd);
10950 }
10951
10952 struct i40e_customized_pctype*
10953 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
10954 {
10955         int i;
10956
10957         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
10958                 if (pf->customized_pctype[i].index == index)
10959                         return &pf->customized_pctype[i];
10960         }
10961         return NULL;
10962 }
10963
10964 static int
10965 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
10966                               uint32_t pkg_size, uint32_t proto_num,
10967                               struct rte_pmd_i40e_proto_info *proto)
10968 {
10969         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10970         uint32_t pctype_num;
10971         struct rte_pmd_i40e_ptype_info *pctype;
10972         uint32_t buff_size;
10973         struct i40e_customized_pctype *new_pctype = NULL;
10974         uint8_t proto_id;
10975         uint8_t pctype_value;
10976         char name[64];
10977         uint32_t i, j, n;
10978         int ret;
10979
10980         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10981                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
10982                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
10983         if (ret) {
10984                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
10985                 return -1;
10986         }
10987         if (!pctype_num) {
10988                 PMD_DRV_LOG(INFO, "No new pctype added");
10989                 return -1;
10990         }
10991
10992         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
10993         pctype = rte_zmalloc("new_pctype", buff_size, 0);
10994         if (!pctype) {
10995                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
10996                 return -1;
10997         }
10998         /* get information about new pctype list */
10999         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11000                                         (uint8_t *)pctype, buff_size,
11001                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11002         if (ret) {
11003                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11004                 rte_free(pctype);
11005                 return -1;
11006         }
11007
11008         /* Update customized pctype. */
11009         for (i = 0; i < pctype_num; i++) {
11010                 pctype_value = pctype[i].ptype_id;
11011                 memset(name, 0, sizeof(name));
11012                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11013                         proto_id = pctype[i].protocols[j];
11014                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11015                                 continue;
11016                         for (n = 0; n < proto_num; n++) {
11017                                 if (proto[n].proto_id != proto_id)
11018                                         continue;
11019                                 strcat(name, proto[n].name);
11020                                 strcat(name, "_");
11021                                 break;
11022                         }
11023                 }
11024                 name[strlen(name) - 1] = '\0';
11025                 if (!strcmp(name, "GTPC"))
11026                         new_pctype =
11027                                 i40e_find_customized_pctype(pf,
11028                                                       I40E_CUSTOMIZED_GTPC);
11029                 else if (!strcmp(name, "GTPU_IPV4"))
11030                         new_pctype =
11031                                 i40e_find_customized_pctype(pf,
11032                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11033                 else if (!strcmp(name, "GTPU_IPV6"))
11034                         new_pctype =
11035                                 i40e_find_customized_pctype(pf,
11036                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11037                 else if (!strcmp(name, "GTPU"))
11038                         new_pctype =
11039                                 i40e_find_customized_pctype(pf,
11040                                                       I40E_CUSTOMIZED_GTPU);
11041                 if (new_pctype) {
11042                         new_pctype->pctype = pctype_value;
11043                         new_pctype->valid = true;
11044                 }
11045         }
11046
11047         rte_free(pctype);
11048         return 0;
11049 }
11050
11051 static int
11052 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11053                                uint32_t pkg_size, uint32_t proto_num,
11054                                struct rte_pmd_i40e_proto_info *proto)
11055 {
11056         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11057         uint16_t port_id = dev->data->port_id;
11058         uint32_t ptype_num;
11059         struct rte_pmd_i40e_ptype_info *ptype;
11060         uint32_t buff_size;
11061         uint8_t proto_id;
11062         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11063         uint32_t i, j, n;
11064         bool in_tunnel;
11065         int ret;
11066
11067         /* get information about new ptype num */
11068         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11069                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11070                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11071         if (ret) {
11072                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11073                 return ret;
11074         }
11075         if (!ptype_num) {
11076                 PMD_DRV_LOG(INFO, "No new ptype added");
11077                 return -1;
11078         }
11079
11080         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11081         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11082         if (!ptype) {
11083                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11084                 return -1;
11085         }
11086
11087         /* get information about new ptype list */
11088         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11089                                         (uint8_t *)ptype, buff_size,
11090                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11091         if (ret) {
11092                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11093                 rte_free(ptype);
11094                 return ret;
11095         }
11096
11097         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11098         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11099         if (!ptype_mapping) {
11100                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11101                 rte_free(ptype);
11102                 return -1;
11103         }
11104
11105         /* Update ptype mapping table. */
11106         for (i = 0; i < ptype_num; i++) {
11107                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11108                 ptype_mapping[i].sw_ptype = 0;
11109                 in_tunnel = false;
11110                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11111                         proto_id = ptype[i].protocols[j];
11112                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11113                                 continue;
11114                         for (n = 0; n < proto_num; n++) {
11115                                 if (proto[n].proto_id != proto_id)
11116                                         continue;
11117                                 memset(name, 0, sizeof(name));
11118                                 strcpy(name, proto[n].name);
11119                                 if (!strncmp(name, "PPPOE", 5))
11120                                         ptype_mapping[i].sw_ptype |=
11121                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11122                                 else if (!strncmp(name, "OIPV4", 5)) {
11123                                         ptype_mapping[i].sw_ptype |=
11124                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11125                                         in_tunnel = true;
11126                                 } else if (!strncmp(name, "IPV4", 4) &&
11127                                            !in_tunnel)
11128                                         ptype_mapping[i].sw_ptype |=
11129                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11130                                 else if (!strncmp(name, "IPV4FRAG", 8) &&
11131                                          in_tunnel) {
11132                                         ptype_mapping[i].sw_ptype |=
11133                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11134                                         ptype_mapping[i].sw_ptype |=
11135                                                 RTE_PTYPE_INNER_L4_FRAG;
11136                                 } else if (!strncmp(name, "IPV4", 4) &&
11137                                            in_tunnel)
11138                                         ptype_mapping[i].sw_ptype |=
11139                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11140                                 else if (!strncmp(name, "OIPV6", 5)) {
11141                                         ptype_mapping[i].sw_ptype |=
11142                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11143                                         in_tunnel = true;
11144                                 } else if (!strncmp(name, "IPV6", 4) &&
11145                                            !in_tunnel)
11146                                         ptype_mapping[i].sw_ptype |=
11147                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11148                                 else if (!strncmp(name, "IPV6FRAG", 8) &&
11149                                          in_tunnel) {
11150                                         ptype_mapping[i].sw_ptype |=
11151                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11152                                         ptype_mapping[i].sw_ptype |=
11153                                                 RTE_PTYPE_INNER_L4_FRAG;
11154                                 } else if (!strncmp(name, "IPV6", 4) &&
11155                                            in_tunnel)
11156                                         ptype_mapping[i].sw_ptype |=
11157                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11158                                 else if (!strncmp(name, "UDP", 3) && !in_tunnel)
11159                                         ptype_mapping[i].sw_ptype |=
11160                                                 RTE_PTYPE_L4_UDP;
11161                                 else if (!strncmp(name, "UDP", 3) && in_tunnel)
11162                                         ptype_mapping[i].sw_ptype |=
11163                                                 RTE_PTYPE_INNER_L4_UDP;
11164                                 else if (!strncmp(name, "TCP", 3) && !in_tunnel)
11165                                         ptype_mapping[i].sw_ptype |=
11166                                                 RTE_PTYPE_L4_TCP;
11167                                 else if (!strncmp(name, "TCP", 3) && in_tunnel)
11168                                         ptype_mapping[i].sw_ptype |=
11169                                                 RTE_PTYPE_INNER_L4_TCP;
11170                                 else if (!strncmp(name, "SCTP", 4) &&
11171                                          !in_tunnel)
11172                                         ptype_mapping[i].sw_ptype |=
11173                                                 RTE_PTYPE_L4_SCTP;
11174                                 else if (!strncmp(name, "SCTP", 4) && in_tunnel)
11175                                         ptype_mapping[i].sw_ptype |=
11176                                                 RTE_PTYPE_INNER_L4_SCTP;
11177                                 else if ((!strncmp(name, "ICMP", 4) ||
11178                                           !strncmp(name, "ICMPV6", 6)) &&
11179                                          !in_tunnel)
11180                                         ptype_mapping[i].sw_ptype |=
11181                                                 RTE_PTYPE_L4_ICMP;
11182                                 else if ((!strncmp(name, "ICMP", 4) ||
11183                                           !strncmp(name, "ICMPV6", 6)) &&
11184                                          in_tunnel)
11185                                         ptype_mapping[i].sw_ptype |=
11186                                                 RTE_PTYPE_INNER_L4_ICMP;
11187                                 else if (!strncmp(name, "GTPC", 4)) {
11188                                         ptype_mapping[i].sw_ptype |=
11189                                                 RTE_PTYPE_TUNNEL_GTPC;
11190                                         in_tunnel = true;
11191                                 } else if (!strncmp(name, "GTPU", 4)) {
11192                                         ptype_mapping[i].sw_ptype |=
11193                                                 RTE_PTYPE_TUNNEL_GTPU;
11194                                         in_tunnel = true;
11195                                 } else if (!strncmp(name, "GRENAT", 6)) {
11196                                         ptype_mapping[i].sw_ptype |=
11197                                                 RTE_PTYPE_TUNNEL_GRENAT;
11198                                         in_tunnel = true;
11199                                 } else if (!strncmp(name, "L2TPv2CTL", 9)) {
11200                                         ptype_mapping[i].sw_ptype |=
11201                                                 RTE_PTYPE_TUNNEL_L2TP;
11202                                         in_tunnel = true;
11203                                 }
11204
11205                                 break;
11206                         }
11207                 }
11208         }
11209
11210         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11211                                                 ptype_num, 0);
11212         if (ret)
11213                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11214
11215         rte_free(ptype_mapping);
11216         rte_free(ptype);
11217         return ret;
11218 }
11219
11220 void
11221 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11222                               uint32_t pkg_size)
11223 {
11224         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11225         uint32_t proto_num;
11226         struct rte_pmd_i40e_proto_info *proto;
11227         uint32_t buff_size;
11228         uint32_t i;
11229         int ret;
11230
11231         /* get information about protocol number */
11232         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11233                                        (uint8_t *)&proto_num, sizeof(proto_num),
11234                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11235         if (ret) {
11236                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11237                 return;
11238         }
11239         if (!proto_num) {
11240                 PMD_DRV_LOG(INFO, "No new protocol added");
11241                 return;
11242         }
11243
11244         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11245         proto = rte_zmalloc("new_proto", buff_size, 0);
11246         if (!proto) {
11247                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11248                 return;
11249         }
11250
11251         /* get information about protocol list */
11252         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11253                                         (uint8_t *)proto, buff_size,
11254                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11255         if (ret) {
11256                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11257                 rte_free(proto);
11258                 return;
11259         }
11260
11261         /* Check if GTP is supported. */
11262         for (i = 0; i < proto_num; i++) {
11263                 if (!strncmp(proto[i].name, "GTP", 3)) {
11264                         pf->gtp_support = true;
11265                         break;
11266                 }
11267         }
11268
11269         /* Update customized pctype info */
11270         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11271                                             proto_num, proto);
11272         if (ret)
11273                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11274
11275         /* Update customized ptype info */
11276         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11277                                            proto_num, proto);
11278         if (ret)
11279                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11280
11281         rte_free(proto);
11282 }
11283
11284 /* Create a QinQ cloud filter
11285  *
11286  * The Fortville NIC has limited resources for tunnel filters,
11287  * so we can only reuse existing filters.
11288  *
11289  * In step 1 we define which Field Vector fields can be used for
11290  * filter types.
11291  * As we do not have the inner tag defined as a field,
11292  * we have to define it first, by reusing one of L1 entries.
11293  *
11294  * In step 2 we are replacing one of existing filter types with
11295  * a new one for QinQ.
11296  * As we reusing L1 and replacing L2, some of the default filter
11297  * types will disappear,which depends on L1 and L2 entries we reuse.
11298  *
11299  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11300  *
11301  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11302  *              later when we define the cloud filter.
11303  *      a.      Valid_flags.replace_cloud = 0
11304  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11305  *      c.      New_filter = 0x10
11306  *      d.      TR bit = 0xff (optional, not used here)
11307  *      e.      Buffer – 2 entries:
11308  *              i.      Byte 0 = 8 (outer vlan FV index).
11309  *                      Byte 1 = 0 (rsv)
11310  *                      Byte 2-3 = 0x0fff
11311  *              ii.     Byte 0 = 37 (inner vlan FV index).
11312  *                      Byte 1 =0 (rsv)
11313  *                      Byte 2-3 = 0x0fff
11314  *
11315  * Step 2:
11316  * 2.   Create cloud filter using two L1 filters entries: stag and
11317  *              new filter(outer vlan+ inner vlan)
11318  *      a.      Valid_flags.replace_cloud = 1
11319  *      b.      Old_filter = 1 (instead of outer IP)
11320  *      c.      New_filter = 0x10
11321  *      d.      Buffer – 2 entries:
11322  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11323  *                      Byte 1-3 = 0 (rsv)
11324  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11325  *                      Byte 9-11 = 0 (rsv)
11326  */
11327 static int
11328 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11329 {
11330         int ret = -ENOTSUP;
11331         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11332         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11333         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11334
11335         /* Init */
11336         memset(&filter_replace, 0,
11337                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11338         memset(&filter_replace_buf, 0,
11339                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11340
11341         /* create L1 filter */
11342         filter_replace.old_filter_type =
11343                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11344         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11345         filter_replace.tr_bit = 0;
11346
11347         /* Prepare the buffer, 2 entries */
11348         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11349         filter_replace_buf.data[0] |=
11350                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11351         /* Field Vector 12b mask */
11352         filter_replace_buf.data[2] = 0xff;
11353         filter_replace_buf.data[3] = 0x0f;
11354         filter_replace_buf.data[4] =
11355                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11356         filter_replace_buf.data[4] |=
11357                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11358         /* Field Vector 12b mask */
11359         filter_replace_buf.data[6] = 0xff;
11360         filter_replace_buf.data[7] = 0x0f;
11361         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11362                         &filter_replace_buf);
11363         if (ret != I40E_SUCCESS)
11364                 return ret;
11365
11366         /* Apply the second L2 cloud filter */
11367         memset(&filter_replace, 0,
11368                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11369         memset(&filter_replace_buf, 0,
11370                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11371
11372         /* create L2 filter, input for L2 filter will be L1 filter  */
11373         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11374         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11375         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11376
11377         /* Prepare the buffer, 2 entries */
11378         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11379         filter_replace_buf.data[0] |=
11380                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11381         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11382         filter_replace_buf.data[4] |=
11383                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11384         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11385                         &filter_replace_buf);
11386         return ret;
11387 }
11388
11389 RTE_INIT(i40e_init_log);
11390 static void
11391 i40e_init_log(void)
11392 {
11393         i40e_logtype_init = rte_log_register("pmd.i40e.init");
11394         if (i40e_logtype_init >= 0)
11395                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11396         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11397         if (i40e_logtype_driver >= 0)
11398                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11399 }