drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_eth_ctrl.h>
  28 #include <rte_tailq.h>
  29 #include <rte_hash_crc.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45
  46 #define I40E_CLEAR_PXE_WAIT_MS     200
  47
  48 /* Maximun number of capability elements */
  49 #define I40E_MAX_CAP_ELE_NUM       128
  50
  51 /* Wait count and interval */
  52 #define I40E_CHK_Q_ENA_COUNT       1000
  53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  54
  55 /* Maximun number of VSI */
  56 #define I40E_MAX_NUM_VSIS          (384UL)
  57
  58 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  59
  60 /* Flow control default timer */
  61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  62
  63 /* Flow control enable fwd bit */
  64 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  65
  66 /* Receive Packet Buffer size */
  67 #define I40E_RXPBSIZE (968 * 1024)
  68
  69 /* Kilobytes shift */
  70 #define I40E_KILOSHIFT 10
  71
  72 /* Flow control default high water */
  73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  74
  75 /* Flow control default low water */
  76 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Receive Average Packet Size in Byte*/
  79 #define I40E_PACKET_AVERAGE_SIZE 128
  80
  81 /* Mask of PF interrupt causes */
  82 #define I40E_PFINT_ICR0_ENA_MASK ( \
  83                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  84                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  85                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  86                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  87                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  92
  93 #define I40E_FLOW_TYPES ( \
  94         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  99         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 104         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 105
 106 /* Additional timesync values. */
 107 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 108 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 109 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 110 #define I40E_PRTTSYN_TSYNENA     0x80000000
 111 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 112 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 113
 114 /**
 115  * Below are values for writing un-exposed registers suggested
 116  * by silicon experts
 117  */
 118 /* Destination MAC address */
 119 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 120 /* Source MAC address */
 121 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 123 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 125 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 126 /* Single VLAN tag in the inner L2 header */
 127 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 128 /* Source IPv4 address */
 129 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 130 /* Destination IPv4 address */
 131 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 132 /* Source IPv4 address for X722 */
 133 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 134 /* Destination IPv4 address for X722 */
 135 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 136 /* IPv4 Protocol for X722 */
 137 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 138 /* IPv4 Time to Live for X722 */
 139 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 140 /* IPv4 Type of Service (TOS) */
 141 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 142 /* IPv4 Protocol */
 143 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 144 /* IPv4 Time to Live */
 145 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 146 /* Source IPv6 address */
 147 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 148 /* Destination IPv6 address */
 149 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 150 /* IPv6 Traffic Class (TC) */
 151 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 152 /* IPv6 Next Header */
 153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 154 /* IPv6 Hop Limit */
 155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 156 /* Source L4 port */
 157 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 158 /* Destination L4 port */
 159 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 160 /* SCTP verification tag */
 161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 164 /* Source port of tunneling UDP */
 165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 166 /* Destination port of tunneling UDP */
 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 168 /* UDP Tunneling ID, NVGRE/GRE key */
 169 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 170 /* Last ether type */
 171 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 172 /* Tunneling outer destination IPv4 address */
 173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 174 /* Tunneling outer destination IPv6 address */
 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 176 /* 1st word of flex payload */
 177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 178 /* 2nd word of flex payload */
 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 180 /* 3rd word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 182 /* 4th word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 184 /* 5th word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 186 /* 6th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 188 /* 7th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 190 /* 8th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 192 /* all 8 words flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 194 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 195
 196 #define I40E_TRANSLATE_INSET 0
 197 #define I40E_TRANSLATE_REG   1
 198
 199 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 200 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 201 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 202 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 204 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 205
 206 /* PCI offset for querying capability */
 207 #define PCI_DEV_CAP_REG            0xA4
 208 /* PCI offset for enabling/disabling Extended Tag */
 209 #define PCI_DEV_CTRL_REG           0xA8
 210 /* Bit mask of Extended Tag capability */
 211 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 212 /* Bit shift of Extended Tag enable/disable */
 213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 214 /* Bit mask of Extended Tag enable/disable */
 215 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 216
 217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 219 static int i40e_dev_configure(struct rte_eth_dev *dev);
 220 static int i40e_dev_start(struct rte_eth_dev *dev);
 221 static void i40e_dev_stop(struct rte_eth_dev *dev);
 222 static void i40e_dev_close(struct rte_eth_dev *dev);
 223 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_stats *stats);
 232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 233                                struct rte_eth_xstat *xstats, unsigned n);
 234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 235                                      struct rte_eth_xstat_name *xstats_names,
 236                                      unsigned limit);
 237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 239                                             uint16_t queue_id,
 240                                             uint8_t stat_idx,
 241                                             uint8_t is_rx);
 242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 243                                 char *fw_version, size_t fw_size);
 244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 245                               struct rte_eth_dev_info *dev_info);
 246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 247                                 uint16_t vlan_id,
 248                                 int on);
 249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 250                               enum rte_vlan_type vlan_type,
 251                               uint16_t tpid);
 252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                                       uint16_t queue,
 255                                       int on);
 256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 260                               struct rte_eth_fc_conf *fc_conf);
 261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 264                                        struct rte_eth_pfc_conf *pfc_conf);
 265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 266                             struct ether_addr *mac_addr,
 267                             uint32_t index,
 268                             uint32_t pool);
 269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 271                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 272                                     uint16_t reta_size);
 273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 274                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 275                                    uint16_t reta_size);
 276
 277 static int i40e_get_cap(struct i40e_hw *hw);
 278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 279 static int i40e_pf_setup(struct i40e_pf *pf);
 280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 284                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 285 static void i40e_stat_update_48(struct i40e_hw *hw,
 286                                uint32_t hireg,
 287                                uint32_t loreg,
 288                                bool offset_loaded,
 289                                uint64_t *offset,
 290                                uint64_t *stat);
 291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 292 static void i40e_dev_interrupt_handler(void *param);
 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 294                                 uint32_t base, uint32_t num);
 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 297                         uint32_t base);
 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 299                         uint16_t num);
 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 301 static int i40e_veb_release(struct i40e_veb *veb);
 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 303                                                 struct i40e_vsi *vsi);
 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static int i40e_get_module_info(struct rte_eth_dev *dev,
 374                                 struct rte_eth_dev_module_info *modinfo);
 375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 376                                   struct rte_dev_eeprom_info *info);
 377
 378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 379                                       struct ether_addr *mac_addr);
 380
 381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 382
 383 static int i40e_ethertype_filter_convert(
 384         const struct rte_eth_ethertype_filter *input,
 385         struct i40e_ethertype_filter *filter);
 386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 387                                    struct i40e_ethertype_filter *filter);
 388
 389 static int i40e_tunnel_filter_convert(
 390         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 391         struct i40e_tunnel_filter *tunnel_filter);
 392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 393                                 struct i40e_tunnel_filter *tunnel_filter);
 394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 395
 396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 398 static void i40e_filter_restore(struct i40e_pf *pf);
 399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 400
 401 int i40e_logtype_init;
 402 int i40e_logtype_driver;
 403
 404 static const struct rte_pci_id pci_id_i40e_map[] = {
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 425         { .vendor_id = 0, /* sentinel */ },
 426 };
 427
 428 static const struct eth_dev_ops i40e_eth_dev_ops = {
 429         .dev_configure                = i40e_dev_configure,
 430         .dev_start                    = i40e_dev_start,
 431         .dev_stop                     = i40e_dev_stop,
 432         .dev_close                    = i40e_dev_close,
 433         .dev_reset                    = i40e_dev_reset,
 434         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 435         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 436         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 437         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 438         .dev_set_link_up              = i40e_dev_set_link_up,
 439         .dev_set_link_down            = i40e_dev_set_link_down,
 440         .link_update                  = i40e_dev_link_update,
 441         .stats_get                    = i40e_dev_stats_get,
 442         .xstats_get                   = i40e_dev_xstats_get,
 443         .xstats_get_names             = i40e_dev_xstats_get_names,
 444         .stats_reset                  = i40e_dev_stats_reset,
 445         .xstats_reset                 = i40e_dev_stats_reset,
 446         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 447         .fw_version_get               = i40e_fw_version_get,
 448         .dev_infos_get                = i40e_dev_info_get,
 449         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 450         .vlan_filter_set              = i40e_vlan_filter_set,
 451         .vlan_tpid_set                = i40e_vlan_tpid_set,
 452         .vlan_offload_set             = i40e_vlan_offload_set,
 453         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 454         .vlan_pvid_set                = i40e_vlan_pvid_set,
 455         .rx_queue_start               = i40e_dev_rx_queue_start,
 456         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 457         .tx_queue_start               = i40e_dev_tx_queue_start,
 458         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 459         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 460         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 461         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 462         .rx_queue_release             = i40e_dev_rx_queue_release,
 463         .rx_queue_count               = i40e_dev_rx_queue_count,
 464         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 465         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 466         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 467         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 468         .tx_queue_release             = i40e_dev_tx_queue_release,
 469         .dev_led_on                   = i40e_dev_led_on,
 470         .dev_led_off                  = i40e_dev_led_off,
 471         .flow_ctrl_get                = i40e_flow_ctrl_get,
 472         .flow_ctrl_set                = i40e_flow_ctrl_set,
 473         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 474         .mac_addr_add                 = i40e_macaddr_add,
 475         .mac_addr_remove              = i40e_macaddr_remove,
 476         .reta_update                  = i40e_dev_rss_reta_update,
 477         .reta_query                   = i40e_dev_rss_reta_query,
 478         .rss_hash_update              = i40e_dev_rss_hash_update,
 479         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 480         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 481         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 482         .filter_ctrl                  = i40e_dev_filter_ctrl,
 483         .rxq_info_get                 = i40e_rxq_info_get,
 484         .txq_info_get                 = i40e_txq_info_get,
 485         .mirror_rule_set              = i40e_mirror_rule_set,
 486         .mirror_rule_reset            = i40e_mirror_rule_reset,
 487         .timesync_enable              = i40e_timesync_enable,
 488         .timesync_disable             = i40e_timesync_disable,
 489         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 490         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 491         .get_dcb_info                 = i40e_dev_get_dcb_info,
 492         .timesync_adjust_time         = i40e_timesync_adjust_time,
 493         .timesync_read_time           = i40e_timesync_read_time,
 494         .timesync_write_time          = i40e_timesync_write_time,
 495         .get_reg                      = i40e_get_regs,
 496         .get_eeprom_length            = i40e_get_eeprom_length,
 497         .get_eeprom                   = i40e_get_eeprom,
 498         .get_module_info              = i40e_get_module_info,
 499         .get_module_eeprom            = i40e_get_module_eeprom,
 500         .mac_addr_set                 = i40e_set_default_mac_addr,
 501         .mtu_set                      = i40e_dev_mtu_set,
 502         .tm_ops_get                   = i40e_tm_ops_get,
 503 };
 504
 505 /* store statistics names and its offset in stats structure */
 506 struct rte_i40e_xstats_name_off {
 507         char name[RTE_ETH_XSTATS_NAME_SIZE];
 508         unsigned offset;
 509 };
 510
 511 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 512         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 513         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 514         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 515         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 516         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 517                 rx_unknown_protocol)},
 518         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 519         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 520         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 521         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 522 };
 523
 524 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 525                 sizeof(rte_i40e_stats_strings[0]))
 526
 527 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 528         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 529                 tx_dropped_link_down)},
 530         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 531         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 532                 illegal_bytes)},
 533         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 534         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 535                 mac_local_faults)},
 536         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 537                 mac_remote_faults)},
 538         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 539                 rx_length_errors)},
 540         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 541         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 542         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 543         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 544         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 545         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 546                 rx_size_127)},
 547         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 548                 rx_size_255)},
 549         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 550                 rx_size_511)},
 551         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 552                 rx_size_1023)},
 553         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 554                 rx_size_1522)},
 555         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 556                 rx_size_big)},
 557         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 558                 rx_undersize)},
 559         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 560                 rx_oversize)},
 561         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 562                 mac_short_packet_dropped)},
 563         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 564                 rx_fragments)},
 565         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 566         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 567         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 568                 tx_size_127)},
 569         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 570                 tx_size_255)},
 571         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 572                 tx_size_511)},
 573         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 574                 tx_size_1023)},
 575         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 576                 tx_size_1522)},
 577         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 578                 tx_size_big)},
 579         {"rx_flow_director_atr_match_packets",
 580                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 581         {"rx_flow_director_sb_match_packets",
 582                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 583         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 584                 tx_lpi_status)},
 585         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 586                 rx_lpi_status)},
 587         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 588                 tx_lpi_count)},
 589         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 590                 rx_lpi_count)},
 591 };
 592
 593 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 594                 sizeof(rte_i40e_hw_port_strings[0]))
 595
 596 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 597         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 598                 priority_xon_rx)},
 599         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 600                 priority_xoff_rx)},
 601 };
 602
 603 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 604                 sizeof(rte_i40e_rxq_prio_strings[0]))
 605
 606 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 607         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 608                 priority_xon_tx)},
 609         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xoff_tx)},
 611         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xon_2_xoff)},
 613 };
 614
 615 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 616                 sizeof(rte_i40e_txq_prio_strings[0]))
 617
 618 static int
 619 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 620         struct rte_pci_device *pci_dev)
 621 {
 622         char name[RTE_ETH_NAME_MAX_LEN];
 623         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 624         int i, retval;
 625
 626         if (pci_dev->device.devargs) {
 627                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 628                                 &eth_da);
 629                 if (retval)
 630                         return retval;
 631         }
 632
 633         /* physical port net_bdf_port */
 634         snprintf(name, sizeof(name), "net_%s", pci_dev->device.name);
 635
 636         retval = rte_eth_dev_create(&pci_dev->device, name,
 637                 sizeof(struct i40e_adapter),
 638                 eth_dev_pci_specific_init, pci_dev,
 639                 eth_i40e_dev_init, NULL);
 640
 641         if (retval || eth_da.nb_representor_ports < 1)
 642                 return retval;
 643
 644         /* probe VF representor ports */
 645         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(name);
 646
 647         if (pf_ethdev == NULL)
 648                 return -ENODEV;
 649
 650         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 651                 struct i40e_vf_representor representor = {
 652                         .vf_id = eth_da.representor_ports[i],
 653                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 654                                 pf_ethdev->data->dev_private)->switch_domain_id,
 655                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 656                                 pf_ethdev->data->dev_private)
 657                 };
 658
 659                 /* representor port net_bdf_port */
 660                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 661                         pci_dev->device.name, eth_da.representor_ports[i]);
 662
 663                 retval = rte_eth_dev_create(&pci_dev->device, name,
 664                         sizeof(struct i40e_vf_representor), NULL, NULL,
 665                         i40e_vf_representor_init, &representor);
 666
 667                 if (retval)
 668                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 669                                 "representor %s.", name);
 670         }
 671
 672         return 0;
 673 }
 674
 675 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 676 {
 677         struct rte_eth_dev *ethdev;
 678
 679         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 680         if (!ethdev)
 681                 return -ENODEV;
 682
 683
 684         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 685                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 686         else
 687                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 688 }
 689
 690 static struct rte_pci_driver rte_i40e_pmd = {
 691         .id_table = pci_id_i40e_map,
 692         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 693                      RTE_PCI_DRV_IOVA_AS_VA,
 694         .probe = eth_i40e_pci_probe,
 695         .remove = eth_i40e_pci_remove,
 696 };
 697
 698 static inline void
 699 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
 700 {
 701         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 702         PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
 703                     "with value 0x%08x",
 704                     reg_addr, reg_val);
 705 }
 706
 707 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 708 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 709 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 710
 711 #ifndef I40E_GLQF_ORT
 712 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 713 #endif
 714 #ifndef I40E_GLQF_PIT
 715 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 716 #endif
 717 #ifndef I40E_GLQF_L3_MAP
 718 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 719 #endif
 720
 721 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 722 {
 723         /*
 724          * Initialize registers for parsing packet type of QinQ
 725          * This should be removed from code once proper
 726          * configuration API is added to avoid configuration conflicts
 727          * between ports of the same device.
 728          */
 729         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 730         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 731         i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
 732 }
 733
 734 static inline void i40e_config_automask(struct i40e_pf *pf)
 735 {
 736         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 737         uint32_t val;
 738
 739         /* INTENA flag is not auto-cleared for interrupt */
 740         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 741         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 742                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 743
 744         /* If support multi-driver, PF will use INT0. */
 745         if (!pf->support_multi_driver)
 746                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 747
 748         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 749 }
 750
 751 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 752
 753 /*
 754  * Add a ethertype filter to drop all flow control frames transmitted
 755  * from VSIs.
 756 */
 757 static void
 758 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 759 {
 760         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 761         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 762                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 763                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 764         int ret;
 765
 766         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 767                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 768                                 pf->main_vsi_seid, 0,
 769                                 TRUE, NULL, NULL);
 770         if (ret)
 771                 PMD_INIT_LOG(ERR,
 772                         "Failed to add filter to drop flow control frames from VSIs.");
 773 }
 774
 775 static int
 776 floating_veb_list_handler(__rte_unused const char *key,
 777                           const char *floating_veb_value,
 778                           void *opaque)
 779 {
 780         int idx = 0;
 781         unsigned int count = 0;
 782         char *end = NULL;
 783         int min, max;
 784         bool *vf_floating_veb = opaque;
 785
 786         while (isblank(*floating_veb_value))
 787                 floating_veb_value++;
 788
 789         /* Reset floating VEB configuration for VFs */
 790         for (idx = 0; idx < I40E_MAX_VF; idx++)
 791                 vf_floating_veb[idx] = false;
 792
 793         min = I40E_MAX_VF;
 794         do {
 795                 while (isblank(*floating_veb_value))
 796                         floating_veb_value++;
 797                 if (*floating_veb_value == '\0')
 798                         return -1;
 799                 errno = 0;
 800                 idx = strtoul(floating_veb_value, &end, 10);
 801                 if (errno || end == NULL)
 802                         return -1;
 803                 while (isblank(*end))
 804                         end++;
 805                 if (*end == '-') {
 806                         min = idx;
 807                 } else if ((*end == ';') || (*end == '\0')) {
 808                         max = idx;
 809                         if (min == I40E_MAX_VF)
 810                                 min = idx;
 811                         if (max >= I40E_MAX_VF)
 812                                 max = I40E_MAX_VF - 1;
 813                         for (idx = min; idx <= max; idx++) {
 814                                 vf_floating_veb[idx] = true;
 815                                 count++;
 816                         }
 817                         min = I40E_MAX_VF;
 818                 } else {
 819                         return -1;
 820                 }
 821                 floating_veb_value = end + 1;
 822         } while (*end != '\0');
 823
 824         if (count == 0)
 825                 return -1;
 826
 827         return 0;
 828 }
 829
 830 static void
 831 config_vf_floating_veb(struct rte_devargs *devargs,
 832                        uint16_t floating_veb,
 833                        bool *vf_floating_veb)
 834 {
 835         struct rte_kvargs *kvlist;
 836         int i;
 837         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 838
 839         if (!floating_veb)
 840                 return;
 841         /* All the VFs attach to the floating VEB by default
 842          * when the floating VEB is enabled.
 843          */
 844         for (i = 0; i < I40E_MAX_VF; i++)
 845                 vf_floating_veb[i] = true;
 846
 847         if (devargs == NULL)
 848                 return;
 849
 850         kvlist = rte_kvargs_parse(devargs->args, NULL);
 851         if (kvlist == NULL)
 852                 return;
 853
 854         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 855                 rte_kvargs_free(kvlist);
 856                 return;
 857         }
 858         /* When the floating_veb_list parameter exists, all the VFs
 859          * will attach to the legacy VEB firstly, then configure VFs
 860          * to the floating VEB according to the floating_veb_list.
 861          */
 862         if (rte_kvargs_process(kvlist, floating_veb_list,
 863                                floating_veb_list_handler,
 864                                vf_floating_veb) < 0) {
 865                 rte_kvargs_free(kvlist);
 866                 return;
 867         }
 868         rte_kvargs_free(kvlist);
 869 }
 870
 871 static int
 872 i40e_check_floating_handler(__rte_unused const char *key,
 873                             const char *value,
 874                             __rte_unused void *opaque)
 875 {
 876         if (strcmp(value, "1"))
 877                 return -1;
 878
 879         return 0;
 880 }
 881
 882 static int
 883 is_floating_veb_supported(struct rte_devargs *devargs)
 884 {
 885         struct rte_kvargs *kvlist;
 886         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 887
 888         if (devargs == NULL)
 889                 return 0;
 890
 891         kvlist = rte_kvargs_parse(devargs->args, NULL);
 892         if (kvlist == NULL)
 893                 return 0;
 894
 895         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 896                 rte_kvargs_free(kvlist);
 897                 return 0;
 898         }
 899         /* Floating VEB is enabled when there's key-value:
 900          * enable_floating_veb=1
 901          */
 902         if (rte_kvargs_process(kvlist, floating_veb_key,
 903                                i40e_check_floating_handler, NULL) < 0) {
 904                 rte_kvargs_free(kvlist);
 905                 return 0;
 906         }
 907         rte_kvargs_free(kvlist);
 908
 909         return 1;
 910 }
 911
 912 static void
 913 config_floating_veb(struct rte_eth_dev *dev)
 914 {
 915         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 916         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 917         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 918
 919         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 920
 921         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 922                 pf->floating_veb =
 923                         is_floating_veb_supported(pci_dev->device.devargs);
 924                 config_vf_floating_veb(pci_dev->device.devargs,
 925                                        pf->floating_veb,
 926                                        pf->floating_veb_list);
 927         } else {
 928                 pf->floating_veb = false;
 929         }
 930 }
 931
 932 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 933 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 934
 935 static int
 936 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 937 {
 938         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 939         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 940         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 941         int ret;
 942
 943         struct rte_hash_parameters ethertype_hash_params = {
 944                 .name = ethertype_hash_name,
 945                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 946                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 947                 .hash_func = rte_hash_crc,
 948                 .hash_func_init_val = 0,
 949                 .socket_id = rte_socket_id(),
 950         };
 951
 952         /* Initialize ethertype filter rule list and hash */
 953         TAILQ_INIT(&ethertype_rule->ethertype_list);
 954         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 955                  "ethertype_%s", dev->device->name);
 956         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 957         if (!ethertype_rule->hash_table) {
 958                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 959                 return -EINVAL;
 960         }
 961         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 962                                        sizeof(struct i40e_ethertype_filter *) *
 963                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 964                                        0);
 965         if (!ethertype_rule->hash_map) {
 966                 PMD_INIT_LOG(ERR,
 967                              "Failed to allocate memory for ethertype hash map!");
 968                 ret = -ENOMEM;
 969                 goto err_ethertype_hash_map_alloc;
 970         }
 971
 972         return 0;
 973
 974 err_ethertype_hash_map_alloc:
 975         rte_hash_free(ethertype_rule->hash_table);
 976
 977         return ret;
 978 }
 979
 980 static int
 981 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 982 {
 983         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 984         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 985         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 986         int ret;
 987
 988         struct rte_hash_parameters tunnel_hash_params = {
 989                 .name = tunnel_hash_name,
 990                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 991                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 992                 .hash_func = rte_hash_crc,
 993                 .hash_func_init_val = 0,
 994                 .socket_id = rte_socket_id(),
 995         };
 996
 997         /* Initialize tunnel filter rule list and hash */
 998         TAILQ_INIT(&tunnel_rule->tunnel_list);
 999         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1000                  "tunnel_%s", dev->device->name);
1001         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1002         if (!tunnel_rule->hash_table) {
1003                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1004                 return -EINVAL;
1005         }
1006         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1007                                     sizeof(struct i40e_tunnel_filter *) *
1008                                     I40E_MAX_TUNNEL_FILTER_NUM,
1009                                     0);
1010         if (!tunnel_rule->hash_map) {
1011                 PMD_INIT_LOG(ERR,
1012                              "Failed to allocate memory for tunnel hash map!");
1013                 ret = -ENOMEM;
1014                 goto err_tunnel_hash_map_alloc;
1015         }
1016
1017         return 0;
1018
1019 err_tunnel_hash_map_alloc:
1020         rte_hash_free(tunnel_rule->hash_table);
1021
1022         return ret;
1023 }
1024
1025 static int
1026 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1027 {
1028         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1029         struct i40e_fdir_info *fdir_info = &pf->fdir;
1030         char fdir_hash_name[RTE_HASH_NAMESIZE];
1031         int ret;
1032
1033         struct rte_hash_parameters fdir_hash_params = {
1034                 .name = fdir_hash_name,
1035                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1036                 .key_len = sizeof(struct i40e_fdir_input),
1037                 .hash_func = rte_hash_crc,
1038                 .hash_func_init_val = 0,
1039                 .socket_id = rte_socket_id(),
1040         };
1041
1042         /* Initialize flow director filter rule list and hash */
1043         TAILQ_INIT(&fdir_info->fdir_list);
1044         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1045                  "fdir_%s", dev->device->name);
1046         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1047         if (!fdir_info->hash_table) {
1048                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1049                 return -EINVAL;
1050         }
1051         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1052                                           sizeof(struct i40e_fdir_filter *) *
1053                                           I40E_MAX_FDIR_FILTER_NUM,
1054                                           0);
1055         if (!fdir_info->hash_map) {
1056                 PMD_INIT_LOG(ERR,
1057                              "Failed to allocate memory for fdir hash map!");
1058                 ret = -ENOMEM;
1059                 goto err_fdir_hash_map_alloc;
1060         }
1061         return 0;
1062
1063 err_fdir_hash_map_alloc:
1064         rte_hash_free(fdir_info->hash_table);
1065
1066         return ret;
1067 }
1068
1069 static void
1070 i40e_init_customized_info(struct i40e_pf *pf)
1071 {
1072         int i;
1073
1074         /* Initialize customized pctype */
1075         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1076                 pf->customized_pctype[i].index = i;
1077                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1078                 pf->customized_pctype[i].valid = false;
1079         }
1080
1081         pf->gtp_support = false;
1082 }
1083
1084 void
1085 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1086 {
1087         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1088         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1089         struct i40e_queue_regions *info = &pf->queue_region;
1090         uint16_t i;
1091
1092         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1093                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1094
1095         memset(info, 0, sizeof(struct i40e_queue_regions));
1096 }
1097
1098 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
1099
1100 static int
1101 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1102                                const char *value,
1103                                void *opaque)
1104 {
1105         struct i40e_pf *pf;
1106         unsigned long support_multi_driver;
1107         char *end;
1108
1109         pf = (struct i40e_pf *)opaque;
1110
1111         errno = 0;
1112         support_multi_driver = strtoul(value, &end, 10);
1113         if (errno != 0 || end == value || *end != 0) {
1114                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1115                 return -(EINVAL);
1116         }
1117
1118         if (support_multi_driver == 1 || support_multi_driver == 0)
1119                 pf->support_multi_driver = (bool)support_multi_driver;
1120         else
1121                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1122                             "enable global configuration by default."
1123                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1124         return 0;
1125 }
1126
1127 static int
1128 i40e_support_multi_driver(struct rte_eth_dev *dev)
1129 {
1130         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1131         static const char *const valid_keys[] = {
1132                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1133         struct rte_kvargs *kvlist;
1134
1135         /* Enable global configuration by default */
1136         pf->support_multi_driver = false;
1137
1138         if (!dev->device->devargs)
1139                 return 0;
1140
1141         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1142         if (!kvlist)
1143                 return -EINVAL;
1144
1145         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1146                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1147                             "the first invalid or last valid one is used !",
1148                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1149
1150         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1151                                i40e_parse_multi_drv_handler, pf) < 0) {
1152                 rte_kvargs_free(kvlist);
1153                 return -EINVAL;
1154         }
1155
1156         rte_kvargs_free(kvlist);
1157         return 0;
1158 }
1159
1160 static int
1161 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1162 {
1163         struct rte_pci_device *pci_dev;
1164         struct rte_intr_handle *intr_handle;
1165         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1166         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1167         struct i40e_vsi *vsi;
1168         int ret;
1169         uint32_t len;
1170         uint8_t aq_fail = 0;
1171
1172         PMD_INIT_FUNC_TRACE();
1173
1174         dev->dev_ops = &i40e_eth_dev_ops;
1175         dev->rx_pkt_burst = i40e_recv_pkts;
1176         dev->tx_pkt_burst = i40e_xmit_pkts;
1177         dev->tx_pkt_prepare = i40e_prep_pkts;
1178
1179         /* for secondary processes, we don't initialise any further as primary
1180          * has already done this work. Only check we don't need a different
1181          * RX function */
1182         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1183                 i40e_set_rx_function(dev);
1184                 i40e_set_tx_function(dev);
1185                 return 0;
1186         }
1187         i40e_set_default_ptype_table(dev);
1188         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1189         intr_handle = &pci_dev->intr_handle;
1190
1191         rte_eth_copy_pci_info(dev, pci_dev);
1192
1193         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1194         pf->adapter->eth_dev = dev;
1195         pf->dev_data = dev->data;
1196
1197         hw->back = I40E_PF_TO_ADAPTER(pf);
1198         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1199         if (!hw->hw_addr) {
1200                 PMD_INIT_LOG(ERR,
1201                         "Hardware is not available, as address is NULL");
1202                 return -ENODEV;
1203         }
1204
1205         hw->vendor_id = pci_dev->id.vendor_id;
1206         hw->device_id = pci_dev->id.device_id;
1207         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1208         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1209         hw->bus.device = pci_dev->addr.devid;
1210         hw->bus.func = pci_dev->addr.function;
1211         hw->adapter_stopped = 0;
1212
1213         /* Check if need to support multi-driver */
1214         i40e_support_multi_driver(dev);
1215
1216         /* Make sure all is clean before doing PF reset */
1217         i40e_clear_hw(hw);
1218
1219         /* Initialize the hardware */
1220         i40e_hw_init(dev);
1221
1222         /* Reset here to make sure all is clean for each PF */
1223         ret = i40e_pf_reset(hw);
1224         if (ret) {
1225                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1226                 return ret;
1227         }
1228
1229         /* Initialize the shared code (base driver) */
1230         ret = i40e_init_shared_code(hw);
1231         if (ret) {
1232                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1233                 return ret;
1234         }
1235
1236         i40e_config_automask(pf);
1237
1238         i40e_set_default_pctype_table(dev);
1239
1240         /*
1241          * To work around the NVM issue, initialize registers
1242          * for packet type of QinQ by software.
1243          * It should be removed once issues are fixed in NVM.
1244          */
1245         if (!pf->support_multi_driver)
1246                 i40e_GLQF_reg_init(hw);
1247
1248         /* Initialize the input set for filters (hash and fd) to default value */
1249         i40e_filter_input_set_init(pf);
1250
1251         /* Initialize the parameters for adminq */
1252         i40e_init_adminq_parameter(hw);
1253         ret = i40e_init_adminq(hw);
1254         if (ret != I40E_SUCCESS) {
1255                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1256                 return -EIO;
1257         }
1258         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1259                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1260                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1261                      ((hw->nvm.version >> 12) & 0xf),
1262                      ((hw->nvm.version >> 4) & 0xff),
1263                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1264
1265         /* initialise the L3_MAP register */
1266         if (!pf->support_multi_driver) {
1267                 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1268                                                    0x00000028,  NULL);
1269                 if (ret)
1270                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1271                                      ret);
1272                 PMD_INIT_LOG(DEBUG,
1273                              "Global register 0x%08x is changed with 0x28",
1274                              I40E_GLQF_L3_MAP(40));
1275                 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1276         }
1277
1278         /* Need the special FW version to support floating VEB */
1279         config_floating_veb(dev);
1280         /* Clear PXE mode */
1281         i40e_clear_pxe_mode(hw);
1282         i40e_dev_sync_phy_type(hw);
1283
1284         /*
1285          * On X710, performance number is far from the expectation on recent
1286          * firmware versions. The fix for this issue may not be integrated in
1287          * the following firmware version. So the workaround in software driver
1288          * is needed. It needs to modify the initial values of 3 internal only
1289          * registers. Note that the workaround can be removed when it is fixed
1290          * in firmware in the future.
1291          */
1292         i40e_configure_registers(hw);
1293
1294         /* Get hw capabilities */
1295         ret = i40e_get_cap(hw);
1296         if (ret != I40E_SUCCESS) {
1297                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1298                 goto err_get_capabilities;
1299         }
1300
1301         /* Initialize parameters for PF */
1302         ret = i40e_pf_parameter_init(dev);
1303         if (ret != 0) {
1304                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1305                 goto err_parameter_init;
1306         }
1307
1308         /* Initialize the queue management */
1309         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1310         if (ret < 0) {
1311                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1312                 goto err_qp_pool_init;
1313         }
1314         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1315                                 hw->func_caps.num_msix_vectors - 1);
1316         if (ret < 0) {
1317                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1318                 goto err_msix_pool_init;
1319         }
1320
1321         /* Initialize lan hmc */
1322         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1323                                 hw->func_caps.num_rx_qp, 0, 0);
1324         if (ret != I40E_SUCCESS) {
1325                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1326                 goto err_init_lan_hmc;
1327         }
1328
1329         /* Configure lan hmc */
1330         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1331         if (ret != I40E_SUCCESS) {
1332                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1333                 goto err_configure_lan_hmc;
1334         }
1335
1336         /* Get and check the mac address */
1337         i40e_get_mac_addr(hw, hw->mac.addr);
1338         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1339                 PMD_INIT_LOG(ERR, "mac address is not valid");
1340                 ret = -EIO;
1341                 goto err_get_mac_addr;
1342         }
1343         /* Copy the permanent MAC address */
1344         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1345                         (struct ether_addr *) hw->mac.perm_addr);
1346
1347         /* Disable flow control */
1348         hw->fc.requested_mode = I40E_FC_NONE;
1349         i40e_set_fc(hw, &aq_fail, TRUE);
1350
1351         /* Set the global registers with default ether type value */
1352         if (!pf->support_multi_driver) {
1353                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1354                                          ETHER_TYPE_VLAN);
1355                 if (ret != I40E_SUCCESS) {
1356                         PMD_INIT_LOG(ERR,
1357                                      "Failed to set the default outer "
1358                                      "VLAN ether type");
1359                         goto err_setup_pf_switch;
1360                 }
1361         }
1362
1363         /* PF setup, which includes VSI setup */
1364         ret = i40e_pf_setup(pf);
1365         if (ret) {
1366                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1367                 goto err_setup_pf_switch;
1368         }
1369
1370         /* reset all stats of the device, including pf and main vsi */
1371         i40e_dev_stats_reset(dev);
1372
1373         vsi = pf->main_vsi;
1374
1375         /* Disable double vlan by default */
1376         i40e_vsi_config_double_vlan(vsi, FALSE);
1377
1378         /* Disable S-TAG identification when floating_veb is disabled */
1379         if (!pf->floating_veb) {
1380                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1381                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1382                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1383                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1384                 }
1385         }
1386
1387         if (!vsi->max_macaddrs)
1388                 len = ETHER_ADDR_LEN;
1389         else
1390                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1391
1392         /* Should be after VSI initialized */
1393         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1394         if (!dev->data->mac_addrs) {
1395                 PMD_INIT_LOG(ERR,
1396                         "Failed to allocated memory for storing mac address");
1397                 goto err_mac_alloc;
1398         }
1399         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1400                                         &dev->data->mac_addrs[0]);
1401
1402         /* Init dcb to sw mode by default */
1403         ret = i40e_dcb_init_configure(dev, TRUE);
1404         if (ret != I40E_SUCCESS) {
1405                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1406                 pf->flags &= ~I40E_FLAG_DCB;
1407         }
1408         /* Update HW struct after DCB configuration */
1409         i40e_get_cap(hw);
1410
1411         /* initialize pf host driver to setup SRIOV resource if applicable */
1412         i40e_pf_host_init(dev);
1413
1414         /* register callback func to eal lib */
1415         rte_intr_callback_register(intr_handle,
1416                                    i40e_dev_interrupt_handler, dev);
1417
1418         /* configure and enable device interrupt */
1419         i40e_pf_config_irq0(hw, TRUE);
1420         i40e_pf_enable_irq0(hw);
1421
1422         /* enable uio intr after callback register */
1423         rte_intr_enable(intr_handle);
1424
1425         /* By default disable flexible payload in global configuration */
1426         if (!pf->support_multi_driver)
1427                 i40e_flex_payload_reg_set_default(hw);
1428
1429         /*
1430          * Add an ethertype filter to drop all flow control frames transmitted
1431          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1432          * frames to wire.
1433          */
1434         i40e_add_tx_flow_control_drop_filter(pf);
1435
1436         /* Set the max frame size to 0x2600 by default,
1437          * in case other drivers changed the default value.
1438          */
1439         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1440
1441         /* initialize mirror rule list */
1442         TAILQ_INIT(&pf->mirror_list);
1443
1444         /* initialize Traffic Manager configuration */
1445         i40e_tm_conf_init(dev);
1446
1447         /* Initialize customized information */
1448         i40e_init_customized_info(pf);
1449
1450         ret = i40e_init_ethtype_filter_list(dev);
1451         if (ret < 0)
1452                 goto err_init_ethtype_filter_list;
1453         ret = i40e_init_tunnel_filter_list(dev);
1454         if (ret < 0)
1455                 goto err_init_tunnel_filter_list;
1456         ret = i40e_init_fdir_filter_list(dev);
1457         if (ret < 0)
1458                 goto err_init_fdir_filter_list;
1459
1460         /* initialize queue region configuration */
1461         i40e_init_queue_region_conf(dev);
1462
1463         /* initialize rss configuration from rte_flow */
1464         memset(&pf->rss_info, 0,
1465                 sizeof(struct i40e_rte_flow_rss_conf));
1466
1467         return 0;
1468
1469 err_init_fdir_filter_list:
1470         rte_free(pf->tunnel.hash_table);
1471         rte_free(pf->tunnel.hash_map);
1472 err_init_tunnel_filter_list:
1473         rte_free(pf->ethertype.hash_table);
1474         rte_free(pf->ethertype.hash_map);
1475 err_init_ethtype_filter_list:
1476         rte_free(dev->data->mac_addrs);
1477 err_mac_alloc:
1478         i40e_vsi_release(pf->main_vsi);
1479 err_setup_pf_switch:
1480 err_get_mac_addr:
1481 err_configure_lan_hmc:
1482         (void)i40e_shutdown_lan_hmc(hw);
1483 err_init_lan_hmc:
1484         i40e_res_pool_destroy(&pf->msix_pool);
1485 err_msix_pool_init:
1486         i40e_res_pool_destroy(&pf->qp_pool);
1487 err_qp_pool_init:
1488 err_parameter_init:
1489 err_get_capabilities:
1490         (void)i40e_shutdown_adminq(hw);
1491
1492         return ret;
1493 }
1494
1495 static void
1496 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1497 {
1498         struct i40e_ethertype_filter *p_ethertype;
1499         struct i40e_ethertype_rule *ethertype_rule;
1500
1501         ethertype_rule = &pf->ethertype;
1502         /* Remove all ethertype filter rules and hash */
1503         if (ethertype_rule->hash_map)
1504                 rte_free(ethertype_rule->hash_map);
1505         if (ethertype_rule->hash_table)
1506                 rte_hash_free(ethertype_rule->hash_table);
1507
1508         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1509                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1510                              p_ethertype, rules);
1511                 rte_free(p_ethertype);
1512         }
1513 }
1514
1515 static void
1516 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1517 {
1518         struct i40e_tunnel_filter *p_tunnel;
1519         struct i40e_tunnel_rule *tunnel_rule;
1520
1521         tunnel_rule = &pf->tunnel;
1522         /* Remove all tunnel director rules and hash */
1523         if (tunnel_rule->hash_map)
1524                 rte_free(tunnel_rule->hash_map);
1525         if (tunnel_rule->hash_table)
1526                 rte_hash_free(tunnel_rule->hash_table);
1527
1528         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1529                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1530                 rte_free(p_tunnel);
1531         }
1532 }
1533
1534 static void
1535 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1536 {
1537         struct i40e_fdir_filter *p_fdir;
1538         struct i40e_fdir_info *fdir_info;
1539
1540         fdir_info = &pf->fdir;
1541         /* Remove all flow director rules and hash */
1542         if (fdir_info->hash_map)
1543                 rte_free(fdir_info->hash_map);
1544         if (fdir_info->hash_table)
1545                 rte_hash_free(fdir_info->hash_table);
1546
1547         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1548                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1549                 rte_free(p_fdir);
1550         }
1551 }
1552
1553 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1554 {
1555         /*
1556          * Disable by default flexible payload
1557          * for corresponding L2/L3/L4 layers.
1558          */
1559         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1560         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1561         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1562         i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
1563 }
1564
1565 static int
1566 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1567 {
1568         struct i40e_pf *pf;
1569         struct rte_pci_device *pci_dev;
1570         struct rte_intr_handle *intr_handle;
1571         struct i40e_hw *hw;
1572         struct i40e_filter_control_settings settings;
1573         struct rte_flow *p_flow;
1574         int ret;
1575         uint8_t aq_fail = 0;
1576         int retries = 0;
1577
1578         PMD_INIT_FUNC_TRACE();
1579
1580         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1581                 return 0;
1582
1583         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1584         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1586         intr_handle = &pci_dev->intr_handle;
1587
1588         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1589         if (ret)
1590                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1591
1592         if (hw->adapter_stopped == 0)
1593                 i40e_dev_close(dev);
1594
1595         dev->dev_ops = NULL;
1596         dev->rx_pkt_burst = NULL;
1597         dev->tx_pkt_burst = NULL;
1598
1599         /* Clear PXE mode */
1600         i40e_clear_pxe_mode(hw);
1601
1602         /* Unconfigure filter control */
1603         memset(&settings, 0, sizeof(settings));
1604         ret = i40e_set_filter_control(hw, &settings);
1605         if (ret)
1606                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1607                                         ret);
1608
1609         /* Disable flow control */
1610         hw->fc.requested_mode = I40E_FC_NONE;
1611         i40e_set_fc(hw, &aq_fail, TRUE);
1612
1613         /* uninitialize pf host driver */
1614         i40e_pf_host_uninit(dev);
1615
1616         rte_free(dev->data->mac_addrs);
1617         dev->data->mac_addrs = NULL;
1618
1619         /* disable uio intr before callback unregister */
1620         rte_intr_disable(intr_handle);
1621
1622         /* unregister callback func to eal lib */
1623         do {
1624                 ret = rte_intr_callback_unregister(intr_handle,
1625                                 i40e_dev_interrupt_handler, dev);
1626                 if (ret >= 0) {
1627                         break;
1628                 } else if (ret != -EAGAIN) {
1629                         PMD_INIT_LOG(ERR,
1630                                  "intr callback unregister failed: %d",
1631                                  ret);
1632                         return ret;
1633                 }
1634                 i40e_msec_delay(500);
1635         } while (retries++ < 5);
1636
1637         i40e_rm_ethtype_filter_list(pf);
1638         i40e_rm_tunnel_filter_list(pf);
1639         i40e_rm_fdir_filter_list(pf);
1640
1641         /* Remove all flows */
1642         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1643                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1644                 rte_free(p_flow);
1645         }
1646
1647         /* Remove all Traffic Manager configuration */
1648         i40e_tm_conf_uninit(dev);
1649
1650         return 0;
1651 }
1652
1653 static int
1654 i40e_dev_configure(struct rte_eth_dev *dev)
1655 {
1656         struct i40e_adapter *ad =
1657                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1658         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1659         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1660         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1661         int i, ret;
1662
1663         ret = i40e_dev_sync_phy_type(hw);
1664         if (ret)
1665                 return ret;
1666
1667         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1668          * bulk allocation or vector Rx preconditions we will reset it.
1669          */
1670         ad->rx_bulk_alloc_allowed = true;
1671         ad->rx_vec_allowed = true;
1672         ad->tx_simple_allowed = true;
1673         ad->tx_vec_allowed = true;
1674
1675         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1676                 ret = i40e_fdir_setup(pf);
1677                 if (ret != I40E_SUCCESS) {
1678                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1679                         return -ENOTSUP;
1680                 }
1681                 ret = i40e_fdir_configure(dev);
1682                 if (ret < 0) {
1683                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1684                         goto err;
1685                 }
1686         } else
1687                 i40e_fdir_teardown(pf);
1688
1689         ret = i40e_dev_init_vlan(dev);
1690         if (ret < 0)
1691                 goto err;
1692
1693         /* VMDQ setup.
1694          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1695          *  RSS setting have different requirements.
1696          *  General PMD driver call sequence are NIC init, configure,
1697          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1698          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1699          *  applicable. So, VMDQ setting has to be done before
1700          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1701          *  For RSS setting, it will try to calculate actual configured RX queue
1702          *  number, which will be available after rx_queue_setup(). dev_start()
1703          *  function is good to place RSS setup.
1704          */
1705         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1706                 ret = i40e_vmdq_setup(dev);
1707                 if (ret)
1708                         goto err;
1709         }
1710
1711         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1712                 ret = i40e_dcb_setup(dev);
1713                 if (ret) {
1714                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1715                         goto err_dcb;
1716                 }
1717         }
1718
1719         TAILQ_INIT(&pf->flow_list);
1720
1721         return 0;
1722
1723 err_dcb:
1724         /* need to release vmdq resource if exists */
1725         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1726                 i40e_vsi_release(pf->vmdq[i].vsi);
1727                 pf->vmdq[i].vsi = NULL;
1728         }
1729         rte_free(pf->vmdq);
1730         pf->vmdq = NULL;
1731 err:
1732         /* need to release fdir resource if exists */
1733         i40e_fdir_teardown(pf);
1734         return ret;
1735 }
1736
1737 void
1738 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1739 {
1740         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1741         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1742         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1743         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1744         uint16_t msix_vect = vsi->msix_intr;
1745         uint16_t i;
1746
1747         for (i = 0; i < vsi->nb_qps; i++) {
1748                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1749                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1750                 rte_wmb();
1751         }
1752
1753         if (vsi->type != I40E_VSI_SRIOV) {
1754                 if (!rte_intr_allow_others(intr_handle)) {
1755                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1756                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1757                         I40E_WRITE_REG(hw,
1758                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1759                                        0);
1760                 } else {
1761                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1762                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1763                         I40E_WRITE_REG(hw,
1764                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1765                                                        msix_vect - 1), 0);
1766                 }
1767         } else {
1768                 uint32_t reg;
1769                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1770                         vsi->user_param + (msix_vect - 1);
1771
1772                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1773                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1774         }
1775         I40E_WRITE_FLUSH(hw);
1776 }
1777
1778 static void
1779 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1780                        int base_queue, int nb_queue,
1781                        uint16_t itr_idx)
1782 {
1783         int i;
1784         uint32_t val;
1785         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1786         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1787
1788         /* Bind all RX queues to allocated MSIX interrupt */
1789         for (i = 0; i < nb_queue; i++) {
1790                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1791                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1792                         ((base_queue + i + 1) <<
1793                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1794                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1795                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1796
1797                 if (i == nb_queue - 1)
1798                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1799                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1800         }
1801
1802         /* Write first RX queue to Link list register as the head element */
1803         if (vsi->type != I40E_VSI_SRIOV) {
1804                 uint16_t interval =
1805                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,
1806                                                pf->support_multi_driver);
1807
1808                 if (msix_vect == I40E_MISC_VEC_ID) {
1809                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1810                                        (base_queue <<
1811                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1812                                        (0x0 <<
1813                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1814                         I40E_WRITE_REG(hw,
1815                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1816                                        interval);
1817                 } else {
1818                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1819                                        (base_queue <<
1820                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1821                                        (0x0 <<
1822                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1823                         I40E_WRITE_REG(hw,
1824                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1825                                                        msix_vect - 1),
1826                                        interval);
1827                 }
1828         } else {
1829                 uint32_t reg;
1830
1831                 if (msix_vect == I40E_MISC_VEC_ID) {
1832                         I40E_WRITE_REG(hw,
1833                                        I40E_VPINT_LNKLST0(vsi->user_param),
1834                                        (base_queue <<
1835                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1836                                        (0x0 <<
1837                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1838                 } else {
1839                         /* num_msix_vectors_vf needs to minus irq0 */
1840                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1841                                 vsi->user_param + (msix_vect - 1);
1842
1843                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1844                                        (base_queue <<
1845                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1846                                        (0x0 <<
1847                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1848                 }
1849         }
1850
1851         I40E_WRITE_FLUSH(hw);
1852 }
1853
1854 void
1855 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1856 {
1857         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1858         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1859         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1860         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1861         uint16_t msix_vect = vsi->msix_intr;
1862         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1863         uint16_t queue_idx = 0;
1864         int record = 0;
1865         int i;
1866
1867         for (i = 0; i < vsi->nb_qps; i++) {
1868                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1869                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1870         }
1871
1872         /* VF bind interrupt */
1873         if (vsi->type == I40E_VSI_SRIOV) {
1874                 __vsi_queues_bind_intr(vsi, msix_vect,
1875                                        vsi->base_queue, vsi->nb_qps,
1876                                        itr_idx);
1877                 return;
1878         }
1879
1880         /* PF & VMDq bind interrupt */
1881         if (rte_intr_dp_is_en(intr_handle)) {
1882                 if (vsi->type == I40E_VSI_MAIN) {
1883                         queue_idx = 0;
1884                         record = 1;
1885                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1886                         struct i40e_vsi *main_vsi =
1887                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1888                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1889                         record = 1;
1890                 }
1891         }
1892
1893         for (i = 0; i < vsi->nb_used_qps; i++) {
1894                 if (nb_msix <= 1) {
1895                         if (!rte_intr_allow_others(intr_handle))
1896                                 /* allow to share MISC_VEC_ID */
1897                                 msix_vect = I40E_MISC_VEC_ID;
1898
1899                         /* no enough msix_vect, map all to one */
1900                         __vsi_queues_bind_intr(vsi, msix_vect,
1901                                                vsi->base_queue + i,
1902                                                vsi->nb_used_qps - i,
1903                                                itr_idx);
1904                         for (; !!record && i < vsi->nb_used_qps; i++)
1905                                 intr_handle->intr_vec[queue_idx + i] =
1906                                         msix_vect;
1907                         break;
1908                 }
1909                 /* 1:1 queue/msix_vect mapping */
1910                 __vsi_queues_bind_intr(vsi, msix_vect,
1911                                        vsi->base_queue + i, 1,
1912                                        itr_idx);
1913                 if (!!record)
1914                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1915
1916                 msix_vect++;
1917                 nb_msix--;
1918         }
1919 }
1920
1921 static void
1922 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1923 {
1924         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1925         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1926         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1927         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1928         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1929         uint16_t msix_intr, i;
1930
1931         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1932                 for (i = 0; i < vsi->nb_msix; i++) {
1933                         msix_intr = vsi->msix_intr + i;
1934                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1935                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1936                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1937                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1938                 }
1939         else
1940                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1941                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1942                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1943                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1944
1945         I40E_WRITE_FLUSH(hw);
1946 }
1947
1948 static void
1949 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1950 {
1951         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1952         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1953         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1954         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1955         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1956         uint16_t msix_intr, i;
1957
1958         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1959                 for (i = 0; i < vsi->nb_msix; i++) {
1960                         msix_intr = vsi->msix_intr + i;
1961                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1962                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1963                 }
1964         else
1965                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1966                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1967
1968         I40E_WRITE_FLUSH(hw);
1969 }
1970
1971 static inline uint8_t
1972 i40e_parse_link_speeds(uint16_t link_speeds)
1973 {
1974         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1975
1976         if (link_speeds & ETH_LINK_SPEED_40G)
1977                 link_speed |= I40E_LINK_SPEED_40GB;
1978         if (link_speeds & ETH_LINK_SPEED_25G)
1979                 link_speed |= I40E_LINK_SPEED_25GB;
1980         if (link_speeds & ETH_LINK_SPEED_20G)
1981                 link_speed |= I40E_LINK_SPEED_20GB;
1982         if (link_speeds & ETH_LINK_SPEED_10G)
1983                 link_speed |= I40E_LINK_SPEED_10GB;
1984         if (link_speeds & ETH_LINK_SPEED_1G)
1985                 link_speed |= I40E_LINK_SPEED_1GB;
1986         if (link_speeds & ETH_LINK_SPEED_100M)
1987                 link_speed |= I40E_LINK_SPEED_100MB;
1988
1989         return link_speed;
1990 }
1991
1992 static int
1993 i40e_phy_conf_link(struct i40e_hw *hw,
1994                    uint8_t abilities,
1995                    uint8_t force_speed,
1996                    bool is_up)
1997 {
1998         enum i40e_status_code status;
1999         struct i40e_aq_get_phy_abilities_resp phy_ab;
2000         struct i40e_aq_set_phy_config phy_conf;
2001         enum i40e_aq_phy_type cnt;
2002         uint32_t phy_type_mask = 0;
2003
2004         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2005                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2006                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2007                         I40E_AQ_PHY_FLAG_LOW_POWER;
2008         const uint8_t advt = I40E_LINK_SPEED_40GB |
2009                         I40E_LINK_SPEED_25GB |
2010                         I40E_LINK_SPEED_10GB |
2011                         I40E_LINK_SPEED_1GB |
2012                         I40E_LINK_SPEED_100MB;
2013         int ret = -ENOTSUP;
2014
2015
2016         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2017                                               NULL);
2018         if (status)
2019                 return ret;
2020
2021         /* If link already up, no need to set up again */
2022         if (is_up && phy_ab.phy_type != 0)
2023                 return I40E_SUCCESS;
2024
2025         memset(&phy_conf, 0, sizeof(phy_conf));
2026
2027         /* bits 0-2 use the values from get_phy_abilities_resp */
2028         abilities &= ~mask;
2029         abilities |= phy_ab.abilities & mask;
2030
2031         /* update ablities and speed */
2032         if (abilities & I40E_AQ_PHY_AN_ENABLED)
2033                 phy_conf.link_speed = advt;
2034         else
2035                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
2036
2037         phy_conf.abilities = abilities;
2038
2039
2040
2041         /* To enable link, phy_type mask needs to include each type */
2042         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
2043                 phy_type_mask |= 1 << cnt;
2044
2045         /* use get_phy_abilities_resp value for the rest */
2046         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2047         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2048                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2049                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2050         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2051         phy_conf.eee_capability = phy_ab.eee_capability;
2052         phy_conf.eeer = phy_ab.eeer_val;
2053         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2054
2055         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2056                     phy_ab.abilities, phy_ab.link_speed);
2057         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2058                     phy_conf.abilities, phy_conf.link_speed);
2059
2060         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2061         if (status)
2062                 return ret;
2063
2064         return I40E_SUCCESS;
2065 }
2066
2067 static int
2068 i40e_apply_link_speed(struct rte_eth_dev *dev)
2069 {
2070         uint8_t speed;
2071         uint8_t abilities = 0;
2072         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2073         struct rte_eth_conf *conf = &dev->data->dev_conf;
2074
2075         speed = i40e_parse_link_speeds(conf->link_speeds);
2076         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2077         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2078                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2079         abilities |= I40E_AQ_PHY_LINK_ENABLED;
2080
2081         return i40e_phy_conf_link(hw, abilities, speed, true);
2082 }
2083
2084 static int
2085 i40e_dev_start(struct rte_eth_dev *dev)
2086 {
2087         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2088         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2089         struct i40e_vsi *main_vsi = pf->main_vsi;
2090         int ret, i;
2091         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2092         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2093         uint32_t intr_vector = 0;
2094         struct i40e_vsi *vsi;
2095
2096         hw->adapter_stopped = 0;
2097
2098         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2099                 PMD_INIT_LOG(ERR,
2100                 "Invalid link_speeds for port %u, autonegotiation disabled",
2101                               dev->data->port_id);
2102                 return -EINVAL;
2103         }
2104
2105         rte_intr_disable(intr_handle);
2106
2107         if ((rte_intr_cap_multiple(intr_handle) ||
2108              !RTE_ETH_DEV_SRIOV(dev).active) &&
2109             dev->data->dev_conf.intr_conf.rxq != 0) {
2110                 intr_vector = dev->data->nb_rx_queues;
2111                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2112                 if (ret)
2113                         return ret;
2114         }
2115
2116         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2117                 intr_handle->intr_vec =
2118                         rte_zmalloc("intr_vec",
2119                                     dev->data->nb_rx_queues * sizeof(int),
2120                                     0);
2121                 if (!intr_handle->intr_vec) {
2122                         PMD_INIT_LOG(ERR,
2123                                 "Failed to allocate %d rx_queues intr_vec",
2124                                 dev->data->nb_rx_queues);
2125                         return -ENOMEM;
2126                 }
2127         }
2128
2129         /* Initialize VSI */
2130         ret = i40e_dev_rxtx_init(pf);
2131         if (ret != I40E_SUCCESS) {
2132                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2133                 goto err_up;
2134         }
2135
2136         /* Map queues with MSIX interrupt */
2137         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2138                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2139         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2140         i40e_vsi_enable_queues_intr(main_vsi);
2141
2142         /* Map VMDQ VSI queues with MSIX interrupt */
2143         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2144                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2145                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2146                                           I40E_ITR_INDEX_DEFAULT);
2147                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2148         }
2149
2150         /* enable FDIR MSIX interrupt */
2151         if (pf->fdir.fdir_vsi) {
2152                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2153                                           I40E_ITR_INDEX_NONE);
2154                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2155         }
2156
2157         /* Enable all queues which have been configured */
2158         ret = i40e_dev_switch_queues(pf, TRUE);
2159         if (ret != I40E_SUCCESS) {
2160                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2161                 goto err_up;
2162         }
2163
2164         /* Enable receiving broadcast packets */
2165         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2166         if (ret != I40E_SUCCESS)
2167                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2168
2169         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2170                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2171                                                 true, NULL);
2172                 if (ret != I40E_SUCCESS)
2173                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2174         }
2175
2176         /* Enable the VLAN promiscuous mode. */
2177         if (pf->vfs) {
2178                 for (i = 0; i < pf->vf_num; i++) {
2179                         vsi = pf->vfs[i].vsi;
2180                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2181                                                      true, NULL);
2182                 }
2183         }
2184
2185         /* Enable mac loopback mode */
2186         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2187             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2188                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2189                 if (ret != I40E_SUCCESS) {
2190                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2191                         goto err_up;
2192                 }
2193         }
2194
2195         /* Apply link configure */
2196         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2197                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2198                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2199                                 ETH_LINK_SPEED_40G)) {
2200                 PMD_DRV_LOG(ERR, "Invalid link setting");
2201                 goto err_up;
2202         }
2203         ret = i40e_apply_link_speed(dev);
2204         if (I40E_SUCCESS != ret) {
2205                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2206                 goto err_up;
2207         }
2208
2209         if (!rte_intr_allow_others(intr_handle)) {
2210                 rte_intr_callback_unregister(intr_handle,
2211                                              i40e_dev_interrupt_handler,
2212                                              (void *)dev);
2213                 /* configure and enable device interrupt */
2214                 i40e_pf_config_irq0(hw, FALSE);
2215                 i40e_pf_enable_irq0(hw);
2216
2217                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2218                         PMD_INIT_LOG(INFO,
2219                                 "lsc won't enable because of no intr multiplex");
2220         } else {
2221                 ret = i40e_aq_set_phy_int_mask(hw,
2222                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2223                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2224                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2225                 if (ret != I40E_SUCCESS)
2226                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2227
2228                 /* Call get_link_info aq commond to enable/disable LSE */
2229                 i40e_dev_link_update(dev, 0);
2230         }
2231
2232         /* enable uio intr after callback register */
2233         rte_intr_enable(intr_handle);
2234
2235         i40e_filter_restore(pf);
2236
2237         if (pf->tm_conf.root && !pf->tm_conf.committed)
2238                 PMD_DRV_LOG(WARNING,
2239                             "please call hierarchy_commit() "
2240                             "before starting the port");
2241
2242         return I40E_SUCCESS;
2243
2244 err_up:
2245         i40e_dev_switch_queues(pf, FALSE);
2246         i40e_dev_clear_queues(dev);
2247
2248         return ret;
2249 }
2250
2251 static void
2252 i40e_dev_stop(struct rte_eth_dev *dev)
2253 {
2254         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2255         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2256         struct i40e_vsi *main_vsi = pf->main_vsi;
2257         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2258         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2259         int i;
2260
2261         if (hw->adapter_stopped == 1)
2262                 return;
2263         /* Disable all queues */
2264         i40e_dev_switch_queues(pf, FALSE);
2265
2266         /* un-map queues with interrupt registers */
2267         i40e_vsi_disable_queues_intr(main_vsi);
2268         i40e_vsi_queues_unbind_intr(main_vsi);
2269
2270         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2271                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2272                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2273         }
2274
2275         if (pf->fdir.fdir_vsi) {
2276                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2277                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2278         }
2279         /* Clear all queues and release memory */
2280         i40e_dev_clear_queues(dev);
2281
2282         /* Set link down */
2283         i40e_dev_set_link_down(dev);
2284
2285         if (!rte_intr_allow_others(intr_handle))
2286                 /* resume to the default handler */
2287                 rte_intr_callback_register(intr_handle,
2288                                            i40e_dev_interrupt_handler,
2289                                            (void *)dev);
2290
2291         /* Clean datapath event and queue/vec mapping */
2292         rte_intr_efd_disable(intr_handle);
2293         if (intr_handle->intr_vec) {
2294                 rte_free(intr_handle->intr_vec);
2295                 intr_handle->intr_vec = NULL;
2296         }
2297
2298         /* reset hierarchy commit */
2299         pf->tm_conf.committed = false;
2300
2301         hw->adapter_stopped = 1;
2302 }
2303
2304 static void
2305 i40e_dev_close(struct rte_eth_dev *dev)
2306 {
2307         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2308         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2309         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2310         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2311         struct i40e_mirror_rule *p_mirror;
2312         uint32_t reg;
2313         int i;
2314         int ret;
2315
2316         PMD_INIT_FUNC_TRACE();
2317
2318         i40e_dev_stop(dev);
2319
2320         /* Remove all mirror rules */
2321         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2322                 ret = i40e_aq_del_mirror_rule(hw,
2323                                               pf->main_vsi->veb->seid,
2324                                               p_mirror->rule_type,
2325                                               p_mirror->entries,
2326                                               p_mirror->num_entries,
2327                                               p_mirror->id);
2328                 if (ret < 0)
2329                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2330                                     "status = %d, aq_err = %d.", ret,
2331                                     hw->aq.asq_last_status);
2332
2333                 /* remove mirror software resource anyway */
2334                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2335                 rte_free(p_mirror);
2336                 pf->nb_mirror_rule--;
2337         }
2338
2339         i40e_dev_free_queues(dev);
2340
2341         /* Disable interrupt */
2342         i40e_pf_disable_irq0(hw);
2343         rte_intr_disable(intr_handle);
2344
2345         /* shutdown and destroy the HMC */
2346         i40e_shutdown_lan_hmc(hw);
2347
2348         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2349                 i40e_vsi_release(pf->vmdq[i].vsi);
2350                 pf->vmdq[i].vsi = NULL;
2351         }
2352         rte_free(pf->vmdq);
2353         pf->vmdq = NULL;
2354
2355         /* release all the existing VSIs and VEBs */
2356         i40e_fdir_teardown(pf);
2357         i40e_vsi_release(pf->main_vsi);
2358
2359         /* shutdown the adminq */
2360         i40e_aq_queue_shutdown(hw, true);
2361         i40e_shutdown_adminq(hw);
2362
2363         i40e_res_pool_destroy(&pf->qp_pool);
2364         i40e_res_pool_destroy(&pf->msix_pool);
2365
2366         /* Disable flexible payload in global configuration */
2367         if (!pf->support_multi_driver)
2368                 i40e_flex_payload_reg_set_default(hw);
2369
2370         /* force a PF reset to clean anything leftover */
2371         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2372         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2373                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2374         I40E_WRITE_FLUSH(hw);
2375 }
2376
2377 /*
2378  * Reset PF device only to re-initialize resources in PMD layer
2379  */
2380 static int
2381 i40e_dev_reset(struct rte_eth_dev *dev)
2382 {
2383         int ret;
2384
2385         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2386          * its VF to make them align with it. The detailed notification
2387          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2388          * To avoid unexpected behavior in VF, currently reset of PF with
2389          * SR-IOV activation is not supported. It might be supported later.
2390          */
2391         if (dev->data->sriov.active)
2392                 return -ENOTSUP;
2393
2394         ret = eth_i40e_dev_uninit(dev);
2395         if (ret)
2396                 return ret;
2397
2398         ret = eth_i40e_dev_init(dev, NULL);
2399
2400         return ret;
2401 }
2402
2403 static void
2404 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2405 {
2406         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2407         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2408         struct i40e_vsi *vsi = pf->main_vsi;
2409         int status;
2410
2411         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2412                                                      true, NULL, true);
2413         if (status != I40E_SUCCESS)
2414                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2415
2416         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2417                                                         TRUE, NULL);
2418         if (status != I40E_SUCCESS)
2419                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2420
2421 }
2422
2423 static void
2424 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2425 {
2426         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2427         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2428         struct i40e_vsi *vsi = pf->main_vsi;
2429         int status;
2430
2431         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2432                                                      false, NULL, true);
2433         if (status != I40E_SUCCESS)
2434                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2435
2436         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2437                                                         false, NULL);
2438         if (status != I40E_SUCCESS)
2439                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2440 }
2441
2442 static void
2443 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2444 {
2445         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2446         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2447         struct i40e_vsi *vsi = pf->main_vsi;
2448         int ret;
2449
2450         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2451         if (ret != I40E_SUCCESS)
2452                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2453 }
2454
2455 static void
2456 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2457 {
2458         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2459         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2460         struct i40e_vsi *vsi = pf->main_vsi;
2461         int ret;
2462
2463         if (dev->data->promiscuous == 1)
2464                 return; /* must remain in all_multicast mode */
2465
2466         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2467                                 vsi->seid, FALSE, NULL);
2468         if (ret != I40E_SUCCESS)
2469                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2470 }
2471
2472 /*
2473  * Set device link up.
2474  */
2475 static int
2476 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2477 {
2478         /* re-apply link speed setting */
2479         return i40e_apply_link_speed(dev);
2480 }
2481
2482 /*
2483  * Set device link down.
2484  */
2485 static int
2486 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2487 {
2488         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2489         uint8_t abilities = 0;
2490         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2491
2492         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2493         return i40e_phy_conf_link(hw, abilities, speed, false);
2494 }
2495
2496 static __rte_always_inline void
2497 update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link)
2498 {
2499 /* Link status registers and values*/
2500 #define I40E_PRTMAC_LINKSTA             0x001E2420
2501 #define I40E_REG_LINK_UP                0x40000080
2502 #define I40E_PRTMAC_MACC                0x001E24E0
2503 #define I40E_REG_MACC_25GB              0x00020000
2504 #define I40E_REG_SPEED_MASK             0x38000000
2505 #define I40E_REG_SPEED_100MB            0x00000000
2506 #define I40E_REG_SPEED_1GB              0x08000000
2507 #define I40E_REG_SPEED_10GB             0x10000000
2508 #define I40E_REG_SPEED_20GB             0x20000000
2509 #define I40E_REG_SPEED_25_40GB          0x18000000
2510         uint32_t link_speed;
2511         uint32_t reg_val;
2512
2513         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2514         link_speed = reg_val & I40E_REG_SPEED_MASK;
2515         reg_val &= I40E_REG_LINK_UP;
2516         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2517
2518         if (unlikely(link->link_status != 0))
2519                 return;
2520
2521         /* Parse the link status */
2522         switch (link_speed) {
2523         case I40E_REG_SPEED_100MB:
2524                 link->link_speed = ETH_SPEED_NUM_100M;
2525                 break;
2526         case I40E_REG_SPEED_1GB:
2527                 link->link_speed = ETH_SPEED_NUM_1G;
2528                 break;
2529         case I40E_REG_SPEED_10GB:
2530                 link->link_speed = ETH_SPEED_NUM_10G;
2531                 break;
2532         case I40E_REG_SPEED_20GB:
2533                 link->link_speed = ETH_SPEED_NUM_20G;
2534                 break;
2535         case I40E_REG_SPEED_25_40GB:
2536                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2537
2538                 if (reg_val & I40E_REG_MACC_25GB)
2539                         link->link_speed = ETH_SPEED_NUM_25G;
2540                 else
2541                         link->link_speed = ETH_SPEED_NUM_40G;
2542
2543                 break;
2544         default:
2545                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2546                 break;
2547         }
2548 }
2549
2550 static __rte_always_inline void
2551 update_link_wait(struct i40e_hw *hw, struct rte_eth_link *link,
2552         bool enable_lse)
2553 {
2554 #define CHECK_INTERVAL             100  /* 100ms */
2555 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2556         uint32_t rep_cnt = MAX_REPEAT_TIME;
2557         struct i40e_link_status link_status;
2558         int status;
2559
2560         memset(&link_status, 0, sizeof(link_status));
2561
2562         do {
2563                 memset(&link_status, 0, sizeof(link_status));
2564
2565                 /* Get link status information from hardware */
2566                 status = i40e_aq_get_link_info(hw, enable_lse,
2567                                                 &link_status, NULL);
2568                 if (unlikely(status != I40E_SUCCESS)) {
2569                         link->link_speed = ETH_SPEED_NUM_100M;
2570                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2571                         PMD_DRV_LOG(ERR, "Failed to get link info");
2572                         return;
2573                 }
2574
2575                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2576                 if (unlikely(link->link_status != 0))
2577                         return;
2578
2579                 rte_delay_ms(CHECK_INTERVAL);
2580         } while (--rep_cnt);
2581
2582         /* Parse the link status */
2583         switch (link_status.link_speed) {
2584         case I40E_LINK_SPEED_100MB:
2585                 link->link_speed = ETH_SPEED_NUM_100M;
2586                 break;
2587         case I40E_LINK_SPEED_1GB:
2588                 link->link_speed = ETH_SPEED_NUM_1G;
2589                 break;
2590         case I40E_LINK_SPEED_10GB:
2591                 link->link_speed = ETH_SPEED_NUM_10G;
2592                 break;
2593         case I40E_LINK_SPEED_20GB:
2594                 link->link_speed = ETH_SPEED_NUM_20G;
2595                 break;
2596         case I40E_LINK_SPEED_25GB:
2597                 link->link_speed = ETH_SPEED_NUM_25G;
2598                 break;
2599         case I40E_LINK_SPEED_40GB:
2600                 link->link_speed = ETH_SPEED_NUM_40G;
2601                 break;
2602         default:
2603                 link->link_speed = ETH_SPEED_NUM_100M;
2604                 break;
2605         }
2606 }
2607
2608 int
2609 i40e_dev_link_update(struct rte_eth_dev *dev,
2610                      int wait_to_complete)
2611 {
2612         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2613         struct rte_eth_link link;
2614         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2615         int ret;
2616
2617         memset(&link, 0, sizeof(link));
2618
2619         /* i40e uses full duplex only */
2620         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2621         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2622                         ETH_LINK_SPEED_FIXED);
2623
2624         if (!wait_to_complete)
2625                 update_link_no_wait(hw, &link);
2626         else
2627                 update_link_wait(hw, &link, enable_lse);
2628
2629         ret = rte_eth_linkstatus_set(dev, &link);
2630         i40e_notify_all_vfs_link_status(dev);
2631
2632         return ret;
2633 }
2634
2635 /* Get all the statistics of a VSI */
2636 void
2637 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2638 {
2639         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2640         struct i40e_eth_stats *nes = &vsi->eth_stats;
2641         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2642         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2643
2644         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2645                             vsi->offset_loaded, &oes->rx_bytes,
2646                             &nes->rx_bytes);
2647         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2648                             vsi->offset_loaded, &oes->rx_unicast,
2649                             &nes->rx_unicast);
2650         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2651                             vsi->offset_loaded, &oes->rx_multicast,
2652                             &nes->rx_multicast);
2653         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2654                             vsi->offset_loaded, &oes->rx_broadcast,
2655                             &nes->rx_broadcast);
2656         /* exclude CRC bytes */
2657         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2658                 nes->rx_broadcast) * ETHER_CRC_LEN;
2659
2660         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2661                             &oes->rx_discards, &nes->rx_discards);
2662         /* GLV_REPC not supported */
2663         /* GLV_RMPC not supported */
2664         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2665                             &oes->rx_unknown_protocol,
2666                             &nes->rx_unknown_protocol);
2667         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2668                             vsi->offset_loaded, &oes->tx_bytes,
2669                             &nes->tx_bytes);
2670         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2671                             vsi->offset_loaded, &oes->tx_unicast,
2672                             &nes->tx_unicast);
2673         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2674                             vsi->offset_loaded, &oes->tx_multicast,
2675                             &nes->tx_multicast);
2676         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2677                             vsi->offset_loaded,  &oes->tx_broadcast,
2678                             &nes->tx_broadcast);
2679         /* GLV_TDPC not supported */
2680         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2681                             &oes->tx_errors, &nes->tx_errors);
2682         vsi->offset_loaded = true;
2683
2684         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2685                     vsi->vsi_id);
2686         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2687         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2688         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2689         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2690         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2691         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2692                     nes->rx_unknown_protocol);
2693         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2694         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2695         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2696         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2697         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2698         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2699         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2700                     vsi->vsi_id);
2701 }
2702
2703 static void
2704 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2705 {
2706         unsigned int i;
2707         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2708         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2709
2710         /* Get rx/tx bytes of internal transfer packets */
2711         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2712                         I40E_GLV_GORCL(hw->port),
2713                         pf->offset_loaded,
2714                         &pf->internal_stats_offset.rx_bytes,
2715                         &pf->internal_stats.rx_bytes);
2716
2717         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2718                         I40E_GLV_GOTCL(hw->port),
2719                         pf->offset_loaded,
2720                         &pf->internal_stats_offset.tx_bytes,
2721                         &pf->internal_stats.tx_bytes);
2722         /* Get total internal rx packet count */
2723         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2724                             I40E_GLV_UPRCL(hw->port),
2725                             pf->offset_loaded,
2726                             &pf->internal_stats_offset.rx_unicast,
2727                             &pf->internal_stats.rx_unicast);
2728         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2729                             I40E_GLV_MPRCL(hw->port),
2730                             pf->offset_loaded,
2731                             &pf->internal_stats_offset.rx_multicast,
2732                             &pf->internal_stats.rx_multicast);
2733         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2734                             I40E_GLV_BPRCL(hw->port),
2735                             pf->offset_loaded,
2736                             &pf->internal_stats_offset.rx_broadcast,
2737                             &pf->internal_stats.rx_broadcast);
2738         /* Get total internal tx packet count */
2739         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2740                             I40E_GLV_UPTCL(hw->port),
2741                             pf->offset_loaded,
2742                             &pf->internal_stats_offset.tx_unicast,
2743                             &pf->internal_stats.tx_unicast);
2744         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2745                             I40E_GLV_MPTCL(hw->port),
2746                             pf->offset_loaded,
2747                             &pf->internal_stats_offset.tx_multicast,
2748                             &pf->internal_stats.tx_multicast);
2749         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2750                             I40E_GLV_BPTCL(hw->port),
2751                             pf->offset_loaded,
2752                             &pf->internal_stats_offset.tx_broadcast,
2753                             &pf->internal_stats.tx_broadcast);
2754
2755         /* exclude CRC size */
2756         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2757                 pf->internal_stats.rx_multicast +
2758                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2759
2760         /* Get statistics of struct i40e_eth_stats */
2761         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2762                             I40E_GLPRT_GORCL(hw->port),
2763                             pf->offset_loaded, &os->eth.rx_bytes,
2764                             &ns->eth.rx_bytes);
2765         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2766                             I40E_GLPRT_UPRCL(hw->port),
2767                             pf->offset_loaded, &os->eth.rx_unicast,
2768                             &ns->eth.rx_unicast);
2769         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2770                             I40E_GLPRT_MPRCL(hw->port),
2771                             pf->offset_loaded, &os->eth.rx_multicast,
2772                             &ns->eth.rx_multicast);
2773         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2774                             I40E_GLPRT_BPRCL(hw->port),
2775                             pf->offset_loaded, &os->eth.rx_broadcast,
2776                             &ns->eth.rx_broadcast);
2777         /* Workaround: CRC size should not be included in byte statistics,
2778          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2779          */
2780         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2781                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2782
2783         /* exclude internal rx bytes
2784          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2785          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2786          * value.
2787          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2788          */
2789         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2790                 ns->eth.rx_bytes = 0;
2791         else
2792                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2793
2794         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2795                 ns->eth.rx_unicast = 0;
2796         else
2797                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2798
2799         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2800                 ns->eth.rx_multicast = 0;
2801         else
2802                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2803
2804         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2805                 ns->eth.rx_broadcast = 0;
2806         else
2807                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2808
2809         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2810                             pf->offset_loaded, &os->eth.rx_discards,
2811                             &ns->eth.rx_discards);
2812         /* GLPRT_REPC not supported */
2813         /* GLPRT_RMPC not supported */
2814         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2815                             pf->offset_loaded,
2816                             &os->eth.rx_unknown_protocol,
2817                             &ns->eth.rx_unknown_protocol);
2818         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2819                             I40E_GLPRT_GOTCL(hw->port),
2820                             pf->offset_loaded, &os->eth.tx_bytes,
2821                             &ns->eth.tx_bytes);
2822         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2823                             I40E_GLPRT_UPTCL(hw->port),
2824                             pf->offset_loaded, &os->eth.tx_unicast,
2825                             &ns->eth.tx_unicast);
2826         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2827                             I40E_GLPRT_MPTCL(hw->port),
2828                             pf->offset_loaded, &os->eth.tx_multicast,
2829                             &ns->eth.tx_multicast);
2830         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2831                             I40E_GLPRT_BPTCL(hw->port),
2832                             pf->offset_loaded, &os->eth.tx_broadcast,
2833                             &ns->eth.tx_broadcast);
2834         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2835                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2836
2837         /* exclude internal tx bytes
2838          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2839          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2840          * value.
2841          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2842          */
2843         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2844                 ns->eth.tx_bytes = 0;
2845         else
2846                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2847
2848         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2849                 ns->eth.tx_unicast = 0;
2850         else
2851                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2852
2853         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2854                 ns->eth.tx_multicast = 0;
2855         else
2856                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2857
2858         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2859                 ns->eth.tx_broadcast = 0;
2860         else
2861                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2862
2863         /* GLPRT_TEPC not supported */
2864
2865         /* additional port specific stats */
2866         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2867                             pf->offset_loaded, &os->tx_dropped_link_down,
2868                             &ns->tx_dropped_link_down);
2869         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2870                             pf->offset_loaded, &os->crc_errors,
2871                             &ns->crc_errors);
2872         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2873                             pf->offset_loaded, &os->illegal_bytes,
2874                             &ns->illegal_bytes);
2875         /* GLPRT_ERRBC not supported */
2876         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2877                             pf->offset_loaded, &os->mac_local_faults,
2878                             &ns->mac_local_faults);
2879         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2880                             pf->offset_loaded, &os->mac_remote_faults,
2881                             &ns->mac_remote_faults);
2882         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2883                             pf->offset_loaded, &os->rx_length_errors,
2884                             &ns->rx_length_errors);
2885         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2886                             pf->offset_loaded, &os->link_xon_rx,
2887                             &ns->link_xon_rx);
2888         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2889                             pf->offset_loaded, &os->link_xoff_rx,
2890                             &ns->link_xoff_rx);
2891         for (i = 0; i < 8; i++) {
2892                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2893                                     pf->offset_loaded,
2894                                     &os->priority_xon_rx[i],
2895                                     &ns->priority_xon_rx[i]);
2896                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2897                                     pf->offset_loaded,
2898                                     &os->priority_xoff_rx[i],
2899                                     &ns->priority_xoff_rx[i]);
2900         }
2901         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2902                             pf->offset_loaded, &os->link_xon_tx,
2903                             &ns->link_xon_tx);
2904         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2905                             pf->offset_loaded, &os->link_xoff_tx,
2906                             &ns->link_xoff_tx);
2907         for (i = 0; i < 8; i++) {
2908                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2909                                     pf->offset_loaded,
2910                                     &os->priority_xon_tx[i],
2911                                     &ns->priority_xon_tx[i]);
2912                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2913                                     pf->offset_loaded,
2914                                     &os->priority_xoff_tx[i],
2915                                     &ns->priority_xoff_tx[i]);
2916                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2917                                     pf->offset_loaded,
2918                                     &os->priority_xon_2_xoff[i],
2919                                     &ns->priority_xon_2_xoff[i]);
2920         }
2921         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2922                             I40E_GLPRT_PRC64L(hw->port),
2923                             pf->offset_loaded, &os->rx_size_64,
2924                             &ns->rx_size_64);
2925         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2926                             I40E_GLPRT_PRC127L(hw->port),
2927                             pf->offset_loaded, &os->rx_size_127,
2928                             &ns->rx_size_127);
2929         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2930                             I40E_GLPRT_PRC255L(hw->port),
2931                             pf->offset_loaded, &os->rx_size_255,
2932                             &ns->rx_size_255);
2933         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2934                             I40E_GLPRT_PRC511L(hw->port),
2935                             pf->offset_loaded, &os->rx_size_511,
2936                             &ns->rx_size_511);
2937         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2938                             I40E_GLPRT_PRC1023L(hw->port),
2939                             pf->offset_loaded, &os->rx_size_1023,
2940                             &ns->rx_size_1023);
2941         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2942                             I40E_GLPRT_PRC1522L(hw->port),
2943                             pf->offset_loaded, &os->rx_size_1522,
2944                             &ns->rx_size_1522);
2945         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2946                             I40E_GLPRT_PRC9522L(hw->port),
2947                             pf->offset_loaded, &os->rx_size_big,
2948                             &ns->rx_size_big);
2949         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2950                             pf->offset_loaded, &os->rx_undersize,
2951                             &ns->rx_undersize);
2952         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2953                             pf->offset_loaded, &os->rx_fragments,
2954                             &ns->rx_fragments);
2955         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2956                             pf->offset_loaded, &os->rx_oversize,
2957                             &ns->rx_oversize);
2958         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2959                             pf->offset_loaded, &os->rx_jabber,
2960                             &ns->rx_jabber);
2961         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2962                             I40E_GLPRT_PTC64L(hw->port),
2963                             pf->offset_loaded, &os->tx_size_64,
2964                             &ns->tx_size_64);
2965         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2966                             I40E_GLPRT_PTC127L(hw->port),
2967                             pf->offset_loaded, &os->tx_size_127,
2968                             &ns->tx_size_127);
2969         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2970                             I40E_GLPRT_PTC255L(hw->port),
2971                             pf->offset_loaded, &os->tx_size_255,
2972                             &ns->tx_size_255);
2973         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2974                             I40E_GLPRT_PTC511L(hw->port),
2975                             pf->offset_loaded, &os->tx_size_511,
2976                             &ns->tx_size_511);
2977         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2978                             I40E_GLPRT_PTC1023L(hw->port),
2979                             pf->offset_loaded, &os->tx_size_1023,
2980                             &ns->tx_size_1023);
2981         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2982                             I40E_GLPRT_PTC1522L(hw->port),
2983                             pf->offset_loaded, &os->tx_size_1522,
2984                             &ns->tx_size_1522);
2985         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2986                             I40E_GLPRT_PTC9522L(hw->port),
2987                             pf->offset_loaded, &os->tx_size_big,
2988                             &ns->tx_size_big);
2989         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2990                            pf->offset_loaded,
2991                            &os->fd_sb_match, &ns->fd_sb_match);
2992         /* GLPRT_MSPDC not supported */
2993         /* GLPRT_XEC not supported */
2994
2995         pf->offset_loaded = true;
2996
2997         if (pf->main_vsi)
2998                 i40e_update_vsi_stats(pf->main_vsi);
2999 }
3000
3001 /* Get all statistics of a port */
3002 static int
3003 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3004 {
3005         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3006         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3007         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3008         unsigned i;
3009
3010         /* call read registers - updates values, now write them to struct */
3011         i40e_read_stats_registers(pf, hw);
3012
3013         stats->ipackets = ns->eth.rx_unicast +
3014                         ns->eth.rx_multicast +
3015                         ns->eth.rx_broadcast -
3016                         ns->eth.rx_discards -
3017                         pf->main_vsi->eth_stats.rx_discards;
3018         stats->opackets = ns->eth.tx_unicast +
3019                         ns->eth.tx_multicast +
3020                         ns->eth.tx_broadcast;
3021         stats->ibytes   = ns->eth.rx_bytes;
3022         stats->obytes   = ns->eth.tx_bytes;
3023         stats->oerrors  = ns->eth.tx_errors +
3024                         pf->main_vsi->eth_stats.tx_errors;
3025
3026         /* Rx Errors */
3027         stats->imissed  = ns->eth.rx_discards +
3028                         pf->main_vsi->eth_stats.rx_discards;
3029         stats->ierrors  = ns->crc_errors +
3030                         ns->rx_length_errors + ns->rx_undersize +
3031                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3032
3033         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3034         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3035         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3036         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3037         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3038         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3039         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3040                     ns->eth.rx_unknown_protocol);
3041         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3042         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3043         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3044         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3045         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3046         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3047
3048         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3049                     ns->tx_dropped_link_down);
3050         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3051         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3052                     ns->illegal_bytes);
3053         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3054         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3055                     ns->mac_local_faults);
3056         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3057                     ns->mac_remote_faults);
3058         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3059                     ns->rx_length_errors);
3060         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3061         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3062         for (i = 0; i < 8; i++) {
3063                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3064                                 i, ns->priority_xon_rx[i]);
3065                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3066                                 i, ns->priority_xoff_rx[i]);
3067         }
3068         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3069         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3070         for (i = 0; i < 8; i++) {
3071                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3072                                 i, ns->priority_xon_tx[i]);
3073                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3074                                 i, ns->priority_xoff_tx[i]);
3075                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3076                                 i, ns->priority_xon_2_xoff[i]);
3077         }
3078         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3079         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3080         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3081         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3082         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3083         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3084         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3085         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3086         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3087         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3088         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3089         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3090         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3091         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3092         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3093         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3094         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3095         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3096         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3097                         ns->mac_short_packet_dropped);
3098         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3099                     ns->checksum_error);
3100         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3101         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3102         return 0;
3103 }
3104
3105 /* Reset the statistics */
3106 static void
3107 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3108 {
3109         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3110         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3111
3112         /* Mark PF and VSI stats to update the offset, aka "reset" */
3113         pf->offset_loaded = false;
3114         if (pf->main_vsi)
3115                 pf->main_vsi->offset_loaded = false;
3116
3117         /* read the stats, reading current register values into offset */
3118         i40e_read_stats_registers(pf, hw);
3119 }
3120
3121 static uint32_t
3122 i40e_xstats_calc_num(void)
3123 {
3124         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3125                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3126                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3127 }
3128
3129 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3130                                      struct rte_eth_xstat_name *xstats_names,
3131                                      __rte_unused unsigned limit)
3132 {
3133         unsigned count = 0;
3134         unsigned i, prio;
3135
3136         if (xstats_names == NULL)
3137                 return i40e_xstats_calc_num();
3138
3139         /* Note: limit checked in rte_eth_xstats_names() */
3140
3141         /* Get stats from i40e_eth_stats struct */
3142         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3143                 snprintf(xstats_names[count].name,
3144                          sizeof(xstats_names[count].name),
3145                          "%s", rte_i40e_stats_strings[i].name);
3146                 count++;
3147         }
3148
3149         /* Get individiual stats from i40e_hw_port struct */
3150         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3151                 snprintf(xstats_names[count].name,
3152                         sizeof(xstats_names[count].name),
3153                          "%s", rte_i40e_hw_port_strings[i].name);
3154                 count++;
3155         }
3156
3157         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3158                 for (prio = 0; prio < 8; prio++) {
3159                         snprintf(xstats_names[count].name,
3160                                  sizeof(xstats_names[count].name),
3161                                  "rx_priority%u_%s", prio,
3162                                  rte_i40e_rxq_prio_strings[i].name);
3163                         count++;
3164                 }
3165         }
3166
3167         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3168                 for (prio = 0; prio < 8; prio++) {
3169                         snprintf(xstats_names[count].name,
3170                                  sizeof(xstats_names[count].name),
3171                                  "tx_priority%u_%s", prio,
3172                                  rte_i40e_txq_prio_strings[i].name);
3173                         count++;
3174                 }
3175         }
3176         return count;
3177 }
3178
3179 static int
3180 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3181                     unsigned n)
3182 {
3183         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3184         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3185         unsigned i, count, prio;
3186         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3187
3188         count = i40e_xstats_calc_num();
3189         if (n < count)
3190                 return count;
3191
3192         i40e_read_stats_registers(pf, hw);
3193
3194         if (xstats == NULL)
3195                 return 0;
3196
3197         count = 0;
3198
3199         /* Get stats from i40e_eth_stats struct */
3200         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3201                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3202                         rte_i40e_stats_strings[i].offset);
3203                 xstats[count].id = count;
3204                 count++;
3205         }
3206
3207         /* Get individiual stats from i40e_hw_port struct */
3208         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3209                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3210                         rte_i40e_hw_port_strings[i].offset);
3211                 xstats[count].id = count;
3212                 count++;
3213         }
3214
3215         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3216                 for (prio = 0; prio < 8; prio++) {
3217                         xstats[count].value =
3218                                 *(uint64_t *)(((char *)hw_stats) +
3219                                 rte_i40e_rxq_prio_strings[i].offset +
3220                                 (sizeof(uint64_t) * prio));
3221                         xstats[count].id = count;
3222                         count++;
3223                 }
3224         }
3225
3226         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3227                 for (prio = 0; prio < 8; prio++) {
3228                         xstats[count].value =
3229                                 *(uint64_t *)(((char *)hw_stats) +
3230                                 rte_i40e_txq_prio_strings[i].offset +
3231                                 (sizeof(uint64_t) * prio));
3232                         xstats[count].id = count;
3233                         count++;
3234                 }
3235         }
3236
3237         return count;
3238 }
3239
3240 static int
3241 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3242                                  __rte_unused uint16_t queue_id,
3243                                  __rte_unused uint8_t stat_idx,
3244                                  __rte_unused uint8_t is_rx)
3245 {
3246         PMD_INIT_FUNC_TRACE();
3247
3248         return -ENOSYS;
3249 }
3250
3251 static int
3252 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3253 {
3254         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3255         u32 full_ver;
3256         u8 ver, patch;
3257         u16 build;
3258         int ret;
3259
3260         full_ver = hw->nvm.oem_ver;
3261         ver = (u8)(full_ver >> 24);
3262         build = (u16)((full_ver >> 8) & 0xffff);
3263         patch = (u8)(full_ver & 0xff);
3264
3265         ret = snprintf(fw_version, fw_size,
3266                  "%d.%d%d 0x%08x %d.%d.%d",
3267                  ((hw->nvm.version >> 12) & 0xf),
3268                  ((hw->nvm.version >> 4) & 0xff),
3269                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3270                  ver, build, patch);
3271
3272         ret += 1; /* add the size of '\0' */
3273         if (fw_size < (u32)ret)
3274                 return ret;
3275         else
3276                 return 0;
3277 }
3278
3279 static void
3280 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3281 {
3282         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3283         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3284         struct i40e_vsi *vsi = pf->main_vsi;
3285         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3286
3287         dev_info->max_rx_queues = vsi->nb_qps;
3288         dev_info->max_tx_queues = vsi->nb_qps;
3289         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3290         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3291         dev_info->max_mac_addrs = vsi->max_macaddrs;
3292         dev_info->max_vfs = pci_dev->max_vfs;
3293         dev_info->rx_queue_offload_capa = 0;
3294         dev_info->rx_offload_capa =
3295                 DEV_RX_OFFLOAD_VLAN_STRIP |
3296                 DEV_RX_OFFLOAD_QINQ_STRIP |
3297                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3298                 DEV_RX_OFFLOAD_UDP_CKSUM |
3299                 DEV_RX_OFFLOAD_TCP_CKSUM |
3300                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3301                 DEV_RX_OFFLOAD_CRC_STRIP |
3302                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3303                 DEV_RX_OFFLOAD_VLAN_FILTER |
3304                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3305
3306         dev_info->tx_queue_offload_capa = 0;
3307         dev_info->tx_offload_capa =
3308                 DEV_TX_OFFLOAD_VLAN_INSERT |
3309                 DEV_TX_OFFLOAD_QINQ_INSERT |
3310                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3311                 DEV_TX_OFFLOAD_UDP_CKSUM |
3312                 DEV_TX_OFFLOAD_TCP_CKSUM |
3313                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3314                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3315                 DEV_TX_OFFLOAD_TCP_TSO |
3316                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3317                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3318                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3319                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3320         dev_info->dev_capa =
3321                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3322                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3323
3324         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3325                                                 sizeof(uint32_t);
3326         dev_info->reta_size = pf->hash_lut_size;
3327         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3328
3329         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3330                 .rx_thresh = {
3331                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3332                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3333                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3334                 },
3335                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3336                 .rx_drop_en = 0,
3337                 .offloads = 0,
3338         };
3339
3340         dev_info->default_txconf = (struct rte_eth_txconf) {
3341                 .tx_thresh = {
3342                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3343                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3344                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3345                 },
3346                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3347                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3348                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3349                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3350         };
3351
3352         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3353                 .nb_max = I40E_MAX_RING_DESC,
3354                 .nb_min = I40E_MIN_RING_DESC,
3355                 .nb_align = I40E_ALIGN_RING_DESC,
3356         };
3357
3358         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3359                 .nb_max = I40E_MAX_RING_DESC,
3360                 .nb_min = I40E_MIN_RING_DESC,
3361                 .nb_align = I40E_ALIGN_RING_DESC,
3362                 .nb_seg_max = I40E_TX_MAX_SEG,
3363                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3364         };
3365
3366         if (pf->flags & I40E_FLAG_VMDQ) {
3367                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3368                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3369                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3370                                                 pf->max_nb_vmdq_vsi;
3371                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3372                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3373                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3374         }
3375
3376         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3377                 /* For XL710 */
3378                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3379                 dev_info->default_rxportconf.nb_queues = 2;
3380                 dev_info->default_txportconf.nb_queues = 2;
3381                 if (dev->data->nb_rx_queues == 1)
3382                         dev_info->default_rxportconf.ring_size = 2048;
3383                 else
3384                         dev_info->default_rxportconf.ring_size = 1024;
3385                 if (dev->data->nb_tx_queues == 1)
3386                         dev_info->default_txportconf.ring_size = 1024;
3387                 else
3388                         dev_info->default_txportconf.ring_size = 512;
3389
3390         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3391                 /* For XXV710 */
3392                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3393                 dev_info->default_rxportconf.nb_queues = 1;
3394                 dev_info->default_txportconf.nb_queues = 1;
3395                 dev_info->default_rxportconf.ring_size = 256;
3396                 dev_info->default_txportconf.ring_size = 256;
3397         } else {
3398                 /* For X710 */
3399                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3400                 dev_info->default_rxportconf.nb_queues = 1;
3401                 dev_info->default_txportconf.nb_queues = 1;
3402                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3403                         dev_info->default_rxportconf.ring_size = 512;
3404                         dev_info->default_txportconf.ring_size = 256;
3405                 } else {
3406                         dev_info->default_rxportconf.ring_size = 256;
3407                         dev_info->default_txportconf.ring_size = 256;
3408                 }
3409         }
3410         dev_info->default_rxportconf.burst_size = 32;
3411         dev_info->default_txportconf.burst_size = 32;
3412 }
3413
3414 static int
3415 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3416 {
3417         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3418         struct i40e_vsi *vsi = pf->main_vsi;
3419         PMD_INIT_FUNC_TRACE();
3420
3421         if (on)
3422                 return i40e_vsi_add_vlan(vsi, vlan_id);
3423         else
3424                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3425 }
3426
3427 static int
3428 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3429                                 enum rte_vlan_type vlan_type,
3430                                 uint16_t tpid, int qinq)
3431 {
3432         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3433         uint64_t reg_r = 0;
3434         uint64_t reg_w = 0;
3435         uint16_t reg_id = 3;
3436         int ret;
3437
3438         if (qinq) {
3439                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3440                         reg_id = 2;
3441         }
3442
3443         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3444                                           &reg_r, NULL);
3445         if (ret != I40E_SUCCESS) {
3446                 PMD_DRV_LOG(ERR,
3447                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3448                            reg_id);
3449                 return -EIO;
3450         }
3451         PMD_DRV_LOG(DEBUG,
3452                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3453                     reg_id, reg_r);
3454
3455         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3456         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3457         if (reg_r == reg_w) {
3458                 PMD_DRV_LOG(DEBUG, "No need to write");
3459                 return 0;
3460         }
3461
3462         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3463                                            reg_w, NULL);
3464         if (ret != I40E_SUCCESS) {
3465                 PMD_DRV_LOG(ERR,
3466                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3467                             reg_id);
3468                 return -EIO;
3469         }
3470         PMD_DRV_LOG(DEBUG,
3471                     "Global register 0x%08x is changed with value 0x%08x",
3472                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3473
3474         return 0;
3475 }
3476
3477 static int
3478 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3479                    enum rte_vlan_type vlan_type,
3480                    uint16_t tpid)
3481 {
3482         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3483         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3484         int qinq = dev->data->dev_conf.rxmode.offloads &
3485                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3486         int ret = 0;
3487
3488         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3489              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3490             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3491                 PMD_DRV_LOG(ERR,
3492                             "Unsupported vlan type.");
3493                 return -EINVAL;
3494         }
3495
3496         if (pf->support_multi_driver) {
3497                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3498                 return -ENOTSUP;
3499         }
3500
3501         /* 802.1ad frames ability is added in NVM API 1.7*/
3502         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3503                 if (qinq) {
3504                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3505                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3506                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3507                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3508                 } else {
3509                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3510                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3511                 }
3512                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3513                 if (ret != I40E_SUCCESS) {
3514                         PMD_DRV_LOG(ERR,
3515                                     "Set switch config failed aq_err: %d",
3516                                     hw->aq.asq_last_status);
3517                         ret = -EIO;
3518                 }
3519         } else
3520                 /* If NVM API < 1.7, keep the register setting */
3521                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3522                                                       tpid, qinq);
3523         i40e_global_cfg_warning(I40E_WARNING_TPID);
3524
3525         return ret;
3526 }
3527
3528 static int
3529 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3530 {
3531         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3532         struct i40e_vsi *vsi = pf->main_vsi;
3533         struct rte_eth_rxmode *rxmode;
3534
3535         rxmode = &dev->data->dev_conf.rxmode;
3536         if (mask & ETH_VLAN_FILTER_MASK) {
3537                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3538                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3539                 else
3540                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3541         }
3542
3543         if (mask & ETH_VLAN_STRIP_MASK) {
3544                 /* Enable or disable VLAN stripping */
3545                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3546                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3547                 else
3548                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3549         }
3550
3551         if (mask & ETH_VLAN_EXTEND_MASK) {
3552                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3553                         i40e_vsi_config_double_vlan(vsi, TRUE);
3554                         /* Set global registers with default ethertype. */
3555                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3556                                            ETHER_TYPE_VLAN);
3557                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3558                                            ETHER_TYPE_VLAN);
3559                 }
3560                 else
3561                         i40e_vsi_config_double_vlan(vsi, FALSE);
3562         }
3563
3564         return 0;
3565 }
3566
3567 static void
3568 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3569                           __rte_unused uint16_t queue,
3570                           __rte_unused int on)
3571 {
3572         PMD_INIT_FUNC_TRACE();
3573 }
3574
3575 static int
3576 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3577 {
3578         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3579         struct i40e_vsi *vsi = pf->main_vsi;
3580         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3581         struct i40e_vsi_vlan_pvid_info info;
3582
3583         memset(&info, 0, sizeof(info));
3584         info.on = on;
3585         if (info.on)
3586                 info.config.pvid = pvid;
3587         else {
3588                 info.config.reject.tagged =
3589                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3590                 info.config.reject.untagged =
3591                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3592         }
3593
3594         return i40e_vsi_vlan_pvid_set(vsi, &info);
3595 }
3596
3597 static int
3598 i40e_dev_led_on(struct rte_eth_dev *dev)
3599 {
3600         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601         uint32_t mode = i40e_led_get(hw);
3602
3603         if (mode == 0)
3604                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3605
3606         return 0;
3607 }
3608
3609 static int
3610 i40e_dev_led_off(struct rte_eth_dev *dev)
3611 {
3612         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3613         uint32_t mode = i40e_led_get(hw);
3614
3615         if (mode != 0)
3616                 i40e_led_set(hw, 0, false);
3617
3618         return 0;
3619 }
3620
3621 static int
3622 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3623 {
3624         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3625         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3626
3627         fc_conf->pause_time = pf->fc_conf.pause_time;
3628
3629         /* read out from register, in case they are modified by other port */
3630         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3631                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3632         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3633                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3634
3635         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3636         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3637
3638          /* Return current mode according to actual setting*/
3639         switch (hw->fc.current_mode) {
3640         case I40E_FC_FULL:
3641                 fc_conf->mode = RTE_FC_FULL;
3642                 break;
3643         case I40E_FC_TX_PAUSE:
3644                 fc_conf->mode = RTE_FC_TX_PAUSE;
3645                 break;
3646         case I40E_FC_RX_PAUSE:
3647                 fc_conf->mode = RTE_FC_RX_PAUSE;
3648                 break;
3649         case I40E_FC_NONE:
3650         default:
3651                 fc_conf->mode = RTE_FC_NONE;
3652         };
3653
3654         return 0;
3655 }
3656
3657 static int
3658 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3659 {
3660         uint32_t mflcn_reg, fctrl_reg, reg;
3661         uint32_t max_high_water;
3662         uint8_t i, aq_failure;
3663         int err;
3664         struct i40e_hw *hw;
3665         struct i40e_pf *pf;
3666         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3667                 [RTE_FC_NONE] = I40E_FC_NONE,
3668                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3669                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3670                 [RTE_FC_FULL] = I40E_FC_FULL
3671         };
3672
3673         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3674
3675         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3676         if ((fc_conf->high_water > max_high_water) ||
3677                         (fc_conf->high_water < fc_conf->low_water)) {
3678                 PMD_INIT_LOG(ERR,
3679                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3680                         max_high_water);
3681                 return -EINVAL;
3682         }
3683
3684         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3685         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3686         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3687
3688         pf->fc_conf.pause_time = fc_conf->pause_time;
3689         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3690         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3691
3692         PMD_INIT_FUNC_TRACE();
3693
3694         /* All the link flow control related enable/disable register
3695          * configuration is handle by the F/W
3696          */
3697         err = i40e_set_fc(hw, &aq_failure, true);
3698         if (err < 0)
3699                 return -ENOSYS;
3700
3701         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3702                 /* Configure flow control refresh threshold,
3703                  * the value for stat_tx_pause_refresh_timer[8]
3704                  * is used for global pause operation.
3705                  */
3706
3707                 I40E_WRITE_REG(hw,
3708                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3709                                pf->fc_conf.pause_time);
3710
3711                 /* configure the timer value included in transmitted pause
3712                  * frame,
3713                  * the value for stat_tx_pause_quanta[8] is used for global
3714                  * pause operation
3715                  */
3716                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3717                                pf->fc_conf.pause_time);
3718
3719                 fctrl_reg = I40E_READ_REG(hw,
3720                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3721
3722                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3723                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3724                 else
3725                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3726
3727                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3728                                fctrl_reg);
3729         } else {
3730                 /* Configure pause time (2 TCs per register) */
3731                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3732                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3733                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3734
3735                 /* Configure flow control refresh threshold value */
3736                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3737                                pf->fc_conf.pause_time / 2);
3738
3739                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3740
3741                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3742                  *depending on configuration
3743                  */
3744                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3745                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3746                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3747                 } else {
3748                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3749                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3750                 }
3751
3752                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3753         }
3754
3755         if (!pf->support_multi_driver) {
3756                 /* config water marker both based on the packets and bytes */
3757                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3758                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3759                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3760                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3761                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3762                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3763                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3764                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3765                                   << I40E_KILOSHIFT);
3766                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3767                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3768                                    << I40E_KILOSHIFT);
3769                 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3770         } else {
3771                 PMD_DRV_LOG(ERR,
3772                             "Water marker configuration is not supported.");
3773         }
3774
3775         I40E_WRITE_FLUSH(hw);
3776
3777         return 0;
3778 }
3779
3780 static int
3781 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3782                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3783 {
3784         PMD_INIT_FUNC_TRACE();
3785
3786         return -ENOSYS;
3787 }
3788
3789 /* Add a MAC address, and update filters */
3790 static int
3791 i40e_macaddr_add(struct rte_eth_dev *dev,
3792                  struct ether_addr *mac_addr,
3793                  __rte_unused uint32_t index,
3794                  uint32_t pool)
3795 {
3796         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3797         struct i40e_mac_filter_info mac_filter;
3798         struct i40e_vsi *vsi;
3799         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3800         int ret;
3801
3802         /* If VMDQ not enabled or configured, return */
3803         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3804                           !pf->nb_cfg_vmdq_vsi)) {
3805                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3806                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3807                         pool);
3808                 return -ENOTSUP;
3809         }
3810
3811         if (pool > pf->nb_cfg_vmdq_vsi) {
3812                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3813                                 pool, pf->nb_cfg_vmdq_vsi);
3814                 return -EINVAL;
3815         }
3816
3817         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3818         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3819                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3820         else
3821                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3822
3823         if (pool == 0)
3824                 vsi = pf->main_vsi;
3825         else
3826                 vsi = pf->vmdq[pool - 1].vsi;
3827
3828         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3829         if (ret != I40E_SUCCESS) {
3830                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3831                 return -ENODEV;
3832         }
3833         return 0;
3834 }
3835
3836 /* Remove a MAC address, and update filters */
3837 static void
3838 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3839 {
3840         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3841         struct i40e_vsi *vsi;
3842         struct rte_eth_dev_data *data = dev->data;
3843         struct ether_addr *macaddr;
3844         int ret;
3845         uint32_t i;
3846         uint64_t pool_sel;
3847
3848         macaddr = &(data->mac_addrs[index]);
3849
3850         pool_sel = dev->data->mac_pool_sel[index];
3851
3852         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3853                 if (pool_sel & (1ULL << i)) {
3854                         if (i == 0)
3855                                 vsi = pf->main_vsi;
3856                         else {
3857                                 /* No VMDQ pool enabled or configured */
3858                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3859                                         (i > pf->nb_cfg_vmdq_vsi)) {
3860                                         PMD_DRV_LOG(ERR,
3861                                                 "No VMDQ pool enabled/configured");
3862                                         return;
3863                                 }
3864                                 vsi = pf->vmdq[i - 1].vsi;
3865                         }
3866                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3867
3868                         if (ret) {
3869                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3870                                 return;
3871                         }
3872                 }
3873         }
3874 }
3875
3876 /* Set perfect match or hash match of MAC and VLAN for a VF */
3877 static int
3878 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3879                  struct rte_eth_mac_filter *filter,
3880                  bool add)
3881 {
3882         struct i40e_hw *hw;
3883         struct i40e_mac_filter_info mac_filter;
3884         struct ether_addr old_mac;
3885         struct ether_addr *new_mac;
3886         struct i40e_pf_vf *vf = NULL;
3887         uint16_t vf_id;
3888         int ret;
3889
3890         if (pf == NULL) {
3891                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3892                 return -EINVAL;
3893         }
3894         hw = I40E_PF_TO_HW(pf);
3895
3896         if (filter == NULL) {
3897                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3898                 return -EINVAL;
3899         }
3900
3901         new_mac = &filter->mac_addr;
3902
3903         if (is_zero_ether_addr(new_mac)) {
3904                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3905                 return -EINVAL;
3906         }
3907
3908         vf_id = filter->dst_id;
3909
3910         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3911                 PMD_DRV_LOG(ERR, "Invalid argument.");
3912                 return -EINVAL;
3913         }
3914         vf = &pf->vfs[vf_id];
3915
3916         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3917                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3918                 return -EINVAL;
3919         }
3920
3921         if (add) {
3922                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3923                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3924                                 ETHER_ADDR_LEN);
3925                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3926                                  ETHER_ADDR_LEN);
3927
3928                 mac_filter.filter_type = filter->filter_type;
3929                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3930                 if (ret != I40E_SUCCESS) {
3931                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3932                         return -1;
3933                 }
3934                 ether_addr_copy(new_mac, &pf->dev_addr);
3935         } else {
3936                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3937                                 ETHER_ADDR_LEN);
3938                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3939                 if (ret != I40E_SUCCESS) {
3940                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3941                         return -1;
3942                 }
3943
3944                 /* Clear device address as it has been removed */
3945                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3946                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3947         }
3948
3949         return 0;
3950 }
3951
3952 /* MAC filter handle */
3953 static int
3954 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3955                 void *arg)
3956 {
3957         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3958         struct rte_eth_mac_filter *filter;
3959         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3960         int ret = I40E_NOT_SUPPORTED;
3961
3962         filter = (struct rte_eth_mac_filter *)(arg);
3963
3964         switch (filter_op) {
3965         case RTE_ETH_FILTER_NOP:
3966                 ret = I40E_SUCCESS;
3967                 break;
3968         case RTE_ETH_FILTER_ADD:
3969                 i40e_pf_disable_irq0(hw);
3970                 if (filter->is_vf)
3971                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3972                 i40e_pf_enable_irq0(hw);
3973                 break;
3974         case RTE_ETH_FILTER_DELETE:
3975                 i40e_pf_disable_irq0(hw);
3976                 if (filter->is_vf)
3977                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3978                 i40e_pf_enable_irq0(hw);
3979                 break;
3980         default:
3981                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3982                 ret = I40E_ERR_PARAM;
3983                 break;
3984         }
3985
3986         return ret;
3987 }
3988
3989 static int
3990 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3991 {
3992         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3993         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3994         uint32_t reg;
3995         int ret;
3996
3997         if (!lut)
3998                 return -EINVAL;
3999
4000         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4001                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4002                                           lut, lut_size);
4003                 if (ret) {
4004                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4005                         return ret;
4006                 }
4007         } else {
4008                 uint32_t *lut_dw = (uint32_t *)lut;
4009                 uint16_t i, lut_size_dw = lut_size / 4;
4010
4011                 if (vsi->type == I40E_VSI_SRIOV) {
4012                         for (i = 0; i <= lut_size_dw; i++) {
4013                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4014                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4015                         }
4016                 } else {
4017                         for (i = 0; i < lut_size_dw; i++)
4018                                 lut_dw[i] = I40E_READ_REG(hw,
4019                                                           I40E_PFQF_HLUT(i));
4020                 }
4021         }
4022
4023         return 0;
4024 }
4025
4026 int
4027 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4028 {
4029         struct i40e_pf *pf;
4030         struct i40e_hw *hw;
4031         int ret;
4032
4033         if (!vsi || !lut)
4034                 return -EINVAL;
4035
4036         pf = I40E_VSI_TO_PF(vsi);
4037         hw = I40E_VSI_TO_HW(vsi);
4038
4039         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4040                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4041                                           lut, lut_size);
4042                 if (ret) {
4043                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4044                         return ret;
4045                 }
4046         } else {
4047                 uint32_t *lut_dw = (uint32_t *)lut;
4048                 uint16_t i, lut_size_dw = lut_size / 4;
4049
4050                 if (vsi->type == I40E_VSI_SRIOV) {
4051                         for (i = 0; i < lut_size_dw; i++)
4052                                 I40E_WRITE_REG(
4053                                         hw,
4054                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4055                                         lut_dw[i]);
4056                 } else {
4057                         for (i = 0; i < lut_size_dw; i++)
4058                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4059                                                lut_dw[i]);
4060                 }
4061                 I40E_WRITE_FLUSH(hw);
4062         }
4063
4064         return 0;
4065 }
4066
4067 static int
4068 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4069                          struct rte_eth_rss_reta_entry64 *reta_conf,
4070                          uint16_t reta_size)
4071 {
4072         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4073         uint16_t i, lut_size = pf->hash_lut_size;
4074         uint16_t idx, shift;
4075         uint8_t *lut;
4076         int ret;
4077
4078         if (reta_size != lut_size ||
4079                 reta_size > ETH_RSS_RETA_SIZE_512) {
4080                 PMD_DRV_LOG(ERR,
4081                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4082                         reta_size, lut_size);
4083                 return -EINVAL;
4084         }
4085
4086         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4087         if (!lut) {
4088                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4089                 return -ENOMEM;
4090         }
4091         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4092         if (ret)
4093                 goto out;
4094         for (i = 0; i < reta_size; i++) {
4095                 idx = i / RTE_RETA_GROUP_SIZE;
4096                 shift = i % RTE_RETA_GROUP_SIZE;
4097                 if (reta_conf[idx].mask & (1ULL << shift))
4098                         lut[i] = reta_conf[idx].reta[shift];
4099         }
4100         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4101
4102 out:
4103         rte_free(lut);
4104
4105         return ret;
4106 }
4107
4108 static int
4109 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4110                         struct rte_eth_rss_reta_entry64 *reta_conf,
4111                         uint16_t reta_size)
4112 {
4113         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4114         uint16_t i, lut_size = pf->hash_lut_size;
4115         uint16_t idx, shift;
4116         uint8_t *lut;
4117         int ret;
4118
4119         if (reta_size != lut_size ||
4120                 reta_size > ETH_RSS_RETA_SIZE_512) {
4121                 PMD_DRV_LOG(ERR,
4122                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4123                         reta_size, lut_size);
4124                 return -EINVAL;
4125         }
4126
4127         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4128         if (!lut) {
4129                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4130                 return -ENOMEM;
4131         }
4132
4133         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4134         if (ret)
4135                 goto out;
4136         for (i = 0; i < reta_size; i++) {
4137                 idx = i / RTE_RETA_GROUP_SIZE;
4138                 shift = i % RTE_RETA_GROUP_SIZE;
4139                 if (reta_conf[idx].mask & (1ULL << shift))
4140                         reta_conf[idx].reta[shift] = lut[i];
4141         }
4142
4143 out:
4144         rte_free(lut);
4145
4146         return ret;
4147 }
4148
4149 /**
4150  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4151  * @hw:   pointer to the HW structure
4152  * @mem:  pointer to mem struct to fill out
4153  * @size: size of memory requested
4154  * @alignment: what to align the allocation to
4155  **/
4156 enum i40e_status_code
4157 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4158                         struct i40e_dma_mem *mem,
4159                         u64 size,
4160                         u32 alignment)
4161 {
4162         const struct rte_memzone *mz = NULL;
4163         char z_name[RTE_MEMZONE_NAMESIZE];
4164
4165         if (!mem)
4166                 return I40E_ERR_PARAM;
4167
4168         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4169         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4170                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4171         if (!mz)
4172                 return I40E_ERR_NO_MEMORY;
4173
4174         mem->size = size;
4175         mem->va = mz->addr;
4176         mem->pa = mz->iova;
4177         mem->zone = (const void *)mz;
4178         PMD_DRV_LOG(DEBUG,
4179                 "memzone %s allocated with physical address: %"PRIu64,
4180                 mz->name, mem->pa);
4181
4182         return I40E_SUCCESS;
4183 }
4184
4185 /**
4186  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4187  * @hw:   pointer to the HW structure
4188  * @mem:  ptr to mem struct to free
4189  **/
4190 enum i40e_status_code
4191 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4192                     struct i40e_dma_mem *mem)
4193 {
4194         if (!mem)
4195                 return I40E_ERR_PARAM;
4196
4197         PMD_DRV_LOG(DEBUG,
4198                 "memzone %s to be freed with physical address: %"PRIu64,
4199                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4200         rte_memzone_free((const struct rte_memzone *)mem->zone);
4201         mem->zone = NULL;
4202         mem->va = NULL;
4203         mem->pa = (u64)0;
4204
4205         return I40E_SUCCESS;
4206 }
4207
4208 /**
4209  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4210  * @hw:   pointer to the HW structure
4211  * @mem:  pointer to mem struct to fill out
4212  * @size: size of memory requested
4213  **/
4214 enum i40e_status_code
4215 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4216                          struct i40e_virt_mem *mem,
4217                          u32 size)
4218 {
4219         if (!mem)
4220                 return I40E_ERR_PARAM;
4221
4222         mem->size = size;
4223         mem->va = rte_zmalloc("i40e", size, 0);
4224
4225         if (mem->va)
4226                 return I40E_SUCCESS;
4227         else
4228                 return I40E_ERR_NO_MEMORY;
4229 }
4230
4231 /**
4232  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4233  * @hw:   pointer to the HW structure
4234  * @mem:  pointer to mem struct to free
4235  **/
4236 enum i40e_status_code
4237 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4238                      struct i40e_virt_mem *mem)
4239 {
4240         if (!mem)
4241                 return I40E_ERR_PARAM;
4242
4243         rte_free(mem->va);
4244         mem->va = NULL;
4245
4246         return I40E_SUCCESS;
4247 }
4248
4249 void
4250 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4251 {
4252         rte_spinlock_init(&sp->spinlock);
4253 }
4254
4255 void
4256 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4257 {
4258         rte_spinlock_lock(&sp->spinlock);
4259 }
4260
4261 void
4262 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4263 {
4264         rte_spinlock_unlock(&sp->spinlock);
4265 }
4266
4267 void
4268 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4269 {
4270         return;
4271 }
4272
4273 /**
4274  * Get the hardware capabilities, which will be parsed
4275  * and saved into struct i40e_hw.
4276  */
4277 static int
4278 i40e_get_cap(struct i40e_hw *hw)
4279 {
4280         struct i40e_aqc_list_capabilities_element_resp *buf;
4281         uint16_t len, size = 0;
4282         int ret;
4283
4284         /* Calculate a huge enough buff for saving response data temporarily */
4285         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4286                                                 I40E_MAX_CAP_ELE_NUM;
4287         buf = rte_zmalloc("i40e", len, 0);
4288         if (!buf) {
4289                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4290                 return I40E_ERR_NO_MEMORY;
4291         }
4292
4293         /* Get, parse the capabilities and save it to hw */
4294         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4295                         i40e_aqc_opc_list_func_capabilities, NULL);
4296         if (ret != I40E_SUCCESS)
4297                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4298
4299         /* Free the temporary buffer after being used */
4300         rte_free(buf);
4301
4302         return ret;
4303 }
4304
4305 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4306 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
4307
4308 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4309                 const char *value,
4310                 void *opaque)
4311 {
4312         struct i40e_pf *pf;
4313         unsigned long num;
4314         char *end;
4315
4316         pf = (struct i40e_pf *)opaque;
4317         RTE_SET_USED(key);
4318
4319         errno = 0;
4320         num = strtoul(value, &end, 0);
4321         if (errno != 0 || end == value || *end != 0) {
4322                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4323                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4324                 return -(EINVAL);
4325         }
4326
4327         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4328                 pf->vf_nb_qp_max = (uint16_t)num;
4329         else
4330                 /* here return 0 to make next valid same argument work */
4331                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4332                             "power of 2 and equal or less than 16 !, Now it is "
4333                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4334
4335         return 0;
4336 }
4337
4338 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4339 {
4340         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4341         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4342         struct rte_kvargs *kvlist;
4343
4344         /* set default queue number per VF as 4 */
4345         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4346
4347         if (dev->device->devargs == NULL)
4348                 return 0;
4349
4350         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4351         if (kvlist == NULL)
4352                 return -(EINVAL);
4353
4354         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4355                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4356                             "the first invalid or last valid one is used !",
4357                             QUEUE_NUM_PER_VF_ARG);
4358
4359         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4360                            i40e_pf_parse_vf_queue_number_handler, pf);
4361
4362         rte_kvargs_free(kvlist);
4363
4364         return 0;
4365 }
4366
4367 static int
4368 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4369 {
4370         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4371         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4372         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4373         uint16_t qp_count = 0, vsi_count = 0;
4374
4375         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4376                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4377                 return -EINVAL;
4378         }
4379
4380         i40e_pf_config_vf_rxq_number(dev);
4381
4382         /* Add the parameter init for LFC */
4383         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4384         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4385         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4386
4387         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4388         pf->max_num_vsi = hw->func_caps.num_vsis;
4389         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4390         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4391
4392         /* FDir queue/VSI allocation */
4393         pf->fdir_qp_offset = 0;
4394         if (hw->func_caps.fd) {
4395                 pf->flags |= I40E_FLAG_FDIR;
4396                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4397         } else {
4398                 pf->fdir_nb_qps = 0;
4399         }
4400         qp_count += pf->fdir_nb_qps;
4401         vsi_count += 1;
4402
4403         /* LAN queue/VSI allocation */
4404         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4405         if (!hw->func_caps.rss) {
4406                 pf->lan_nb_qps = 1;
4407         } else {
4408                 pf->flags |= I40E_FLAG_RSS;
4409                 if (hw->mac.type == I40E_MAC_X722)
4410                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4411                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4412         }
4413         qp_count += pf->lan_nb_qps;
4414         vsi_count += 1;
4415
4416         /* VF queue/VSI allocation */
4417         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4418         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4419                 pf->flags |= I40E_FLAG_SRIOV;
4420                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4421                 pf->vf_num = pci_dev->max_vfs;
4422                 PMD_DRV_LOG(DEBUG,
4423                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4424                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4425         } else {
4426                 pf->vf_nb_qps = 0;
4427                 pf->vf_num = 0;
4428         }
4429         qp_count += pf->vf_nb_qps * pf->vf_num;
4430         vsi_count += pf->vf_num;
4431
4432         /* VMDq queue/VSI allocation */
4433         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4434         pf->vmdq_nb_qps = 0;
4435         pf->max_nb_vmdq_vsi = 0;
4436         if (hw->func_caps.vmdq) {
4437                 if (qp_count < hw->func_caps.num_tx_qp &&
4438                         vsi_count < hw->func_caps.num_vsis) {
4439                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4440                                 qp_count) / pf->vmdq_nb_qp_max;
4441
4442                         /* Limit the maximum number of VMDq vsi to the maximum
4443                          * ethdev can support
4444                          */
4445                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4446                                 hw->func_caps.num_vsis - vsi_count);
4447                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4448                                 ETH_64_POOLS);
4449                         if (pf->max_nb_vmdq_vsi) {
4450                                 pf->flags |= I40E_FLAG_VMDQ;
4451                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4452                                 PMD_DRV_LOG(DEBUG,
4453                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4454                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4455                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4456                         } else {
4457                                 PMD_DRV_LOG(INFO,
4458                                         "No enough queues left for VMDq");
4459                         }
4460                 } else {
4461                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4462                 }
4463         }
4464         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4465         vsi_count += pf->max_nb_vmdq_vsi;
4466
4467         if (hw->func_caps.dcb)
4468                 pf->flags |= I40E_FLAG_DCB;
4469
4470         if (qp_count > hw->func_caps.num_tx_qp) {
4471                 PMD_DRV_LOG(ERR,
4472                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4473                         qp_count, hw->func_caps.num_tx_qp);
4474                 return -EINVAL;
4475         }
4476         if (vsi_count > hw->func_caps.num_vsis) {
4477                 PMD_DRV_LOG(ERR,
4478                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4479                         vsi_count, hw->func_caps.num_vsis);
4480                 return -EINVAL;
4481         }
4482
4483         return 0;
4484 }
4485
4486 static int
4487 i40e_pf_get_switch_config(struct i40e_pf *pf)
4488 {
4489         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4490         struct i40e_aqc_get_switch_config_resp *switch_config;
4491         struct i40e_aqc_switch_config_element_resp *element;
4492         uint16_t start_seid = 0, num_reported;
4493         int ret;
4494
4495         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4496                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4497         if (!switch_config) {
4498                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4499                 return -ENOMEM;
4500         }
4501
4502         /* Get the switch configurations */
4503         ret = i40e_aq_get_switch_config(hw, switch_config,
4504                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4505         if (ret != I40E_SUCCESS) {
4506                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4507                 goto fail;
4508         }
4509         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4510         if (num_reported != 1) { /* The number should be 1 */
4511                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4512                 goto fail;
4513         }
4514
4515         /* Parse the switch configuration elements */
4516         element = &(switch_config->element[0]);
4517         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4518                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4519                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4520         } else
4521                 PMD_DRV_LOG(INFO, "Unknown element type");
4522
4523 fail:
4524         rte_free(switch_config);
4525
4526         return ret;
4527 }
4528
4529 static int
4530 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4531                         uint32_t num)
4532 {
4533         struct pool_entry *entry;
4534
4535         if (pool == NULL || num == 0)
4536                 return -EINVAL;
4537
4538         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4539         if (entry == NULL) {
4540                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4541                 return -ENOMEM;
4542         }
4543
4544         /* queue heap initialize */
4545         pool->num_free = num;
4546         pool->num_alloc = 0;
4547         pool->base = base;
4548         LIST_INIT(&pool->alloc_list);
4549         LIST_INIT(&pool->free_list);
4550
4551         /* Initialize element  */
4552         entry->base = 0;
4553         entry->len = num;
4554
4555         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4556         return 0;
4557 }
4558
4559 static void
4560 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4561 {
4562         struct pool_entry *entry, *next_entry;
4563
4564         if (pool == NULL)
4565                 return;
4566
4567         for (entry = LIST_FIRST(&pool->alloc_list);
4568                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4569                         entry = next_entry) {
4570                 LIST_REMOVE(entry, next);
4571                 rte_free(entry);
4572         }
4573
4574         for (entry = LIST_FIRST(&pool->free_list);
4575                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4576                         entry = next_entry) {
4577                 LIST_REMOVE(entry, next);
4578                 rte_free(entry);
4579         }
4580
4581         pool->num_free = 0;
4582         pool->num_alloc = 0;
4583         pool->base = 0;
4584         LIST_INIT(&pool->alloc_list);
4585         LIST_INIT(&pool->free_list);
4586 }
4587
4588 static int
4589 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4590                        uint32_t base)
4591 {
4592         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4593         uint32_t pool_offset;
4594         int insert;
4595
4596         if (pool == NULL) {
4597                 PMD_DRV_LOG(ERR, "Invalid parameter");
4598                 return -EINVAL;
4599         }
4600
4601         pool_offset = base - pool->base;
4602         /* Lookup in alloc list */
4603         LIST_FOREACH(entry, &pool->alloc_list, next) {
4604                 if (entry->base == pool_offset) {
4605                         valid_entry = entry;
4606                         LIST_REMOVE(entry, next);
4607                         break;
4608                 }
4609         }
4610
4611         /* Not find, return */
4612         if (valid_entry == NULL) {
4613                 PMD_DRV_LOG(ERR, "Failed to find entry");
4614                 return -EINVAL;
4615         }
4616
4617         /**
4618          * Found it, move it to free list  and try to merge.
4619          * In order to make merge easier, always sort it by qbase.
4620          * Find adjacent prev and last entries.
4621          */
4622         prev = next = NULL;
4623         LIST_FOREACH(entry, &pool->free_list, next) {
4624                 if (entry->base > valid_entry->base) {
4625                         next = entry;
4626                         break;
4627                 }
4628                 prev = entry;
4629         }
4630
4631         insert = 0;
4632         /* Try to merge with next one*/
4633         if (next != NULL) {
4634                 /* Merge with next one */
4635                 if (valid_entry->base + valid_entry->len == next->base) {
4636                         next->base = valid_entry->base;
4637                         next->len += valid_entry->len;
4638                         rte_free(valid_entry);
4639                         valid_entry = next;
4640                         insert = 1;
4641                 }
4642         }
4643
4644         if (prev != NULL) {
4645                 /* Merge with previous one */
4646                 if (prev->base + prev->len == valid_entry->base) {
4647                         prev->len += valid_entry->len;
4648                         /* If it merge with next one, remove next node */
4649                         if (insert == 1) {
4650                                 LIST_REMOVE(valid_entry, next);
4651                                 rte_free(valid_entry);
4652                         } else {
4653                                 rte_free(valid_entry);
4654                                 insert = 1;
4655                         }
4656                 }
4657         }
4658
4659         /* Not find any entry to merge, insert */
4660         if (insert == 0) {
4661                 if (prev != NULL)
4662                         LIST_INSERT_AFTER(prev, valid_entry, next);
4663                 else if (next != NULL)
4664                         LIST_INSERT_BEFORE(next, valid_entry, next);
4665                 else /* It's empty list, insert to head */
4666                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4667         }
4668
4669         pool->num_free += valid_entry->len;
4670         pool->num_alloc -= valid_entry->len;
4671
4672         return 0;
4673 }
4674
4675 static int
4676 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4677                        uint16_t num)
4678 {
4679         struct pool_entry *entry, *valid_entry;
4680
4681         if (pool == NULL || num == 0) {
4682                 PMD_DRV_LOG(ERR, "Invalid parameter");
4683                 return -EINVAL;
4684         }
4685
4686         if (pool->num_free < num) {
4687                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4688                             num, pool->num_free);
4689                 return -ENOMEM;
4690         }
4691
4692         valid_entry = NULL;
4693         /* Lookup  in free list and find most fit one */
4694         LIST_FOREACH(entry, &pool->free_list, next) {
4695                 if (entry->len >= num) {
4696                         /* Find best one */
4697                         if (entry->len == num) {
4698                                 valid_entry = entry;
4699                                 break;
4700                         }
4701                         if (valid_entry == NULL || valid_entry->len > entry->len)
4702                                 valid_entry = entry;
4703                 }
4704         }
4705
4706         /* Not find one to satisfy the request, return */
4707         if (valid_entry == NULL) {
4708                 PMD_DRV_LOG(ERR, "No valid entry found");
4709                 return -ENOMEM;
4710         }
4711         /**
4712          * The entry have equal queue number as requested,
4713          * remove it from alloc_list.
4714          */
4715         if (valid_entry->len == num) {
4716                 LIST_REMOVE(valid_entry, next);
4717         } else {
4718                 /**
4719                  * The entry have more numbers than requested,
4720                  * create a new entry for alloc_list and minus its
4721                  * queue base and number in free_list.
4722                  */
4723                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4724                 if (entry == NULL) {
4725                         PMD_DRV_LOG(ERR,
4726                                 "Failed to allocate memory for resource pool");
4727                         return -ENOMEM;
4728                 }
4729                 entry->base = valid_entry->base;
4730                 entry->len = num;
4731                 valid_entry->base += num;
4732                 valid_entry->len -= num;
4733                 valid_entry = entry;
4734         }
4735
4736         /* Insert it into alloc list, not sorted */
4737         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4738
4739         pool->num_free -= valid_entry->len;
4740         pool->num_alloc += valid_entry->len;
4741
4742         return valid_entry->base + pool->base;
4743 }
4744
4745 /**
4746  * bitmap_is_subset - Check whether src2 is subset of src1
4747  **/
4748 static inline int
4749 bitmap_is_subset(uint8_t src1, uint8_t src2)
4750 {
4751         return !((src1 ^ src2) & src2);
4752 }
4753
4754 static enum i40e_status_code
4755 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4756 {
4757         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4758
4759         /* If DCB is not supported, only default TC is supported */
4760         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4761                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4762                 return I40E_NOT_SUPPORTED;
4763         }
4764
4765         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4766                 PMD_DRV_LOG(ERR,
4767                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4768                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4769                 return I40E_NOT_SUPPORTED;
4770         }
4771         return I40E_SUCCESS;
4772 }
4773
4774 int
4775 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4776                                 struct i40e_vsi_vlan_pvid_info *info)
4777 {
4778         struct i40e_hw *hw;
4779         struct i40e_vsi_context ctxt;
4780         uint8_t vlan_flags = 0;
4781         int ret;
4782
4783         if (vsi == NULL || info == NULL) {
4784                 PMD_DRV_LOG(ERR, "invalid parameters");
4785                 return I40E_ERR_PARAM;
4786         }
4787
4788         if (info->on) {
4789                 vsi->info.pvid = info->config.pvid;
4790                 /**
4791                  * If insert pvid is enabled, only tagged pkts are
4792                  * allowed to be sent out.
4793                  */
4794                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4795                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4796         } else {
4797                 vsi->info.pvid = 0;
4798                 if (info->config.reject.tagged == 0)
4799                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4800
4801                 if (info->config.reject.untagged == 0)
4802                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4803         }
4804         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4805                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4806         vsi->info.port_vlan_flags |= vlan_flags;
4807         vsi->info.valid_sections =
4808                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4809         memset(&ctxt, 0, sizeof(ctxt));
4810         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4811         ctxt.seid = vsi->seid;
4812
4813         hw = I40E_VSI_TO_HW(vsi);
4814         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4815         if (ret != I40E_SUCCESS)
4816                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4817
4818         return ret;
4819 }
4820
4821 static int
4822 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4823 {
4824         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4825         int i, ret;
4826         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4827
4828         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4829         if (ret != I40E_SUCCESS)
4830                 return ret;
4831
4832         if (!vsi->seid) {
4833                 PMD_DRV_LOG(ERR, "seid not valid");
4834                 return -EINVAL;
4835         }
4836
4837         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4838         tc_bw_data.tc_valid_bits = enabled_tcmap;
4839         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4840                 tc_bw_data.tc_bw_credits[i] =
4841                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4842
4843         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4844         if (ret != I40E_SUCCESS) {
4845                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4846                 return ret;
4847         }
4848
4849         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4850                                         sizeof(vsi->info.qs_handle));
4851         return I40E_SUCCESS;
4852 }
4853
4854 static enum i40e_status_code
4855 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4856                                  struct i40e_aqc_vsi_properties_data *info,
4857                                  uint8_t enabled_tcmap)
4858 {
4859         enum i40e_status_code ret;
4860         int i, total_tc = 0;
4861         uint16_t qpnum_per_tc, bsf, qp_idx;
4862
4863         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4864         if (ret != I40E_SUCCESS)
4865                 return ret;
4866
4867         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4868                 if (enabled_tcmap & (1 << i))
4869                         total_tc++;
4870         if (total_tc == 0)
4871                 total_tc = 1;
4872         vsi->enabled_tc = enabled_tcmap;
4873
4874         /* Number of queues per enabled TC */
4875         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4876         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4877         bsf = rte_bsf32(qpnum_per_tc);
4878
4879         /* Adjust the queue number to actual queues that can be applied */
4880         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4881                 vsi->nb_qps = qpnum_per_tc * total_tc;
4882
4883         /**
4884          * Configure TC and queue mapping parameters, for enabled TC,
4885          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4886          * default queue will serve it.
4887          */
4888         qp_idx = 0;
4889         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4890                 if (vsi->enabled_tc & (1 << i)) {
4891                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4892                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4893                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4894                         qp_idx += qpnum_per_tc;
4895                 } else
4896                         info->tc_mapping[i] = 0;
4897         }
4898
4899         /* Associate queue number with VSI */
4900         if (vsi->type == I40E_VSI_SRIOV) {
4901                 info->mapping_flags |=
4902                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4903                 for (i = 0; i < vsi->nb_qps; i++)
4904                         info->queue_mapping[i] =
4905                                 rte_cpu_to_le_16(vsi->base_queue + i);
4906         } else {
4907                 info->mapping_flags |=
4908                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4909                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4910         }
4911         info->valid_sections |=
4912                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4913
4914         return I40E_SUCCESS;
4915 }
4916
4917 static int
4918 i40e_veb_release(struct i40e_veb *veb)
4919 {
4920         struct i40e_vsi *vsi;
4921         struct i40e_hw *hw;
4922
4923         if (veb == NULL)
4924                 return -EINVAL;
4925
4926         if (!TAILQ_EMPTY(&veb->head)) {
4927                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4928                 return -EACCES;
4929         }
4930         /* associate_vsi field is NULL for floating VEB */
4931         if (veb->associate_vsi != NULL) {
4932                 vsi = veb->associate_vsi;
4933                 hw = I40E_VSI_TO_HW(vsi);
4934
4935                 vsi->uplink_seid = veb->uplink_seid;
4936                 vsi->veb = NULL;
4937         } else {
4938                 veb->associate_pf->main_vsi->floating_veb = NULL;
4939                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4940         }
4941
4942         i40e_aq_delete_element(hw, veb->seid, NULL);
4943         rte_free(veb);
4944         return I40E_SUCCESS;
4945 }
4946
4947 /* Setup a veb */
4948 static struct i40e_veb *
4949 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4950 {
4951         struct i40e_veb *veb;
4952         int ret;
4953         struct i40e_hw *hw;
4954
4955         if (pf == NULL) {
4956                 PMD_DRV_LOG(ERR,
4957                             "veb setup failed, associated PF shouldn't null");
4958                 return NULL;
4959         }
4960         hw = I40E_PF_TO_HW(pf);
4961
4962         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4963         if (!veb) {
4964                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4965                 goto fail;
4966         }
4967
4968         veb->associate_vsi = vsi;
4969         veb->associate_pf = pf;
4970         TAILQ_INIT(&veb->head);
4971         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4972
4973         /* create floating veb if vsi is NULL */
4974         if (vsi != NULL) {
4975                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4976                                       I40E_DEFAULT_TCMAP, false,
4977                                       &veb->seid, false, NULL);
4978         } else {
4979                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4980                                       true, &veb->seid, false, NULL);
4981         }
4982
4983         if (ret != I40E_SUCCESS) {
4984                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4985                             hw->aq.asq_last_status);
4986                 goto fail;
4987         }
4988         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4989
4990         /* get statistics index */
4991         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4992                                 &veb->stats_idx, NULL, NULL, NULL);
4993         if (ret != I40E_SUCCESS) {
4994                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4995                             hw->aq.asq_last_status);
4996                 goto fail;
4997         }
4998         /* Get VEB bandwidth, to be implemented */
4999         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5000         if (vsi)
5001                 vsi->uplink_seid = veb->seid;
5002
5003         return veb;
5004 fail:
5005         rte_free(veb);
5006         return NULL;
5007 }
5008
5009 int
5010 i40e_vsi_release(struct i40e_vsi *vsi)
5011 {
5012         struct i40e_pf *pf;
5013         struct i40e_hw *hw;
5014         struct i40e_vsi_list *vsi_list;
5015         void *temp;
5016         int ret;
5017         struct i40e_mac_filter *f;
5018         uint16_t user_param;
5019
5020         if (!vsi)
5021                 return I40E_SUCCESS;
5022
5023         if (!vsi->adapter)
5024                 return -EFAULT;
5025
5026         user_param = vsi->user_param;
5027
5028         pf = I40E_VSI_TO_PF(vsi);
5029         hw = I40E_VSI_TO_HW(vsi);
5030
5031         /* VSI has child to attach, release child first */
5032         if (vsi->veb) {
5033                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5034                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5035                                 return -1;
5036                 }
5037                 i40e_veb_release(vsi->veb);
5038         }
5039
5040         if (vsi->floating_veb) {
5041                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5042                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5043                                 return -1;
5044                 }
5045         }
5046
5047         /* Remove all macvlan filters of the VSI */
5048         i40e_vsi_remove_all_macvlan_filter(vsi);
5049         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5050                 rte_free(f);
5051
5052         if (vsi->type != I40E_VSI_MAIN &&
5053             ((vsi->type != I40E_VSI_SRIOV) ||
5054             !pf->floating_veb_list[user_param])) {
5055                 /* Remove vsi from parent's sibling list */
5056                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5057                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5058                         return I40E_ERR_PARAM;
5059                 }
5060                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5061                                 &vsi->sib_vsi_list, list);
5062
5063                 /* Remove all switch element of the VSI */
5064                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5065                 if (ret != I40E_SUCCESS)
5066                         PMD_DRV_LOG(ERR, "Failed to delete element");
5067         }
5068
5069         if ((vsi->type == I40E_VSI_SRIOV) &&
5070             pf->floating_veb_list[user_param]) {
5071                 /* Remove vsi from parent's sibling list */
5072                 if (vsi->parent_vsi == NULL ||
5073                     vsi->parent_vsi->floating_veb == NULL) {
5074                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5075                         return I40E_ERR_PARAM;
5076                 }
5077                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5078                              &vsi->sib_vsi_list, list);
5079
5080                 /* Remove all switch element of the VSI */
5081                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5082                 if (ret != I40E_SUCCESS)
5083                         PMD_DRV_LOG(ERR, "Failed to delete element");
5084         }
5085
5086         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5087
5088         if (vsi->type != I40E_VSI_SRIOV)
5089                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5090         rte_free(vsi);
5091
5092         return I40E_SUCCESS;
5093 }
5094
5095 static int
5096 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5097 {
5098         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5099         struct i40e_aqc_remove_macvlan_element_data def_filter;
5100         struct i40e_mac_filter_info filter;
5101         int ret;
5102
5103         if (vsi->type != I40E_VSI_MAIN)
5104                 return I40E_ERR_CONFIG;
5105         memset(&def_filter, 0, sizeof(def_filter));
5106         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5107                                         ETH_ADDR_LEN);
5108         def_filter.vlan_tag = 0;
5109         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5110                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5111         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5112         if (ret != I40E_SUCCESS) {
5113                 struct i40e_mac_filter *f;
5114                 struct ether_addr *mac;
5115
5116                 PMD_DRV_LOG(DEBUG,
5117                             "Cannot remove the default macvlan filter");
5118                 /* It needs to add the permanent mac into mac list */
5119                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5120                 if (f == NULL) {
5121                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5122                         return I40E_ERR_NO_MEMORY;
5123                 }
5124                 mac = &f->mac_info.mac_addr;
5125                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5126                                 ETH_ADDR_LEN);
5127                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5128                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5129                 vsi->mac_num++;
5130
5131                 return ret;
5132         }
5133         rte_memcpy(&filter.mac_addr,
5134                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5135         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5136         return i40e_vsi_add_mac(vsi, &filter);
5137 }
5138
5139 /*
5140  * i40e_vsi_get_bw_config - Query VSI BW Information
5141  * @vsi: the VSI to be queried
5142  *
5143  * Returns 0 on success, negative value on failure
5144  */
5145 static enum i40e_status_code
5146 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5147 {
5148         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5149         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5150         struct i40e_hw *hw = &vsi->adapter->hw;
5151         i40e_status ret;
5152         int i;
5153         uint32_t bw_max;
5154
5155         memset(&bw_config, 0, sizeof(bw_config));
5156         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5157         if (ret != I40E_SUCCESS) {
5158                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5159                             hw->aq.asq_last_status);
5160                 return ret;
5161         }
5162
5163         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5164         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5165                                         &ets_sla_config, NULL);
5166         if (ret != I40E_SUCCESS) {
5167                 PMD_DRV_LOG(ERR,
5168                         "VSI failed to get TC bandwdith configuration %u",
5169                         hw->aq.asq_last_status);
5170                 return ret;
5171         }
5172
5173         /* store and print out BW info */
5174         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5175         vsi->bw_info.bw_max = bw_config.max_bw;
5176         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5177         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5178         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5179                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5180                      I40E_16_BIT_WIDTH);
5181         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5182                 vsi->bw_info.bw_ets_share_credits[i] =
5183                                 ets_sla_config.share_credits[i];
5184                 vsi->bw_info.bw_ets_credits[i] =
5185                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5186                 /* 4 bits per TC, 4th bit is reserved */
5187                 vsi->bw_info.bw_ets_max[i] =
5188                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5189                                   RTE_LEN2MASK(3, uint8_t));
5190                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5191                             vsi->bw_info.bw_ets_share_credits[i]);
5192                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5193                             vsi->bw_info.bw_ets_credits[i]);
5194                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5195                             vsi->bw_info.bw_ets_max[i]);
5196         }
5197
5198         return I40E_SUCCESS;
5199 }
5200
5201 /* i40e_enable_pf_lb
5202  * @pf: pointer to the pf structure
5203  *
5204  * allow loopback on pf
5205  */
5206 static inline void
5207 i40e_enable_pf_lb(struct i40e_pf *pf)
5208 {
5209         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5210         struct i40e_vsi_context ctxt;
5211         int ret;
5212
5213         /* Use the FW API if FW >= v5.0 */
5214         if (hw->aq.fw_maj_ver < 5) {
5215                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5216                 return;
5217         }
5218
5219         memset(&ctxt, 0, sizeof(ctxt));
5220         ctxt.seid = pf->main_vsi_seid;
5221         ctxt.pf_num = hw->pf_id;
5222         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5223         if (ret) {
5224                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5225                             ret, hw->aq.asq_last_status);
5226                 return;
5227         }
5228         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5229         ctxt.info.valid_sections =
5230                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5231         ctxt.info.switch_id |=
5232                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5233
5234         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5235         if (ret)
5236                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5237                             hw->aq.asq_last_status);
5238 }
5239
5240 /* Setup a VSI */
5241 struct i40e_vsi *
5242 i40e_vsi_setup(struct i40e_pf *pf,
5243                enum i40e_vsi_type type,
5244                struct i40e_vsi *uplink_vsi,
5245                uint16_t user_param)
5246 {
5247         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5248         struct i40e_vsi *vsi;
5249         struct i40e_mac_filter_info filter;
5250         int ret;
5251         struct i40e_vsi_context ctxt;
5252         struct ether_addr broadcast =
5253                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5254
5255         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5256             uplink_vsi == NULL) {
5257                 PMD_DRV_LOG(ERR,
5258                         "VSI setup failed, VSI link shouldn't be NULL");
5259                 return NULL;
5260         }
5261
5262         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5263                 PMD_DRV_LOG(ERR,
5264                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5265                 return NULL;
5266         }
5267
5268         /* two situations
5269          * 1.type is not MAIN and uplink vsi is not NULL
5270          * If uplink vsi didn't setup VEB, create one first under veb field
5271          * 2.type is SRIOV and the uplink is NULL
5272          * If floating VEB is NULL, create one veb under floating veb field
5273          */
5274
5275         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5276             uplink_vsi->veb == NULL) {
5277                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5278
5279                 if (uplink_vsi->veb == NULL) {
5280                         PMD_DRV_LOG(ERR, "VEB setup failed");
5281                         return NULL;
5282                 }
5283                 /* set ALLOWLOOPBACk on pf, when veb is created */
5284                 i40e_enable_pf_lb(pf);
5285         }
5286
5287         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5288             pf->main_vsi->floating_veb == NULL) {
5289                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5290
5291                 if (pf->main_vsi->floating_veb == NULL) {
5292                         PMD_DRV_LOG(ERR, "VEB setup failed");
5293                         return NULL;
5294                 }
5295         }
5296
5297         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5298         if (!vsi) {
5299                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5300                 return NULL;
5301         }
5302         TAILQ_INIT(&vsi->mac_list);
5303         vsi->type = type;
5304         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5305         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5306         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5307         vsi->user_param = user_param;
5308         vsi->vlan_anti_spoof_on = 0;
5309         vsi->vlan_filter_on = 0;
5310         /* Allocate queues */
5311         switch (vsi->type) {
5312         case I40E_VSI_MAIN  :
5313                 vsi->nb_qps = pf->lan_nb_qps;
5314                 break;
5315         case I40E_VSI_SRIOV :
5316                 vsi->nb_qps = pf->vf_nb_qps;
5317                 break;
5318         case I40E_VSI_VMDQ2:
5319                 vsi->nb_qps = pf->vmdq_nb_qps;
5320                 break;
5321         case I40E_VSI_FDIR:
5322                 vsi->nb_qps = pf->fdir_nb_qps;
5323                 break;
5324         default:
5325                 goto fail_mem;
5326         }
5327         /*
5328          * The filter status descriptor is reported in rx queue 0,
5329          * while the tx queue for fdir filter programming has no
5330          * such constraints, can be non-zero queues.
5331          * To simplify it, choose FDIR vsi use queue 0 pair.
5332          * To make sure it will use queue 0 pair, queue allocation
5333          * need be done before this function is called
5334          */
5335         if (type != I40E_VSI_FDIR) {
5336                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5337                         if (ret < 0) {
5338                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5339                                                 vsi->seid, ret);
5340                                 goto fail_mem;
5341                         }
5342                         vsi->base_queue = ret;
5343         } else
5344                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5345
5346         /* VF has MSIX interrupt in VF range, don't allocate here */
5347         if (type == I40E_VSI_MAIN) {
5348                 if (pf->support_multi_driver) {
5349                         /* If support multi-driver, need to use INT0 instead of
5350                          * allocating from msix pool. The Msix pool is init from
5351                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5352                          * to 1 without calling i40e_res_pool_alloc.
5353                          */
5354                         vsi->msix_intr = 0;
5355                         vsi->nb_msix = 1;
5356                 } else {
5357                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5358                                                   RTE_MIN(vsi->nb_qps,
5359                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5360                         if (ret < 0) {
5361                                 PMD_DRV_LOG(ERR,
5362                                             "VSI MAIN %d get heap failed %d",
5363                                             vsi->seid, ret);
5364                                 goto fail_queue_alloc;
5365                         }
5366                         vsi->msix_intr = ret;
5367                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5368                                                RTE_MAX_RXTX_INTR_VEC_ID);
5369                 }
5370         } else if (type != I40E_VSI_SRIOV) {
5371                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5372                 if (ret < 0) {
5373                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5374                         goto fail_queue_alloc;
5375                 }
5376                 vsi->msix_intr = ret;
5377                 vsi->nb_msix = 1;
5378         } else {
5379                 vsi->msix_intr = 0;
5380                 vsi->nb_msix = 0;
5381         }
5382
5383         /* Add VSI */
5384         if (type == I40E_VSI_MAIN) {
5385                 /* For main VSI, no need to add since it's default one */
5386                 vsi->uplink_seid = pf->mac_seid;
5387                 vsi->seid = pf->main_vsi_seid;
5388                 /* Bind queues with specific MSIX interrupt */
5389                 /**
5390                  * Needs 2 interrupt at least, one for misc cause which will
5391                  * enabled from OS side, Another for queues binding the
5392                  * interrupt from device side only.
5393                  */
5394
5395                 /* Get default VSI parameters from hardware */
5396                 memset(&ctxt, 0, sizeof(ctxt));
5397                 ctxt.seid = vsi->seid;
5398                 ctxt.pf_num = hw->pf_id;
5399                 ctxt.uplink_seid = vsi->uplink_seid;
5400                 ctxt.vf_num = 0;
5401                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5402                 if (ret != I40E_SUCCESS) {
5403                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5404                         goto fail_msix_alloc;
5405                 }
5406                 rte_memcpy(&vsi->info, &ctxt.info,
5407                         sizeof(struct i40e_aqc_vsi_properties_data));
5408                 vsi->vsi_id = ctxt.vsi_number;
5409                 vsi->info.valid_sections = 0;
5410
5411                 /* Configure tc, enabled TC0 only */
5412                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5413                         I40E_SUCCESS) {
5414                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5415                         goto fail_msix_alloc;
5416                 }
5417
5418                 /* TC, queue mapping */
5419                 memset(&ctxt, 0, sizeof(ctxt));
5420                 vsi->info.valid_sections |=
5421                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5422                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5423                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5424                 rte_memcpy(&ctxt.info, &vsi->info,
5425                         sizeof(struct i40e_aqc_vsi_properties_data));
5426                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5427                                                 I40E_DEFAULT_TCMAP);
5428                 if (ret != I40E_SUCCESS) {
5429                         PMD_DRV_LOG(ERR,
5430                                 "Failed to configure TC queue mapping");
5431                         goto fail_msix_alloc;
5432                 }
5433                 ctxt.seid = vsi->seid;
5434                 ctxt.pf_num = hw->pf_id;
5435                 ctxt.uplink_seid = vsi->uplink_seid;
5436                 ctxt.vf_num = 0;
5437
5438                 /* Update VSI parameters */
5439                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5440                 if (ret != I40E_SUCCESS) {
5441                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5442                         goto fail_msix_alloc;
5443                 }
5444
5445                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5446                                                 sizeof(vsi->info.tc_mapping));
5447                 rte_memcpy(&vsi->info.queue_mapping,
5448                                 &ctxt.info.queue_mapping,
5449                         sizeof(vsi->info.queue_mapping));
5450                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5451                 vsi->info.valid_sections = 0;
5452
5453                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5454                                 ETH_ADDR_LEN);
5455
5456                 /**
5457                  * Updating default filter settings are necessary to prevent
5458                  * reception of tagged packets.
5459                  * Some old firmware configurations load a default macvlan
5460                  * filter which accepts both tagged and untagged packets.
5461                  * The updating is to use a normal filter instead if needed.
5462                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5463                  * The firmware with correct configurations load the default
5464                  * macvlan filter which is expected and cannot be removed.
5465                  */
5466                 i40e_update_default_filter_setting(vsi);
5467                 i40e_config_qinq(hw, vsi);
5468         } else if (type == I40E_VSI_SRIOV) {
5469                 memset(&ctxt, 0, sizeof(ctxt));
5470                 /**
5471                  * For other VSI, the uplink_seid equals to uplink VSI's
5472                  * uplink_seid since they share same VEB
5473                  */
5474                 if (uplink_vsi == NULL)
5475                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5476                 else
5477                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5478                 ctxt.pf_num = hw->pf_id;
5479                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5480                 ctxt.uplink_seid = vsi->uplink_seid;
5481                 ctxt.connection_type = 0x1;
5482                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5483
5484                 /* Use the VEB configuration if FW >= v5.0 */
5485                 if (hw->aq.fw_maj_ver >= 5) {
5486                         /* Configure switch ID */
5487                         ctxt.info.valid_sections |=
5488                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5489                         ctxt.info.switch_id =
5490                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5491                 }
5492
5493                 /* Configure port/vlan */
5494                 ctxt.info.valid_sections |=
5495                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5496                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5497                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5498                                                 hw->func_caps.enabled_tcmap);
5499                 if (ret != I40E_SUCCESS) {
5500                         PMD_DRV_LOG(ERR,
5501                                 "Failed to configure TC queue mapping");
5502                         goto fail_msix_alloc;
5503                 }
5504
5505                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5506                 ctxt.info.valid_sections |=
5507                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5508                 /**
5509                  * Since VSI is not created yet, only configure parameter,
5510                  * will add vsi below.
5511                  */
5512
5513                 i40e_config_qinq(hw, vsi);
5514         } else if (type == I40E_VSI_VMDQ2) {
5515                 memset(&ctxt, 0, sizeof(ctxt));
5516                 /*
5517                  * For other VSI, the uplink_seid equals to uplink VSI's
5518                  * uplink_seid since they share same VEB
5519                  */
5520                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5521                 ctxt.pf_num = hw->pf_id;
5522                 ctxt.vf_num = 0;
5523                 ctxt.uplink_seid = vsi->uplink_seid;
5524                 ctxt.connection_type = 0x1;
5525                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5526
5527                 ctxt.info.valid_sections |=
5528                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5529                 /* user_param carries flag to enable loop back */
5530                 if (user_param) {
5531                         ctxt.info.switch_id =
5532                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5533                         ctxt.info.switch_id |=
5534                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5535                 }
5536
5537                 /* Configure port/vlan */
5538                 ctxt.info.valid_sections |=
5539                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5540                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5541                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5542                                                 I40E_DEFAULT_TCMAP);
5543                 if (ret != I40E_SUCCESS) {
5544                         PMD_DRV_LOG(ERR,
5545                                 "Failed to configure TC queue mapping");
5546                         goto fail_msix_alloc;
5547                 }
5548                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5549                 ctxt.info.valid_sections |=
5550                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5551         } else if (type == I40E_VSI_FDIR) {
5552                 memset(&ctxt, 0, sizeof(ctxt));
5553                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5554                 ctxt.pf_num = hw->pf_id;
5555                 ctxt.vf_num = 0;
5556                 ctxt.uplink_seid = vsi->uplink_seid;
5557                 ctxt.connection_type = 0x1;     /* regular data port */
5558                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5559                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5560                                                 I40E_DEFAULT_TCMAP);
5561                 if (ret != I40E_SUCCESS) {
5562                         PMD_DRV_LOG(ERR,
5563                                 "Failed to configure TC queue mapping.");
5564                         goto fail_msix_alloc;
5565                 }
5566                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5567                 ctxt.info.valid_sections |=
5568                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5569         } else {
5570                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5571                 goto fail_msix_alloc;
5572         }
5573
5574         if (vsi->type != I40E_VSI_MAIN) {
5575                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5576                 if (ret != I40E_SUCCESS) {
5577                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5578                                     hw->aq.asq_last_status);
5579                         goto fail_msix_alloc;
5580                 }
5581                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5582                 vsi->info.valid_sections = 0;
5583                 vsi->seid = ctxt.seid;
5584                 vsi->vsi_id = ctxt.vsi_number;
5585                 vsi->sib_vsi_list.vsi = vsi;
5586                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5587                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5588                                           &vsi->sib_vsi_list, list);
5589                 } else {
5590                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5591                                           &vsi->sib_vsi_list, list);
5592                 }
5593         }
5594
5595         /* MAC/VLAN configuration */
5596         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5597         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5598
5599         ret = i40e_vsi_add_mac(vsi, &filter);
5600         if (ret != I40E_SUCCESS) {
5601                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5602                 goto fail_msix_alloc;
5603         }
5604
5605         /* Get VSI BW information */
5606         i40e_vsi_get_bw_config(vsi);
5607         return vsi;
5608 fail_msix_alloc:
5609         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5610 fail_queue_alloc:
5611         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5612 fail_mem:
5613         rte_free(vsi);
5614         return NULL;
5615 }
5616
5617 /* Configure vlan filter on or off */
5618 int
5619 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5620 {
5621         int i, num;
5622         struct i40e_mac_filter *f;
5623         void *temp;
5624         struct i40e_mac_filter_info *mac_filter;
5625         enum rte_mac_filter_type desired_filter;
5626         int ret = I40E_SUCCESS;
5627
5628         if (on) {
5629                 /* Filter to match MAC and VLAN */
5630                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5631         } else {
5632                 /* Filter to match only MAC */
5633                 desired_filter = RTE_MAC_PERFECT_MATCH;
5634         }
5635
5636         num = vsi->mac_num;
5637
5638         mac_filter = rte_zmalloc("mac_filter_info_data",
5639                                  num * sizeof(*mac_filter), 0);
5640         if (mac_filter == NULL) {
5641                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5642                 return I40E_ERR_NO_MEMORY;
5643         }
5644
5645         i = 0;
5646
5647         /* Remove all existing mac */
5648         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5649                 mac_filter[i] = f->mac_info;
5650                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5651                 if (ret) {
5652                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5653                                     on ? "enable" : "disable");
5654                         goto DONE;
5655                 }
5656                 i++;
5657         }
5658
5659         /* Override with new filter */
5660         for (i = 0; i < num; i++) {
5661                 mac_filter[i].filter_type = desired_filter;
5662                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5663                 if (ret) {
5664                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5665                                     on ? "enable" : "disable");
5666                         goto DONE;
5667                 }
5668         }
5669
5670 DONE:
5671         rte_free(mac_filter);
5672         return ret;
5673 }
5674
5675 /* Configure vlan stripping on or off */
5676 int
5677 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5678 {
5679         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5680         struct i40e_vsi_context ctxt;
5681         uint8_t vlan_flags;
5682         int ret = I40E_SUCCESS;
5683
5684         /* Check if it has been already on or off */
5685         if (vsi->info.valid_sections &
5686                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5687                 if (on) {
5688                         if ((vsi->info.port_vlan_flags &
5689                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5690                                 return 0; /* already on */
5691                 } else {
5692                         if ((vsi->info.port_vlan_flags &
5693                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5694                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5695                                 return 0; /* already off */
5696                 }
5697         }
5698
5699         if (on)
5700                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5701         else
5702                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5703         vsi->info.valid_sections =
5704                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5705         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5706         vsi->info.port_vlan_flags |= vlan_flags;
5707         ctxt.seid = vsi->seid;
5708         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5709         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5710         if (ret)
5711                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5712                             on ? "enable" : "disable");
5713
5714         return ret;
5715 }
5716
5717 static int
5718 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5719 {
5720         struct rte_eth_dev_data *data = dev->data;
5721         int ret;
5722         int mask = 0;
5723
5724         /* Apply vlan offload setting */
5725         mask = ETH_VLAN_STRIP_MASK |
5726                ETH_VLAN_FILTER_MASK |
5727                ETH_VLAN_EXTEND_MASK;
5728         ret = i40e_vlan_offload_set(dev, mask);
5729         if (ret) {
5730                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5731                 return ret;
5732         }
5733
5734         /* Apply pvid setting */
5735         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5736                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5737         if (ret)
5738                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5739
5740         return ret;
5741 }
5742
5743 static int
5744 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5745 {
5746         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5747
5748         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5749 }
5750
5751 static int
5752 i40e_update_flow_control(struct i40e_hw *hw)
5753 {
5754 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5755         struct i40e_link_status link_status;
5756         uint32_t rxfc = 0, txfc = 0, reg;
5757         uint8_t an_info;
5758         int ret;
5759
5760         memset(&link_status, 0, sizeof(link_status));
5761         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5762         if (ret != I40E_SUCCESS) {
5763                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5764                 goto write_reg; /* Disable flow control */
5765         }
5766
5767         an_info = hw->phy.link_info.an_info;
5768         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5769                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5770                 ret = I40E_ERR_NOT_READY;
5771                 goto write_reg; /* Disable flow control */
5772         }
5773         /**
5774          * If link auto negotiation is enabled, flow control needs to
5775          * be configured according to it
5776          */
5777         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5778         case I40E_LINK_PAUSE_RXTX:
5779                 rxfc = 1;
5780                 txfc = 1;
5781                 hw->fc.current_mode = I40E_FC_FULL;
5782                 break;
5783         case I40E_AQ_LINK_PAUSE_RX:
5784                 rxfc = 1;
5785                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5786                 break;
5787         case I40E_AQ_LINK_PAUSE_TX:
5788                 txfc = 1;
5789                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5790                 break;
5791         default:
5792                 hw->fc.current_mode = I40E_FC_NONE;
5793                 break;
5794         }
5795
5796 write_reg:
5797         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5798                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5799         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5800         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5801         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5802         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5803
5804         return ret;
5805 }
5806
5807 /* PF setup */
5808 static int
5809 i40e_pf_setup(struct i40e_pf *pf)
5810 {
5811         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5812         struct i40e_filter_control_settings settings;
5813         struct i40e_vsi *vsi;
5814         int ret;
5815
5816         /* Clear all stats counters */
5817         pf->offset_loaded = FALSE;
5818         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5819         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5820         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5821         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5822
5823         ret = i40e_pf_get_switch_config(pf);
5824         if (ret != I40E_SUCCESS) {
5825                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5826                 return ret;
5827         }
5828
5829         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
5830         if (ret)
5831                 PMD_INIT_LOG(WARNING,
5832                         "failed to allocate switch domain for device %d", ret);
5833
5834         if (pf->flags & I40E_FLAG_FDIR) {
5835                 /* make queue allocated first, let FDIR use queue pair 0*/
5836                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5837                 if (ret != I40E_FDIR_QUEUE_ID) {
5838                         PMD_DRV_LOG(ERR,
5839                                 "queue allocation fails for FDIR: ret =%d",
5840                                 ret);
5841                         pf->flags &= ~I40E_FLAG_FDIR;
5842                 }
5843         }
5844         /*  main VSI setup */
5845         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5846         if (!vsi) {
5847                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5848                 return I40E_ERR_NOT_READY;
5849         }
5850         pf->main_vsi = vsi;
5851
5852         /* Configure filter control */
5853         memset(&settings, 0, sizeof(settings));
5854         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5855                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5856         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5857                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5858         else {
5859                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5860                         hw->func_caps.rss_table_size);
5861                 return I40E_ERR_PARAM;
5862         }
5863         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5864                 hw->func_caps.rss_table_size);
5865         pf->hash_lut_size = hw->func_caps.rss_table_size;
5866
5867         /* Enable ethtype and macvlan filters */
5868         settings.enable_ethtype = TRUE;
5869         settings.enable_macvlan = TRUE;
5870         ret = i40e_set_filter_control(hw, &settings);
5871         if (ret)
5872                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5873                                                                 ret);
5874
5875         /* Update flow control according to the auto negotiation */
5876         i40e_update_flow_control(hw);
5877
5878         return I40E_SUCCESS;
5879 }
5880
5881 int
5882 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5883 {
5884         uint32_t reg;
5885         uint16_t j;
5886
5887         /**
5888          * Set or clear TX Queue Disable flags,
5889          * which is required by hardware.
5890          */
5891         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5892         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5893
5894         /* Wait until the request is finished */
5895         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5896                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5897                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5898                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5899                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5900                                                         & 0x1))) {
5901                         break;
5902                 }
5903         }
5904         if (on) {
5905                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5906                         return I40E_SUCCESS; /* already on, skip next steps */
5907
5908                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5909                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5910         } else {
5911                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5912                         return I40E_SUCCESS; /* already off, skip next steps */
5913                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5914         }
5915         /* Write the register */
5916         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5917         /* Check the result */
5918         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5919                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5920                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5921                 if (on) {
5922                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5923                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5924                                 break;
5925                 } else {
5926                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5927                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5928                                 break;
5929                 }
5930         }
5931         /* Check if it is timeout */
5932         if (j >= I40E_CHK_Q_ENA_COUNT) {
5933                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5934                             (on ? "enable" : "disable"), q_idx);
5935                 return I40E_ERR_TIMEOUT;
5936         }
5937
5938         return I40E_SUCCESS;
5939 }
5940
5941 /* Swith on or off the tx queues */
5942 static int
5943 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5944 {
5945         struct rte_eth_dev_data *dev_data = pf->dev_data;
5946         struct i40e_tx_queue *txq;
5947         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5948         uint16_t i;
5949         int ret;
5950
5951         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5952                 txq = dev_data->tx_queues[i];
5953                 /* Don't operate the queue if not configured or
5954                  * if starting only per queue */
5955                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5956                         continue;
5957                 if (on)
5958                         ret = i40e_dev_tx_queue_start(dev, i);
5959                 else
5960                         ret = i40e_dev_tx_queue_stop(dev, i);
5961                 if ( ret != I40E_SUCCESS)
5962                         return ret;
5963         }
5964
5965         return I40E_SUCCESS;
5966 }
5967
5968 int
5969 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5970 {
5971         uint32_t reg;
5972         uint16_t j;
5973
5974         /* Wait until the request is finished */
5975         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5976                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5977                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5978                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5979                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5980                         break;
5981         }
5982
5983         if (on) {
5984                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5985                         return I40E_SUCCESS; /* Already on, skip next steps */
5986                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5987         } else {
5988                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5989                         return I40E_SUCCESS; /* Already off, skip next steps */
5990                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5991         }
5992
5993         /* Write the register */
5994         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5995         /* Check the result */
5996         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5997                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5998                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5999                 if (on) {
6000                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6001                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6002                                 break;
6003                 } else {
6004                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6005                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6006                                 break;
6007                 }
6008         }
6009
6010         /* Check if it is timeout */
6011         if (j >= I40E_CHK_Q_ENA_COUNT) {
6012                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6013                             (on ? "enable" : "disable"), q_idx);
6014                 return I40E_ERR_TIMEOUT;
6015         }
6016
6017         return I40E_SUCCESS;
6018 }
6019 /* Switch on or off the rx queues */
6020 static int
6021 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6022 {
6023         struct rte_eth_dev_data *dev_data = pf->dev_data;
6024         struct i40e_rx_queue *rxq;
6025         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6026         uint16_t i;
6027         int ret;
6028
6029         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6030                 rxq = dev_data->rx_queues[i];
6031                 /* Don't operate the queue if not configured or
6032                  * if starting only per queue */
6033                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6034                         continue;
6035                 if (on)
6036                         ret = i40e_dev_rx_queue_start(dev, i);
6037                 else
6038                         ret = i40e_dev_rx_queue_stop(dev, i);
6039                 if (ret != I40E_SUCCESS)
6040                         return ret;
6041         }
6042
6043         return I40E_SUCCESS;
6044 }
6045
6046 /* Switch on or off all the rx/tx queues */
6047 int
6048 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6049 {
6050         int ret;
6051
6052         if (on) {
6053                 /* enable rx queues before enabling tx queues */
6054                 ret = i40e_dev_switch_rx_queues(pf, on);
6055                 if (ret) {
6056                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6057                         return ret;
6058                 }
6059                 ret = i40e_dev_switch_tx_queues(pf, on);
6060         } else {
6061                 /* Stop tx queues before stopping rx queues */
6062                 ret = i40e_dev_switch_tx_queues(pf, on);
6063                 if (ret) {
6064                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6065                         return ret;
6066                 }
6067                 ret = i40e_dev_switch_rx_queues(pf, on);
6068         }
6069
6070         return ret;
6071 }
6072
6073 /* Initialize VSI for TX */
6074 static int
6075 i40e_dev_tx_init(struct i40e_pf *pf)
6076 {
6077         struct rte_eth_dev_data *data = pf->dev_data;
6078         uint16_t i;
6079         uint32_t ret = I40E_SUCCESS;
6080         struct i40e_tx_queue *txq;
6081
6082         for (i = 0; i < data->nb_tx_queues; i++) {
6083                 txq = data->tx_queues[i];
6084                 if (!txq || !txq->q_set)
6085                         continue;
6086                 ret = i40e_tx_queue_init(txq);
6087                 if (ret != I40E_SUCCESS)
6088                         break;
6089         }
6090         if (ret == I40E_SUCCESS)
6091                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6092                                      ->eth_dev);
6093
6094         return ret;
6095 }
6096
6097 /* Initialize VSI for RX */
6098 static int
6099 i40e_dev_rx_init(struct i40e_pf *pf)
6100 {
6101         struct rte_eth_dev_data *data = pf->dev_data;
6102         int ret = I40E_SUCCESS;
6103         uint16_t i;
6104         struct i40e_rx_queue *rxq;
6105
6106         i40e_pf_config_mq_rx(pf);
6107         for (i = 0; i < data->nb_rx_queues; i++) {
6108                 rxq = data->rx_queues[i];
6109                 if (!rxq || !rxq->q_set)
6110                         continue;
6111
6112                 ret = i40e_rx_queue_init(rxq);
6113                 if (ret != I40E_SUCCESS) {
6114                         PMD_DRV_LOG(ERR,
6115                                 "Failed to do RX queue initialization");
6116                         break;
6117                 }
6118         }
6119         if (ret == I40E_SUCCESS)
6120                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6121                                      ->eth_dev);
6122
6123         return ret;
6124 }
6125
6126 static int
6127 i40e_dev_rxtx_init(struct i40e_pf *pf)
6128 {
6129         int err;
6130
6131         err = i40e_dev_tx_init(pf);
6132         if (err) {
6133                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6134                 return err;
6135         }
6136         err = i40e_dev_rx_init(pf);
6137         if (err) {
6138                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6139                 return err;
6140         }
6141
6142         return err;
6143 }
6144
6145 static int
6146 i40e_vmdq_setup(struct rte_eth_dev *dev)
6147 {
6148         struct rte_eth_conf *conf = &dev->data->dev_conf;
6149         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6150         int i, err, conf_vsis, j, loop;
6151         struct i40e_vsi *vsi;
6152         struct i40e_vmdq_info *vmdq_info;
6153         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6154         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6155
6156         /*
6157          * Disable interrupt to avoid message from VF. Furthermore, it will
6158          * avoid race condition in VSI creation/destroy.
6159          */
6160         i40e_pf_disable_irq0(hw);
6161
6162         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6163                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6164                 return -ENOTSUP;
6165         }
6166
6167         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6168         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6169                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6170                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6171                         pf->max_nb_vmdq_vsi);
6172                 return -ENOTSUP;
6173         }
6174
6175         if (pf->vmdq != NULL) {
6176                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6177                 return 0;
6178         }
6179
6180         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6181                                 sizeof(*vmdq_info) * conf_vsis, 0);
6182
6183         if (pf->vmdq == NULL) {
6184                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6185                 return -ENOMEM;
6186         }
6187
6188         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6189
6190         /* Create VMDQ VSI */
6191         for (i = 0; i < conf_vsis; i++) {
6192                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6193                                 vmdq_conf->enable_loop_back);
6194                 if (vsi == NULL) {
6195                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6196                         err = -1;
6197                         goto err_vsi_setup;
6198                 }
6199                 vmdq_info = &pf->vmdq[i];
6200                 vmdq_info->pf = pf;
6201                 vmdq_info->vsi = vsi;
6202         }
6203         pf->nb_cfg_vmdq_vsi = conf_vsis;
6204
6205         /* Configure Vlan */
6206         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6207         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6208                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6209                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6210                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6211                                         vmdq_conf->pool_map[i].vlan_id, j);
6212
6213                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6214                                                 vmdq_conf->pool_map[i].vlan_id);
6215                                 if (err) {
6216                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6217                                         err = -1;
6218                                         goto err_vsi_setup;
6219                                 }
6220                         }
6221                 }
6222         }
6223
6224         i40e_pf_enable_irq0(hw);
6225
6226         return 0;
6227
6228 err_vsi_setup:
6229         for (i = 0; i < conf_vsis; i++)
6230                 if (pf->vmdq[i].vsi == NULL)
6231                         break;
6232                 else
6233                         i40e_vsi_release(pf->vmdq[i].vsi);
6234
6235         rte_free(pf->vmdq);
6236         pf->vmdq = NULL;
6237         i40e_pf_enable_irq0(hw);
6238         return err;
6239 }
6240
6241 static void
6242 i40e_stat_update_32(struct i40e_hw *hw,
6243                    uint32_t reg,
6244                    bool offset_loaded,
6245                    uint64_t *offset,
6246                    uint64_t *stat)
6247 {
6248         uint64_t new_data;
6249
6250         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6251         if (!offset_loaded)
6252                 *offset = new_data;
6253
6254         if (new_data >= *offset)
6255                 *stat = (uint64_t)(new_data - *offset);
6256         else
6257                 *stat = (uint64_t)((new_data +
6258                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6259 }
6260
6261 static void
6262 i40e_stat_update_48(struct i40e_hw *hw,
6263                    uint32_t hireg,
6264                    uint32_t loreg,
6265                    bool offset_loaded,
6266                    uint64_t *offset,
6267                    uint64_t *stat)
6268 {
6269         uint64_t new_data;
6270
6271         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6272         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6273                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6274
6275         if (!offset_loaded)
6276                 *offset = new_data;
6277
6278         if (new_data >= *offset)
6279                 *stat = new_data - *offset;
6280         else
6281                 *stat = (uint64_t)((new_data +
6282                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6283
6284         *stat &= I40E_48_BIT_MASK;
6285 }
6286
6287 /* Disable IRQ0 */
6288 void
6289 i40e_pf_disable_irq0(struct i40e_hw *hw)
6290 {
6291         /* Disable all interrupt types */
6292         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6293                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6294         I40E_WRITE_FLUSH(hw);
6295 }
6296
6297 /* Enable IRQ0 */
6298 void
6299 i40e_pf_enable_irq0(struct i40e_hw *hw)
6300 {
6301         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6302                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6303                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6304                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6305         I40E_WRITE_FLUSH(hw);
6306 }
6307
6308 static void
6309 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6310 {
6311         /* read pending request and disable first */
6312         i40e_pf_disable_irq0(hw);
6313         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6314         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6315                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6316
6317         if (no_queue)
6318                 /* Link no queues with irq0 */
6319                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6320                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6321 }
6322
6323 static void
6324 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6325 {
6326         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6327         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6328         int i;
6329         uint16_t abs_vf_id;
6330         uint32_t index, offset, val;
6331
6332         if (!pf->vfs)
6333                 return;
6334         /**
6335          * Try to find which VF trigger a reset, use absolute VF id to access
6336          * since the reg is global register.
6337          */
6338         for (i = 0; i < pf->vf_num; i++) {
6339                 abs_vf_id = hw->func_caps.vf_base_id + i;
6340                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6341                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6342                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6343                 /* VFR event occurred */
6344                 if (val & (0x1 << offset)) {
6345                         int ret;
6346
6347                         /* Clear the event first */
6348                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6349                                                         (0x1 << offset));
6350                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6351                         /**
6352                          * Only notify a VF reset event occurred,
6353                          * don't trigger another SW reset
6354                          */
6355                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6356                         if (ret != I40E_SUCCESS)
6357                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6358                 }
6359         }
6360 }
6361
6362 static void
6363 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6364 {
6365         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6366         int i;
6367
6368         for (i = 0; i < pf->vf_num; i++)
6369                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6370 }
6371
6372 static void
6373 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6374 {
6375         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6376         struct i40e_arq_event_info info;
6377         uint16_t pending, opcode;
6378         int ret;
6379
6380         info.buf_len = I40E_AQ_BUF_SZ;
6381         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6382         if (!info.msg_buf) {
6383                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6384                 return;
6385         }
6386
6387         pending = 1;
6388         while (pending) {
6389                 ret = i40e_clean_arq_element(hw, &info, &pending);
6390
6391                 if (ret != I40E_SUCCESS) {
6392                         PMD_DRV_LOG(INFO,
6393                                 "Failed to read msg from AdminQ, aq_err: %u",
6394                                 hw->aq.asq_last_status);
6395                         break;
6396                 }
6397                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6398
6399                 switch (opcode) {
6400                 case i40e_aqc_opc_send_msg_to_pf:
6401                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6402                         i40e_pf_host_handle_vf_msg(dev,
6403                                         rte_le_to_cpu_16(info.desc.retval),
6404                                         rte_le_to_cpu_32(info.desc.cookie_high),
6405                                         rte_le_to_cpu_32(info.desc.cookie_low),
6406                                         info.msg_buf,
6407                                         info.msg_len);
6408                         break;
6409                 case i40e_aqc_opc_get_link_status:
6410                         ret = i40e_dev_link_update(dev, 0);
6411                         if (!ret)
6412                                 _rte_eth_dev_callback_process(dev,
6413                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6414                         break;
6415                 default:
6416                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6417                                     opcode);
6418                         break;
6419                 }
6420         }
6421         rte_free(info.msg_buf);
6422 }
6423
6424 /**
6425  * Interrupt handler triggered by NIC  for handling
6426  * specific interrupt.
6427  *
6428  * @param handle
6429  *  Pointer to interrupt handle.
6430  * @param param
6431  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6432  *
6433  * @return
6434  *  void
6435  */
6436 static void
6437 i40e_dev_interrupt_handler(void *param)
6438 {
6439         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6440         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6441         uint32_t icr0;
6442
6443         /* Disable interrupt */
6444         i40e_pf_disable_irq0(hw);
6445
6446         /* read out interrupt causes */
6447         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6448
6449         /* No interrupt event indicated */
6450         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6451                 PMD_DRV_LOG(INFO, "No interrupt event");
6452                 goto done;
6453         }
6454         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6455                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6456         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6457                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6458         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6459                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6460         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6461                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6462         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6463                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6464         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6465                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6466         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6467                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6468
6469         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6470                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6471                 i40e_dev_handle_vfr_event(dev);
6472         }
6473         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6474                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6475                 i40e_dev_handle_aq_msg(dev);
6476         }
6477
6478 done:
6479         /* Enable interrupt */
6480         i40e_pf_enable_irq0(hw);
6481         rte_intr_enable(dev->intr_handle);
6482 }
6483
6484 int
6485 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6486                          struct i40e_macvlan_filter *filter,
6487                          int total)
6488 {
6489         int ele_num, ele_buff_size;
6490         int num, actual_num, i;
6491         uint16_t flags;
6492         int ret = I40E_SUCCESS;
6493         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6494         struct i40e_aqc_add_macvlan_element_data *req_list;
6495
6496         if (filter == NULL  || total == 0)
6497                 return I40E_ERR_PARAM;
6498         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6499         ele_buff_size = hw->aq.asq_buf_size;
6500
6501         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6502         if (req_list == NULL) {
6503                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6504                 return I40E_ERR_NO_MEMORY;
6505         }
6506
6507         num = 0;
6508         do {
6509                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6510                 memset(req_list, 0, ele_buff_size);
6511
6512                 for (i = 0; i < actual_num; i++) {
6513                         rte_memcpy(req_list[i].mac_addr,
6514                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6515                         req_list[i].vlan_tag =
6516                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6517
6518                         switch (filter[num + i].filter_type) {
6519                         case RTE_MAC_PERFECT_MATCH:
6520                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6521                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6522                                 break;
6523                         case RTE_MACVLAN_PERFECT_MATCH:
6524                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6525                                 break;
6526                         case RTE_MAC_HASH_MATCH:
6527                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6528                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6529                                 break;
6530                         case RTE_MACVLAN_HASH_MATCH:
6531                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6532                                 break;
6533                         default:
6534                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6535                                 ret = I40E_ERR_PARAM;
6536                                 goto DONE;
6537                         }
6538
6539                         req_list[i].queue_number = 0;
6540
6541                         req_list[i].flags = rte_cpu_to_le_16(flags);
6542                 }
6543
6544                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6545                                                 actual_num, NULL);
6546                 if (ret != I40E_SUCCESS) {
6547                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6548                         goto DONE;
6549                 }
6550                 num += actual_num;
6551         } while (num < total);
6552
6553 DONE:
6554         rte_free(req_list);
6555         return ret;
6556 }
6557
6558 int
6559 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6560                             struct i40e_macvlan_filter *filter,
6561                             int total)
6562 {
6563         int ele_num, ele_buff_size;
6564         int num, actual_num, i;
6565         uint16_t flags;
6566         int ret = I40E_SUCCESS;
6567         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6568         struct i40e_aqc_remove_macvlan_element_data *req_list;
6569
6570         if (filter == NULL  || total == 0)
6571                 return I40E_ERR_PARAM;
6572
6573         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6574         ele_buff_size = hw->aq.asq_buf_size;
6575
6576         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6577         if (req_list == NULL) {
6578                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6579                 return I40E_ERR_NO_MEMORY;
6580         }
6581
6582         num = 0;
6583         do {
6584                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6585                 memset(req_list, 0, ele_buff_size);
6586
6587                 for (i = 0; i < actual_num; i++) {
6588                         rte_memcpy(req_list[i].mac_addr,
6589                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6590                         req_list[i].vlan_tag =
6591                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6592
6593                         switch (filter[num + i].filter_type) {
6594                         case RTE_MAC_PERFECT_MATCH:
6595                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6596                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6597                                 break;
6598                         case RTE_MACVLAN_PERFECT_MATCH:
6599                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6600                                 break;
6601                         case RTE_MAC_HASH_MATCH:
6602                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6603                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6604                                 break;
6605                         case RTE_MACVLAN_HASH_MATCH:
6606                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6607                                 break;
6608                         default:
6609                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6610                                 ret = I40E_ERR_PARAM;
6611                                 goto DONE;
6612                         }
6613                         req_list[i].flags = rte_cpu_to_le_16(flags);
6614                 }
6615
6616                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6617                                                 actual_num, NULL);
6618                 if (ret != I40E_SUCCESS) {
6619                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6620                         goto DONE;
6621                 }
6622                 num += actual_num;
6623         } while (num < total);
6624
6625 DONE:
6626         rte_free(req_list);
6627         return ret;
6628 }
6629
6630 /* Find out specific MAC filter */
6631 static struct i40e_mac_filter *
6632 i40e_find_mac_filter(struct i40e_vsi *vsi,
6633                          struct ether_addr *macaddr)
6634 {
6635         struct i40e_mac_filter *f;
6636
6637         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6638                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6639                         return f;
6640         }
6641
6642         return NULL;
6643 }
6644
6645 static bool
6646 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6647                          uint16_t vlan_id)
6648 {
6649         uint32_t vid_idx, vid_bit;
6650
6651         if (vlan_id > ETH_VLAN_ID_MAX)
6652                 return 0;
6653
6654         vid_idx = I40E_VFTA_IDX(vlan_id);
6655         vid_bit = I40E_VFTA_BIT(vlan_id);
6656
6657         if (vsi->vfta[vid_idx] & vid_bit)
6658                 return 1;
6659         else
6660                 return 0;
6661 }
6662
6663 static void
6664 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6665                        uint16_t vlan_id, bool on)
6666 {
6667         uint32_t vid_idx, vid_bit;
6668
6669         vid_idx = I40E_VFTA_IDX(vlan_id);
6670         vid_bit = I40E_VFTA_BIT(vlan_id);
6671
6672         if (on)
6673                 vsi->vfta[vid_idx] |= vid_bit;
6674         else
6675                 vsi->vfta[vid_idx] &= ~vid_bit;
6676 }
6677
6678 void
6679 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6680                      uint16_t vlan_id, bool on)
6681 {
6682         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6683         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6684         int ret;
6685
6686         if (vlan_id > ETH_VLAN_ID_MAX)
6687                 return;
6688
6689         i40e_store_vlan_filter(vsi, vlan_id, on);
6690
6691         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6692                 return;
6693
6694         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6695
6696         if (on) {
6697                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6698                                        &vlan_data, 1, NULL);
6699                 if (ret != I40E_SUCCESS)
6700                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6701         } else {
6702                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6703                                           &vlan_data, 1, NULL);
6704                 if (ret != I40E_SUCCESS)
6705                         PMD_DRV_LOG(ERR,
6706                                     "Failed to remove vlan filter");
6707         }
6708 }
6709
6710 /**
6711  * Find all vlan options for specific mac addr,
6712  * return with actual vlan found.
6713  */
6714 int
6715 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6716                            struct i40e_macvlan_filter *mv_f,
6717                            int num, struct ether_addr *addr)
6718 {
6719         int i;
6720         uint32_t j, k;
6721
6722         /**
6723          * Not to use i40e_find_vlan_filter to decrease the loop time,
6724          * although the code looks complex.
6725           */
6726         if (num < vsi->vlan_num)
6727                 return I40E_ERR_PARAM;
6728
6729         i = 0;
6730         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6731                 if (vsi->vfta[j]) {
6732                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6733                                 if (vsi->vfta[j] & (1 << k)) {
6734                                         if (i > num - 1) {
6735                                                 PMD_DRV_LOG(ERR,
6736                                                         "vlan number doesn't match");
6737                                                 return I40E_ERR_PARAM;
6738                                         }
6739                                         rte_memcpy(&mv_f[i].macaddr,
6740                                                         addr, ETH_ADDR_LEN);
6741                                         mv_f[i].vlan_id =
6742                                                 j * I40E_UINT32_BIT_SIZE + k;
6743                                         i++;
6744                                 }
6745                         }
6746                 }
6747         }
6748         return I40E_SUCCESS;
6749 }
6750
6751 static inline int
6752 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6753                            struct i40e_macvlan_filter *mv_f,
6754                            int num,
6755                            uint16_t vlan)
6756 {
6757         int i = 0;
6758         struct i40e_mac_filter *f;
6759
6760         if (num < vsi->mac_num)
6761                 return I40E_ERR_PARAM;
6762
6763         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6764                 if (i > num - 1) {
6765                         PMD_DRV_LOG(ERR, "buffer number not match");
6766                         return I40E_ERR_PARAM;
6767                 }
6768                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6769                                 ETH_ADDR_LEN);
6770                 mv_f[i].vlan_id = vlan;
6771                 mv_f[i].filter_type = f->mac_info.filter_type;
6772                 i++;
6773         }
6774
6775         return I40E_SUCCESS;
6776 }
6777
6778 static int
6779 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6780 {
6781         int i, j, num;
6782         struct i40e_mac_filter *f;
6783         struct i40e_macvlan_filter *mv_f;
6784         int ret = I40E_SUCCESS;
6785
6786         if (vsi == NULL || vsi->mac_num == 0)
6787                 return I40E_ERR_PARAM;
6788
6789         /* Case that no vlan is set */
6790         if (vsi->vlan_num == 0)
6791                 num = vsi->mac_num;
6792         else
6793                 num = vsi->mac_num * vsi->vlan_num;
6794
6795         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6796         if (mv_f == NULL) {
6797                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6798                 return I40E_ERR_NO_MEMORY;
6799         }
6800
6801         i = 0;
6802         if (vsi->vlan_num == 0) {
6803                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6804                         rte_memcpy(&mv_f[i].macaddr,
6805                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6806                         mv_f[i].filter_type = f->mac_info.filter_type;
6807                         mv_f[i].vlan_id = 0;
6808                         i++;
6809                 }
6810         } else {
6811                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6812                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6813                                         vsi->vlan_num, &f->mac_info.mac_addr);
6814                         if (ret != I40E_SUCCESS)
6815                                 goto DONE;
6816                         for (j = i; j < i + vsi->vlan_num; j++)
6817                                 mv_f[j].filter_type = f->mac_info.filter_type;
6818                         i += vsi->vlan_num;
6819                 }
6820         }
6821
6822         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6823 DONE:
6824         rte_free(mv_f);
6825
6826         return ret;
6827 }
6828
6829 int
6830 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6831 {
6832         struct i40e_macvlan_filter *mv_f;
6833         int mac_num;
6834         int ret = I40E_SUCCESS;
6835
6836         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6837                 return I40E_ERR_PARAM;
6838
6839         /* If it's already set, just return */
6840         if (i40e_find_vlan_filter(vsi,vlan))
6841                 return I40E_SUCCESS;
6842
6843         mac_num = vsi->mac_num;
6844
6845         if (mac_num == 0) {
6846                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6847                 return I40E_ERR_PARAM;
6848         }
6849
6850         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6851
6852         if (mv_f == NULL) {
6853                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6854                 return I40E_ERR_NO_MEMORY;
6855         }
6856
6857         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6858
6859         if (ret != I40E_SUCCESS)
6860                 goto DONE;
6861
6862         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6863
6864         if (ret != I40E_SUCCESS)
6865                 goto DONE;
6866
6867         i40e_set_vlan_filter(vsi, vlan, 1);
6868
6869         vsi->vlan_num++;
6870         ret = I40E_SUCCESS;
6871 DONE:
6872         rte_free(mv_f);
6873         return ret;
6874 }
6875
6876 int
6877 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6878 {
6879         struct i40e_macvlan_filter *mv_f;
6880         int mac_num;
6881         int ret = I40E_SUCCESS;
6882
6883         /**
6884          * Vlan 0 is the generic filter for untagged packets
6885          * and can't be removed.
6886          */
6887         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6888                 return I40E_ERR_PARAM;
6889
6890         /* If can't find it, just return */
6891         if (!i40e_find_vlan_filter(vsi, vlan))
6892                 return I40E_ERR_PARAM;
6893
6894         mac_num = vsi->mac_num;
6895
6896         if (mac_num == 0) {
6897                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6898                 return I40E_ERR_PARAM;
6899         }
6900
6901         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6902
6903         if (mv_f == NULL) {
6904                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6905                 return I40E_ERR_NO_MEMORY;
6906         }
6907
6908         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6909
6910         if (ret != I40E_SUCCESS)
6911                 goto DONE;
6912
6913         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6914
6915         if (ret != I40E_SUCCESS)
6916                 goto DONE;
6917
6918         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6919         if (vsi->vlan_num == 1) {
6920                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6921                 if (ret != I40E_SUCCESS)
6922                         goto DONE;
6923
6924                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6925                 if (ret != I40E_SUCCESS)
6926                         goto DONE;
6927         }
6928
6929         i40e_set_vlan_filter(vsi, vlan, 0);
6930
6931         vsi->vlan_num--;
6932         ret = I40E_SUCCESS;
6933 DONE:
6934         rte_free(mv_f);
6935         return ret;
6936 }
6937
6938 int
6939 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6940 {
6941         struct i40e_mac_filter *f;
6942         struct i40e_macvlan_filter *mv_f;
6943         int i, vlan_num = 0;
6944         int ret = I40E_SUCCESS;
6945
6946         /* If it's add and we've config it, return */
6947         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6948         if (f != NULL)
6949                 return I40E_SUCCESS;
6950         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6951                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6952
6953                 /**
6954                  * If vlan_num is 0, that's the first time to add mac,
6955                  * set mask for vlan_id 0.
6956                  */
6957                 if (vsi->vlan_num == 0) {
6958                         i40e_set_vlan_filter(vsi, 0, 1);
6959                         vsi->vlan_num = 1;
6960                 }
6961                 vlan_num = vsi->vlan_num;
6962         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6963                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6964                 vlan_num = 1;
6965
6966         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6967         if (mv_f == NULL) {
6968                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6969                 return I40E_ERR_NO_MEMORY;
6970         }
6971
6972         for (i = 0; i < vlan_num; i++) {
6973                 mv_f[i].filter_type = mac_filter->filter_type;
6974                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6975                                 ETH_ADDR_LEN);
6976         }
6977
6978         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6979                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6980                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6981                                         &mac_filter->mac_addr);
6982                 if (ret != I40E_SUCCESS)
6983                         goto DONE;
6984         }
6985
6986         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6987         if (ret != I40E_SUCCESS)
6988                 goto DONE;
6989
6990         /* Add the mac addr into mac list */
6991         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6992         if (f == NULL) {
6993                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6994                 ret = I40E_ERR_NO_MEMORY;
6995                 goto DONE;
6996         }
6997         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6998                         ETH_ADDR_LEN);
6999         f->mac_info.filter_type = mac_filter->filter_type;
7000         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7001         vsi->mac_num++;
7002
7003         ret = I40E_SUCCESS;
7004 DONE:
7005         rte_free(mv_f);
7006
7007         return ret;
7008 }
7009
7010 int
7011 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7012 {
7013         struct i40e_mac_filter *f;
7014         struct i40e_macvlan_filter *mv_f;
7015         int i, vlan_num;
7016         enum rte_mac_filter_type filter_type;
7017         int ret = I40E_SUCCESS;
7018
7019         /* Can't find it, return an error */
7020         f = i40e_find_mac_filter(vsi, addr);
7021         if (f == NULL)
7022                 return I40E_ERR_PARAM;
7023
7024         vlan_num = vsi->vlan_num;
7025         filter_type = f->mac_info.filter_type;
7026         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7027                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7028                 if (vlan_num == 0) {
7029                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7030                         return I40E_ERR_PARAM;
7031                 }
7032         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7033                         filter_type == RTE_MAC_HASH_MATCH)
7034                 vlan_num = 1;
7035
7036         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7037         if (mv_f == NULL) {
7038                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7039                 return I40E_ERR_NO_MEMORY;
7040         }
7041
7042         for (i = 0; i < vlan_num; i++) {
7043                 mv_f[i].filter_type = filter_type;
7044                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7045                                 ETH_ADDR_LEN);
7046         }
7047         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7048                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7049                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7050                 if (ret != I40E_SUCCESS)
7051                         goto DONE;
7052         }
7053
7054         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7055         if (ret != I40E_SUCCESS)
7056                 goto DONE;
7057
7058         /* Remove the mac addr into mac list */
7059         TAILQ_REMOVE(&vsi->mac_list, f, next);
7060         rte_free(f);
7061         vsi->mac_num--;
7062
7063         ret = I40E_SUCCESS;
7064 DONE:
7065         rte_free(mv_f);
7066         return ret;
7067 }
7068
7069 /* Configure hash enable flags for RSS */
7070 uint64_t
7071 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7072 {
7073         uint64_t hena = 0;
7074         int i;
7075
7076         if (!flags)
7077                 return hena;
7078
7079         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7080                 if (flags & (1ULL << i))
7081                         hena |= adapter->pctypes_tbl[i];
7082         }
7083
7084         return hena;
7085 }
7086
7087 /* Parse the hash enable flags */
7088 uint64_t
7089 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7090 {
7091         uint64_t rss_hf = 0;
7092
7093         if (!flags)
7094                 return rss_hf;
7095         int i;
7096
7097         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7098                 if (flags & adapter->pctypes_tbl[i])
7099                         rss_hf |= (1ULL << i);
7100         }
7101         return rss_hf;
7102 }
7103
7104 /* Disable RSS */
7105 static void
7106 i40e_pf_disable_rss(struct i40e_pf *pf)
7107 {
7108         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7109
7110         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7111         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7112         I40E_WRITE_FLUSH(hw);
7113 }
7114
7115 int
7116 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7117 {
7118         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7119         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7120         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7121                            I40E_VFQF_HKEY_MAX_INDEX :
7122                            I40E_PFQF_HKEY_MAX_INDEX;
7123         int ret = 0;
7124
7125         if (!key || key_len == 0) {
7126                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7127                 return 0;
7128         } else if (key_len != (key_idx + 1) *
7129                 sizeof(uint32_t)) {
7130                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7131                 return -EINVAL;
7132         }
7133
7134         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7135                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7136                         (struct i40e_aqc_get_set_rss_key_data *)key;
7137
7138                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7139                 if (ret)
7140                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7141         } else {
7142                 uint32_t *hash_key = (uint32_t *)key;
7143                 uint16_t i;
7144
7145                 if (vsi->type == I40E_VSI_SRIOV) {
7146                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7147                                 I40E_WRITE_REG(
7148                                         hw,
7149                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7150                                         hash_key[i]);
7151
7152                 } else {
7153                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7154                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7155                                                hash_key[i]);
7156                 }
7157                 I40E_WRITE_FLUSH(hw);
7158         }
7159
7160         return ret;
7161 }
7162
7163 static int
7164 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7165 {
7166         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7167         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7168         uint32_t reg;
7169         int ret;
7170
7171         if (!key || !key_len)
7172                 return -EINVAL;
7173
7174         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7175                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7176                         (struct i40e_aqc_get_set_rss_key_data *)key);
7177                 if (ret) {
7178                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7179                         return ret;
7180                 }
7181         } else {
7182                 uint32_t *key_dw = (uint32_t *)key;
7183                 uint16_t i;
7184
7185                 if (vsi->type == I40E_VSI_SRIOV) {
7186                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7187                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7188                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7189                         }
7190                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7191                                    sizeof(uint32_t);
7192                 } else {
7193                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7194                                 reg = I40E_PFQF_HKEY(i);
7195                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7196                         }
7197                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7198                                    sizeof(uint32_t);
7199                 }
7200         }
7201         return 0;
7202 }
7203
7204 static int
7205 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7206 {
7207         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7208         uint64_t hena;
7209         int ret;
7210
7211         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7212                                rss_conf->rss_key_len);
7213         if (ret)
7214                 return ret;
7215
7216         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7217         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7218         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7219         I40E_WRITE_FLUSH(hw);
7220
7221         return 0;
7222 }
7223
7224 static int
7225 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7226                          struct rte_eth_rss_conf *rss_conf)
7227 {
7228         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7229         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7230         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7231         uint64_t hena;
7232
7233         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7234         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7235
7236         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7237                 if (rss_hf != 0) /* Enable RSS */
7238                         return -EINVAL;
7239                 return 0; /* Nothing to do */
7240         }
7241         /* RSS enabled */
7242         if (rss_hf == 0) /* Disable RSS */
7243                 return -EINVAL;
7244
7245         return i40e_hw_rss_hash_set(pf, rss_conf);
7246 }
7247
7248 static int
7249 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7250                            struct rte_eth_rss_conf *rss_conf)
7251 {
7252         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7253         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7254         uint64_t hena;
7255
7256         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7257                          &rss_conf->rss_key_len);
7258
7259         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7260         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7261         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7262
7263         return 0;
7264 }
7265
7266 static int
7267 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7268 {
7269         switch (filter_type) {
7270         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7271                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7272                 break;
7273         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7274                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7275                 break;
7276         case RTE_TUNNEL_FILTER_IMAC_TENID:
7277                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7278                 break;
7279         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7280                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7281                 break;
7282         case ETH_TUNNEL_FILTER_IMAC:
7283                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7284                 break;
7285         case ETH_TUNNEL_FILTER_OIP:
7286                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7287                 break;
7288         case ETH_TUNNEL_FILTER_IIP:
7289                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7290                 break;
7291         default:
7292                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7293                 return -EINVAL;
7294         }
7295
7296         return 0;
7297 }
7298
7299 /* Convert tunnel filter structure */
7300 static int
7301 i40e_tunnel_filter_convert(
7302         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7303         struct i40e_tunnel_filter *tunnel_filter)
7304 {
7305         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7306                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7307         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7308                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7309         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7310         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7311              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7312             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7313                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7314         else
7315                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7316         tunnel_filter->input.flags = cld_filter->element.flags;
7317         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7318         tunnel_filter->queue = cld_filter->element.queue_number;
7319         rte_memcpy(tunnel_filter->input.general_fields,
7320                    cld_filter->general_fields,
7321                    sizeof(cld_filter->general_fields));
7322
7323         return 0;
7324 }
7325
7326 /* Check if there exists the tunnel filter */
7327 struct i40e_tunnel_filter *
7328 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7329                              const struct i40e_tunnel_filter_input *input)
7330 {
7331         int ret;
7332
7333         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7334         if (ret < 0)
7335                 return NULL;
7336
7337         return tunnel_rule->hash_map[ret];
7338 }
7339
7340 /* Add a tunnel filter into the SW list */
7341 static int
7342 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7343                              struct i40e_tunnel_filter *tunnel_filter)
7344 {
7345         struct i40e_tunnel_rule *rule = &pf->tunnel;
7346         int ret;
7347
7348         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7349         if (ret < 0) {
7350                 PMD_DRV_LOG(ERR,
7351                             "Failed to insert tunnel filter to hash table %d!",
7352                             ret);
7353                 return ret;
7354         }
7355         rule->hash_map[ret] = tunnel_filter;
7356
7357         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7358
7359         return 0;
7360 }
7361
7362 /* Delete a tunnel filter from the SW list */
7363 int
7364 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7365                           struct i40e_tunnel_filter_input *input)
7366 {
7367         struct i40e_tunnel_rule *rule = &pf->tunnel;
7368         struct i40e_tunnel_filter *tunnel_filter;
7369         int ret;
7370
7371         ret = rte_hash_del_key(rule->hash_table, input);
7372         if (ret < 0) {
7373                 PMD_DRV_LOG(ERR,
7374                             "Failed to delete tunnel filter to hash table %d!",
7375                             ret);
7376                 return ret;
7377         }
7378         tunnel_filter = rule->hash_map[ret];
7379         rule->hash_map[ret] = NULL;
7380
7381         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7382         rte_free(tunnel_filter);
7383
7384         return 0;
7385 }
7386
7387 int
7388 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7389                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7390                         uint8_t add)
7391 {
7392         uint16_t ip_type;
7393         uint32_t ipv4_addr, ipv4_addr_le;
7394         uint8_t i, tun_type = 0;
7395         /* internal varialbe to convert ipv6 byte order */
7396         uint32_t convert_ipv6[4];
7397         int val, ret = 0;
7398         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7399         struct i40e_vsi *vsi = pf->main_vsi;
7400         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7401         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7402         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7403         struct i40e_tunnel_filter *tunnel, *node;
7404         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7405
7406         cld_filter = rte_zmalloc("tunnel_filter",
7407                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7408         0);
7409
7410         if (NULL == cld_filter) {
7411                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7412                 return -ENOMEM;
7413         }
7414         pfilter = cld_filter;
7415
7416         ether_addr_copy(&tunnel_filter->outer_mac,
7417                         (struct ether_addr *)&pfilter->element.outer_mac);
7418         ether_addr_copy(&tunnel_filter->inner_mac,
7419                         (struct ether_addr *)&pfilter->element.inner_mac);
7420
7421         pfilter->element.inner_vlan =
7422                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7423         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7424                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7425                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7426                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7427                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7428                                 &ipv4_addr_le,
7429                                 sizeof(pfilter->element.ipaddr.v4.data));
7430         } else {
7431                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7432                 for (i = 0; i < 4; i++) {
7433                         convert_ipv6[i] =
7434                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7435                 }
7436                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7437                            &convert_ipv6,
7438                            sizeof(pfilter->element.ipaddr.v6.data));
7439         }
7440
7441         /* check tunneled type */
7442         switch (tunnel_filter->tunnel_type) {
7443         case RTE_TUNNEL_TYPE_VXLAN:
7444                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7445                 break;
7446         case RTE_TUNNEL_TYPE_NVGRE:
7447                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7448                 break;
7449         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7450                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7451                 break;
7452         default:
7453                 /* Other tunnel types is not supported. */
7454                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7455                 rte_free(cld_filter);
7456                 return -EINVAL;
7457         }
7458
7459         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7460                                        &pfilter->element.flags);
7461         if (val < 0) {
7462                 rte_free(cld_filter);
7463                 return -EINVAL;
7464         }
7465
7466         pfilter->element.flags |= rte_cpu_to_le_16(
7467                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7468                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7469         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7470         pfilter->element.queue_number =
7471                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7472
7473         /* Check if there is the filter in SW list */
7474         memset(&check_filter, 0, sizeof(check_filter));
7475         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7476         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7477         if (add && node) {
7478                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7479                 rte_free(cld_filter);
7480                 return -EINVAL;
7481         }
7482
7483         if (!add && !node) {
7484                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7485                 rte_free(cld_filter);
7486                 return -EINVAL;
7487         }
7488
7489         if (add) {
7490                 ret = i40e_aq_add_cloud_filters(hw,
7491                                         vsi->seid, &cld_filter->element, 1);
7492                 if (ret < 0) {
7493                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7494                         rte_free(cld_filter);
7495                         return -ENOTSUP;
7496                 }
7497                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7498                 if (tunnel == NULL) {
7499                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7500                         rte_free(cld_filter);
7501                         return -ENOMEM;
7502                 }
7503
7504                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7505                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7506                 if (ret < 0)
7507                         rte_free(tunnel);
7508         } else {
7509                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7510                                                    &cld_filter->element, 1);
7511                 if (ret < 0) {
7512                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7513                         rte_free(cld_filter);
7514                         return -ENOTSUP;
7515                 }
7516                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7517         }
7518
7519         rte_free(cld_filter);
7520         return ret;
7521 }
7522
7523 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7524 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7525 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7526 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7527 #define I40E_TR_GRE_KEY_MASK                    0x400
7528 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7529 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7530
7531 static enum
7532 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7533 {
7534         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7535         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7536         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7537         enum i40e_status_code status = I40E_SUCCESS;
7538
7539         if (pf->support_multi_driver) {
7540                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7541                 return I40E_NOT_SUPPORTED;
7542         }
7543
7544         memset(&filter_replace, 0,
7545                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7546         memset(&filter_replace_buf, 0,
7547                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7548
7549         /* create L1 filter */
7550         filter_replace.old_filter_type =
7551                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7552         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7553         filter_replace.tr_bit = 0;
7554
7555         /* Prepare the buffer, 3 entries */
7556         filter_replace_buf.data[0] =
7557                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7558         filter_replace_buf.data[0] |=
7559                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7560         filter_replace_buf.data[2] = 0xFF;
7561         filter_replace_buf.data[3] = 0xFF;
7562         filter_replace_buf.data[4] =
7563                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7564         filter_replace_buf.data[4] |=
7565                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7566         filter_replace_buf.data[7] = 0xF0;
7567         filter_replace_buf.data[8]
7568                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7569         filter_replace_buf.data[8] |=
7570                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7571         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7572                 I40E_TR_GENEVE_KEY_MASK |
7573                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7574         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7575                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7576                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7577
7578         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7579                                                &filter_replace_buf);
7580         if (!status) {
7581                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7582                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7583                             "cloud l1 type is changed from 0x%x to 0x%x",
7584                             filter_replace.old_filter_type,
7585                             filter_replace.new_filter_type);
7586         }
7587         return status;
7588 }
7589
7590 static enum
7591 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7592 {
7593         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7594         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7595         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7596         enum i40e_status_code status = I40E_SUCCESS;
7597
7598         if (pf->support_multi_driver) {
7599                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7600                 return I40E_NOT_SUPPORTED;
7601         }
7602
7603         /* For MPLSoUDP */
7604         memset(&filter_replace, 0,
7605                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7606         memset(&filter_replace_buf, 0,
7607                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7608         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7609                 I40E_AQC_MIRROR_CLOUD_FILTER;
7610         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7611         filter_replace.new_filter_type =
7612                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7613         /* Prepare the buffer, 2 entries */
7614         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7615         filter_replace_buf.data[0] |=
7616                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7617         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7618         filter_replace_buf.data[4] |=
7619                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7620         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7621                                                &filter_replace_buf);
7622         if (status < 0)
7623                 return status;
7624         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7625                     "cloud filter type is changed from 0x%x to 0x%x",
7626                     filter_replace.old_filter_type,
7627                     filter_replace.new_filter_type);
7628
7629         /* For MPLSoGRE */
7630         memset(&filter_replace, 0,
7631                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7632         memset(&filter_replace_buf, 0,
7633                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7634
7635         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7636                 I40E_AQC_MIRROR_CLOUD_FILTER;
7637         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7638         filter_replace.new_filter_type =
7639                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7640         /* Prepare the buffer, 2 entries */
7641         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7642         filter_replace_buf.data[0] |=
7643                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7644         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7645         filter_replace_buf.data[4] |=
7646                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7647
7648         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7649                                                &filter_replace_buf);
7650         if (!status) {
7651                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7652                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7653                             "cloud filter type is changed from 0x%x to 0x%x",
7654                             filter_replace.old_filter_type,
7655                             filter_replace.new_filter_type);
7656         }
7657         return status;
7658 }
7659
7660 static enum i40e_status_code
7661 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7662 {
7663         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7664         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7665         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7666         enum i40e_status_code status = I40E_SUCCESS;
7667
7668         if (pf->support_multi_driver) {
7669                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7670                 return I40E_NOT_SUPPORTED;
7671         }
7672
7673         /* For GTP-C */
7674         memset(&filter_replace, 0,
7675                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7676         memset(&filter_replace_buf, 0,
7677                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7678         /* create L1 filter */
7679         filter_replace.old_filter_type =
7680                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7681         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7682         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7683                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7684         /* Prepare the buffer, 2 entries */
7685         filter_replace_buf.data[0] =
7686                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7687         filter_replace_buf.data[0] |=
7688                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7689         filter_replace_buf.data[2] = 0xFF;
7690         filter_replace_buf.data[3] = 0xFF;
7691         filter_replace_buf.data[4] =
7692                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7693         filter_replace_buf.data[4] |=
7694                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7695         filter_replace_buf.data[6] = 0xFF;
7696         filter_replace_buf.data[7] = 0xFF;
7697         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7698                                                &filter_replace_buf);
7699         if (status < 0)
7700                 return status;
7701         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7702                     "cloud l1 type is changed from 0x%x to 0x%x",
7703                     filter_replace.old_filter_type,
7704                     filter_replace.new_filter_type);
7705
7706         /* for GTP-U */
7707         memset(&filter_replace, 0,
7708                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7709         memset(&filter_replace_buf, 0,
7710                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7711         /* create L1 filter */
7712         filter_replace.old_filter_type =
7713                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7714         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7715         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7716                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7717         /* Prepare the buffer, 2 entries */
7718         filter_replace_buf.data[0] =
7719                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7720         filter_replace_buf.data[0] |=
7721                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7722         filter_replace_buf.data[2] = 0xFF;
7723         filter_replace_buf.data[3] = 0xFF;
7724         filter_replace_buf.data[4] =
7725                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7726         filter_replace_buf.data[4] |=
7727                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7728         filter_replace_buf.data[6] = 0xFF;
7729         filter_replace_buf.data[7] = 0xFF;
7730
7731         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7732                                                &filter_replace_buf);
7733         if (!status) {
7734                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7735                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7736                             "cloud l1 type is changed from 0x%x to 0x%x",
7737                             filter_replace.old_filter_type,
7738                             filter_replace.new_filter_type);
7739         }
7740         return status;
7741 }
7742
7743 static enum
7744 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7745 {
7746         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7747         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7748         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7749         enum i40e_status_code status = I40E_SUCCESS;
7750
7751         if (pf->support_multi_driver) {
7752                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7753                 return I40E_NOT_SUPPORTED;
7754         }
7755
7756         /* for GTP-C */
7757         memset(&filter_replace, 0,
7758                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7759         memset(&filter_replace_buf, 0,
7760                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7761         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7762         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7763         filter_replace.new_filter_type =
7764                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7765         /* Prepare the buffer, 2 entries */
7766         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7767         filter_replace_buf.data[0] |=
7768                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7769         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7770         filter_replace_buf.data[4] |=
7771                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7772         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7773                                                &filter_replace_buf);
7774         if (status < 0)
7775                 return status;
7776         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7777                     "cloud filter type is changed from 0x%x to 0x%x",
7778                     filter_replace.old_filter_type,
7779                     filter_replace.new_filter_type);
7780
7781         /* for GTP-U */
7782         memset(&filter_replace, 0,
7783                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7784         memset(&filter_replace_buf, 0,
7785                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7786         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7787         filter_replace.old_filter_type =
7788                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7789         filter_replace.new_filter_type =
7790                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7791         /* Prepare the buffer, 2 entries */
7792         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7793         filter_replace_buf.data[0] |=
7794                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7795         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7796         filter_replace_buf.data[4] |=
7797                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7798
7799         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7800                                                &filter_replace_buf);
7801         if (!status) {
7802                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7803                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7804                             "cloud filter type is changed from 0x%x to 0x%x",
7805                             filter_replace.old_filter_type,
7806                             filter_replace.new_filter_type);
7807         }
7808         return status;
7809 }
7810
7811 int
7812 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7813                       struct i40e_tunnel_filter_conf *tunnel_filter,
7814                       uint8_t add)
7815 {
7816         uint16_t ip_type;
7817         uint32_t ipv4_addr, ipv4_addr_le;
7818         uint8_t i, tun_type = 0;
7819         /* internal variable to convert ipv6 byte order */
7820         uint32_t convert_ipv6[4];
7821         int val, ret = 0;
7822         struct i40e_pf_vf *vf = NULL;
7823         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7824         struct i40e_vsi *vsi;
7825         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7826         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7827         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7828         struct i40e_tunnel_filter *tunnel, *node;
7829         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7830         uint32_t teid_le;
7831         bool big_buffer = 0;
7832
7833         cld_filter = rte_zmalloc("tunnel_filter",
7834                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7835                          0);
7836
7837         if (cld_filter == NULL) {
7838                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7839                 return -ENOMEM;
7840         }
7841         pfilter = cld_filter;
7842
7843         ether_addr_copy(&tunnel_filter->outer_mac,
7844                         (struct ether_addr *)&pfilter->element.outer_mac);
7845         ether_addr_copy(&tunnel_filter->inner_mac,
7846                         (struct ether_addr *)&pfilter->element.inner_mac);
7847
7848         pfilter->element.inner_vlan =
7849                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7850         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7851                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7852                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7853                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7854                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7855                                 &ipv4_addr_le,
7856                                 sizeof(pfilter->element.ipaddr.v4.data));
7857         } else {
7858                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7859                 for (i = 0; i < 4; i++) {
7860                         convert_ipv6[i] =
7861                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7862                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7863                 }
7864                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7865                            &convert_ipv6,
7866                            sizeof(pfilter->element.ipaddr.v6.data));
7867         }
7868
7869         /* check tunneled type */
7870         switch (tunnel_filter->tunnel_type) {
7871         case I40E_TUNNEL_TYPE_VXLAN:
7872                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7873                 break;
7874         case I40E_TUNNEL_TYPE_NVGRE:
7875                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7876                 break;
7877         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7878                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7879                 break;
7880         case I40E_TUNNEL_TYPE_MPLSoUDP:
7881                 if (!pf->mpls_replace_flag) {
7882                         i40e_replace_mpls_l1_filter(pf);
7883                         i40e_replace_mpls_cloud_filter(pf);
7884                         pf->mpls_replace_flag = 1;
7885                 }
7886                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7887                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7888                         teid_le >> 4;
7889                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7890                         (teid_le & 0xF) << 12;
7891                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7892                         0x40;
7893                 big_buffer = 1;
7894                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7895                 break;
7896         case I40E_TUNNEL_TYPE_MPLSoGRE:
7897                 if (!pf->mpls_replace_flag) {
7898                         i40e_replace_mpls_l1_filter(pf);
7899                         i40e_replace_mpls_cloud_filter(pf);
7900                         pf->mpls_replace_flag = 1;
7901                 }
7902                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7903                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7904                         teid_le >> 4;
7905                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7906                         (teid_le & 0xF) << 12;
7907                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7908                         0x0;
7909                 big_buffer = 1;
7910                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7911                 break;
7912         case I40E_TUNNEL_TYPE_GTPC:
7913                 if (!pf->gtp_replace_flag) {
7914                         i40e_replace_gtp_l1_filter(pf);
7915                         i40e_replace_gtp_cloud_filter(pf);
7916                         pf->gtp_replace_flag = 1;
7917                 }
7918                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7919                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7920                         (teid_le >> 16) & 0xFFFF;
7921                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7922                         teid_le & 0xFFFF;
7923                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7924                         0x0;
7925                 big_buffer = 1;
7926                 break;
7927         case I40E_TUNNEL_TYPE_GTPU:
7928                 if (!pf->gtp_replace_flag) {
7929                         i40e_replace_gtp_l1_filter(pf);
7930                         i40e_replace_gtp_cloud_filter(pf);
7931                         pf->gtp_replace_flag = 1;
7932                 }
7933                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7934                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7935                         (teid_le >> 16) & 0xFFFF;
7936                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7937                         teid_le & 0xFFFF;
7938                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7939                         0x0;
7940                 big_buffer = 1;
7941                 break;
7942         case I40E_TUNNEL_TYPE_QINQ:
7943                 if (!pf->qinq_replace_flag) {
7944                         ret = i40e_cloud_filter_qinq_create(pf);
7945                         if (ret < 0)
7946                                 PMD_DRV_LOG(DEBUG,
7947                                             "QinQ tunnel filter already created.");
7948                         pf->qinq_replace_flag = 1;
7949                 }
7950                 /*      Add in the General fields the values of
7951                  *      the Outer and Inner VLAN
7952                  *      Big Buffer should be set, see changes in
7953                  *      i40e_aq_add_cloud_filters
7954                  */
7955                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7956                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7957                 big_buffer = 1;
7958                 break;
7959         default:
7960                 /* Other tunnel types is not supported. */
7961                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7962                 rte_free(cld_filter);
7963                 return -EINVAL;
7964         }
7965
7966         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7967                 pfilter->element.flags =
7968                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7969         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7970                 pfilter->element.flags =
7971                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7972         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7973                 pfilter->element.flags =
7974                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7975         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7976                 pfilter->element.flags =
7977                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7978         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7979                 pfilter->element.flags |=
7980                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7981         else {
7982                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7983                                                 &pfilter->element.flags);
7984                 if (val < 0) {
7985                         rte_free(cld_filter);
7986                         return -EINVAL;
7987                 }
7988         }
7989
7990         pfilter->element.flags |= rte_cpu_to_le_16(
7991                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7992                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7993         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7994         pfilter->element.queue_number =
7995                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7996
7997         if (!tunnel_filter->is_to_vf)
7998                 vsi = pf->main_vsi;
7999         else {
8000                 if (tunnel_filter->vf_id >= pf->vf_num) {
8001                         PMD_DRV_LOG(ERR, "Invalid argument.");
8002                         rte_free(cld_filter);
8003                         return -EINVAL;
8004                 }
8005                 vf = &pf->vfs[tunnel_filter->vf_id];
8006                 vsi = vf->vsi;
8007         }
8008
8009         /* Check if there is the filter in SW list */
8010         memset(&check_filter, 0, sizeof(check_filter));
8011         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8012         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8013         check_filter.vf_id = tunnel_filter->vf_id;
8014         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8015         if (add && node) {
8016                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8017                 rte_free(cld_filter);
8018                 return -EINVAL;
8019         }
8020
8021         if (!add && !node) {
8022                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8023                 rte_free(cld_filter);
8024                 return -EINVAL;
8025         }
8026
8027         if (add) {
8028                 if (big_buffer)
8029                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
8030                                                    vsi->seid, cld_filter, 1);
8031                 else
8032                         ret = i40e_aq_add_cloud_filters(hw,
8033                                         vsi->seid, &cld_filter->element, 1);
8034                 if (ret < 0) {
8035                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8036                         rte_free(cld_filter);
8037                         return -ENOTSUP;
8038                 }
8039                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8040                 if (tunnel == NULL) {
8041                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8042                         rte_free(cld_filter);
8043                         return -ENOMEM;
8044                 }
8045
8046                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8047                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8048                 if (ret < 0)
8049                         rte_free(tunnel);
8050         } else {
8051                 if (big_buffer)
8052                         ret = i40e_aq_remove_cloud_filters_big_buffer(
8053                                 hw, vsi->seid, cld_filter, 1);
8054                 else
8055                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
8056                                                    &cld_filter->element, 1);
8057                 if (ret < 0) {
8058                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8059                         rte_free(cld_filter);
8060                         return -ENOTSUP;
8061                 }
8062                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8063         }
8064
8065         rte_free(cld_filter);
8066         return ret;
8067 }
8068
8069 static int
8070 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8071 {
8072         uint8_t i;
8073
8074         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8075                 if (pf->vxlan_ports[i] == port)
8076                         return i;
8077         }
8078
8079         return -1;
8080 }
8081
8082 static int
8083 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8084 {
8085         int  idx, ret;
8086         uint8_t filter_idx;
8087         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8088
8089         idx = i40e_get_vxlan_port_idx(pf, port);
8090
8091         /* Check if port already exists */
8092         if (idx >= 0) {
8093                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8094                 return -EINVAL;
8095         }
8096
8097         /* Now check if there is space to add the new port */
8098         idx = i40e_get_vxlan_port_idx(pf, 0);
8099         if (idx < 0) {
8100                 PMD_DRV_LOG(ERR,
8101                         "Maximum number of UDP ports reached, not adding port %d",
8102                         port);
8103                 return -ENOSPC;
8104         }
8105
8106         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8107                                         &filter_idx, NULL);
8108         if (ret < 0) {
8109                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8110                 return -1;
8111         }
8112
8113         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8114                          port,  filter_idx);
8115
8116         /* New port: add it and mark its index in the bitmap */
8117         pf->vxlan_ports[idx] = port;
8118         pf->vxlan_bitmap |= (1 << idx);
8119
8120         if (!(pf->flags & I40E_FLAG_VXLAN))
8121                 pf->flags |= I40E_FLAG_VXLAN;
8122
8123         return 0;
8124 }
8125
8126 static int
8127 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8128 {
8129         int idx;
8130         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8131
8132         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8133                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8134                 return -EINVAL;
8135         }
8136
8137         idx = i40e_get_vxlan_port_idx(pf, port);
8138
8139         if (idx < 0) {
8140                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8141                 return -EINVAL;
8142         }
8143
8144         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8145                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8146                 return -1;
8147         }
8148
8149         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8150                         port, idx);
8151
8152         pf->vxlan_ports[idx] = 0;
8153         pf->vxlan_bitmap &= ~(1 << idx);
8154
8155         if (!pf->vxlan_bitmap)
8156                 pf->flags &= ~I40E_FLAG_VXLAN;
8157
8158         return 0;
8159 }
8160
8161 /* Add UDP tunneling port */
8162 static int
8163 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8164                              struct rte_eth_udp_tunnel *udp_tunnel)
8165 {
8166         int ret = 0;
8167         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8168
8169         if (udp_tunnel == NULL)
8170                 return -EINVAL;
8171
8172         switch (udp_tunnel->prot_type) {
8173         case RTE_TUNNEL_TYPE_VXLAN:
8174                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8175                 break;
8176
8177         case RTE_TUNNEL_TYPE_GENEVE:
8178         case RTE_TUNNEL_TYPE_TEREDO:
8179                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8180                 ret = -1;
8181                 break;
8182
8183         default:
8184                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8185                 ret = -1;
8186                 break;
8187         }
8188
8189         return ret;
8190 }
8191
8192 /* Remove UDP tunneling port */
8193 static int
8194 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8195                              struct rte_eth_udp_tunnel *udp_tunnel)
8196 {
8197         int ret = 0;
8198         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8199
8200         if (udp_tunnel == NULL)
8201                 return -EINVAL;
8202
8203         switch (udp_tunnel->prot_type) {
8204         case RTE_TUNNEL_TYPE_VXLAN:
8205                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8206                 break;
8207         case RTE_TUNNEL_TYPE_GENEVE:
8208         case RTE_TUNNEL_TYPE_TEREDO:
8209                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8210                 ret = -1;
8211                 break;
8212         default:
8213                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8214                 ret = -1;
8215                 break;
8216         }
8217
8218         return ret;
8219 }
8220
8221 /* Calculate the maximum number of contiguous PF queues that are configured */
8222 static int
8223 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8224 {
8225         struct rte_eth_dev_data *data = pf->dev_data;
8226         int i, num;
8227         struct i40e_rx_queue *rxq;
8228
8229         num = 0;
8230         for (i = 0; i < pf->lan_nb_qps; i++) {
8231                 rxq = data->rx_queues[i];
8232                 if (rxq && rxq->q_set)
8233                         num++;
8234                 else
8235                         break;
8236         }
8237
8238         return num;
8239 }
8240
8241 /* Configure RSS */
8242 static int
8243 i40e_pf_config_rss(struct i40e_pf *pf)
8244 {
8245         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8246         struct rte_eth_rss_conf rss_conf;
8247         uint32_t i, lut = 0;
8248         uint16_t j, num;
8249
8250         /*
8251          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8252          * It's necessary to calculate the actual PF queues that are configured.
8253          */
8254         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8255                 num = i40e_pf_calc_configured_queues_num(pf);
8256         else
8257                 num = pf->dev_data->nb_rx_queues;
8258
8259         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8260         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8261                         num);
8262
8263         if (num == 0) {
8264                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8265                 return -ENOTSUP;
8266         }
8267
8268         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8269                 if (j == num)
8270                         j = 0;
8271                 lut = (lut << 8) | (j & ((0x1 <<
8272                         hw->func_caps.rss_table_entry_width) - 1));
8273                 if ((i & 3) == 3)
8274                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8275         }
8276
8277         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8278         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8279                 i40e_pf_disable_rss(pf);
8280                 return 0;
8281         }
8282         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8283                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8284                 /* Random default keys */
8285                 static uint32_t rss_key_default[] = {0x6b793944,
8286                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8287                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8288                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8289
8290                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8291                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8292                                                         sizeof(uint32_t);
8293         }
8294
8295         return i40e_hw_rss_hash_set(pf, &rss_conf);
8296 }
8297
8298 static int
8299 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8300                                struct rte_eth_tunnel_filter_conf *filter)
8301 {
8302         if (pf == NULL || filter == NULL) {
8303                 PMD_DRV_LOG(ERR, "Invalid parameter");
8304                 return -EINVAL;
8305         }
8306
8307         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8308                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8309                 return -EINVAL;
8310         }
8311
8312         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8313                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8314                 return -EINVAL;
8315         }
8316
8317         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8318                 (is_zero_ether_addr(&filter->outer_mac))) {
8319                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8320                 return -EINVAL;
8321         }
8322
8323         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8324                 (is_zero_ether_addr(&filter->inner_mac))) {
8325                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8326                 return -EINVAL;
8327         }
8328
8329         return 0;
8330 }
8331
8332 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8333 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8334 static int
8335 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8336 {
8337         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8338         uint32_t val, reg;
8339         int ret = -EINVAL;
8340
8341         if (pf->support_multi_driver) {
8342                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8343                 return -ENOTSUP;
8344         }
8345
8346         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8347         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8348
8349         if (len == 3) {
8350                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8351         } else if (len == 4) {
8352                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8353         } else {
8354                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8355                 return ret;
8356         }
8357
8358         if (reg != val) {
8359                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
8360                                                    reg, NULL);
8361                 if (ret != 0)
8362                         return ret;
8363                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8364                             "with value 0x%08x",
8365                             I40E_GL_PRS_FVBM(2), reg);
8366                 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8367         } else {
8368                 ret = 0;
8369         }
8370         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8371                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8372
8373         return ret;
8374 }
8375
8376 static int
8377 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8378 {
8379         int ret = -EINVAL;
8380
8381         if (!hw || !cfg)
8382                 return -EINVAL;
8383
8384         switch (cfg->cfg_type) {
8385         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8386                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8387                 break;
8388         default:
8389                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8390                 break;
8391         }
8392
8393         return ret;
8394 }
8395
8396 static int
8397 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8398                                enum rte_filter_op filter_op,
8399                                void *arg)
8400 {
8401         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8402         int ret = I40E_ERR_PARAM;
8403
8404         switch (filter_op) {
8405         case RTE_ETH_FILTER_SET:
8406                 ret = i40e_dev_global_config_set(hw,
8407                         (struct rte_eth_global_cfg *)arg);
8408                 break;
8409         default:
8410                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8411                 break;
8412         }
8413
8414         return ret;
8415 }
8416
8417 static int
8418 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8419                           enum rte_filter_op filter_op,
8420                           void *arg)
8421 {
8422         struct rte_eth_tunnel_filter_conf *filter;
8423         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8424         int ret = I40E_SUCCESS;
8425
8426         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8427
8428         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8429                 return I40E_ERR_PARAM;
8430
8431         switch (filter_op) {
8432         case RTE_ETH_FILTER_NOP:
8433                 if (!(pf->flags & I40E_FLAG_VXLAN))
8434                         ret = I40E_NOT_SUPPORTED;
8435                 break;
8436         case RTE_ETH_FILTER_ADD:
8437                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8438                 break;
8439         case RTE_ETH_FILTER_DELETE:
8440                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8441                 break;
8442         default:
8443                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8444                 ret = I40E_ERR_PARAM;
8445                 break;
8446         }
8447
8448         return ret;
8449 }
8450
8451 static int
8452 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8453 {
8454         int ret = 0;
8455         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8456
8457         /* RSS setup */
8458         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8459                 ret = i40e_pf_config_rss(pf);
8460         else
8461                 i40e_pf_disable_rss(pf);
8462
8463         return ret;
8464 }
8465
8466 /* Get the symmetric hash enable configurations per port */
8467 static void
8468 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8469 {
8470         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8471
8472         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8473 }
8474
8475 /* Set the symmetric hash enable configurations per port */
8476 static void
8477 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8478 {
8479         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8480
8481         if (enable > 0) {
8482                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8483                         PMD_DRV_LOG(INFO,
8484                                 "Symmetric hash has already been enabled");
8485                         return;
8486                 }
8487                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8488         } else {
8489                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8490                         PMD_DRV_LOG(INFO,
8491                                 "Symmetric hash has already been disabled");
8492                         return;
8493                 }
8494                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8495         }
8496         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8497         I40E_WRITE_FLUSH(hw);
8498 }
8499
8500 /*
8501  * Get global configurations of hash function type and symmetric hash enable
8502  * per flow type (pctype). Note that global configuration means it affects all
8503  * the ports on the same NIC.
8504  */
8505 static int
8506 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8507                                    struct rte_eth_hash_global_conf *g_cfg)
8508 {
8509         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8510         uint32_t reg;
8511         uint16_t i, j;
8512
8513         memset(g_cfg, 0, sizeof(*g_cfg));
8514         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8515         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8516                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8517         else
8518                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8519         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8520                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8521
8522         /*
8523          * As i40e supports less than 64 flow types, only first 64 bits need to
8524          * be checked.
8525          */
8526         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8527                 g_cfg->valid_bit_mask[i] = 0ULL;
8528                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8529         }
8530
8531         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8532
8533         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8534                 if (!adapter->pctypes_tbl[i])
8535                         continue;
8536                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8537                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8538                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8539                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8540                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8541                                         g_cfg->sym_hash_enable_mask[0] |=
8542                                                                 (1ULL << i);
8543                                 }
8544                         }
8545                 }
8546         }
8547
8548         return 0;
8549 }
8550
8551 static int
8552 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8553                               const struct rte_eth_hash_global_conf *g_cfg)
8554 {
8555         uint32_t i;
8556         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8557
8558         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8559                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8560                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8561                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8562                                                 g_cfg->hash_func);
8563                 return -EINVAL;
8564         }
8565
8566         /*
8567          * As i40e supports less than 64 flow types, only first 64 bits need to
8568          * be checked.
8569          */
8570         mask0 = g_cfg->valid_bit_mask[0];
8571         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8572                 if (i == 0) {
8573                         /* Check if any unsupported flow type configured */
8574                         if ((mask0 | i40e_mask) ^ i40e_mask)
8575                                 goto mask_err;
8576                 } else {
8577                         if (g_cfg->valid_bit_mask[i])
8578                                 goto mask_err;
8579                 }
8580         }
8581
8582         return 0;
8583
8584 mask_err:
8585         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8586
8587         return -EINVAL;
8588 }
8589
8590 /*
8591  * Set global configurations of hash function type and symmetric hash enable
8592  * per flow type (pctype). Note any modifying global configuration will affect
8593  * all the ports on the same NIC.
8594  */
8595 static int
8596 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8597                                    struct rte_eth_hash_global_conf *g_cfg)
8598 {
8599         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8600         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8601         int ret;
8602         uint16_t i, j;
8603         uint32_t reg;
8604         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8605
8606         if (pf->support_multi_driver) {
8607                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8608                 return -ENOTSUP;
8609         }
8610
8611         /* Check the input parameters */
8612         ret = i40e_hash_global_config_check(adapter, g_cfg);
8613         if (ret < 0)
8614                 return ret;
8615
8616         /*
8617          * As i40e supports less than 64 flow types, only first 64 bits need to
8618          * be configured.
8619          */
8620         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8621                 if (mask0 & (1UL << i)) {
8622                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8623                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8624
8625                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8626                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8627                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8628                                         i40e_write_global_rx_ctl(hw,
8629                                                           I40E_GLQF_HSYM(j),
8630                                                           reg);
8631                         }
8632                         i40e_global_cfg_warning(I40E_WARNING_HSYM);
8633                 }
8634         }
8635
8636         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8637         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8638                 /* Toeplitz */
8639                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8640                         PMD_DRV_LOG(DEBUG,
8641                                 "Hash function already set to Toeplitz");
8642                         goto out;
8643                 }
8644                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8645         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8646                 /* Simple XOR */
8647                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8648                         PMD_DRV_LOG(DEBUG,
8649                                 "Hash function already set to Simple XOR");
8650                         goto out;
8651                 }
8652                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8653         } else
8654                 /* Use the default, and keep it as it is */
8655                 goto out;
8656
8657         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8658         i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8659
8660 out:
8661         I40E_WRITE_FLUSH(hw);
8662
8663         return 0;
8664 }
8665
8666 /**
8667  * Valid input sets for hash and flow director filters per PCTYPE
8668  */
8669 static uint64_t
8670 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8671                 enum rte_filter_type filter)
8672 {
8673         uint64_t valid;
8674
8675         static const uint64_t valid_hash_inset_table[] = {
8676                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8677                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8678                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8679                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8680                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8681                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8682                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8683                         I40E_INSET_FLEX_PAYLOAD,
8684                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8685                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8686                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8687                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8688                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8689                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8690                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8691                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8692                         I40E_INSET_FLEX_PAYLOAD,
8693                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8694                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8695                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8696                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8697                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8698                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8699                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8700                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8701                         I40E_INSET_FLEX_PAYLOAD,
8702                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8703                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8704                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8705                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8706                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8707                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8708                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8709                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8710                         I40E_INSET_FLEX_PAYLOAD,
8711                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8712                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8713                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8714                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8715                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8716                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8717                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8718                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8719                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8720                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8721                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8722                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8723                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8724                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8725                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8726                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8727                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8728                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8729                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8730                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8731                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8732                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8733                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8734                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8735                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8736                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8737                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8738                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8739                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8740                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8741                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8742                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8743                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8744                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8745                         I40E_INSET_FLEX_PAYLOAD,
8746                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8747                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8748                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8749                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8750                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8751                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8752                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8753                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8754                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8755                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8756                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8757                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8758                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8759                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8760                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8761                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8762                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8763                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8764                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8765                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8766                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8767                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8768                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8769                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8770                         I40E_INSET_FLEX_PAYLOAD,
8771                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8772                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8773                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8774                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8775                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8776                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8777                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8778                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8779                         I40E_INSET_FLEX_PAYLOAD,
8780                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8781                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8782                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8783                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8784                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8785                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8786                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8787                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8788                         I40E_INSET_FLEX_PAYLOAD,
8789                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8790                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8791                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8792                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8793                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8794                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8795                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8796                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8797                         I40E_INSET_FLEX_PAYLOAD,
8798                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8799                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8800                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8801                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8802                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8803                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8804                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8805                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8806                         I40E_INSET_FLEX_PAYLOAD,
8807                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8808                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8809                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8810                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8811                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8812                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8813                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8814                         I40E_INSET_FLEX_PAYLOAD,
8815                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8816                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8817                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8818                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8819                         I40E_INSET_FLEX_PAYLOAD,
8820         };
8821
8822         /**
8823          * Flow director supports only fields defined in
8824          * union rte_eth_fdir_flow.
8825          */
8826         static const uint64_t valid_fdir_inset_table[] = {
8827                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8828                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8829                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8830                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8831                 I40E_INSET_IPV4_TTL,
8832                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8833                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8834                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8835                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8836                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8837                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8838                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8839                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8840                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8841                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8842                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8843                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8844                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8845                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8846                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8847                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8848                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8849                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8850                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8851                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8852                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8853                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8854                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8855                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8856                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8857                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8858                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8859                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8860                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8861                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8862                 I40E_INSET_SCTP_VT,
8863                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8864                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8865                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8866                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8867                 I40E_INSET_IPV4_TTL,
8868                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8869                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8870                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8871                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8872                 I40E_INSET_IPV6_HOP_LIMIT,
8873                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8874                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8875                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8876                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8877                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8878                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8879                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8880                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8881                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8882                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8883                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8884                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8885                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8886                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8887                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8888                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8889                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8890                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8891                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8892                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8893                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8894                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8895                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8896                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8897                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8898                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8899                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8900                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8901                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8902                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8903                 I40E_INSET_SCTP_VT,
8904                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8905                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8906                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8907                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8908                 I40E_INSET_IPV6_HOP_LIMIT,
8909                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8910                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8911                 I40E_INSET_LAST_ETHER_TYPE,
8912         };
8913
8914         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8915                 return 0;
8916         if (filter == RTE_ETH_FILTER_HASH)
8917                 valid = valid_hash_inset_table[pctype];
8918         else
8919                 valid = valid_fdir_inset_table[pctype];
8920
8921         return valid;
8922 }
8923
8924 /**
8925  * Validate if the input set is allowed for a specific PCTYPE
8926  */
8927 int
8928 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8929                 enum rte_filter_type filter, uint64_t inset)
8930 {
8931         uint64_t valid;
8932
8933         valid = i40e_get_valid_input_set(pctype, filter);
8934         if (inset & (~valid))
8935                 return -EINVAL;
8936
8937         return 0;
8938 }
8939
8940 /* default input set fields combination per pctype */
8941 uint64_t
8942 i40e_get_default_input_set(uint16_t pctype)
8943 {
8944         static const uint64_t default_inset_table[] = {
8945                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8946                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8947                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8948                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8949                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8950                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8951                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8952                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8953                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8954                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8955                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8956                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8957                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8958                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8959                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8960                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8961                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8962                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8963                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8964                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8965                         I40E_INSET_SCTP_VT,
8966                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8967                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8968                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8969                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8970                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8971                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8972                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8973                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8974                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8975                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8976                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8977                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8978                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8979                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8980                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8981                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8982                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8983                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8984                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8985                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8986                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8987                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8988                         I40E_INSET_SCTP_VT,
8989                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8990                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8991                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8992                         I40E_INSET_LAST_ETHER_TYPE,
8993         };
8994
8995         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8996                 return 0;
8997
8998         return default_inset_table[pctype];
8999 }
9000
9001 /**
9002  * Parse the input set from index to logical bit masks
9003  */
9004 static int
9005 i40e_parse_input_set(uint64_t *inset,
9006                      enum i40e_filter_pctype pctype,
9007                      enum rte_eth_input_set_field *field,
9008                      uint16_t size)
9009 {
9010         uint16_t i, j;
9011         int ret = -EINVAL;
9012
9013         static const struct {
9014                 enum rte_eth_input_set_field field;
9015                 uint64_t inset;
9016         } inset_convert_table[] = {
9017                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9018                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9019                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9020                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9021                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9022                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9023                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9024                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9025                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9026                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9027                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9028                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9029                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9030                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9031                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9032                         I40E_INSET_IPV6_NEXT_HDR},
9033                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9034                         I40E_INSET_IPV6_HOP_LIMIT},
9035                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9036                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9037                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9038                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9039                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9040                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9041                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9042                         I40E_INSET_SCTP_VT},
9043                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9044                         I40E_INSET_TUNNEL_DMAC},
9045                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9046                         I40E_INSET_VLAN_TUNNEL},
9047                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9048                         I40E_INSET_TUNNEL_ID},
9049                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9050                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9051                         I40E_INSET_FLEX_PAYLOAD_W1},
9052                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9053                         I40E_INSET_FLEX_PAYLOAD_W2},
9054                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9055                         I40E_INSET_FLEX_PAYLOAD_W3},
9056                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9057                         I40E_INSET_FLEX_PAYLOAD_W4},
9058                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9059                         I40E_INSET_FLEX_PAYLOAD_W5},
9060                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9061                         I40E_INSET_FLEX_PAYLOAD_W6},
9062                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9063                         I40E_INSET_FLEX_PAYLOAD_W7},
9064                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9065                         I40E_INSET_FLEX_PAYLOAD_W8},
9066         };
9067
9068         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9069                 return ret;
9070
9071         /* Only one item allowed for default or all */
9072         if (size == 1) {
9073                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9074                         *inset = i40e_get_default_input_set(pctype);
9075                         return 0;
9076                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9077                         *inset = I40E_INSET_NONE;
9078                         return 0;
9079                 }
9080         }
9081
9082         for (i = 0, *inset = 0; i < size; i++) {
9083                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9084                         if (field[i] == inset_convert_table[j].field) {
9085                                 *inset |= inset_convert_table[j].inset;
9086                                 break;
9087                         }
9088                 }
9089
9090                 /* It contains unsupported input set, return immediately */
9091                 if (j == RTE_DIM(inset_convert_table))
9092                         return ret;
9093         }
9094
9095         return 0;
9096 }
9097
9098 /**
9099  * Translate the input set from bit masks to register aware bit masks
9100  * and vice versa
9101  */
9102 uint64_t
9103 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9104 {
9105         uint64_t val = 0;
9106         uint16_t i;
9107
9108         struct inset_map {
9109                 uint64_t inset;
9110                 uint64_t inset_reg;
9111         };
9112
9113         static const struct inset_map inset_map_common[] = {
9114                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9115                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9116                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9117                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9118                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9119                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9120                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9121                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9122                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9123                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9124                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9125                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9126                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9127                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9128                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9129                 {I40E_INSET_TUNNEL_DMAC,
9130                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9131                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9132                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9133                 {I40E_INSET_TUNNEL_SRC_PORT,
9134                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9135                 {I40E_INSET_TUNNEL_DST_PORT,
9136                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9137                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9138                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9139                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9140                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9141                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9142                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9143                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9144                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9145                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9146         };
9147
9148     /* some different registers map in x722*/
9149         static const struct inset_map inset_map_diff_x722[] = {
9150                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9151                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9152                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9153                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9154         };
9155
9156         static const struct inset_map inset_map_diff_not_x722[] = {
9157                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9158                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9159                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9160                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9161         };
9162
9163         if (input == 0)
9164                 return val;
9165
9166         /* Translate input set to register aware inset */
9167         if (type == I40E_MAC_X722) {
9168                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9169                         if (input & inset_map_diff_x722[i].inset)
9170                                 val |= inset_map_diff_x722[i].inset_reg;
9171                 }
9172         } else {
9173                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9174                         if (input & inset_map_diff_not_x722[i].inset)
9175                                 val |= inset_map_diff_not_x722[i].inset_reg;
9176                 }
9177         }
9178
9179         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9180                 if (input & inset_map_common[i].inset)
9181                         val |= inset_map_common[i].inset_reg;
9182         }
9183
9184         return val;
9185 }
9186
9187 int
9188 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9189 {
9190         uint8_t i, idx = 0;
9191         uint64_t inset_need_mask = inset;
9192
9193         static const struct {
9194                 uint64_t inset;
9195                 uint32_t mask;
9196         } inset_mask_map[] = {
9197                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9198                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9199                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9200                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9201                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9202                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9203                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9204                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9205         };
9206
9207         if (!inset || !mask || !nb_elem)
9208                 return 0;
9209
9210         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9211                 /* Clear the inset bit, if no MASK is required,
9212                  * for example proto + ttl
9213                  */
9214                 if ((inset & inset_mask_map[i].inset) ==
9215                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9216                         inset_need_mask &= ~inset_mask_map[i].inset;
9217                 if (!inset_need_mask)
9218                         return 0;
9219         }
9220         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9221                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9222                     inset_mask_map[i].inset) {
9223                         if (idx >= nb_elem) {
9224                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9225                                 return -EINVAL;
9226                         }
9227                         mask[idx] = inset_mask_map[i].mask;
9228                         idx++;
9229                 }
9230         }
9231
9232         return idx;
9233 }
9234
9235 void
9236 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9237 {
9238         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9239
9240         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9241         if (reg != val)
9242                 i40e_write_rx_ctl(hw, addr, val);
9243         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9244                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9245 }
9246
9247 void
9248 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9249 {
9250         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9251
9252         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9253         if (reg != val)
9254                 i40e_write_global_rx_ctl(hw, addr, val);
9255         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9256                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9257 }
9258
9259 static void
9260 i40e_filter_input_set_init(struct i40e_pf *pf)
9261 {
9262         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9263         enum i40e_filter_pctype pctype;
9264         uint64_t input_set, inset_reg;
9265         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9266         int num, i;
9267         uint16_t flow_type;
9268
9269         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9270              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9271                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9272
9273                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9274                         continue;
9275
9276                 input_set = i40e_get_default_input_set(pctype);
9277
9278                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9279                                                    I40E_INSET_MASK_NUM_REG);
9280                 if (num < 0)
9281                         return;
9282                 if (pf->support_multi_driver && num > 0) {
9283                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9284                         return;
9285                 }
9286                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9287                                         input_set);
9288
9289                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9290                                       (uint32_t)(inset_reg & UINT32_MAX));
9291                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9292                                      (uint32_t)((inset_reg >>
9293                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9294                 if (!pf->support_multi_driver) {
9295                         i40e_check_write_global_reg(hw,
9296                                             I40E_GLQF_HASH_INSET(0, pctype),
9297                                             (uint32_t)(inset_reg & UINT32_MAX));
9298                         i40e_check_write_global_reg(hw,
9299                                              I40E_GLQF_HASH_INSET(1, pctype),
9300                                              (uint32_t)((inset_reg >>
9301                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9302
9303                         for (i = 0; i < num; i++) {
9304                                 i40e_check_write_global_reg(hw,
9305                                                     I40E_GLQF_FD_MSK(i, pctype),
9306                                                     mask_reg[i]);
9307                                 i40e_check_write_global_reg(hw,
9308                                                   I40E_GLQF_HASH_MSK(i, pctype),
9309                                                   mask_reg[i]);
9310                         }
9311                         /*clear unused mask registers of the pctype */
9312                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9313                                 i40e_check_write_global_reg(hw,
9314                                                     I40E_GLQF_FD_MSK(i, pctype),
9315                                                     0);
9316                                 i40e_check_write_global_reg(hw,
9317                                                   I40E_GLQF_HASH_MSK(i, pctype),
9318                                                   0);
9319                         }
9320                 } else {
9321                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9322                 }
9323                 I40E_WRITE_FLUSH(hw);
9324
9325                 /* store the default input set */
9326                 if (!pf->support_multi_driver)
9327                         pf->hash_input_set[pctype] = input_set;
9328                 pf->fdir.input_set[pctype] = input_set;
9329         }
9330
9331         if (!pf->support_multi_driver) {
9332                 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9333                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9334                 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9335         }
9336 }
9337
9338 int
9339 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9340                          struct rte_eth_input_set_conf *conf)
9341 {
9342         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9343         enum i40e_filter_pctype pctype;
9344         uint64_t input_set, inset_reg = 0;
9345         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9346         int ret, i, num;
9347
9348         if (!conf) {
9349                 PMD_DRV_LOG(ERR, "Invalid pointer");
9350                 return -EFAULT;
9351         }
9352         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9353             conf->op != RTE_ETH_INPUT_SET_ADD) {
9354                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9355                 return -EINVAL;
9356         }
9357
9358         if (pf->support_multi_driver) {
9359                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9360                 return -ENOTSUP;
9361         }
9362
9363         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9364         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9365                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9366                 return -EINVAL;
9367         }
9368
9369         if (hw->mac.type == I40E_MAC_X722) {
9370                 /* get translated pctype value in fd pctype register */
9371                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9372                         I40E_GLQF_FD_PCTYPES((int)pctype));
9373         }
9374
9375         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9376                                    conf->inset_size);
9377         if (ret) {
9378                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9379                 return -EINVAL;
9380         }
9381
9382         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9383                 /* get inset value in register */
9384                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9385                 inset_reg <<= I40E_32_BIT_WIDTH;
9386                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9387                 input_set |= pf->hash_input_set[pctype];
9388         }
9389         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9390                                            I40E_INSET_MASK_NUM_REG);
9391         if (num < 0)
9392                 return -EINVAL;
9393
9394         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9395
9396         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9397                                     (uint32_t)(inset_reg & UINT32_MAX));
9398         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9399                                     (uint32_t)((inset_reg >>
9400                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9401         i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9402
9403         for (i = 0; i < num; i++)
9404                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9405                                             mask_reg[i]);
9406         /*clear unused mask registers of the pctype */
9407         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9408                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9409                                             0);
9410         i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9411         I40E_WRITE_FLUSH(hw);
9412
9413         pf->hash_input_set[pctype] = input_set;
9414         return 0;
9415 }
9416
9417 int
9418 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9419                          struct rte_eth_input_set_conf *conf)
9420 {
9421         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9422         enum i40e_filter_pctype pctype;
9423         uint64_t input_set, inset_reg = 0;
9424         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9425         int ret, i, num;
9426
9427         if (!hw || !conf) {
9428                 PMD_DRV_LOG(ERR, "Invalid pointer");
9429                 return -EFAULT;
9430         }
9431         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9432             conf->op != RTE_ETH_INPUT_SET_ADD) {
9433                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9434                 return -EINVAL;
9435         }
9436
9437         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9438
9439         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9440                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9441                 return -EINVAL;
9442         }
9443
9444         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9445                                    conf->inset_size);
9446         if (ret) {
9447                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9448                 return -EINVAL;
9449         }
9450
9451         /* get inset value in register */
9452         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9453         inset_reg <<= I40E_32_BIT_WIDTH;
9454         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9455
9456         /* Can not change the inset reg for flex payload for fdir,
9457          * it is done by writing I40E_PRTQF_FD_FLXINSET
9458          * in i40e_set_flex_mask_on_pctype.
9459          */
9460         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9461                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9462         else
9463                 input_set |= pf->fdir.input_set[pctype];
9464         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9465                                            I40E_INSET_MASK_NUM_REG);
9466         if (num < 0)
9467                 return -EINVAL;
9468         if (pf->support_multi_driver && num > 0) {
9469                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9470                 return -ENOTSUP;
9471         }
9472
9473         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9474
9475         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9476                               (uint32_t)(inset_reg & UINT32_MAX));
9477         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9478                              (uint32_t)((inset_reg >>
9479                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9480
9481         if (!pf->support_multi_driver) {
9482                 for (i = 0; i < num; i++)
9483                         i40e_check_write_global_reg(hw,
9484                                                     I40E_GLQF_FD_MSK(i, pctype),
9485                                                     mask_reg[i]);
9486                 /*clear unused mask registers of the pctype */
9487                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9488                         i40e_check_write_global_reg(hw,
9489                                                     I40E_GLQF_FD_MSK(i, pctype),
9490                                                     0);
9491                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9492         } else {
9493                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9494         }
9495         I40E_WRITE_FLUSH(hw);
9496
9497         pf->fdir.input_set[pctype] = input_set;
9498         return 0;
9499 }
9500
9501 static int
9502 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9503 {
9504         int ret = 0;
9505
9506         if (!hw || !info) {
9507                 PMD_DRV_LOG(ERR, "Invalid pointer");
9508                 return -EFAULT;
9509         }
9510
9511         switch (info->info_type) {
9512         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9513                 i40e_get_symmetric_hash_enable_per_port(hw,
9514                                         &(info->info.enable));
9515                 break;
9516         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9517                 ret = i40e_get_hash_filter_global_config(hw,
9518                                 &(info->info.global_conf));
9519                 break;
9520         default:
9521                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9522                                                         info->info_type);
9523                 ret = -EINVAL;
9524                 break;
9525         }
9526
9527         return ret;
9528 }
9529
9530 static int
9531 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9532 {
9533         int ret = 0;
9534
9535         if (!hw || !info) {
9536                 PMD_DRV_LOG(ERR, "Invalid pointer");
9537                 return -EFAULT;
9538         }
9539
9540         switch (info->info_type) {
9541         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9542                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9543                 break;
9544         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9545                 ret = i40e_set_hash_filter_global_config(hw,
9546                                 &(info->info.global_conf));
9547                 break;
9548         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9549                 ret = i40e_hash_filter_inset_select(hw,
9550                                                &(info->info.input_set_conf));
9551                 break;
9552
9553         default:
9554                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9555                                                         info->info_type);
9556                 ret = -EINVAL;
9557                 break;
9558         }
9559
9560         return ret;
9561 }
9562
9563 /* Operations for hash function */
9564 static int
9565 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9566                       enum rte_filter_op filter_op,
9567                       void *arg)
9568 {
9569         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9570         int ret = 0;
9571
9572         switch (filter_op) {
9573         case RTE_ETH_FILTER_NOP:
9574                 break;
9575         case RTE_ETH_FILTER_GET:
9576                 ret = i40e_hash_filter_get(hw,
9577                         (struct rte_eth_hash_filter_info *)arg);
9578                 break;
9579         case RTE_ETH_FILTER_SET:
9580                 ret = i40e_hash_filter_set(hw,
9581                         (struct rte_eth_hash_filter_info *)arg);
9582                 break;
9583         default:
9584                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9585                                                                 filter_op);
9586                 ret = -ENOTSUP;
9587                 break;
9588         }
9589
9590         return ret;
9591 }
9592
9593 /* Convert ethertype filter structure */
9594 static int
9595 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9596                               struct i40e_ethertype_filter *filter)
9597 {
9598         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9599         filter->input.ether_type = input->ether_type;
9600         filter->flags = input->flags;
9601         filter->queue = input->queue;
9602
9603         return 0;
9604 }
9605
9606 /* Check if there exists the ehtertype filter */
9607 struct i40e_ethertype_filter *
9608 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9609                                 const struct i40e_ethertype_filter_input *input)
9610 {
9611         int ret;
9612
9613         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9614         if (ret < 0)
9615                 return NULL;
9616
9617         return ethertype_rule->hash_map[ret];
9618 }
9619
9620 /* Add ethertype filter in SW list */
9621 static int
9622 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9623                                 struct i40e_ethertype_filter *filter)
9624 {
9625         struct i40e_ethertype_rule *rule = &pf->ethertype;
9626         int ret;
9627
9628         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9629         if (ret < 0) {
9630                 PMD_DRV_LOG(ERR,
9631                             "Failed to insert ethertype filter"
9632                             " to hash table %d!",
9633                             ret);
9634                 return ret;
9635         }
9636         rule->hash_map[ret] = filter;
9637
9638         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9639
9640         return 0;
9641 }
9642
9643 /* Delete ethertype filter in SW list */
9644 int
9645 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9646                              struct i40e_ethertype_filter_input *input)
9647 {
9648         struct i40e_ethertype_rule *rule = &pf->ethertype;
9649         struct i40e_ethertype_filter *filter;
9650         int ret;
9651
9652         ret = rte_hash_del_key(rule->hash_table, input);
9653         if (ret < 0) {
9654                 PMD_DRV_LOG(ERR,
9655                             "Failed to delete ethertype filter"
9656                             " to hash table %d!",
9657                             ret);
9658                 return ret;
9659         }
9660         filter = rule->hash_map[ret];
9661         rule->hash_map[ret] = NULL;
9662
9663         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9664         rte_free(filter);
9665
9666         return 0;
9667 }
9668
9669 /*
9670  * Configure ethertype filter, which can director packet by filtering
9671  * with mac address and ether_type or only ether_type
9672  */
9673 int
9674 i40e_ethertype_filter_set(struct i40e_pf *pf,
9675                         struct rte_eth_ethertype_filter *filter,
9676                         bool add)
9677 {
9678         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9679         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9680         struct i40e_ethertype_filter *ethertype_filter, *node;
9681         struct i40e_ethertype_filter check_filter;
9682         struct i40e_control_filter_stats stats;
9683         uint16_t flags = 0;
9684         int ret;
9685
9686         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9687                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9688                 return -EINVAL;
9689         }
9690         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9691                 filter->ether_type == ETHER_TYPE_IPv6) {
9692                 PMD_DRV_LOG(ERR,
9693                         "unsupported ether_type(0x%04x) in control packet filter.",
9694                         filter->ether_type);
9695                 return -EINVAL;
9696         }
9697         if (filter->ether_type == ETHER_TYPE_VLAN)
9698                 PMD_DRV_LOG(WARNING,
9699                         "filter vlan ether_type in first tag is not supported.");
9700
9701         /* Check if there is the filter in SW list */
9702         memset(&check_filter, 0, sizeof(check_filter));
9703         i40e_ethertype_filter_convert(filter, &check_filter);
9704         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9705                                                &check_filter.input);
9706         if (add && node) {
9707                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9708                 return -EINVAL;
9709         }
9710
9711         if (!add && !node) {
9712                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9713                 return -EINVAL;
9714         }
9715
9716         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9717                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9718         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9719                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9720         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9721
9722         memset(&stats, 0, sizeof(stats));
9723         ret = i40e_aq_add_rem_control_packet_filter(hw,
9724                         filter->mac_addr.addr_bytes,
9725                         filter->ether_type, flags,
9726                         pf->main_vsi->seid,
9727                         filter->queue, add, &stats, NULL);
9728
9729         PMD_DRV_LOG(INFO,
9730                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9731                 ret, stats.mac_etype_used, stats.etype_used,
9732                 stats.mac_etype_free, stats.etype_free);
9733         if (ret < 0)
9734                 return -ENOSYS;
9735
9736         /* Add or delete a filter in SW list */
9737         if (add) {
9738                 ethertype_filter = rte_zmalloc("ethertype_filter",
9739                                        sizeof(*ethertype_filter), 0);
9740                 if (ethertype_filter == NULL) {
9741                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9742                         return -ENOMEM;
9743                 }
9744
9745                 rte_memcpy(ethertype_filter, &check_filter,
9746                            sizeof(check_filter));
9747                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9748                 if (ret < 0)
9749                         rte_free(ethertype_filter);
9750         } else {
9751                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9752         }
9753
9754         return ret;
9755 }
9756
9757 /*
9758  * Handle operations for ethertype filter.
9759  */
9760 static int
9761 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9762                                 enum rte_filter_op filter_op,
9763                                 void *arg)
9764 {
9765         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9766         int ret = 0;
9767
9768         if (filter_op == RTE_ETH_FILTER_NOP)
9769                 return ret;
9770
9771         if (arg == NULL) {
9772                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9773                             filter_op);
9774                 return -EINVAL;
9775         }
9776
9777         switch (filter_op) {
9778         case RTE_ETH_FILTER_ADD:
9779                 ret = i40e_ethertype_filter_set(pf,
9780                         (struct rte_eth_ethertype_filter *)arg,
9781                         TRUE);
9782                 break;
9783         case RTE_ETH_FILTER_DELETE:
9784                 ret = i40e_ethertype_filter_set(pf,
9785                         (struct rte_eth_ethertype_filter *)arg,
9786                         FALSE);
9787                 break;
9788         default:
9789                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9790                 ret = -ENOSYS;
9791                 break;
9792         }
9793         return ret;
9794 }
9795
9796 static int
9797 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9798                      enum rte_filter_type filter_type,
9799                      enum rte_filter_op filter_op,
9800                      void *arg)
9801 {
9802         int ret = 0;
9803
9804         if (dev == NULL)
9805                 return -EINVAL;
9806
9807         switch (filter_type) {
9808         case RTE_ETH_FILTER_NONE:
9809                 /* For global configuration */
9810                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9811                 break;
9812         case RTE_ETH_FILTER_HASH:
9813                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9814                 break;
9815         case RTE_ETH_FILTER_MACVLAN:
9816                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9817                 break;
9818         case RTE_ETH_FILTER_ETHERTYPE:
9819                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9820                 break;
9821         case RTE_ETH_FILTER_TUNNEL:
9822                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9823                 break;
9824         case RTE_ETH_FILTER_FDIR:
9825                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9826                 break;
9827         case RTE_ETH_FILTER_GENERIC:
9828                 if (filter_op != RTE_ETH_FILTER_GET)
9829                         return -EINVAL;
9830                 *(const void **)arg = &i40e_flow_ops;
9831                 break;
9832         default:
9833                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9834                                                         filter_type);
9835                 ret = -EINVAL;
9836                 break;
9837         }
9838
9839         return ret;
9840 }
9841
9842 /*
9843  * Check and enable Extended Tag.
9844  * Enabling Extended Tag is important for 40G performance.
9845  */
9846 static void
9847 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9848 {
9849         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9850         uint32_t buf = 0;
9851         int ret;
9852
9853         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9854                                       PCI_DEV_CAP_REG);
9855         if (ret < 0) {
9856                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9857                             PCI_DEV_CAP_REG);
9858                 return;
9859         }
9860         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9861                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9862                 return;
9863         }
9864
9865         buf = 0;
9866         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9867                                       PCI_DEV_CTRL_REG);
9868         if (ret < 0) {
9869                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9870                             PCI_DEV_CTRL_REG);
9871                 return;
9872         }
9873         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9874                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9875                 return;
9876         }
9877         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9878         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9879                                        PCI_DEV_CTRL_REG);
9880         if (ret < 0) {
9881                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9882                             PCI_DEV_CTRL_REG);
9883                 return;
9884         }
9885 }
9886
9887 /*
9888  * As some registers wouldn't be reset unless a global hardware reset,
9889  * hardware initialization is needed to put those registers into an
9890  * expected initial state.
9891  */
9892 static void
9893 i40e_hw_init(struct rte_eth_dev *dev)
9894 {
9895         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9896
9897         i40e_enable_extended_tag(dev);
9898
9899         /* clear the PF Queue Filter control register */
9900         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9901
9902         /* Disable symmetric hash per port */
9903         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9904 }
9905
9906 /*
9907  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9908  * however this function will return only one highest pctype index,
9909  * which is not quite correct. This is known problem of i40e driver
9910  * and needs to be fixed later.
9911  */
9912 enum i40e_filter_pctype
9913 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9914 {
9915         int i;
9916         uint64_t pctype_mask;
9917
9918         if (flow_type < I40E_FLOW_TYPE_MAX) {
9919                 pctype_mask = adapter->pctypes_tbl[flow_type];
9920                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9921                         if (pctype_mask & (1ULL << i))
9922                                 return (enum i40e_filter_pctype)i;
9923                 }
9924         }
9925         return I40E_FILTER_PCTYPE_INVALID;
9926 }
9927
9928 uint16_t
9929 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9930                         enum i40e_filter_pctype pctype)
9931 {
9932         uint16_t flowtype;
9933         uint64_t pctype_mask = 1ULL << pctype;
9934
9935         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9936              flowtype++) {
9937                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9938                         return flowtype;
9939         }
9940
9941         return RTE_ETH_FLOW_UNKNOWN;
9942 }
9943
9944 /*
9945  * On X710, performance number is far from the expectation on recent firmware
9946  * versions; on XL710, performance number is also far from the expectation on
9947  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9948  * mode is enabled and port MAC address is equal to the packet destination MAC
9949  * address. The fix for this issue may not be integrated in the following
9950  * firmware version. So the workaround in software driver is needed. It needs
9951  * to modify the initial values of 3 internal only registers for both X710 and
9952  * XL710. Note that the values for X710 or XL710 could be different, and the
9953  * workaround can be removed when it is fixed in firmware in the future.
9954  */
9955
9956 /* For both X710 and XL710 */
9957 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9958 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9959 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9960
9961 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9962 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9963
9964 /* For X722 */
9965 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9966 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9967
9968 /* For X710 */
9969 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9970 /* For XL710 */
9971 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9972 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9973
9974 static int
9975 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9976 {
9977         enum i40e_status_code status;
9978         struct i40e_aq_get_phy_abilities_resp phy_ab;
9979         int ret = -ENOTSUP;
9980         int retries = 0;
9981
9982         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9983                                               NULL);
9984
9985         while (status) {
9986                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9987                         status);
9988                 retries++;
9989                 rte_delay_us(100000);
9990                 if  (retries < 5)
9991                         status = i40e_aq_get_phy_capabilities(hw, false,
9992                                         true, &phy_ab, NULL);
9993                 else
9994                         return ret;
9995         }
9996         return 0;
9997 }
9998
9999 static void
10000 i40e_configure_registers(struct i40e_hw *hw)
10001 {
10002         static struct {
10003                 uint32_t addr;
10004                 uint64_t val;
10005         } reg_table[] = {
10006                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10007                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10008                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10009         };
10010         uint64_t reg;
10011         uint32_t i;
10012         int ret;
10013
10014         for (i = 0; i < RTE_DIM(reg_table); i++) {
10015                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10016                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10017                                 reg_table[i].val =
10018                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10019                         else /* For X710/XL710/XXV710 */
10020                                 if (hw->aq.fw_maj_ver < 6)
10021                                         reg_table[i].val =
10022                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10023                                 else
10024                                         reg_table[i].val =
10025                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10026                 }
10027
10028                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10029                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10030                                 reg_table[i].val =
10031                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10032                         else /* For X710/XL710/XXV710 */
10033                                 reg_table[i].val =
10034                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10035                 }
10036
10037                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10038                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
10039                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
10040                                 reg_table[i].val =
10041                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
10042                         else /* For X710 */
10043                                 reg_table[i].val =
10044                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
10045                 }
10046
10047                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10048                                                         &reg, NULL);
10049                 if (ret < 0) {
10050                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10051                                                         reg_table[i].addr);
10052                         break;
10053                 }
10054                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10055                                                 reg_table[i].addr, reg);
10056                 if (reg == reg_table[i].val)
10057                         continue;
10058
10059                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10060                                                 reg_table[i].val, NULL);
10061                 if (ret < 0) {
10062                         PMD_DRV_LOG(ERR,
10063                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10064                                 reg_table[i].val, reg_table[i].addr);
10065                         break;
10066                 }
10067                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10068                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10069         }
10070 }
10071
10072 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10073 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10074 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10075 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10076 static int
10077 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10078 {
10079         uint32_t reg;
10080         int ret;
10081
10082         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10083                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10084                 return -EINVAL;
10085         }
10086
10087         /* Configure for double VLAN RX stripping */
10088         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10089         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10090                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10091                 ret = i40e_aq_debug_write_register(hw,
10092                                                    I40E_VSI_TSR(vsi->vsi_id),
10093                                                    reg, NULL);
10094                 if (ret < 0) {
10095                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10096                                     vsi->vsi_id);
10097                         return I40E_ERR_CONFIG;
10098                 }
10099         }
10100
10101         /* Configure for double VLAN TX insertion */
10102         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10103         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10104                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10105                 ret = i40e_aq_debug_write_register(hw,
10106                                                    I40E_VSI_L2TAGSTXVALID(
10107                                                    vsi->vsi_id), reg, NULL);
10108                 if (ret < 0) {
10109                         PMD_DRV_LOG(ERR,
10110                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10111                                 vsi->vsi_id);
10112                         return I40E_ERR_CONFIG;
10113                 }
10114         }
10115
10116         return 0;
10117 }
10118
10119 /**
10120  * i40e_aq_add_mirror_rule
10121  * @hw: pointer to the hardware structure
10122  * @seid: VEB seid to add mirror rule to
10123  * @dst_id: destination vsi seid
10124  * @entries: Buffer which contains the entities to be mirrored
10125  * @count: number of entities contained in the buffer
10126  * @rule_id:the rule_id of the rule to be added
10127  *
10128  * Add a mirror rule for a given veb.
10129  *
10130  **/
10131 static enum i40e_status_code
10132 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10133                         uint16_t seid, uint16_t dst_id,
10134                         uint16_t rule_type, uint16_t *entries,
10135                         uint16_t count, uint16_t *rule_id)
10136 {
10137         struct i40e_aq_desc desc;
10138         struct i40e_aqc_add_delete_mirror_rule cmd;
10139         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10140                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10141                 &desc.params.raw;
10142         uint16_t buff_len;
10143         enum i40e_status_code status;
10144
10145         i40e_fill_default_direct_cmd_desc(&desc,
10146                                           i40e_aqc_opc_add_mirror_rule);
10147         memset(&cmd, 0, sizeof(cmd));
10148
10149         buff_len = sizeof(uint16_t) * count;
10150         desc.datalen = rte_cpu_to_le_16(buff_len);
10151         if (buff_len > 0)
10152                 desc.flags |= rte_cpu_to_le_16(
10153                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10154         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10155                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10156         cmd.num_entries = rte_cpu_to_le_16(count);
10157         cmd.seid = rte_cpu_to_le_16(seid);
10158         cmd.destination = rte_cpu_to_le_16(dst_id);
10159
10160         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10161         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10162         PMD_DRV_LOG(INFO,
10163                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10164                 hw->aq.asq_last_status, resp->rule_id,
10165                 resp->mirror_rules_used, resp->mirror_rules_free);
10166         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10167
10168         return status;
10169 }
10170
10171 /**
10172  * i40e_aq_del_mirror_rule
10173  * @hw: pointer to the hardware structure
10174  * @seid: VEB seid to add mirror rule to
10175  * @entries: Buffer which contains the entities to be mirrored
10176  * @count: number of entities contained in the buffer
10177  * @rule_id:the rule_id of the rule to be delete
10178  *
10179  * Delete a mirror rule for a given veb.
10180  *
10181  **/
10182 static enum i40e_status_code
10183 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10184                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10185                 uint16_t count, uint16_t rule_id)
10186 {
10187         struct i40e_aq_desc desc;
10188         struct i40e_aqc_add_delete_mirror_rule cmd;
10189         uint16_t buff_len = 0;
10190         enum i40e_status_code status;
10191         void *buff = NULL;
10192
10193         i40e_fill_default_direct_cmd_desc(&desc,
10194                                           i40e_aqc_opc_delete_mirror_rule);
10195         memset(&cmd, 0, sizeof(cmd));
10196         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10197                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10198                                                           I40E_AQ_FLAG_RD));
10199                 cmd.num_entries = count;
10200                 buff_len = sizeof(uint16_t) * count;
10201                 desc.datalen = rte_cpu_to_le_16(buff_len);
10202                 buff = (void *)entries;
10203         } else
10204                 /* rule id is filled in destination field for deleting mirror rule */
10205                 cmd.destination = rte_cpu_to_le_16(rule_id);
10206
10207         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10208                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10209         cmd.seid = rte_cpu_to_le_16(seid);
10210
10211         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10212         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10213
10214         return status;
10215 }
10216
10217 /**
10218  * i40e_mirror_rule_set
10219  * @dev: pointer to the hardware structure
10220  * @mirror_conf: mirror rule info
10221  * @sw_id: mirror rule's sw_id
10222  * @on: enable/disable
10223  *
10224  * set a mirror rule.
10225  *
10226  **/
10227 static int
10228 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10229                         struct rte_eth_mirror_conf *mirror_conf,
10230                         uint8_t sw_id, uint8_t on)
10231 {
10232         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10233         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10234         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10235         struct i40e_mirror_rule *parent = NULL;
10236         uint16_t seid, dst_seid, rule_id;
10237         uint16_t i, j = 0;
10238         int ret;
10239
10240         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10241
10242         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10243                 PMD_DRV_LOG(ERR,
10244                         "mirror rule can not be configured without veb or vfs.");
10245                 return -ENOSYS;
10246         }
10247         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10248                 PMD_DRV_LOG(ERR, "mirror table is full.");
10249                 return -ENOSPC;
10250         }
10251         if (mirror_conf->dst_pool > pf->vf_num) {
10252                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10253                                  mirror_conf->dst_pool);
10254                 return -EINVAL;
10255         }
10256
10257         seid = pf->main_vsi->veb->seid;
10258
10259         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10260                 if (sw_id <= it->index) {
10261                         mirr_rule = it;
10262                         break;
10263                 }
10264                 parent = it;
10265         }
10266         if (mirr_rule && sw_id == mirr_rule->index) {
10267                 if (on) {
10268                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10269                         return -EEXIST;
10270                 } else {
10271                         ret = i40e_aq_del_mirror_rule(hw, seid,
10272                                         mirr_rule->rule_type,
10273                                         mirr_rule->entries,
10274                                         mirr_rule->num_entries, mirr_rule->id);
10275                         if (ret < 0) {
10276                                 PMD_DRV_LOG(ERR,
10277                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10278                                         ret, hw->aq.asq_last_status);
10279                                 return -ENOSYS;
10280                         }
10281                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10282                         rte_free(mirr_rule);
10283                         pf->nb_mirror_rule--;
10284                         return 0;
10285                 }
10286         } else if (!on) {
10287                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10288                 return -ENOENT;
10289         }
10290
10291         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10292                                 sizeof(struct i40e_mirror_rule) , 0);
10293         if (!mirr_rule) {
10294                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10295                 return I40E_ERR_NO_MEMORY;
10296         }
10297         switch (mirror_conf->rule_type) {
10298         case ETH_MIRROR_VLAN:
10299                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10300                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10301                                 mirr_rule->entries[j] =
10302                                         mirror_conf->vlan.vlan_id[i];
10303                                 j++;
10304                         }
10305                 }
10306                 if (j == 0) {
10307                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10308                         rte_free(mirr_rule);
10309                         return -EINVAL;
10310                 }
10311                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10312                 break;
10313         case ETH_MIRROR_VIRTUAL_POOL_UP:
10314         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10315                 /* check if the specified pool bit is out of range */
10316                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10317                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10318                         rte_free(mirr_rule);
10319                         return -EINVAL;
10320                 }
10321                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10322                         if (mirror_conf->pool_mask & (1ULL << i)) {
10323                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10324                                 j++;
10325                         }
10326                 }
10327                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10328                         /* add pf vsi to entries */
10329                         mirr_rule->entries[j] = pf->main_vsi_seid;
10330                         j++;
10331                 }
10332                 if (j == 0) {
10333                         PMD_DRV_LOG(ERR, "pool is not specified.");
10334                         rte_free(mirr_rule);
10335                         return -EINVAL;
10336                 }
10337                 /* egress and ingress in aq commands means from switch but not port */
10338                 mirr_rule->rule_type =
10339                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10340                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10341                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10342                 break;
10343         case ETH_MIRROR_UPLINK_PORT:
10344                 /* egress and ingress in aq commands means from switch but not port*/
10345                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10346                 break;
10347         case ETH_MIRROR_DOWNLINK_PORT:
10348                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10349                 break;
10350         default:
10351                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10352                         mirror_conf->rule_type);
10353                 rte_free(mirr_rule);
10354                 return -EINVAL;
10355         }
10356
10357         /* If the dst_pool is equal to vf_num, consider it as PF */
10358         if (mirror_conf->dst_pool == pf->vf_num)
10359                 dst_seid = pf->main_vsi_seid;
10360         else
10361                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10362
10363         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10364                                       mirr_rule->rule_type, mirr_rule->entries,
10365                                       j, &rule_id);
10366         if (ret < 0) {
10367                 PMD_DRV_LOG(ERR,
10368                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10369                         ret, hw->aq.asq_last_status);
10370                 rte_free(mirr_rule);
10371                 return -ENOSYS;
10372         }
10373
10374         mirr_rule->index = sw_id;
10375         mirr_rule->num_entries = j;
10376         mirr_rule->id = rule_id;
10377         mirr_rule->dst_vsi_seid = dst_seid;
10378
10379         if (parent)
10380                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10381         else
10382                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10383
10384         pf->nb_mirror_rule++;
10385         return 0;
10386 }
10387
10388 /**
10389  * i40e_mirror_rule_reset
10390  * @dev: pointer to the device
10391  * @sw_id: mirror rule's sw_id
10392  *
10393  * reset a mirror rule.
10394  *
10395  **/
10396 static int
10397 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10398 {
10399         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10400         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10401         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10402         uint16_t seid;
10403         int ret;
10404
10405         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10406
10407         seid = pf->main_vsi->veb->seid;
10408
10409         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10410                 if (sw_id == it->index) {
10411                         mirr_rule = it;
10412                         break;
10413                 }
10414         }
10415         if (mirr_rule) {
10416                 ret = i40e_aq_del_mirror_rule(hw, seid,
10417                                 mirr_rule->rule_type,
10418                                 mirr_rule->entries,
10419                                 mirr_rule->num_entries, mirr_rule->id);
10420                 if (ret < 0) {
10421                         PMD_DRV_LOG(ERR,
10422                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10423                                 ret, hw->aq.asq_last_status);
10424                         return -ENOSYS;
10425                 }
10426                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10427                 rte_free(mirr_rule);
10428                 pf->nb_mirror_rule--;
10429         } else {
10430                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10431                 return -ENOENT;
10432         }
10433         return 0;
10434 }
10435
10436 static uint64_t
10437 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10438 {
10439         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10440         uint64_t systim_cycles;
10441
10442         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10443         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10444                         << 32;
10445
10446         return systim_cycles;
10447 }
10448
10449 static uint64_t
10450 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10451 {
10452         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10453         uint64_t rx_tstamp;
10454
10455         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10456         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10457                         << 32;
10458
10459         return rx_tstamp;
10460 }
10461
10462 static uint64_t
10463 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10464 {
10465         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10466         uint64_t tx_tstamp;
10467
10468         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10469         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10470                         << 32;
10471
10472         return tx_tstamp;
10473 }
10474
10475 static void
10476 i40e_start_timecounters(struct rte_eth_dev *dev)
10477 {
10478         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10479         struct i40e_adapter *adapter =
10480                         (struct i40e_adapter *)dev->data->dev_private;
10481         struct rte_eth_link link;
10482         uint32_t tsync_inc_l;
10483         uint32_t tsync_inc_h;
10484
10485         /* Get current link speed. */
10486         i40e_dev_link_update(dev, 1);
10487         rte_eth_linkstatus_get(dev, &link);
10488
10489         switch (link.link_speed) {
10490         case ETH_SPEED_NUM_40G:
10491                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10492                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10493                 break;
10494         case ETH_SPEED_NUM_10G:
10495                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10496                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10497                 break;
10498         case ETH_SPEED_NUM_1G:
10499                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10500                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10501                 break;
10502         default:
10503                 tsync_inc_l = 0x0;
10504                 tsync_inc_h = 0x0;
10505         }
10506
10507         /* Set the timesync increment value. */
10508         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10509         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10510
10511         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10512         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10513         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10514
10515         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10516         adapter->systime_tc.cc_shift = 0;
10517         adapter->systime_tc.nsec_mask = 0;
10518
10519         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10520         adapter->rx_tstamp_tc.cc_shift = 0;
10521         adapter->rx_tstamp_tc.nsec_mask = 0;
10522
10523         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10524         adapter->tx_tstamp_tc.cc_shift = 0;
10525         adapter->tx_tstamp_tc.nsec_mask = 0;
10526 }
10527
10528 static int
10529 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10530 {
10531         struct i40e_adapter *adapter =
10532                         (struct i40e_adapter *)dev->data->dev_private;
10533
10534         adapter->systime_tc.nsec += delta;
10535         adapter->rx_tstamp_tc.nsec += delta;
10536         adapter->tx_tstamp_tc.nsec += delta;
10537
10538         return 0;
10539 }
10540
10541 static int
10542 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10543 {
10544         uint64_t ns;
10545         struct i40e_adapter *adapter =
10546                         (struct i40e_adapter *)dev->data->dev_private;
10547
10548         ns = rte_timespec_to_ns(ts);
10549
10550         /* Set the timecounters to a new value. */
10551         adapter->systime_tc.nsec = ns;
10552         adapter->rx_tstamp_tc.nsec = ns;
10553         adapter->tx_tstamp_tc.nsec = ns;
10554
10555         return 0;
10556 }
10557
10558 static int
10559 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10560 {
10561         uint64_t ns, systime_cycles;
10562         struct i40e_adapter *adapter =
10563                         (struct i40e_adapter *)dev->data->dev_private;
10564
10565         systime_cycles = i40e_read_systime_cyclecounter(dev);
10566         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10567         *ts = rte_ns_to_timespec(ns);
10568
10569         return 0;
10570 }
10571
10572 static int
10573 i40e_timesync_enable(struct rte_eth_dev *dev)
10574 {
10575         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10576         uint32_t tsync_ctl_l;
10577         uint32_t tsync_ctl_h;
10578
10579         /* Stop the timesync system time. */
10580         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10581         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10582         /* Reset the timesync system time value. */
10583         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10584         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10585
10586         i40e_start_timecounters(dev);
10587
10588         /* Clear timesync registers. */
10589         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10590         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10591         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10592         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10593         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10594         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10595
10596         /* Enable timestamping of PTP packets. */
10597         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10598         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10599
10600         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10601         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10602         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10603
10604         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10605         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10606
10607         return 0;
10608 }
10609
10610 static int
10611 i40e_timesync_disable(struct rte_eth_dev *dev)
10612 {
10613         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10614         uint32_t tsync_ctl_l;
10615         uint32_t tsync_ctl_h;
10616
10617         /* Disable timestamping of transmitted PTP packets. */
10618         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10619         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10620
10621         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10622         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10623
10624         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10625         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10626
10627         /* Reset the timesync increment value. */
10628         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10629         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10630
10631         return 0;
10632 }
10633
10634 static int
10635 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10636                                 struct timespec *timestamp, uint32_t flags)
10637 {
10638         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10639         struct i40e_adapter *adapter =
10640                 (struct i40e_adapter *)dev->data->dev_private;
10641
10642         uint32_t sync_status;
10643         uint32_t index = flags & 0x03;
10644         uint64_t rx_tstamp_cycles;
10645         uint64_t ns;
10646
10647         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10648         if ((sync_status & (1 << index)) == 0)
10649                 return -EINVAL;
10650
10651         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10652         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10653         *timestamp = rte_ns_to_timespec(ns);
10654
10655         return 0;
10656 }
10657
10658 static int
10659 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10660                                 struct timespec *timestamp)
10661 {
10662         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10663         struct i40e_adapter *adapter =
10664                 (struct i40e_adapter *)dev->data->dev_private;
10665
10666         uint32_t sync_status;
10667         uint64_t tx_tstamp_cycles;
10668         uint64_t ns;
10669
10670         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10671         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10672                 return -EINVAL;
10673
10674         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10675         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10676         *timestamp = rte_ns_to_timespec(ns);
10677
10678         return 0;
10679 }
10680
10681 /*
10682  * i40e_parse_dcb_configure - parse dcb configure from user
10683  * @dev: the device being configured
10684  * @dcb_cfg: pointer of the result of parse
10685  * @*tc_map: bit map of enabled traffic classes
10686  *
10687  * Returns 0 on success, negative value on failure
10688  */
10689 static int
10690 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10691                          struct i40e_dcbx_config *dcb_cfg,
10692                          uint8_t *tc_map)
10693 {
10694         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10695         uint8_t i, tc_bw, bw_lf;
10696
10697         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10698
10699         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10700         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10701                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10702                 return -EINVAL;
10703         }
10704
10705         /* assume each tc has the same bw */
10706         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10707         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10708                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10709         /* to ensure the sum of tcbw is equal to 100 */
10710         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10711         for (i = 0; i < bw_lf; i++)
10712                 dcb_cfg->etscfg.tcbwtable[i]++;
10713
10714         /* assume each tc has the same Transmission Selection Algorithm */
10715         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10716                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10717
10718         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10719                 dcb_cfg->etscfg.prioritytable[i] =
10720                                 dcb_rx_conf->dcb_tc[i];
10721
10722         /* FW needs one App to configure HW */
10723         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10724         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10725         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10726         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10727
10728         if (dcb_rx_conf->nb_tcs == 0)
10729                 *tc_map = 1; /* tc0 only */
10730         else
10731                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10732
10733         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10734                 dcb_cfg->pfc.willing = 0;
10735                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10736                 dcb_cfg->pfc.pfcenable = *tc_map;
10737         }
10738         return 0;
10739 }
10740
10741
10742 static enum i40e_status_code
10743 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10744                               struct i40e_aqc_vsi_properties_data *info,
10745                               uint8_t enabled_tcmap)
10746 {
10747         enum i40e_status_code ret;
10748         int i, total_tc = 0;
10749         uint16_t qpnum_per_tc, bsf, qp_idx;
10750         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10751         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10752         uint16_t used_queues;
10753
10754         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10755         if (ret != I40E_SUCCESS)
10756                 return ret;
10757
10758         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10759                 if (enabled_tcmap & (1 << i))
10760                         total_tc++;
10761         }
10762         if (total_tc == 0)
10763                 total_tc = 1;
10764         vsi->enabled_tc = enabled_tcmap;
10765
10766         /* different VSI has different queues assigned */
10767         if (vsi->type == I40E_VSI_MAIN)
10768                 used_queues = dev_data->nb_rx_queues -
10769                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10770         else if (vsi->type == I40E_VSI_VMDQ2)
10771                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10772         else {
10773                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10774                 return I40E_ERR_NO_AVAILABLE_VSI;
10775         }
10776
10777         qpnum_per_tc = used_queues / total_tc;
10778         /* Number of queues per enabled TC */
10779         if (qpnum_per_tc == 0) {
10780                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10781                 return I40E_ERR_INVALID_QP_ID;
10782         }
10783         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10784                                 I40E_MAX_Q_PER_TC);
10785         bsf = rte_bsf32(qpnum_per_tc);
10786
10787         /**
10788          * Configure TC and queue mapping parameters, for enabled TC,
10789          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10790          * default queue will serve it.
10791          */
10792         qp_idx = 0;
10793         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10794                 if (vsi->enabled_tc & (1 << i)) {
10795                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10796                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10797                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10798                         qp_idx += qpnum_per_tc;
10799                 } else
10800                         info->tc_mapping[i] = 0;
10801         }
10802
10803         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10804         if (vsi->type == I40E_VSI_SRIOV) {
10805                 info->mapping_flags |=
10806                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10807                 for (i = 0; i < vsi->nb_qps; i++)
10808                         info->queue_mapping[i] =
10809                                 rte_cpu_to_le_16(vsi->base_queue + i);
10810         } else {
10811                 info->mapping_flags |=
10812                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10813                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10814         }
10815         info->valid_sections |=
10816                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10817
10818         return I40E_SUCCESS;
10819 }
10820
10821 /*
10822  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10823  * @veb: VEB to be configured
10824  * @tc_map: enabled TC bitmap
10825  *
10826  * Returns 0 on success, negative value on failure
10827  */
10828 static enum i40e_status_code
10829 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10830 {
10831         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10832         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10833         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10834         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10835         enum i40e_status_code ret = I40E_SUCCESS;
10836         int i;
10837         uint32_t bw_max;
10838
10839         /* Check if enabled_tc is same as existing or new TCs */
10840         if (veb->enabled_tc == tc_map)
10841                 return ret;
10842
10843         /* configure tc bandwidth */
10844         memset(&veb_bw, 0, sizeof(veb_bw));
10845         veb_bw.tc_valid_bits = tc_map;
10846         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10847         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10848                 if (tc_map & BIT_ULL(i))
10849                         veb_bw.tc_bw_share_credits[i] = 1;
10850         }
10851         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10852                                                    &veb_bw, NULL);
10853         if (ret) {
10854                 PMD_INIT_LOG(ERR,
10855                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10856                         hw->aq.asq_last_status);
10857                 return ret;
10858         }
10859
10860         memset(&ets_query, 0, sizeof(ets_query));
10861         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10862                                                    &ets_query, NULL);
10863         if (ret != I40E_SUCCESS) {
10864                 PMD_DRV_LOG(ERR,
10865                         "Failed to get switch_comp ETS configuration %u",
10866                         hw->aq.asq_last_status);
10867                 return ret;
10868         }
10869         memset(&bw_query, 0, sizeof(bw_query));
10870         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10871                                                   &bw_query, NULL);
10872         if (ret != I40E_SUCCESS) {
10873                 PMD_DRV_LOG(ERR,
10874                         "Failed to get switch_comp bandwidth configuration %u",
10875                         hw->aq.asq_last_status);
10876                 return ret;
10877         }
10878
10879         /* store and print out BW info */
10880         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10881         veb->bw_info.bw_max = ets_query.tc_bw_max;
10882         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10883         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10884         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10885                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10886                      I40E_16_BIT_WIDTH);
10887         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10888                 veb->bw_info.bw_ets_share_credits[i] =
10889                                 bw_query.tc_bw_share_credits[i];
10890                 veb->bw_info.bw_ets_credits[i] =
10891                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10892                 /* 4 bits per TC, 4th bit is reserved */
10893                 veb->bw_info.bw_ets_max[i] =
10894                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10895                                   RTE_LEN2MASK(3, uint8_t));
10896                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10897                             veb->bw_info.bw_ets_share_credits[i]);
10898                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10899                             veb->bw_info.bw_ets_credits[i]);
10900                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10901                             veb->bw_info.bw_ets_max[i]);
10902         }
10903
10904         veb->enabled_tc = tc_map;
10905
10906         return ret;
10907 }
10908
10909
10910 /*
10911  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10912  * @vsi: VSI to be configured
10913  * @tc_map: enabled TC bitmap
10914  *
10915  * Returns 0 on success, negative value on failure
10916  */
10917 static enum i40e_status_code
10918 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10919 {
10920         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10921         struct i40e_vsi_context ctxt;
10922         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10923         enum i40e_status_code ret = I40E_SUCCESS;
10924         int i;
10925
10926         /* Check if enabled_tc is same as existing or new TCs */
10927         if (vsi->enabled_tc == tc_map)
10928                 return ret;
10929
10930         /* configure tc bandwidth */
10931         memset(&bw_data, 0, sizeof(bw_data));
10932         bw_data.tc_valid_bits = tc_map;
10933         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10934         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10935                 if (tc_map & BIT_ULL(i))
10936                         bw_data.tc_bw_credits[i] = 1;
10937         }
10938         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10939         if (ret) {
10940                 PMD_INIT_LOG(ERR,
10941                         "AQ command Config VSI BW allocation per TC failed = %d",
10942                         hw->aq.asq_last_status);
10943                 goto out;
10944         }
10945         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10946                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10947
10948         /* Update Queue Pairs Mapping for currently enabled UPs */
10949         ctxt.seid = vsi->seid;
10950         ctxt.pf_num = hw->pf_id;
10951         ctxt.vf_num = 0;
10952         ctxt.uplink_seid = vsi->uplink_seid;
10953         ctxt.info = vsi->info;
10954         i40e_get_cap(hw);
10955         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10956         if (ret)
10957                 goto out;
10958
10959         /* Update the VSI after updating the VSI queue-mapping information */
10960         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10961         if (ret) {
10962                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10963                         hw->aq.asq_last_status);
10964                 goto out;
10965         }
10966         /* update the local VSI info with updated queue map */
10967         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10968                                         sizeof(vsi->info.tc_mapping));
10969         rte_memcpy(&vsi->info.queue_mapping,
10970                         &ctxt.info.queue_mapping,
10971                 sizeof(vsi->info.queue_mapping));
10972         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10973         vsi->info.valid_sections = 0;
10974
10975         /* query and update current VSI BW information */
10976         ret = i40e_vsi_get_bw_config(vsi);
10977         if (ret) {
10978                 PMD_INIT_LOG(ERR,
10979                          "Failed updating vsi bw info, err %s aq_err %s",
10980                          i40e_stat_str(hw, ret),
10981                          i40e_aq_str(hw, hw->aq.asq_last_status));
10982                 goto out;
10983         }
10984
10985         vsi->enabled_tc = tc_map;
10986
10987 out:
10988         return ret;
10989 }
10990
10991 /*
10992  * i40e_dcb_hw_configure - program the dcb setting to hw
10993  * @pf: pf the configuration is taken on
10994  * @new_cfg: new configuration
10995  * @tc_map: enabled TC bitmap
10996  *
10997  * Returns 0 on success, negative value on failure
10998  */
10999 static enum i40e_status_code
11000 i40e_dcb_hw_configure(struct i40e_pf *pf,
11001                       struct i40e_dcbx_config *new_cfg,
11002                       uint8_t tc_map)
11003 {
11004         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11005         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11006         struct i40e_vsi *main_vsi = pf->main_vsi;
11007         struct i40e_vsi_list *vsi_list;
11008         enum i40e_status_code ret;
11009         int i;
11010         uint32_t val;
11011
11012         /* Use the FW API if FW > v4.4*/
11013         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11014               (hw->aq.fw_maj_ver >= 5))) {
11015                 PMD_INIT_LOG(ERR,
11016                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11017                 return I40E_ERR_FIRMWARE_API_VERSION;
11018         }
11019
11020         /* Check if need reconfiguration */
11021         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11022                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11023                 return I40E_SUCCESS;
11024         }
11025
11026         /* Copy the new config to the current config */
11027         *old_cfg = *new_cfg;
11028         old_cfg->etsrec = old_cfg->etscfg;
11029         ret = i40e_set_dcb_config(hw);
11030         if (ret) {
11031                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11032                          i40e_stat_str(hw, ret),
11033                          i40e_aq_str(hw, hw->aq.asq_last_status));
11034                 return ret;
11035         }
11036         /* set receive Arbiter to RR mode and ETS scheme by default */
11037         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11038                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11039                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11040                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11041                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11042                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11043                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11044                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11045                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11046                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11047                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11048                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11049                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11050         }
11051         /* get local mib to check whether it is configured correctly */
11052         /* IEEE mode */
11053         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11054         /* Get Local DCB Config */
11055         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11056                                      &hw->local_dcbx_config);
11057
11058         /* if Veb is created, need to update TC of it at first */
11059         if (main_vsi->veb) {
11060                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11061                 if (ret)
11062                         PMD_INIT_LOG(WARNING,
11063                                  "Failed configuring TC for VEB seid=%d",
11064                                  main_vsi->veb->seid);
11065         }
11066         /* Update each VSI */
11067         i40e_vsi_config_tc(main_vsi, tc_map);
11068         if (main_vsi->veb) {
11069                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11070                         /* Beside main VSI and VMDQ VSIs, only enable default
11071                          * TC for other VSIs
11072                          */
11073                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11074                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11075                                                          tc_map);
11076                         else
11077                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11078                                                          I40E_DEFAULT_TCMAP);
11079                         if (ret)
11080                                 PMD_INIT_LOG(WARNING,
11081                                         "Failed configuring TC for VSI seid=%d",
11082                                         vsi_list->vsi->seid);
11083                         /* continue */
11084                 }
11085         }
11086         return I40E_SUCCESS;
11087 }
11088
11089 /*
11090  * i40e_dcb_init_configure - initial dcb config
11091  * @dev: device being configured
11092  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11093  *
11094  * Returns 0 on success, negative value on failure
11095  */
11096 int
11097 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11098 {
11099         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11100         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11101         int i, ret = 0;
11102
11103         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11104                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11105                 return -ENOTSUP;
11106         }
11107
11108         /* DCB initialization:
11109          * Update DCB configuration from the Firmware and configure
11110          * LLDP MIB change event.
11111          */
11112         if (sw_dcb == TRUE) {
11113                 ret = i40e_init_dcb(hw);
11114                 /* If lldp agent is stopped, the return value from
11115                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11116                  * adminq status. Otherwise, it should return success.
11117                  */
11118                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11119                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11120                         memset(&hw->local_dcbx_config, 0,
11121                                 sizeof(struct i40e_dcbx_config));
11122                         /* set dcb default configuration */
11123                         hw->local_dcbx_config.etscfg.willing = 0;
11124                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11125                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11126                         hw->local_dcbx_config.etscfg.tsatable[0] =
11127                                                 I40E_IEEE_TSA_ETS;
11128                         /* all UPs mapping to TC0 */
11129                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11130                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11131                         hw->local_dcbx_config.etsrec =
11132                                 hw->local_dcbx_config.etscfg;
11133                         hw->local_dcbx_config.pfc.willing = 0;
11134                         hw->local_dcbx_config.pfc.pfccap =
11135                                                 I40E_MAX_TRAFFIC_CLASS;
11136                         /* FW needs one App to configure HW */
11137                         hw->local_dcbx_config.numapps = 1;
11138                         hw->local_dcbx_config.app[0].selector =
11139                                                 I40E_APP_SEL_ETHTYPE;
11140                         hw->local_dcbx_config.app[0].priority = 3;
11141                         hw->local_dcbx_config.app[0].protocolid =
11142                                                 I40E_APP_PROTOID_FCOE;
11143                         ret = i40e_set_dcb_config(hw);
11144                         if (ret) {
11145                                 PMD_INIT_LOG(ERR,
11146                                         "default dcb config fails. err = %d, aq_err = %d.",
11147                                         ret, hw->aq.asq_last_status);
11148                                 return -ENOSYS;
11149                         }
11150                 } else {
11151                         PMD_INIT_LOG(ERR,
11152                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11153                                 ret, hw->aq.asq_last_status);
11154                         return -ENOTSUP;
11155                 }
11156         } else {
11157                 ret = i40e_aq_start_lldp(hw, NULL);
11158                 if (ret != I40E_SUCCESS)
11159                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11160
11161                 ret = i40e_init_dcb(hw);
11162                 if (!ret) {
11163                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11164                                 PMD_INIT_LOG(ERR,
11165                                         "HW doesn't support DCBX offload.");
11166                                 return -ENOTSUP;
11167                         }
11168                 } else {
11169                         PMD_INIT_LOG(ERR,
11170                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11171                                 ret, hw->aq.asq_last_status);
11172                         return -ENOTSUP;
11173                 }
11174         }
11175         return 0;
11176 }
11177
11178 /*
11179  * i40e_dcb_setup - setup dcb related config
11180  * @dev: device being configured
11181  *
11182  * Returns 0 on success, negative value on failure
11183  */
11184 static int
11185 i40e_dcb_setup(struct rte_eth_dev *dev)
11186 {
11187         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11188         struct i40e_dcbx_config dcb_cfg;
11189         uint8_t tc_map = 0;
11190         int ret = 0;
11191
11192         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11193                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11194                 return -ENOTSUP;
11195         }
11196
11197         if (pf->vf_num != 0)
11198                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11199
11200         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11201         if (ret) {
11202                 PMD_INIT_LOG(ERR, "invalid dcb config");
11203                 return -EINVAL;
11204         }
11205         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11206         if (ret) {
11207                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11208                 return -ENOSYS;
11209         }
11210
11211         return 0;
11212 }
11213
11214 static int
11215 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11216                       struct rte_eth_dcb_info *dcb_info)
11217 {
11218         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11219         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11220         struct i40e_vsi *vsi = pf->main_vsi;
11221         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11222         uint16_t bsf, tc_mapping;
11223         int i, j = 0;
11224
11225         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11226                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11227         else
11228                 dcb_info->nb_tcs = 1;
11229         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11230                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11231         for (i = 0; i < dcb_info->nb_tcs; i++)
11232                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11233
11234         /* get queue mapping if vmdq is disabled */
11235         if (!pf->nb_cfg_vmdq_vsi) {
11236                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11237                         if (!(vsi->enabled_tc & (1 << i)))
11238                                 continue;
11239                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11240                         dcb_info->tc_queue.tc_rxq[j][i].base =
11241                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11242                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11243                         dcb_info->tc_queue.tc_txq[j][i].base =
11244                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11245                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11246                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11247                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11248                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11249                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11250                 }
11251                 return 0;
11252         }
11253
11254         /* get queue mapping if vmdq is enabled */
11255         do {
11256                 vsi = pf->vmdq[j].vsi;
11257                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11258                         if (!(vsi->enabled_tc & (1 << i)))
11259                                 continue;
11260                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11261                         dcb_info->tc_queue.tc_rxq[j][i].base =
11262                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11263                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11264                         dcb_info->tc_queue.tc_txq[j][i].base =
11265                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11266                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11267                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11268                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11269                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11270                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11271                 }
11272                 j++;
11273         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11274         return 0;
11275 }
11276
11277 static int
11278 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11279 {
11280         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11281         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11282         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11283         uint16_t msix_intr;
11284
11285         msix_intr = intr_handle->intr_vec[queue_id];
11286         if (msix_intr == I40E_MISC_VEC_ID)
11287                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11288                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11289                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11290                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11291         else
11292                 I40E_WRITE_REG(hw,
11293                                I40E_PFINT_DYN_CTLN(msix_intr -
11294                                                    I40E_RX_VEC_START),
11295                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11296                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11297                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11298
11299         I40E_WRITE_FLUSH(hw);
11300         rte_intr_enable(&pci_dev->intr_handle);
11301
11302         return 0;
11303 }
11304
11305 static int
11306 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11307 {
11308         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11309         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11310         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11311         uint16_t msix_intr;
11312
11313         msix_intr = intr_handle->intr_vec[queue_id];
11314         if (msix_intr == I40E_MISC_VEC_ID)
11315                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11316                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11317         else
11318                 I40E_WRITE_REG(hw,
11319                                I40E_PFINT_DYN_CTLN(msix_intr -
11320                                                    I40E_RX_VEC_START),
11321                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11322         I40E_WRITE_FLUSH(hw);
11323
11324         return 0;
11325 }
11326
11327 static int i40e_get_regs(struct rte_eth_dev *dev,
11328                          struct rte_dev_reg_info *regs)
11329 {
11330         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11331         uint32_t *ptr_data = regs->data;
11332         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11333         const struct i40e_reg_info *reg_info;
11334
11335         if (ptr_data == NULL) {
11336                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11337                 regs->width = sizeof(uint32_t);
11338                 return 0;
11339         }
11340
11341         /* The first few registers have to be read using AQ operations */
11342         reg_idx = 0;
11343         while (i40e_regs_adminq[reg_idx].name) {
11344                 reg_info = &i40e_regs_adminq[reg_idx++];
11345                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11346                         for (arr_idx2 = 0;
11347                                         arr_idx2 <= reg_info->count2;
11348                                         arr_idx2++) {
11349                                 reg_offset = arr_idx * reg_info->stride1 +
11350                                         arr_idx2 * reg_info->stride2;
11351                                 reg_offset += reg_info->base_addr;
11352                                 ptr_data[reg_offset >> 2] =
11353                                         i40e_read_rx_ctl(hw, reg_offset);
11354                         }
11355         }
11356
11357         /* The remaining registers can be read using primitives */
11358         reg_idx = 0;
11359         while (i40e_regs_others[reg_idx].name) {
11360                 reg_info = &i40e_regs_others[reg_idx++];
11361                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11362                         for (arr_idx2 = 0;
11363                                         arr_idx2 <= reg_info->count2;
11364                                         arr_idx2++) {
11365                                 reg_offset = arr_idx * reg_info->stride1 +
11366                                         arr_idx2 * reg_info->stride2;
11367                                 reg_offset += reg_info->base_addr;
11368                                 ptr_data[reg_offset >> 2] =
11369                                         I40E_READ_REG(hw, reg_offset);
11370                         }
11371         }
11372
11373         return 0;
11374 }
11375
11376 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11377 {
11378         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11379
11380         /* Convert word count to byte count */
11381         return hw->nvm.sr_size << 1;
11382 }
11383
11384 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11385                            struct rte_dev_eeprom_info *eeprom)
11386 {
11387         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11388         uint16_t *data = eeprom->data;
11389         uint16_t offset, length, cnt_words;
11390         int ret_code;
11391
11392         offset = eeprom->offset >> 1;
11393         length = eeprom->length >> 1;
11394         cnt_words = length;
11395
11396         if (offset > hw->nvm.sr_size ||
11397                 offset + length > hw->nvm.sr_size) {
11398                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11399                 return -EINVAL;
11400         }
11401
11402         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11403
11404         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11405         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11406                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11407                 return -EIO;
11408         }
11409
11410         return 0;
11411 }
11412
11413 static int i40e_get_module_info(struct rte_eth_dev *dev,
11414                                 struct rte_eth_dev_module_info *modinfo)
11415 {
11416         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11417         uint32_t sff8472_comp = 0;
11418         uint32_t sff8472_swap = 0;
11419         uint32_t sff8636_rev = 0;
11420         i40e_status status;
11421         uint32_t type = 0;
11422
11423         /* Check if firmware supports reading module EEPROM. */
11424         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11425                 PMD_DRV_LOG(ERR,
11426                             "Module EEPROM memory read not supported. "
11427                             "Please update the NVM image.\n");
11428                 return -EINVAL;
11429         }
11430
11431         status = i40e_update_link_info(hw);
11432         if (status)
11433                 return -EIO;
11434
11435         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11436                 PMD_DRV_LOG(ERR,
11437                             "Cannot read module EEPROM memory. "
11438                             "No module connected.\n");
11439                 return -EINVAL;
11440         }
11441
11442         type = hw->phy.link_info.module_type[0];
11443
11444         switch (type) {
11445         case I40E_MODULE_TYPE_SFP:
11446                 status = i40e_aq_get_phy_register(hw,
11447                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11448                                 I40E_I2C_EEPROM_DEV_ADDR,
11449                                 I40E_MODULE_SFF_8472_COMP,
11450                                 &sff8472_comp, NULL);
11451                 if (status)
11452                         return -EIO;
11453
11454                 status = i40e_aq_get_phy_register(hw,
11455                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11456                                 I40E_I2C_EEPROM_DEV_ADDR,
11457                                 I40E_MODULE_SFF_8472_SWAP,
11458                                 &sff8472_swap, NULL);
11459                 if (status)
11460                         return -EIO;
11461
11462                 /* Check if the module requires address swap to access
11463                  * the other EEPROM memory page.
11464                  */
11465                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11466                         PMD_DRV_LOG(WARNING,
11467                                     "Module address swap to access "
11468                                     "page 0xA2 is not supported.\n");
11469                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11470                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11471                 } else if (sff8472_comp == 0x00) {
11472                         /* Module is not SFF-8472 compliant */
11473                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11474                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11475                 } else {
11476                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11477                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11478                 }
11479                 break;
11480         case I40E_MODULE_TYPE_QSFP_PLUS:
11481                 /* Read from memory page 0. */
11482                 status = i40e_aq_get_phy_register(hw,
11483                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11484                                 0,
11485                                 I40E_MODULE_REVISION_ADDR,
11486                                 &sff8636_rev, NULL);
11487                 if (status)
11488                         return -EIO;
11489                 /* Determine revision compliance byte */
11490                 if (sff8636_rev > 0x02) {
11491                         /* Module is SFF-8636 compliant */
11492                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11493                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11494                 } else {
11495                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11496                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11497                 }
11498                 break;
11499         case I40E_MODULE_TYPE_QSFP28:
11500                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11501                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11502                 break;
11503         default:
11504                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11505                 return -EINVAL;
11506         }
11507         return 0;
11508 }
11509
11510 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11511                                   struct rte_dev_eeprom_info *info)
11512 {
11513         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11514         bool is_sfp = false;
11515         i40e_status status;
11516         uint8_t *data = info->data;
11517         uint32_t value = 0;
11518         uint32_t i;
11519
11520         if (!info || !info->length || !data)
11521                 return -EINVAL;
11522
11523         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11524                 is_sfp = true;
11525
11526         for (i = 0; i < info->length; i++) {
11527                 u32 offset = i + info->offset;
11528                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11529
11530                 /* Check if we need to access the other memory page */
11531                 if (is_sfp) {
11532                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11533                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11534                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11535                         }
11536                 } else {
11537                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11538                                 /* Compute memory page number and offset. */
11539                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11540                                 addr++;
11541                         }
11542                 }
11543                 status = i40e_aq_get_phy_register(hw,
11544                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11545                                 addr, offset, &value, NULL);
11546                 if (status)
11547                         return -EIO;
11548                 data[i] = (uint8_t)value;
11549         }
11550         return 0;
11551 }
11552
11553 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11554                                      struct ether_addr *mac_addr)
11555 {
11556         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11557         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11558         struct i40e_vsi *vsi = pf->main_vsi;
11559         struct i40e_mac_filter_info mac_filter;
11560         struct i40e_mac_filter *f;
11561         int ret;
11562
11563         if (!is_valid_assigned_ether_addr(mac_addr)) {
11564                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11565                 return -EINVAL;
11566         }
11567
11568         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11569                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11570                         break;
11571         }
11572
11573         if (f == NULL) {
11574                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11575                 return -EIO;
11576         }
11577
11578         mac_filter = f->mac_info;
11579         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11580         if (ret != I40E_SUCCESS) {
11581                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11582                 return -EIO;
11583         }
11584         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11585         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11586         if (ret != I40E_SUCCESS) {
11587                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11588                 return -EIO;
11589         }
11590         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11591
11592         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11593                                         mac_addr->addr_bytes, NULL);
11594         if (ret != I40E_SUCCESS) {
11595                 PMD_DRV_LOG(ERR, "Failed to change mac");
11596                 return -EIO;
11597         }
11598
11599         return 0;
11600 }
11601
11602 static int
11603 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11604 {
11605         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11606         struct rte_eth_dev_data *dev_data = pf->dev_data;
11607         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11608         int ret = 0;
11609
11610         /* check if mtu is within the allowed range */
11611         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11612                 return -EINVAL;
11613
11614         /* mtu setting is forbidden if port is start */
11615         if (dev_data->dev_started) {
11616                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11617                             dev_data->port_id);
11618                 return -EBUSY;
11619         }
11620
11621         if (frame_size > ETHER_MAX_LEN)
11622                 dev_data->dev_conf.rxmode.offloads |=
11623                         DEV_RX_OFFLOAD_JUMBO_FRAME;
11624         else
11625                 dev_data->dev_conf.rxmode.offloads &=
11626                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11627
11628         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11629
11630         return ret;
11631 }
11632
11633 /* Restore ethertype filter */
11634 static void
11635 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11636 {
11637         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11638         struct i40e_ethertype_filter_list
11639                 *ethertype_list = &pf->ethertype.ethertype_list;
11640         struct i40e_ethertype_filter *f;
11641         struct i40e_control_filter_stats stats;
11642         uint16_t flags;
11643
11644         TAILQ_FOREACH(f, ethertype_list, rules) {
11645                 flags = 0;
11646                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11647                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11648                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11649                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11650                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11651
11652                 memset(&stats, 0, sizeof(stats));
11653                 i40e_aq_add_rem_control_packet_filter(hw,
11654                                             f->input.mac_addr.addr_bytes,
11655                                             f->input.ether_type,
11656                                             flags, pf->main_vsi->seid,
11657                                             f->queue, 1, &stats, NULL);
11658         }
11659         PMD_DRV_LOG(INFO, "Ethertype filter:"
11660                     " mac_etype_used = %u, etype_used = %u,"
11661                     " mac_etype_free = %u, etype_free = %u",
11662                     stats.mac_etype_used, stats.etype_used,
11663                     stats.mac_etype_free, stats.etype_free);
11664 }
11665
11666 /* Restore tunnel filter */
11667 static void
11668 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11669 {
11670         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11671         struct i40e_vsi *vsi;
11672         struct i40e_pf_vf *vf;
11673         struct i40e_tunnel_filter_list
11674                 *tunnel_list = &pf->tunnel.tunnel_list;
11675         struct i40e_tunnel_filter *f;
11676         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11677         bool big_buffer = 0;
11678
11679         TAILQ_FOREACH(f, tunnel_list, rules) {
11680                 if (!f->is_to_vf)
11681                         vsi = pf->main_vsi;
11682                 else {
11683                         vf = &pf->vfs[f->vf_id];
11684                         vsi = vf->vsi;
11685                 }
11686                 memset(&cld_filter, 0, sizeof(cld_filter));
11687                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11688                         (struct ether_addr *)&cld_filter.element.outer_mac);
11689                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11690                         (struct ether_addr *)&cld_filter.element.inner_mac);
11691                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11692                 cld_filter.element.flags = f->input.flags;
11693                 cld_filter.element.tenant_id = f->input.tenant_id;
11694                 cld_filter.element.queue_number = f->queue;
11695                 rte_memcpy(cld_filter.general_fields,
11696                            f->input.general_fields,
11697                            sizeof(f->input.general_fields));
11698
11699                 if (((f->input.flags &
11700                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11701                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11702                     ((f->input.flags &
11703                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11704                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11705                     ((f->input.flags &
11706                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11707                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11708                         big_buffer = 1;
11709
11710                 if (big_buffer)
11711                         i40e_aq_add_cloud_filters_big_buffer(hw,
11712                                              vsi->seid, &cld_filter, 1);
11713                 else
11714                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11715                                                   &cld_filter.element, 1);
11716         }
11717 }
11718
11719 /* Restore rss filter */
11720 static inline void
11721 i40e_rss_filter_restore(struct i40e_pf *pf)
11722 {
11723         struct i40e_rte_flow_rss_conf *conf =
11724                                         &pf->rss_info;
11725         if (conf->conf.queue_num)
11726                 i40e_config_rss_filter(pf, conf, TRUE);
11727 }
11728
11729 static void
11730 i40e_filter_restore(struct i40e_pf *pf)
11731 {
11732         i40e_ethertype_filter_restore(pf);
11733         i40e_tunnel_filter_restore(pf);
11734         i40e_fdir_filter_restore(pf);
11735         i40e_rss_filter_restore(pf);
11736 }
11737
11738 static bool
11739 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11740 {
11741         if (strcmp(dev->device->driver->name, drv->driver.name))
11742                 return false;
11743
11744         return true;
11745 }
11746
11747 bool
11748 is_i40e_supported(struct rte_eth_dev *dev)
11749 {
11750         return is_device_supported(dev, &rte_i40e_pmd);
11751 }
11752
11753 struct i40e_customized_pctype*
11754 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11755 {
11756         int i;
11757
11758         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11759                 if (pf->customized_pctype[i].index == index)
11760                         return &pf->customized_pctype[i];
11761         }
11762         return NULL;
11763 }
11764
11765 static int
11766 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11767                               uint32_t pkg_size, uint32_t proto_num,
11768                               struct rte_pmd_i40e_proto_info *proto,
11769                               enum rte_pmd_i40e_package_op op)
11770 {
11771         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11772         uint32_t pctype_num;
11773         struct rte_pmd_i40e_ptype_info *pctype;
11774         uint32_t buff_size;
11775         struct i40e_customized_pctype *new_pctype = NULL;
11776         uint8_t proto_id;
11777         uint8_t pctype_value;
11778         char name[64];
11779         uint32_t i, j, n;
11780         int ret;
11781
11782         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11783             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11784                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11785                 return -1;
11786         }
11787
11788         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11789                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11790                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11791         if (ret) {
11792                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11793                 return -1;
11794         }
11795         if (!pctype_num) {
11796                 PMD_DRV_LOG(INFO, "No new pctype added");
11797                 return -1;
11798         }
11799
11800         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11801         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11802         if (!pctype) {
11803                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11804                 return -1;
11805         }
11806         /* get information about new pctype list */
11807         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11808                                         (uint8_t *)pctype, buff_size,
11809                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11810         if (ret) {
11811                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11812                 rte_free(pctype);
11813                 return -1;
11814         }
11815
11816         /* Update customized pctype. */
11817         for (i = 0; i < pctype_num; i++) {
11818                 pctype_value = pctype[i].ptype_id;
11819                 memset(name, 0, sizeof(name));
11820                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11821                         proto_id = pctype[i].protocols[j];
11822                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11823                                 continue;
11824                         for (n = 0; n < proto_num; n++) {
11825                                 if (proto[n].proto_id != proto_id)
11826                                         continue;
11827                                 strcat(name, proto[n].name);
11828                                 strcat(name, "_");
11829                                 break;
11830                         }
11831                 }
11832                 name[strlen(name) - 1] = '\0';
11833                 if (!strcmp(name, "GTPC"))
11834                         new_pctype =
11835                                 i40e_find_customized_pctype(pf,
11836                                                       I40E_CUSTOMIZED_GTPC);
11837                 else if (!strcmp(name, "GTPU_IPV4"))
11838                         new_pctype =
11839                                 i40e_find_customized_pctype(pf,
11840                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11841                 else if (!strcmp(name, "GTPU_IPV6"))
11842                         new_pctype =
11843                                 i40e_find_customized_pctype(pf,
11844                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11845                 else if (!strcmp(name, "GTPU"))
11846                         new_pctype =
11847                                 i40e_find_customized_pctype(pf,
11848                                                       I40E_CUSTOMIZED_GTPU);
11849                 if (new_pctype) {
11850                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11851                                 new_pctype->pctype = pctype_value;
11852                                 new_pctype->valid = true;
11853                         } else {
11854                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11855                                 new_pctype->valid = false;
11856                         }
11857                 }
11858         }
11859
11860         rte_free(pctype);
11861         return 0;
11862 }
11863
11864 static int
11865 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11866                              uint32_t pkg_size, uint32_t proto_num,
11867                              struct rte_pmd_i40e_proto_info *proto,
11868                              enum rte_pmd_i40e_package_op op)
11869 {
11870         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11871         uint16_t port_id = dev->data->port_id;
11872         uint32_t ptype_num;
11873         struct rte_pmd_i40e_ptype_info *ptype;
11874         uint32_t buff_size;
11875         uint8_t proto_id;
11876         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11877         uint32_t i, j, n;
11878         bool in_tunnel;
11879         int ret;
11880
11881         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11882             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11883                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11884                 return -1;
11885         }
11886
11887         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11888                 rte_pmd_i40e_ptype_mapping_reset(port_id);
11889                 return 0;
11890         }
11891
11892         /* get information about new ptype num */
11893         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11894                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11895                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11896         if (ret) {
11897                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11898                 return ret;
11899         }
11900         if (!ptype_num) {
11901                 PMD_DRV_LOG(INFO, "No new ptype added");
11902                 return -1;
11903         }
11904
11905         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11906         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11907         if (!ptype) {
11908                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11909                 return -1;
11910         }
11911
11912         /* get information about new ptype list */
11913         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11914                                         (uint8_t *)ptype, buff_size,
11915                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11916         if (ret) {
11917                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11918                 rte_free(ptype);
11919                 return ret;
11920         }
11921
11922         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11923         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11924         if (!ptype_mapping) {
11925                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11926                 rte_free(ptype);
11927                 return -1;
11928         }
11929
11930         /* Update ptype mapping table. */
11931         for (i = 0; i < ptype_num; i++) {
11932                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11933                 ptype_mapping[i].sw_ptype = 0;
11934                 in_tunnel = false;
11935                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11936                         proto_id = ptype[i].protocols[j];
11937                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11938                                 continue;
11939                         for (n = 0; n < proto_num; n++) {
11940                                 if (proto[n].proto_id != proto_id)
11941                                         continue;
11942                                 memset(name, 0, sizeof(name));
11943                                 strcpy(name, proto[n].name);
11944                                 if (!strncasecmp(name, "PPPOE", 5))
11945                                         ptype_mapping[i].sw_ptype |=
11946                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11947                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11948                                          !in_tunnel) {
11949                                         ptype_mapping[i].sw_ptype |=
11950                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11951                                         ptype_mapping[i].sw_ptype |=
11952                                                 RTE_PTYPE_L4_FRAG;
11953                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11954                                            in_tunnel) {
11955                                         ptype_mapping[i].sw_ptype |=
11956                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11957                                         ptype_mapping[i].sw_ptype |=
11958                                                 RTE_PTYPE_INNER_L4_FRAG;
11959                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
11960                                         ptype_mapping[i].sw_ptype |=
11961                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11962                                         in_tunnel = true;
11963                                 } else if (!strncasecmp(name, "IPV4", 4) &&
11964                                            !in_tunnel)
11965                                         ptype_mapping[i].sw_ptype |=
11966                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11967                                 else if (!strncasecmp(name, "IPV4", 4) &&
11968                                          in_tunnel)
11969                                         ptype_mapping[i].sw_ptype |=
11970                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11971                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11972                                          !in_tunnel) {
11973                                         ptype_mapping[i].sw_ptype |=
11974                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11975                                         ptype_mapping[i].sw_ptype |=
11976                                                 RTE_PTYPE_L4_FRAG;
11977                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11978                                            in_tunnel) {
11979                                         ptype_mapping[i].sw_ptype |=
11980                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11981                                         ptype_mapping[i].sw_ptype |=
11982                                                 RTE_PTYPE_INNER_L4_FRAG;
11983                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
11984                                         ptype_mapping[i].sw_ptype |=
11985                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11986                                         in_tunnel = true;
11987                                 } else if (!strncasecmp(name, "IPV6", 4) &&
11988                                            !in_tunnel)
11989                                         ptype_mapping[i].sw_ptype |=
11990                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11991                                 else if (!strncasecmp(name, "IPV6", 4) &&
11992                                          in_tunnel)
11993                                         ptype_mapping[i].sw_ptype |=
11994                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11995                                 else if (!strncasecmp(name, "UDP", 3) &&
11996                                          !in_tunnel)
11997                                         ptype_mapping[i].sw_ptype |=
11998                                                 RTE_PTYPE_L4_UDP;
11999                                 else if (!strncasecmp(name, "UDP", 3) &&
12000                                          in_tunnel)
12001                                         ptype_mapping[i].sw_ptype |=
12002                                                 RTE_PTYPE_INNER_L4_UDP;
12003                                 else if (!strncasecmp(name, "TCP", 3) &&
12004                                          !in_tunnel)
12005                                         ptype_mapping[i].sw_ptype |=
12006                                                 RTE_PTYPE_L4_TCP;
12007                                 else if (!strncasecmp(name, "TCP", 3) &&
12008                                          in_tunnel)
12009                                         ptype_mapping[i].sw_ptype |=
12010                                                 RTE_PTYPE_INNER_L4_TCP;
12011                                 else if (!strncasecmp(name, "SCTP", 4) &&
12012                                          !in_tunnel)
12013                                         ptype_mapping[i].sw_ptype |=
12014                                                 RTE_PTYPE_L4_SCTP;
12015                                 else if (!strncasecmp(name, "SCTP", 4) &&
12016                                          in_tunnel)
12017                                         ptype_mapping[i].sw_ptype |=
12018                                                 RTE_PTYPE_INNER_L4_SCTP;
12019                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12020                                           !strncasecmp(name, "ICMPV6", 6)) &&
12021                                          !in_tunnel)
12022                                         ptype_mapping[i].sw_ptype |=
12023                                                 RTE_PTYPE_L4_ICMP;
12024                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12025                                           !strncasecmp(name, "ICMPV6", 6)) &&
12026                                          in_tunnel)
12027                                         ptype_mapping[i].sw_ptype |=
12028                                                 RTE_PTYPE_INNER_L4_ICMP;
12029                                 else if (!strncasecmp(name, "GTPC", 4)) {
12030                                         ptype_mapping[i].sw_ptype |=
12031                                                 RTE_PTYPE_TUNNEL_GTPC;
12032                                         in_tunnel = true;
12033                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12034                                         ptype_mapping[i].sw_ptype |=
12035                                                 RTE_PTYPE_TUNNEL_GTPU;
12036                                         in_tunnel = true;
12037                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12038                                         ptype_mapping[i].sw_ptype |=
12039                                                 RTE_PTYPE_TUNNEL_GRENAT;
12040                                         in_tunnel = true;
12041                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
12042                                         ptype_mapping[i].sw_ptype |=
12043                                                 RTE_PTYPE_TUNNEL_L2TP;
12044                                         in_tunnel = true;
12045                                 }
12046
12047                                 break;
12048                         }
12049                 }
12050         }
12051
12052         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12053                                                 ptype_num, 0);
12054         if (ret)
12055                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12056
12057         rte_free(ptype_mapping);
12058         rte_free(ptype);
12059         return ret;
12060 }
12061
12062 void
12063 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12064                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12065 {
12066         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12067         uint32_t proto_num;
12068         struct rte_pmd_i40e_proto_info *proto;
12069         uint32_t buff_size;
12070         uint32_t i;
12071         int ret;
12072
12073         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12074             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12075                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12076                 return;
12077         }
12078
12079         /* get information about protocol number */
12080         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12081                                        (uint8_t *)&proto_num, sizeof(proto_num),
12082                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12083         if (ret) {
12084                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12085                 return;
12086         }
12087         if (!proto_num) {
12088                 PMD_DRV_LOG(INFO, "No new protocol added");
12089                 return;
12090         }
12091
12092         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12093         proto = rte_zmalloc("new_proto", buff_size, 0);
12094         if (!proto) {
12095                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12096                 return;
12097         }
12098
12099         /* get information about protocol list */
12100         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12101                                         (uint8_t *)proto, buff_size,
12102                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12103         if (ret) {
12104                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12105                 rte_free(proto);
12106                 return;
12107         }
12108
12109         /* Check if GTP is supported. */
12110         for (i = 0; i < proto_num; i++) {
12111                 if (!strncmp(proto[i].name, "GTP", 3)) {
12112                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12113                                 pf->gtp_support = true;
12114                         else
12115                                 pf->gtp_support = false;
12116                         break;
12117                 }
12118         }
12119
12120         /* Update customized pctype info */
12121         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12122                                             proto_num, proto, op);
12123         if (ret)
12124                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12125
12126         /* Update customized ptype info */
12127         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12128                                            proto_num, proto, op);
12129         if (ret)
12130                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12131
12132         rte_free(proto);
12133 }
12134
12135 /* Create a QinQ cloud filter
12136  *
12137  * The Fortville NIC has limited resources for tunnel filters,
12138  * so we can only reuse existing filters.
12139  *
12140  * In step 1 we define which Field Vector fields can be used for
12141  * filter types.
12142  * As we do not have the inner tag defined as a field,
12143  * we have to define it first, by reusing one of L1 entries.
12144  *
12145  * In step 2 we are replacing one of existing filter types with
12146  * a new one for QinQ.
12147  * As we reusing L1 and replacing L2, some of the default filter
12148  * types will disappear,which depends on L1 and L2 entries we reuse.
12149  *
12150  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12151  *
12152  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12153  *              later when we define the cloud filter.
12154  *      a.      Valid_flags.replace_cloud = 0
12155  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12156  *      c.      New_filter = 0x10
12157  *      d.      TR bit = 0xff (optional, not used here)
12158  *      e.      Buffer – 2 entries:
12159  *              i.      Byte 0 = 8 (outer vlan FV index).
12160  *                      Byte 1 = 0 (rsv)
12161  *                      Byte 2-3 = 0x0fff
12162  *              ii.     Byte 0 = 37 (inner vlan FV index).
12163  *                      Byte 1 =0 (rsv)
12164  *                      Byte 2-3 = 0x0fff
12165  *
12166  * Step 2:
12167  * 2.   Create cloud filter using two L1 filters entries: stag and
12168  *              new filter(outer vlan+ inner vlan)
12169  *      a.      Valid_flags.replace_cloud = 1
12170  *      b.      Old_filter = 1 (instead of outer IP)
12171  *      c.      New_filter = 0x10
12172  *      d.      Buffer – 2 entries:
12173  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12174  *                      Byte 1-3 = 0 (rsv)
12175  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12176  *                      Byte 9-11 = 0 (rsv)
12177  */
12178 static int
12179 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12180 {
12181         int ret = -ENOTSUP;
12182         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12183         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12184         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12185
12186         if (pf->support_multi_driver) {
12187                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12188                 return ret;
12189         }
12190
12191         /* Init */
12192         memset(&filter_replace, 0,
12193                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12194         memset(&filter_replace_buf, 0,
12195                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12196
12197         /* create L1 filter */
12198         filter_replace.old_filter_type =
12199                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12200         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12201         filter_replace.tr_bit = 0;
12202
12203         /* Prepare the buffer, 2 entries */
12204         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12205         filter_replace_buf.data[0] |=
12206                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12207         /* Field Vector 12b mask */
12208         filter_replace_buf.data[2] = 0xff;
12209         filter_replace_buf.data[3] = 0x0f;
12210         filter_replace_buf.data[4] =
12211                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12212         filter_replace_buf.data[4] |=
12213                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12214         /* Field Vector 12b mask */
12215         filter_replace_buf.data[6] = 0xff;
12216         filter_replace_buf.data[7] = 0x0f;
12217         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12218                         &filter_replace_buf);
12219         if (ret != I40E_SUCCESS)
12220                 return ret;
12221         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
12222                     "cloud l1 type is changed from 0x%x to 0x%x",
12223                     filter_replace.old_filter_type,
12224                     filter_replace.new_filter_type);
12225
12226         /* Apply the second L2 cloud filter */
12227         memset(&filter_replace, 0,
12228                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12229         memset(&filter_replace_buf, 0,
12230                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12231
12232         /* create L2 filter, input for L2 filter will be L1 filter  */
12233         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12234         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12235         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12236
12237         /* Prepare the buffer, 2 entries */
12238         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12239         filter_replace_buf.data[0] |=
12240                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12241         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12242         filter_replace_buf.data[4] |=
12243                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12244         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12245                         &filter_replace_buf);
12246         if (!ret) {
12247                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
12248                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
12249                             "cloud filter type is changed from 0x%x to 0x%x",
12250                             filter_replace.old_filter_type,
12251                             filter_replace.new_filter_type);
12252         }
12253         return ret;
12254 }
12255
12256 int
12257 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12258                    const struct rte_flow_action_rss *in)
12259 {
12260         if (in->key_len > RTE_DIM(out->key) ||
12261             in->queue_num > RTE_DIM(out->queue))
12262                 return -EINVAL;
12263         out->conf = (struct rte_flow_action_rss){
12264                 .func = in->func,
12265                 .level = in->level,
12266                 .types = in->types,
12267                 .key_len = in->key_len,
12268                 .queue_num = in->queue_num,
12269                 .key = memcpy(out->key, in->key, in->key_len),
12270                 .queue = memcpy(out->queue, in->queue,
12271                                 sizeof(*in->queue) * in->queue_num),
12272         };
12273         return 0;
12274 }
12275
12276 int
12277 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12278                      const struct rte_flow_action_rss *with)
12279 {
12280         return (comp->func == with->func &&
12281                 comp->level == with->level &&
12282                 comp->types == with->types &&
12283                 comp->key_len == with->key_len &&
12284                 comp->queue_num == with->queue_num &&
12285                 !memcmp(comp->key, with->key, with->key_len) &&
12286                 !memcmp(comp->queue, with->queue,
12287                         sizeof(*with->queue) * with->queue_num));
12288 }
12289
12290 int
12291 i40e_config_rss_filter(struct i40e_pf *pf,
12292                 struct i40e_rte_flow_rss_conf *conf, bool add)
12293 {
12294         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12295         uint32_t i, lut = 0;
12296         uint16_t j, num;
12297         struct rte_eth_rss_conf rss_conf = {
12298                 .rss_key = conf->conf.key_len ?
12299                         (void *)(uintptr_t)conf->conf.key : NULL,
12300                 .rss_key_len = conf->conf.key_len,
12301                 .rss_hf = conf->conf.types,
12302         };
12303         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12304
12305         if (!add) {
12306                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12307                         i40e_pf_disable_rss(pf);
12308                         memset(rss_info, 0,
12309                                 sizeof(struct i40e_rte_flow_rss_conf));
12310                         return 0;
12311                 }
12312                 return -EINVAL;
12313         }
12314
12315         if (rss_info->conf.queue_num)
12316                 return -EINVAL;
12317
12318         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12319          * It's necessary to calculate the actual PF queues that are configured.
12320          */
12321         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12322                 num = i40e_pf_calc_configured_queues_num(pf);
12323         else
12324                 num = pf->dev_data->nb_rx_queues;
12325
12326         num = RTE_MIN(num, conf->conf.queue_num);
12327         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12328                         num);
12329
12330         if (num == 0) {
12331                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12332                 return -ENOTSUP;
12333         }
12334
12335         /* Fill in redirection table */
12336         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12337                 if (j == num)
12338                         j = 0;
12339                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12340                         hw->func_caps.rss_table_entry_width) - 1));
12341                 if ((i & 3) == 3)
12342                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12343         }
12344
12345         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12346                 i40e_pf_disable_rss(pf);
12347                 return 0;
12348         }
12349         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12350                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12351                 /* Random default keys */
12352                 static uint32_t rss_key_default[] = {0x6b793944,
12353                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12354                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12355                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12356
12357                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12358                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12359                                                         sizeof(uint32_t);
12360         }
12361
12362         i40e_hw_rss_hash_set(pf, &rss_conf);
12363
12364         if (i40e_rss_conf_init(rss_info, &conf->conf))
12365                 return -EINVAL;
12366
12367         return 0;
12368 }
12369
12370 RTE_INIT(i40e_init_log);
12371 static void
12372 i40e_init_log(void)
12373 {
12374         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12375         if (i40e_logtype_init >= 0)
12376                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12377         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12378         if (i40e_logtype_driver >= 0)
12379                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12380 }
12381
12382 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12383                               QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12384                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");