drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_eth_ctrl.h>
  28 #include <rte_tailq.h>
  29 #include <rte_hash_crc.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  48
  49 #define I40E_CLEAR_PXE_WAIT_MS     200
  50
  51 /* Maximun number of capability elements */
  52 #define I40E_MAX_CAP_ELE_NUM       128
  53
  54 /* Wait count and interval */
  55 #define I40E_CHK_Q_ENA_COUNT       1000
  56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  57
  58 /* Maximun number of VSI */
  59 #define I40E_MAX_NUM_VSIS          (384UL)
  60
  61 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  62
  63 /* Flow control default timer */
  64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  65
  66 /* Flow control enable fwd bit */
  67 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  68
  69 /* Receive Packet Buffer size */
  70 #define I40E_RXPBSIZE (968 * 1024)
  71
  72 /* Kilobytes shift */
  73 #define I40E_KILOSHIFT 10
  74
  75 /* Flow control default high water */
  76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Flow control default low water */
  79 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  80
  81 /* Receive Average Packet Size in Byte*/
  82 #define I40E_PACKET_AVERAGE_SIZE 128
  83
  84 /* Mask of PF interrupt causes */
  85 #define I40E_PFINT_ICR0_ENA_MASK ( \
  86                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  87                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  90                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 /* Additional timesync values. */
 110 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 111 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 112 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 113 #define I40E_PRTTSYN_TSYNENA     0x80000000
 114 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 115 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 116
 117 /**
 118  * Below are values for writing un-exposed registers suggested
 119  * by silicon experts
 120  */
 121 /* Destination MAC address */
 122 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 123 /* Source MAC address */
 124 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 126 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 128 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 129 /* Single VLAN tag in the inner L2 header */
 130 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 131 /* Source IPv4 address */
 132 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 133 /* Destination IPv4 address */
 134 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 135 /* Source IPv4 address for X722 */
 136 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 137 /* Destination IPv4 address for X722 */
 138 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 139 /* IPv4 Protocol for X722 */
 140 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 141 /* IPv4 Time to Live for X722 */
 142 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 143 /* IPv4 Type of Service (TOS) */
 144 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 145 /* IPv4 Protocol */
 146 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 147 /* IPv4 Time to Live */
 148 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 149 /* Source IPv6 address */
 150 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 151 /* Destination IPv6 address */
 152 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 153 /* IPv6 Traffic Class (TC) */
 154 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 155 /* IPv6 Next Header */
 156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 157 /* IPv6 Hop Limit */
 158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 159 /* Source L4 port */
 160 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 161 /* Destination L4 port */
 162 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 163 /* SCTP verification tag */
 164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 167 /* Source port of tunneling UDP */
 168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 169 /* Destination port of tunneling UDP */
 170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 171 /* UDP Tunneling ID, NVGRE/GRE key */
 172 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 173 /* Last ether type */
 174 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 175 /* Tunneling outer destination IPv4 address */
 176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 177 /* Tunneling outer destination IPv6 address */
 178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 179 /* 1st word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 181 /* 2nd word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 183 /* 3rd word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 185 /* 4th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 187 /* 5th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 189 /* 6th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 191 /* 7th word of flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 193 /* 8th word of flex payload */
 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 195 /* all 8 words flex payload */
 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 197 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 198
 199 #define I40E_TRANSLATE_INSET 0
 200 #define I40E_TRANSLATE_REG   1
 201
 202 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 203 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 204 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 205 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 207 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 208
 209 /* PCI offset for querying capability */
 210 #define PCI_DEV_CAP_REG            0xA4
 211 /* PCI offset for enabling/disabling Extended Tag */
 212 #define PCI_DEV_CTRL_REG           0xA8
 213 /* Bit mask of Extended Tag capability */
 214 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 215 /* Bit shift of Extended Tag enable/disable */
 216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 217 /* Bit mask of Extended Tag enable/disable */
 218 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 219
 220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 222 static int i40e_dev_configure(struct rte_eth_dev *dev);
 223 static int i40e_dev_start(struct rte_eth_dev *dev);
 224 static void i40e_dev_stop(struct rte_eth_dev *dev);
 225 static void i40e_dev_close(struct rte_eth_dev *dev);
 226 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 227 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 228 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 229 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 230 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 234                                struct rte_eth_stats *stats);
 235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 236                                struct rte_eth_xstat *xstats, unsigned n);
 237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 238                                      struct rte_eth_xstat_name *xstats_names,
 239                                      unsigned limit);
 240 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 241 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 242                                             uint16_t queue_id,
 243                                             uint8_t stat_idx,
 244                                             uint8_t is_rx);
 245 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 246                                 char *fw_version, size_t fw_size);
 247 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 248                               struct rte_eth_dev_info *dev_info);
 249 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 250                                 uint16_t vlan_id,
 251                                 int on);
 252 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 253                               enum rte_vlan_type vlan_type,
 254                               uint16_t tpid);
 255 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 256 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 257                                       uint16_t queue,
 258                                       int on);
 259 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 260 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 261 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 262 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 263                               struct rte_eth_fc_conf *fc_conf);
 264 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 265                               struct rte_eth_fc_conf *fc_conf);
 266 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 267                                        struct rte_eth_pfc_conf *pfc_conf);
 268 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 269                             struct ether_addr *mac_addr,
 270                             uint32_t index,
 271                             uint32_t pool);
 272 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 273 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 274                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 275                                     uint16_t reta_size);
 276 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 277                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 278                                    uint16_t reta_size);
 279
 280 static int i40e_get_cap(struct i40e_hw *hw);
 281 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 282 static int i40e_pf_setup(struct i40e_pf *pf);
 283 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 284 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 285 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 286 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 287                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 288 static void i40e_stat_update_48(struct i40e_hw *hw,
 289                                uint32_t hireg,
 290                                uint32_t loreg,
 291                                bool offset_loaded,
 292                                uint64_t *offset,
 293                                uint64_t *stat);
 294 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 295 static void i40e_dev_interrupt_handler(void *param);
 296 static void i40e_dev_alarm_handler(void *param);
 297 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 298                                 uint32_t base, uint32_t num);
 299 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 300 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 301                         uint32_t base);
 302 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 303                         uint16_t num);
 304 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 305 static int i40e_veb_release(struct i40e_veb *veb);
 306 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 307                                                 struct i40e_vsi *vsi);
 308 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 309 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 310 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 311                                              struct i40e_macvlan_filter *mv_f,
 312                                              int num,
 313                                              uint16_t vlan);
 314 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 315 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 316                                     struct rte_eth_rss_conf *rss_conf);
 317 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 318                                       struct rte_eth_rss_conf *rss_conf);
 319 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 320                                         struct rte_eth_udp_tunnel *udp_tunnel);
 321 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 322                                         struct rte_eth_udp_tunnel *udp_tunnel);
 323 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 324 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 328                                 enum rte_filter_type filter_type,
 329                                 enum rte_filter_op filter_op,
 330                                 void *arg);
 331 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 332                                   struct rte_eth_dcb_info *dcb_info);
 333 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 334 static void i40e_configure_registers(struct i40e_hw *hw);
 335 static void i40e_hw_init(struct rte_eth_dev *dev);
 336 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 337 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 338                                                      uint16_t seid,
 339                                                      uint16_t rule_type,
 340                                                      uint16_t *entries,
 341                                                      uint16_t count,
 342                                                      uint16_t rule_id);
 343 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 344                         struct rte_eth_mirror_conf *mirror_conf,
 345                         uint8_t sw_id, uint8_t on);
 346 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 347
 348 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 349 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 350 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 351                                            struct timespec *timestamp,
 352                                            uint32_t flags);
 353 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 354                                            struct timespec *timestamp);
 355 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 356
 357 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 358
 359 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 360                                    struct timespec *timestamp);
 361 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 362                                     const struct timespec *timestamp);
 363
 364 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 365                                          uint16_t queue_id);
 366 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 367                                           uint16_t queue_id);
 368
 369 static int i40e_get_regs(struct rte_eth_dev *dev,
 370                          struct rte_dev_reg_info *regs);
 371
 372 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 373
 374 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 375                            struct rte_dev_eeprom_info *eeprom);
 376
 377 static int i40e_get_module_info(struct rte_eth_dev *dev,
 378                                 struct rte_eth_dev_module_info *modinfo);
 379 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 380                                   struct rte_dev_eeprom_info *info);
 381
 382 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 383                                       struct ether_addr *mac_addr);
 384
 385 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 386
 387 static int i40e_ethertype_filter_convert(
 388         const struct rte_eth_ethertype_filter *input,
 389         struct i40e_ethertype_filter *filter);
 390 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 391                                    struct i40e_ethertype_filter *filter);
 392
 393 static int i40e_tunnel_filter_convert(
 394         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 395         struct i40e_tunnel_filter *tunnel_filter);
 396 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 397                                 struct i40e_tunnel_filter *tunnel_filter);
 398 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 399
 400 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 401 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 402 static void i40e_filter_restore(struct i40e_pf *pf);
 403 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 404
 405 int i40e_logtype_init;
 406 int i40e_logtype_driver;
 407
 408 static const char *const valid_keys[] = {
 409         ETH_I40E_FLOATING_VEB_ARG,
 410         ETH_I40E_FLOATING_VEB_LIST_ARG,
 411         ETH_I40E_SUPPORT_MULTI_DRIVER,
 412         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 413         ETH_I40E_USE_LATEST_VEC,
 414         NULL};
 415
 416 static const struct rte_pci_id pci_id_i40e_map[] = {
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 437         { .vendor_id = 0, /* sentinel */ },
 438 };
 439
 440 static const struct eth_dev_ops i40e_eth_dev_ops = {
 441         .dev_configure                = i40e_dev_configure,
 442         .dev_start                    = i40e_dev_start,
 443         .dev_stop                     = i40e_dev_stop,
 444         .dev_close                    = i40e_dev_close,
 445         .dev_reset                    = i40e_dev_reset,
 446         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 447         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 448         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 449         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 450         .dev_set_link_up              = i40e_dev_set_link_up,
 451         .dev_set_link_down            = i40e_dev_set_link_down,
 452         .link_update                  = i40e_dev_link_update,
 453         .stats_get                    = i40e_dev_stats_get,
 454         .xstats_get                   = i40e_dev_xstats_get,
 455         .xstats_get_names             = i40e_dev_xstats_get_names,
 456         .stats_reset                  = i40e_dev_stats_reset,
 457         .xstats_reset                 = i40e_dev_stats_reset,
 458         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 459         .fw_version_get               = i40e_fw_version_get,
 460         .dev_infos_get                = i40e_dev_info_get,
 461         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 462         .vlan_filter_set              = i40e_vlan_filter_set,
 463         .vlan_tpid_set                = i40e_vlan_tpid_set,
 464         .vlan_offload_set             = i40e_vlan_offload_set,
 465         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 466         .vlan_pvid_set                = i40e_vlan_pvid_set,
 467         .rx_queue_start               = i40e_dev_rx_queue_start,
 468         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 469         .tx_queue_start               = i40e_dev_tx_queue_start,
 470         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 471         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 472         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 473         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 474         .rx_queue_release             = i40e_dev_rx_queue_release,
 475         .rx_queue_count               = i40e_dev_rx_queue_count,
 476         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 477         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 478         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 479         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 480         .tx_queue_release             = i40e_dev_tx_queue_release,
 481         .dev_led_on                   = i40e_dev_led_on,
 482         .dev_led_off                  = i40e_dev_led_off,
 483         .flow_ctrl_get                = i40e_flow_ctrl_get,
 484         .flow_ctrl_set                = i40e_flow_ctrl_set,
 485         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 486         .mac_addr_add                 = i40e_macaddr_add,
 487         .mac_addr_remove              = i40e_macaddr_remove,
 488         .reta_update                  = i40e_dev_rss_reta_update,
 489         .reta_query                   = i40e_dev_rss_reta_query,
 490         .rss_hash_update              = i40e_dev_rss_hash_update,
 491         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 492         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 493         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 494         .filter_ctrl                  = i40e_dev_filter_ctrl,
 495         .rxq_info_get                 = i40e_rxq_info_get,
 496         .txq_info_get                 = i40e_txq_info_get,
 497         .mirror_rule_set              = i40e_mirror_rule_set,
 498         .mirror_rule_reset            = i40e_mirror_rule_reset,
 499         .timesync_enable              = i40e_timesync_enable,
 500         .timesync_disable             = i40e_timesync_disable,
 501         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 502         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 503         .get_dcb_info                 = i40e_dev_get_dcb_info,
 504         .timesync_adjust_time         = i40e_timesync_adjust_time,
 505         .timesync_read_time           = i40e_timesync_read_time,
 506         .timesync_write_time          = i40e_timesync_write_time,
 507         .get_reg                      = i40e_get_regs,
 508         .get_eeprom_length            = i40e_get_eeprom_length,
 509         .get_eeprom                   = i40e_get_eeprom,
 510         .get_module_info              = i40e_get_module_info,
 511         .get_module_eeprom            = i40e_get_module_eeprom,
 512         .mac_addr_set                 = i40e_set_default_mac_addr,
 513         .mtu_set                      = i40e_dev_mtu_set,
 514         .tm_ops_get                   = i40e_tm_ops_get,
 515 };
 516
 517 /* store statistics names and its offset in stats structure */
 518 struct rte_i40e_xstats_name_off {
 519         char name[RTE_ETH_XSTATS_NAME_SIZE];
 520         unsigned offset;
 521 };
 522
 523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 524         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 525         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 526         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 527         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 528         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 529                 rx_unknown_protocol)},
 530         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 531         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 532         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 533         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 534 };
 535
 536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 537                 sizeof(rte_i40e_stats_strings[0]))
 538
 539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 540         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 541                 tx_dropped_link_down)},
 542         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 543         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 544                 illegal_bytes)},
 545         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 546         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 547                 mac_local_faults)},
 548         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_remote_faults)},
 550         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 551                 rx_length_errors)},
 552         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 553         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 554         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 555         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 556         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 557         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 558                 rx_size_127)},
 559         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_255)},
 561         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_511)},
 563         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_1023)},
 565         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1522)},
 567         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_big)},
 569         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 570                 rx_undersize)},
 571         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_oversize)},
 573         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 574                 mac_short_packet_dropped)},
 575         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_fragments)},
 577         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 578         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 579         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 580                 tx_size_127)},
 581         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_255)},
 583         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_511)},
 585         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_1023)},
 587         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1522)},
 589         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_big)},
 591         {"rx_flow_director_atr_match_packets",
 592                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 593         {"rx_flow_director_sb_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 595         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 596                 tx_lpi_status)},
 597         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 rx_lpi_status)},
 599         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 600                 tx_lpi_count)},
 601         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 rx_lpi_count)},
 603 };
 604
 605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 606                 sizeof(rte_i40e_hw_port_strings[0]))
 607
 608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 609         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xon_rx)},
 611         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xoff_rx)},
 613 };
 614
 615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 616                 sizeof(rte_i40e_rxq_prio_strings[0]))
 617
 618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 619         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xon_tx)},
 621         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xoff_tx)},
 623         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xon_2_xoff)},
 625 };
 626
 627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 628                 sizeof(rte_i40e_txq_prio_strings[0]))
 629
 630 static int
 631 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 632         struct rte_pci_device *pci_dev)
 633 {
 634         char name[RTE_ETH_NAME_MAX_LEN];
 635         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 636         int i, retval;
 637
 638         if (pci_dev->device.devargs) {
 639                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 640                                 &eth_da);
 641                 if (retval)
 642                         return retval;
 643         }
 644
 645         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 646                 sizeof(struct i40e_adapter),
 647                 eth_dev_pci_specific_init, pci_dev,
 648                 eth_i40e_dev_init, NULL);
 649
 650         if (retval || eth_da.nb_representor_ports < 1)
 651                 return retval;
 652
 653         /* probe VF representor ports */
 654         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 655                 pci_dev->device.name);
 656
 657         if (pf_ethdev == NULL)
 658                 return -ENODEV;
 659
 660         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 661                 struct i40e_vf_representor representor = {
 662                         .vf_id = eth_da.representor_ports[i],
 663                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 664                                 pf_ethdev->data->dev_private)->switch_domain_id,
 665                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 666                                 pf_ethdev->data->dev_private)
 667                 };
 668
 669                 /* representor port net_bdf_port */
 670                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 671                         pci_dev->device.name, eth_da.representor_ports[i]);
 672
 673                 retval = rte_eth_dev_create(&pci_dev->device, name,
 674                         sizeof(struct i40e_vf_representor), NULL, NULL,
 675                         i40e_vf_representor_init, &representor);
 676
 677                 if (retval)
 678                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 679                                 "representor %s.", name);
 680         }
 681
 682         return 0;
 683 }
 684
 685 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 686 {
 687         struct rte_eth_dev *ethdev;
 688
 689         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 690         if (!ethdev)
 691                 return -ENODEV;
 692
 693
 694         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 695                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 696         else
 697                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 698 }
 699
 700 static struct rte_pci_driver rte_i40e_pmd = {
 701         .id_table = pci_id_i40e_map,
 702         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 703                      RTE_PCI_DRV_IOVA_AS_VA,
 704         .probe = eth_i40e_pci_probe,
 705         .remove = eth_i40e_pci_remove,
 706 };
 707
 708 static inline void
 709 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 710                          uint32_t reg_val)
 711 {
 712         uint32_t ori_reg_val;
 713         struct rte_eth_dev *dev;
 714
 715         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 716         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 717         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 718         if (ori_reg_val != reg_val)
 719                 PMD_DRV_LOG(WARNING,
 720                             "i40e device %s changed global register [0x%08x]."
 721                             " original: 0x%08x, new: 0x%08x",
 722                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 723 }
 724
 725 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 726 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 727 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 728
 729 #ifndef I40E_GLQF_ORT
 730 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 731 #endif
 732 #ifndef I40E_GLQF_PIT
 733 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 734 #endif
 735 #ifndef I40E_GLQF_L3_MAP
 736 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 737 #endif
 738
 739 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 740 {
 741         /*
 742          * Initialize registers for parsing packet type of QinQ
 743          * This should be removed from code once proper
 744          * configuration API is added to avoid configuration conflicts
 745          * between ports of the same device.
 746          */
 747         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 748         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 749 }
 750
 751 static inline void i40e_config_automask(struct i40e_pf *pf)
 752 {
 753         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 754         uint32_t val;
 755
 756         /* INTENA flag is not auto-cleared for interrupt */
 757         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 758         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 759                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 760
 761         /* If support multi-driver, PF will use INT0. */
 762         if (!pf->support_multi_driver)
 763                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 764
 765         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 766 }
 767
 768 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 769
 770 /*
 771  * Add a ethertype filter to drop all flow control frames transmitted
 772  * from VSIs.
 773 */
 774 static void
 775 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 776 {
 777         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 778         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 779                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 780                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 781         int ret;
 782
 783         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 784                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 785                                 pf->main_vsi_seid, 0,
 786                                 TRUE, NULL, NULL);
 787         if (ret)
 788                 PMD_INIT_LOG(ERR,
 789                         "Failed to add filter to drop flow control frames from VSIs.");
 790 }
 791
 792 static int
 793 floating_veb_list_handler(__rte_unused const char *key,
 794                           const char *floating_veb_value,
 795                           void *opaque)
 796 {
 797         int idx = 0;
 798         unsigned int count = 0;
 799         char *end = NULL;
 800         int min, max;
 801         bool *vf_floating_veb = opaque;
 802
 803         while (isblank(*floating_veb_value))
 804                 floating_veb_value++;
 805
 806         /* Reset floating VEB configuration for VFs */
 807         for (idx = 0; idx < I40E_MAX_VF; idx++)
 808                 vf_floating_veb[idx] = false;
 809
 810         min = I40E_MAX_VF;
 811         do {
 812                 while (isblank(*floating_veb_value))
 813                         floating_veb_value++;
 814                 if (*floating_veb_value == '\0')
 815                         return -1;
 816                 errno = 0;
 817                 idx = strtoul(floating_veb_value, &end, 10);
 818                 if (errno || end == NULL)
 819                         return -1;
 820                 while (isblank(*end))
 821                         end++;
 822                 if (*end == '-') {
 823                         min = idx;
 824                 } else if ((*end == ';') || (*end == '\0')) {
 825                         max = idx;
 826                         if (min == I40E_MAX_VF)
 827                                 min = idx;
 828                         if (max >= I40E_MAX_VF)
 829                                 max = I40E_MAX_VF - 1;
 830                         for (idx = min; idx <= max; idx++) {
 831                                 vf_floating_veb[idx] = true;
 832                                 count++;
 833                         }
 834                         min = I40E_MAX_VF;
 835                 } else {
 836                         return -1;
 837                 }
 838                 floating_veb_value = end + 1;
 839         } while (*end != '\0');
 840
 841         if (count == 0)
 842                 return -1;
 843
 844         return 0;
 845 }
 846
 847 static void
 848 config_vf_floating_veb(struct rte_devargs *devargs,
 849                        uint16_t floating_veb,
 850                        bool *vf_floating_veb)
 851 {
 852         struct rte_kvargs *kvlist;
 853         int i;
 854         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 855
 856         if (!floating_veb)
 857                 return;
 858         /* All the VFs attach to the floating VEB by default
 859          * when the floating VEB is enabled.
 860          */
 861         for (i = 0; i < I40E_MAX_VF; i++)
 862                 vf_floating_veb[i] = true;
 863
 864         if (devargs == NULL)
 865                 return;
 866
 867         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 868         if (kvlist == NULL)
 869                 return;
 870
 871         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 872                 rte_kvargs_free(kvlist);
 873                 return;
 874         }
 875         /* When the floating_veb_list parameter exists, all the VFs
 876          * will attach to the legacy VEB firstly, then configure VFs
 877          * to the floating VEB according to the floating_veb_list.
 878          */
 879         if (rte_kvargs_process(kvlist, floating_veb_list,
 880                                floating_veb_list_handler,
 881                                vf_floating_veb) < 0) {
 882                 rte_kvargs_free(kvlist);
 883                 return;
 884         }
 885         rte_kvargs_free(kvlist);
 886 }
 887
 888 static int
 889 i40e_check_floating_handler(__rte_unused const char *key,
 890                             const char *value,
 891                             __rte_unused void *opaque)
 892 {
 893         if (strcmp(value, "1"))
 894                 return -1;
 895
 896         return 0;
 897 }
 898
 899 static int
 900 is_floating_veb_supported(struct rte_devargs *devargs)
 901 {
 902         struct rte_kvargs *kvlist;
 903         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 904
 905         if (devargs == NULL)
 906                 return 0;
 907
 908         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 909         if (kvlist == NULL)
 910                 return 0;
 911
 912         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 913                 rte_kvargs_free(kvlist);
 914                 return 0;
 915         }
 916         /* Floating VEB is enabled when there's key-value:
 917          * enable_floating_veb=1
 918          */
 919         if (rte_kvargs_process(kvlist, floating_veb_key,
 920                                i40e_check_floating_handler, NULL) < 0) {
 921                 rte_kvargs_free(kvlist);
 922                 return 0;
 923         }
 924         rte_kvargs_free(kvlist);
 925
 926         return 1;
 927 }
 928
 929 static void
 930 config_floating_veb(struct rte_eth_dev *dev)
 931 {
 932         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 933         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 934         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 935
 936         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 937
 938         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 939                 pf->floating_veb =
 940                         is_floating_veb_supported(pci_dev->device.devargs);
 941                 config_vf_floating_veb(pci_dev->device.devargs,
 942                                        pf->floating_veb,
 943                                        pf->floating_veb_list);
 944         } else {
 945                 pf->floating_veb = false;
 946         }
 947 }
 948
 949 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 950 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 951
 952 static int
 953 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 954 {
 955         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 956         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 957         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 958         int ret;
 959
 960         struct rte_hash_parameters ethertype_hash_params = {
 961                 .name = ethertype_hash_name,
 962                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 963                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 964                 .hash_func = rte_hash_crc,
 965                 .hash_func_init_val = 0,
 966                 .socket_id = rte_socket_id(),
 967         };
 968
 969         /* Initialize ethertype filter rule list and hash */
 970         TAILQ_INIT(&ethertype_rule->ethertype_list);
 971         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 972                  "ethertype_%s", dev->device->name);
 973         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 974         if (!ethertype_rule->hash_table) {
 975                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 976                 return -EINVAL;
 977         }
 978         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 979                                        sizeof(struct i40e_ethertype_filter *) *
 980                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 981                                        0);
 982         if (!ethertype_rule->hash_map) {
 983                 PMD_INIT_LOG(ERR,
 984                              "Failed to allocate memory for ethertype hash map!");
 985                 ret = -ENOMEM;
 986                 goto err_ethertype_hash_map_alloc;
 987         }
 988
 989         return 0;
 990
 991 err_ethertype_hash_map_alloc:
 992         rte_hash_free(ethertype_rule->hash_table);
 993
 994         return ret;
 995 }
 996
 997 static int
 998 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 999 {
1000         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1001         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1002         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1003         int ret;
1004
1005         struct rte_hash_parameters tunnel_hash_params = {
1006                 .name = tunnel_hash_name,
1007                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1008                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1009                 .hash_func = rte_hash_crc,
1010                 .hash_func_init_val = 0,
1011                 .socket_id = rte_socket_id(),
1012         };
1013
1014         /* Initialize tunnel filter rule list and hash */
1015         TAILQ_INIT(&tunnel_rule->tunnel_list);
1016         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1017                  "tunnel_%s", dev->device->name);
1018         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1019         if (!tunnel_rule->hash_table) {
1020                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1021                 return -EINVAL;
1022         }
1023         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1024                                     sizeof(struct i40e_tunnel_filter *) *
1025                                     I40E_MAX_TUNNEL_FILTER_NUM,
1026                                     0);
1027         if (!tunnel_rule->hash_map) {
1028                 PMD_INIT_LOG(ERR,
1029                              "Failed to allocate memory for tunnel hash map!");
1030                 ret = -ENOMEM;
1031                 goto err_tunnel_hash_map_alloc;
1032         }
1033
1034         return 0;
1035
1036 err_tunnel_hash_map_alloc:
1037         rte_hash_free(tunnel_rule->hash_table);
1038
1039         return ret;
1040 }
1041
1042 static int
1043 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1044 {
1045         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1046         struct i40e_fdir_info *fdir_info = &pf->fdir;
1047         char fdir_hash_name[RTE_HASH_NAMESIZE];
1048         int ret;
1049
1050         struct rte_hash_parameters fdir_hash_params = {
1051                 .name = fdir_hash_name,
1052                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1053                 .key_len = sizeof(struct i40e_fdir_input),
1054                 .hash_func = rte_hash_crc,
1055                 .hash_func_init_val = 0,
1056                 .socket_id = rte_socket_id(),
1057         };
1058
1059         /* Initialize flow director filter rule list and hash */
1060         TAILQ_INIT(&fdir_info->fdir_list);
1061         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1062                  "fdir_%s", dev->device->name);
1063         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1064         if (!fdir_info->hash_table) {
1065                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1066                 return -EINVAL;
1067         }
1068         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1069                                           sizeof(struct i40e_fdir_filter *) *
1070                                           I40E_MAX_FDIR_FILTER_NUM,
1071                                           0);
1072         if (!fdir_info->hash_map) {
1073                 PMD_INIT_LOG(ERR,
1074                              "Failed to allocate memory for fdir hash map!");
1075                 ret = -ENOMEM;
1076                 goto err_fdir_hash_map_alloc;
1077         }
1078         return 0;
1079
1080 err_fdir_hash_map_alloc:
1081         rte_hash_free(fdir_info->hash_table);
1082
1083         return ret;
1084 }
1085
1086 static void
1087 i40e_init_customized_info(struct i40e_pf *pf)
1088 {
1089         int i;
1090
1091         /* Initialize customized pctype */
1092         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1093                 pf->customized_pctype[i].index = i;
1094                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1095                 pf->customized_pctype[i].valid = false;
1096         }
1097
1098         pf->gtp_support = false;
1099 }
1100
1101 void
1102 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1103 {
1104         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1105         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1106         struct i40e_queue_regions *info = &pf->queue_region;
1107         uint16_t i;
1108
1109         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1110                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1111
1112         memset(info, 0, sizeof(struct i40e_queue_regions));
1113 }
1114
1115 static int
1116 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1117                                const char *value,
1118                                void *opaque)
1119 {
1120         struct i40e_pf *pf;
1121         unsigned long support_multi_driver;
1122         char *end;
1123
1124         pf = (struct i40e_pf *)opaque;
1125
1126         errno = 0;
1127         support_multi_driver = strtoul(value, &end, 10);
1128         if (errno != 0 || end == value || *end != 0) {
1129                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1130                 return -(EINVAL);
1131         }
1132
1133         if (support_multi_driver == 1 || support_multi_driver == 0)
1134                 pf->support_multi_driver = (bool)support_multi_driver;
1135         else
1136                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1137                             "enable global configuration by default."
1138                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1139         return 0;
1140 }
1141
1142 static int
1143 i40e_support_multi_driver(struct rte_eth_dev *dev)
1144 {
1145         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1146         struct rte_kvargs *kvlist;
1147         int kvargs_count;
1148
1149         /* Enable global configuration by default */
1150         pf->support_multi_driver = false;
1151
1152         if (!dev->device->devargs)
1153                 return 0;
1154
1155         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1156         if (!kvlist)
1157                 return -EINVAL;
1158
1159         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1160         if (!kvargs_count) {
1161                 rte_kvargs_free(kvlist);
1162                 return 0;
1163         }
1164
1165         if (kvargs_count > 1)
1166                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1167                             "the first invalid or last valid one is used !",
1168                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1169
1170         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1171                                i40e_parse_multi_drv_handler, pf) < 0) {
1172                 rte_kvargs_free(kvlist);
1173                 return -EINVAL;
1174         }
1175
1176         rte_kvargs_free(kvlist);
1177         return 0;
1178 }
1179
1180 static int
1181 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1182                                     uint32_t reg_addr, uint64_t reg_val,
1183                                     struct i40e_asq_cmd_details *cmd_details)
1184 {
1185         uint64_t ori_reg_val;
1186         struct rte_eth_dev *dev;
1187         int ret;
1188
1189         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1190         if (ret != I40E_SUCCESS) {
1191                 PMD_DRV_LOG(ERR,
1192                             "Fail to debug read from 0x%08x",
1193                             reg_addr);
1194                 return -EIO;
1195         }
1196         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1197
1198         if (ori_reg_val != reg_val)
1199                 PMD_DRV_LOG(WARNING,
1200                             "i40e device %s changed global register [0x%08x]."
1201                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1202                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1203
1204         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1205 }
1206
1207 static int
1208 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1209                                 const char *value,
1210                                 void *opaque)
1211 {
1212         struct i40e_adapter *ad;
1213         int use_latest_vec;
1214
1215         ad = (struct i40e_adapter *)opaque;
1216
1217         use_latest_vec = atoi(value);
1218
1219         if (use_latest_vec != 0 && use_latest_vec != 1)
1220                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1221
1222         ad->use_latest_vec = (uint8_t)use_latest_vec;
1223
1224         return 0;
1225 }
1226
1227 static int
1228 i40e_use_latest_vec(struct rte_eth_dev *dev)
1229 {
1230         struct i40e_adapter *ad =
1231                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1232         struct rte_kvargs *kvlist;
1233         int kvargs_count;
1234
1235         ad->use_latest_vec = false;
1236
1237         if (!dev->device->devargs)
1238                 return 0;
1239
1240         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1241         if (!kvlist)
1242                 return -EINVAL;
1243
1244         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1245         if (!kvargs_count) {
1246                 rte_kvargs_free(kvlist);
1247                 return 0;
1248         }
1249
1250         if (kvargs_count > 1)
1251                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1252                             "the first invalid or last valid one is used !",
1253                             ETH_I40E_USE_LATEST_VEC);
1254
1255         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1256                                 i40e_parse_latest_vec_handler, ad) < 0) {
1257                 rte_kvargs_free(kvlist);
1258                 return -EINVAL;
1259         }
1260
1261         rte_kvargs_free(kvlist);
1262         return 0;
1263 }
1264
1265 #define I40E_ALARM_INTERVAL 50000 /* us */
1266
1267 static int
1268 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1269 {
1270         struct rte_pci_device *pci_dev;
1271         struct rte_intr_handle *intr_handle;
1272         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1273         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274         struct i40e_vsi *vsi;
1275         int ret;
1276         uint32_t len, val;
1277         uint8_t aq_fail = 0;
1278
1279         PMD_INIT_FUNC_TRACE();
1280
1281         dev->dev_ops = &i40e_eth_dev_ops;
1282         dev->rx_pkt_burst = i40e_recv_pkts;
1283         dev->tx_pkt_burst = i40e_xmit_pkts;
1284         dev->tx_pkt_prepare = i40e_prep_pkts;
1285
1286         /* for secondary processes, we don't initialise any further as primary
1287          * has already done this work. Only check we don't need a different
1288          * RX function */
1289         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1290                 i40e_set_rx_function(dev);
1291                 i40e_set_tx_function(dev);
1292                 return 0;
1293         }
1294         i40e_set_default_ptype_table(dev);
1295         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1296         intr_handle = &pci_dev->intr_handle;
1297
1298         rte_eth_copy_pci_info(dev, pci_dev);
1299
1300         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1301         pf->adapter->eth_dev = dev;
1302         pf->dev_data = dev->data;
1303
1304         hw->back = I40E_PF_TO_ADAPTER(pf);
1305         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1306         if (!hw->hw_addr) {
1307                 PMD_INIT_LOG(ERR,
1308                         "Hardware is not available, as address is NULL");
1309                 return -ENODEV;
1310         }
1311
1312         hw->vendor_id = pci_dev->id.vendor_id;
1313         hw->device_id = pci_dev->id.device_id;
1314         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1315         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1316         hw->bus.device = pci_dev->addr.devid;
1317         hw->bus.func = pci_dev->addr.function;
1318         hw->adapter_stopped = 0;
1319         hw->adapter_closed = 0;
1320
1321         /*
1322          * Switch Tag value should not be identical to either the First Tag
1323          * or Second Tag values. So set something other than common Ethertype
1324          * for internal switching.
1325          */
1326         hw->switch_tag = 0xffff;
1327
1328         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1329         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1330                 PMD_INIT_LOG(ERR, "\nERROR: "
1331                         "Firmware recovery mode detected. Limiting functionality.\n"
1332                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1333                         "User Guide for details on firmware recovery mode.");
1334                 return -EIO;
1335         }
1336
1337         /* Check if need to support multi-driver */
1338         i40e_support_multi_driver(dev);
1339         /* Check if users want the latest supported vec path */
1340         i40e_use_latest_vec(dev);
1341
1342         /* Make sure all is clean before doing PF reset */
1343         i40e_clear_hw(hw);
1344
1345         /* Reset here to make sure all is clean for each PF */
1346         ret = i40e_pf_reset(hw);
1347         if (ret) {
1348                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1349                 return ret;
1350         }
1351
1352         /* Initialize the shared code (base driver) */
1353         ret = i40e_init_shared_code(hw);
1354         if (ret) {
1355                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1356                 return ret;
1357         }
1358
1359         /* Initialize the parameters for adminq */
1360         i40e_init_adminq_parameter(hw);
1361         ret = i40e_init_adminq(hw);
1362         if (ret != I40E_SUCCESS) {
1363                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1364                 return -EIO;
1365         }
1366         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1367                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1368                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1369                      ((hw->nvm.version >> 12) & 0xf),
1370                      ((hw->nvm.version >> 4) & 0xff),
1371                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1372
1373         /* Initialize the hardware */
1374         i40e_hw_init(dev);
1375
1376         i40e_config_automask(pf);
1377
1378         i40e_set_default_pctype_table(dev);
1379
1380         /*
1381          * To work around the NVM issue, initialize registers
1382          * for packet type of QinQ by software.
1383          * It should be removed once issues are fixed in NVM.
1384          */
1385         if (!pf->support_multi_driver)
1386                 i40e_GLQF_reg_init(hw);
1387
1388         /* Initialize the input set for filters (hash and fd) to default value */
1389         i40e_filter_input_set_init(pf);
1390
1391         /* initialise the L3_MAP register */
1392         if (!pf->support_multi_driver) {
1393                 ret = i40e_aq_debug_write_global_register(hw,
1394                                                    I40E_GLQF_L3_MAP(40),
1395                                                    0x00000028,  NULL);
1396                 if (ret)
1397                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1398                                      ret);
1399                 PMD_INIT_LOG(DEBUG,
1400                              "Global register 0x%08x is changed with 0x28",
1401                              I40E_GLQF_L3_MAP(40));
1402         }
1403
1404         /* Need the special FW version to support floating VEB */
1405         config_floating_veb(dev);
1406         /* Clear PXE mode */
1407         i40e_clear_pxe_mode(hw);
1408         i40e_dev_sync_phy_type(hw);
1409
1410         /*
1411          * On X710, performance number is far from the expectation on recent
1412          * firmware versions. The fix for this issue may not be integrated in
1413          * the following firmware version. So the workaround in software driver
1414          * is needed. It needs to modify the initial values of 3 internal only
1415          * registers. Note that the workaround can be removed when it is fixed
1416          * in firmware in the future.
1417          */
1418         i40e_configure_registers(hw);
1419
1420         /* Get hw capabilities */
1421         ret = i40e_get_cap(hw);
1422         if (ret != I40E_SUCCESS) {
1423                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1424                 goto err_get_capabilities;
1425         }
1426
1427         /* Initialize parameters for PF */
1428         ret = i40e_pf_parameter_init(dev);
1429         if (ret != 0) {
1430                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1431                 goto err_parameter_init;
1432         }
1433
1434         /* Initialize the queue management */
1435         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1436         if (ret < 0) {
1437                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1438                 goto err_qp_pool_init;
1439         }
1440         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1441                                 hw->func_caps.num_msix_vectors - 1);
1442         if (ret < 0) {
1443                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1444                 goto err_msix_pool_init;
1445         }
1446
1447         /* Initialize lan hmc */
1448         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1449                                 hw->func_caps.num_rx_qp, 0, 0);
1450         if (ret != I40E_SUCCESS) {
1451                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1452                 goto err_init_lan_hmc;
1453         }
1454
1455         /* Configure lan hmc */
1456         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1457         if (ret != I40E_SUCCESS) {
1458                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1459                 goto err_configure_lan_hmc;
1460         }
1461
1462         /* Get and check the mac address */
1463         i40e_get_mac_addr(hw, hw->mac.addr);
1464         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1465                 PMD_INIT_LOG(ERR, "mac address is not valid");
1466                 ret = -EIO;
1467                 goto err_get_mac_addr;
1468         }
1469         /* Copy the permanent MAC address */
1470         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1471                         (struct ether_addr *) hw->mac.perm_addr);
1472
1473         /* Disable flow control */
1474         hw->fc.requested_mode = I40E_FC_NONE;
1475         i40e_set_fc(hw, &aq_fail, TRUE);
1476
1477         /* Set the global registers with default ether type value */
1478         if (!pf->support_multi_driver) {
1479                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1480                                          ETHER_TYPE_VLAN);
1481                 if (ret != I40E_SUCCESS) {
1482                         PMD_INIT_LOG(ERR,
1483                                      "Failed to set the default outer "
1484                                      "VLAN ether type");
1485                         goto err_setup_pf_switch;
1486                 }
1487         }
1488
1489         /* PF setup, which includes VSI setup */
1490         ret = i40e_pf_setup(pf);
1491         if (ret) {
1492                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1493                 goto err_setup_pf_switch;
1494         }
1495
1496         /* reset all stats of the device, including pf and main vsi */
1497         i40e_dev_stats_reset(dev);
1498
1499         vsi = pf->main_vsi;
1500
1501         /* Disable double vlan by default */
1502         i40e_vsi_config_double_vlan(vsi, FALSE);
1503
1504         /* Disable S-TAG identification when floating_veb is disabled */
1505         if (!pf->floating_veb) {
1506                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1507                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1508                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1509                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1510                 }
1511         }
1512
1513         if (!vsi->max_macaddrs)
1514                 len = ETHER_ADDR_LEN;
1515         else
1516                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1517
1518         /* Should be after VSI initialized */
1519         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1520         if (!dev->data->mac_addrs) {
1521                 PMD_INIT_LOG(ERR,
1522                         "Failed to allocated memory for storing mac address");
1523                 goto err_mac_alloc;
1524         }
1525         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1526                                         &dev->data->mac_addrs[0]);
1527
1528         /* Init dcb to sw mode by default */
1529         ret = i40e_dcb_init_configure(dev, TRUE);
1530         if (ret != I40E_SUCCESS) {
1531                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1532                 pf->flags &= ~I40E_FLAG_DCB;
1533         }
1534         /* Update HW struct after DCB configuration */
1535         i40e_get_cap(hw);
1536
1537         /* initialize pf host driver to setup SRIOV resource if applicable */
1538         i40e_pf_host_init(dev);
1539
1540         /* register callback func to eal lib */
1541         rte_intr_callback_register(intr_handle,
1542                                    i40e_dev_interrupt_handler, dev);
1543
1544         /* configure and enable device interrupt */
1545         i40e_pf_config_irq0(hw, TRUE);
1546         i40e_pf_enable_irq0(hw);
1547
1548         /* enable uio intr after callback register */
1549         rte_intr_enable(intr_handle);
1550
1551         /* By default disable flexible payload in global configuration */
1552         if (!pf->support_multi_driver)
1553                 i40e_flex_payload_reg_set_default(hw);
1554
1555         /*
1556          * Add an ethertype filter to drop all flow control frames transmitted
1557          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1558          * frames to wire.
1559          */
1560         i40e_add_tx_flow_control_drop_filter(pf);
1561
1562         /* Set the max frame size to 0x2600 by default,
1563          * in case other drivers changed the default value.
1564          */
1565         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1566
1567         /* initialize mirror rule list */
1568         TAILQ_INIT(&pf->mirror_list);
1569
1570         /* initialize Traffic Manager configuration */
1571         i40e_tm_conf_init(dev);
1572
1573         /* Initialize customized information */
1574         i40e_init_customized_info(pf);
1575
1576         ret = i40e_init_ethtype_filter_list(dev);
1577         if (ret < 0)
1578                 goto err_init_ethtype_filter_list;
1579         ret = i40e_init_tunnel_filter_list(dev);
1580         if (ret < 0)
1581                 goto err_init_tunnel_filter_list;
1582         ret = i40e_init_fdir_filter_list(dev);
1583         if (ret < 0)
1584                 goto err_init_fdir_filter_list;
1585
1586         /* initialize queue region configuration */
1587         i40e_init_queue_region_conf(dev);
1588
1589         /* initialize rss configuration from rte_flow */
1590         memset(&pf->rss_info, 0,
1591                 sizeof(struct i40e_rte_flow_rss_conf));
1592
1593         return 0;
1594
1595 err_init_fdir_filter_list:
1596         rte_free(pf->tunnel.hash_table);
1597         rte_free(pf->tunnel.hash_map);
1598 err_init_tunnel_filter_list:
1599         rte_free(pf->ethertype.hash_table);
1600         rte_free(pf->ethertype.hash_map);
1601 err_init_ethtype_filter_list:
1602         rte_free(dev->data->mac_addrs);
1603 err_mac_alloc:
1604         i40e_vsi_release(pf->main_vsi);
1605 err_setup_pf_switch:
1606 err_get_mac_addr:
1607 err_configure_lan_hmc:
1608         (void)i40e_shutdown_lan_hmc(hw);
1609 err_init_lan_hmc:
1610         i40e_res_pool_destroy(&pf->msix_pool);
1611 err_msix_pool_init:
1612         i40e_res_pool_destroy(&pf->qp_pool);
1613 err_qp_pool_init:
1614 err_parameter_init:
1615 err_get_capabilities:
1616         (void)i40e_shutdown_adminq(hw);
1617
1618         return ret;
1619 }
1620
1621 static void
1622 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1623 {
1624         struct i40e_ethertype_filter *p_ethertype;
1625         struct i40e_ethertype_rule *ethertype_rule;
1626
1627         ethertype_rule = &pf->ethertype;
1628         /* Remove all ethertype filter rules and hash */
1629         if (ethertype_rule->hash_map)
1630                 rte_free(ethertype_rule->hash_map);
1631         if (ethertype_rule->hash_table)
1632                 rte_hash_free(ethertype_rule->hash_table);
1633
1634         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1635                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1636                              p_ethertype, rules);
1637                 rte_free(p_ethertype);
1638         }
1639 }
1640
1641 static void
1642 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1643 {
1644         struct i40e_tunnel_filter *p_tunnel;
1645         struct i40e_tunnel_rule *tunnel_rule;
1646
1647         tunnel_rule = &pf->tunnel;
1648         /* Remove all tunnel director rules and hash */
1649         if (tunnel_rule->hash_map)
1650                 rte_free(tunnel_rule->hash_map);
1651         if (tunnel_rule->hash_table)
1652                 rte_hash_free(tunnel_rule->hash_table);
1653
1654         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1655                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1656                 rte_free(p_tunnel);
1657         }
1658 }
1659
1660 static void
1661 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1662 {
1663         struct i40e_fdir_filter *p_fdir;
1664         struct i40e_fdir_info *fdir_info;
1665
1666         fdir_info = &pf->fdir;
1667         /* Remove all flow director rules and hash */
1668         if (fdir_info->hash_map)
1669                 rte_free(fdir_info->hash_map);
1670         if (fdir_info->hash_table)
1671                 rte_hash_free(fdir_info->hash_table);
1672
1673         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1674                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1675                 rte_free(p_fdir);
1676         }
1677 }
1678
1679 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1680 {
1681         /*
1682          * Disable by default flexible payload
1683          * for corresponding L2/L3/L4 layers.
1684          */
1685         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1686         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1687         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1688 }
1689
1690 static int
1691 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1692 {
1693         struct i40e_pf *pf;
1694         struct rte_pci_device *pci_dev;
1695         struct rte_intr_handle *intr_handle;
1696         struct i40e_hw *hw;
1697         struct i40e_filter_control_settings settings;
1698         struct rte_flow *p_flow;
1699         int ret;
1700         uint8_t aq_fail = 0;
1701         int retries = 0;
1702
1703         PMD_INIT_FUNC_TRACE();
1704
1705         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1706                 return 0;
1707
1708         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1709         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1710         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1711         intr_handle = &pci_dev->intr_handle;
1712
1713         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1714         if (ret)
1715                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1716
1717         if (hw->adapter_closed == 0)
1718                 i40e_dev_close(dev);
1719
1720         dev->dev_ops = NULL;
1721         dev->rx_pkt_burst = NULL;
1722         dev->tx_pkt_burst = NULL;
1723
1724         /* Clear PXE mode */
1725         i40e_clear_pxe_mode(hw);
1726
1727         /* Unconfigure filter control */
1728         memset(&settings, 0, sizeof(settings));
1729         ret = i40e_set_filter_control(hw, &settings);
1730         if (ret)
1731                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1732                                         ret);
1733
1734         /* Disable flow control */
1735         hw->fc.requested_mode = I40E_FC_NONE;
1736         i40e_set_fc(hw, &aq_fail, TRUE);
1737
1738         /* uninitialize pf host driver */
1739         i40e_pf_host_uninit(dev);
1740
1741         /* disable uio intr before callback unregister */
1742         rte_intr_disable(intr_handle);
1743
1744         /* unregister callback func to eal lib */
1745         do {
1746                 ret = rte_intr_callback_unregister(intr_handle,
1747                                 i40e_dev_interrupt_handler, dev);
1748                 if (ret >= 0) {
1749                         break;
1750                 } else if (ret != -EAGAIN) {
1751                         PMD_INIT_LOG(ERR,
1752                                  "intr callback unregister failed: %d",
1753                                  ret);
1754                         return ret;
1755                 }
1756                 i40e_msec_delay(500);
1757         } while (retries++ < 5);
1758
1759         i40e_rm_ethtype_filter_list(pf);
1760         i40e_rm_tunnel_filter_list(pf);
1761         i40e_rm_fdir_filter_list(pf);
1762
1763         /* Remove all flows */
1764         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1765                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1766                 rte_free(p_flow);
1767         }
1768
1769         /* Remove all Traffic Manager configuration */
1770         i40e_tm_conf_uninit(dev);
1771
1772         return 0;
1773 }
1774
1775 static int
1776 i40e_dev_configure(struct rte_eth_dev *dev)
1777 {
1778         struct i40e_adapter *ad =
1779                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1780         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1782         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1783         int i, ret;
1784
1785         ret = i40e_dev_sync_phy_type(hw);
1786         if (ret)
1787                 return ret;
1788
1789         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1790          * bulk allocation or vector Rx preconditions we will reset it.
1791          */
1792         ad->rx_bulk_alloc_allowed = true;
1793         ad->rx_vec_allowed = true;
1794         ad->tx_simple_allowed = true;
1795         ad->tx_vec_allowed = true;
1796
1797         /* Only legacy filter API needs the following fdir config. So when the
1798          * legacy filter API is deprecated, the following codes should also be
1799          * removed.
1800          */
1801         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1802                 ret = i40e_fdir_setup(pf);
1803                 if (ret != I40E_SUCCESS) {
1804                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1805                         return -ENOTSUP;
1806                 }
1807                 ret = i40e_fdir_configure(dev);
1808                 if (ret < 0) {
1809                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1810                         goto err;
1811                 }
1812         } else
1813                 i40e_fdir_teardown(pf);
1814
1815         ret = i40e_dev_init_vlan(dev);
1816         if (ret < 0)
1817                 goto err;
1818
1819         /* VMDQ setup.
1820          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1821          *  RSS setting have different requirements.
1822          *  General PMD driver call sequence are NIC init, configure,
1823          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1824          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1825          *  applicable. So, VMDQ setting has to be done before
1826          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1827          *  For RSS setting, it will try to calculate actual configured RX queue
1828          *  number, which will be available after rx_queue_setup(). dev_start()
1829          *  function is good to place RSS setup.
1830          */
1831         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1832                 ret = i40e_vmdq_setup(dev);
1833                 if (ret)
1834                         goto err;
1835         }
1836
1837         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1838                 ret = i40e_dcb_setup(dev);
1839                 if (ret) {
1840                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1841                         goto err_dcb;
1842                 }
1843         }
1844
1845         TAILQ_INIT(&pf->flow_list);
1846
1847         return 0;
1848
1849 err_dcb:
1850         /* need to release vmdq resource if exists */
1851         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1852                 i40e_vsi_release(pf->vmdq[i].vsi);
1853                 pf->vmdq[i].vsi = NULL;
1854         }
1855         rte_free(pf->vmdq);
1856         pf->vmdq = NULL;
1857 err:
1858         /* Need to release fdir resource if exists.
1859          * Only legacy filter API needs the following fdir config. So when the
1860          * legacy filter API is deprecated, the following code should also be
1861          * removed.
1862          */
1863         i40e_fdir_teardown(pf);
1864         return ret;
1865 }
1866
1867 void
1868 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1869 {
1870         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1871         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1872         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1873         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1874         uint16_t msix_vect = vsi->msix_intr;
1875         uint16_t i;
1876
1877         for (i = 0; i < vsi->nb_qps; i++) {
1878                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1879                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1880                 rte_wmb();
1881         }
1882
1883         if (vsi->type != I40E_VSI_SRIOV) {
1884                 if (!rte_intr_allow_others(intr_handle)) {
1885                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1886                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1887                         I40E_WRITE_REG(hw,
1888                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1889                                        0);
1890                 } else {
1891                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1892                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1893                         I40E_WRITE_REG(hw,
1894                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1895                                                        msix_vect - 1), 0);
1896                 }
1897         } else {
1898                 uint32_t reg;
1899                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1900                         vsi->user_param + (msix_vect - 1);
1901
1902                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1903                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1904         }
1905         I40E_WRITE_FLUSH(hw);
1906 }
1907
1908 static void
1909 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1910                        int base_queue, int nb_queue,
1911                        uint16_t itr_idx)
1912 {
1913         int i;
1914         uint32_t val;
1915         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1916         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1917
1918         /* Bind all RX queues to allocated MSIX interrupt */
1919         for (i = 0; i < nb_queue; i++) {
1920                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1921                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1922                         ((base_queue + i + 1) <<
1923                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1924                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1925                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1926
1927                 if (i == nb_queue - 1)
1928                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1929                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1930         }
1931
1932         /* Write first RX queue to Link list register as the head element */
1933         if (vsi->type != I40E_VSI_SRIOV) {
1934                 uint16_t interval =
1935                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1936
1937                 if (msix_vect == I40E_MISC_VEC_ID) {
1938                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1939                                        (base_queue <<
1940                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1941                                        (0x0 <<
1942                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1943                         I40E_WRITE_REG(hw,
1944                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1945                                        interval);
1946                 } else {
1947                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1948                                        (base_queue <<
1949                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1950                                        (0x0 <<
1951                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1952                         I40E_WRITE_REG(hw,
1953                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1954                                                        msix_vect - 1),
1955                                        interval);
1956                 }
1957         } else {
1958                 uint32_t reg;
1959
1960                 if (msix_vect == I40E_MISC_VEC_ID) {
1961                         I40E_WRITE_REG(hw,
1962                                        I40E_VPINT_LNKLST0(vsi->user_param),
1963                                        (base_queue <<
1964                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1965                                        (0x0 <<
1966                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1967                 } else {
1968                         /* num_msix_vectors_vf needs to minus irq0 */
1969                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1970                                 vsi->user_param + (msix_vect - 1);
1971
1972                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1973                                        (base_queue <<
1974                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1975                                        (0x0 <<
1976                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1977                 }
1978         }
1979
1980         I40E_WRITE_FLUSH(hw);
1981 }
1982
1983 void
1984 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1985 {
1986         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1987         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1988         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1989         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1990         uint16_t msix_vect = vsi->msix_intr;
1991         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1992         uint16_t queue_idx = 0;
1993         int record = 0;
1994         int i;
1995
1996         for (i = 0; i < vsi->nb_qps; i++) {
1997                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1998                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1999         }
2000
2001         /* VF bind interrupt */
2002         if (vsi->type == I40E_VSI_SRIOV) {
2003                 __vsi_queues_bind_intr(vsi, msix_vect,
2004                                        vsi->base_queue, vsi->nb_qps,
2005                                        itr_idx);
2006                 return;
2007         }
2008
2009         /* PF & VMDq bind interrupt */
2010         if (rte_intr_dp_is_en(intr_handle)) {
2011                 if (vsi->type == I40E_VSI_MAIN) {
2012                         queue_idx = 0;
2013                         record = 1;
2014                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2015                         struct i40e_vsi *main_vsi =
2016                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2017                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2018                         record = 1;
2019                 }
2020         }
2021
2022         for (i = 0; i < vsi->nb_used_qps; i++) {
2023                 if (nb_msix <= 1) {
2024                         if (!rte_intr_allow_others(intr_handle))
2025                                 /* allow to share MISC_VEC_ID */
2026                                 msix_vect = I40E_MISC_VEC_ID;
2027
2028                         /* no enough msix_vect, map all to one */
2029                         __vsi_queues_bind_intr(vsi, msix_vect,
2030                                                vsi->base_queue + i,
2031                                                vsi->nb_used_qps - i,
2032                                                itr_idx);
2033                         for (; !!record && i < vsi->nb_used_qps; i++)
2034                                 intr_handle->intr_vec[queue_idx + i] =
2035                                         msix_vect;
2036                         break;
2037                 }
2038                 /* 1:1 queue/msix_vect mapping */
2039                 __vsi_queues_bind_intr(vsi, msix_vect,
2040                                        vsi->base_queue + i, 1,
2041                                        itr_idx);
2042                 if (!!record)
2043                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2044
2045                 msix_vect++;
2046                 nb_msix--;
2047         }
2048 }
2049
2050 static void
2051 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2052 {
2053         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2054         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2055         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2056         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2057         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2058         uint16_t msix_intr, i;
2059
2060         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2061                 for (i = 0; i < vsi->nb_msix; i++) {
2062                         msix_intr = vsi->msix_intr + i;
2063                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2064                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2065                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2066                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2067                 }
2068         else
2069                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2070                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2071                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2072                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2073
2074         I40E_WRITE_FLUSH(hw);
2075 }
2076
2077 static void
2078 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2079 {
2080         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2081         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2082         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2083         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2084         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2085         uint16_t msix_intr, i;
2086
2087         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2088                 for (i = 0; i < vsi->nb_msix; i++) {
2089                         msix_intr = vsi->msix_intr + i;
2090                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2091                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2092                 }
2093         else
2094                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2095                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2096
2097         I40E_WRITE_FLUSH(hw);
2098 }
2099
2100 static inline uint8_t
2101 i40e_parse_link_speeds(uint16_t link_speeds)
2102 {
2103         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2104
2105         if (link_speeds & ETH_LINK_SPEED_40G)
2106                 link_speed |= I40E_LINK_SPEED_40GB;
2107         if (link_speeds & ETH_LINK_SPEED_25G)
2108                 link_speed |= I40E_LINK_SPEED_25GB;
2109         if (link_speeds & ETH_LINK_SPEED_20G)
2110                 link_speed |= I40E_LINK_SPEED_20GB;
2111         if (link_speeds & ETH_LINK_SPEED_10G)
2112                 link_speed |= I40E_LINK_SPEED_10GB;
2113         if (link_speeds & ETH_LINK_SPEED_1G)
2114                 link_speed |= I40E_LINK_SPEED_1GB;
2115         if (link_speeds & ETH_LINK_SPEED_100M)
2116                 link_speed |= I40E_LINK_SPEED_100MB;
2117
2118         return link_speed;
2119 }
2120
2121 static int
2122 i40e_phy_conf_link(struct i40e_hw *hw,
2123                    uint8_t abilities,
2124                    uint8_t force_speed,
2125                    bool is_up)
2126 {
2127         enum i40e_status_code status;
2128         struct i40e_aq_get_phy_abilities_resp phy_ab;
2129         struct i40e_aq_set_phy_config phy_conf;
2130         enum i40e_aq_phy_type cnt;
2131         uint8_t avail_speed;
2132         uint32_t phy_type_mask = 0;
2133
2134         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2135                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2136                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2137                         I40E_AQ_PHY_FLAG_LOW_POWER;
2138         int ret = -ENOTSUP;
2139
2140         /* To get phy capabilities of available speeds. */
2141         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2142                                               NULL);
2143         if (status) {
2144                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2145                                 status);
2146                 return ret;
2147         }
2148         avail_speed = phy_ab.link_speed;
2149
2150         /* To get the current phy config. */
2151         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2152                                               NULL);
2153         if (status) {
2154                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2155                                 status);
2156                 return ret;
2157         }
2158
2159         /* If link needs to go up and it is in autoneg mode the speed is OK,
2160          * no need to set up again.
2161          */
2162         if (is_up && phy_ab.phy_type != 0 &&
2163                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2164                      phy_ab.link_speed != 0)
2165                 return I40E_SUCCESS;
2166
2167         memset(&phy_conf, 0, sizeof(phy_conf));
2168
2169         /* bits 0-2 use the values from get_phy_abilities_resp */
2170         abilities &= ~mask;
2171         abilities |= phy_ab.abilities & mask;
2172
2173         phy_conf.abilities = abilities;
2174
2175         /* If link needs to go up, but the force speed is not supported,
2176          * Warn users and config the default available speeds.
2177          */
2178         if (is_up && !(force_speed & avail_speed)) {
2179                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2180                 phy_conf.link_speed = avail_speed;
2181         } else {
2182                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2183         }
2184
2185         /* PHY type mask needs to include each type except PHY type extension */
2186         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2187                 phy_type_mask |= 1 << cnt;
2188
2189         /* use get_phy_abilities_resp value for the rest */
2190         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2191         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2192                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2193                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2194         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2195         phy_conf.eee_capability = phy_ab.eee_capability;
2196         phy_conf.eeer = phy_ab.eeer_val;
2197         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2198
2199         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2200                     phy_ab.abilities, phy_ab.link_speed);
2201         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2202                     phy_conf.abilities, phy_conf.link_speed);
2203
2204         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2205         if (status)
2206                 return ret;
2207
2208         return I40E_SUCCESS;
2209 }
2210
2211 static int
2212 i40e_apply_link_speed(struct rte_eth_dev *dev)
2213 {
2214         uint8_t speed;
2215         uint8_t abilities = 0;
2216         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2217         struct rte_eth_conf *conf = &dev->data->dev_conf;
2218
2219         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2220                 conf->link_speeds = ETH_LINK_SPEED_40G |
2221                                     ETH_LINK_SPEED_25G |
2222                                     ETH_LINK_SPEED_20G |
2223                                     ETH_LINK_SPEED_10G |
2224                                     ETH_LINK_SPEED_1G |
2225                                     ETH_LINK_SPEED_100M;
2226         }
2227         speed = i40e_parse_link_speeds(conf->link_speeds);
2228         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2229                      I40E_AQ_PHY_AN_ENABLED |
2230                      I40E_AQ_PHY_LINK_ENABLED;
2231
2232         return i40e_phy_conf_link(hw, abilities, speed, true);
2233 }
2234
2235 static int
2236 i40e_dev_start(struct rte_eth_dev *dev)
2237 {
2238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2239         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240         struct i40e_vsi *main_vsi = pf->main_vsi;
2241         int ret, i;
2242         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2243         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2244         uint32_t intr_vector = 0;
2245         struct i40e_vsi *vsi;
2246
2247         hw->adapter_stopped = 0;
2248
2249         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2250                 PMD_INIT_LOG(ERR,
2251                 "Invalid link_speeds for port %u, autonegotiation disabled",
2252                               dev->data->port_id);
2253                 return -EINVAL;
2254         }
2255
2256         rte_intr_disable(intr_handle);
2257
2258         if ((rte_intr_cap_multiple(intr_handle) ||
2259              !RTE_ETH_DEV_SRIOV(dev).active) &&
2260             dev->data->dev_conf.intr_conf.rxq != 0) {
2261                 intr_vector = dev->data->nb_rx_queues;
2262                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2263                 if (ret)
2264                         return ret;
2265         }
2266
2267         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2268                 intr_handle->intr_vec =
2269                         rte_zmalloc("intr_vec",
2270                                     dev->data->nb_rx_queues * sizeof(int),
2271                                     0);
2272                 if (!intr_handle->intr_vec) {
2273                         PMD_INIT_LOG(ERR,
2274                                 "Failed to allocate %d rx_queues intr_vec",
2275                                 dev->data->nb_rx_queues);
2276                         return -ENOMEM;
2277                 }
2278         }
2279
2280         /* Initialize VSI */
2281         ret = i40e_dev_rxtx_init(pf);
2282         if (ret != I40E_SUCCESS) {
2283                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2284                 goto err_up;
2285         }
2286
2287         /* Map queues with MSIX interrupt */
2288         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2289                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2290         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2291         i40e_vsi_enable_queues_intr(main_vsi);
2292
2293         /* Map VMDQ VSI queues with MSIX interrupt */
2294         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2295                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2296                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2297                                           I40E_ITR_INDEX_DEFAULT);
2298                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2299         }
2300
2301         /* enable FDIR MSIX interrupt */
2302         if (pf->fdir.fdir_vsi) {
2303                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2304                                           I40E_ITR_INDEX_NONE);
2305                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2306         }
2307
2308         /* Enable all queues which have been configured */
2309         ret = i40e_dev_switch_queues(pf, TRUE);
2310         if (ret != I40E_SUCCESS) {
2311                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2312                 goto err_up;
2313         }
2314
2315         /* Enable receiving broadcast packets */
2316         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2317         if (ret != I40E_SUCCESS)
2318                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2319
2320         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2321                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2322                                                 true, NULL);
2323                 if (ret != I40E_SUCCESS)
2324                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2325         }
2326
2327         /* Enable the VLAN promiscuous mode. */
2328         if (pf->vfs) {
2329                 for (i = 0; i < pf->vf_num; i++) {
2330                         vsi = pf->vfs[i].vsi;
2331                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2332                                                      true, NULL);
2333                 }
2334         }
2335
2336         /* Enable mac loopback mode */
2337         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2338             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2339                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2340                 if (ret != I40E_SUCCESS) {
2341                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2342                         goto err_up;
2343                 }
2344         }
2345
2346         /* Apply link configure */
2347         ret = i40e_apply_link_speed(dev);
2348         if (I40E_SUCCESS != ret) {
2349                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2350                 goto err_up;
2351         }
2352
2353         if (!rte_intr_allow_others(intr_handle)) {
2354                 rte_intr_callback_unregister(intr_handle,
2355                                              i40e_dev_interrupt_handler,
2356                                              (void *)dev);
2357                 /* configure and enable device interrupt */
2358                 i40e_pf_config_irq0(hw, FALSE);
2359                 i40e_pf_enable_irq0(hw);
2360
2361                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2362                         PMD_INIT_LOG(INFO,
2363                                 "lsc won't enable because of no intr multiplex");
2364         } else {
2365                 ret = i40e_aq_set_phy_int_mask(hw,
2366                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2367                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2368                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2369                 if (ret != I40E_SUCCESS)
2370                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2371
2372                 /* Call get_link_info aq commond to enable/disable LSE */
2373                 i40e_dev_link_update(dev, 0);
2374         }
2375
2376         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2377                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2378                                   i40e_dev_alarm_handler, dev);
2379         } else {
2380                 /* enable uio intr after callback register */
2381                 rte_intr_enable(intr_handle);
2382         }
2383
2384         i40e_filter_restore(pf);
2385
2386         if (pf->tm_conf.root && !pf->tm_conf.committed)
2387                 PMD_DRV_LOG(WARNING,
2388                             "please call hierarchy_commit() "
2389                             "before starting the port");
2390
2391         return I40E_SUCCESS;
2392
2393 err_up:
2394         i40e_dev_switch_queues(pf, FALSE);
2395         i40e_dev_clear_queues(dev);
2396
2397         return ret;
2398 }
2399
2400 static void
2401 i40e_dev_stop(struct rte_eth_dev *dev)
2402 {
2403         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2404         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2405         struct i40e_vsi *main_vsi = pf->main_vsi;
2406         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2407         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2408         int i;
2409
2410         if (hw->adapter_stopped == 1)
2411                 return;
2412
2413         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2414                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2415                 rte_intr_enable(intr_handle);
2416         }
2417
2418         /* Disable all queues */
2419         i40e_dev_switch_queues(pf, FALSE);
2420
2421         /* un-map queues with interrupt registers */
2422         i40e_vsi_disable_queues_intr(main_vsi);
2423         i40e_vsi_queues_unbind_intr(main_vsi);
2424
2425         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2426                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2427                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2428         }
2429
2430         if (pf->fdir.fdir_vsi) {
2431                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2432                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2433         }
2434         /* Clear all queues and release memory */
2435         i40e_dev_clear_queues(dev);
2436
2437         /* Set link down */
2438         i40e_dev_set_link_down(dev);
2439
2440         if (!rte_intr_allow_others(intr_handle))
2441                 /* resume to the default handler */
2442                 rte_intr_callback_register(intr_handle,
2443                                            i40e_dev_interrupt_handler,
2444                                            (void *)dev);
2445
2446         /* Clean datapath event and queue/vec mapping */
2447         rte_intr_efd_disable(intr_handle);
2448         if (intr_handle->intr_vec) {
2449                 rte_free(intr_handle->intr_vec);
2450                 intr_handle->intr_vec = NULL;
2451         }
2452
2453         /* reset hierarchy commit */
2454         pf->tm_conf.committed = false;
2455
2456         hw->adapter_stopped = 1;
2457
2458         pf->adapter->rss_reta_updated = 0;
2459 }
2460
2461 static void
2462 i40e_dev_close(struct rte_eth_dev *dev)
2463 {
2464         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2465         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2467         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2468         struct i40e_mirror_rule *p_mirror;
2469         uint32_t reg;
2470         int i;
2471         int ret;
2472
2473         PMD_INIT_FUNC_TRACE();
2474
2475         i40e_dev_stop(dev);
2476
2477         /* Remove all mirror rules */
2478         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2479                 ret = i40e_aq_del_mirror_rule(hw,
2480                                               pf->main_vsi->veb->seid,
2481                                               p_mirror->rule_type,
2482                                               p_mirror->entries,
2483                                               p_mirror->num_entries,
2484                                               p_mirror->id);
2485                 if (ret < 0)
2486                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2487                                     "status = %d, aq_err = %d.", ret,
2488                                     hw->aq.asq_last_status);
2489
2490                 /* remove mirror software resource anyway */
2491                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2492                 rte_free(p_mirror);
2493                 pf->nb_mirror_rule--;
2494         }
2495
2496         i40e_dev_free_queues(dev);
2497
2498         /* Disable interrupt */
2499         i40e_pf_disable_irq0(hw);
2500         rte_intr_disable(intr_handle);
2501
2502         /*
2503          * Only legacy filter API needs the following fdir config. So when the
2504          * legacy filter API is deprecated, the following code should also be
2505          * removed.
2506          */
2507         i40e_fdir_teardown(pf);
2508
2509         /* shutdown and destroy the HMC */
2510         i40e_shutdown_lan_hmc(hw);
2511
2512         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2513                 i40e_vsi_release(pf->vmdq[i].vsi);
2514                 pf->vmdq[i].vsi = NULL;
2515         }
2516         rte_free(pf->vmdq);
2517         pf->vmdq = NULL;
2518
2519         /* release all the existing VSIs and VEBs */
2520         i40e_vsi_release(pf->main_vsi);
2521
2522         /* shutdown the adminq */
2523         i40e_aq_queue_shutdown(hw, true);
2524         i40e_shutdown_adminq(hw);
2525
2526         i40e_res_pool_destroy(&pf->qp_pool);
2527         i40e_res_pool_destroy(&pf->msix_pool);
2528
2529         /* Disable flexible payload in global configuration */
2530         if (!pf->support_multi_driver)
2531                 i40e_flex_payload_reg_set_default(hw);
2532
2533         /* force a PF reset to clean anything leftover */
2534         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2535         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2536                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2537         I40E_WRITE_FLUSH(hw);
2538
2539         hw->adapter_closed = 1;
2540 }
2541
2542 /*
2543  * Reset PF device only to re-initialize resources in PMD layer
2544  */
2545 static int
2546 i40e_dev_reset(struct rte_eth_dev *dev)
2547 {
2548         int ret;
2549
2550         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2551          * its VF to make them align with it. The detailed notification
2552          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2553          * To avoid unexpected behavior in VF, currently reset of PF with
2554          * SR-IOV activation is not supported. It might be supported later.
2555          */
2556         if (dev->data->sriov.active)
2557                 return -ENOTSUP;
2558
2559         ret = eth_i40e_dev_uninit(dev);
2560         if (ret)
2561                 return ret;
2562
2563         ret = eth_i40e_dev_init(dev, NULL);
2564
2565         return ret;
2566 }
2567
2568 static void
2569 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2570 {
2571         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2572         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2573         struct i40e_vsi *vsi = pf->main_vsi;
2574         int status;
2575
2576         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2577                                                      true, NULL, true);
2578         if (status != I40E_SUCCESS)
2579                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2580
2581         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2582                                                         TRUE, NULL);
2583         if (status != I40E_SUCCESS)
2584                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2585
2586 }
2587
2588 static void
2589 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2590 {
2591         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2592         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2593         struct i40e_vsi *vsi = pf->main_vsi;
2594         int status;
2595
2596         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2597                                                      false, NULL, true);
2598         if (status != I40E_SUCCESS)
2599                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2600
2601         /* must remain in all_multicast mode */
2602         if (dev->data->all_multicast == 1)
2603                 return;
2604
2605         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2606                                                         false, NULL);
2607         if (status != I40E_SUCCESS)
2608                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2609 }
2610
2611 static void
2612 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2613 {
2614         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616         struct i40e_vsi *vsi = pf->main_vsi;
2617         int ret;
2618
2619         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2620         if (ret != I40E_SUCCESS)
2621                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2622 }
2623
2624 static void
2625 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2626 {
2627         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2628         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2629         struct i40e_vsi *vsi = pf->main_vsi;
2630         int ret;
2631
2632         if (dev->data->promiscuous == 1)
2633                 return; /* must remain in all_multicast mode */
2634
2635         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2636                                 vsi->seid, FALSE, NULL);
2637         if (ret != I40E_SUCCESS)
2638                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2639 }
2640
2641 /*
2642  * Set device link up.
2643  */
2644 static int
2645 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2646 {
2647         /* re-apply link speed setting */
2648         return i40e_apply_link_speed(dev);
2649 }
2650
2651 /*
2652  * Set device link down.
2653  */
2654 static int
2655 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2656 {
2657         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2658         uint8_t abilities = 0;
2659         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2660
2661         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2662         return i40e_phy_conf_link(hw, abilities, speed, false);
2663 }
2664
2665 static __rte_always_inline void
2666 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2667 {
2668 /* Link status registers and values*/
2669 #define I40E_PRTMAC_LINKSTA             0x001E2420
2670 #define I40E_REG_LINK_UP                0x40000080
2671 #define I40E_PRTMAC_MACC                0x001E24E0
2672 #define I40E_REG_MACC_25GB              0x00020000
2673 #define I40E_REG_SPEED_MASK             0x38000000
2674 #define I40E_REG_SPEED_100MB            0x00000000
2675 #define I40E_REG_SPEED_1GB              0x08000000
2676 #define I40E_REG_SPEED_10GB             0x10000000
2677 #define I40E_REG_SPEED_20GB             0x20000000
2678 #define I40E_REG_SPEED_25_40GB          0x18000000
2679         uint32_t link_speed;
2680         uint32_t reg_val;
2681
2682         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2683         link_speed = reg_val & I40E_REG_SPEED_MASK;
2684         reg_val &= I40E_REG_LINK_UP;
2685         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2686
2687         if (unlikely(link->link_status == 0))
2688                 return;
2689
2690         /* Parse the link status */
2691         switch (link_speed) {
2692         case I40E_REG_SPEED_100MB:
2693                 link->link_speed = ETH_SPEED_NUM_100M;
2694                 break;
2695         case I40E_REG_SPEED_1GB:
2696                 link->link_speed = ETH_SPEED_NUM_1G;
2697                 break;
2698         case I40E_REG_SPEED_10GB:
2699                 link->link_speed = ETH_SPEED_NUM_10G;
2700                 break;
2701         case I40E_REG_SPEED_20GB:
2702                 link->link_speed = ETH_SPEED_NUM_20G;
2703                 break;
2704         case I40E_REG_SPEED_25_40GB:
2705                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2706
2707                 if (reg_val & I40E_REG_MACC_25GB)
2708                         link->link_speed = ETH_SPEED_NUM_25G;
2709                 else
2710                         link->link_speed = ETH_SPEED_NUM_40G;
2711
2712                 break;
2713         default:
2714                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2715                 break;
2716         }
2717 }
2718
2719 static __rte_always_inline void
2720 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2721         bool enable_lse, int wait_to_complete)
2722 {
2723 #define CHECK_INTERVAL             100  /* 100ms */
2724 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2725         uint32_t rep_cnt = MAX_REPEAT_TIME;
2726         struct i40e_link_status link_status;
2727         int status;
2728
2729         memset(&link_status, 0, sizeof(link_status));
2730
2731         do {
2732                 memset(&link_status, 0, sizeof(link_status));
2733
2734                 /* Get link status information from hardware */
2735                 status = i40e_aq_get_link_info(hw, enable_lse,
2736                                                 &link_status, NULL);
2737                 if (unlikely(status != I40E_SUCCESS)) {
2738                         link->link_speed = ETH_SPEED_NUM_100M;
2739                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2740                         PMD_DRV_LOG(ERR, "Failed to get link info");
2741                         return;
2742                 }
2743
2744                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2745                 if (!wait_to_complete || link->link_status)
2746                         break;
2747
2748                 rte_delay_ms(CHECK_INTERVAL);
2749         } while (--rep_cnt);
2750
2751         /* Parse the link status */
2752         switch (link_status.link_speed) {
2753         case I40E_LINK_SPEED_100MB:
2754                 link->link_speed = ETH_SPEED_NUM_100M;
2755                 break;
2756         case I40E_LINK_SPEED_1GB:
2757                 link->link_speed = ETH_SPEED_NUM_1G;
2758                 break;
2759         case I40E_LINK_SPEED_10GB:
2760                 link->link_speed = ETH_SPEED_NUM_10G;
2761                 break;
2762         case I40E_LINK_SPEED_20GB:
2763                 link->link_speed = ETH_SPEED_NUM_20G;
2764                 break;
2765         case I40E_LINK_SPEED_25GB:
2766                 link->link_speed = ETH_SPEED_NUM_25G;
2767                 break;
2768         case I40E_LINK_SPEED_40GB:
2769                 link->link_speed = ETH_SPEED_NUM_40G;
2770                 break;
2771         default:
2772                 link->link_speed = ETH_SPEED_NUM_100M;
2773                 break;
2774         }
2775 }
2776
2777 int
2778 i40e_dev_link_update(struct rte_eth_dev *dev,
2779                      int wait_to_complete)
2780 {
2781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782         struct rte_eth_link link;
2783         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2784         int ret;
2785
2786         memset(&link, 0, sizeof(link));
2787
2788         /* i40e uses full duplex only */
2789         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2790         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2791                         ETH_LINK_SPEED_FIXED);
2792
2793         if (!wait_to_complete && !enable_lse)
2794                 update_link_reg(hw, &link);
2795         else
2796                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2797
2798         ret = rte_eth_linkstatus_set(dev, &link);
2799         i40e_notify_all_vfs_link_status(dev);
2800
2801         return ret;
2802 }
2803
2804 /* Get all the statistics of a VSI */
2805 void
2806 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2807 {
2808         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2809         struct i40e_eth_stats *nes = &vsi->eth_stats;
2810         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2811         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2812
2813         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2814                             vsi->offset_loaded, &oes->rx_bytes,
2815                             &nes->rx_bytes);
2816         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2817                             vsi->offset_loaded, &oes->rx_unicast,
2818                             &nes->rx_unicast);
2819         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2820                             vsi->offset_loaded, &oes->rx_multicast,
2821                             &nes->rx_multicast);
2822         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2823                             vsi->offset_loaded, &oes->rx_broadcast,
2824                             &nes->rx_broadcast);
2825         /* exclude CRC bytes */
2826         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2827                 nes->rx_broadcast) * ETHER_CRC_LEN;
2828
2829         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2830                             &oes->rx_discards, &nes->rx_discards);
2831         /* GLV_REPC not supported */
2832         /* GLV_RMPC not supported */
2833         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2834                             &oes->rx_unknown_protocol,
2835                             &nes->rx_unknown_protocol);
2836         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2837                             vsi->offset_loaded, &oes->tx_bytes,
2838                             &nes->tx_bytes);
2839         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2840                             vsi->offset_loaded, &oes->tx_unicast,
2841                             &nes->tx_unicast);
2842         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2843                             vsi->offset_loaded, &oes->tx_multicast,
2844                             &nes->tx_multicast);
2845         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2846                             vsi->offset_loaded,  &oes->tx_broadcast,
2847                             &nes->tx_broadcast);
2848         /* GLV_TDPC not supported */
2849         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2850                             &oes->tx_errors, &nes->tx_errors);
2851         vsi->offset_loaded = true;
2852
2853         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2854                     vsi->vsi_id);
2855         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2856         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2857         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2858         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2859         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2860         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2861                     nes->rx_unknown_protocol);
2862         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2863         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2864         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2865         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2866         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2867         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2868         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2869                     vsi->vsi_id);
2870 }
2871
2872 static void
2873 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2874 {
2875         unsigned int i;
2876         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2877         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2878
2879         /* Get rx/tx bytes of internal transfer packets */
2880         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2881                         I40E_GLV_GORCL(hw->port),
2882                         pf->offset_loaded,
2883                         &pf->internal_stats_offset.rx_bytes,
2884                         &pf->internal_stats.rx_bytes);
2885
2886         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2887                         I40E_GLV_GOTCL(hw->port),
2888                         pf->offset_loaded,
2889                         &pf->internal_stats_offset.tx_bytes,
2890                         &pf->internal_stats.tx_bytes);
2891         /* Get total internal rx packet count */
2892         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2893                             I40E_GLV_UPRCL(hw->port),
2894                             pf->offset_loaded,
2895                             &pf->internal_stats_offset.rx_unicast,
2896                             &pf->internal_stats.rx_unicast);
2897         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2898                             I40E_GLV_MPRCL(hw->port),
2899                             pf->offset_loaded,
2900                             &pf->internal_stats_offset.rx_multicast,
2901                             &pf->internal_stats.rx_multicast);
2902         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2903                             I40E_GLV_BPRCL(hw->port),
2904                             pf->offset_loaded,
2905                             &pf->internal_stats_offset.rx_broadcast,
2906                             &pf->internal_stats.rx_broadcast);
2907         /* Get total internal tx packet count */
2908         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2909                             I40E_GLV_UPTCL(hw->port),
2910                             pf->offset_loaded,
2911                             &pf->internal_stats_offset.tx_unicast,
2912                             &pf->internal_stats.tx_unicast);
2913         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2914                             I40E_GLV_MPTCL(hw->port),
2915                             pf->offset_loaded,
2916                             &pf->internal_stats_offset.tx_multicast,
2917                             &pf->internal_stats.tx_multicast);
2918         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2919                             I40E_GLV_BPTCL(hw->port),
2920                             pf->offset_loaded,
2921                             &pf->internal_stats_offset.tx_broadcast,
2922                             &pf->internal_stats.tx_broadcast);
2923
2924         /* exclude CRC size */
2925         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2926                 pf->internal_stats.rx_multicast +
2927                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2928
2929         /* Get statistics of struct i40e_eth_stats */
2930         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2931                             I40E_GLPRT_GORCL(hw->port),
2932                             pf->offset_loaded, &os->eth.rx_bytes,
2933                             &ns->eth.rx_bytes);
2934         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2935                             I40E_GLPRT_UPRCL(hw->port),
2936                             pf->offset_loaded, &os->eth.rx_unicast,
2937                             &ns->eth.rx_unicast);
2938         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2939                             I40E_GLPRT_MPRCL(hw->port),
2940                             pf->offset_loaded, &os->eth.rx_multicast,
2941                             &ns->eth.rx_multicast);
2942         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2943                             I40E_GLPRT_BPRCL(hw->port),
2944                             pf->offset_loaded, &os->eth.rx_broadcast,
2945                             &ns->eth.rx_broadcast);
2946         /* Workaround: CRC size should not be included in byte statistics,
2947          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2948          */
2949         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2950                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2951
2952         /* exclude internal rx bytes
2953          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2954          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2955          * value.
2956          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2957          */
2958         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2959                 ns->eth.rx_bytes = 0;
2960         else
2961                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2962
2963         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2964                 ns->eth.rx_unicast = 0;
2965         else
2966                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2967
2968         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2969                 ns->eth.rx_multicast = 0;
2970         else
2971                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2972
2973         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2974                 ns->eth.rx_broadcast = 0;
2975         else
2976                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2977
2978         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2979                             pf->offset_loaded, &os->eth.rx_discards,
2980                             &ns->eth.rx_discards);
2981         /* GLPRT_REPC not supported */
2982         /* GLPRT_RMPC not supported */
2983         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2984                             pf->offset_loaded,
2985                             &os->eth.rx_unknown_protocol,
2986                             &ns->eth.rx_unknown_protocol);
2987         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2988                             I40E_GLPRT_GOTCL(hw->port),
2989                             pf->offset_loaded, &os->eth.tx_bytes,
2990                             &ns->eth.tx_bytes);
2991         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2992                             I40E_GLPRT_UPTCL(hw->port),
2993                             pf->offset_loaded, &os->eth.tx_unicast,
2994                             &ns->eth.tx_unicast);
2995         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2996                             I40E_GLPRT_MPTCL(hw->port),
2997                             pf->offset_loaded, &os->eth.tx_multicast,
2998                             &ns->eth.tx_multicast);
2999         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3000                             I40E_GLPRT_BPTCL(hw->port),
3001                             pf->offset_loaded, &os->eth.tx_broadcast,
3002                             &ns->eth.tx_broadcast);
3003         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3004                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
3005
3006         /* exclude internal tx bytes
3007          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3008          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3009          * value.
3010          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3011          */
3012         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3013                 ns->eth.tx_bytes = 0;
3014         else
3015                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3016
3017         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3018                 ns->eth.tx_unicast = 0;
3019         else
3020                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3021
3022         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3023                 ns->eth.tx_multicast = 0;
3024         else
3025                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3026
3027         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3028                 ns->eth.tx_broadcast = 0;
3029         else
3030                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3031
3032         /* GLPRT_TEPC not supported */
3033
3034         /* additional port specific stats */
3035         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3036                             pf->offset_loaded, &os->tx_dropped_link_down,
3037                             &ns->tx_dropped_link_down);
3038         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3039                             pf->offset_loaded, &os->crc_errors,
3040                             &ns->crc_errors);
3041         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3042                             pf->offset_loaded, &os->illegal_bytes,
3043                             &ns->illegal_bytes);
3044         /* GLPRT_ERRBC not supported */
3045         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3046                             pf->offset_loaded, &os->mac_local_faults,
3047                             &ns->mac_local_faults);
3048         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3049                             pf->offset_loaded, &os->mac_remote_faults,
3050                             &ns->mac_remote_faults);
3051         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3052                             pf->offset_loaded, &os->rx_length_errors,
3053                             &ns->rx_length_errors);
3054         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3055                             pf->offset_loaded, &os->link_xon_rx,
3056                             &ns->link_xon_rx);
3057         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3058                             pf->offset_loaded, &os->link_xoff_rx,
3059                             &ns->link_xoff_rx);
3060         for (i = 0; i < 8; i++) {
3061                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3062                                     pf->offset_loaded,
3063                                     &os->priority_xon_rx[i],
3064                                     &ns->priority_xon_rx[i]);
3065                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3066                                     pf->offset_loaded,
3067                                     &os->priority_xoff_rx[i],
3068                                     &ns->priority_xoff_rx[i]);
3069         }
3070         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3071                             pf->offset_loaded, &os->link_xon_tx,
3072                             &ns->link_xon_tx);
3073         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3074                             pf->offset_loaded, &os->link_xoff_tx,
3075                             &ns->link_xoff_tx);
3076         for (i = 0; i < 8; i++) {
3077                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3078                                     pf->offset_loaded,
3079                                     &os->priority_xon_tx[i],
3080                                     &ns->priority_xon_tx[i]);
3081                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3082                                     pf->offset_loaded,
3083                                     &os->priority_xoff_tx[i],
3084                                     &ns->priority_xoff_tx[i]);
3085                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3086                                     pf->offset_loaded,
3087                                     &os->priority_xon_2_xoff[i],
3088                                     &ns->priority_xon_2_xoff[i]);
3089         }
3090         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3091                             I40E_GLPRT_PRC64L(hw->port),
3092                             pf->offset_loaded, &os->rx_size_64,
3093                             &ns->rx_size_64);
3094         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3095                             I40E_GLPRT_PRC127L(hw->port),
3096                             pf->offset_loaded, &os->rx_size_127,
3097                             &ns->rx_size_127);
3098         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3099                             I40E_GLPRT_PRC255L(hw->port),
3100                             pf->offset_loaded, &os->rx_size_255,
3101                             &ns->rx_size_255);
3102         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3103                             I40E_GLPRT_PRC511L(hw->port),
3104                             pf->offset_loaded, &os->rx_size_511,
3105                             &ns->rx_size_511);
3106         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3107                             I40E_GLPRT_PRC1023L(hw->port),
3108                             pf->offset_loaded, &os->rx_size_1023,
3109                             &ns->rx_size_1023);
3110         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3111                             I40E_GLPRT_PRC1522L(hw->port),
3112                             pf->offset_loaded, &os->rx_size_1522,
3113                             &ns->rx_size_1522);
3114         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3115                             I40E_GLPRT_PRC9522L(hw->port),
3116                             pf->offset_loaded, &os->rx_size_big,
3117                             &ns->rx_size_big);
3118         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3119                             pf->offset_loaded, &os->rx_undersize,
3120                             &ns->rx_undersize);
3121         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3122                             pf->offset_loaded, &os->rx_fragments,
3123                             &ns->rx_fragments);
3124         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3125                             pf->offset_loaded, &os->rx_oversize,
3126                             &ns->rx_oversize);
3127         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3128                             pf->offset_loaded, &os->rx_jabber,
3129                             &ns->rx_jabber);
3130         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3131                             I40E_GLPRT_PTC64L(hw->port),
3132                             pf->offset_loaded, &os->tx_size_64,
3133                             &ns->tx_size_64);
3134         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3135                             I40E_GLPRT_PTC127L(hw->port),
3136                             pf->offset_loaded, &os->tx_size_127,
3137                             &ns->tx_size_127);
3138         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3139                             I40E_GLPRT_PTC255L(hw->port),
3140                             pf->offset_loaded, &os->tx_size_255,
3141                             &ns->tx_size_255);
3142         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3143                             I40E_GLPRT_PTC511L(hw->port),
3144                             pf->offset_loaded, &os->tx_size_511,
3145                             &ns->tx_size_511);
3146         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3147                             I40E_GLPRT_PTC1023L(hw->port),
3148                             pf->offset_loaded, &os->tx_size_1023,
3149                             &ns->tx_size_1023);
3150         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3151                             I40E_GLPRT_PTC1522L(hw->port),
3152                             pf->offset_loaded, &os->tx_size_1522,
3153                             &ns->tx_size_1522);
3154         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3155                             I40E_GLPRT_PTC9522L(hw->port),
3156                             pf->offset_loaded, &os->tx_size_big,
3157                             &ns->tx_size_big);
3158         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3159                            pf->offset_loaded,
3160                            &os->fd_sb_match, &ns->fd_sb_match);
3161         /* GLPRT_MSPDC not supported */
3162         /* GLPRT_XEC not supported */
3163
3164         pf->offset_loaded = true;
3165
3166         if (pf->main_vsi)
3167                 i40e_update_vsi_stats(pf->main_vsi);
3168 }
3169
3170 /* Get all statistics of a port */
3171 static int
3172 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3173 {
3174         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3175         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3176         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3177         struct i40e_vsi *vsi;
3178         unsigned i;
3179
3180         /* call read registers - updates values, now write them to struct */
3181         i40e_read_stats_registers(pf, hw);
3182
3183         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3184                         pf->main_vsi->eth_stats.rx_multicast +
3185                         pf->main_vsi->eth_stats.rx_broadcast -
3186                         pf->main_vsi->eth_stats.rx_discards;
3187         stats->opackets = ns->eth.tx_unicast +
3188                         ns->eth.tx_multicast +
3189                         ns->eth.tx_broadcast;
3190         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3191         stats->obytes   = ns->eth.tx_bytes;
3192         stats->oerrors  = ns->eth.tx_errors +
3193                         pf->main_vsi->eth_stats.tx_errors;
3194
3195         /* Rx Errors */
3196         stats->imissed  = ns->eth.rx_discards +
3197                         pf->main_vsi->eth_stats.rx_discards;
3198         stats->ierrors  = ns->crc_errors +
3199                         ns->rx_length_errors + ns->rx_undersize +
3200                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3201
3202         if (pf->vfs) {
3203                 for (i = 0; i < pf->vf_num; i++) {
3204                         vsi = pf->vfs[i].vsi;
3205                         i40e_update_vsi_stats(vsi);
3206
3207                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3208                                         vsi->eth_stats.rx_multicast +
3209                                         vsi->eth_stats.rx_broadcast -
3210                                         vsi->eth_stats.rx_discards);
3211                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3212                         stats->oerrors  += vsi->eth_stats.tx_errors;
3213                         stats->imissed  += vsi->eth_stats.rx_discards;
3214                 }
3215         }
3216
3217         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3218         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3219         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3220         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3221         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3222         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3223         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3224                     ns->eth.rx_unknown_protocol);
3225         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3226         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3227         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3228         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3229         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3230         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3231
3232         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3233                     ns->tx_dropped_link_down);
3234         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3235         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3236                     ns->illegal_bytes);
3237         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3238         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3239                     ns->mac_local_faults);
3240         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3241                     ns->mac_remote_faults);
3242         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3243                     ns->rx_length_errors);
3244         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3245         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3246         for (i = 0; i < 8; i++) {
3247                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3248                                 i, ns->priority_xon_rx[i]);
3249                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3250                                 i, ns->priority_xoff_rx[i]);
3251         }
3252         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3253         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3254         for (i = 0; i < 8; i++) {
3255                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3256                                 i, ns->priority_xon_tx[i]);
3257                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3258                                 i, ns->priority_xoff_tx[i]);
3259                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3260                                 i, ns->priority_xon_2_xoff[i]);
3261         }
3262         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3263         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3264         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3265         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3266         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3267         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3268         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3269         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3270         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3271         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3272         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3273         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3274         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3275         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3276         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3277         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3278         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3279         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3280         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3281                         ns->mac_short_packet_dropped);
3282         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3283                     ns->checksum_error);
3284         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3285         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3286         return 0;
3287 }
3288
3289 /* Reset the statistics */
3290 static void
3291 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3292 {
3293         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3294         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3295
3296         /* Mark PF and VSI stats to update the offset, aka "reset" */
3297         pf->offset_loaded = false;
3298         if (pf->main_vsi)
3299                 pf->main_vsi->offset_loaded = false;
3300
3301         /* read the stats, reading current register values into offset */
3302         i40e_read_stats_registers(pf, hw);
3303 }
3304
3305 static uint32_t
3306 i40e_xstats_calc_num(void)
3307 {
3308         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3309                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3310                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3311 }
3312
3313 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3314                                      struct rte_eth_xstat_name *xstats_names,
3315                                      __rte_unused unsigned limit)
3316 {
3317         unsigned count = 0;
3318         unsigned i, prio;
3319
3320         if (xstats_names == NULL)
3321                 return i40e_xstats_calc_num();
3322
3323         /* Note: limit checked in rte_eth_xstats_names() */
3324
3325         /* Get stats from i40e_eth_stats struct */
3326         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3327                 snprintf(xstats_names[count].name,
3328                          sizeof(xstats_names[count].name),
3329                          "%s", rte_i40e_stats_strings[i].name);
3330                 count++;
3331         }
3332
3333         /* Get individiual stats from i40e_hw_port struct */
3334         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3335                 snprintf(xstats_names[count].name,
3336                         sizeof(xstats_names[count].name),
3337                          "%s", rte_i40e_hw_port_strings[i].name);
3338                 count++;
3339         }
3340
3341         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3342                 for (prio = 0; prio < 8; prio++) {
3343                         snprintf(xstats_names[count].name,
3344                                  sizeof(xstats_names[count].name),
3345                                  "rx_priority%u_%s", prio,
3346                                  rte_i40e_rxq_prio_strings[i].name);
3347                         count++;
3348                 }
3349         }
3350
3351         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3352                 for (prio = 0; prio < 8; prio++) {
3353                         snprintf(xstats_names[count].name,
3354                                  sizeof(xstats_names[count].name),
3355                                  "tx_priority%u_%s", prio,
3356                                  rte_i40e_txq_prio_strings[i].name);
3357                         count++;
3358                 }
3359         }
3360         return count;
3361 }
3362
3363 static int
3364 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3365                     unsigned n)
3366 {
3367         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3368         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3369         unsigned i, count, prio;
3370         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3371
3372         count = i40e_xstats_calc_num();
3373         if (n < count)
3374                 return count;
3375
3376         i40e_read_stats_registers(pf, hw);
3377
3378         if (xstats == NULL)
3379                 return 0;
3380
3381         count = 0;
3382
3383         /* Get stats from i40e_eth_stats struct */
3384         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3385                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3386                         rte_i40e_stats_strings[i].offset);
3387                 xstats[count].id = count;
3388                 count++;
3389         }
3390
3391         /* Get individiual stats from i40e_hw_port struct */
3392         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3393                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3394                         rte_i40e_hw_port_strings[i].offset);
3395                 xstats[count].id = count;
3396                 count++;
3397         }
3398
3399         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3400                 for (prio = 0; prio < 8; prio++) {
3401                         xstats[count].value =
3402                                 *(uint64_t *)(((char *)hw_stats) +
3403                                 rte_i40e_rxq_prio_strings[i].offset +
3404                                 (sizeof(uint64_t) * prio));
3405                         xstats[count].id = count;
3406                         count++;
3407                 }
3408         }
3409
3410         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3411                 for (prio = 0; prio < 8; prio++) {
3412                         xstats[count].value =
3413                                 *(uint64_t *)(((char *)hw_stats) +
3414                                 rte_i40e_txq_prio_strings[i].offset +
3415                                 (sizeof(uint64_t) * prio));
3416                         xstats[count].id = count;
3417                         count++;
3418                 }
3419         }
3420
3421         return count;
3422 }
3423
3424 static int
3425 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3426                                  __rte_unused uint16_t queue_id,
3427                                  __rte_unused uint8_t stat_idx,
3428                                  __rte_unused uint8_t is_rx)
3429 {
3430         PMD_INIT_FUNC_TRACE();
3431
3432         return -ENOSYS;
3433 }
3434
3435 static int
3436 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3437 {
3438         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3439         u32 full_ver;
3440         u8 ver, patch;
3441         u16 build;
3442         int ret;
3443
3444         full_ver = hw->nvm.oem_ver;
3445         ver = (u8)(full_ver >> 24);
3446         build = (u16)((full_ver >> 8) & 0xffff);
3447         patch = (u8)(full_ver & 0xff);
3448
3449         ret = snprintf(fw_version, fw_size,
3450                  "%d.%d%d 0x%08x %d.%d.%d",
3451                  ((hw->nvm.version >> 12) & 0xf),
3452                  ((hw->nvm.version >> 4) & 0xff),
3453                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3454                  ver, build, patch);
3455
3456         ret += 1; /* add the size of '\0' */
3457         if (fw_size < (u32)ret)
3458                 return ret;
3459         else
3460                 return 0;
3461 }
3462
3463 static void
3464 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3465 {
3466         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3467         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3468         struct i40e_vsi *vsi = pf->main_vsi;
3469         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3470
3471         dev_info->max_rx_queues = vsi->nb_qps;
3472         dev_info->max_tx_queues = vsi->nb_qps;
3473         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3474         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3475         dev_info->max_mac_addrs = vsi->max_macaddrs;
3476         dev_info->max_vfs = pci_dev->max_vfs;
3477         dev_info->rx_queue_offload_capa = 0;
3478         dev_info->rx_offload_capa =
3479                 DEV_RX_OFFLOAD_VLAN_STRIP |
3480                 DEV_RX_OFFLOAD_QINQ_STRIP |
3481                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3482                 DEV_RX_OFFLOAD_UDP_CKSUM |
3483                 DEV_RX_OFFLOAD_TCP_CKSUM |
3484                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3485                 DEV_RX_OFFLOAD_KEEP_CRC |
3486                 DEV_RX_OFFLOAD_SCATTER |
3487                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3488                 DEV_RX_OFFLOAD_VLAN_FILTER |
3489                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3490
3491         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3492         dev_info->tx_offload_capa =
3493                 DEV_TX_OFFLOAD_VLAN_INSERT |
3494                 DEV_TX_OFFLOAD_QINQ_INSERT |
3495                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3496                 DEV_TX_OFFLOAD_UDP_CKSUM |
3497                 DEV_TX_OFFLOAD_TCP_CKSUM |
3498                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3499                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3500                 DEV_TX_OFFLOAD_TCP_TSO |
3501                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3502                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3503                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3504                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3505                 DEV_TX_OFFLOAD_MULTI_SEGS |
3506                 dev_info->tx_queue_offload_capa;
3507         dev_info->dev_capa =
3508                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3509                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3510
3511         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3512                                                 sizeof(uint32_t);
3513         dev_info->reta_size = pf->hash_lut_size;
3514         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3515
3516         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3517                 .rx_thresh = {
3518                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3519                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3520                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3521                 },
3522                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3523                 .rx_drop_en = 0,
3524                 .offloads = 0,
3525         };
3526
3527         dev_info->default_txconf = (struct rte_eth_txconf) {
3528                 .tx_thresh = {
3529                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3530                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3531                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3532                 },
3533                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3534                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3535                 .offloads = 0,
3536         };
3537
3538         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3539                 .nb_max = I40E_MAX_RING_DESC,
3540                 .nb_min = I40E_MIN_RING_DESC,
3541                 .nb_align = I40E_ALIGN_RING_DESC,
3542         };
3543
3544         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3545                 .nb_max = I40E_MAX_RING_DESC,
3546                 .nb_min = I40E_MIN_RING_DESC,
3547                 .nb_align = I40E_ALIGN_RING_DESC,
3548                 .nb_seg_max = I40E_TX_MAX_SEG,
3549                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3550         };
3551
3552         if (pf->flags & I40E_FLAG_VMDQ) {
3553                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3554                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3555                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3556                                                 pf->max_nb_vmdq_vsi;
3557                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3558                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3559                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3560         }
3561
3562         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3563                 /* For XL710 */
3564                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3565                 dev_info->default_rxportconf.nb_queues = 2;
3566                 dev_info->default_txportconf.nb_queues = 2;
3567                 if (dev->data->nb_rx_queues == 1)
3568                         dev_info->default_rxportconf.ring_size = 2048;
3569                 else
3570                         dev_info->default_rxportconf.ring_size = 1024;
3571                 if (dev->data->nb_tx_queues == 1)
3572                         dev_info->default_txportconf.ring_size = 1024;
3573                 else
3574                         dev_info->default_txportconf.ring_size = 512;
3575
3576         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3577                 /* For XXV710 */
3578                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3579                 dev_info->default_rxportconf.nb_queues = 1;
3580                 dev_info->default_txportconf.nb_queues = 1;
3581                 dev_info->default_rxportconf.ring_size = 256;
3582                 dev_info->default_txportconf.ring_size = 256;
3583         } else {
3584                 /* For X710 */
3585                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3586                 dev_info->default_rxportconf.nb_queues = 1;
3587                 dev_info->default_txportconf.nb_queues = 1;
3588                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3589                         dev_info->default_rxportconf.ring_size = 512;
3590                         dev_info->default_txportconf.ring_size = 256;
3591                 } else {
3592                         dev_info->default_rxportconf.ring_size = 256;
3593                         dev_info->default_txportconf.ring_size = 256;
3594                 }
3595         }
3596         dev_info->default_rxportconf.burst_size = 32;
3597         dev_info->default_txportconf.burst_size = 32;
3598 }
3599
3600 static int
3601 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3602 {
3603         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3604         struct i40e_vsi *vsi = pf->main_vsi;
3605         PMD_INIT_FUNC_TRACE();
3606
3607         if (on)
3608                 return i40e_vsi_add_vlan(vsi, vlan_id);
3609         else
3610                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3611 }
3612
3613 static int
3614 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3615                                 enum rte_vlan_type vlan_type,
3616                                 uint16_t tpid, int qinq)
3617 {
3618         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3619         uint64_t reg_r = 0;
3620         uint64_t reg_w = 0;
3621         uint16_t reg_id = 3;
3622         int ret;
3623
3624         if (qinq) {
3625                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3626                         reg_id = 2;
3627         }
3628
3629         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3630                                           &reg_r, NULL);
3631         if (ret != I40E_SUCCESS) {
3632                 PMD_DRV_LOG(ERR,
3633                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3634                            reg_id);
3635                 return -EIO;
3636         }
3637         PMD_DRV_LOG(DEBUG,
3638                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3639                     reg_id, reg_r);
3640
3641         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3642         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3643         if (reg_r == reg_w) {
3644                 PMD_DRV_LOG(DEBUG, "No need to write");
3645                 return 0;
3646         }
3647
3648         ret = i40e_aq_debug_write_global_register(hw,
3649                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3650                                            reg_w, NULL);
3651         if (ret != I40E_SUCCESS) {
3652                 PMD_DRV_LOG(ERR,
3653                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3654                             reg_id);
3655                 return -EIO;
3656         }
3657         PMD_DRV_LOG(DEBUG,
3658                     "Global register 0x%08x is changed with value 0x%08x",
3659                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3660
3661         return 0;
3662 }
3663
3664 static int
3665 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3666                    enum rte_vlan_type vlan_type,
3667                    uint16_t tpid)
3668 {
3669         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3670         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3671         int qinq = dev->data->dev_conf.rxmode.offloads &
3672                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3673         int ret = 0;
3674
3675         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3676              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3677             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3678                 PMD_DRV_LOG(ERR,
3679                             "Unsupported vlan type.");
3680                 return -EINVAL;
3681         }
3682
3683         if (pf->support_multi_driver) {
3684                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3685                 return -ENOTSUP;
3686         }
3687
3688         /* 802.1ad frames ability is added in NVM API 1.7*/
3689         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3690                 if (qinq) {
3691                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3692                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3693                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3694                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3695                 } else {
3696                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3697                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3698                 }
3699                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3700                 if (ret != I40E_SUCCESS) {
3701                         PMD_DRV_LOG(ERR,
3702                                     "Set switch config failed aq_err: %d",
3703                                     hw->aq.asq_last_status);
3704                         ret = -EIO;
3705                 }
3706         } else
3707                 /* If NVM API < 1.7, keep the register setting */
3708                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3709                                                       tpid, qinq);
3710
3711         return ret;
3712 }
3713
3714 static int
3715 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3716 {
3717         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3718         struct i40e_vsi *vsi = pf->main_vsi;
3719         struct rte_eth_rxmode *rxmode;
3720
3721         rxmode = &dev->data->dev_conf.rxmode;
3722         if (mask & ETH_VLAN_FILTER_MASK) {
3723                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3724                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3725                 else
3726                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3727         }
3728
3729         if (mask & ETH_VLAN_STRIP_MASK) {
3730                 /* Enable or disable VLAN stripping */
3731                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3732                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3733                 else
3734                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3735         }
3736
3737         if (mask & ETH_VLAN_EXTEND_MASK) {
3738                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3739                         i40e_vsi_config_double_vlan(vsi, TRUE);
3740                         /* Set global registers with default ethertype. */
3741                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3742                                            ETHER_TYPE_VLAN);
3743                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3744                                            ETHER_TYPE_VLAN);
3745                 }
3746                 else
3747                         i40e_vsi_config_double_vlan(vsi, FALSE);
3748         }
3749
3750         return 0;
3751 }
3752
3753 static void
3754 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3755                           __rte_unused uint16_t queue,
3756                           __rte_unused int on)
3757 {
3758         PMD_INIT_FUNC_TRACE();
3759 }
3760
3761 static int
3762 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3763 {
3764         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3765         struct i40e_vsi *vsi = pf->main_vsi;
3766         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3767         struct i40e_vsi_vlan_pvid_info info;
3768
3769         memset(&info, 0, sizeof(info));
3770         info.on = on;
3771         if (info.on)
3772                 info.config.pvid = pvid;
3773         else {
3774                 info.config.reject.tagged =
3775                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3776                 info.config.reject.untagged =
3777                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3778         }
3779
3780         return i40e_vsi_vlan_pvid_set(vsi, &info);
3781 }
3782
3783 static int
3784 i40e_dev_led_on(struct rte_eth_dev *dev)
3785 {
3786         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3787         uint32_t mode = i40e_led_get(hw);
3788
3789         if (mode == 0)
3790                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3791
3792         return 0;
3793 }
3794
3795 static int
3796 i40e_dev_led_off(struct rte_eth_dev *dev)
3797 {
3798         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3799         uint32_t mode = i40e_led_get(hw);
3800
3801         if (mode != 0)
3802                 i40e_led_set(hw, 0, false);
3803
3804         return 0;
3805 }
3806
3807 static int
3808 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3809 {
3810         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3811         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3812
3813         fc_conf->pause_time = pf->fc_conf.pause_time;
3814
3815         /* read out from register, in case they are modified by other port */
3816         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3817                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3818         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3819                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3820
3821         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3822         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3823
3824          /* Return current mode according to actual setting*/
3825         switch (hw->fc.current_mode) {
3826         case I40E_FC_FULL:
3827                 fc_conf->mode = RTE_FC_FULL;
3828                 break;
3829         case I40E_FC_TX_PAUSE:
3830                 fc_conf->mode = RTE_FC_TX_PAUSE;
3831                 break;
3832         case I40E_FC_RX_PAUSE:
3833                 fc_conf->mode = RTE_FC_RX_PAUSE;
3834                 break;
3835         case I40E_FC_NONE:
3836         default:
3837                 fc_conf->mode = RTE_FC_NONE;
3838         };
3839
3840         return 0;
3841 }
3842
3843 static int
3844 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3845 {
3846         uint32_t mflcn_reg, fctrl_reg, reg;
3847         uint32_t max_high_water;
3848         uint8_t i, aq_failure;
3849         int err;
3850         struct i40e_hw *hw;
3851         struct i40e_pf *pf;
3852         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3853                 [RTE_FC_NONE] = I40E_FC_NONE,
3854                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3855                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3856                 [RTE_FC_FULL] = I40E_FC_FULL
3857         };
3858
3859         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3860
3861         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3862         if ((fc_conf->high_water > max_high_water) ||
3863                         (fc_conf->high_water < fc_conf->low_water)) {
3864                 PMD_INIT_LOG(ERR,
3865                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3866                         max_high_water);
3867                 return -EINVAL;
3868         }
3869
3870         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3871         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3872         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3873
3874         pf->fc_conf.pause_time = fc_conf->pause_time;
3875         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3876         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3877
3878         PMD_INIT_FUNC_TRACE();
3879
3880         /* All the link flow control related enable/disable register
3881          * configuration is handle by the F/W
3882          */
3883         err = i40e_set_fc(hw, &aq_failure, true);
3884         if (err < 0)
3885                 return -ENOSYS;
3886
3887         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3888                 /* Configure flow control refresh threshold,
3889                  * the value for stat_tx_pause_refresh_timer[8]
3890                  * is used for global pause operation.
3891                  */
3892
3893                 I40E_WRITE_REG(hw,
3894                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3895                                pf->fc_conf.pause_time);
3896
3897                 /* configure the timer value included in transmitted pause
3898                  * frame,
3899                  * the value for stat_tx_pause_quanta[8] is used for global
3900                  * pause operation
3901                  */
3902                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3903                                pf->fc_conf.pause_time);
3904
3905                 fctrl_reg = I40E_READ_REG(hw,
3906                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3907
3908                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3909                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3910                 else
3911                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3912
3913                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3914                                fctrl_reg);
3915         } else {
3916                 /* Configure pause time (2 TCs per register) */
3917                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3918                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3919                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3920
3921                 /* Configure flow control refresh threshold value */
3922                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3923                                pf->fc_conf.pause_time / 2);
3924
3925                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3926
3927                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3928                  *depending on configuration
3929                  */
3930                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3931                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3932                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3933                 } else {
3934                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3935                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3936                 }
3937
3938                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3939         }
3940
3941         if (!pf->support_multi_driver) {
3942                 /* config water marker both based on the packets and bytes */
3943                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3944                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3945                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3946                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3947                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3948                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3949                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3950                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3951                                   << I40E_KILOSHIFT);
3952                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3953                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3954                                    << I40E_KILOSHIFT);
3955         } else {
3956                 PMD_DRV_LOG(ERR,
3957                             "Water marker configuration is not supported.");
3958         }
3959
3960         I40E_WRITE_FLUSH(hw);
3961
3962         return 0;
3963 }
3964
3965 static int
3966 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3967                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3968 {
3969         PMD_INIT_FUNC_TRACE();
3970
3971         return -ENOSYS;
3972 }
3973
3974 /* Add a MAC address, and update filters */
3975 static int
3976 i40e_macaddr_add(struct rte_eth_dev *dev,
3977                  struct ether_addr *mac_addr,
3978                  __rte_unused uint32_t index,
3979                  uint32_t pool)
3980 {
3981         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3982         struct i40e_mac_filter_info mac_filter;
3983         struct i40e_vsi *vsi;
3984         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3985         int ret;
3986
3987         /* If VMDQ not enabled or configured, return */
3988         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3989                           !pf->nb_cfg_vmdq_vsi)) {
3990                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3991                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3992                         pool);
3993                 return -ENOTSUP;
3994         }
3995
3996         if (pool > pf->nb_cfg_vmdq_vsi) {
3997                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3998                                 pool, pf->nb_cfg_vmdq_vsi);
3999                 return -EINVAL;
4000         }
4001
4002         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
4003         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4004                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4005         else
4006                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4007
4008         if (pool == 0)
4009                 vsi = pf->main_vsi;
4010         else
4011                 vsi = pf->vmdq[pool - 1].vsi;
4012
4013         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4014         if (ret != I40E_SUCCESS) {
4015                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4016                 return -ENODEV;
4017         }
4018         return 0;
4019 }
4020
4021 /* Remove a MAC address, and update filters */
4022 static void
4023 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4024 {
4025         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4026         struct i40e_vsi *vsi;
4027         struct rte_eth_dev_data *data = dev->data;
4028         struct ether_addr *macaddr;
4029         int ret;
4030         uint32_t i;
4031         uint64_t pool_sel;
4032
4033         macaddr = &(data->mac_addrs[index]);
4034
4035         pool_sel = dev->data->mac_pool_sel[index];
4036
4037         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4038                 if (pool_sel & (1ULL << i)) {
4039                         if (i == 0)
4040                                 vsi = pf->main_vsi;
4041                         else {
4042                                 /* No VMDQ pool enabled or configured */
4043                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4044                                         (i > pf->nb_cfg_vmdq_vsi)) {
4045                                         PMD_DRV_LOG(ERR,
4046                                                 "No VMDQ pool enabled/configured");
4047                                         return;
4048                                 }
4049                                 vsi = pf->vmdq[i - 1].vsi;
4050                         }
4051                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4052
4053                         if (ret) {
4054                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4055                                 return;
4056                         }
4057                 }
4058         }
4059 }
4060
4061 /* Set perfect match or hash match of MAC and VLAN for a VF */
4062 static int
4063 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4064                  struct rte_eth_mac_filter *filter,
4065                  bool add)
4066 {
4067         struct i40e_hw *hw;
4068         struct i40e_mac_filter_info mac_filter;
4069         struct ether_addr old_mac;
4070         struct ether_addr *new_mac;
4071         struct i40e_pf_vf *vf = NULL;
4072         uint16_t vf_id;
4073         int ret;
4074
4075         if (pf == NULL) {
4076                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4077                 return -EINVAL;
4078         }
4079         hw = I40E_PF_TO_HW(pf);
4080
4081         if (filter == NULL) {
4082                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4083                 return -EINVAL;
4084         }
4085
4086         new_mac = &filter->mac_addr;
4087
4088         if (is_zero_ether_addr(new_mac)) {
4089                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4090                 return -EINVAL;
4091         }
4092
4093         vf_id = filter->dst_id;
4094
4095         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4096                 PMD_DRV_LOG(ERR, "Invalid argument.");
4097                 return -EINVAL;
4098         }
4099         vf = &pf->vfs[vf_id];
4100
4101         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
4102                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4103                 return -EINVAL;
4104         }
4105
4106         if (add) {
4107                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
4108                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4109                                 ETHER_ADDR_LEN);
4110                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4111                                  ETHER_ADDR_LEN);
4112
4113                 mac_filter.filter_type = filter->filter_type;
4114                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4115                 if (ret != I40E_SUCCESS) {
4116                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4117                         return -1;
4118                 }
4119                 ether_addr_copy(new_mac, &pf->dev_addr);
4120         } else {
4121                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4122                                 ETHER_ADDR_LEN);
4123                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4124                 if (ret != I40E_SUCCESS) {
4125                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4126                         return -1;
4127                 }
4128
4129                 /* Clear device address as it has been removed */
4130                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
4131                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
4132         }
4133
4134         return 0;
4135 }
4136
4137 /* MAC filter handle */
4138 static int
4139 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4140                 void *arg)
4141 {
4142         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4143         struct rte_eth_mac_filter *filter;
4144         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4145         int ret = I40E_NOT_SUPPORTED;
4146
4147         filter = (struct rte_eth_mac_filter *)(arg);
4148
4149         switch (filter_op) {
4150         case RTE_ETH_FILTER_NOP:
4151                 ret = I40E_SUCCESS;
4152                 break;
4153         case RTE_ETH_FILTER_ADD:
4154                 i40e_pf_disable_irq0(hw);
4155                 if (filter->is_vf)
4156                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4157                 i40e_pf_enable_irq0(hw);
4158                 break;
4159         case RTE_ETH_FILTER_DELETE:
4160                 i40e_pf_disable_irq0(hw);
4161                 if (filter->is_vf)
4162                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4163                 i40e_pf_enable_irq0(hw);
4164                 break;
4165         default:
4166                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4167                 ret = I40E_ERR_PARAM;
4168                 break;
4169         }
4170
4171         return ret;
4172 }
4173
4174 static int
4175 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4176 {
4177         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4178         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4179         uint32_t reg;
4180         int ret;
4181
4182         if (!lut)
4183                 return -EINVAL;
4184
4185         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4186                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4187                                           vsi->type != I40E_VSI_SRIOV,
4188                                           lut, lut_size);
4189                 if (ret) {
4190                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4191                         return ret;
4192                 }
4193         } else {
4194                 uint32_t *lut_dw = (uint32_t *)lut;
4195                 uint16_t i, lut_size_dw = lut_size / 4;
4196
4197                 if (vsi->type == I40E_VSI_SRIOV) {
4198                         for (i = 0; i <= lut_size_dw; i++) {
4199                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4200                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4201                         }
4202                 } else {
4203                         for (i = 0; i < lut_size_dw; i++)
4204                                 lut_dw[i] = I40E_READ_REG(hw,
4205                                                           I40E_PFQF_HLUT(i));
4206                 }
4207         }
4208
4209         return 0;
4210 }
4211
4212 int
4213 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4214 {
4215         struct i40e_pf *pf;
4216         struct i40e_hw *hw;
4217         int ret;
4218
4219         if (!vsi || !lut)
4220                 return -EINVAL;
4221
4222         pf = I40E_VSI_TO_PF(vsi);
4223         hw = I40E_VSI_TO_HW(vsi);
4224
4225         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4226                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4227                                           vsi->type != I40E_VSI_SRIOV,
4228                                           lut, lut_size);
4229                 if (ret) {
4230                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4231                         return ret;
4232                 }
4233         } else {
4234                 uint32_t *lut_dw = (uint32_t *)lut;
4235                 uint16_t i, lut_size_dw = lut_size / 4;
4236
4237                 if (vsi->type == I40E_VSI_SRIOV) {
4238                         for (i = 0; i < lut_size_dw; i++)
4239                                 I40E_WRITE_REG(
4240                                         hw,
4241                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4242                                         lut_dw[i]);
4243                 } else {
4244                         for (i = 0; i < lut_size_dw; i++)
4245                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4246                                                lut_dw[i]);
4247                 }
4248                 I40E_WRITE_FLUSH(hw);
4249         }
4250
4251         return 0;
4252 }
4253
4254 static int
4255 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4256                          struct rte_eth_rss_reta_entry64 *reta_conf,
4257                          uint16_t reta_size)
4258 {
4259         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4260         uint16_t i, lut_size = pf->hash_lut_size;
4261         uint16_t idx, shift;
4262         uint8_t *lut;
4263         int ret;
4264
4265         if (reta_size != lut_size ||
4266                 reta_size > ETH_RSS_RETA_SIZE_512) {
4267                 PMD_DRV_LOG(ERR,
4268                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4269                         reta_size, lut_size);
4270                 return -EINVAL;
4271         }
4272
4273         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4274         if (!lut) {
4275                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4276                 return -ENOMEM;
4277         }
4278         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4279         if (ret)
4280                 goto out;
4281         for (i = 0; i < reta_size; i++) {
4282                 idx = i / RTE_RETA_GROUP_SIZE;
4283                 shift = i % RTE_RETA_GROUP_SIZE;
4284                 if (reta_conf[idx].mask & (1ULL << shift))
4285                         lut[i] = reta_conf[idx].reta[shift];
4286         }
4287         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4288
4289         pf->adapter->rss_reta_updated = 1;
4290
4291 out:
4292         rte_free(lut);
4293
4294         return ret;
4295 }
4296
4297 static int
4298 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4299                         struct rte_eth_rss_reta_entry64 *reta_conf,
4300                         uint16_t reta_size)
4301 {
4302         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4303         uint16_t i, lut_size = pf->hash_lut_size;
4304         uint16_t idx, shift;
4305         uint8_t *lut;
4306         int ret;
4307
4308         if (reta_size != lut_size ||
4309                 reta_size > ETH_RSS_RETA_SIZE_512) {
4310                 PMD_DRV_LOG(ERR,
4311                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4312                         reta_size, lut_size);
4313                 return -EINVAL;
4314         }
4315
4316         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4317         if (!lut) {
4318                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4319                 return -ENOMEM;
4320         }
4321
4322         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4323         if (ret)
4324                 goto out;
4325         for (i = 0; i < reta_size; i++) {
4326                 idx = i / RTE_RETA_GROUP_SIZE;
4327                 shift = i % RTE_RETA_GROUP_SIZE;
4328                 if (reta_conf[idx].mask & (1ULL << shift))
4329                         reta_conf[idx].reta[shift] = lut[i];
4330         }
4331
4332 out:
4333         rte_free(lut);
4334
4335         return ret;
4336 }
4337
4338 /**
4339  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4340  * @hw:   pointer to the HW structure
4341  * @mem:  pointer to mem struct to fill out
4342  * @size: size of memory requested
4343  * @alignment: what to align the allocation to
4344  **/
4345 enum i40e_status_code
4346 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4347                         struct i40e_dma_mem *mem,
4348                         u64 size,
4349                         u32 alignment)
4350 {
4351         const struct rte_memzone *mz = NULL;
4352         char z_name[RTE_MEMZONE_NAMESIZE];
4353
4354         if (!mem)
4355                 return I40E_ERR_PARAM;
4356
4357         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4358         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4359                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4360         if (!mz)
4361                 return I40E_ERR_NO_MEMORY;
4362
4363         mem->size = size;
4364         mem->va = mz->addr;
4365         mem->pa = mz->iova;
4366         mem->zone = (const void *)mz;
4367         PMD_DRV_LOG(DEBUG,
4368                 "memzone %s allocated with physical address: %"PRIu64,
4369                 mz->name, mem->pa);
4370
4371         return I40E_SUCCESS;
4372 }
4373
4374 /**
4375  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4376  * @hw:   pointer to the HW structure
4377  * @mem:  ptr to mem struct to free
4378  **/
4379 enum i40e_status_code
4380 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4381                     struct i40e_dma_mem *mem)
4382 {
4383         if (!mem)
4384                 return I40E_ERR_PARAM;
4385
4386         PMD_DRV_LOG(DEBUG,
4387                 "memzone %s to be freed with physical address: %"PRIu64,
4388                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4389         rte_memzone_free((const struct rte_memzone *)mem->zone);
4390         mem->zone = NULL;
4391         mem->va = NULL;
4392         mem->pa = (u64)0;
4393
4394         return I40E_SUCCESS;
4395 }
4396
4397 /**
4398  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4399  * @hw:   pointer to the HW structure
4400  * @mem:  pointer to mem struct to fill out
4401  * @size: size of memory requested
4402  **/
4403 enum i40e_status_code
4404 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4405                          struct i40e_virt_mem *mem,
4406                          u32 size)
4407 {
4408         if (!mem)
4409                 return I40E_ERR_PARAM;
4410
4411         mem->size = size;
4412         mem->va = rte_zmalloc("i40e", size, 0);
4413
4414         if (mem->va)
4415                 return I40E_SUCCESS;
4416         else
4417                 return I40E_ERR_NO_MEMORY;
4418 }
4419
4420 /**
4421  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4422  * @hw:   pointer to the HW structure
4423  * @mem:  pointer to mem struct to free
4424  **/
4425 enum i40e_status_code
4426 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4427                      struct i40e_virt_mem *mem)
4428 {
4429         if (!mem)
4430                 return I40E_ERR_PARAM;
4431
4432         rte_free(mem->va);
4433         mem->va = NULL;
4434
4435         return I40E_SUCCESS;
4436 }
4437
4438 void
4439 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4440 {
4441         rte_spinlock_init(&sp->spinlock);
4442 }
4443
4444 void
4445 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4446 {
4447         rte_spinlock_lock(&sp->spinlock);
4448 }
4449
4450 void
4451 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4452 {
4453         rte_spinlock_unlock(&sp->spinlock);
4454 }
4455
4456 void
4457 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4458 {
4459         return;
4460 }
4461
4462 /**
4463  * Get the hardware capabilities, which will be parsed
4464  * and saved into struct i40e_hw.
4465  */
4466 static int
4467 i40e_get_cap(struct i40e_hw *hw)
4468 {
4469         struct i40e_aqc_list_capabilities_element_resp *buf;
4470         uint16_t len, size = 0;
4471         int ret;
4472
4473         /* Calculate a huge enough buff for saving response data temporarily */
4474         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4475                                                 I40E_MAX_CAP_ELE_NUM;
4476         buf = rte_zmalloc("i40e", len, 0);
4477         if (!buf) {
4478                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4479                 return I40E_ERR_NO_MEMORY;
4480         }
4481
4482         /* Get, parse the capabilities and save it to hw */
4483         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4484                         i40e_aqc_opc_list_func_capabilities, NULL);
4485         if (ret != I40E_SUCCESS)
4486                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4487
4488         /* Free the temporary buffer after being used */
4489         rte_free(buf);
4490
4491         return ret;
4492 }
4493
4494 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4495
4496 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4497                 const char *value,
4498                 void *opaque)
4499 {
4500         struct i40e_pf *pf;
4501         unsigned long num;
4502         char *end;
4503
4504         pf = (struct i40e_pf *)opaque;
4505         RTE_SET_USED(key);
4506
4507         errno = 0;
4508         num = strtoul(value, &end, 0);
4509         if (errno != 0 || end == value || *end != 0) {
4510                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4511                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4512                 return -(EINVAL);
4513         }
4514
4515         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4516                 pf->vf_nb_qp_max = (uint16_t)num;
4517         else
4518                 /* here return 0 to make next valid same argument work */
4519                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4520                             "power of 2 and equal or less than 16 !, Now it is "
4521                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4522
4523         return 0;
4524 }
4525
4526 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4527 {
4528         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4529         struct rte_kvargs *kvlist;
4530         int kvargs_count;
4531
4532         /* set default queue number per VF as 4 */
4533         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4534
4535         if (dev->device->devargs == NULL)
4536                 return 0;
4537
4538         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4539         if (kvlist == NULL)
4540                 return -(EINVAL);
4541
4542         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4543         if (!kvargs_count) {
4544                 rte_kvargs_free(kvlist);
4545                 return 0;
4546         }
4547
4548         if (kvargs_count > 1)
4549                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4550                             "the first invalid or last valid one is used !",
4551                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4552
4553         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4554                            i40e_pf_parse_vf_queue_number_handler, pf);
4555
4556         rte_kvargs_free(kvlist);
4557
4558         return 0;
4559 }
4560
4561 static int
4562 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4563 {
4564         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4565         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4566         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4567         uint16_t qp_count = 0, vsi_count = 0;
4568
4569         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4570                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4571                 return -EINVAL;
4572         }
4573
4574         i40e_pf_config_vf_rxq_number(dev);
4575
4576         /* Add the parameter init for LFC */
4577         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4578         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4579         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4580
4581         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4582         pf->max_num_vsi = hw->func_caps.num_vsis;
4583         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4584         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4585
4586         /* FDir queue/VSI allocation */
4587         pf->fdir_qp_offset = 0;
4588         if (hw->func_caps.fd) {
4589                 pf->flags |= I40E_FLAG_FDIR;
4590                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4591         } else {
4592                 pf->fdir_nb_qps = 0;
4593         }
4594         qp_count += pf->fdir_nb_qps;
4595         vsi_count += 1;
4596
4597         /* LAN queue/VSI allocation */
4598         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4599         if (!hw->func_caps.rss) {
4600                 pf->lan_nb_qps = 1;
4601         } else {
4602                 pf->flags |= I40E_FLAG_RSS;
4603                 if (hw->mac.type == I40E_MAC_X722)
4604                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4605                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4606         }
4607         qp_count += pf->lan_nb_qps;
4608         vsi_count += 1;
4609
4610         /* VF queue/VSI allocation */
4611         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4612         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4613                 pf->flags |= I40E_FLAG_SRIOV;
4614                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4615                 pf->vf_num = pci_dev->max_vfs;
4616                 PMD_DRV_LOG(DEBUG,
4617                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4618                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4619         } else {
4620                 pf->vf_nb_qps = 0;
4621                 pf->vf_num = 0;
4622         }
4623         qp_count += pf->vf_nb_qps * pf->vf_num;
4624         vsi_count += pf->vf_num;
4625
4626         /* VMDq queue/VSI allocation */
4627         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4628         pf->vmdq_nb_qps = 0;
4629         pf->max_nb_vmdq_vsi = 0;
4630         if (hw->func_caps.vmdq) {
4631                 if (qp_count < hw->func_caps.num_tx_qp &&
4632                         vsi_count < hw->func_caps.num_vsis) {
4633                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4634                                 qp_count) / pf->vmdq_nb_qp_max;
4635
4636                         /* Limit the maximum number of VMDq vsi to the maximum
4637                          * ethdev can support
4638                          */
4639                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4640                                 hw->func_caps.num_vsis - vsi_count);
4641                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4642                                 ETH_64_POOLS);
4643                         if (pf->max_nb_vmdq_vsi) {
4644                                 pf->flags |= I40E_FLAG_VMDQ;
4645                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4646                                 PMD_DRV_LOG(DEBUG,
4647                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4648                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4649                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4650                         } else {
4651                                 PMD_DRV_LOG(INFO,
4652                                         "No enough queues left for VMDq");
4653                         }
4654                 } else {
4655                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4656                 }
4657         }
4658         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4659         vsi_count += pf->max_nb_vmdq_vsi;
4660
4661         if (hw->func_caps.dcb)
4662                 pf->flags |= I40E_FLAG_DCB;
4663
4664         if (qp_count > hw->func_caps.num_tx_qp) {
4665                 PMD_DRV_LOG(ERR,
4666                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4667                         qp_count, hw->func_caps.num_tx_qp);
4668                 return -EINVAL;
4669         }
4670         if (vsi_count > hw->func_caps.num_vsis) {
4671                 PMD_DRV_LOG(ERR,
4672                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4673                         vsi_count, hw->func_caps.num_vsis);
4674                 return -EINVAL;
4675         }
4676
4677         return 0;
4678 }
4679
4680 static int
4681 i40e_pf_get_switch_config(struct i40e_pf *pf)
4682 {
4683         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4684         struct i40e_aqc_get_switch_config_resp *switch_config;
4685         struct i40e_aqc_switch_config_element_resp *element;
4686         uint16_t start_seid = 0, num_reported;
4687         int ret;
4688
4689         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4690                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4691         if (!switch_config) {
4692                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4693                 return -ENOMEM;
4694         }
4695
4696         /* Get the switch configurations */
4697         ret = i40e_aq_get_switch_config(hw, switch_config,
4698                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4699         if (ret != I40E_SUCCESS) {
4700                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4701                 goto fail;
4702         }
4703         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4704         if (num_reported != 1) { /* The number should be 1 */
4705                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4706                 goto fail;
4707         }
4708
4709         /* Parse the switch configuration elements */
4710         element = &(switch_config->element[0]);
4711         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4712                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4713                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4714         } else
4715                 PMD_DRV_LOG(INFO, "Unknown element type");
4716
4717 fail:
4718         rte_free(switch_config);
4719
4720         return ret;
4721 }
4722
4723 static int
4724 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4725                         uint32_t num)
4726 {
4727         struct pool_entry *entry;
4728
4729         if (pool == NULL || num == 0)
4730                 return -EINVAL;
4731
4732         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4733         if (entry == NULL) {
4734                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4735                 return -ENOMEM;
4736         }
4737
4738         /* queue heap initialize */
4739         pool->num_free = num;
4740         pool->num_alloc = 0;
4741         pool->base = base;
4742         LIST_INIT(&pool->alloc_list);
4743         LIST_INIT(&pool->free_list);
4744
4745         /* Initialize element  */
4746         entry->base = 0;
4747         entry->len = num;
4748
4749         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4750         return 0;
4751 }
4752
4753 static void
4754 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4755 {
4756         struct pool_entry *entry, *next_entry;
4757
4758         if (pool == NULL)
4759                 return;
4760
4761         for (entry = LIST_FIRST(&pool->alloc_list);
4762                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4763                         entry = next_entry) {
4764                 LIST_REMOVE(entry, next);
4765                 rte_free(entry);
4766         }
4767
4768         for (entry = LIST_FIRST(&pool->free_list);
4769                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4770                         entry = next_entry) {
4771                 LIST_REMOVE(entry, next);
4772                 rte_free(entry);
4773         }
4774
4775         pool->num_free = 0;
4776         pool->num_alloc = 0;
4777         pool->base = 0;
4778         LIST_INIT(&pool->alloc_list);
4779         LIST_INIT(&pool->free_list);
4780 }
4781
4782 static int
4783 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4784                        uint32_t base)
4785 {
4786         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4787         uint32_t pool_offset;
4788         int insert;
4789
4790         if (pool == NULL) {
4791                 PMD_DRV_LOG(ERR, "Invalid parameter");
4792                 return -EINVAL;
4793         }
4794
4795         pool_offset = base - pool->base;
4796         /* Lookup in alloc list */
4797         LIST_FOREACH(entry, &pool->alloc_list, next) {
4798                 if (entry->base == pool_offset) {
4799                         valid_entry = entry;
4800                         LIST_REMOVE(entry, next);
4801                         break;
4802                 }
4803         }
4804
4805         /* Not find, return */
4806         if (valid_entry == NULL) {
4807                 PMD_DRV_LOG(ERR, "Failed to find entry");
4808                 return -EINVAL;
4809         }
4810
4811         /**
4812          * Found it, move it to free list  and try to merge.
4813          * In order to make merge easier, always sort it by qbase.
4814          * Find adjacent prev and last entries.
4815          */
4816         prev = next = NULL;
4817         LIST_FOREACH(entry, &pool->free_list, next) {
4818                 if (entry->base > valid_entry->base) {
4819                         next = entry;
4820                         break;
4821                 }
4822                 prev = entry;
4823         }
4824
4825         insert = 0;
4826         /* Try to merge with next one*/
4827         if (next != NULL) {
4828                 /* Merge with next one */
4829                 if (valid_entry->base + valid_entry->len == next->base) {
4830                         next->base = valid_entry->base;
4831                         next->len += valid_entry->len;
4832                         rte_free(valid_entry);
4833                         valid_entry = next;
4834                         insert = 1;
4835                 }
4836         }
4837
4838         if (prev != NULL) {
4839                 /* Merge with previous one */
4840                 if (prev->base + prev->len == valid_entry->base) {
4841                         prev->len += valid_entry->len;
4842                         /* If it merge with next one, remove next node */
4843                         if (insert == 1) {
4844                                 LIST_REMOVE(valid_entry, next);
4845                                 rte_free(valid_entry);
4846                         } else {
4847                                 rte_free(valid_entry);
4848                                 insert = 1;
4849                         }
4850                 }
4851         }
4852
4853         /* Not find any entry to merge, insert */
4854         if (insert == 0) {
4855                 if (prev != NULL)
4856                         LIST_INSERT_AFTER(prev, valid_entry, next);
4857                 else if (next != NULL)
4858                         LIST_INSERT_BEFORE(next, valid_entry, next);
4859                 else /* It's empty list, insert to head */
4860                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4861         }
4862
4863         pool->num_free += valid_entry->len;
4864         pool->num_alloc -= valid_entry->len;
4865
4866         return 0;
4867 }
4868
4869 static int
4870 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4871                        uint16_t num)
4872 {
4873         struct pool_entry *entry, *valid_entry;
4874
4875         if (pool == NULL || num == 0) {
4876                 PMD_DRV_LOG(ERR, "Invalid parameter");
4877                 return -EINVAL;
4878         }
4879
4880         if (pool->num_free < num) {
4881                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4882                             num, pool->num_free);
4883                 return -ENOMEM;
4884         }
4885
4886         valid_entry = NULL;
4887         /* Lookup  in free list and find most fit one */
4888         LIST_FOREACH(entry, &pool->free_list, next) {
4889                 if (entry->len >= num) {
4890                         /* Find best one */
4891                         if (entry->len == num) {
4892                                 valid_entry = entry;
4893                                 break;
4894                         }
4895                         if (valid_entry == NULL || valid_entry->len > entry->len)
4896                                 valid_entry = entry;
4897                 }
4898         }
4899
4900         /* Not find one to satisfy the request, return */
4901         if (valid_entry == NULL) {
4902                 PMD_DRV_LOG(ERR, "No valid entry found");
4903                 return -ENOMEM;
4904         }
4905         /**
4906          * The entry have equal queue number as requested,
4907          * remove it from alloc_list.
4908          */
4909         if (valid_entry->len == num) {
4910                 LIST_REMOVE(valid_entry, next);
4911         } else {
4912                 /**
4913                  * The entry have more numbers than requested,
4914                  * create a new entry for alloc_list and minus its
4915                  * queue base and number in free_list.
4916                  */
4917                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4918                 if (entry == NULL) {
4919                         PMD_DRV_LOG(ERR,
4920                                 "Failed to allocate memory for resource pool");
4921                         return -ENOMEM;
4922                 }
4923                 entry->base = valid_entry->base;
4924                 entry->len = num;
4925                 valid_entry->base += num;
4926                 valid_entry->len -= num;
4927                 valid_entry = entry;
4928         }
4929
4930         /* Insert it into alloc list, not sorted */
4931         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4932
4933         pool->num_free -= valid_entry->len;
4934         pool->num_alloc += valid_entry->len;
4935
4936         return valid_entry->base + pool->base;
4937 }
4938
4939 /**
4940  * bitmap_is_subset - Check whether src2 is subset of src1
4941  **/
4942 static inline int
4943 bitmap_is_subset(uint8_t src1, uint8_t src2)
4944 {
4945         return !((src1 ^ src2) & src2);
4946 }
4947
4948 static enum i40e_status_code
4949 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4950 {
4951         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4952
4953         /* If DCB is not supported, only default TC is supported */
4954         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4955                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4956                 return I40E_NOT_SUPPORTED;
4957         }
4958
4959         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4960                 PMD_DRV_LOG(ERR,
4961                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4962                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4963                 return I40E_NOT_SUPPORTED;
4964         }
4965         return I40E_SUCCESS;
4966 }
4967
4968 int
4969 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4970                                 struct i40e_vsi_vlan_pvid_info *info)
4971 {
4972         struct i40e_hw *hw;
4973         struct i40e_vsi_context ctxt;
4974         uint8_t vlan_flags = 0;
4975         int ret;
4976
4977         if (vsi == NULL || info == NULL) {
4978                 PMD_DRV_LOG(ERR, "invalid parameters");
4979                 return I40E_ERR_PARAM;
4980         }
4981
4982         if (info->on) {
4983                 vsi->info.pvid = info->config.pvid;
4984                 /**
4985                  * If insert pvid is enabled, only tagged pkts are
4986                  * allowed to be sent out.
4987                  */
4988                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4989                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4990         } else {
4991                 vsi->info.pvid = 0;
4992                 if (info->config.reject.tagged == 0)
4993                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4994
4995                 if (info->config.reject.untagged == 0)
4996                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4997         }
4998         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4999                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5000         vsi->info.port_vlan_flags |= vlan_flags;
5001         vsi->info.valid_sections =
5002                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5003         memset(&ctxt, 0, sizeof(ctxt));
5004         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5005         ctxt.seid = vsi->seid;
5006
5007         hw = I40E_VSI_TO_HW(vsi);
5008         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5009         if (ret != I40E_SUCCESS)
5010                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5011
5012         return ret;
5013 }
5014
5015 static int
5016 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5017 {
5018         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5019         int i, ret;
5020         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5021
5022         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5023         if (ret != I40E_SUCCESS)
5024                 return ret;
5025
5026         if (!vsi->seid) {
5027                 PMD_DRV_LOG(ERR, "seid not valid");
5028                 return -EINVAL;
5029         }
5030
5031         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5032         tc_bw_data.tc_valid_bits = enabled_tcmap;
5033         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5034                 tc_bw_data.tc_bw_credits[i] =
5035                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5036
5037         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5038         if (ret != I40E_SUCCESS) {
5039                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5040                 return ret;
5041         }
5042
5043         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5044                                         sizeof(vsi->info.qs_handle));
5045         return I40E_SUCCESS;
5046 }
5047
5048 static enum i40e_status_code
5049 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5050                                  struct i40e_aqc_vsi_properties_data *info,
5051                                  uint8_t enabled_tcmap)
5052 {
5053         enum i40e_status_code ret;
5054         int i, total_tc = 0;
5055         uint16_t qpnum_per_tc, bsf, qp_idx;
5056
5057         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5058         if (ret != I40E_SUCCESS)
5059                 return ret;
5060
5061         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5062                 if (enabled_tcmap & (1 << i))
5063                         total_tc++;
5064         if (total_tc == 0)
5065                 total_tc = 1;
5066         vsi->enabled_tc = enabled_tcmap;
5067
5068         /* Number of queues per enabled TC */
5069         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5070         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5071         bsf = rte_bsf32(qpnum_per_tc);
5072
5073         /* Adjust the queue number to actual queues that can be applied */
5074         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5075                 vsi->nb_qps = qpnum_per_tc * total_tc;
5076
5077         /**
5078          * Configure TC and queue mapping parameters, for enabled TC,
5079          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5080          * default queue will serve it.
5081          */
5082         qp_idx = 0;
5083         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5084                 if (vsi->enabled_tc & (1 << i)) {
5085                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5086                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5087                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5088                         qp_idx += qpnum_per_tc;
5089                 } else
5090                         info->tc_mapping[i] = 0;
5091         }
5092
5093         /* Associate queue number with VSI */
5094         if (vsi->type == I40E_VSI_SRIOV) {
5095                 info->mapping_flags |=
5096                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5097                 for (i = 0; i < vsi->nb_qps; i++)
5098                         info->queue_mapping[i] =
5099                                 rte_cpu_to_le_16(vsi->base_queue + i);
5100         } else {
5101                 info->mapping_flags |=
5102                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5103                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5104         }
5105         info->valid_sections |=
5106                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5107
5108         return I40E_SUCCESS;
5109 }
5110
5111 static int
5112 i40e_veb_release(struct i40e_veb *veb)
5113 {
5114         struct i40e_vsi *vsi;
5115         struct i40e_hw *hw;
5116
5117         if (veb == NULL)
5118                 return -EINVAL;
5119
5120         if (!TAILQ_EMPTY(&veb->head)) {
5121                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5122                 return -EACCES;
5123         }
5124         /* associate_vsi field is NULL for floating VEB */
5125         if (veb->associate_vsi != NULL) {
5126                 vsi = veb->associate_vsi;
5127                 hw = I40E_VSI_TO_HW(vsi);
5128
5129                 vsi->uplink_seid = veb->uplink_seid;
5130                 vsi->veb = NULL;
5131         } else {
5132                 veb->associate_pf->main_vsi->floating_veb = NULL;
5133                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5134         }
5135
5136         i40e_aq_delete_element(hw, veb->seid, NULL);
5137         rte_free(veb);
5138         return I40E_SUCCESS;
5139 }
5140
5141 /* Setup a veb */
5142 static struct i40e_veb *
5143 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5144 {
5145         struct i40e_veb *veb;
5146         int ret;
5147         struct i40e_hw *hw;
5148
5149         if (pf == NULL) {
5150                 PMD_DRV_LOG(ERR,
5151                             "veb setup failed, associated PF shouldn't null");
5152                 return NULL;
5153         }
5154         hw = I40E_PF_TO_HW(pf);
5155
5156         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5157         if (!veb) {
5158                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5159                 goto fail;
5160         }
5161
5162         veb->associate_vsi = vsi;
5163         veb->associate_pf = pf;
5164         TAILQ_INIT(&veb->head);
5165         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5166
5167         /* create floating veb if vsi is NULL */
5168         if (vsi != NULL) {
5169                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5170                                       I40E_DEFAULT_TCMAP, false,
5171                                       &veb->seid, false, NULL);
5172         } else {
5173                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5174                                       true, &veb->seid, false, NULL);
5175         }
5176
5177         if (ret != I40E_SUCCESS) {
5178                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5179                             hw->aq.asq_last_status);
5180                 goto fail;
5181         }
5182         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5183
5184         /* get statistics index */
5185         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5186                                 &veb->stats_idx, NULL, NULL, NULL);
5187         if (ret != I40E_SUCCESS) {
5188                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5189                             hw->aq.asq_last_status);
5190                 goto fail;
5191         }
5192         /* Get VEB bandwidth, to be implemented */
5193         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5194         if (vsi)
5195                 vsi->uplink_seid = veb->seid;
5196
5197         return veb;
5198 fail:
5199         rte_free(veb);
5200         return NULL;
5201 }
5202
5203 int
5204 i40e_vsi_release(struct i40e_vsi *vsi)
5205 {
5206         struct i40e_pf *pf;
5207         struct i40e_hw *hw;
5208         struct i40e_vsi_list *vsi_list;
5209         void *temp;
5210         int ret;
5211         struct i40e_mac_filter *f;
5212         uint16_t user_param;
5213
5214         if (!vsi)
5215                 return I40E_SUCCESS;
5216
5217         if (!vsi->adapter)
5218                 return -EFAULT;
5219
5220         user_param = vsi->user_param;
5221
5222         pf = I40E_VSI_TO_PF(vsi);
5223         hw = I40E_VSI_TO_HW(vsi);
5224
5225         /* VSI has child to attach, release child first */
5226         if (vsi->veb) {
5227                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5228                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5229                                 return -1;
5230                 }
5231                 i40e_veb_release(vsi->veb);
5232         }
5233
5234         if (vsi->floating_veb) {
5235                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5236                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5237                                 return -1;
5238                 }
5239         }
5240
5241         /* Remove all macvlan filters of the VSI */
5242         i40e_vsi_remove_all_macvlan_filter(vsi);
5243         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5244                 rte_free(f);
5245
5246         if (vsi->type != I40E_VSI_MAIN &&
5247             ((vsi->type != I40E_VSI_SRIOV) ||
5248             !pf->floating_veb_list[user_param])) {
5249                 /* Remove vsi from parent's sibling list */
5250                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5251                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5252                         return I40E_ERR_PARAM;
5253                 }
5254                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5255                                 &vsi->sib_vsi_list, list);
5256
5257                 /* Remove all switch element of the VSI */
5258                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5259                 if (ret != I40E_SUCCESS)
5260                         PMD_DRV_LOG(ERR, "Failed to delete element");
5261         }
5262
5263         if ((vsi->type == I40E_VSI_SRIOV) &&
5264             pf->floating_veb_list[user_param]) {
5265                 /* Remove vsi from parent's sibling list */
5266                 if (vsi->parent_vsi == NULL ||
5267                     vsi->parent_vsi->floating_veb == NULL) {
5268                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5269                         return I40E_ERR_PARAM;
5270                 }
5271                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5272                              &vsi->sib_vsi_list, list);
5273
5274                 /* Remove all switch element of the VSI */
5275                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5276                 if (ret != I40E_SUCCESS)
5277                         PMD_DRV_LOG(ERR, "Failed to delete element");
5278         }
5279
5280         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5281
5282         if (vsi->type != I40E_VSI_SRIOV)
5283                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5284         rte_free(vsi);
5285
5286         return I40E_SUCCESS;
5287 }
5288
5289 static int
5290 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5291 {
5292         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5293         struct i40e_aqc_remove_macvlan_element_data def_filter;
5294         struct i40e_mac_filter_info filter;
5295         int ret;
5296
5297         if (vsi->type != I40E_VSI_MAIN)
5298                 return I40E_ERR_CONFIG;
5299         memset(&def_filter, 0, sizeof(def_filter));
5300         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5301                                         ETH_ADDR_LEN);
5302         def_filter.vlan_tag = 0;
5303         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5304                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5305         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5306         if (ret != I40E_SUCCESS) {
5307                 struct i40e_mac_filter *f;
5308                 struct ether_addr *mac;
5309
5310                 PMD_DRV_LOG(DEBUG,
5311                             "Cannot remove the default macvlan filter");
5312                 /* It needs to add the permanent mac into mac list */
5313                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5314                 if (f == NULL) {
5315                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5316                         return I40E_ERR_NO_MEMORY;
5317                 }
5318                 mac = &f->mac_info.mac_addr;
5319                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5320                                 ETH_ADDR_LEN);
5321                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5322                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5323                 vsi->mac_num++;
5324
5325                 return ret;
5326         }
5327         rte_memcpy(&filter.mac_addr,
5328                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5329         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5330         return i40e_vsi_add_mac(vsi, &filter);
5331 }
5332
5333 /*
5334  * i40e_vsi_get_bw_config - Query VSI BW Information
5335  * @vsi: the VSI to be queried
5336  *
5337  * Returns 0 on success, negative value on failure
5338  */
5339 static enum i40e_status_code
5340 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5341 {
5342         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5343         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5344         struct i40e_hw *hw = &vsi->adapter->hw;
5345         i40e_status ret;
5346         int i;
5347         uint32_t bw_max;
5348
5349         memset(&bw_config, 0, sizeof(bw_config));
5350         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5351         if (ret != I40E_SUCCESS) {
5352                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5353                             hw->aq.asq_last_status);
5354                 return ret;
5355         }
5356
5357         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5358         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5359                                         &ets_sla_config, NULL);
5360         if (ret != I40E_SUCCESS) {
5361                 PMD_DRV_LOG(ERR,
5362                         "VSI failed to get TC bandwdith configuration %u",
5363                         hw->aq.asq_last_status);
5364                 return ret;
5365         }
5366
5367         /* store and print out BW info */
5368         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5369         vsi->bw_info.bw_max = bw_config.max_bw;
5370         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5371         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5372         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5373                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5374                      I40E_16_BIT_WIDTH);
5375         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5376                 vsi->bw_info.bw_ets_share_credits[i] =
5377                                 ets_sla_config.share_credits[i];
5378                 vsi->bw_info.bw_ets_credits[i] =
5379                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5380                 /* 4 bits per TC, 4th bit is reserved */
5381                 vsi->bw_info.bw_ets_max[i] =
5382                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5383                                   RTE_LEN2MASK(3, uint8_t));
5384                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5385                             vsi->bw_info.bw_ets_share_credits[i]);
5386                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5387                             vsi->bw_info.bw_ets_credits[i]);
5388                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5389                             vsi->bw_info.bw_ets_max[i]);
5390         }
5391
5392         return I40E_SUCCESS;
5393 }
5394
5395 /* i40e_enable_pf_lb
5396  * @pf: pointer to the pf structure
5397  *
5398  * allow loopback on pf
5399  */
5400 static inline void
5401 i40e_enable_pf_lb(struct i40e_pf *pf)
5402 {
5403         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5404         struct i40e_vsi_context ctxt;
5405         int ret;
5406
5407         /* Use the FW API if FW >= v5.0 */
5408         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5409                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5410                 return;
5411         }
5412
5413         memset(&ctxt, 0, sizeof(ctxt));
5414         ctxt.seid = pf->main_vsi_seid;
5415         ctxt.pf_num = hw->pf_id;
5416         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5417         if (ret) {
5418                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5419                             ret, hw->aq.asq_last_status);
5420                 return;
5421         }
5422         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5423         ctxt.info.valid_sections =
5424                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5425         ctxt.info.switch_id |=
5426                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5427
5428         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5429         if (ret)
5430                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5431                             hw->aq.asq_last_status);
5432 }
5433
5434 /* Setup a VSI */
5435 struct i40e_vsi *
5436 i40e_vsi_setup(struct i40e_pf *pf,
5437                enum i40e_vsi_type type,
5438                struct i40e_vsi *uplink_vsi,
5439                uint16_t user_param)
5440 {
5441         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5442         struct i40e_vsi *vsi;
5443         struct i40e_mac_filter_info filter;
5444         int ret;
5445         struct i40e_vsi_context ctxt;
5446         struct ether_addr broadcast =
5447                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5448
5449         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5450             uplink_vsi == NULL) {
5451                 PMD_DRV_LOG(ERR,
5452                         "VSI setup failed, VSI link shouldn't be NULL");
5453                 return NULL;
5454         }
5455
5456         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5457                 PMD_DRV_LOG(ERR,
5458                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5459                 return NULL;
5460         }
5461
5462         /* two situations
5463          * 1.type is not MAIN and uplink vsi is not NULL
5464          * If uplink vsi didn't setup VEB, create one first under veb field
5465          * 2.type is SRIOV and the uplink is NULL
5466          * If floating VEB is NULL, create one veb under floating veb field
5467          */
5468
5469         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5470             uplink_vsi->veb == NULL) {
5471                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5472
5473                 if (uplink_vsi->veb == NULL) {
5474                         PMD_DRV_LOG(ERR, "VEB setup failed");
5475                         return NULL;
5476                 }
5477                 /* set ALLOWLOOPBACk on pf, when veb is created */
5478                 i40e_enable_pf_lb(pf);
5479         }
5480
5481         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5482             pf->main_vsi->floating_veb == NULL) {
5483                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5484
5485                 if (pf->main_vsi->floating_veb == NULL) {
5486                         PMD_DRV_LOG(ERR, "VEB setup failed");
5487                         return NULL;
5488                 }
5489         }
5490
5491         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5492         if (!vsi) {
5493                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5494                 return NULL;
5495         }
5496         TAILQ_INIT(&vsi->mac_list);
5497         vsi->type = type;
5498         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5499         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5500         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5501         vsi->user_param = user_param;
5502         vsi->vlan_anti_spoof_on = 0;
5503         vsi->vlan_filter_on = 0;
5504         /* Allocate queues */
5505         switch (vsi->type) {
5506         case I40E_VSI_MAIN  :
5507                 vsi->nb_qps = pf->lan_nb_qps;
5508                 break;
5509         case I40E_VSI_SRIOV :
5510                 vsi->nb_qps = pf->vf_nb_qps;
5511                 break;
5512         case I40E_VSI_VMDQ2:
5513                 vsi->nb_qps = pf->vmdq_nb_qps;
5514                 break;
5515         case I40E_VSI_FDIR:
5516                 vsi->nb_qps = pf->fdir_nb_qps;
5517                 break;
5518         default:
5519                 goto fail_mem;
5520         }
5521         /*
5522          * The filter status descriptor is reported in rx queue 0,
5523          * while the tx queue for fdir filter programming has no
5524          * such constraints, can be non-zero queues.
5525          * To simplify it, choose FDIR vsi use queue 0 pair.
5526          * To make sure it will use queue 0 pair, queue allocation
5527          * need be done before this function is called
5528          */
5529         if (type != I40E_VSI_FDIR) {
5530                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5531                         if (ret < 0) {
5532                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5533                                                 vsi->seid, ret);
5534                                 goto fail_mem;
5535                         }
5536                         vsi->base_queue = ret;
5537         } else
5538                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5539
5540         /* VF has MSIX interrupt in VF range, don't allocate here */
5541         if (type == I40E_VSI_MAIN) {
5542                 if (pf->support_multi_driver) {
5543                         /* If support multi-driver, need to use INT0 instead of
5544                          * allocating from msix pool. The Msix pool is init from
5545                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5546                          * to 1 without calling i40e_res_pool_alloc.
5547                          */
5548                         vsi->msix_intr = 0;
5549                         vsi->nb_msix = 1;
5550                 } else {
5551                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5552                                                   RTE_MIN(vsi->nb_qps,
5553                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5554                         if (ret < 0) {
5555                                 PMD_DRV_LOG(ERR,
5556                                             "VSI MAIN %d get heap failed %d",
5557                                             vsi->seid, ret);
5558                                 goto fail_queue_alloc;
5559                         }
5560                         vsi->msix_intr = ret;
5561                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5562                                                RTE_MAX_RXTX_INTR_VEC_ID);
5563                 }
5564         } else if (type != I40E_VSI_SRIOV) {
5565                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5566                 if (ret < 0) {
5567                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5568                         goto fail_queue_alloc;
5569                 }
5570                 vsi->msix_intr = ret;
5571                 vsi->nb_msix = 1;
5572         } else {
5573                 vsi->msix_intr = 0;
5574                 vsi->nb_msix = 0;
5575         }
5576
5577         /* Add VSI */
5578         if (type == I40E_VSI_MAIN) {
5579                 /* For main VSI, no need to add since it's default one */
5580                 vsi->uplink_seid = pf->mac_seid;
5581                 vsi->seid = pf->main_vsi_seid;
5582                 /* Bind queues with specific MSIX interrupt */
5583                 /**
5584                  * Needs 2 interrupt at least, one for misc cause which will
5585                  * enabled from OS side, Another for queues binding the
5586                  * interrupt from device side only.
5587                  */
5588
5589                 /* Get default VSI parameters from hardware */
5590                 memset(&ctxt, 0, sizeof(ctxt));
5591                 ctxt.seid = vsi->seid;
5592                 ctxt.pf_num = hw->pf_id;
5593                 ctxt.uplink_seid = vsi->uplink_seid;
5594                 ctxt.vf_num = 0;
5595                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5596                 if (ret != I40E_SUCCESS) {
5597                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5598                         goto fail_msix_alloc;
5599                 }
5600                 rte_memcpy(&vsi->info, &ctxt.info,
5601                         sizeof(struct i40e_aqc_vsi_properties_data));
5602                 vsi->vsi_id = ctxt.vsi_number;
5603                 vsi->info.valid_sections = 0;
5604
5605                 /* Configure tc, enabled TC0 only */
5606                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5607                         I40E_SUCCESS) {
5608                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5609                         goto fail_msix_alloc;
5610                 }
5611
5612                 /* TC, queue mapping */
5613                 memset(&ctxt, 0, sizeof(ctxt));
5614                 vsi->info.valid_sections |=
5615                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5616                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5617                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5618                 rte_memcpy(&ctxt.info, &vsi->info,
5619                         sizeof(struct i40e_aqc_vsi_properties_data));
5620                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5621                                                 I40E_DEFAULT_TCMAP);
5622                 if (ret != I40E_SUCCESS) {
5623                         PMD_DRV_LOG(ERR,
5624                                 "Failed to configure TC queue mapping");
5625                         goto fail_msix_alloc;
5626                 }
5627                 ctxt.seid = vsi->seid;
5628                 ctxt.pf_num = hw->pf_id;
5629                 ctxt.uplink_seid = vsi->uplink_seid;
5630                 ctxt.vf_num = 0;
5631
5632                 /* Update VSI parameters */
5633                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5634                 if (ret != I40E_SUCCESS) {
5635                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5636                         goto fail_msix_alloc;
5637                 }
5638
5639                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5640                                                 sizeof(vsi->info.tc_mapping));
5641                 rte_memcpy(&vsi->info.queue_mapping,
5642                                 &ctxt.info.queue_mapping,
5643                         sizeof(vsi->info.queue_mapping));
5644                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5645                 vsi->info.valid_sections = 0;
5646
5647                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5648                                 ETH_ADDR_LEN);
5649
5650                 /**
5651                  * Updating default filter settings are necessary to prevent
5652                  * reception of tagged packets.
5653                  * Some old firmware configurations load a default macvlan
5654                  * filter which accepts both tagged and untagged packets.
5655                  * The updating is to use a normal filter instead if needed.
5656                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5657                  * The firmware with correct configurations load the default
5658                  * macvlan filter which is expected and cannot be removed.
5659                  */
5660                 i40e_update_default_filter_setting(vsi);
5661                 i40e_config_qinq(hw, vsi);
5662         } else if (type == I40E_VSI_SRIOV) {
5663                 memset(&ctxt, 0, sizeof(ctxt));
5664                 /**
5665                  * For other VSI, the uplink_seid equals to uplink VSI's
5666                  * uplink_seid since they share same VEB
5667                  */
5668                 if (uplink_vsi == NULL)
5669                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5670                 else
5671                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5672                 ctxt.pf_num = hw->pf_id;
5673                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5674                 ctxt.uplink_seid = vsi->uplink_seid;
5675                 ctxt.connection_type = 0x1;
5676                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5677
5678                 /* Use the VEB configuration if FW >= v5.0 */
5679                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5680                         /* Configure switch ID */
5681                         ctxt.info.valid_sections |=
5682                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5683                         ctxt.info.switch_id =
5684                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5685                 }
5686
5687                 /* Configure port/vlan */
5688                 ctxt.info.valid_sections |=
5689                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5690                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5691                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5692                                                 hw->func_caps.enabled_tcmap);
5693                 if (ret != I40E_SUCCESS) {
5694                         PMD_DRV_LOG(ERR,
5695                                 "Failed to configure TC queue mapping");
5696                         goto fail_msix_alloc;
5697                 }
5698
5699                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5700                 ctxt.info.valid_sections |=
5701                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5702                 /**
5703                  * Since VSI is not created yet, only configure parameter,
5704                  * will add vsi below.
5705                  */
5706
5707                 i40e_config_qinq(hw, vsi);
5708         } else if (type == I40E_VSI_VMDQ2) {
5709                 memset(&ctxt, 0, sizeof(ctxt));
5710                 /*
5711                  * For other VSI, the uplink_seid equals to uplink VSI's
5712                  * uplink_seid since they share same VEB
5713                  */
5714                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5715                 ctxt.pf_num = hw->pf_id;
5716                 ctxt.vf_num = 0;
5717                 ctxt.uplink_seid = vsi->uplink_seid;
5718                 ctxt.connection_type = 0x1;
5719                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5720
5721                 ctxt.info.valid_sections |=
5722                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5723                 /* user_param carries flag to enable loop back */
5724                 if (user_param) {
5725                         ctxt.info.switch_id =
5726                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5727                         ctxt.info.switch_id |=
5728                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5729                 }
5730
5731                 /* Configure port/vlan */
5732                 ctxt.info.valid_sections |=
5733                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5734                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5735                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5736                                                 I40E_DEFAULT_TCMAP);
5737                 if (ret != I40E_SUCCESS) {
5738                         PMD_DRV_LOG(ERR,
5739                                 "Failed to configure TC queue mapping");
5740                         goto fail_msix_alloc;
5741                 }
5742                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5743                 ctxt.info.valid_sections |=
5744                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5745         } else if (type == I40E_VSI_FDIR) {
5746                 memset(&ctxt, 0, sizeof(ctxt));
5747                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5748                 ctxt.pf_num = hw->pf_id;
5749                 ctxt.vf_num = 0;
5750                 ctxt.uplink_seid = vsi->uplink_seid;
5751                 ctxt.connection_type = 0x1;     /* regular data port */
5752                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5753                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5754                                                 I40E_DEFAULT_TCMAP);
5755                 if (ret != I40E_SUCCESS) {
5756                         PMD_DRV_LOG(ERR,
5757                                 "Failed to configure TC queue mapping.");
5758                         goto fail_msix_alloc;
5759                 }
5760                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5761                 ctxt.info.valid_sections |=
5762                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5763         } else {
5764                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5765                 goto fail_msix_alloc;
5766         }
5767
5768         if (vsi->type != I40E_VSI_MAIN) {
5769                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5770                 if (ret != I40E_SUCCESS) {
5771                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5772                                     hw->aq.asq_last_status);
5773                         goto fail_msix_alloc;
5774                 }
5775                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5776                 vsi->info.valid_sections = 0;
5777                 vsi->seid = ctxt.seid;
5778                 vsi->vsi_id = ctxt.vsi_number;
5779                 vsi->sib_vsi_list.vsi = vsi;
5780                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5781                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5782                                           &vsi->sib_vsi_list, list);
5783                 } else {
5784                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5785                                           &vsi->sib_vsi_list, list);
5786                 }
5787         }
5788
5789         /* MAC/VLAN configuration */
5790         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5791         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5792
5793         ret = i40e_vsi_add_mac(vsi, &filter);
5794         if (ret != I40E_SUCCESS) {
5795                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5796                 goto fail_msix_alloc;
5797         }
5798
5799         /* Get VSI BW information */
5800         i40e_vsi_get_bw_config(vsi);
5801         return vsi;
5802 fail_msix_alloc:
5803         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5804 fail_queue_alloc:
5805         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5806 fail_mem:
5807         rte_free(vsi);
5808         return NULL;
5809 }
5810
5811 /* Configure vlan filter on or off */
5812 int
5813 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5814 {
5815         int i, num;
5816         struct i40e_mac_filter *f;
5817         void *temp;
5818         struct i40e_mac_filter_info *mac_filter;
5819         enum rte_mac_filter_type desired_filter;
5820         int ret = I40E_SUCCESS;
5821
5822         if (on) {
5823                 /* Filter to match MAC and VLAN */
5824                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5825         } else {
5826                 /* Filter to match only MAC */
5827                 desired_filter = RTE_MAC_PERFECT_MATCH;
5828         }
5829
5830         num = vsi->mac_num;
5831
5832         mac_filter = rte_zmalloc("mac_filter_info_data",
5833                                  num * sizeof(*mac_filter), 0);
5834         if (mac_filter == NULL) {
5835                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5836                 return I40E_ERR_NO_MEMORY;
5837         }
5838
5839         i = 0;
5840
5841         /* Remove all existing mac */
5842         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5843                 mac_filter[i] = f->mac_info;
5844                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5845                 if (ret) {
5846                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5847                                     on ? "enable" : "disable");
5848                         goto DONE;
5849                 }
5850                 i++;
5851         }
5852
5853         /* Override with new filter */
5854         for (i = 0; i < num; i++) {
5855                 mac_filter[i].filter_type = desired_filter;
5856                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5857                 if (ret) {
5858                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5859                                     on ? "enable" : "disable");
5860                         goto DONE;
5861                 }
5862         }
5863
5864 DONE:
5865         rte_free(mac_filter);
5866         return ret;
5867 }
5868
5869 /* Configure vlan stripping on or off */
5870 int
5871 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5872 {
5873         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5874         struct i40e_vsi_context ctxt;
5875         uint8_t vlan_flags;
5876         int ret = I40E_SUCCESS;
5877
5878         /* Check if it has been already on or off */
5879         if (vsi->info.valid_sections &
5880                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5881                 if (on) {
5882                         if ((vsi->info.port_vlan_flags &
5883                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5884                                 return 0; /* already on */
5885                 } else {
5886                         if ((vsi->info.port_vlan_flags &
5887                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5888                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5889                                 return 0; /* already off */
5890                 }
5891         }
5892
5893         if (on)
5894                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5895         else
5896                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5897         vsi->info.valid_sections =
5898                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5899         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5900         vsi->info.port_vlan_flags |= vlan_flags;
5901         ctxt.seid = vsi->seid;
5902         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5903         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5904         if (ret)
5905                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5906                             on ? "enable" : "disable");
5907
5908         return ret;
5909 }
5910
5911 static int
5912 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5913 {
5914         struct rte_eth_dev_data *data = dev->data;
5915         int ret;
5916         int mask = 0;
5917
5918         /* Apply vlan offload setting */
5919         mask = ETH_VLAN_STRIP_MASK |
5920                ETH_VLAN_FILTER_MASK |
5921                ETH_VLAN_EXTEND_MASK;
5922         ret = i40e_vlan_offload_set(dev, mask);
5923         if (ret) {
5924                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5925                 return ret;
5926         }
5927
5928         /* Apply pvid setting */
5929         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5930                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5931         if (ret)
5932                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5933
5934         return ret;
5935 }
5936
5937 static int
5938 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5939 {
5940         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5941
5942         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5943 }
5944
5945 static int
5946 i40e_update_flow_control(struct i40e_hw *hw)
5947 {
5948 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5949         struct i40e_link_status link_status;
5950         uint32_t rxfc = 0, txfc = 0, reg;
5951         uint8_t an_info;
5952         int ret;
5953
5954         memset(&link_status, 0, sizeof(link_status));
5955         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5956         if (ret != I40E_SUCCESS) {
5957                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5958                 goto write_reg; /* Disable flow control */
5959         }
5960
5961         an_info = hw->phy.link_info.an_info;
5962         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5963                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5964                 ret = I40E_ERR_NOT_READY;
5965                 goto write_reg; /* Disable flow control */
5966         }
5967         /**
5968          * If link auto negotiation is enabled, flow control needs to
5969          * be configured according to it
5970          */
5971         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5972         case I40E_LINK_PAUSE_RXTX:
5973                 rxfc = 1;
5974                 txfc = 1;
5975                 hw->fc.current_mode = I40E_FC_FULL;
5976                 break;
5977         case I40E_AQ_LINK_PAUSE_RX:
5978                 rxfc = 1;
5979                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5980                 break;
5981         case I40E_AQ_LINK_PAUSE_TX:
5982                 txfc = 1;
5983                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5984                 break;
5985         default:
5986                 hw->fc.current_mode = I40E_FC_NONE;
5987                 break;
5988         }
5989
5990 write_reg:
5991         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5992                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5993         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5994         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5995         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5996         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5997
5998         return ret;
5999 }
6000
6001 /* PF setup */
6002 static int
6003 i40e_pf_setup(struct i40e_pf *pf)
6004 {
6005         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6006         struct i40e_filter_control_settings settings;
6007         struct i40e_vsi *vsi;
6008         int ret;
6009
6010         /* Clear all stats counters */
6011         pf->offset_loaded = FALSE;
6012         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6013         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6014         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6015         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6016
6017         ret = i40e_pf_get_switch_config(pf);
6018         if (ret != I40E_SUCCESS) {
6019                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6020                 return ret;
6021         }
6022
6023         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6024         if (ret)
6025                 PMD_INIT_LOG(WARNING,
6026                         "failed to allocate switch domain for device %d", ret);
6027
6028         if (pf->flags & I40E_FLAG_FDIR) {
6029                 /* make queue allocated first, let FDIR use queue pair 0*/
6030                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6031                 if (ret != I40E_FDIR_QUEUE_ID) {
6032                         PMD_DRV_LOG(ERR,
6033                                 "queue allocation fails for FDIR: ret =%d",
6034                                 ret);
6035                         pf->flags &= ~I40E_FLAG_FDIR;
6036                 }
6037         }
6038         /*  main VSI setup */
6039         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6040         if (!vsi) {
6041                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6042                 return I40E_ERR_NOT_READY;
6043         }
6044         pf->main_vsi = vsi;
6045
6046         /* Configure filter control */
6047         memset(&settings, 0, sizeof(settings));
6048         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6049                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6050         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6051                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6052         else {
6053                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6054                         hw->func_caps.rss_table_size);
6055                 return I40E_ERR_PARAM;
6056         }
6057         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6058                 hw->func_caps.rss_table_size);
6059         pf->hash_lut_size = hw->func_caps.rss_table_size;
6060
6061         /* Enable ethtype and macvlan filters */
6062         settings.enable_ethtype = TRUE;
6063         settings.enable_macvlan = TRUE;
6064         ret = i40e_set_filter_control(hw, &settings);
6065         if (ret)
6066                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6067                                                                 ret);
6068
6069         /* Update flow control according to the auto negotiation */
6070         i40e_update_flow_control(hw);
6071
6072         return I40E_SUCCESS;
6073 }
6074
6075 int
6076 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6077 {
6078         uint32_t reg;
6079         uint16_t j;
6080
6081         /**
6082          * Set or clear TX Queue Disable flags,
6083          * which is required by hardware.
6084          */
6085         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6086         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6087
6088         /* Wait until the request is finished */
6089         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6090                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6091                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6092                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6093                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6094                                                         & 0x1))) {
6095                         break;
6096                 }
6097         }
6098         if (on) {
6099                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6100                         return I40E_SUCCESS; /* already on, skip next steps */
6101
6102                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6103                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6104         } else {
6105                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6106                         return I40E_SUCCESS; /* already off, skip next steps */
6107                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6108         }
6109         /* Write the register */
6110         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6111         /* Check the result */
6112         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6113                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6114                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6115                 if (on) {
6116                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6117                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6118                                 break;
6119                 } else {
6120                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6121                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6122                                 break;
6123                 }
6124         }
6125         /* Check if it is timeout */
6126         if (j >= I40E_CHK_Q_ENA_COUNT) {
6127                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6128                             (on ? "enable" : "disable"), q_idx);
6129                 return I40E_ERR_TIMEOUT;
6130         }
6131
6132         return I40E_SUCCESS;
6133 }
6134
6135 /* Swith on or off the tx queues */
6136 static int
6137 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6138 {
6139         struct rte_eth_dev_data *dev_data = pf->dev_data;
6140         struct i40e_tx_queue *txq;
6141         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6142         uint16_t i;
6143         int ret;
6144
6145         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6146                 txq = dev_data->tx_queues[i];
6147                 /* Don't operate the queue if not configured or
6148                  * if starting only per queue */
6149                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6150                         continue;
6151                 if (on)
6152                         ret = i40e_dev_tx_queue_start(dev, i);
6153                 else
6154                         ret = i40e_dev_tx_queue_stop(dev, i);
6155                 if ( ret != I40E_SUCCESS)
6156                         return ret;
6157         }
6158
6159         return I40E_SUCCESS;
6160 }
6161
6162 int
6163 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6164 {
6165         uint32_t reg;
6166         uint16_t j;
6167
6168         /* Wait until the request is finished */
6169         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6170                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6171                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6172                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6173                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6174                         break;
6175         }
6176
6177         if (on) {
6178                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6179                         return I40E_SUCCESS; /* Already on, skip next steps */
6180                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6181         } else {
6182                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6183                         return I40E_SUCCESS; /* Already off, skip next steps */
6184                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6185         }
6186
6187         /* Write the register */
6188         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6189         /* Check the result */
6190         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6191                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6192                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6193                 if (on) {
6194                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6195                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6196                                 break;
6197                 } else {
6198                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6199                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6200                                 break;
6201                 }
6202         }
6203
6204         /* Check if it is timeout */
6205         if (j >= I40E_CHK_Q_ENA_COUNT) {
6206                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6207                             (on ? "enable" : "disable"), q_idx);
6208                 return I40E_ERR_TIMEOUT;
6209         }
6210
6211         return I40E_SUCCESS;
6212 }
6213 /* Switch on or off the rx queues */
6214 static int
6215 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6216 {
6217         struct rte_eth_dev_data *dev_data = pf->dev_data;
6218         struct i40e_rx_queue *rxq;
6219         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6220         uint16_t i;
6221         int ret;
6222
6223         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6224                 rxq = dev_data->rx_queues[i];
6225                 /* Don't operate the queue if not configured or
6226                  * if starting only per queue */
6227                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6228                         continue;
6229                 if (on)
6230                         ret = i40e_dev_rx_queue_start(dev, i);
6231                 else
6232                         ret = i40e_dev_rx_queue_stop(dev, i);
6233                 if (ret != I40E_SUCCESS)
6234                         return ret;
6235         }
6236
6237         return I40E_SUCCESS;
6238 }
6239
6240 /* Switch on or off all the rx/tx queues */
6241 int
6242 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6243 {
6244         int ret;
6245
6246         if (on) {
6247                 /* enable rx queues before enabling tx queues */
6248                 ret = i40e_dev_switch_rx_queues(pf, on);
6249                 if (ret) {
6250                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6251                         return ret;
6252                 }
6253                 ret = i40e_dev_switch_tx_queues(pf, on);
6254         } else {
6255                 /* Stop tx queues before stopping rx queues */
6256                 ret = i40e_dev_switch_tx_queues(pf, on);
6257                 if (ret) {
6258                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6259                         return ret;
6260                 }
6261                 ret = i40e_dev_switch_rx_queues(pf, on);
6262         }
6263
6264         return ret;
6265 }
6266
6267 /* Initialize VSI for TX */
6268 static int
6269 i40e_dev_tx_init(struct i40e_pf *pf)
6270 {
6271         struct rte_eth_dev_data *data = pf->dev_data;
6272         uint16_t i;
6273         uint32_t ret = I40E_SUCCESS;
6274         struct i40e_tx_queue *txq;
6275
6276         for (i = 0; i < data->nb_tx_queues; i++) {
6277                 txq = data->tx_queues[i];
6278                 if (!txq || !txq->q_set)
6279                         continue;
6280                 ret = i40e_tx_queue_init(txq);
6281                 if (ret != I40E_SUCCESS)
6282                         break;
6283         }
6284         if (ret == I40E_SUCCESS)
6285                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6286                                      ->eth_dev);
6287
6288         return ret;
6289 }
6290
6291 /* Initialize VSI for RX */
6292 static int
6293 i40e_dev_rx_init(struct i40e_pf *pf)
6294 {
6295         struct rte_eth_dev_data *data = pf->dev_data;
6296         int ret = I40E_SUCCESS;
6297         uint16_t i;
6298         struct i40e_rx_queue *rxq;
6299
6300         i40e_pf_config_mq_rx(pf);
6301         for (i = 0; i < data->nb_rx_queues; i++) {
6302                 rxq = data->rx_queues[i];
6303                 if (!rxq || !rxq->q_set)
6304                         continue;
6305
6306                 ret = i40e_rx_queue_init(rxq);
6307                 if (ret != I40E_SUCCESS) {
6308                         PMD_DRV_LOG(ERR,
6309                                 "Failed to do RX queue initialization");
6310                         break;
6311                 }
6312         }
6313         if (ret == I40E_SUCCESS)
6314                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6315                                      ->eth_dev);
6316
6317         return ret;
6318 }
6319
6320 static int
6321 i40e_dev_rxtx_init(struct i40e_pf *pf)
6322 {
6323         int err;
6324
6325         err = i40e_dev_tx_init(pf);
6326         if (err) {
6327                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6328                 return err;
6329         }
6330         err = i40e_dev_rx_init(pf);
6331         if (err) {
6332                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6333                 return err;
6334         }
6335
6336         return err;
6337 }
6338
6339 static int
6340 i40e_vmdq_setup(struct rte_eth_dev *dev)
6341 {
6342         struct rte_eth_conf *conf = &dev->data->dev_conf;
6343         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6344         int i, err, conf_vsis, j, loop;
6345         struct i40e_vsi *vsi;
6346         struct i40e_vmdq_info *vmdq_info;
6347         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6348         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6349
6350         /*
6351          * Disable interrupt to avoid message from VF. Furthermore, it will
6352          * avoid race condition in VSI creation/destroy.
6353          */
6354         i40e_pf_disable_irq0(hw);
6355
6356         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6357                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6358                 return -ENOTSUP;
6359         }
6360
6361         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6362         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6363                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6364                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6365                         pf->max_nb_vmdq_vsi);
6366                 return -ENOTSUP;
6367         }
6368
6369         if (pf->vmdq != NULL) {
6370                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6371                 return 0;
6372         }
6373
6374         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6375                                 sizeof(*vmdq_info) * conf_vsis, 0);
6376
6377         if (pf->vmdq == NULL) {
6378                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6379                 return -ENOMEM;
6380         }
6381
6382         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6383
6384         /* Create VMDQ VSI */
6385         for (i = 0; i < conf_vsis; i++) {
6386                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6387                                 vmdq_conf->enable_loop_back);
6388                 if (vsi == NULL) {
6389                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6390                         err = -1;
6391                         goto err_vsi_setup;
6392                 }
6393                 vmdq_info = &pf->vmdq[i];
6394                 vmdq_info->pf = pf;
6395                 vmdq_info->vsi = vsi;
6396         }
6397         pf->nb_cfg_vmdq_vsi = conf_vsis;
6398
6399         /* Configure Vlan */
6400         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6401         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6402                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6403                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6404                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6405                                         vmdq_conf->pool_map[i].vlan_id, j);
6406
6407                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6408                                                 vmdq_conf->pool_map[i].vlan_id);
6409                                 if (err) {
6410                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6411                                         err = -1;
6412                                         goto err_vsi_setup;
6413                                 }
6414                         }
6415                 }
6416         }
6417
6418         i40e_pf_enable_irq0(hw);
6419
6420         return 0;
6421
6422 err_vsi_setup:
6423         for (i = 0; i < conf_vsis; i++)
6424                 if (pf->vmdq[i].vsi == NULL)
6425                         break;
6426                 else
6427                         i40e_vsi_release(pf->vmdq[i].vsi);
6428
6429         rte_free(pf->vmdq);
6430         pf->vmdq = NULL;
6431         i40e_pf_enable_irq0(hw);
6432         return err;
6433 }
6434
6435 static void
6436 i40e_stat_update_32(struct i40e_hw *hw,
6437                    uint32_t reg,
6438                    bool offset_loaded,
6439                    uint64_t *offset,
6440                    uint64_t *stat)
6441 {
6442         uint64_t new_data;
6443
6444         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6445         if (!offset_loaded)
6446                 *offset = new_data;
6447
6448         if (new_data >= *offset)
6449                 *stat = (uint64_t)(new_data - *offset);
6450         else
6451                 *stat = (uint64_t)((new_data +
6452                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6453 }
6454
6455 static void
6456 i40e_stat_update_48(struct i40e_hw *hw,
6457                    uint32_t hireg,
6458                    uint32_t loreg,
6459                    bool offset_loaded,
6460                    uint64_t *offset,
6461                    uint64_t *stat)
6462 {
6463         uint64_t new_data;
6464
6465         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6466         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6467                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6468
6469         if (!offset_loaded)
6470                 *offset = new_data;
6471
6472         if (new_data >= *offset)
6473                 *stat = new_data - *offset;
6474         else
6475                 *stat = (uint64_t)((new_data +
6476                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6477
6478         *stat &= I40E_48_BIT_MASK;
6479 }
6480
6481 /* Disable IRQ0 */
6482 void
6483 i40e_pf_disable_irq0(struct i40e_hw *hw)
6484 {
6485         /* Disable all interrupt types */
6486         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6487                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6488         I40E_WRITE_FLUSH(hw);
6489 }
6490
6491 /* Enable IRQ0 */
6492 void
6493 i40e_pf_enable_irq0(struct i40e_hw *hw)
6494 {
6495         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6496                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6497                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6498                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6499         I40E_WRITE_FLUSH(hw);
6500 }
6501
6502 static void
6503 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6504 {
6505         /* read pending request and disable first */
6506         i40e_pf_disable_irq0(hw);
6507         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6508         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6509                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6510
6511         if (no_queue)
6512                 /* Link no queues with irq0 */
6513                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6514                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6515 }
6516
6517 static void
6518 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6519 {
6520         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6521         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6522         int i;
6523         uint16_t abs_vf_id;
6524         uint32_t index, offset, val;
6525
6526         if (!pf->vfs)
6527                 return;
6528         /**
6529          * Try to find which VF trigger a reset, use absolute VF id to access
6530          * since the reg is global register.
6531          */
6532         for (i = 0; i < pf->vf_num; i++) {
6533                 abs_vf_id = hw->func_caps.vf_base_id + i;
6534                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6535                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6536                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6537                 /* VFR event occurred */
6538                 if (val & (0x1 << offset)) {
6539                         int ret;
6540
6541                         /* Clear the event first */
6542                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6543                                                         (0x1 << offset));
6544                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6545                         /**
6546                          * Only notify a VF reset event occurred,
6547                          * don't trigger another SW reset
6548                          */
6549                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6550                         if (ret != I40E_SUCCESS)
6551                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6552                 }
6553         }
6554 }
6555
6556 static void
6557 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6558 {
6559         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6560         int i;
6561
6562         for (i = 0; i < pf->vf_num; i++)
6563                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6564 }
6565
6566 static void
6567 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6568 {
6569         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6570         struct i40e_arq_event_info info;
6571         uint16_t pending, opcode;
6572         int ret;
6573
6574         info.buf_len = I40E_AQ_BUF_SZ;
6575         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6576         if (!info.msg_buf) {
6577                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6578                 return;
6579         }
6580
6581         pending = 1;
6582         while (pending) {
6583                 ret = i40e_clean_arq_element(hw, &info, &pending);
6584
6585                 if (ret != I40E_SUCCESS) {
6586                         PMD_DRV_LOG(INFO,
6587                                 "Failed to read msg from AdminQ, aq_err: %u",
6588                                 hw->aq.asq_last_status);
6589                         break;
6590                 }
6591                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6592
6593                 switch (opcode) {
6594                 case i40e_aqc_opc_send_msg_to_pf:
6595                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6596                         i40e_pf_host_handle_vf_msg(dev,
6597                                         rte_le_to_cpu_16(info.desc.retval),
6598                                         rte_le_to_cpu_32(info.desc.cookie_high),
6599                                         rte_le_to_cpu_32(info.desc.cookie_low),
6600                                         info.msg_buf,
6601                                         info.msg_len);
6602                         break;
6603                 case i40e_aqc_opc_get_link_status:
6604                         ret = i40e_dev_link_update(dev, 0);
6605                         if (!ret)
6606                                 _rte_eth_dev_callback_process(dev,
6607                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6608                         break;
6609                 default:
6610                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6611                                     opcode);
6612                         break;
6613                 }
6614         }
6615         rte_free(info.msg_buf);
6616 }
6617
6618 /**
6619  * Interrupt handler triggered by NIC  for handling
6620  * specific interrupt.
6621  *
6622  * @param handle
6623  *  Pointer to interrupt handle.
6624  * @param param
6625  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6626  *
6627  * @return
6628  *  void
6629  */
6630 static void
6631 i40e_dev_interrupt_handler(void *param)
6632 {
6633         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6634         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6635         uint32_t icr0;
6636
6637         /* Disable interrupt */
6638         i40e_pf_disable_irq0(hw);
6639
6640         /* read out interrupt causes */
6641         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6642
6643         /* No interrupt event indicated */
6644         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6645                 PMD_DRV_LOG(INFO, "No interrupt event");
6646                 goto done;
6647         }
6648         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6649                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6650         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6651                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6652         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6653                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6654         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6655                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6656         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6657                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6658         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6659                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6660         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6661                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6662
6663         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6664                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6665                 i40e_dev_handle_vfr_event(dev);
6666         }
6667         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6668                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6669                 i40e_dev_handle_aq_msg(dev);
6670         }
6671
6672 done:
6673         /* Enable interrupt */
6674         i40e_pf_enable_irq0(hw);
6675 }
6676
6677 static void
6678 i40e_dev_alarm_handler(void *param)
6679 {
6680         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6681         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6682         uint32_t icr0;
6683
6684         /* Disable interrupt */
6685         i40e_pf_disable_irq0(hw);
6686
6687         /* read out interrupt causes */
6688         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6689
6690         /* No interrupt event indicated */
6691         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6692                 goto done;
6693         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6694                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6695         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6696                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6697         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6698                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6699         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6700                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6701         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6702                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6703         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6704                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6705         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6706                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6707
6708         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6709                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6710                 i40e_dev_handle_vfr_event(dev);
6711         }
6712         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6713                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6714                 i40e_dev_handle_aq_msg(dev);
6715         }
6716
6717 done:
6718         /* Enable interrupt */
6719         i40e_pf_enable_irq0(hw);
6720         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6721                           i40e_dev_alarm_handler, dev);
6722 }
6723
6724 int
6725 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6726                          struct i40e_macvlan_filter *filter,
6727                          int total)
6728 {
6729         int ele_num, ele_buff_size;
6730         int num, actual_num, i;
6731         uint16_t flags;
6732         int ret = I40E_SUCCESS;
6733         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6734         struct i40e_aqc_add_macvlan_element_data *req_list;
6735
6736         if (filter == NULL  || total == 0)
6737                 return I40E_ERR_PARAM;
6738         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6739         ele_buff_size = hw->aq.asq_buf_size;
6740
6741         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6742         if (req_list == NULL) {
6743                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6744                 return I40E_ERR_NO_MEMORY;
6745         }
6746
6747         num = 0;
6748         do {
6749                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6750                 memset(req_list, 0, ele_buff_size);
6751
6752                 for (i = 0; i < actual_num; i++) {
6753                         rte_memcpy(req_list[i].mac_addr,
6754                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6755                         req_list[i].vlan_tag =
6756                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6757
6758                         switch (filter[num + i].filter_type) {
6759                         case RTE_MAC_PERFECT_MATCH:
6760                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6761                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6762                                 break;
6763                         case RTE_MACVLAN_PERFECT_MATCH:
6764                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6765                                 break;
6766                         case RTE_MAC_HASH_MATCH:
6767                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6768                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6769                                 break;
6770                         case RTE_MACVLAN_HASH_MATCH:
6771                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6772                                 break;
6773                         default:
6774                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6775                                 ret = I40E_ERR_PARAM;
6776                                 goto DONE;
6777                         }
6778
6779                         req_list[i].queue_number = 0;
6780
6781                         req_list[i].flags = rte_cpu_to_le_16(flags);
6782                 }
6783
6784                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6785                                                 actual_num, NULL);
6786                 if (ret != I40E_SUCCESS) {
6787                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6788                         goto DONE;
6789                 }
6790                 num += actual_num;
6791         } while (num < total);
6792
6793 DONE:
6794         rte_free(req_list);
6795         return ret;
6796 }
6797
6798 int
6799 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6800                             struct i40e_macvlan_filter *filter,
6801                             int total)
6802 {
6803         int ele_num, ele_buff_size;
6804         int num, actual_num, i;
6805         uint16_t flags;
6806         int ret = I40E_SUCCESS;
6807         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6808         struct i40e_aqc_remove_macvlan_element_data *req_list;
6809
6810         if (filter == NULL  || total == 0)
6811                 return I40E_ERR_PARAM;
6812
6813         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6814         ele_buff_size = hw->aq.asq_buf_size;
6815
6816         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6817         if (req_list == NULL) {
6818                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6819                 return I40E_ERR_NO_MEMORY;
6820         }
6821
6822         num = 0;
6823         do {
6824                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6825                 memset(req_list, 0, ele_buff_size);
6826
6827                 for (i = 0; i < actual_num; i++) {
6828                         rte_memcpy(req_list[i].mac_addr,
6829                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6830                         req_list[i].vlan_tag =
6831                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6832
6833                         switch (filter[num + i].filter_type) {
6834                         case RTE_MAC_PERFECT_MATCH:
6835                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6836                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6837                                 break;
6838                         case RTE_MACVLAN_PERFECT_MATCH:
6839                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6840                                 break;
6841                         case RTE_MAC_HASH_MATCH:
6842                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6843                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6844                                 break;
6845                         case RTE_MACVLAN_HASH_MATCH:
6846                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6847                                 break;
6848                         default:
6849                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6850                                 ret = I40E_ERR_PARAM;
6851                                 goto DONE;
6852                         }
6853                         req_list[i].flags = rte_cpu_to_le_16(flags);
6854                 }
6855
6856                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6857                                                 actual_num, NULL);
6858                 if (ret != I40E_SUCCESS) {
6859                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6860                         goto DONE;
6861                 }
6862                 num += actual_num;
6863         } while (num < total);
6864
6865 DONE:
6866         rte_free(req_list);
6867         return ret;
6868 }
6869
6870 /* Find out specific MAC filter */
6871 static struct i40e_mac_filter *
6872 i40e_find_mac_filter(struct i40e_vsi *vsi,
6873                          struct ether_addr *macaddr)
6874 {
6875         struct i40e_mac_filter *f;
6876
6877         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6878                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6879                         return f;
6880         }
6881
6882         return NULL;
6883 }
6884
6885 static bool
6886 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6887                          uint16_t vlan_id)
6888 {
6889         uint32_t vid_idx, vid_bit;
6890
6891         if (vlan_id > ETH_VLAN_ID_MAX)
6892                 return 0;
6893
6894         vid_idx = I40E_VFTA_IDX(vlan_id);
6895         vid_bit = I40E_VFTA_BIT(vlan_id);
6896
6897         if (vsi->vfta[vid_idx] & vid_bit)
6898                 return 1;
6899         else
6900                 return 0;
6901 }
6902
6903 static void
6904 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6905                        uint16_t vlan_id, bool on)
6906 {
6907         uint32_t vid_idx, vid_bit;
6908
6909         vid_idx = I40E_VFTA_IDX(vlan_id);
6910         vid_bit = I40E_VFTA_BIT(vlan_id);
6911
6912         if (on)
6913                 vsi->vfta[vid_idx] |= vid_bit;
6914         else
6915                 vsi->vfta[vid_idx] &= ~vid_bit;
6916 }
6917
6918 void
6919 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6920                      uint16_t vlan_id, bool on)
6921 {
6922         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6923         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6924         int ret;
6925
6926         if (vlan_id > ETH_VLAN_ID_MAX)
6927                 return;
6928
6929         i40e_store_vlan_filter(vsi, vlan_id, on);
6930
6931         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6932                 return;
6933
6934         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6935
6936         if (on) {
6937                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6938                                        &vlan_data, 1, NULL);
6939                 if (ret != I40E_SUCCESS)
6940                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6941         } else {
6942                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6943                                           &vlan_data, 1, NULL);
6944                 if (ret != I40E_SUCCESS)
6945                         PMD_DRV_LOG(ERR,
6946                                     "Failed to remove vlan filter");
6947         }
6948 }
6949
6950 /**
6951  * Find all vlan options for specific mac addr,
6952  * return with actual vlan found.
6953  */
6954 int
6955 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6956                            struct i40e_macvlan_filter *mv_f,
6957                            int num, struct ether_addr *addr)
6958 {
6959         int i;
6960         uint32_t j, k;
6961
6962         /**
6963          * Not to use i40e_find_vlan_filter to decrease the loop time,
6964          * although the code looks complex.
6965           */
6966         if (num < vsi->vlan_num)
6967                 return I40E_ERR_PARAM;
6968
6969         i = 0;
6970         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6971                 if (vsi->vfta[j]) {
6972                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6973                                 if (vsi->vfta[j] & (1 << k)) {
6974                                         if (i > num - 1) {
6975                                                 PMD_DRV_LOG(ERR,
6976                                                         "vlan number doesn't match");
6977                                                 return I40E_ERR_PARAM;
6978                                         }
6979                                         rte_memcpy(&mv_f[i].macaddr,
6980                                                         addr, ETH_ADDR_LEN);
6981                                         mv_f[i].vlan_id =
6982                                                 j * I40E_UINT32_BIT_SIZE + k;
6983                                         i++;
6984                                 }
6985                         }
6986                 }
6987         }
6988         return I40E_SUCCESS;
6989 }
6990
6991 static inline int
6992 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6993                            struct i40e_macvlan_filter *mv_f,
6994                            int num,
6995                            uint16_t vlan)
6996 {
6997         int i = 0;
6998         struct i40e_mac_filter *f;
6999
7000         if (num < vsi->mac_num)
7001                 return I40E_ERR_PARAM;
7002
7003         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7004                 if (i > num - 1) {
7005                         PMD_DRV_LOG(ERR, "buffer number not match");
7006                         return I40E_ERR_PARAM;
7007                 }
7008                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7009                                 ETH_ADDR_LEN);
7010                 mv_f[i].vlan_id = vlan;
7011                 mv_f[i].filter_type = f->mac_info.filter_type;
7012                 i++;
7013         }
7014
7015         return I40E_SUCCESS;
7016 }
7017
7018 static int
7019 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7020 {
7021         int i, j, num;
7022         struct i40e_mac_filter *f;
7023         struct i40e_macvlan_filter *mv_f;
7024         int ret = I40E_SUCCESS;
7025
7026         if (vsi == NULL || vsi->mac_num == 0)
7027                 return I40E_ERR_PARAM;
7028
7029         /* Case that no vlan is set */
7030         if (vsi->vlan_num == 0)
7031                 num = vsi->mac_num;
7032         else
7033                 num = vsi->mac_num * vsi->vlan_num;
7034
7035         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7036         if (mv_f == NULL) {
7037                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7038                 return I40E_ERR_NO_MEMORY;
7039         }
7040
7041         i = 0;
7042         if (vsi->vlan_num == 0) {
7043                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7044                         rte_memcpy(&mv_f[i].macaddr,
7045                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7046                         mv_f[i].filter_type = f->mac_info.filter_type;
7047                         mv_f[i].vlan_id = 0;
7048                         i++;
7049                 }
7050         } else {
7051                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7052                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7053                                         vsi->vlan_num, &f->mac_info.mac_addr);
7054                         if (ret != I40E_SUCCESS)
7055                                 goto DONE;
7056                         for (j = i; j < i + vsi->vlan_num; j++)
7057                                 mv_f[j].filter_type = f->mac_info.filter_type;
7058                         i += vsi->vlan_num;
7059                 }
7060         }
7061
7062         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7063 DONE:
7064         rte_free(mv_f);
7065
7066         return ret;
7067 }
7068
7069 int
7070 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7071 {
7072         struct i40e_macvlan_filter *mv_f;
7073         int mac_num;
7074         int ret = I40E_SUCCESS;
7075
7076         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
7077                 return I40E_ERR_PARAM;
7078
7079         /* If it's already set, just return */
7080         if (i40e_find_vlan_filter(vsi,vlan))
7081                 return I40E_SUCCESS;
7082
7083         mac_num = vsi->mac_num;
7084
7085         if (mac_num == 0) {
7086                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7087                 return I40E_ERR_PARAM;
7088         }
7089
7090         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7091
7092         if (mv_f == NULL) {
7093                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7094                 return I40E_ERR_NO_MEMORY;
7095         }
7096
7097         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7098
7099         if (ret != I40E_SUCCESS)
7100                 goto DONE;
7101
7102         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7103
7104         if (ret != I40E_SUCCESS)
7105                 goto DONE;
7106
7107         i40e_set_vlan_filter(vsi, vlan, 1);
7108
7109         vsi->vlan_num++;
7110         ret = I40E_SUCCESS;
7111 DONE:
7112         rte_free(mv_f);
7113         return ret;
7114 }
7115
7116 int
7117 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7118 {
7119         struct i40e_macvlan_filter *mv_f;
7120         int mac_num;
7121         int ret = I40E_SUCCESS;
7122
7123         /**
7124          * Vlan 0 is the generic filter for untagged packets
7125          * and can't be removed.
7126          */
7127         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
7128                 return I40E_ERR_PARAM;
7129
7130         /* If can't find it, just return */
7131         if (!i40e_find_vlan_filter(vsi, vlan))
7132                 return I40E_ERR_PARAM;
7133
7134         mac_num = vsi->mac_num;
7135
7136         if (mac_num == 0) {
7137                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7138                 return I40E_ERR_PARAM;
7139         }
7140
7141         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7142
7143         if (mv_f == NULL) {
7144                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7145                 return I40E_ERR_NO_MEMORY;
7146         }
7147
7148         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7149
7150         if (ret != I40E_SUCCESS)
7151                 goto DONE;
7152
7153         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7154
7155         if (ret != I40E_SUCCESS)
7156                 goto DONE;
7157
7158         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7159         if (vsi->vlan_num == 1) {
7160                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7161                 if (ret != I40E_SUCCESS)
7162                         goto DONE;
7163
7164                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7165                 if (ret != I40E_SUCCESS)
7166                         goto DONE;
7167         }
7168
7169         i40e_set_vlan_filter(vsi, vlan, 0);
7170
7171         vsi->vlan_num--;
7172         ret = I40E_SUCCESS;
7173 DONE:
7174         rte_free(mv_f);
7175         return ret;
7176 }
7177
7178 int
7179 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7180 {
7181         struct i40e_mac_filter *f;
7182         struct i40e_macvlan_filter *mv_f;
7183         int i, vlan_num = 0;
7184         int ret = I40E_SUCCESS;
7185
7186         /* If it's add and we've config it, return */
7187         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7188         if (f != NULL)
7189                 return I40E_SUCCESS;
7190         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7191                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7192
7193                 /**
7194                  * If vlan_num is 0, that's the first time to add mac,
7195                  * set mask for vlan_id 0.
7196                  */
7197                 if (vsi->vlan_num == 0) {
7198                         i40e_set_vlan_filter(vsi, 0, 1);
7199                         vsi->vlan_num = 1;
7200                 }
7201                 vlan_num = vsi->vlan_num;
7202         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7203                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7204                 vlan_num = 1;
7205
7206         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7207         if (mv_f == NULL) {
7208                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7209                 return I40E_ERR_NO_MEMORY;
7210         }
7211
7212         for (i = 0; i < vlan_num; i++) {
7213                 mv_f[i].filter_type = mac_filter->filter_type;
7214                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7215                                 ETH_ADDR_LEN);
7216         }
7217
7218         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7219                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7220                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7221                                         &mac_filter->mac_addr);
7222                 if (ret != I40E_SUCCESS)
7223                         goto DONE;
7224         }
7225
7226         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7227         if (ret != I40E_SUCCESS)
7228                 goto DONE;
7229
7230         /* Add the mac addr into mac list */
7231         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7232         if (f == NULL) {
7233                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7234                 ret = I40E_ERR_NO_MEMORY;
7235                 goto DONE;
7236         }
7237         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7238                         ETH_ADDR_LEN);
7239         f->mac_info.filter_type = mac_filter->filter_type;
7240         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7241         vsi->mac_num++;
7242
7243         ret = I40E_SUCCESS;
7244 DONE:
7245         rte_free(mv_f);
7246
7247         return ret;
7248 }
7249
7250 int
7251 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7252 {
7253         struct i40e_mac_filter *f;
7254         struct i40e_macvlan_filter *mv_f;
7255         int i, vlan_num;
7256         enum rte_mac_filter_type filter_type;
7257         int ret = I40E_SUCCESS;
7258
7259         /* Can't find it, return an error */
7260         f = i40e_find_mac_filter(vsi, addr);
7261         if (f == NULL)
7262                 return I40E_ERR_PARAM;
7263
7264         vlan_num = vsi->vlan_num;
7265         filter_type = f->mac_info.filter_type;
7266         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7267                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7268                 if (vlan_num == 0) {
7269                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7270                         return I40E_ERR_PARAM;
7271                 }
7272         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7273                         filter_type == RTE_MAC_HASH_MATCH)
7274                 vlan_num = 1;
7275
7276         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7277         if (mv_f == NULL) {
7278                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7279                 return I40E_ERR_NO_MEMORY;
7280         }
7281
7282         for (i = 0; i < vlan_num; i++) {
7283                 mv_f[i].filter_type = filter_type;
7284                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7285                                 ETH_ADDR_LEN);
7286         }
7287         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7288                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7289                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7290                 if (ret != I40E_SUCCESS)
7291                         goto DONE;
7292         }
7293
7294         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7295         if (ret != I40E_SUCCESS)
7296                 goto DONE;
7297
7298         /* Remove the mac addr into mac list */
7299         TAILQ_REMOVE(&vsi->mac_list, f, next);
7300         rte_free(f);
7301         vsi->mac_num--;
7302
7303         ret = I40E_SUCCESS;
7304 DONE:
7305         rte_free(mv_f);
7306         return ret;
7307 }
7308
7309 /* Configure hash enable flags for RSS */
7310 uint64_t
7311 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7312 {
7313         uint64_t hena = 0;
7314         int i;
7315
7316         if (!flags)
7317                 return hena;
7318
7319         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7320                 if (flags & (1ULL << i))
7321                         hena |= adapter->pctypes_tbl[i];
7322         }
7323
7324         return hena;
7325 }
7326
7327 /* Parse the hash enable flags */
7328 uint64_t
7329 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7330 {
7331         uint64_t rss_hf = 0;
7332
7333         if (!flags)
7334                 return rss_hf;
7335         int i;
7336
7337         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7338                 if (flags & adapter->pctypes_tbl[i])
7339                         rss_hf |= (1ULL << i);
7340         }
7341         return rss_hf;
7342 }
7343
7344 /* Disable RSS */
7345 static void
7346 i40e_pf_disable_rss(struct i40e_pf *pf)
7347 {
7348         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7349
7350         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7351         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7352         I40E_WRITE_FLUSH(hw);
7353 }
7354
7355 int
7356 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7357 {
7358         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7359         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7360         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7361                            I40E_VFQF_HKEY_MAX_INDEX :
7362                            I40E_PFQF_HKEY_MAX_INDEX;
7363         int ret = 0;
7364
7365         if (!key || key_len == 0) {
7366                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7367                 return 0;
7368         } else if (key_len != (key_idx + 1) *
7369                 sizeof(uint32_t)) {
7370                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7371                 return -EINVAL;
7372         }
7373
7374         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7375                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7376                         (struct i40e_aqc_get_set_rss_key_data *)key;
7377
7378                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7379                 if (ret)
7380                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7381         } else {
7382                 uint32_t *hash_key = (uint32_t *)key;
7383                 uint16_t i;
7384
7385                 if (vsi->type == I40E_VSI_SRIOV) {
7386                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7387                                 I40E_WRITE_REG(
7388                                         hw,
7389                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7390                                         hash_key[i]);
7391
7392                 } else {
7393                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7394                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7395                                                hash_key[i]);
7396                 }
7397                 I40E_WRITE_FLUSH(hw);
7398         }
7399
7400         return ret;
7401 }
7402
7403 static int
7404 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7405 {
7406         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7407         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7408         uint32_t reg;
7409         int ret;
7410
7411         if (!key || !key_len)
7412                 return 0;
7413
7414         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7415                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7416                         (struct i40e_aqc_get_set_rss_key_data *)key);
7417                 if (ret) {
7418                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7419                         return ret;
7420                 }
7421         } else {
7422                 uint32_t *key_dw = (uint32_t *)key;
7423                 uint16_t i;
7424
7425                 if (vsi->type == I40E_VSI_SRIOV) {
7426                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7427                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7428                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7429                         }
7430                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7431                                    sizeof(uint32_t);
7432                 } else {
7433                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7434                                 reg = I40E_PFQF_HKEY(i);
7435                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7436                         }
7437                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7438                                    sizeof(uint32_t);
7439                 }
7440         }
7441         return 0;
7442 }
7443
7444 static int
7445 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7446 {
7447         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7448         uint64_t hena;
7449         int ret;
7450
7451         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7452                                rss_conf->rss_key_len);
7453         if (ret)
7454                 return ret;
7455
7456         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7457         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7458         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7459         I40E_WRITE_FLUSH(hw);
7460
7461         return 0;
7462 }
7463
7464 static int
7465 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7466                          struct rte_eth_rss_conf *rss_conf)
7467 {
7468         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7469         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7470         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7471         uint64_t hena;
7472
7473         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7474         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7475
7476         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7477                 if (rss_hf != 0) /* Enable RSS */
7478                         return -EINVAL;
7479                 return 0; /* Nothing to do */
7480         }
7481         /* RSS enabled */
7482         if (rss_hf == 0) /* Disable RSS */
7483                 return -EINVAL;
7484
7485         return i40e_hw_rss_hash_set(pf, rss_conf);
7486 }
7487
7488 static int
7489 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7490                            struct rte_eth_rss_conf *rss_conf)
7491 {
7492         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7493         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7494         uint64_t hena;
7495         int ret;
7496
7497         if (!rss_conf)
7498                 return -EINVAL;
7499
7500         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7501                          &rss_conf->rss_key_len);
7502         if (ret)
7503                 return ret;
7504
7505         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7506         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7507         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7508
7509         return 0;
7510 }
7511
7512 static int
7513 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7514 {
7515         switch (filter_type) {
7516         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7517                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7518                 break;
7519         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7520                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7521                 break;
7522         case RTE_TUNNEL_FILTER_IMAC_TENID:
7523                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7524                 break;
7525         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7526                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7527                 break;
7528         case ETH_TUNNEL_FILTER_IMAC:
7529                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7530                 break;
7531         case ETH_TUNNEL_FILTER_OIP:
7532                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7533                 break;
7534         case ETH_TUNNEL_FILTER_IIP:
7535                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7536                 break;
7537         default:
7538                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7539                 return -EINVAL;
7540         }
7541
7542         return 0;
7543 }
7544
7545 /* Convert tunnel filter structure */
7546 static int
7547 i40e_tunnel_filter_convert(
7548         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7549         struct i40e_tunnel_filter *tunnel_filter)
7550 {
7551         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7552                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7553         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7554                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7555         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7556         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7557              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7558             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7559                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7560         else
7561                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7562         tunnel_filter->input.flags = cld_filter->element.flags;
7563         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7564         tunnel_filter->queue = cld_filter->element.queue_number;
7565         rte_memcpy(tunnel_filter->input.general_fields,
7566                    cld_filter->general_fields,
7567                    sizeof(cld_filter->general_fields));
7568
7569         return 0;
7570 }
7571
7572 /* Check if there exists the tunnel filter */
7573 struct i40e_tunnel_filter *
7574 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7575                              const struct i40e_tunnel_filter_input *input)
7576 {
7577         int ret;
7578
7579         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7580         if (ret < 0)
7581                 return NULL;
7582
7583         return tunnel_rule->hash_map[ret];
7584 }
7585
7586 /* Add a tunnel filter into the SW list */
7587 static int
7588 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7589                              struct i40e_tunnel_filter *tunnel_filter)
7590 {
7591         struct i40e_tunnel_rule *rule = &pf->tunnel;
7592         int ret;
7593
7594         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7595         if (ret < 0) {
7596                 PMD_DRV_LOG(ERR,
7597                             "Failed to insert tunnel filter to hash table %d!",
7598                             ret);
7599                 return ret;
7600         }
7601         rule->hash_map[ret] = tunnel_filter;
7602
7603         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7604
7605         return 0;
7606 }
7607
7608 /* Delete a tunnel filter from the SW list */
7609 int
7610 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7611                           struct i40e_tunnel_filter_input *input)
7612 {
7613         struct i40e_tunnel_rule *rule = &pf->tunnel;
7614         struct i40e_tunnel_filter *tunnel_filter;
7615         int ret;
7616
7617         ret = rte_hash_del_key(rule->hash_table, input);
7618         if (ret < 0) {
7619                 PMD_DRV_LOG(ERR,
7620                             "Failed to delete tunnel filter to hash table %d!",
7621                             ret);
7622                 return ret;
7623         }
7624         tunnel_filter = rule->hash_map[ret];
7625         rule->hash_map[ret] = NULL;
7626
7627         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7628         rte_free(tunnel_filter);
7629
7630         return 0;
7631 }
7632
7633 int
7634 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7635                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7636                         uint8_t add)
7637 {
7638         uint16_t ip_type;
7639         uint32_t ipv4_addr, ipv4_addr_le;
7640         uint8_t i, tun_type = 0;
7641         /* internal varialbe to convert ipv6 byte order */
7642         uint32_t convert_ipv6[4];
7643         int val, ret = 0;
7644         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7645         struct i40e_vsi *vsi = pf->main_vsi;
7646         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7647         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7648         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7649         struct i40e_tunnel_filter *tunnel, *node;
7650         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7651
7652         cld_filter = rte_zmalloc("tunnel_filter",
7653                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7654         0);
7655
7656         if (NULL == cld_filter) {
7657                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7658                 return -ENOMEM;
7659         }
7660         pfilter = cld_filter;
7661
7662         ether_addr_copy(&tunnel_filter->outer_mac,
7663                         (struct ether_addr *)&pfilter->element.outer_mac);
7664         ether_addr_copy(&tunnel_filter->inner_mac,
7665                         (struct ether_addr *)&pfilter->element.inner_mac);
7666
7667         pfilter->element.inner_vlan =
7668                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7669         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7670                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7671                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7672                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7673                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7674                                 &ipv4_addr_le,
7675                                 sizeof(pfilter->element.ipaddr.v4.data));
7676         } else {
7677                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7678                 for (i = 0; i < 4; i++) {
7679                         convert_ipv6[i] =
7680                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7681                 }
7682                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7683                            &convert_ipv6,
7684                            sizeof(pfilter->element.ipaddr.v6.data));
7685         }
7686
7687         /* check tunneled type */
7688         switch (tunnel_filter->tunnel_type) {
7689         case RTE_TUNNEL_TYPE_VXLAN:
7690                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7691                 break;
7692         case RTE_TUNNEL_TYPE_NVGRE:
7693                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7694                 break;
7695         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7696                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7697                 break;
7698         default:
7699                 /* Other tunnel types is not supported. */
7700                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7701                 rte_free(cld_filter);
7702                 return -EINVAL;
7703         }
7704
7705         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7706                                        &pfilter->element.flags);
7707         if (val < 0) {
7708                 rte_free(cld_filter);
7709                 return -EINVAL;
7710         }
7711
7712         pfilter->element.flags |= rte_cpu_to_le_16(
7713                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7714                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7715         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7716         pfilter->element.queue_number =
7717                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7718
7719         /* Check if there is the filter in SW list */
7720         memset(&check_filter, 0, sizeof(check_filter));
7721         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7722         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7723         if (add && node) {
7724                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7725                 rte_free(cld_filter);
7726                 return -EINVAL;
7727         }
7728
7729         if (!add && !node) {
7730                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7731                 rte_free(cld_filter);
7732                 return -EINVAL;
7733         }
7734
7735         if (add) {
7736                 ret = i40e_aq_add_cloud_filters(hw,
7737                                         vsi->seid, &cld_filter->element, 1);
7738                 if (ret < 0) {
7739                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7740                         rte_free(cld_filter);
7741                         return -ENOTSUP;
7742                 }
7743                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7744                 if (tunnel == NULL) {
7745                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7746                         rte_free(cld_filter);
7747                         return -ENOMEM;
7748                 }
7749
7750                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7751                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7752                 if (ret < 0)
7753                         rte_free(tunnel);
7754         } else {
7755                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7756                                                    &cld_filter->element, 1);
7757                 if (ret < 0) {
7758                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7759                         rte_free(cld_filter);
7760                         return -ENOTSUP;
7761                 }
7762                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7763         }
7764
7765         rte_free(cld_filter);
7766         return ret;
7767 }
7768
7769 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7770 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7771 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7772 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7773 #define I40E_TR_GRE_KEY_MASK                    0x400
7774 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7775 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7776
7777 static enum
7778 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7779 {
7780         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7781         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7782         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7783         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7784         enum i40e_status_code status = I40E_SUCCESS;
7785
7786         if (pf->support_multi_driver) {
7787                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7788                 return I40E_NOT_SUPPORTED;
7789         }
7790
7791         memset(&filter_replace, 0,
7792                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7793         memset(&filter_replace_buf, 0,
7794                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7795
7796         /* create L1 filter */
7797         filter_replace.old_filter_type =
7798                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7799         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7800         filter_replace.tr_bit = 0;
7801
7802         /* Prepare the buffer, 3 entries */
7803         filter_replace_buf.data[0] =
7804                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7805         filter_replace_buf.data[0] |=
7806                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7807         filter_replace_buf.data[2] = 0xFF;
7808         filter_replace_buf.data[3] = 0xFF;
7809         filter_replace_buf.data[4] =
7810                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7811         filter_replace_buf.data[4] |=
7812                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7813         filter_replace_buf.data[7] = 0xF0;
7814         filter_replace_buf.data[8]
7815                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7816         filter_replace_buf.data[8] |=
7817                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7818         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7819                 I40E_TR_GENEVE_KEY_MASK |
7820                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7821         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7822                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7823                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7824
7825         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7826                                                &filter_replace_buf);
7827         if (!status && (filter_replace.old_filter_type !=
7828                         filter_replace.new_filter_type))
7829                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7830                             " original: 0x%x, new: 0x%x",
7831                             dev->device->name,
7832                             filter_replace.old_filter_type,
7833                             filter_replace.new_filter_type);
7834
7835         return status;
7836 }
7837
7838 static enum
7839 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7840 {
7841         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7842         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7843         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7844         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7845         enum i40e_status_code status = I40E_SUCCESS;
7846
7847         if (pf->support_multi_driver) {
7848                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7849                 return I40E_NOT_SUPPORTED;
7850         }
7851
7852         /* For MPLSoUDP */
7853         memset(&filter_replace, 0,
7854                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7855         memset(&filter_replace_buf, 0,
7856                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7857         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7858                 I40E_AQC_MIRROR_CLOUD_FILTER;
7859         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7860         filter_replace.new_filter_type =
7861                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7862         /* Prepare the buffer, 2 entries */
7863         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7864         filter_replace_buf.data[0] |=
7865                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7866         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7867         filter_replace_buf.data[4] |=
7868                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7869         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7870                                                &filter_replace_buf);
7871         if (status < 0)
7872                 return status;
7873         if (filter_replace.old_filter_type !=
7874             filter_replace.new_filter_type)
7875                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7876                             " original: 0x%x, new: 0x%x",
7877                             dev->device->name,
7878                             filter_replace.old_filter_type,
7879                             filter_replace.new_filter_type);
7880
7881         /* For MPLSoGRE */
7882         memset(&filter_replace, 0,
7883                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7884         memset(&filter_replace_buf, 0,
7885                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7886
7887         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7888                 I40E_AQC_MIRROR_CLOUD_FILTER;
7889         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7890         filter_replace.new_filter_type =
7891                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7892         /* Prepare the buffer, 2 entries */
7893         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7894         filter_replace_buf.data[0] |=
7895                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7896         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7897         filter_replace_buf.data[4] |=
7898                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7899
7900         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7901                                                &filter_replace_buf);
7902         if (!status && (filter_replace.old_filter_type !=
7903                         filter_replace.new_filter_type))
7904                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7905                             " original: 0x%x, new: 0x%x",
7906                             dev->device->name,
7907                             filter_replace.old_filter_type,
7908                             filter_replace.new_filter_type);
7909
7910         return status;
7911 }
7912
7913 static enum i40e_status_code
7914 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7915 {
7916         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7917         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7918         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7919         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7920         enum i40e_status_code status = I40E_SUCCESS;
7921
7922         if (pf->support_multi_driver) {
7923                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7924                 return I40E_NOT_SUPPORTED;
7925         }
7926
7927         /* For GTP-C */
7928         memset(&filter_replace, 0,
7929                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7930         memset(&filter_replace_buf, 0,
7931                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7932         /* create L1 filter */
7933         filter_replace.old_filter_type =
7934                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7935         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7936         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7937                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7938         /* Prepare the buffer, 2 entries */
7939         filter_replace_buf.data[0] =
7940                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7941         filter_replace_buf.data[0] |=
7942                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7943         filter_replace_buf.data[2] = 0xFF;
7944         filter_replace_buf.data[3] = 0xFF;
7945         filter_replace_buf.data[4] =
7946                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7947         filter_replace_buf.data[4] |=
7948                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7949         filter_replace_buf.data[6] = 0xFF;
7950         filter_replace_buf.data[7] = 0xFF;
7951         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7952                                                &filter_replace_buf);
7953         if (status < 0)
7954                 return status;
7955         if (filter_replace.old_filter_type !=
7956             filter_replace.new_filter_type)
7957                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7958                             " original: 0x%x, new: 0x%x",
7959                             dev->device->name,
7960                             filter_replace.old_filter_type,
7961                             filter_replace.new_filter_type);
7962
7963         /* for GTP-U */
7964         memset(&filter_replace, 0,
7965                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7966         memset(&filter_replace_buf, 0,
7967                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7968         /* create L1 filter */
7969         filter_replace.old_filter_type =
7970                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7971         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7972         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7973                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7974         /* Prepare the buffer, 2 entries */
7975         filter_replace_buf.data[0] =
7976                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7977         filter_replace_buf.data[0] |=
7978                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7979         filter_replace_buf.data[2] = 0xFF;
7980         filter_replace_buf.data[3] = 0xFF;
7981         filter_replace_buf.data[4] =
7982                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7983         filter_replace_buf.data[4] |=
7984                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7985         filter_replace_buf.data[6] = 0xFF;
7986         filter_replace_buf.data[7] = 0xFF;
7987
7988         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7989                                                &filter_replace_buf);
7990         if (!status && (filter_replace.old_filter_type !=
7991                         filter_replace.new_filter_type))
7992                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7993                             " original: 0x%x, new: 0x%x",
7994                             dev->device->name,
7995                             filter_replace.old_filter_type,
7996                             filter_replace.new_filter_type);
7997
7998         return status;
7999 }
8000
8001 static enum
8002 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8003 {
8004         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8005         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8006         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8007         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8008         enum i40e_status_code status = I40E_SUCCESS;
8009
8010         if (pf->support_multi_driver) {
8011                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8012                 return I40E_NOT_SUPPORTED;
8013         }
8014
8015         /* for GTP-C */
8016         memset(&filter_replace, 0,
8017                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8018         memset(&filter_replace_buf, 0,
8019                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8020         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8021         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8022         filter_replace.new_filter_type =
8023                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8024         /* Prepare the buffer, 2 entries */
8025         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8026         filter_replace_buf.data[0] |=
8027                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8028         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8029         filter_replace_buf.data[4] |=
8030                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8031         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8032                                                &filter_replace_buf);
8033         if (status < 0)
8034                 return status;
8035         if (filter_replace.old_filter_type !=
8036             filter_replace.new_filter_type)
8037                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8038                             " original: 0x%x, new: 0x%x",
8039                             dev->device->name,
8040                             filter_replace.old_filter_type,
8041                             filter_replace.new_filter_type);
8042
8043         /* for GTP-U */
8044         memset(&filter_replace, 0,
8045                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8046         memset(&filter_replace_buf, 0,
8047                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8048         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8049         filter_replace.old_filter_type =
8050                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8051         filter_replace.new_filter_type =
8052                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8053         /* Prepare the buffer, 2 entries */
8054         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8055         filter_replace_buf.data[0] |=
8056                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8057         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8058         filter_replace_buf.data[4] |=
8059                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8060
8061         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8062                                                &filter_replace_buf);
8063         if (!status && (filter_replace.old_filter_type !=
8064                         filter_replace.new_filter_type))
8065                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8066                             " original: 0x%x, new: 0x%x",
8067                             dev->device->name,
8068                             filter_replace.old_filter_type,
8069                             filter_replace.new_filter_type);
8070
8071         return status;
8072 }
8073
8074 int
8075 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8076                       struct i40e_tunnel_filter_conf *tunnel_filter,
8077                       uint8_t add)
8078 {
8079         uint16_t ip_type;
8080         uint32_t ipv4_addr, ipv4_addr_le;
8081         uint8_t i, tun_type = 0;
8082         /* internal variable to convert ipv6 byte order */
8083         uint32_t convert_ipv6[4];
8084         int val, ret = 0;
8085         struct i40e_pf_vf *vf = NULL;
8086         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8087         struct i40e_vsi *vsi;
8088         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8089         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8090         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8091         struct i40e_tunnel_filter *tunnel, *node;
8092         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8093         uint32_t teid_le;
8094         bool big_buffer = 0;
8095
8096         cld_filter = rte_zmalloc("tunnel_filter",
8097                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8098                          0);
8099
8100         if (cld_filter == NULL) {
8101                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8102                 return -ENOMEM;
8103         }
8104         pfilter = cld_filter;
8105
8106         ether_addr_copy(&tunnel_filter->outer_mac,
8107                         (struct ether_addr *)&pfilter->element.outer_mac);
8108         ether_addr_copy(&tunnel_filter->inner_mac,
8109                         (struct ether_addr *)&pfilter->element.inner_mac);
8110
8111         pfilter->element.inner_vlan =
8112                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8113         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8114                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8115                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8116                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8117                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8118                                 &ipv4_addr_le,
8119                                 sizeof(pfilter->element.ipaddr.v4.data));
8120         } else {
8121                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8122                 for (i = 0; i < 4; i++) {
8123                         convert_ipv6[i] =
8124                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8125                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8126                 }
8127                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8128                            &convert_ipv6,
8129                            sizeof(pfilter->element.ipaddr.v6.data));
8130         }
8131
8132         /* check tunneled type */
8133         switch (tunnel_filter->tunnel_type) {
8134         case I40E_TUNNEL_TYPE_VXLAN:
8135                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8136                 break;
8137         case I40E_TUNNEL_TYPE_NVGRE:
8138                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8139                 break;
8140         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8141                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8142                 break;
8143         case I40E_TUNNEL_TYPE_MPLSoUDP:
8144                 if (!pf->mpls_replace_flag) {
8145                         i40e_replace_mpls_l1_filter(pf);
8146                         i40e_replace_mpls_cloud_filter(pf);
8147                         pf->mpls_replace_flag = 1;
8148                 }
8149                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8150                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8151                         teid_le >> 4;
8152                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8153                         (teid_le & 0xF) << 12;
8154                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8155                         0x40;
8156                 big_buffer = 1;
8157                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8158                 break;
8159         case I40E_TUNNEL_TYPE_MPLSoGRE:
8160                 if (!pf->mpls_replace_flag) {
8161                         i40e_replace_mpls_l1_filter(pf);
8162                         i40e_replace_mpls_cloud_filter(pf);
8163                         pf->mpls_replace_flag = 1;
8164                 }
8165                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8166                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8167                         teid_le >> 4;
8168                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8169                         (teid_le & 0xF) << 12;
8170                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8171                         0x0;
8172                 big_buffer = 1;
8173                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8174                 break;
8175         case I40E_TUNNEL_TYPE_GTPC:
8176                 if (!pf->gtp_replace_flag) {
8177                         i40e_replace_gtp_l1_filter(pf);
8178                         i40e_replace_gtp_cloud_filter(pf);
8179                         pf->gtp_replace_flag = 1;
8180                 }
8181                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8182                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8183                         (teid_le >> 16) & 0xFFFF;
8184                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8185                         teid_le & 0xFFFF;
8186                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8187                         0x0;
8188                 big_buffer = 1;
8189                 break;
8190         case I40E_TUNNEL_TYPE_GTPU:
8191                 if (!pf->gtp_replace_flag) {
8192                         i40e_replace_gtp_l1_filter(pf);
8193                         i40e_replace_gtp_cloud_filter(pf);
8194                         pf->gtp_replace_flag = 1;
8195                 }
8196                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8197                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8198                         (teid_le >> 16) & 0xFFFF;
8199                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8200                         teid_le & 0xFFFF;
8201                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8202                         0x0;
8203                 big_buffer = 1;
8204                 break;
8205         case I40E_TUNNEL_TYPE_QINQ:
8206                 if (!pf->qinq_replace_flag) {
8207                         ret = i40e_cloud_filter_qinq_create(pf);
8208                         if (ret < 0)
8209                                 PMD_DRV_LOG(DEBUG,
8210                                             "QinQ tunnel filter already created.");
8211                         pf->qinq_replace_flag = 1;
8212                 }
8213                 /*      Add in the General fields the values of
8214                  *      the Outer and Inner VLAN
8215                  *      Big Buffer should be set, see changes in
8216                  *      i40e_aq_add_cloud_filters
8217                  */
8218                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8219                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8220                 big_buffer = 1;
8221                 break;
8222         default:
8223                 /* Other tunnel types is not supported. */
8224                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8225                 rte_free(cld_filter);
8226                 return -EINVAL;
8227         }
8228
8229         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8230                 pfilter->element.flags =
8231                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8232         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8233                 pfilter->element.flags =
8234                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8235         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8236                 pfilter->element.flags =
8237                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8238         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8239                 pfilter->element.flags =
8240                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8241         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8242                 pfilter->element.flags |=
8243                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8244         else {
8245                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8246                                                 &pfilter->element.flags);
8247                 if (val < 0) {
8248                         rte_free(cld_filter);
8249                         return -EINVAL;
8250                 }
8251         }
8252
8253         pfilter->element.flags |= rte_cpu_to_le_16(
8254                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8255                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8256         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8257         pfilter->element.queue_number =
8258                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8259
8260         if (!tunnel_filter->is_to_vf)
8261                 vsi = pf->main_vsi;
8262         else {
8263                 if (tunnel_filter->vf_id >= pf->vf_num) {
8264                         PMD_DRV_LOG(ERR, "Invalid argument.");
8265                         rte_free(cld_filter);
8266                         return -EINVAL;
8267                 }
8268                 vf = &pf->vfs[tunnel_filter->vf_id];
8269                 vsi = vf->vsi;
8270         }
8271
8272         /* Check if there is the filter in SW list */
8273         memset(&check_filter, 0, sizeof(check_filter));
8274         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8275         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8276         check_filter.vf_id = tunnel_filter->vf_id;
8277         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8278         if (add && node) {
8279                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8280                 rte_free(cld_filter);
8281                 return -EINVAL;
8282         }
8283
8284         if (!add && !node) {
8285                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8286                 rte_free(cld_filter);
8287                 return -EINVAL;
8288         }
8289
8290         if (add) {
8291                 if (big_buffer)
8292                         ret = i40e_aq_add_cloud_filters_bb(hw,
8293                                                    vsi->seid, cld_filter, 1);
8294                 else
8295                         ret = i40e_aq_add_cloud_filters(hw,
8296                                         vsi->seid, &cld_filter->element, 1);
8297                 if (ret < 0) {
8298                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8299                         rte_free(cld_filter);
8300                         return -ENOTSUP;
8301                 }
8302                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8303                 if (tunnel == NULL) {
8304                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8305                         rte_free(cld_filter);
8306                         return -ENOMEM;
8307                 }
8308
8309                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8310                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8311                 if (ret < 0)
8312                         rte_free(tunnel);
8313         } else {
8314                 if (big_buffer)
8315                         ret = i40e_aq_rem_cloud_filters_bb(
8316                                 hw, vsi->seid, cld_filter, 1);
8317                 else
8318                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8319                                                 &cld_filter->element, 1);
8320                 if (ret < 0) {
8321                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8322                         rte_free(cld_filter);
8323                         return -ENOTSUP;
8324                 }
8325                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8326         }
8327
8328         rte_free(cld_filter);
8329         return ret;
8330 }
8331
8332 static int
8333 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8334 {
8335         uint8_t i;
8336
8337         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8338                 if (pf->vxlan_ports[i] == port)
8339                         return i;
8340         }
8341
8342         return -1;
8343 }
8344
8345 static int
8346 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8347 {
8348         int  idx, ret;
8349         uint8_t filter_idx;
8350         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8351
8352         idx = i40e_get_vxlan_port_idx(pf, port);
8353
8354         /* Check if port already exists */
8355         if (idx >= 0) {
8356                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8357                 return -EINVAL;
8358         }
8359
8360         /* Now check if there is space to add the new port */
8361         idx = i40e_get_vxlan_port_idx(pf, 0);
8362         if (idx < 0) {
8363                 PMD_DRV_LOG(ERR,
8364                         "Maximum number of UDP ports reached, not adding port %d",
8365                         port);
8366                 return -ENOSPC;
8367         }
8368
8369         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8370                                         &filter_idx, NULL);
8371         if (ret < 0) {
8372                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8373                 return -1;
8374         }
8375
8376         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8377                          port,  filter_idx);
8378
8379         /* New port: add it and mark its index in the bitmap */
8380         pf->vxlan_ports[idx] = port;
8381         pf->vxlan_bitmap |= (1 << idx);
8382
8383         if (!(pf->flags & I40E_FLAG_VXLAN))
8384                 pf->flags |= I40E_FLAG_VXLAN;
8385
8386         return 0;
8387 }
8388
8389 static int
8390 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8391 {
8392         int idx;
8393         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8394
8395         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8396                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8397                 return -EINVAL;
8398         }
8399
8400         idx = i40e_get_vxlan_port_idx(pf, port);
8401
8402         if (idx < 0) {
8403                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8404                 return -EINVAL;
8405         }
8406
8407         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8408                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8409                 return -1;
8410         }
8411
8412         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8413                         port, idx);
8414
8415         pf->vxlan_ports[idx] = 0;
8416         pf->vxlan_bitmap &= ~(1 << idx);
8417
8418         if (!pf->vxlan_bitmap)
8419                 pf->flags &= ~I40E_FLAG_VXLAN;
8420
8421         return 0;
8422 }
8423
8424 /* Add UDP tunneling port */
8425 static int
8426 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8427                              struct rte_eth_udp_tunnel *udp_tunnel)
8428 {
8429         int ret = 0;
8430         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8431
8432         if (udp_tunnel == NULL)
8433                 return -EINVAL;
8434
8435         switch (udp_tunnel->prot_type) {
8436         case RTE_TUNNEL_TYPE_VXLAN:
8437                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8438                 break;
8439
8440         case RTE_TUNNEL_TYPE_GENEVE:
8441         case RTE_TUNNEL_TYPE_TEREDO:
8442                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8443                 ret = -1;
8444                 break;
8445
8446         default:
8447                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8448                 ret = -1;
8449                 break;
8450         }
8451
8452         return ret;
8453 }
8454
8455 /* Remove UDP tunneling port */
8456 static int
8457 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8458                              struct rte_eth_udp_tunnel *udp_tunnel)
8459 {
8460         int ret = 0;
8461         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8462
8463         if (udp_tunnel == NULL)
8464                 return -EINVAL;
8465
8466         switch (udp_tunnel->prot_type) {
8467         case RTE_TUNNEL_TYPE_VXLAN:
8468                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8469                 break;
8470         case RTE_TUNNEL_TYPE_GENEVE:
8471         case RTE_TUNNEL_TYPE_TEREDO:
8472                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8473                 ret = -1;
8474                 break;
8475         default:
8476                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8477                 ret = -1;
8478                 break;
8479         }
8480
8481         return ret;
8482 }
8483
8484 /* Calculate the maximum number of contiguous PF queues that are configured */
8485 static int
8486 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8487 {
8488         struct rte_eth_dev_data *data = pf->dev_data;
8489         int i, num;
8490         struct i40e_rx_queue *rxq;
8491
8492         num = 0;
8493         for (i = 0; i < pf->lan_nb_qps; i++) {
8494                 rxq = data->rx_queues[i];
8495                 if (rxq && rxq->q_set)
8496                         num++;
8497                 else
8498                         break;
8499         }
8500
8501         return num;
8502 }
8503
8504 /* Configure RSS */
8505 static int
8506 i40e_pf_config_rss(struct i40e_pf *pf)
8507 {
8508         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8509         struct rte_eth_rss_conf rss_conf;
8510         uint32_t i, lut = 0;
8511         uint16_t j, num;
8512
8513         /*
8514          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8515          * It's necessary to calculate the actual PF queues that are configured.
8516          */
8517         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8518                 num = i40e_pf_calc_configured_queues_num(pf);
8519         else
8520                 num = pf->dev_data->nb_rx_queues;
8521
8522         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8523         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8524                         num);
8525
8526         if (num == 0) {
8527                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8528                 return -ENOTSUP;
8529         }
8530
8531         if (pf->adapter->rss_reta_updated == 0) {
8532                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8533                         if (j == num)
8534                                 j = 0;
8535                         lut = (lut << 8) | (j & ((0x1 <<
8536                                 hw->func_caps.rss_table_entry_width) - 1));
8537                         if ((i & 3) == 3)
8538                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8539                                                rte_bswap32(lut));
8540                 }
8541         }
8542
8543         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8544         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8545                 i40e_pf_disable_rss(pf);
8546                 return 0;
8547         }
8548         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8549                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8550                 /* Random default keys */
8551                 static uint32_t rss_key_default[] = {0x6b793944,
8552                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8553                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8554                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8555
8556                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8557                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8558                                                         sizeof(uint32_t);
8559         }
8560
8561         return i40e_hw_rss_hash_set(pf, &rss_conf);
8562 }
8563
8564 static int
8565 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8566                                struct rte_eth_tunnel_filter_conf *filter)
8567 {
8568         if (pf == NULL || filter == NULL) {
8569                 PMD_DRV_LOG(ERR, "Invalid parameter");
8570                 return -EINVAL;
8571         }
8572
8573         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8574                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8575                 return -EINVAL;
8576         }
8577
8578         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8579                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8580                 return -EINVAL;
8581         }
8582
8583         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8584                 (is_zero_ether_addr(&filter->outer_mac))) {
8585                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8586                 return -EINVAL;
8587         }
8588
8589         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8590                 (is_zero_ether_addr(&filter->inner_mac))) {
8591                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8592                 return -EINVAL;
8593         }
8594
8595         return 0;
8596 }
8597
8598 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8599 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8600 static int
8601 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8602 {
8603         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8604         uint32_t val, reg;
8605         int ret = -EINVAL;
8606
8607         if (pf->support_multi_driver) {
8608                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8609                 return -ENOTSUP;
8610         }
8611
8612         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8613         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8614
8615         if (len == 3) {
8616                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8617         } else if (len == 4) {
8618                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8619         } else {
8620                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8621                 return ret;
8622         }
8623
8624         if (reg != val) {
8625                 ret = i40e_aq_debug_write_global_register(hw,
8626                                                    I40E_GL_PRS_FVBM(2),
8627                                                    reg, NULL);
8628                 if (ret != 0)
8629                         return ret;
8630                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8631                             "with value 0x%08x",
8632                             I40E_GL_PRS_FVBM(2), reg);
8633         } else {
8634                 ret = 0;
8635         }
8636         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8637                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8638
8639         return ret;
8640 }
8641
8642 static int
8643 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8644 {
8645         int ret = -EINVAL;
8646
8647         if (!hw || !cfg)
8648                 return -EINVAL;
8649
8650         switch (cfg->cfg_type) {
8651         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8652                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8653                 break;
8654         default:
8655                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8656                 break;
8657         }
8658
8659         return ret;
8660 }
8661
8662 static int
8663 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8664                                enum rte_filter_op filter_op,
8665                                void *arg)
8666 {
8667         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8668         int ret = I40E_ERR_PARAM;
8669
8670         switch (filter_op) {
8671         case RTE_ETH_FILTER_SET:
8672                 ret = i40e_dev_global_config_set(hw,
8673                         (struct rte_eth_global_cfg *)arg);
8674                 break;
8675         default:
8676                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8677                 break;
8678         }
8679
8680         return ret;
8681 }
8682
8683 static int
8684 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8685                           enum rte_filter_op filter_op,
8686                           void *arg)
8687 {
8688         struct rte_eth_tunnel_filter_conf *filter;
8689         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8690         int ret = I40E_SUCCESS;
8691
8692         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8693
8694         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8695                 return I40E_ERR_PARAM;
8696
8697         switch (filter_op) {
8698         case RTE_ETH_FILTER_NOP:
8699                 if (!(pf->flags & I40E_FLAG_VXLAN))
8700                         ret = I40E_NOT_SUPPORTED;
8701                 break;
8702         case RTE_ETH_FILTER_ADD:
8703                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8704                 break;
8705         case RTE_ETH_FILTER_DELETE:
8706                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8707                 break;
8708         default:
8709                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8710                 ret = I40E_ERR_PARAM;
8711                 break;
8712         }
8713
8714         return ret;
8715 }
8716
8717 static int
8718 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8719 {
8720         int ret = 0;
8721         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8722
8723         /* RSS setup */
8724         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8725                 ret = i40e_pf_config_rss(pf);
8726         else
8727                 i40e_pf_disable_rss(pf);
8728
8729         return ret;
8730 }
8731
8732 /* Get the symmetric hash enable configurations per port */
8733 static void
8734 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8735 {
8736         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8737
8738         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8739 }
8740
8741 /* Set the symmetric hash enable configurations per port */
8742 static void
8743 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8744 {
8745         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8746
8747         if (enable > 0) {
8748                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8749                         PMD_DRV_LOG(INFO,
8750                                 "Symmetric hash has already been enabled");
8751                         return;
8752                 }
8753                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8754         } else {
8755                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8756                         PMD_DRV_LOG(INFO,
8757                                 "Symmetric hash has already been disabled");
8758                         return;
8759                 }
8760                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8761         }
8762         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8763         I40E_WRITE_FLUSH(hw);
8764 }
8765
8766 /*
8767  * Get global configurations of hash function type and symmetric hash enable
8768  * per flow type (pctype). Note that global configuration means it affects all
8769  * the ports on the same NIC.
8770  */
8771 static int
8772 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8773                                    struct rte_eth_hash_global_conf *g_cfg)
8774 {
8775         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8776         uint32_t reg;
8777         uint16_t i, j;
8778
8779         memset(g_cfg, 0, sizeof(*g_cfg));
8780         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8781         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8782                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8783         else
8784                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8785         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8786                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8787
8788         /*
8789          * As i40e supports less than 64 flow types, only first 64 bits need to
8790          * be checked.
8791          */
8792         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8793                 g_cfg->valid_bit_mask[i] = 0ULL;
8794                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8795         }
8796
8797         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8798
8799         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8800                 if (!adapter->pctypes_tbl[i])
8801                         continue;
8802                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8803                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8804                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8805                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8806                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8807                                         g_cfg->sym_hash_enable_mask[0] |=
8808                                                                 (1ULL << i);
8809                                 }
8810                         }
8811                 }
8812         }
8813
8814         return 0;
8815 }
8816
8817 static int
8818 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8819                               const struct rte_eth_hash_global_conf *g_cfg)
8820 {
8821         uint32_t i;
8822         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8823
8824         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8825                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8826                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8827                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8828                                                 g_cfg->hash_func);
8829                 return -EINVAL;
8830         }
8831
8832         /*
8833          * As i40e supports less than 64 flow types, only first 64 bits need to
8834          * be checked.
8835          */
8836         mask0 = g_cfg->valid_bit_mask[0];
8837         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8838                 if (i == 0) {
8839                         /* Check if any unsupported flow type configured */
8840                         if ((mask0 | i40e_mask) ^ i40e_mask)
8841                                 goto mask_err;
8842                 } else {
8843                         if (g_cfg->valid_bit_mask[i])
8844                                 goto mask_err;
8845                 }
8846         }
8847
8848         return 0;
8849
8850 mask_err:
8851         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8852
8853         return -EINVAL;
8854 }
8855
8856 /*
8857  * Set global configurations of hash function type and symmetric hash enable
8858  * per flow type (pctype). Note any modifying global configuration will affect
8859  * all the ports on the same NIC.
8860  */
8861 static int
8862 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8863                                    struct rte_eth_hash_global_conf *g_cfg)
8864 {
8865         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8866         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8867         int ret;
8868         uint16_t i, j;
8869         uint32_t reg;
8870         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8871
8872         if (pf->support_multi_driver) {
8873                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8874                 return -ENOTSUP;
8875         }
8876
8877         /* Check the input parameters */
8878         ret = i40e_hash_global_config_check(adapter, g_cfg);
8879         if (ret < 0)
8880                 return ret;
8881
8882         /*
8883          * As i40e supports less than 64 flow types, only first 64 bits need to
8884          * be configured.
8885          */
8886         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8887                 if (mask0 & (1UL << i)) {
8888                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8889                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8890
8891                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8892                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8893                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8894                                         i40e_write_global_rx_ctl(hw,
8895                                                           I40E_GLQF_HSYM(j),
8896                                                           reg);
8897                         }
8898                 }
8899         }
8900
8901         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8902         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8903                 /* Toeplitz */
8904                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8905                         PMD_DRV_LOG(DEBUG,
8906                                 "Hash function already set to Toeplitz");
8907                         goto out;
8908                 }
8909                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8910         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8911                 /* Simple XOR */
8912                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8913                         PMD_DRV_LOG(DEBUG,
8914                                 "Hash function already set to Simple XOR");
8915                         goto out;
8916                 }
8917                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8918         } else
8919                 /* Use the default, and keep it as it is */
8920                 goto out;
8921
8922         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8923
8924 out:
8925         I40E_WRITE_FLUSH(hw);
8926
8927         return 0;
8928 }
8929
8930 /**
8931  * Valid input sets for hash and flow director filters per PCTYPE
8932  */
8933 static uint64_t
8934 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8935                 enum rte_filter_type filter)
8936 {
8937         uint64_t valid;
8938
8939         static const uint64_t valid_hash_inset_table[] = {
8940                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8941                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8942                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8943                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8944                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8945                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8946                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8947                         I40E_INSET_FLEX_PAYLOAD,
8948                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8949                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8950                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8951                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8952                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8953                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8954                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8955                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8956                         I40E_INSET_FLEX_PAYLOAD,
8957                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8958                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8959                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8960                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8961                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8962                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8963                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8964                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8965                         I40E_INSET_FLEX_PAYLOAD,
8966                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8967                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8968                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8969                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8970                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8971                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8972                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8973                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8974                         I40E_INSET_FLEX_PAYLOAD,
8975                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8976                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8977                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8978                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8979                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8980                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8981                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8982                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8983                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8984                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8985                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8986                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8987                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8988                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8989                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8990                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8991                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8992                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8993                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8994                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8995                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8996                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8997                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8998                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8999                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9000                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9001                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9002                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9003                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9004                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9005                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9006                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9007                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9008                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9009                         I40E_INSET_FLEX_PAYLOAD,
9010                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9011                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9012                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9013                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9014                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9015                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9016                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9017                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9018                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9019                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9020                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9021                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9022                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9023                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9024                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9025                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9026                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9027                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9028                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9029                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9030                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9031                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9032                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9033                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9034                         I40E_INSET_FLEX_PAYLOAD,
9035                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9036                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9037                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9038                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9039                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9040                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9041                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9042                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9043                         I40E_INSET_FLEX_PAYLOAD,
9044                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9045                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9046                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9047                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9048                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9049                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9050                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9051                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9052                         I40E_INSET_FLEX_PAYLOAD,
9053                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9054                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9055                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9056                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9057                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9058                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9059                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9060                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9061                         I40E_INSET_FLEX_PAYLOAD,
9062                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9063                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9064                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9065                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9066                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9067                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9068                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9069                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9070                         I40E_INSET_FLEX_PAYLOAD,
9071                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9072                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9073                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9074                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9075                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9076                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9077                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9078                         I40E_INSET_FLEX_PAYLOAD,
9079                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9080                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9081                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9082                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9083                         I40E_INSET_FLEX_PAYLOAD,
9084         };
9085
9086         /**
9087          * Flow director supports only fields defined in
9088          * union rte_eth_fdir_flow.
9089          */
9090         static const uint64_t valid_fdir_inset_table[] = {
9091                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9092                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9093                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9094                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9095                 I40E_INSET_IPV4_TTL,
9096                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9097                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9098                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9099                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9100                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9101                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9102                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9103                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9104                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9105                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9106                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9107                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9108                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9109                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9110                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9111                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9112                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9113                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9114                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9115                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9116                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9117                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9118                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9119                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9120                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9121                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9122                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9123                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9124                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9125                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9126                 I40E_INSET_SCTP_VT,
9127                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9128                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9129                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9130                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9131                 I40E_INSET_IPV4_TTL,
9132                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9133                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9134                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9135                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9136                 I40E_INSET_IPV6_HOP_LIMIT,
9137                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9138                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9139                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9140                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9141                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9142                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9143                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9144                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9145                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9146                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9147                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9148                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9149                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9150                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9151                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9152                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9153                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9154                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9155                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9156                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9157                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9158                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9159                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9160                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9161                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9162                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9163                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9164                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9165                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9166                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9167                 I40E_INSET_SCTP_VT,
9168                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9169                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9170                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9171                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9172                 I40E_INSET_IPV6_HOP_LIMIT,
9173                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9174                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9175                 I40E_INSET_LAST_ETHER_TYPE,
9176         };
9177
9178         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9179                 return 0;
9180         if (filter == RTE_ETH_FILTER_HASH)
9181                 valid = valid_hash_inset_table[pctype];
9182         else
9183                 valid = valid_fdir_inset_table[pctype];
9184
9185         return valid;
9186 }
9187
9188 /**
9189  * Validate if the input set is allowed for a specific PCTYPE
9190  */
9191 int
9192 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9193                 enum rte_filter_type filter, uint64_t inset)
9194 {
9195         uint64_t valid;
9196
9197         valid = i40e_get_valid_input_set(pctype, filter);
9198         if (inset & (~valid))
9199                 return -EINVAL;
9200
9201         return 0;
9202 }
9203
9204 /* default input set fields combination per pctype */
9205 uint64_t
9206 i40e_get_default_input_set(uint16_t pctype)
9207 {
9208         static const uint64_t default_inset_table[] = {
9209                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9210                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9211                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9212                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9213                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9214                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9215                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9216                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9217                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9218                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9219                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9220                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9221                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9222                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9223                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9224                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9225                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9226                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9227                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9228                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9229                         I40E_INSET_SCTP_VT,
9230                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9231                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9232                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9233                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9234                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9235                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9236                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9237                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9238                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9239                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9240                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9241                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9242                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9243                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9244                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9245                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9246                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9247                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9248                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9249                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9250                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9251                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9252                         I40E_INSET_SCTP_VT,
9253                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9254                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9255                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9256                         I40E_INSET_LAST_ETHER_TYPE,
9257         };
9258
9259         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9260                 return 0;
9261
9262         return default_inset_table[pctype];
9263 }
9264
9265 /**
9266  * Parse the input set from index to logical bit masks
9267  */
9268 static int
9269 i40e_parse_input_set(uint64_t *inset,
9270                      enum i40e_filter_pctype pctype,
9271                      enum rte_eth_input_set_field *field,
9272                      uint16_t size)
9273 {
9274         uint16_t i, j;
9275         int ret = -EINVAL;
9276
9277         static const struct {
9278                 enum rte_eth_input_set_field field;
9279                 uint64_t inset;
9280         } inset_convert_table[] = {
9281                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9282                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9283                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9284                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9285                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9286                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9287                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9288                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9289                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9290                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9291                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9292                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9293                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9294                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9295                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9296                         I40E_INSET_IPV6_NEXT_HDR},
9297                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9298                         I40E_INSET_IPV6_HOP_LIMIT},
9299                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9300                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9301                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9302                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9303                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9304                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9305                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9306                         I40E_INSET_SCTP_VT},
9307                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9308                         I40E_INSET_TUNNEL_DMAC},
9309                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9310                         I40E_INSET_VLAN_TUNNEL},
9311                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9312                         I40E_INSET_TUNNEL_ID},
9313                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9314                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9315                         I40E_INSET_FLEX_PAYLOAD_W1},
9316                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9317                         I40E_INSET_FLEX_PAYLOAD_W2},
9318                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9319                         I40E_INSET_FLEX_PAYLOAD_W3},
9320                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9321                         I40E_INSET_FLEX_PAYLOAD_W4},
9322                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9323                         I40E_INSET_FLEX_PAYLOAD_W5},
9324                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9325                         I40E_INSET_FLEX_PAYLOAD_W6},
9326                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9327                         I40E_INSET_FLEX_PAYLOAD_W7},
9328                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9329                         I40E_INSET_FLEX_PAYLOAD_W8},
9330         };
9331
9332         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9333                 return ret;
9334
9335         /* Only one item allowed for default or all */
9336         if (size == 1) {
9337                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9338                         *inset = i40e_get_default_input_set(pctype);
9339                         return 0;
9340                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9341                         *inset = I40E_INSET_NONE;
9342                         return 0;
9343                 }
9344         }
9345
9346         for (i = 0, *inset = 0; i < size; i++) {
9347                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9348                         if (field[i] == inset_convert_table[j].field) {
9349                                 *inset |= inset_convert_table[j].inset;
9350                                 break;
9351                         }
9352                 }
9353
9354                 /* It contains unsupported input set, return immediately */
9355                 if (j == RTE_DIM(inset_convert_table))
9356                         return ret;
9357         }
9358
9359         return 0;
9360 }
9361
9362 /**
9363  * Translate the input set from bit masks to register aware bit masks
9364  * and vice versa
9365  */
9366 uint64_t
9367 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9368 {
9369         uint64_t val = 0;
9370         uint16_t i;
9371
9372         struct inset_map {
9373                 uint64_t inset;
9374                 uint64_t inset_reg;
9375         };
9376
9377         static const struct inset_map inset_map_common[] = {
9378                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9379                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9380                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9381                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9382                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9383                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9384                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9385                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9386                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9387                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9388                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9389                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9390                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9391                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9392                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9393                 {I40E_INSET_TUNNEL_DMAC,
9394                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9395                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9396                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9397                 {I40E_INSET_TUNNEL_SRC_PORT,
9398                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9399                 {I40E_INSET_TUNNEL_DST_PORT,
9400                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9401                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9402                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9403                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9404                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9405                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9406                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9407                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9408                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9409                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9410         };
9411
9412     /* some different registers map in x722*/
9413         static const struct inset_map inset_map_diff_x722[] = {
9414                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9415                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9416                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9417                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9418         };
9419
9420         static const struct inset_map inset_map_diff_not_x722[] = {
9421                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9422                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9423                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9424                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9425         };
9426
9427         if (input == 0)
9428                 return val;
9429
9430         /* Translate input set to register aware inset */
9431         if (type == I40E_MAC_X722) {
9432                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9433                         if (input & inset_map_diff_x722[i].inset)
9434                                 val |= inset_map_diff_x722[i].inset_reg;
9435                 }
9436         } else {
9437                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9438                         if (input & inset_map_diff_not_x722[i].inset)
9439                                 val |= inset_map_diff_not_x722[i].inset_reg;
9440                 }
9441         }
9442
9443         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9444                 if (input & inset_map_common[i].inset)
9445                         val |= inset_map_common[i].inset_reg;
9446         }
9447
9448         return val;
9449 }
9450
9451 int
9452 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9453 {
9454         uint8_t i, idx = 0;
9455         uint64_t inset_need_mask = inset;
9456
9457         static const struct {
9458                 uint64_t inset;
9459                 uint32_t mask;
9460         } inset_mask_map[] = {
9461                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9462                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9463                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9464                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9465                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9466                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9467                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9468                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9469         };
9470
9471         if (!inset || !mask || !nb_elem)
9472                 return 0;
9473
9474         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9475                 /* Clear the inset bit, if no MASK is required,
9476                  * for example proto + ttl
9477                  */
9478                 if ((inset & inset_mask_map[i].inset) ==
9479                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9480                         inset_need_mask &= ~inset_mask_map[i].inset;
9481                 if (!inset_need_mask)
9482                         return 0;
9483         }
9484         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9485                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9486                     inset_mask_map[i].inset) {
9487                         if (idx >= nb_elem) {
9488                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9489                                 return -EINVAL;
9490                         }
9491                         mask[idx] = inset_mask_map[i].mask;
9492                         idx++;
9493                 }
9494         }
9495
9496         return idx;
9497 }
9498
9499 void
9500 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9501 {
9502         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9503
9504         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9505         if (reg != val)
9506                 i40e_write_rx_ctl(hw, addr, val);
9507         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9508                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9509 }
9510
9511 void
9512 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9513 {
9514         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9515         struct rte_eth_dev *dev;
9516
9517         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9518         if (reg != val) {
9519                 i40e_write_rx_ctl(hw, addr, val);
9520                 PMD_DRV_LOG(WARNING,
9521                             "i40e device %s changed global register [0x%08x]."
9522                             " original: 0x%08x, new: 0x%08x",
9523                             dev->device->name, addr, reg,
9524                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9525         }
9526 }
9527
9528 static void
9529 i40e_filter_input_set_init(struct i40e_pf *pf)
9530 {
9531         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9532         enum i40e_filter_pctype pctype;
9533         uint64_t input_set, inset_reg;
9534         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9535         int num, i;
9536         uint16_t flow_type;
9537
9538         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9539              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9540                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9541
9542                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9543                         continue;
9544
9545                 input_set = i40e_get_default_input_set(pctype);
9546
9547                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9548                                                    I40E_INSET_MASK_NUM_REG);
9549                 if (num < 0)
9550                         return;
9551                 if (pf->support_multi_driver && num > 0) {
9552                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9553                         return;
9554                 }
9555                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9556                                         input_set);
9557
9558                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9559                                       (uint32_t)(inset_reg & UINT32_MAX));
9560                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9561                                      (uint32_t)((inset_reg >>
9562                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9563                 if (!pf->support_multi_driver) {
9564                         i40e_check_write_global_reg(hw,
9565                                             I40E_GLQF_HASH_INSET(0, pctype),
9566                                             (uint32_t)(inset_reg & UINT32_MAX));
9567                         i40e_check_write_global_reg(hw,
9568                                              I40E_GLQF_HASH_INSET(1, pctype),
9569                                              (uint32_t)((inset_reg >>
9570                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9571
9572                         for (i = 0; i < num; i++) {
9573                                 i40e_check_write_global_reg(hw,
9574                                                     I40E_GLQF_FD_MSK(i, pctype),
9575                                                     mask_reg[i]);
9576                                 i40e_check_write_global_reg(hw,
9577                                                   I40E_GLQF_HASH_MSK(i, pctype),
9578                                                   mask_reg[i]);
9579                         }
9580                         /*clear unused mask registers of the pctype */
9581                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9582                                 i40e_check_write_global_reg(hw,
9583                                                     I40E_GLQF_FD_MSK(i, pctype),
9584                                                     0);
9585                                 i40e_check_write_global_reg(hw,
9586                                                   I40E_GLQF_HASH_MSK(i, pctype),
9587                                                   0);
9588                         }
9589                 } else {
9590                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9591                 }
9592                 I40E_WRITE_FLUSH(hw);
9593
9594                 /* store the default input set */
9595                 if (!pf->support_multi_driver)
9596                         pf->hash_input_set[pctype] = input_set;
9597                 pf->fdir.input_set[pctype] = input_set;
9598         }
9599 }
9600
9601 int
9602 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9603                          struct rte_eth_input_set_conf *conf)
9604 {
9605         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9606         enum i40e_filter_pctype pctype;
9607         uint64_t input_set, inset_reg = 0;
9608         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9609         int ret, i, num;
9610
9611         if (!conf) {
9612                 PMD_DRV_LOG(ERR, "Invalid pointer");
9613                 return -EFAULT;
9614         }
9615         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9616             conf->op != RTE_ETH_INPUT_SET_ADD) {
9617                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9618                 return -EINVAL;
9619         }
9620
9621         if (pf->support_multi_driver) {
9622                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9623                 return -ENOTSUP;
9624         }
9625
9626         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9627         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9628                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9629                 return -EINVAL;
9630         }
9631
9632         if (hw->mac.type == I40E_MAC_X722) {
9633                 /* get translated pctype value in fd pctype register */
9634                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9635                         I40E_GLQF_FD_PCTYPES((int)pctype));
9636         }
9637
9638         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9639                                    conf->inset_size);
9640         if (ret) {
9641                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9642                 return -EINVAL;
9643         }
9644
9645         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9646                 /* get inset value in register */
9647                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9648                 inset_reg <<= I40E_32_BIT_WIDTH;
9649                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9650                 input_set |= pf->hash_input_set[pctype];
9651         }
9652         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9653                                            I40E_INSET_MASK_NUM_REG);
9654         if (num < 0)
9655                 return -EINVAL;
9656
9657         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9658
9659         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9660                                     (uint32_t)(inset_reg & UINT32_MAX));
9661         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9662                                     (uint32_t)((inset_reg >>
9663                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9664
9665         for (i = 0; i < num; i++)
9666                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9667                                             mask_reg[i]);
9668         /*clear unused mask registers of the pctype */
9669         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9670                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9671                                             0);
9672         I40E_WRITE_FLUSH(hw);
9673
9674         pf->hash_input_set[pctype] = input_set;
9675         return 0;
9676 }
9677
9678 int
9679 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9680                          struct rte_eth_input_set_conf *conf)
9681 {
9682         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9683         enum i40e_filter_pctype pctype;
9684         uint64_t input_set, inset_reg = 0;
9685         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9686         int ret, i, num;
9687
9688         if (!hw || !conf) {
9689                 PMD_DRV_LOG(ERR, "Invalid pointer");
9690                 return -EFAULT;
9691         }
9692         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9693             conf->op != RTE_ETH_INPUT_SET_ADD) {
9694                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9695                 return -EINVAL;
9696         }
9697
9698         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9699
9700         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9701                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9702                 return -EINVAL;
9703         }
9704
9705         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9706                                    conf->inset_size);
9707         if (ret) {
9708                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9709                 return -EINVAL;
9710         }
9711
9712         /* get inset value in register */
9713         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9714         inset_reg <<= I40E_32_BIT_WIDTH;
9715         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9716
9717         /* Can not change the inset reg for flex payload for fdir,
9718          * it is done by writing I40E_PRTQF_FD_FLXINSET
9719          * in i40e_set_flex_mask_on_pctype.
9720          */
9721         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9722                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9723         else
9724                 input_set |= pf->fdir.input_set[pctype];
9725         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9726                                            I40E_INSET_MASK_NUM_REG);
9727         if (num < 0)
9728                 return -EINVAL;
9729         if (pf->support_multi_driver && num > 0) {
9730                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9731                 return -ENOTSUP;
9732         }
9733
9734         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9735
9736         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9737                               (uint32_t)(inset_reg & UINT32_MAX));
9738         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9739                              (uint32_t)((inset_reg >>
9740                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9741
9742         if (!pf->support_multi_driver) {
9743                 for (i = 0; i < num; i++)
9744                         i40e_check_write_global_reg(hw,
9745                                                     I40E_GLQF_FD_MSK(i, pctype),
9746                                                     mask_reg[i]);
9747                 /*clear unused mask registers of the pctype */
9748                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9749                         i40e_check_write_global_reg(hw,
9750                                                     I40E_GLQF_FD_MSK(i, pctype),
9751                                                     0);
9752         } else {
9753                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9754         }
9755         I40E_WRITE_FLUSH(hw);
9756
9757         pf->fdir.input_set[pctype] = input_set;
9758         return 0;
9759 }
9760
9761 static int
9762 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9763 {
9764         int ret = 0;
9765
9766         if (!hw || !info) {
9767                 PMD_DRV_LOG(ERR, "Invalid pointer");
9768                 return -EFAULT;
9769         }
9770
9771         switch (info->info_type) {
9772         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9773                 i40e_get_symmetric_hash_enable_per_port(hw,
9774                                         &(info->info.enable));
9775                 break;
9776         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9777                 ret = i40e_get_hash_filter_global_config(hw,
9778                                 &(info->info.global_conf));
9779                 break;
9780         default:
9781                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9782                                                         info->info_type);
9783                 ret = -EINVAL;
9784                 break;
9785         }
9786
9787         return ret;
9788 }
9789
9790 static int
9791 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9792 {
9793         int ret = 0;
9794
9795         if (!hw || !info) {
9796                 PMD_DRV_LOG(ERR, "Invalid pointer");
9797                 return -EFAULT;
9798         }
9799
9800         switch (info->info_type) {
9801         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9802                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9803                 break;
9804         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9805                 ret = i40e_set_hash_filter_global_config(hw,
9806                                 &(info->info.global_conf));
9807                 break;
9808         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9809                 ret = i40e_hash_filter_inset_select(hw,
9810                                                &(info->info.input_set_conf));
9811                 break;
9812
9813         default:
9814                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9815                                                         info->info_type);
9816                 ret = -EINVAL;
9817                 break;
9818         }
9819
9820         return ret;
9821 }
9822
9823 /* Operations for hash function */
9824 static int
9825 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9826                       enum rte_filter_op filter_op,
9827                       void *arg)
9828 {
9829         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9830         int ret = 0;
9831
9832         switch (filter_op) {
9833         case RTE_ETH_FILTER_NOP:
9834                 break;
9835         case RTE_ETH_FILTER_GET:
9836                 ret = i40e_hash_filter_get(hw,
9837                         (struct rte_eth_hash_filter_info *)arg);
9838                 break;
9839         case RTE_ETH_FILTER_SET:
9840                 ret = i40e_hash_filter_set(hw,
9841                         (struct rte_eth_hash_filter_info *)arg);
9842                 break;
9843         default:
9844                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9845                                                                 filter_op);
9846                 ret = -ENOTSUP;
9847                 break;
9848         }
9849
9850         return ret;
9851 }
9852
9853 /* Convert ethertype filter structure */
9854 static int
9855 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9856                               struct i40e_ethertype_filter *filter)
9857 {
9858         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9859         filter->input.ether_type = input->ether_type;
9860         filter->flags = input->flags;
9861         filter->queue = input->queue;
9862
9863         return 0;
9864 }
9865
9866 /* Check if there exists the ehtertype filter */
9867 struct i40e_ethertype_filter *
9868 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9869                                 const struct i40e_ethertype_filter_input *input)
9870 {
9871         int ret;
9872
9873         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9874         if (ret < 0)
9875                 return NULL;
9876
9877         return ethertype_rule->hash_map[ret];
9878 }
9879
9880 /* Add ethertype filter in SW list */
9881 static int
9882 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9883                                 struct i40e_ethertype_filter *filter)
9884 {
9885         struct i40e_ethertype_rule *rule = &pf->ethertype;
9886         int ret;
9887
9888         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9889         if (ret < 0) {
9890                 PMD_DRV_LOG(ERR,
9891                             "Failed to insert ethertype filter"
9892                             " to hash table %d!",
9893                             ret);
9894                 return ret;
9895         }
9896         rule->hash_map[ret] = filter;
9897
9898         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9899
9900         return 0;
9901 }
9902
9903 /* Delete ethertype filter in SW list */
9904 int
9905 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9906                              struct i40e_ethertype_filter_input *input)
9907 {
9908         struct i40e_ethertype_rule *rule = &pf->ethertype;
9909         struct i40e_ethertype_filter *filter;
9910         int ret;
9911
9912         ret = rte_hash_del_key(rule->hash_table, input);
9913         if (ret < 0) {
9914                 PMD_DRV_LOG(ERR,
9915                             "Failed to delete ethertype filter"
9916                             " to hash table %d!",
9917                             ret);
9918                 return ret;
9919         }
9920         filter = rule->hash_map[ret];
9921         rule->hash_map[ret] = NULL;
9922
9923         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9924         rte_free(filter);
9925
9926         return 0;
9927 }
9928
9929 /*
9930  * Configure ethertype filter, which can director packet by filtering
9931  * with mac address and ether_type or only ether_type
9932  */
9933 int
9934 i40e_ethertype_filter_set(struct i40e_pf *pf,
9935                         struct rte_eth_ethertype_filter *filter,
9936                         bool add)
9937 {
9938         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9939         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9940         struct i40e_ethertype_filter *ethertype_filter, *node;
9941         struct i40e_ethertype_filter check_filter;
9942         struct i40e_control_filter_stats stats;
9943         uint16_t flags = 0;
9944         int ret;
9945
9946         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9947                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9948                 return -EINVAL;
9949         }
9950         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9951                 filter->ether_type == ETHER_TYPE_IPv6) {
9952                 PMD_DRV_LOG(ERR,
9953                         "unsupported ether_type(0x%04x) in control packet filter.",
9954                         filter->ether_type);
9955                 return -EINVAL;
9956         }
9957         if (filter->ether_type == ETHER_TYPE_VLAN)
9958                 PMD_DRV_LOG(WARNING,
9959                         "filter vlan ether_type in first tag is not supported.");
9960
9961         /* Check if there is the filter in SW list */
9962         memset(&check_filter, 0, sizeof(check_filter));
9963         i40e_ethertype_filter_convert(filter, &check_filter);
9964         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9965                                                &check_filter.input);
9966         if (add && node) {
9967                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9968                 return -EINVAL;
9969         }
9970
9971         if (!add && !node) {
9972                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9973                 return -EINVAL;
9974         }
9975
9976         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9977                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9978         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9979                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9980         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9981
9982         memset(&stats, 0, sizeof(stats));
9983         ret = i40e_aq_add_rem_control_packet_filter(hw,
9984                         filter->mac_addr.addr_bytes,
9985                         filter->ether_type, flags,
9986                         pf->main_vsi->seid,
9987                         filter->queue, add, &stats, NULL);
9988
9989         PMD_DRV_LOG(INFO,
9990                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9991                 ret, stats.mac_etype_used, stats.etype_used,
9992                 stats.mac_etype_free, stats.etype_free);
9993         if (ret < 0)
9994                 return -ENOSYS;
9995
9996         /* Add or delete a filter in SW list */
9997         if (add) {
9998                 ethertype_filter = rte_zmalloc("ethertype_filter",
9999                                        sizeof(*ethertype_filter), 0);
10000                 if (ethertype_filter == NULL) {
10001                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10002                         return -ENOMEM;
10003                 }
10004
10005                 rte_memcpy(ethertype_filter, &check_filter,
10006                            sizeof(check_filter));
10007                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10008                 if (ret < 0)
10009                         rte_free(ethertype_filter);
10010         } else {
10011                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10012         }
10013
10014         return ret;
10015 }
10016
10017 /*
10018  * Handle operations for ethertype filter.
10019  */
10020 static int
10021 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10022                                 enum rte_filter_op filter_op,
10023                                 void *arg)
10024 {
10025         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10026         int ret = 0;
10027
10028         if (filter_op == RTE_ETH_FILTER_NOP)
10029                 return ret;
10030
10031         if (arg == NULL) {
10032                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10033                             filter_op);
10034                 return -EINVAL;
10035         }
10036
10037         switch (filter_op) {
10038         case RTE_ETH_FILTER_ADD:
10039                 ret = i40e_ethertype_filter_set(pf,
10040                         (struct rte_eth_ethertype_filter *)arg,
10041                         TRUE);
10042                 break;
10043         case RTE_ETH_FILTER_DELETE:
10044                 ret = i40e_ethertype_filter_set(pf,
10045                         (struct rte_eth_ethertype_filter *)arg,
10046                         FALSE);
10047                 break;
10048         default:
10049                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10050                 ret = -ENOSYS;
10051                 break;
10052         }
10053         return ret;
10054 }
10055
10056 static int
10057 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10058                      enum rte_filter_type filter_type,
10059                      enum rte_filter_op filter_op,
10060                      void *arg)
10061 {
10062         int ret = 0;
10063
10064         if (dev == NULL)
10065                 return -EINVAL;
10066
10067         switch (filter_type) {
10068         case RTE_ETH_FILTER_NONE:
10069                 /* For global configuration */
10070                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10071                 break;
10072         case RTE_ETH_FILTER_HASH:
10073                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10074                 break;
10075         case RTE_ETH_FILTER_MACVLAN:
10076                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10077                 break;
10078         case RTE_ETH_FILTER_ETHERTYPE:
10079                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10080                 break;
10081         case RTE_ETH_FILTER_TUNNEL:
10082                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10083                 break;
10084         case RTE_ETH_FILTER_FDIR:
10085                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10086                 break;
10087         case RTE_ETH_FILTER_GENERIC:
10088                 if (filter_op != RTE_ETH_FILTER_GET)
10089                         return -EINVAL;
10090                 *(const void **)arg = &i40e_flow_ops;
10091                 break;
10092         default:
10093                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10094                                                         filter_type);
10095                 ret = -EINVAL;
10096                 break;
10097         }
10098
10099         return ret;
10100 }
10101
10102 /*
10103  * Check and enable Extended Tag.
10104  * Enabling Extended Tag is important for 40G performance.
10105  */
10106 static void
10107 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10108 {
10109         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10110         uint32_t buf = 0;
10111         int ret;
10112
10113         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10114                                       PCI_DEV_CAP_REG);
10115         if (ret < 0) {
10116                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10117                             PCI_DEV_CAP_REG);
10118                 return;
10119         }
10120         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10121                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10122                 return;
10123         }
10124
10125         buf = 0;
10126         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10127                                       PCI_DEV_CTRL_REG);
10128         if (ret < 0) {
10129                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10130                             PCI_DEV_CTRL_REG);
10131                 return;
10132         }
10133         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10134                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10135                 return;
10136         }
10137         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10138         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10139                                        PCI_DEV_CTRL_REG);
10140         if (ret < 0) {
10141                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10142                             PCI_DEV_CTRL_REG);
10143                 return;
10144         }
10145 }
10146
10147 /*
10148  * As some registers wouldn't be reset unless a global hardware reset,
10149  * hardware initialization is needed to put those registers into an
10150  * expected initial state.
10151  */
10152 static void
10153 i40e_hw_init(struct rte_eth_dev *dev)
10154 {
10155         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10156
10157         i40e_enable_extended_tag(dev);
10158
10159         /* clear the PF Queue Filter control register */
10160         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10161
10162         /* Disable symmetric hash per port */
10163         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10164 }
10165
10166 /*
10167  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10168  * however this function will return only one highest pctype index,
10169  * which is not quite correct. This is known problem of i40e driver
10170  * and needs to be fixed later.
10171  */
10172 enum i40e_filter_pctype
10173 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10174 {
10175         int i;
10176         uint64_t pctype_mask;
10177
10178         if (flow_type < I40E_FLOW_TYPE_MAX) {
10179                 pctype_mask = adapter->pctypes_tbl[flow_type];
10180                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10181                         if (pctype_mask & (1ULL << i))
10182                                 return (enum i40e_filter_pctype)i;
10183                 }
10184         }
10185         return I40E_FILTER_PCTYPE_INVALID;
10186 }
10187
10188 uint16_t
10189 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10190                         enum i40e_filter_pctype pctype)
10191 {
10192         uint16_t flowtype;
10193         uint64_t pctype_mask = 1ULL << pctype;
10194
10195         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10196              flowtype++) {
10197                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10198                         return flowtype;
10199         }
10200
10201         return RTE_ETH_FLOW_UNKNOWN;
10202 }
10203
10204 /*
10205  * On X710, performance number is far from the expectation on recent firmware
10206  * versions; on XL710, performance number is also far from the expectation on
10207  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10208  * mode is enabled and port MAC address is equal to the packet destination MAC
10209  * address. The fix for this issue may not be integrated in the following
10210  * firmware version. So the workaround in software driver is needed. It needs
10211  * to modify the initial values of 3 internal only registers for both X710 and
10212  * XL710. Note that the values for X710 or XL710 could be different, and the
10213  * workaround can be removed when it is fixed in firmware in the future.
10214  */
10215
10216 /* For both X710 and XL710 */
10217 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10218 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10219 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10220
10221 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10222 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10223
10224 /* For X722 */
10225 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10226 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10227
10228 /* For X710 */
10229 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10230 /* For XL710 */
10231 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10232 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10233
10234 /*
10235  * GL_SWR_PM_UP_THR:
10236  * The value is not impacted from the link speed, its value is set according
10237  * to the total number of ports for a better pipe-monitor configuration.
10238  */
10239 static bool
10240 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10241 {
10242 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10243                 .device_id = (dev),   \
10244                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10245
10246 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10247                 .device_id = (dev),   \
10248                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10249
10250         static const struct {
10251                 uint16_t device_id;
10252                 uint32_t val;
10253         } swr_pm_table[] = {
10254                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10255                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10256                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10257                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10258
10259                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10260                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10261                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10262                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10263                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10264                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10265                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10266         };
10267         uint32_t i;
10268
10269         if (value == NULL) {
10270                 PMD_DRV_LOG(ERR, "value is NULL");
10271                 return false;
10272         }
10273
10274         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10275                 if (hw->device_id == swr_pm_table[i].device_id) {
10276                         *value = swr_pm_table[i].val;
10277
10278                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10279                                     "value - 0x%08x",
10280                                     hw->device_id, *value);
10281                         return true;
10282                 }
10283         }
10284
10285         return false;
10286 }
10287
10288 static int
10289 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10290 {
10291         enum i40e_status_code status;
10292         struct i40e_aq_get_phy_abilities_resp phy_ab;
10293         int ret = -ENOTSUP;
10294         int retries = 0;
10295
10296         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10297                                               NULL);
10298
10299         while (status) {
10300                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10301                         status);
10302                 retries++;
10303                 rte_delay_us(100000);
10304                 if  (retries < 5)
10305                         status = i40e_aq_get_phy_capabilities(hw, false,
10306                                         true, &phy_ab, NULL);
10307                 else
10308                         return ret;
10309         }
10310         return 0;
10311 }
10312
10313 static void
10314 i40e_configure_registers(struct i40e_hw *hw)
10315 {
10316         static struct {
10317                 uint32_t addr;
10318                 uint64_t val;
10319         } reg_table[] = {
10320                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10321                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10322                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10323         };
10324         uint64_t reg;
10325         uint32_t i;
10326         int ret;
10327
10328         for (i = 0; i < RTE_DIM(reg_table); i++) {
10329                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10330                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10331                                 reg_table[i].val =
10332                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10333                         else /* For X710/XL710/XXV710 */
10334                                 if (hw->aq.fw_maj_ver < 6)
10335                                         reg_table[i].val =
10336                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10337                                 else
10338                                         reg_table[i].val =
10339                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10340                 }
10341
10342                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10343                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10344                                 reg_table[i].val =
10345                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10346                         else /* For X710/XL710/XXV710 */
10347                                 reg_table[i].val =
10348                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10349                 }
10350
10351                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10352                         uint32_t cfg_val;
10353
10354                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10355                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10356                                             "GL_SWR_PM_UP_THR value fixup",
10357                                             hw->device_id);
10358                                 continue;
10359                         }
10360
10361                         reg_table[i].val = cfg_val;
10362                 }
10363
10364                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10365                                                         &reg, NULL);
10366                 if (ret < 0) {
10367                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10368                                                         reg_table[i].addr);
10369                         break;
10370                 }
10371                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10372                                                 reg_table[i].addr, reg);
10373                 if (reg == reg_table[i].val)
10374                         continue;
10375
10376                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10377                                                 reg_table[i].val, NULL);
10378                 if (ret < 0) {
10379                         PMD_DRV_LOG(ERR,
10380                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10381                                 reg_table[i].val, reg_table[i].addr);
10382                         break;
10383                 }
10384                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10385                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10386         }
10387 }
10388
10389 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10390 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10391 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10392 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10393 static int
10394 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10395 {
10396         uint32_t reg;
10397         int ret;
10398
10399         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10400                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10401                 return -EINVAL;
10402         }
10403
10404         /* Configure for double VLAN RX stripping */
10405         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10406         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10407                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10408                 ret = i40e_aq_debug_write_register(hw,
10409                                                    I40E_VSI_TSR(vsi->vsi_id),
10410                                                    reg, NULL);
10411                 if (ret < 0) {
10412                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10413                                     vsi->vsi_id);
10414                         return I40E_ERR_CONFIG;
10415                 }
10416         }
10417
10418         /* Configure for double VLAN TX insertion */
10419         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10420         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10421                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10422                 ret = i40e_aq_debug_write_register(hw,
10423                                                    I40E_VSI_L2TAGSTXVALID(
10424                                                    vsi->vsi_id), reg, NULL);
10425                 if (ret < 0) {
10426                         PMD_DRV_LOG(ERR,
10427                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10428                                 vsi->vsi_id);
10429                         return I40E_ERR_CONFIG;
10430                 }
10431         }
10432
10433         return 0;
10434 }
10435
10436 /**
10437  * i40e_aq_add_mirror_rule
10438  * @hw: pointer to the hardware structure
10439  * @seid: VEB seid to add mirror rule to
10440  * @dst_id: destination vsi seid
10441  * @entries: Buffer which contains the entities to be mirrored
10442  * @count: number of entities contained in the buffer
10443  * @rule_id:the rule_id of the rule to be added
10444  *
10445  * Add a mirror rule for a given veb.
10446  *
10447  **/
10448 static enum i40e_status_code
10449 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10450                         uint16_t seid, uint16_t dst_id,
10451                         uint16_t rule_type, uint16_t *entries,
10452                         uint16_t count, uint16_t *rule_id)
10453 {
10454         struct i40e_aq_desc desc;
10455         struct i40e_aqc_add_delete_mirror_rule cmd;
10456         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10457                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10458                 &desc.params.raw;
10459         uint16_t buff_len;
10460         enum i40e_status_code status;
10461
10462         i40e_fill_default_direct_cmd_desc(&desc,
10463                                           i40e_aqc_opc_add_mirror_rule);
10464         memset(&cmd, 0, sizeof(cmd));
10465
10466         buff_len = sizeof(uint16_t) * count;
10467         desc.datalen = rte_cpu_to_le_16(buff_len);
10468         if (buff_len > 0)
10469                 desc.flags |= rte_cpu_to_le_16(
10470                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10471         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10472                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10473         cmd.num_entries = rte_cpu_to_le_16(count);
10474         cmd.seid = rte_cpu_to_le_16(seid);
10475         cmd.destination = rte_cpu_to_le_16(dst_id);
10476
10477         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10478         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10479         PMD_DRV_LOG(INFO,
10480                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10481                 hw->aq.asq_last_status, resp->rule_id,
10482                 resp->mirror_rules_used, resp->mirror_rules_free);
10483         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10484
10485         return status;
10486 }
10487
10488 /**
10489  * i40e_aq_del_mirror_rule
10490  * @hw: pointer to the hardware structure
10491  * @seid: VEB seid to add mirror rule to
10492  * @entries: Buffer which contains the entities to be mirrored
10493  * @count: number of entities contained in the buffer
10494  * @rule_id:the rule_id of the rule to be delete
10495  *
10496  * Delete a mirror rule for a given veb.
10497  *
10498  **/
10499 static enum i40e_status_code
10500 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10501                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10502                 uint16_t count, uint16_t rule_id)
10503 {
10504         struct i40e_aq_desc desc;
10505         struct i40e_aqc_add_delete_mirror_rule cmd;
10506         uint16_t buff_len = 0;
10507         enum i40e_status_code status;
10508         void *buff = NULL;
10509
10510         i40e_fill_default_direct_cmd_desc(&desc,
10511                                           i40e_aqc_opc_delete_mirror_rule);
10512         memset(&cmd, 0, sizeof(cmd));
10513         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10514                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10515                                                           I40E_AQ_FLAG_RD));
10516                 cmd.num_entries = count;
10517                 buff_len = sizeof(uint16_t) * count;
10518                 desc.datalen = rte_cpu_to_le_16(buff_len);
10519                 buff = (void *)entries;
10520         } else
10521                 /* rule id is filled in destination field for deleting mirror rule */
10522                 cmd.destination = rte_cpu_to_le_16(rule_id);
10523
10524         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10525                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10526         cmd.seid = rte_cpu_to_le_16(seid);
10527
10528         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10529         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10530
10531         return status;
10532 }
10533
10534 /**
10535  * i40e_mirror_rule_set
10536  * @dev: pointer to the hardware structure
10537  * @mirror_conf: mirror rule info
10538  * @sw_id: mirror rule's sw_id
10539  * @on: enable/disable
10540  *
10541  * set a mirror rule.
10542  *
10543  **/
10544 static int
10545 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10546                         struct rte_eth_mirror_conf *mirror_conf,
10547                         uint8_t sw_id, uint8_t on)
10548 {
10549         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10550         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10551         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10552         struct i40e_mirror_rule *parent = NULL;
10553         uint16_t seid, dst_seid, rule_id;
10554         uint16_t i, j = 0;
10555         int ret;
10556
10557         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10558
10559         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10560                 PMD_DRV_LOG(ERR,
10561                         "mirror rule can not be configured without veb or vfs.");
10562                 return -ENOSYS;
10563         }
10564         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10565                 PMD_DRV_LOG(ERR, "mirror table is full.");
10566                 return -ENOSPC;
10567         }
10568         if (mirror_conf->dst_pool > pf->vf_num) {
10569                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10570                                  mirror_conf->dst_pool);
10571                 return -EINVAL;
10572         }
10573
10574         seid = pf->main_vsi->veb->seid;
10575
10576         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10577                 if (sw_id <= it->index) {
10578                         mirr_rule = it;
10579                         break;
10580                 }
10581                 parent = it;
10582         }
10583         if (mirr_rule && sw_id == mirr_rule->index) {
10584                 if (on) {
10585                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10586                         return -EEXIST;
10587                 } else {
10588                         ret = i40e_aq_del_mirror_rule(hw, seid,
10589                                         mirr_rule->rule_type,
10590                                         mirr_rule->entries,
10591                                         mirr_rule->num_entries, mirr_rule->id);
10592                         if (ret < 0) {
10593                                 PMD_DRV_LOG(ERR,
10594                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10595                                         ret, hw->aq.asq_last_status);
10596                                 return -ENOSYS;
10597                         }
10598                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10599                         rte_free(mirr_rule);
10600                         pf->nb_mirror_rule--;
10601                         return 0;
10602                 }
10603         } else if (!on) {
10604                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10605                 return -ENOENT;
10606         }
10607
10608         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10609                                 sizeof(struct i40e_mirror_rule) , 0);
10610         if (!mirr_rule) {
10611                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10612                 return I40E_ERR_NO_MEMORY;
10613         }
10614         switch (mirror_conf->rule_type) {
10615         case ETH_MIRROR_VLAN:
10616                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10617                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10618                                 mirr_rule->entries[j] =
10619                                         mirror_conf->vlan.vlan_id[i];
10620                                 j++;
10621                         }
10622                 }
10623                 if (j == 0) {
10624                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10625                         rte_free(mirr_rule);
10626                         return -EINVAL;
10627                 }
10628                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10629                 break;
10630         case ETH_MIRROR_VIRTUAL_POOL_UP:
10631         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10632                 /* check if the specified pool bit is out of range */
10633                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10634                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10635                         rte_free(mirr_rule);
10636                         return -EINVAL;
10637                 }
10638                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10639                         if (mirror_conf->pool_mask & (1ULL << i)) {
10640                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10641                                 j++;
10642                         }
10643                 }
10644                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10645                         /* add pf vsi to entries */
10646                         mirr_rule->entries[j] = pf->main_vsi_seid;
10647                         j++;
10648                 }
10649                 if (j == 0) {
10650                         PMD_DRV_LOG(ERR, "pool is not specified.");
10651                         rte_free(mirr_rule);
10652                         return -EINVAL;
10653                 }
10654                 /* egress and ingress in aq commands means from switch but not port */
10655                 mirr_rule->rule_type =
10656                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10657                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10658                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10659                 break;
10660         case ETH_MIRROR_UPLINK_PORT:
10661                 /* egress and ingress in aq commands means from switch but not port*/
10662                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10663                 break;
10664         case ETH_MIRROR_DOWNLINK_PORT:
10665                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10666                 break;
10667         default:
10668                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10669                         mirror_conf->rule_type);
10670                 rte_free(mirr_rule);
10671                 return -EINVAL;
10672         }
10673
10674         /* If the dst_pool is equal to vf_num, consider it as PF */
10675         if (mirror_conf->dst_pool == pf->vf_num)
10676                 dst_seid = pf->main_vsi_seid;
10677         else
10678                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10679
10680         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10681                                       mirr_rule->rule_type, mirr_rule->entries,
10682                                       j, &rule_id);
10683         if (ret < 0) {
10684                 PMD_DRV_LOG(ERR,
10685                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10686                         ret, hw->aq.asq_last_status);
10687                 rte_free(mirr_rule);
10688                 return -ENOSYS;
10689         }
10690
10691         mirr_rule->index = sw_id;
10692         mirr_rule->num_entries = j;
10693         mirr_rule->id = rule_id;
10694         mirr_rule->dst_vsi_seid = dst_seid;
10695
10696         if (parent)
10697                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10698         else
10699                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10700
10701         pf->nb_mirror_rule++;
10702         return 0;
10703 }
10704
10705 /**
10706  * i40e_mirror_rule_reset
10707  * @dev: pointer to the device
10708  * @sw_id: mirror rule's sw_id
10709  *
10710  * reset a mirror rule.
10711  *
10712  **/
10713 static int
10714 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10715 {
10716         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10717         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10718         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10719         uint16_t seid;
10720         int ret;
10721
10722         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10723
10724         seid = pf->main_vsi->veb->seid;
10725
10726         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10727                 if (sw_id == it->index) {
10728                         mirr_rule = it;
10729                         break;
10730                 }
10731         }
10732         if (mirr_rule) {
10733                 ret = i40e_aq_del_mirror_rule(hw, seid,
10734                                 mirr_rule->rule_type,
10735                                 mirr_rule->entries,
10736                                 mirr_rule->num_entries, mirr_rule->id);
10737                 if (ret < 0) {
10738                         PMD_DRV_LOG(ERR,
10739                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10740                                 ret, hw->aq.asq_last_status);
10741                         return -ENOSYS;
10742                 }
10743                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10744                 rte_free(mirr_rule);
10745                 pf->nb_mirror_rule--;
10746         } else {
10747                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10748                 return -ENOENT;
10749         }
10750         return 0;
10751 }
10752
10753 static uint64_t
10754 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10755 {
10756         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10757         uint64_t systim_cycles;
10758
10759         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10760         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10761                         << 32;
10762
10763         return systim_cycles;
10764 }
10765
10766 static uint64_t
10767 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10768 {
10769         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10770         uint64_t rx_tstamp;
10771
10772         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10773         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10774                         << 32;
10775
10776         return rx_tstamp;
10777 }
10778
10779 static uint64_t
10780 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10781 {
10782         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10783         uint64_t tx_tstamp;
10784
10785         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10786         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10787                         << 32;
10788
10789         return tx_tstamp;
10790 }
10791
10792 static void
10793 i40e_start_timecounters(struct rte_eth_dev *dev)
10794 {
10795         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10796         struct i40e_adapter *adapter =
10797                         (struct i40e_adapter *)dev->data->dev_private;
10798         struct rte_eth_link link;
10799         uint32_t tsync_inc_l;
10800         uint32_t tsync_inc_h;
10801
10802         /* Get current link speed. */
10803         i40e_dev_link_update(dev, 1);
10804         rte_eth_linkstatus_get(dev, &link);
10805
10806         switch (link.link_speed) {
10807         case ETH_SPEED_NUM_40G:
10808                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10809                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10810                 break;
10811         case ETH_SPEED_NUM_10G:
10812                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10813                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10814                 break;
10815         case ETH_SPEED_NUM_1G:
10816                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10817                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10818                 break;
10819         default:
10820                 tsync_inc_l = 0x0;
10821                 tsync_inc_h = 0x0;
10822         }
10823
10824         /* Set the timesync increment value. */
10825         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10826         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10827
10828         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10829         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10830         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10831
10832         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10833         adapter->systime_tc.cc_shift = 0;
10834         adapter->systime_tc.nsec_mask = 0;
10835
10836         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10837         adapter->rx_tstamp_tc.cc_shift = 0;
10838         adapter->rx_tstamp_tc.nsec_mask = 0;
10839
10840         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10841         adapter->tx_tstamp_tc.cc_shift = 0;
10842         adapter->tx_tstamp_tc.nsec_mask = 0;
10843 }
10844
10845 static int
10846 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10847 {
10848         struct i40e_adapter *adapter =
10849                         (struct i40e_adapter *)dev->data->dev_private;
10850
10851         adapter->systime_tc.nsec += delta;
10852         adapter->rx_tstamp_tc.nsec += delta;
10853         adapter->tx_tstamp_tc.nsec += delta;
10854
10855         return 0;
10856 }
10857
10858 static int
10859 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10860 {
10861         uint64_t ns;
10862         struct i40e_adapter *adapter =
10863                         (struct i40e_adapter *)dev->data->dev_private;
10864
10865         ns = rte_timespec_to_ns(ts);
10866
10867         /* Set the timecounters to a new value. */
10868         adapter->systime_tc.nsec = ns;
10869         adapter->rx_tstamp_tc.nsec = ns;
10870         adapter->tx_tstamp_tc.nsec = ns;
10871
10872         return 0;
10873 }
10874
10875 static int
10876 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10877 {
10878         uint64_t ns, systime_cycles;
10879         struct i40e_adapter *adapter =
10880                         (struct i40e_adapter *)dev->data->dev_private;
10881
10882         systime_cycles = i40e_read_systime_cyclecounter(dev);
10883         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10884         *ts = rte_ns_to_timespec(ns);
10885
10886         return 0;
10887 }
10888
10889 static int
10890 i40e_timesync_enable(struct rte_eth_dev *dev)
10891 {
10892         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10893         uint32_t tsync_ctl_l;
10894         uint32_t tsync_ctl_h;
10895
10896         /* Stop the timesync system time. */
10897         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10898         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10899         /* Reset the timesync system time value. */
10900         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10901         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10902
10903         i40e_start_timecounters(dev);
10904
10905         /* Clear timesync registers. */
10906         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10907         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10908         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10909         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10910         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10911         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10912
10913         /* Enable timestamping of PTP packets. */
10914         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10915         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10916
10917         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10918         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10919         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10920
10921         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10922         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10923
10924         return 0;
10925 }
10926
10927 static int
10928 i40e_timesync_disable(struct rte_eth_dev *dev)
10929 {
10930         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10931         uint32_t tsync_ctl_l;
10932         uint32_t tsync_ctl_h;
10933
10934         /* Disable timestamping of transmitted PTP packets. */
10935         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10936         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10937
10938         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10939         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10940
10941         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10942         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10943
10944         /* Reset the timesync increment value. */
10945         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10946         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10947
10948         return 0;
10949 }
10950
10951 static int
10952 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10953                                 struct timespec *timestamp, uint32_t flags)
10954 {
10955         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10956         struct i40e_adapter *adapter =
10957                 (struct i40e_adapter *)dev->data->dev_private;
10958
10959         uint32_t sync_status;
10960         uint32_t index = flags & 0x03;
10961         uint64_t rx_tstamp_cycles;
10962         uint64_t ns;
10963
10964         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10965         if ((sync_status & (1 << index)) == 0)
10966                 return -EINVAL;
10967
10968         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10969         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10970         *timestamp = rte_ns_to_timespec(ns);
10971
10972         return 0;
10973 }
10974
10975 static int
10976 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10977                                 struct timespec *timestamp)
10978 {
10979         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10980         struct i40e_adapter *adapter =
10981                 (struct i40e_adapter *)dev->data->dev_private;
10982
10983         uint32_t sync_status;
10984         uint64_t tx_tstamp_cycles;
10985         uint64_t ns;
10986
10987         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10988         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10989                 return -EINVAL;
10990
10991         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10992         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10993         *timestamp = rte_ns_to_timespec(ns);
10994
10995         return 0;
10996 }
10997
10998 /*
10999  * i40e_parse_dcb_configure - parse dcb configure from user
11000  * @dev: the device being configured
11001  * @dcb_cfg: pointer of the result of parse
11002  * @*tc_map: bit map of enabled traffic classes
11003  *
11004  * Returns 0 on success, negative value on failure
11005  */
11006 static int
11007 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11008                          struct i40e_dcbx_config *dcb_cfg,
11009                          uint8_t *tc_map)
11010 {
11011         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11012         uint8_t i, tc_bw, bw_lf;
11013
11014         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11015
11016         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11017         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11018                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11019                 return -EINVAL;
11020         }
11021
11022         /* assume each tc has the same bw */
11023         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11024         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11025                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11026         /* to ensure the sum of tcbw is equal to 100 */
11027         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11028         for (i = 0; i < bw_lf; i++)
11029                 dcb_cfg->etscfg.tcbwtable[i]++;
11030
11031         /* assume each tc has the same Transmission Selection Algorithm */
11032         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11033                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11034
11035         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11036                 dcb_cfg->etscfg.prioritytable[i] =
11037                                 dcb_rx_conf->dcb_tc[i];
11038
11039         /* FW needs one App to configure HW */
11040         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11041         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11042         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11043         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11044
11045         if (dcb_rx_conf->nb_tcs == 0)
11046                 *tc_map = 1; /* tc0 only */
11047         else
11048                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11049
11050         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11051                 dcb_cfg->pfc.willing = 0;
11052                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11053                 dcb_cfg->pfc.pfcenable = *tc_map;
11054         }
11055         return 0;
11056 }
11057
11058
11059 static enum i40e_status_code
11060 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11061                               struct i40e_aqc_vsi_properties_data *info,
11062                               uint8_t enabled_tcmap)
11063 {
11064         enum i40e_status_code ret;
11065         int i, total_tc = 0;
11066         uint16_t qpnum_per_tc, bsf, qp_idx;
11067         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11068         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11069         uint16_t used_queues;
11070
11071         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11072         if (ret != I40E_SUCCESS)
11073                 return ret;
11074
11075         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11076                 if (enabled_tcmap & (1 << i))
11077                         total_tc++;
11078         }
11079         if (total_tc == 0)
11080                 total_tc = 1;
11081         vsi->enabled_tc = enabled_tcmap;
11082
11083         /* different VSI has different queues assigned */
11084         if (vsi->type == I40E_VSI_MAIN)
11085                 used_queues = dev_data->nb_rx_queues -
11086                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11087         else if (vsi->type == I40E_VSI_VMDQ2)
11088                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11089         else {
11090                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11091                 return I40E_ERR_NO_AVAILABLE_VSI;
11092         }
11093
11094         qpnum_per_tc = used_queues / total_tc;
11095         /* Number of queues per enabled TC */
11096         if (qpnum_per_tc == 0) {
11097                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11098                 return I40E_ERR_INVALID_QP_ID;
11099         }
11100         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11101                                 I40E_MAX_Q_PER_TC);
11102         bsf = rte_bsf32(qpnum_per_tc);
11103
11104         /**
11105          * Configure TC and queue mapping parameters, for enabled TC,
11106          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11107          * default queue will serve it.
11108          */
11109         qp_idx = 0;
11110         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11111                 if (vsi->enabled_tc & (1 << i)) {
11112                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11113                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11114                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11115                         qp_idx += qpnum_per_tc;
11116                 } else
11117                         info->tc_mapping[i] = 0;
11118         }
11119
11120         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11121         if (vsi->type == I40E_VSI_SRIOV) {
11122                 info->mapping_flags |=
11123                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11124                 for (i = 0; i < vsi->nb_qps; i++)
11125                         info->queue_mapping[i] =
11126                                 rte_cpu_to_le_16(vsi->base_queue + i);
11127         } else {
11128                 info->mapping_flags |=
11129                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11130                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11131         }
11132         info->valid_sections |=
11133                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11134
11135         return I40E_SUCCESS;
11136 }
11137
11138 /*
11139  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11140  * @veb: VEB to be configured
11141  * @tc_map: enabled TC bitmap
11142  *
11143  * Returns 0 on success, negative value on failure
11144  */
11145 static enum i40e_status_code
11146 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11147 {
11148         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11149         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11150         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11151         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11152         enum i40e_status_code ret = I40E_SUCCESS;
11153         int i;
11154         uint32_t bw_max;
11155
11156         /* Check if enabled_tc is same as existing or new TCs */
11157         if (veb->enabled_tc == tc_map)
11158                 return ret;
11159
11160         /* configure tc bandwidth */
11161         memset(&veb_bw, 0, sizeof(veb_bw));
11162         veb_bw.tc_valid_bits = tc_map;
11163         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11164         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11165                 if (tc_map & BIT_ULL(i))
11166                         veb_bw.tc_bw_share_credits[i] = 1;
11167         }
11168         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11169                                                    &veb_bw, NULL);
11170         if (ret) {
11171                 PMD_INIT_LOG(ERR,
11172                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11173                         hw->aq.asq_last_status);
11174                 return ret;
11175         }
11176
11177         memset(&ets_query, 0, sizeof(ets_query));
11178         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11179                                                    &ets_query, NULL);
11180         if (ret != I40E_SUCCESS) {
11181                 PMD_DRV_LOG(ERR,
11182                         "Failed to get switch_comp ETS configuration %u",
11183                         hw->aq.asq_last_status);
11184                 return ret;
11185         }
11186         memset(&bw_query, 0, sizeof(bw_query));
11187         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11188                                                   &bw_query, NULL);
11189         if (ret != I40E_SUCCESS) {
11190                 PMD_DRV_LOG(ERR,
11191                         "Failed to get switch_comp bandwidth configuration %u",
11192                         hw->aq.asq_last_status);
11193                 return ret;
11194         }
11195
11196         /* store and print out BW info */
11197         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11198         veb->bw_info.bw_max = ets_query.tc_bw_max;
11199         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11200         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11201         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11202                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11203                      I40E_16_BIT_WIDTH);
11204         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11205                 veb->bw_info.bw_ets_share_credits[i] =
11206                                 bw_query.tc_bw_share_credits[i];
11207                 veb->bw_info.bw_ets_credits[i] =
11208                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11209                 /* 4 bits per TC, 4th bit is reserved */
11210                 veb->bw_info.bw_ets_max[i] =
11211                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11212                                   RTE_LEN2MASK(3, uint8_t));
11213                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11214                             veb->bw_info.bw_ets_share_credits[i]);
11215                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11216                             veb->bw_info.bw_ets_credits[i]);
11217                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11218                             veb->bw_info.bw_ets_max[i]);
11219         }
11220
11221         veb->enabled_tc = tc_map;
11222
11223         return ret;
11224 }
11225
11226
11227 /*
11228  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11229  * @vsi: VSI to be configured
11230  * @tc_map: enabled TC bitmap
11231  *
11232  * Returns 0 on success, negative value on failure
11233  */
11234 static enum i40e_status_code
11235 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11236 {
11237         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11238         struct i40e_vsi_context ctxt;
11239         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11240         enum i40e_status_code ret = I40E_SUCCESS;
11241         int i;
11242
11243         /* Check if enabled_tc is same as existing or new TCs */
11244         if (vsi->enabled_tc == tc_map)
11245                 return ret;
11246
11247         /* configure tc bandwidth */
11248         memset(&bw_data, 0, sizeof(bw_data));
11249         bw_data.tc_valid_bits = tc_map;
11250         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11251         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11252                 if (tc_map & BIT_ULL(i))
11253                         bw_data.tc_bw_credits[i] = 1;
11254         }
11255         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11256         if (ret) {
11257                 PMD_INIT_LOG(ERR,
11258                         "AQ command Config VSI BW allocation per TC failed = %d",
11259                         hw->aq.asq_last_status);
11260                 goto out;
11261         }
11262         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11263                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11264
11265         /* Update Queue Pairs Mapping for currently enabled UPs */
11266         ctxt.seid = vsi->seid;
11267         ctxt.pf_num = hw->pf_id;
11268         ctxt.vf_num = 0;
11269         ctxt.uplink_seid = vsi->uplink_seid;
11270         ctxt.info = vsi->info;
11271         i40e_get_cap(hw);
11272         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11273         if (ret)
11274                 goto out;
11275
11276         /* Update the VSI after updating the VSI queue-mapping information */
11277         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11278         if (ret) {
11279                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11280                         hw->aq.asq_last_status);
11281                 goto out;
11282         }
11283         /* update the local VSI info with updated queue map */
11284         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11285                                         sizeof(vsi->info.tc_mapping));
11286         rte_memcpy(&vsi->info.queue_mapping,
11287                         &ctxt.info.queue_mapping,
11288                 sizeof(vsi->info.queue_mapping));
11289         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11290         vsi->info.valid_sections = 0;
11291
11292         /* query and update current VSI BW information */
11293         ret = i40e_vsi_get_bw_config(vsi);
11294         if (ret) {
11295                 PMD_INIT_LOG(ERR,
11296                          "Failed updating vsi bw info, err %s aq_err %s",
11297                          i40e_stat_str(hw, ret),
11298                          i40e_aq_str(hw, hw->aq.asq_last_status));
11299                 goto out;
11300         }
11301
11302         vsi->enabled_tc = tc_map;
11303
11304 out:
11305         return ret;
11306 }
11307
11308 /*
11309  * i40e_dcb_hw_configure - program the dcb setting to hw
11310  * @pf: pf the configuration is taken on
11311  * @new_cfg: new configuration
11312  * @tc_map: enabled TC bitmap
11313  *
11314  * Returns 0 on success, negative value on failure
11315  */
11316 static enum i40e_status_code
11317 i40e_dcb_hw_configure(struct i40e_pf *pf,
11318                       struct i40e_dcbx_config *new_cfg,
11319                       uint8_t tc_map)
11320 {
11321         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11322         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11323         struct i40e_vsi *main_vsi = pf->main_vsi;
11324         struct i40e_vsi_list *vsi_list;
11325         enum i40e_status_code ret;
11326         int i;
11327         uint32_t val;
11328
11329         /* Use the FW API if FW > v4.4*/
11330         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11331               (hw->aq.fw_maj_ver >= 5))) {
11332                 PMD_INIT_LOG(ERR,
11333                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11334                 return I40E_ERR_FIRMWARE_API_VERSION;
11335         }
11336
11337         /* Check if need reconfiguration */
11338         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11339                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11340                 return I40E_SUCCESS;
11341         }
11342
11343         /* Copy the new config to the current config */
11344         *old_cfg = *new_cfg;
11345         old_cfg->etsrec = old_cfg->etscfg;
11346         ret = i40e_set_dcb_config(hw);
11347         if (ret) {
11348                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11349                          i40e_stat_str(hw, ret),
11350                          i40e_aq_str(hw, hw->aq.asq_last_status));
11351                 return ret;
11352         }
11353         /* set receive Arbiter to RR mode and ETS scheme by default */
11354         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11355                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11356                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11357                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11358                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11359                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11360                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11361                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11362                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11363                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11364                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11365                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11366                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11367         }
11368         /* get local mib to check whether it is configured correctly */
11369         /* IEEE mode */
11370         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11371         /* Get Local DCB Config */
11372         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11373                                      &hw->local_dcbx_config);
11374
11375         /* if Veb is created, need to update TC of it at first */
11376         if (main_vsi->veb) {
11377                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11378                 if (ret)
11379                         PMD_INIT_LOG(WARNING,
11380                                  "Failed configuring TC for VEB seid=%d",
11381                                  main_vsi->veb->seid);
11382         }
11383         /* Update each VSI */
11384         i40e_vsi_config_tc(main_vsi, tc_map);
11385         if (main_vsi->veb) {
11386                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11387                         /* Beside main VSI and VMDQ VSIs, only enable default
11388                          * TC for other VSIs
11389                          */
11390                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11391                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11392                                                          tc_map);
11393                         else
11394                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11395                                                          I40E_DEFAULT_TCMAP);
11396                         if (ret)
11397                                 PMD_INIT_LOG(WARNING,
11398                                         "Failed configuring TC for VSI seid=%d",
11399                                         vsi_list->vsi->seid);
11400                         /* continue */
11401                 }
11402         }
11403         return I40E_SUCCESS;
11404 }
11405
11406 /*
11407  * i40e_dcb_init_configure - initial dcb config
11408  * @dev: device being configured
11409  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11410  *
11411  * Returns 0 on success, negative value on failure
11412  */
11413 int
11414 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11415 {
11416         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11417         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11418         int i, ret = 0;
11419
11420         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11421                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11422                 return -ENOTSUP;
11423         }
11424
11425         /* DCB initialization:
11426          * Update DCB configuration from the Firmware and configure
11427          * LLDP MIB change event.
11428          */
11429         if (sw_dcb == TRUE) {
11430                 /* When using NVM 6.01 or later, the RX data path does
11431                  * not hang if the FW LLDP is stopped.
11432                  */
11433                 if (((hw->nvm.version >> 12) & 0xf) >= 6 &&
11434                     ((hw->nvm.version >> 4) & 0xff) >= 1) {
11435                         ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11436                         if (ret != I40E_SUCCESS)
11437                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11438                 }
11439
11440                 ret = i40e_init_dcb(hw);
11441                 /* If lldp agent is stopped, the return value from
11442                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11443                  * adminq status. Otherwise, it should return success.
11444                  */
11445                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11446                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11447                         memset(&hw->local_dcbx_config, 0,
11448                                 sizeof(struct i40e_dcbx_config));
11449                         /* set dcb default configuration */
11450                         hw->local_dcbx_config.etscfg.willing = 0;
11451                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11452                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11453                         hw->local_dcbx_config.etscfg.tsatable[0] =
11454                                                 I40E_IEEE_TSA_ETS;
11455                         /* all UPs mapping to TC0 */
11456                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11457                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11458                         hw->local_dcbx_config.etsrec =
11459                                 hw->local_dcbx_config.etscfg;
11460                         hw->local_dcbx_config.pfc.willing = 0;
11461                         hw->local_dcbx_config.pfc.pfccap =
11462                                                 I40E_MAX_TRAFFIC_CLASS;
11463                         /* FW needs one App to configure HW */
11464                         hw->local_dcbx_config.numapps = 1;
11465                         hw->local_dcbx_config.app[0].selector =
11466                                                 I40E_APP_SEL_ETHTYPE;
11467                         hw->local_dcbx_config.app[0].priority = 3;
11468                         hw->local_dcbx_config.app[0].protocolid =
11469                                                 I40E_APP_PROTOID_FCOE;
11470                         ret = i40e_set_dcb_config(hw);
11471                         if (ret) {
11472                                 PMD_INIT_LOG(ERR,
11473                                         "default dcb config fails. err = %d, aq_err = %d.",
11474                                         ret, hw->aq.asq_last_status);
11475                                 return -ENOSYS;
11476                         }
11477                 } else {
11478                         PMD_INIT_LOG(ERR,
11479                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11480                                 ret, hw->aq.asq_last_status);
11481                         return -ENOTSUP;
11482                 }
11483         } else {
11484                 ret = i40e_aq_start_lldp(hw, NULL);
11485                 if (ret != I40E_SUCCESS)
11486                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11487
11488                 ret = i40e_init_dcb(hw);
11489                 if (!ret) {
11490                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11491                                 PMD_INIT_LOG(ERR,
11492                                         "HW doesn't support DCBX offload.");
11493                                 return -ENOTSUP;
11494                         }
11495                 } else {
11496                         PMD_INIT_LOG(ERR,
11497                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11498                                 ret, hw->aq.asq_last_status);
11499                         return -ENOTSUP;
11500                 }
11501         }
11502         return 0;
11503 }
11504
11505 /*
11506  * i40e_dcb_setup - setup dcb related config
11507  * @dev: device being configured
11508  *
11509  * Returns 0 on success, negative value on failure
11510  */
11511 static int
11512 i40e_dcb_setup(struct rte_eth_dev *dev)
11513 {
11514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11515         struct i40e_dcbx_config dcb_cfg;
11516         uint8_t tc_map = 0;
11517         int ret = 0;
11518
11519         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11520                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11521                 return -ENOTSUP;
11522         }
11523
11524         if (pf->vf_num != 0)
11525                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11526
11527         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11528         if (ret) {
11529                 PMD_INIT_LOG(ERR, "invalid dcb config");
11530                 return -EINVAL;
11531         }
11532         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11533         if (ret) {
11534                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11535                 return -ENOSYS;
11536         }
11537
11538         return 0;
11539 }
11540
11541 static int
11542 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11543                       struct rte_eth_dcb_info *dcb_info)
11544 {
11545         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11546         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11547         struct i40e_vsi *vsi = pf->main_vsi;
11548         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11549         uint16_t bsf, tc_mapping;
11550         int i, j = 0;
11551
11552         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11553                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11554         else
11555                 dcb_info->nb_tcs = 1;
11556         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11557                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11558         for (i = 0; i < dcb_info->nb_tcs; i++)
11559                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11560
11561         /* get queue mapping if vmdq is disabled */
11562         if (!pf->nb_cfg_vmdq_vsi) {
11563                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11564                         if (!(vsi->enabled_tc & (1 << i)))
11565                                 continue;
11566                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11567                         dcb_info->tc_queue.tc_rxq[j][i].base =
11568                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11569                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11570                         dcb_info->tc_queue.tc_txq[j][i].base =
11571                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11572                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11573                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11574                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11575                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11576                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11577                 }
11578                 return 0;
11579         }
11580
11581         /* get queue mapping if vmdq is enabled */
11582         do {
11583                 vsi = pf->vmdq[j].vsi;
11584                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11585                         if (!(vsi->enabled_tc & (1 << i)))
11586                                 continue;
11587                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11588                         dcb_info->tc_queue.tc_rxq[j][i].base =
11589                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11590                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11591                         dcb_info->tc_queue.tc_txq[j][i].base =
11592                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11593                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11594                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11595                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11596                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11597                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11598                 }
11599                 j++;
11600         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11601         return 0;
11602 }
11603
11604 static int
11605 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11606 {
11607         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11608         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11609         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11610         uint16_t msix_intr;
11611
11612         msix_intr = intr_handle->intr_vec[queue_id];
11613         if (msix_intr == I40E_MISC_VEC_ID)
11614                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11615                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11616                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11617                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11618         else
11619                 I40E_WRITE_REG(hw,
11620                                I40E_PFINT_DYN_CTLN(msix_intr -
11621                                                    I40E_RX_VEC_START),
11622                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11623                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11624                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11625
11626         I40E_WRITE_FLUSH(hw);
11627         rte_intr_enable(&pci_dev->intr_handle);
11628
11629         return 0;
11630 }
11631
11632 static int
11633 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11634 {
11635         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11636         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11637         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11638         uint16_t msix_intr;
11639
11640         msix_intr = intr_handle->intr_vec[queue_id];
11641         if (msix_intr == I40E_MISC_VEC_ID)
11642                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11643                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11644         else
11645                 I40E_WRITE_REG(hw,
11646                                I40E_PFINT_DYN_CTLN(msix_intr -
11647                                                    I40E_RX_VEC_START),
11648                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11649         I40E_WRITE_FLUSH(hw);
11650
11651         return 0;
11652 }
11653
11654 /**
11655  * This function is used to check if the register is valid.
11656  * Below is the valid registers list for X722 only:
11657  * 0x2b800--0x2bb00
11658  * 0x38700--0x38a00
11659  * 0x3d800--0x3db00
11660  * 0x208e00--0x209000
11661  * 0x20be00--0x20c000
11662  * 0x263c00--0x264000
11663  * 0x265c00--0x266000
11664  */
11665 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11666 {
11667         if ((type != I40E_MAC_X722) &&
11668             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11669              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11670              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11671              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11672              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11673              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11674              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11675                 return 0;
11676         else
11677                 return 1;
11678 }
11679
11680 static int i40e_get_regs(struct rte_eth_dev *dev,
11681                          struct rte_dev_reg_info *regs)
11682 {
11683         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11684         uint32_t *ptr_data = regs->data;
11685         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11686         const struct i40e_reg_info *reg_info;
11687
11688         if (ptr_data == NULL) {
11689                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11690                 regs->width = sizeof(uint32_t);
11691                 return 0;
11692         }
11693
11694         /* The first few registers have to be read using AQ operations */
11695         reg_idx = 0;
11696         while (i40e_regs_adminq[reg_idx].name) {
11697                 reg_info = &i40e_regs_adminq[reg_idx++];
11698                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11699                         for (arr_idx2 = 0;
11700                                         arr_idx2 <= reg_info->count2;
11701                                         arr_idx2++) {
11702                                 reg_offset = arr_idx * reg_info->stride1 +
11703                                         arr_idx2 * reg_info->stride2;
11704                                 reg_offset += reg_info->base_addr;
11705                                 ptr_data[reg_offset >> 2] =
11706                                         i40e_read_rx_ctl(hw, reg_offset);
11707                         }
11708         }
11709
11710         /* The remaining registers can be read using primitives */
11711         reg_idx = 0;
11712         while (i40e_regs_others[reg_idx].name) {
11713                 reg_info = &i40e_regs_others[reg_idx++];
11714                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11715                         for (arr_idx2 = 0;
11716                                         arr_idx2 <= reg_info->count2;
11717                                         arr_idx2++) {
11718                                 reg_offset = arr_idx * reg_info->stride1 +
11719                                         arr_idx2 * reg_info->stride2;
11720                                 reg_offset += reg_info->base_addr;
11721                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11722                                         ptr_data[reg_offset >> 2] = 0;
11723                                 else
11724                                         ptr_data[reg_offset >> 2] =
11725                                                 I40E_READ_REG(hw, reg_offset);
11726                         }
11727         }
11728
11729         return 0;
11730 }
11731
11732 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11733 {
11734         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11735
11736         /* Convert word count to byte count */
11737         return hw->nvm.sr_size << 1;
11738 }
11739
11740 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11741                            struct rte_dev_eeprom_info *eeprom)
11742 {
11743         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11744         uint16_t *data = eeprom->data;
11745         uint16_t offset, length, cnt_words;
11746         int ret_code;
11747
11748         offset = eeprom->offset >> 1;
11749         length = eeprom->length >> 1;
11750         cnt_words = length;
11751
11752         if (offset > hw->nvm.sr_size ||
11753                 offset + length > hw->nvm.sr_size) {
11754                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11755                 return -EINVAL;
11756         }
11757
11758         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11759
11760         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11761         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11762                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11763                 return -EIO;
11764         }
11765
11766         return 0;
11767 }
11768
11769 static int i40e_get_module_info(struct rte_eth_dev *dev,
11770                                 struct rte_eth_dev_module_info *modinfo)
11771 {
11772         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11773         uint32_t sff8472_comp = 0;
11774         uint32_t sff8472_swap = 0;
11775         uint32_t sff8636_rev = 0;
11776         i40e_status status;
11777         uint32_t type = 0;
11778
11779         /* Check if firmware supports reading module EEPROM. */
11780         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11781                 PMD_DRV_LOG(ERR,
11782                             "Module EEPROM memory read not supported. "
11783                             "Please update the NVM image.\n");
11784                 return -EINVAL;
11785         }
11786
11787         status = i40e_update_link_info(hw);
11788         if (status)
11789                 return -EIO;
11790
11791         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11792                 PMD_DRV_LOG(ERR,
11793                             "Cannot read module EEPROM memory. "
11794                             "No module connected.\n");
11795                 return -EINVAL;
11796         }
11797
11798         type = hw->phy.link_info.module_type[0];
11799
11800         switch (type) {
11801         case I40E_MODULE_TYPE_SFP:
11802                 status = i40e_aq_get_phy_register(hw,
11803                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11804                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11805                                 I40E_MODULE_SFF_8472_COMP,
11806                                 &sff8472_comp, NULL);
11807                 if (status)
11808                         return -EIO;
11809
11810                 status = i40e_aq_get_phy_register(hw,
11811                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11812                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11813                                 I40E_MODULE_SFF_8472_SWAP,
11814                                 &sff8472_swap, NULL);
11815                 if (status)
11816                         return -EIO;
11817
11818                 /* Check if the module requires address swap to access
11819                  * the other EEPROM memory page.
11820                  */
11821                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11822                         PMD_DRV_LOG(WARNING,
11823                                     "Module address swap to access "
11824                                     "page 0xA2 is not supported.\n");
11825                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11826                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11827                 } else if (sff8472_comp == 0x00) {
11828                         /* Module is not SFF-8472 compliant */
11829                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11830                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11831                 } else {
11832                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11833                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11834                 }
11835                 break;
11836         case I40E_MODULE_TYPE_QSFP_PLUS:
11837                 /* Read from memory page 0. */
11838                 status = i40e_aq_get_phy_register(hw,
11839                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11840                                 0, 1,
11841                                 I40E_MODULE_REVISION_ADDR,
11842                                 &sff8636_rev, NULL);
11843                 if (status)
11844                         return -EIO;
11845                 /* Determine revision compliance byte */
11846                 if (sff8636_rev > 0x02) {
11847                         /* Module is SFF-8636 compliant */
11848                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11849                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11850                 } else {
11851                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11852                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11853                 }
11854                 break;
11855         case I40E_MODULE_TYPE_QSFP28:
11856                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11857                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11858                 break;
11859         default:
11860                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11861                 return -EINVAL;
11862         }
11863         return 0;
11864 }
11865
11866 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11867                                   struct rte_dev_eeprom_info *info)
11868 {
11869         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11870         bool is_sfp = false;
11871         i40e_status status;
11872         uint8_t *data = info->data;
11873         uint32_t value = 0;
11874         uint32_t i;
11875
11876         if (!info || !info->length || !data)
11877                 return -EINVAL;
11878
11879         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11880                 is_sfp = true;
11881
11882         for (i = 0; i < info->length; i++) {
11883                 u32 offset = i + info->offset;
11884                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11885
11886                 /* Check if we need to access the other memory page */
11887                 if (is_sfp) {
11888                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11889                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11890                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11891                         }
11892                 } else {
11893                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11894                                 /* Compute memory page number and offset. */
11895                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11896                                 addr++;
11897                         }
11898                 }
11899                 status = i40e_aq_get_phy_register(hw,
11900                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11901                                 addr, offset, 1, &value, NULL);
11902                 if (status)
11903                         return -EIO;
11904                 data[i] = (uint8_t)value;
11905         }
11906         return 0;
11907 }
11908
11909 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11910                                      struct ether_addr *mac_addr)
11911 {
11912         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11913         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11914         struct i40e_vsi *vsi = pf->main_vsi;
11915         struct i40e_mac_filter_info mac_filter;
11916         struct i40e_mac_filter *f;
11917         int ret;
11918
11919         if (!is_valid_assigned_ether_addr(mac_addr)) {
11920                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11921                 return -EINVAL;
11922         }
11923
11924         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11925                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11926                         break;
11927         }
11928
11929         if (f == NULL) {
11930                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11931                 return -EIO;
11932         }
11933
11934         mac_filter = f->mac_info;
11935         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11936         if (ret != I40E_SUCCESS) {
11937                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11938                 return -EIO;
11939         }
11940         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11941         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11942         if (ret != I40E_SUCCESS) {
11943                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11944                 return -EIO;
11945         }
11946         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11947
11948         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11949                                         mac_addr->addr_bytes, NULL);
11950         if (ret != I40E_SUCCESS) {
11951                 PMD_DRV_LOG(ERR, "Failed to change mac");
11952                 return -EIO;
11953         }
11954
11955         return 0;
11956 }
11957
11958 static int
11959 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11960 {
11961         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11962         struct rte_eth_dev_data *dev_data = pf->dev_data;
11963         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11964         int ret = 0;
11965
11966         /* check if mtu is within the allowed range */
11967         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11968                 return -EINVAL;
11969
11970         /* mtu setting is forbidden if port is start */
11971         if (dev_data->dev_started) {
11972                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11973                             dev_data->port_id);
11974                 return -EBUSY;
11975         }
11976
11977         if (frame_size > ETHER_MAX_LEN)
11978                 dev_data->dev_conf.rxmode.offloads |=
11979                         DEV_RX_OFFLOAD_JUMBO_FRAME;
11980         else
11981                 dev_data->dev_conf.rxmode.offloads &=
11982                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11983
11984         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11985
11986         return ret;
11987 }
11988
11989 /* Restore ethertype filter */
11990 static void
11991 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11992 {
11993         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11994         struct i40e_ethertype_filter_list
11995                 *ethertype_list = &pf->ethertype.ethertype_list;
11996         struct i40e_ethertype_filter *f;
11997         struct i40e_control_filter_stats stats;
11998         uint16_t flags;
11999
12000         TAILQ_FOREACH(f, ethertype_list, rules) {
12001                 flags = 0;
12002                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12003                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12004                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12005                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12006                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12007
12008                 memset(&stats, 0, sizeof(stats));
12009                 i40e_aq_add_rem_control_packet_filter(hw,
12010                                             f->input.mac_addr.addr_bytes,
12011                                             f->input.ether_type,
12012                                             flags, pf->main_vsi->seid,
12013                                             f->queue, 1, &stats, NULL);
12014         }
12015         PMD_DRV_LOG(INFO, "Ethertype filter:"
12016                     " mac_etype_used = %u, etype_used = %u,"
12017                     " mac_etype_free = %u, etype_free = %u",
12018                     stats.mac_etype_used, stats.etype_used,
12019                     stats.mac_etype_free, stats.etype_free);
12020 }
12021
12022 /* Restore tunnel filter */
12023 static void
12024 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12025 {
12026         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12027         struct i40e_vsi *vsi;
12028         struct i40e_pf_vf *vf;
12029         struct i40e_tunnel_filter_list
12030                 *tunnel_list = &pf->tunnel.tunnel_list;
12031         struct i40e_tunnel_filter *f;
12032         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12033         bool big_buffer = 0;
12034
12035         TAILQ_FOREACH(f, tunnel_list, rules) {
12036                 if (!f->is_to_vf)
12037                         vsi = pf->main_vsi;
12038                 else {
12039                         vf = &pf->vfs[f->vf_id];
12040                         vsi = vf->vsi;
12041                 }
12042                 memset(&cld_filter, 0, sizeof(cld_filter));
12043                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
12044                         (struct ether_addr *)&cld_filter.element.outer_mac);
12045                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
12046                         (struct ether_addr *)&cld_filter.element.inner_mac);
12047                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12048                 cld_filter.element.flags = f->input.flags;
12049                 cld_filter.element.tenant_id = f->input.tenant_id;
12050                 cld_filter.element.queue_number = f->queue;
12051                 rte_memcpy(cld_filter.general_fields,
12052                            f->input.general_fields,
12053                            sizeof(f->input.general_fields));
12054
12055                 if (((f->input.flags &
12056                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12057                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12058                     ((f->input.flags &
12059                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12060                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12061                     ((f->input.flags &
12062                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12063                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12064                         big_buffer = 1;
12065
12066                 if (big_buffer)
12067                         i40e_aq_add_cloud_filters_bb(hw,
12068                                         vsi->seid, &cld_filter, 1);
12069                 else
12070                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12071                                                   &cld_filter.element, 1);
12072         }
12073 }
12074
12075 /* Restore rss filter */
12076 static inline void
12077 i40e_rss_filter_restore(struct i40e_pf *pf)
12078 {
12079         struct i40e_rte_flow_rss_conf *conf =
12080                                         &pf->rss_info;
12081         if (conf->conf.queue_num)
12082                 i40e_config_rss_filter(pf, conf, TRUE);
12083 }
12084
12085 static void
12086 i40e_filter_restore(struct i40e_pf *pf)
12087 {
12088         i40e_ethertype_filter_restore(pf);
12089         i40e_tunnel_filter_restore(pf);
12090         i40e_fdir_filter_restore(pf);
12091         i40e_rss_filter_restore(pf);
12092 }
12093
12094 static bool
12095 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12096 {
12097         if (strcmp(dev->device->driver->name, drv->driver.name))
12098                 return false;
12099
12100         return true;
12101 }
12102
12103 bool
12104 is_i40e_supported(struct rte_eth_dev *dev)
12105 {
12106         return is_device_supported(dev, &rte_i40e_pmd);
12107 }
12108
12109 struct i40e_customized_pctype*
12110 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12111 {
12112         int i;
12113
12114         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12115                 if (pf->customized_pctype[i].index == index)
12116                         return &pf->customized_pctype[i];
12117         }
12118         return NULL;
12119 }
12120
12121 static int
12122 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12123                               uint32_t pkg_size, uint32_t proto_num,
12124                               struct rte_pmd_i40e_proto_info *proto,
12125                               enum rte_pmd_i40e_package_op op)
12126 {
12127         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12128         uint32_t pctype_num;
12129         struct rte_pmd_i40e_ptype_info *pctype;
12130         uint32_t buff_size;
12131         struct i40e_customized_pctype *new_pctype = NULL;
12132         uint8_t proto_id;
12133         uint8_t pctype_value;
12134         char name[64];
12135         uint32_t i, j, n;
12136         int ret;
12137
12138         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12139             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12140                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12141                 return -1;
12142         }
12143
12144         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12145                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12146                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12147         if (ret) {
12148                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12149                 return -1;
12150         }
12151         if (!pctype_num) {
12152                 PMD_DRV_LOG(INFO, "No new pctype added");
12153                 return -1;
12154         }
12155
12156         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12157         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12158         if (!pctype) {
12159                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12160                 return -1;
12161         }
12162         /* get information about new pctype list */
12163         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12164                                         (uint8_t *)pctype, buff_size,
12165                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12166         if (ret) {
12167                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12168                 rte_free(pctype);
12169                 return -1;
12170         }
12171
12172         /* Update customized pctype. */
12173         for (i = 0; i < pctype_num; i++) {
12174                 pctype_value = pctype[i].ptype_id;
12175                 memset(name, 0, sizeof(name));
12176                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12177                         proto_id = pctype[i].protocols[j];
12178                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12179                                 continue;
12180                         for (n = 0; n < proto_num; n++) {
12181                                 if (proto[n].proto_id != proto_id)
12182                                         continue;
12183                                 strcat(name, proto[n].name);
12184                                 strcat(name, "_");
12185                                 break;
12186                         }
12187                 }
12188                 name[strlen(name) - 1] = '\0';
12189                 if (!strcmp(name, "GTPC"))
12190                         new_pctype =
12191                                 i40e_find_customized_pctype(pf,
12192                                                       I40E_CUSTOMIZED_GTPC);
12193                 else if (!strcmp(name, "GTPU_IPV4"))
12194                         new_pctype =
12195                                 i40e_find_customized_pctype(pf,
12196                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12197                 else if (!strcmp(name, "GTPU_IPV6"))
12198                         new_pctype =
12199                                 i40e_find_customized_pctype(pf,
12200                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12201                 else if (!strcmp(name, "GTPU"))
12202                         new_pctype =
12203                                 i40e_find_customized_pctype(pf,
12204                                                       I40E_CUSTOMIZED_GTPU);
12205                 if (new_pctype) {
12206                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12207                                 new_pctype->pctype = pctype_value;
12208                                 new_pctype->valid = true;
12209                         } else {
12210                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12211                                 new_pctype->valid = false;
12212                         }
12213                 }
12214         }
12215
12216         rte_free(pctype);
12217         return 0;
12218 }
12219
12220 static int
12221 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12222                              uint32_t pkg_size, uint32_t proto_num,
12223                              struct rte_pmd_i40e_proto_info *proto,
12224                              enum rte_pmd_i40e_package_op op)
12225 {
12226         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12227         uint16_t port_id = dev->data->port_id;
12228         uint32_t ptype_num;
12229         struct rte_pmd_i40e_ptype_info *ptype;
12230         uint32_t buff_size;
12231         uint8_t proto_id;
12232         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12233         uint32_t i, j, n;
12234         bool in_tunnel;
12235         int ret;
12236
12237         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12238             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12239                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12240                 return -1;
12241         }
12242
12243         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12244                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12245                 return 0;
12246         }
12247
12248         /* get information about new ptype num */
12249         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12250                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12251                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12252         if (ret) {
12253                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12254                 return ret;
12255         }
12256         if (!ptype_num) {
12257                 PMD_DRV_LOG(INFO, "No new ptype added");
12258                 return -1;
12259         }
12260
12261         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12262         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12263         if (!ptype) {
12264                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12265                 return -1;
12266         }
12267
12268         /* get information about new ptype list */
12269         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12270                                         (uint8_t *)ptype, buff_size,
12271                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12272         if (ret) {
12273                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12274                 rte_free(ptype);
12275                 return ret;
12276         }
12277
12278         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12279         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12280         if (!ptype_mapping) {
12281                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12282                 rte_free(ptype);
12283                 return -1;
12284         }
12285
12286         /* Update ptype mapping table. */
12287         for (i = 0; i < ptype_num; i++) {
12288                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12289                 ptype_mapping[i].sw_ptype = 0;
12290                 in_tunnel = false;
12291                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12292                         proto_id = ptype[i].protocols[j];
12293                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12294                                 continue;
12295                         for (n = 0; n < proto_num; n++) {
12296                                 if (proto[n].proto_id != proto_id)
12297                                         continue;
12298                                 memset(name, 0, sizeof(name));
12299                                 strcpy(name, proto[n].name);
12300                                 if (!strncasecmp(name, "PPPOE", 5))
12301                                         ptype_mapping[i].sw_ptype |=
12302                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12303                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12304                                          !in_tunnel) {
12305                                         ptype_mapping[i].sw_ptype |=
12306                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12307                                         ptype_mapping[i].sw_ptype |=
12308                                                 RTE_PTYPE_L4_FRAG;
12309                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12310                                            in_tunnel) {
12311                                         ptype_mapping[i].sw_ptype |=
12312                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12313                                         ptype_mapping[i].sw_ptype |=
12314                                                 RTE_PTYPE_INNER_L4_FRAG;
12315                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12316                                         ptype_mapping[i].sw_ptype |=
12317                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12318                                         in_tunnel = true;
12319                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12320                                            !in_tunnel)
12321                                         ptype_mapping[i].sw_ptype |=
12322                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12323                                 else if (!strncasecmp(name, "IPV4", 4) &&
12324                                          in_tunnel)
12325                                         ptype_mapping[i].sw_ptype |=
12326                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12327                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12328                                          !in_tunnel) {
12329                                         ptype_mapping[i].sw_ptype |=
12330                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12331                                         ptype_mapping[i].sw_ptype |=
12332                                                 RTE_PTYPE_L4_FRAG;
12333                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12334                                            in_tunnel) {
12335                                         ptype_mapping[i].sw_ptype |=
12336                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12337                                         ptype_mapping[i].sw_ptype |=
12338                                                 RTE_PTYPE_INNER_L4_FRAG;
12339                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12340                                         ptype_mapping[i].sw_ptype |=
12341                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12342                                         in_tunnel = true;
12343                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12344                                            !in_tunnel)
12345                                         ptype_mapping[i].sw_ptype |=
12346                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12347                                 else if (!strncasecmp(name, "IPV6", 4) &&
12348                                          in_tunnel)
12349                                         ptype_mapping[i].sw_ptype |=
12350                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12351                                 else if (!strncasecmp(name, "UDP", 3) &&
12352                                          !in_tunnel)
12353                                         ptype_mapping[i].sw_ptype |=
12354                                                 RTE_PTYPE_L4_UDP;
12355                                 else if (!strncasecmp(name, "UDP", 3) &&
12356                                          in_tunnel)
12357                                         ptype_mapping[i].sw_ptype |=
12358                                                 RTE_PTYPE_INNER_L4_UDP;
12359                                 else if (!strncasecmp(name, "TCP", 3) &&
12360                                          !in_tunnel)
12361                                         ptype_mapping[i].sw_ptype |=
12362                                                 RTE_PTYPE_L4_TCP;
12363                                 else if (!strncasecmp(name, "TCP", 3) &&
12364                                          in_tunnel)
12365                                         ptype_mapping[i].sw_ptype |=
12366                                                 RTE_PTYPE_INNER_L4_TCP;
12367                                 else if (!strncasecmp(name, "SCTP", 4) &&
12368                                          !in_tunnel)
12369                                         ptype_mapping[i].sw_ptype |=
12370                                                 RTE_PTYPE_L4_SCTP;
12371                                 else if (!strncasecmp(name, "SCTP", 4) &&
12372                                          in_tunnel)
12373                                         ptype_mapping[i].sw_ptype |=
12374                                                 RTE_PTYPE_INNER_L4_SCTP;
12375                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12376                                           !strncasecmp(name, "ICMPV6", 6)) &&
12377                                          !in_tunnel)
12378                                         ptype_mapping[i].sw_ptype |=
12379                                                 RTE_PTYPE_L4_ICMP;
12380                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12381                                           !strncasecmp(name, "ICMPV6", 6)) &&
12382                                          in_tunnel)
12383                                         ptype_mapping[i].sw_ptype |=
12384                                                 RTE_PTYPE_INNER_L4_ICMP;
12385                                 else if (!strncasecmp(name, "GTPC", 4)) {
12386                                         ptype_mapping[i].sw_ptype |=
12387                                                 RTE_PTYPE_TUNNEL_GTPC;
12388                                         in_tunnel = true;
12389                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12390                                         ptype_mapping[i].sw_ptype |=
12391                                                 RTE_PTYPE_TUNNEL_GTPU;
12392                                         in_tunnel = true;
12393                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12394                                         ptype_mapping[i].sw_ptype |=
12395                                                 RTE_PTYPE_TUNNEL_GRENAT;
12396                                         in_tunnel = true;
12397                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12398                                            !strncasecmp(name, "L2TPV2", 6)) {
12399                                         ptype_mapping[i].sw_ptype |=
12400                                                 RTE_PTYPE_TUNNEL_L2TP;
12401                                         in_tunnel = true;
12402                                 }
12403
12404                                 break;
12405                         }
12406                 }
12407         }
12408
12409         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12410                                                 ptype_num, 0);
12411         if (ret)
12412                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12413
12414         rte_free(ptype_mapping);
12415         rte_free(ptype);
12416         return ret;
12417 }
12418
12419 void
12420 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12421                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12422 {
12423         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12424         uint32_t proto_num;
12425         struct rte_pmd_i40e_proto_info *proto;
12426         uint32_t buff_size;
12427         uint32_t i;
12428         int ret;
12429
12430         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12431             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12432                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12433                 return;
12434         }
12435
12436         /* get information about protocol number */
12437         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12438                                        (uint8_t *)&proto_num, sizeof(proto_num),
12439                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12440         if (ret) {
12441                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12442                 return;
12443         }
12444         if (!proto_num) {
12445                 PMD_DRV_LOG(INFO, "No new protocol added");
12446                 return;
12447         }
12448
12449         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12450         proto = rte_zmalloc("new_proto", buff_size, 0);
12451         if (!proto) {
12452                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12453                 return;
12454         }
12455
12456         /* get information about protocol list */
12457         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12458                                         (uint8_t *)proto, buff_size,
12459                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12460         if (ret) {
12461                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12462                 rte_free(proto);
12463                 return;
12464         }
12465
12466         /* Check if GTP is supported. */
12467         for (i = 0; i < proto_num; i++) {
12468                 if (!strncmp(proto[i].name, "GTP", 3)) {
12469                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12470                                 pf->gtp_support = true;
12471                         else
12472                                 pf->gtp_support = false;
12473                         break;
12474                 }
12475         }
12476
12477         /* Update customized pctype info */
12478         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12479                                             proto_num, proto, op);
12480         if (ret)
12481                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12482
12483         /* Update customized ptype info */
12484         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12485                                            proto_num, proto, op);
12486         if (ret)
12487                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12488
12489         rte_free(proto);
12490 }
12491
12492 /* Create a QinQ cloud filter
12493  *
12494  * The Fortville NIC has limited resources for tunnel filters,
12495  * so we can only reuse existing filters.
12496  *
12497  * In step 1 we define which Field Vector fields can be used for
12498  * filter types.
12499  * As we do not have the inner tag defined as a field,
12500  * we have to define it first, by reusing one of L1 entries.
12501  *
12502  * In step 2 we are replacing one of existing filter types with
12503  * a new one for QinQ.
12504  * As we reusing L1 and replacing L2, some of the default filter
12505  * types will disappear,which depends on L1 and L2 entries we reuse.
12506  *
12507  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12508  *
12509  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12510  *              later when we define the cloud filter.
12511  *      a.      Valid_flags.replace_cloud = 0
12512  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12513  *      c.      New_filter = 0x10
12514  *      d.      TR bit = 0xff (optional, not used here)
12515  *      e.      Buffer – 2 entries:
12516  *              i.      Byte 0 = 8 (outer vlan FV index).
12517  *                      Byte 1 = 0 (rsv)
12518  *                      Byte 2-3 = 0x0fff
12519  *              ii.     Byte 0 = 37 (inner vlan FV index).
12520  *                      Byte 1 =0 (rsv)
12521  *                      Byte 2-3 = 0x0fff
12522  *
12523  * Step 2:
12524  * 2.   Create cloud filter using two L1 filters entries: stag and
12525  *              new filter(outer vlan+ inner vlan)
12526  *      a.      Valid_flags.replace_cloud = 1
12527  *      b.      Old_filter = 1 (instead of outer IP)
12528  *      c.      New_filter = 0x10
12529  *      d.      Buffer – 2 entries:
12530  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12531  *                      Byte 1-3 = 0 (rsv)
12532  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12533  *                      Byte 9-11 = 0 (rsv)
12534  */
12535 static int
12536 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12537 {
12538         int ret = -ENOTSUP;
12539         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12540         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12541         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12542         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12543
12544         if (pf->support_multi_driver) {
12545                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12546                 return ret;
12547         }
12548
12549         /* Init */
12550         memset(&filter_replace, 0,
12551                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12552         memset(&filter_replace_buf, 0,
12553                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12554
12555         /* create L1 filter */
12556         filter_replace.old_filter_type =
12557                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12558         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12559         filter_replace.tr_bit = 0;
12560
12561         /* Prepare the buffer, 2 entries */
12562         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12563         filter_replace_buf.data[0] |=
12564                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12565         /* Field Vector 12b mask */
12566         filter_replace_buf.data[2] = 0xff;
12567         filter_replace_buf.data[3] = 0x0f;
12568         filter_replace_buf.data[4] =
12569                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12570         filter_replace_buf.data[4] |=
12571                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12572         /* Field Vector 12b mask */
12573         filter_replace_buf.data[6] = 0xff;
12574         filter_replace_buf.data[7] = 0x0f;
12575         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12576                         &filter_replace_buf);
12577         if (ret != I40E_SUCCESS)
12578                 return ret;
12579
12580         if (filter_replace.old_filter_type !=
12581             filter_replace.new_filter_type)
12582                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12583                             " original: 0x%x, new: 0x%x",
12584                             dev->device->name,
12585                             filter_replace.old_filter_type,
12586                             filter_replace.new_filter_type);
12587
12588         /* Apply the second L2 cloud filter */
12589         memset(&filter_replace, 0,
12590                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12591         memset(&filter_replace_buf, 0,
12592                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12593
12594         /* create L2 filter, input for L2 filter will be L1 filter  */
12595         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12596         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12597         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12598
12599         /* Prepare the buffer, 2 entries */
12600         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12601         filter_replace_buf.data[0] |=
12602                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12603         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12604         filter_replace_buf.data[4] |=
12605                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12606         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12607                         &filter_replace_buf);
12608         if (!ret && (filter_replace.old_filter_type !=
12609                      filter_replace.new_filter_type))
12610                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12611                             " original: 0x%x, new: 0x%x",
12612                             dev->device->name,
12613                             filter_replace.old_filter_type,
12614                             filter_replace.new_filter_type);
12615
12616         return ret;
12617 }
12618
12619 int
12620 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12621                    const struct rte_flow_action_rss *in)
12622 {
12623         if (in->key_len > RTE_DIM(out->key) ||
12624             in->queue_num > RTE_DIM(out->queue))
12625                 return -EINVAL;
12626         if (!in->key && in->key_len)
12627                 return -EINVAL;
12628         out->conf = (struct rte_flow_action_rss){
12629                 .func = in->func,
12630                 .level = in->level,
12631                 .types = in->types,
12632                 .key_len = in->key_len,
12633                 .queue_num = in->queue_num,
12634                 .queue = memcpy(out->queue, in->queue,
12635                                 sizeof(*in->queue) * in->queue_num),
12636         };
12637         if (in->key)
12638                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12639         return 0;
12640 }
12641
12642 int
12643 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12644                      const struct rte_flow_action_rss *with)
12645 {
12646         return (comp->func == with->func &&
12647                 comp->level == with->level &&
12648                 comp->types == with->types &&
12649                 comp->key_len == with->key_len &&
12650                 comp->queue_num == with->queue_num &&
12651                 !memcmp(comp->key, with->key, with->key_len) &&
12652                 !memcmp(comp->queue, with->queue,
12653                         sizeof(*with->queue) * with->queue_num));
12654 }
12655
12656 int
12657 i40e_config_rss_filter(struct i40e_pf *pf,
12658                 struct i40e_rte_flow_rss_conf *conf, bool add)
12659 {
12660         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12661         uint32_t i, lut = 0;
12662         uint16_t j, num;
12663         struct rte_eth_rss_conf rss_conf = {
12664                 .rss_key = conf->conf.key_len ?
12665                         (void *)(uintptr_t)conf->conf.key : NULL,
12666                 .rss_key_len = conf->conf.key_len,
12667                 .rss_hf = conf->conf.types,
12668         };
12669         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12670
12671         if (!add) {
12672                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12673                         i40e_pf_disable_rss(pf);
12674                         memset(rss_info, 0,
12675                                 sizeof(struct i40e_rte_flow_rss_conf));
12676                         return 0;
12677                 }
12678                 return -EINVAL;
12679         }
12680
12681         if (rss_info->conf.queue_num)
12682                 return -EINVAL;
12683
12684         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12685          * It's necessary to calculate the actual PF queues that are configured.
12686          */
12687         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12688                 num = i40e_pf_calc_configured_queues_num(pf);
12689         else
12690                 num = pf->dev_data->nb_rx_queues;
12691
12692         num = RTE_MIN(num, conf->conf.queue_num);
12693         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12694                         num);
12695
12696         if (num == 0) {
12697                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12698                 return -ENOTSUP;
12699         }
12700
12701         /* Fill in redirection table */
12702         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12703                 if (j == num)
12704                         j = 0;
12705                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12706                         hw->func_caps.rss_table_entry_width) - 1));
12707                 if ((i & 3) == 3)
12708                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12709         }
12710
12711         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12712                 i40e_pf_disable_rss(pf);
12713                 return 0;
12714         }
12715         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12716                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12717                 /* Random default keys */
12718                 static uint32_t rss_key_default[] = {0x6b793944,
12719                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12720                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12721                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12722
12723                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12724                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12725                                                         sizeof(uint32_t);
12726         }
12727
12728         i40e_hw_rss_hash_set(pf, &rss_conf);
12729
12730         if (i40e_rss_conf_init(rss_info, &conf->conf))
12731                 return -EINVAL;
12732
12733         return 0;
12734 }
12735
12736 RTE_INIT(i40e_init_log)
12737 {
12738         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12739         if (i40e_logtype_init >= 0)
12740                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12741         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12742         if (i40e_logtype_driver >= 0)
12743                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12744 }
12745
12746 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12747                               ETH_I40E_FLOATING_VEB_ARG "=1"
12748                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12749                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12750                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12751                               ETH_I40E_USE_LATEST_VEC "=0|1");