drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_eth_ctrl.h>
  28 #include <rte_tailq.h>
  29 #include <rte_hash_crc.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45
  46 #define I40E_CLEAR_PXE_WAIT_MS     200
  47
  48 /* Maximun number of capability elements */
  49 #define I40E_MAX_CAP_ELE_NUM       128
  50
  51 /* Wait count and interval */
  52 #define I40E_CHK_Q_ENA_COUNT       1000
  53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  54
  55 /* Maximun number of VSI */
  56 #define I40E_MAX_NUM_VSIS          (384UL)
  57
  58 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  59
  60 /* Flow control default timer */
  61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  62
  63 /* Flow control enable fwd bit */
  64 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  65
  66 /* Receive Packet Buffer size */
  67 #define I40E_RXPBSIZE (968 * 1024)
  68
  69 /* Kilobytes shift */
  70 #define I40E_KILOSHIFT 10
  71
  72 /* Flow control default high water */
  73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  74
  75 /* Flow control default low water */
  76 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Receive Average Packet Size in Byte*/
  79 #define I40E_PACKET_AVERAGE_SIZE 128
  80
  81 /* Mask of PF interrupt causes */
  82 #define I40E_PFINT_ICR0_ENA_MASK ( \
  83                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  84                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  85                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  86                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  87                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  92
  93 #define I40E_FLOW_TYPES ( \
  94         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  99         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 104         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 105
 106 /* Additional timesync values. */
 107 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 108 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 109 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 110 #define I40E_PRTTSYN_TSYNENA     0x80000000
 111 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 112 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 113
 114 /**
 115  * Below are values for writing un-exposed registers suggested
 116  * by silicon experts
 117  */
 118 /* Destination MAC address */
 119 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 120 /* Source MAC address */
 121 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 123 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 125 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 126 /* Single VLAN tag in the inner L2 header */
 127 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 128 /* Source IPv4 address */
 129 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 130 /* Destination IPv4 address */
 131 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 132 /* Source IPv4 address for X722 */
 133 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 134 /* Destination IPv4 address for X722 */
 135 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 136 /* IPv4 Protocol for X722 */
 137 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 138 /* IPv4 Time to Live for X722 */
 139 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 140 /* IPv4 Type of Service (TOS) */
 141 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 142 /* IPv4 Protocol */
 143 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 144 /* IPv4 Time to Live */
 145 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 146 /* Source IPv6 address */
 147 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 148 /* Destination IPv6 address */
 149 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 150 /* IPv6 Traffic Class (TC) */
 151 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 152 /* IPv6 Next Header */
 153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 154 /* IPv6 Hop Limit */
 155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 156 /* Source L4 port */
 157 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 158 /* Destination L4 port */
 159 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 160 /* SCTP verification tag */
 161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 164 /* Source port of tunneling UDP */
 165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 166 /* Destination port of tunneling UDP */
 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 168 /* UDP Tunneling ID, NVGRE/GRE key */
 169 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 170 /* Last ether type */
 171 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 172 /* Tunneling outer destination IPv4 address */
 173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 174 /* Tunneling outer destination IPv6 address */
 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 176 /* 1st word of flex payload */
 177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 178 /* 2nd word of flex payload */
 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 180 /* 3rd word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 182 /* 4th word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 184 /* 5th word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 186 /* 6th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 188 /* 7th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 190 /* 8th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 192 /* all 8 words flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 194 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 195
 196 #define I40E_TRANSLATE_INSET 0
 197 #define I40E_TRANSLATE_REG   1
 198
 199 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 200 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 201 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 202 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 204 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 205
 206 /* PCI offset for querying capability */
 207 #define PCI_DEV_CAP_REG            0xA4
 208 /* PCI offset for enabling/disabling Extended Tag */
 209 #define PCI_DEV_CTRL_REG           0xA8
 210 /* Bit mask of Extended Tag capability */
 211 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 212 /* Bit shift of Extended Tag enable/disable */
 213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 214 /* Bit mask of Extended Tag enable/disable */
 215 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 216
 217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 219 static int i40e_dev_configure(struct rte_eth_dev *dev);
 220 static int i40e_dev_start(struct rte_eth_dev *dev);
 221 static void i40e_dev_stop(struct rte_eth_dev *dev);
 222 static void i40e_dev_close(struct rte_eth_dev *dev);
 223 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_stats *stats);
 232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 233                                struct rte_eth_xstat *xstats, unsigned n);
 234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 235                                      struct rte_eth_xstat_name *xstats_names,
 236                                      unsigned limit);
 237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 239                                             uint16_t queue_id,
 240                                             uint8_t stat_idx,
 241                                             uint8_t is_rx);
 242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 243                                 char *fw_version, size_t fw_size);
 244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 245                               struct rte_eth_dev_info *dev_info);
 246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 247                                 uint16_t vlan_id,
 248                                 int on);
 249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 250                               enum rte_vlan_type vlan_type,
 251                               uint16_t tpid);
 252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                                       uint16_t queue,
 255                                       int on);
 256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 260                               struct rte_eth_fc_conf *fc_conf);
 261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 264                                        struct rte_eth_pfc_conf *pfc_conf);
 265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 266                             struct ether_addr *mac_addr,
 267                             uint32_t index,
 268                             uint32_t pool);
 269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 271                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 272                                     uint16_t reta_size);
 273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 274                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 275                                    uint16_t reta_size);
 276
 277 static int i40e_get_cap(struct i40e_hw *hw);
 278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 279 static int i40e_pf_setup(struct i40e_pf *pf);
 280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 284                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 285 static void i40e_stat_update_48(struct i40e_hw *hw,
 286                                uint32_t hireg,
 287                                uint32_t loreg,
 288                                bool offset_loaded,
 289                                uint64_t *offset,
 290                                uint64_t *stat);
 291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 292 static void i40e_dev_interrupt_handler(void *param);
 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 294                                 uint32_t base, uint32_t num);
 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 297                         uint32_t base);
 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 299                         uint16_t num);
 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 301 static int i40e_veb_release(struct i40e_veb *veb);
 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 303                                                 struct i40e_vsi *vsi);
 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static int i40e_get_module_info(struct rte_eth_dev *dev,
 374                                 struct rte_eth_dev_module_info *modinfo);
 375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 376                                   struct rte_dev_eeprom_info *info);
 377
 378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 379                                       struct ether_addr *mac_addr);
 380
 381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 382
 383 static int i40e_ethertype_filter_convert(
 384         const struct rte_eth_ethertype_filter *input,
 385         struct i40e_ethertype_filter *filter);
 386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 387                                    struct i40e_ethertype_filter *filter);
 388
 389 static int i40e_tunnel_filter_convert(
 390         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 391         struct i40e_tunnel_filter *tunnel_filter);
 392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 393                                 struct i40e_tunnel_filter *tunnel_filter);
 394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 395
 396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 398 static void i40e_filter_restore(struct i40e_pf *pf);
 399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 400
 401 int i40e_logtype_init;
 402 int i40e_logtype_driver;
 403
 404 static const struct rte_pci_id pci_id_i40e_map[] = {
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 425         { .vendor_id = 0, /* sentinel */ },
 426 };
 427
 428 static const struct eth_dev_ops i40e_eth_dev_ops = {
 429         .dev_configure                = i40e_dev_configure,
 430         .dev_start                    = i40e_dev_start,
 431         .dev_stop                     = i40e_dev_stop,
 432         .dev_close                    = i40e_dev_close,
 433         .dev_reset                    = i40e_dev_reset,
 434         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 435         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 436         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 437         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 438         .dev_set_link_up              = i40e_dev_set_link_up,
 439         .dev_set_link_down            = i40e_dev_set_link_down,
 440         .link_update                  = i40e_dev_link_update,
 441         .stats_get                    = i40e_dev_stats_get,
 442         .xstats_get                   = i40e_dev_xstats_get,
 443         .xstats_get_names             = i40e_dev_xstats_get_names,
 444         .stats_reset                  = i40e_dev_stats_reset,
 445         .xstats_reset                 = i40e_dev_stats_reset,
 446         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 447         .fw_version_get               = i40e_fw_version_get,
 448         .dev_infos_get                = i40e_dev_info_get,
 449         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 450         .vlan_filter_set              = i40e_vlan_filter_set,
 451         .vlan_tpid_set                = i40e_vlan_tpid_set,
 452         .vlan_offload_set             = i40e_vlan_offload_set,
 453         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 454         .vlan_pvid_set                = i40e_vlan_pvid_set,
 455         .rx_queue_start               = i40e_dev_rx_queue_start,
 456         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 457         .tx_queue_start               = i40e_dev_tx_queue_start,
 458         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 459         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 460         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 461         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 462         .rx_queue_release             = i40e_dev_rx_queue_release,
 463         .rx_queue_count               = i40e_dev_rx_queue_count,
 464         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 465         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 466         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 467         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 468         .tx_queue_release             = i40e_dev_tx_queue_release,
 469         .dev_led_on                   = i40e_dev_led_on,
 470         .dev_led_off                  = i40e_dev_led_off,
 471         .flow_ctrl_get                = i40e_flow_ctrl_get,
 472         .flow_ctrl_set                = i40e_flow_ctrl_set,
 473         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 474         .mac_addr_add                 = i40e_macaddr_add,
 475         .mac_addr_remove              = i40e_macaddr_remove,
 476         .reta_update                  = i40e_dev_rss_reta_update,
 477         .reta_query                   = i40e_dev_rss_reta_query,
 478         .rss_hash_update              = i40e_dev_rss_hash_update,
 479         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 480         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 481         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 482         .filter_ctrl                  = i40e_dev_filter_ctrl,
 483         .rxq_info_get                 = i40e_rxq_info_get,
 484         .txq_info_get                 = i40e_txq_info_get,
 485         .mirror_rule_set              = i40e_mirror_rule_set,
 486         .mirror_rule_reset            = i40e_mirror_rule_reset,
 487         .timesync_enable              = i40e_timesync_enable,
 488         .timesync_disable             = i40e_timesync_disable,
 489         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 490         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 491         .get_dcb_info                 = i40e_dev_get_dcb_info,
 492         .timesync_adjust_time         = i40e_timesync_adjust_time,
 493         .timesync_read_time           = i40e_timesync_read_time,
 494         .timesync_write_time          = i40e_timesync_write_time,
 495         .get_reg                      = i40e_get_regs,
 496         .get_eeprom_length            = i40e_get_eeprom_length,
 497         .get_eeprom                   = i40e_get_eeprom,
 498         .get_module_info              = i40e_get_module_info,
 499         .get_module_eeprom            = i40e_get_module_eeprom,
 500         .mac_addr_set                 = i40e_set_default_mac_addr,
 501         .mtu_set                      = i40e_dev_mtu_set,
 502         .tm_ops_get                   = i40e_tm_ops_get,
 503 };
 504
 505 /* store statistics names and its offset in stats structure */
 506 struct rte_i40e_xstats_name_off {
 507         char name[RTE_ETH_XSTATS_NAME_SIZE];
 508         unsigned offset;
 509 };
 510
 511 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 512         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 513         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 514         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 515         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 516         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 517                 rx_unknown_protocol)},
 518         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 519         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 520         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 521         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 522 };
 523
 524 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 525                 sizeof(rte_i40e_stats_strings[0]))
 526
 527 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 528         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 529                 tx_dropped_link_down)},
 530         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 531         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 532                 illegal_bytes)},
 533         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 534         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 535                 mac_local_faults)},
 536         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 537                 mac_remote_faults)},
 538         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 539                 rx_length_errors)},
 540         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 541         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 542         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 543         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 544         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 545         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 546                 rx_size_127)},
 547         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 548                 rx_size_255)},
 549         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 550                 rx_size_511)},
 551         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 552                 rx_size_1023)},
 553         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 554                 rx_size_1522)},
 555         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 556                 rx_size_big)},
 557         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 558                 rx_undersize)},
 559         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 560                 rx_oversize)},
 561         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 562                 mac_short_packet_dropped)},
 563         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 564                 rx_fragments)},
 565         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 566         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 567         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 568                 tx_size_127)},
 569         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 570                 tx_size_255)},
 571         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 572                 tx_size_511)},
 573         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 574                 tx_size_1023)},
 575         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 576                 tx_size_1522)},
 577         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 578                 tx_size_big)},
 579         {"rx_flow_director_atr_match_packets",
 580                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 581         {"rx_flow_director_sb_match_packets",
 582                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 583         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 584                 tx_lpi_status)},
 585         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 586                 rx_lpi_status)},
 587         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 588                 tx_lpi_count)},
 589         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 590                 rx_lpi_count)},
 591 };
 592
 593 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 594                 sizeof(rte_i40e_hw_port_strings[0]))
 595
 596 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 597         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 598                 priority_xon_rx)},
 599         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 600                 priority_xoff_rx)},
 601 };
 602
 603 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 604                 sizeof(rte_i40e_rxq_prio_strings[0]))
 605
 606 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 607         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 608                 priority_xon_tx)},
 609         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xoff_tx)},
 611         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xon_2_xoff)},
 613 };
 614
 615 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 616                 sizeof(rte_i40e_txq_prio_strings[0]))
 617
 618 static int
 619 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 620         struct rte_pci_device *pci_dev)
 621 {
 622         char name[RTE_ETH_NAME_MAX_LEN];
 623         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 624         int i, retval;
 625
 626         if (pci_dev->device.devargs) {
 627                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 628                                 &eth_da);
 629                 if (retval)
 630                         return retval;
 631         }
 632
 633         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 634                 sizeof(struct i40e_adapter),
 635                 eth_dev_pci_specific_init, pci_dev,
 636                 eth_i40e_dev_init, NULL);
 637
 638         if (retval || eth_da.nb_representor_ports < 1)
 639                 return retval;
 640
 641         /* probe VF representor ports */
 642         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 643                 pci_dev->device.name);
 644
 645         if (pf_ethdev == NULL)
 646                 return -ENODEV;
 647
 648         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 649                 struct i40e_vf_representor representor = {
 650                         .vf_id = eth_da.representor_ports[i],
 651                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 652                                 pf_ethdev->data->dev_private)->switch_domain_id,
 653                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 654                                 pf_ethdev->data->dev_private)
 655                 };
 656
 657                 /* representor port net_bdf_port */
 658                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 659                         pci_dev->device.name, eth_da.representor_ports[i]);
 660
 661                 retval = rte_eth_dev_create(&pci_dev->device, name,
 662                         sizeof(struct i40e_vf_representor), NULL, NULL,
 663                         i40e_vf_representor_init, &representor);
 664
 665                 if (retval)
 666                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 667                                 "representor %s.", name);
 668         }
 669
 670         return 0;
 671 }
 672
 673 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 674 {
 675         struct rte_eth_dev *ethdev;
 676
 677         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 678         if (!ethdev)
 679                 return -ENODEV;
 680
 681
 682         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 683                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 684         else
 685                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 686 }
 687
 688 static struct rte_pci_driver rte_i40e_pmd = {
 689         .id_table = pci_id_i40e_map,
 690         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 691                      RTE_PCI_DRV_IOVA_AS_VA,
 692         .probe = eth_i40e_pci_probe,
 693         .remove = eth_i40e_pci_remove,
 694 };
 695
 696 static inline void
 697 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 698                          uint32_t reg_val)
 699 {
 700         uint32_t ori_reg_val;
 701         struct rte_eth_dev *dev;
 702
 703         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 704         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 705         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 706         if (ori_reg_val != reg_val)
 707                 PMD_DRV_LOG(WARNING,
 708                             "i40e device %s changed global register [0x%08x]."
 709                             " original: 0x%08x, new: 0x%08x",
 710                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 711 }
 712
 713 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 714 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 715 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 716
 717 #ifndef I40E_GLQF_ORT
 718 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 719 #endif
 720 #ifndef I40E_GLQF_PIT
 721 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 722 #endif
 723 #ifndef I40E_GLQF_L3_MAP
 724 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 725 #endif
 726
 727 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 728 {
 729         /*
 730          * Initialize registers for parsing packet type of QinQ
 731          * This should be removed from code once proper
 732          * configuration API is added to avoid configuration conflicts
 733          * between ports of the same device.
 734          */
 735         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 736         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 737 }
 738
 739 static inline void i40e_config_automask(struct i40e_pf *pf)
 740 {
 741         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 742         uint32_t val;
 743
 744         /* INTENA flag is not auto-cleared for interrupt */
 745         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 746         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 747                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 748
 749         /* If support multi-driver, PF will use INT0. */
 750         if (!pf->support_multi_driver)
 751                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 752
 753         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 754 }
 755
 756 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 757
 758 /*
 759  * Add a ethertype filter to drop all flow control frames transmitted
 760  * from VSIs.
 761 */
 762 static void
 763 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 764 {
 765         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 766         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 767                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 768                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 769         int ret;
 770
 771         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 772                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 773                                 pf->main_vsi_seid, 0,
 774                                 TRUE, NULL, NULL);
 775         if (ret)
 776                 PMD_INIT_LOG(ERR,
 777                         "Failed to add filter to drop flow control frames from VSIs.");
 778 }
 779
 780 static int
 781 floating_veb_list_handler(__rte_unused const char *key,
 782                           const char *floating_veb_value,
 783                           void *opaque)
 784 {
 785         int idx = 0;
 786         unsigned int count = 0;
 787         char *end = NULL;
 788         int min, max;
 789         bool *vf_floating_veb = opaque;
 790
 791         while (isblank(*floating_veb_value))
 792                 floating_veb_value++;
 793
 794         /* Reset floating VEB configuration for VFs */
 795         for (idx = 0; idx < I40E_MAX_VF; idx++)
 796                 vf_floating_veb[idx] = false;
 797
 798         min = I40E_MAX_VF;
 799         do {
 800                 while (isblank(*floating_veb_value))
 801                         floating_veb_value++;
 802                 if (*floating_veb_value == '\0')
 803                         return -1;
 804                 errno = 0;
 805                 idx = strtoul(floating_veb_value, &end, 10);
 806                 if (errno || end == NULL)
 807                         return -1;
 808                 while (isblank(*end))
 809                         end++;
 810                 if (*end == '-') {
 811                         min = idx;
 812                 } else if ((*end == ';') || (*end == '\0')) {
 813                         max = idx;
 814                         if (min == I40E_MAX_VF)
 815                                 min = idx;
 816                         if (max >= I40E_MAX_VF)
 817                                 max = I40E_MAX_VF - 1;
 818                         for (idx = min; idx <= max; idx++) {
 819                                 vf_floating_veb[idx] = true;
 820                                 count++;
 821                         }
 822                         min = I40E_MAX_VF;
 823                 } else {
 824                         return -1;
 825                 }
 826                 floating_veb_value = end + 1;
 827         } while (*end != '\0');
 828
 829         if (count == 0)
 830                 return -1;
 831
 832         return 0;
 833 }
 834
 835 static void
 836 config_vf_floating_veb(struct rte_devargs *devargs,
 837                        uint16_t floating_veb,
 838                        bool *vf_floating_veb)
 839 {
 840         struct rte_kvargs *kvlist;
 841         int i;
 842         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 843
 844         if (!floating_veb)
 845                 return;
 846         /* All the VFs attach to the floating VEB by default
 847          * when the floating VEB is enabled.
 848          */
 849         for (i = 0; i < I40E_MAX_VF; i++)
 850                 vf_floating_veb[i] = true;
 851
 852         if (devargs == NULL)
 853                 return;
 854
 855         kvlist = rte_kvargs_parse(devargs->args, NULL);
 856         if (kvlist == NULL)
 857                 return;
 858
 859         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 860                 rte_kvargs_free(kvlist);
 861                 return;
 862         }
 863         /* When the floating_veb_list parameter exists, all the VFs
 864          * will attach to the legacy VEB firstly, then configure VFs
 865          * to the floating VEB according to the floating_veb_list.
 866          */
 867         if (rte_kvargs_process(kvlist, floating_veb_list,
 868                                floating_veb_list_handler,
 869                                vf_floating_veb) < 0) {
 870                 rte_kvargs_free(kvlist);
 871                 return;
 872         }
 873         rte_kvargs_free(kvlist);
 874 }
 875
 876 static int
 877 i40e_check_floating_handler(__rte_unused const char *key,
 878                             const char *value,
 879                             __rte_unused void *opaque)
 880 {
 881         if (strcmp(value, "1"))
 882                 return -1;
 883
 884         return 0;
 885 }
 886
 887 static int
 888 is_floating_veb_supported(struct rte_devargs *devargs)
 889 {
 890         struct rte_kvargs *kvlist;
 891         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 892
 893         if (devargs == NULL)
 894                 return 0;
 895
 896         kvlist = rte_kvargs_parse(devargs->args, NULL);
 897         if (kvlist == NULL)
 898                 return 0;
 899
 900         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 901                 rte_kvargs_free(kvlist);
 902                 return 0;
 903         }
 904         /* Floating VEB is enabled when there's key-value:
 905          * enable_floating_veb=1
 906          */
 907         if (rte_kvargs_process(kvlist, floating_veb_key,
 908                                i40e_check_floating_handler, NULL) < 0) {
 909                 rte_kvargs_free(kvlist);
 910                 return 0;
 911         }
 912         rte_kvargs_free(kvlist);
 913
 914         return 1;
 915 }
 916
 917 static void
 918 config_floating_veb(struct rte_eth_dev *dev)
 919 {
 920         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 921         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 922         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 923
 924         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 925
 926         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 927                 pf->floating_veb =
 928                         is_floating_veb_supported(pci_dev->device.devargs);
 929                 config_vf_floating_veb(pci_dev->device.devargs,
 930                                        pf->floating_veb,
 931                                        pf->floating_veb_list);
 932         } else {
 933                 pf->floating_veb = false;
 934         }
 935 }
 936
 937 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 938 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 939
 940 static int
 941 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 942 {
 943         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 944         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 945         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 946         int ret;
 947
 948         struct rte_hash_parameters ethertype_hash_params = {
 949                 .name = ethertype_hash_name,
 950                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 951                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 952                 .hash_func = rte_hash_crc,
 953                 .hash_func_init_val = 0,
 954                 .socket_id = rte_socket_id(),
 955         };
 956
 957         /* Initialize ethertype filter rule list and hash */
 958         TAILQ_INIT(&ethertype_rule->ethertype_list);
 959         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 960                  "ethertype_%s", dev->device->name);
 961         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 962         if (!ethertype_rule->hash_table) {
 963                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 964                 return -EINVAL;
 965         }
 966         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 967                                        sizeof(struct i40e_ethertype_filter *) *
 968                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 969                                        0);
 970         if (!ethertype_rule->hash_map) {
 971                 PMD_INIT_LOG(ERR,
 972                              "Failed to allocate memory for ethertype hash map!");
 973                 ret = -ENOMEM;
 974                 goto err_ethertype_hash_map_alloc;
 975         }
 976
 977         return 0;
 978
 979 err_ethertype_hash_map_alloc:
 980         rte_hash_free(ethertype_rule->hash_table);
 981
 982         return ret;
 983 }
 984
 985 static int
 986 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 987 {
 988         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 989         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 990         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 991         int ret;
 992
 993         struct rte_hash_parameters tunnel_hash_params = {
 994                 .name = tunnel_hash_name,
 995                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 996                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 997                 .hash_func = rte_hash_crc,
 998                 .hash_func_init_val = 0,
 999                 .socket_id = rte_socket_id(),
1000         };
1001
1002         /* Initialize tunnel filter rule list and hash */
1003         TAILQ_INIT(&tunnel_rule->tunnel_list);
1004         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1005                  "tunnel_%s", dev->device->name);
1006         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1007         if (!tunnel_rule->hash_table) {
1008                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1009                 return -EINVAL;
1010         }
1011         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1012                                     sizeof(struct i40e_tunnel_filter *) *
1013                                     I40E_MAX_TUNNEL_FILTER_NUM,
1014                                     0);
1015         if (!tunnel_rule->hash_map) {
1016                 PMD_INIT_LOG(ERR,
1017                              "Failed to allocate memory for tunnel hash map!");
1018                 ret = -ENOMEM;
1019                 goto err_tunnel_hash_map_alloc;
1020         }
1021
1022         return 0;
1023
1024 err_tunnel_hash_map_alloc:
1025         rte_hash_free(tunnel_rule->hash_table);
1026
1027         return ret;
1028 }
1029
1030 static int
1031 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1032 {
1033         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1034         struct i40e_fdir_info *fdir_info = &pf->fdir;
1035         char fdir_hash_name[RTE_HASH_NAMESIZE];
1036         int ret;
1037
1038         struct rte_hash_parameters fdir_hash_params = {
1039                 .name = fdir_hash_name,
1040                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1041                 .key_len = sizeof(struct i40e_fdir_input),
1042                 .hash_func = rte_hash_crc,
1043                 .hash_func_init_val = 0,
1044                 .socket_id = rte_socket_id(),
1045         };
1046
1047         /* Initialize flow director filter rule list and hash */
1048         TAILQ_INIT(&fdir_info->fdir_list);
1049         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1050                  "fdir_%s", dev->device->name);
1051         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1052         if (!fdir_info->hash_table) {
1053                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1054                 return -EINVAL;
1055         }
1056         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1057                                           sizeof(struct i40e_fdir_filter *) *
1058                                           I40E_MAX_FDIR_FILTER_NUM,
1059                                           0);
1060         if (!fdir_info->hash_map) {
1061                 PMD_INIT_LOG(ERR,
1062                              "Failed to allocate memory for fdir hash map!");
1063                 ret = -ENOMEM;
1064                 goto err_fdir_hash_map_alloc;
1065         }
1066         return 0;
1067
1068 err_fdir_hash_map_alloc:
1069         rte_hash_free(fdir_info->hash_table);
1070
1071         return ret;
1072 }
1073
1074 static void
1075 i40e_init_customized_info(struct i40e_pf *pf)
1076 {
1077         int i;
1078
1079         /* Initialize customized pctype */
1080         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1081                 pf->customized_pctype[i].index = i;
1082                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1083                 pf->customized_pctype[i].valid = false;
1084         }
1085
1086         pf->gtp_support = false;
1087 }
1088
1089 void
1090 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1091 {
1092         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1093         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1094         struct i40e_queue_regions *info = &pf->queue_region;
1095         uint16_t i;
1096
1097         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1098                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1099
1100         memset(info, 0, sizeof(struct i40e_queue_regions));
1101 }
1102
1103 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
1104
1105 static int
1106 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1107                                const char *value,
1108                                void *opaque)
1109 {
1110         struct i40e_pf *pf;
1111         unsigned long support_multi_driver;
1112         char *end;
1113
1114         pf = (struct i40e_pf *)opaque;
1115
1116         errno = 0;
1117         support_multi_driver = strtoul(value, &end, 10);
1118         if (errno != 0 || end == value || *end != 0) {
1119                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1120                 return -(EINVAL);
1121         }
1122
1123         if (support_multi_driver == 1 || support_multi_driver == 0)
1124                 pf->support_multi_driver = (bool)support_multi_driver;
1125         else
1126                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1127                             "enable global configuration by default."
1128                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1129         return 0;
1130 }
1131
1132 static int
1133 i40e_support_multi_driver(struct rte_eth_dev *dev)
1134 {
1135         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1136         static const char *const valid_keys[] = {
1137                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1138         struct rte_kvargs *kvlist;
1139
1140         /* Enable global configuration by default */
1141         pf->support_multi_driver = false;
1142
1143         if (!dev->device->devargs)
1144                 return 0;
1145
1146         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1147         if (!kvlist)
1148                 return -EINVAL;
1149
1150         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1151                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1152                             "the first invalid or last valid one is used !",
1153                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1154
1155         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1156                                i40e_parse_multi_drv_handler, pf) < 0) {
1157                 rte_kvargs_free(kvlist);
1158                 return -EINVAL;
1159         }
1160
1161         rte_kvargs_free(kvlist);
1162         return 0;
1163 }
1164
1165 static int
1166 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1167                                     uint32_t reg_addr, uint64_t reg_val,
1168                                     struct i40e_asq_cmd_details *cmd_details)
1169 {
1170         uint64_t ori_reg_val;
1171         struct rte_eth_dev *dev;
1172         int ret;
1173
1174         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1175         if (ret != I40E_SUCCESS) {
1176                 PMD_DRV_LOG(ERR,
1177                             "Fail to debug read from 0x%08x",
1178                             reg_addr);
1179                 return -EIO;
1180         }
1181         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1182
1183         if (ori_reg_val != reg_val)
1184                 PMD_DRV_LOG(WARNING,
1185                             "i40e device %s changed global register [0x%08x]."
1186                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1187                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1188
1189         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1190 }
1191
1192 static int
1193 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1194 {
1195         struct rte_pci_device *pci_dev;
1196         struct rte_intr_handle *intr_handle;
1197         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1198         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1199         struct i40e_vsi *vsi;
1200         int ret;
1201         uint32_t len;
1202         uint8_t aq_fail = 0;
1203
1204         PMD_INIT_FUNC_TRACE();
1205
1206         dev->dev_ops = &i40e_eth_dev_ops;
1207         dev->rx_pkt_burst = i40e_recv_pkts;
1208         dev->tx_pkt_burst = i40e_xmit_pkts;
1209         dev->tx_pkt_prepare = i40e_prep_pkts;
1210
1211         /* for secondary processes, we don't initialise any further as primary
1212          * has already done this work. Only check we don't need a different
1213          * RX function */
1214         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1215                 i40e_set_rx_function(dev);
1216                 i40e_set_tx_function(dev);
1217                 return 0;
1218         }
1219         i40e_set_default_ptype_table(dev);
1220         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1221         intr_handle = &pci_dev->intr_handle;
1222
1223         rte_eth_copy_pci_info(dev, pci_dev);
1224
1225         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1226         pf->adapter->eth_dev = dev;
1227         pf->dev_data = dev->data;
1228
1229         hw->back = I40E_PF_TO_ADAPTER(pf);
1230         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1231         if (!hw->hw_addr) {
1232                 PMD_INIT_LOG(ERR,
1233                         "Hardware is not available, as address is NULL");
1234                 return -ENODEV;
1235         }
1236
1237         hw->vendor_id = pci_dev->id.vendor_id;
1238         hw->device_id = pci_dev->id.device_id;
1239         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1240         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1241         hw->bus.device = pci_dev->addr.devid;
1242         hw->bus.func = pci_dev->addr.function;
1243         hw->adapter_stopped = 0;
1244
1245         /*
1246          * Switch Tag value should not be identical to either the First Tag
1247          * or Second Tag values. So set something other than common Ethertype
1248          * for internal switching.
1249          */
1250         hw->switch_tag = 0xffff;
1251
1252         /* Check if need to support multi-driver */
1253         i40e_support_multi_driver(dev);
1254
1255         /* Make sure all is clean before doing PF reset */
1256         i40e_clear_hw(hw);
1257
1258         /* Initialize the hardware */
1259         i40e_hw_init(dev);
1260
1261         /* Reset here to make sure all is clean for each PF */
1262         ret = i40e_pf_reset(hw);
1263         if (ret) {
1264                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1265                 return ret;
1266         }
1267
1268         /* Initialize the shared code (base driver) */
1269         ret = i40e_init_shared_code(hw);
1270         if (ret) {
1271                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1272                 return ret;
1273         }
1274
1275         i40e_config_automask(pf);
1276
1277         i40e_set_default_pctype_table(dev);
1278
1279         /*
1280          * To work around the NVM issue, initialize registers
1281          * for packet type of QinQ by software.
1282          * It should be removed once issues are fixed in NVM.
1283          */
1284         if (!pf->support_multi_driver)
1285                 i40e_GLQF_reg_init(hw);
1286
1287         /* Initialize the input set for filters (hash and fd) to default value */
1288         i40e_filter_input_set_init(pf);
1289
1290         /* Initialize the parameters for adminq */
1291         i40e_init_adminq_parameter(hw);
1292         ret = i40e_init_adminq(hw);
1293         if (ret != I40E_SUCCESS) {
1294                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1295                 return -EIO;
1296         }
1297         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1298                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1299                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1300                      ((hw->nvm.version >> 12) & 0xf),
1301                      ((hw->nvm.version >> 4) & 0xff),
1302                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1303
1304         /* initialise the L3_MAP register */
1305         if (!pf->support_multi_driver) {
1306                 ret = i40e_aq_debug_write_global_register(hw,
1307                                                    I40E_GLQF_L3_MAP(40),
1308                                                    0x00000028,  NULL);
1309                 if (ret)
1310                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1311                                      ret);
1312                 PMD_INIT_LOG(DEBUG,
1313                              "Global register 0x%08x is changed with 0x28",
1314                              I40E_GLQF_L3_MAP(40));
1315         }
1316
1317         /* Need the special FW version to support floating VEB */
1318         config_floating_veb(dev);
1319         /* Clear PXE mode */
1320         i40e_clear_pxe_mode(hw);
1321         i40e_dev_sync_phy_type(hw);
1322
1323         /*
1324          * On X710, performance number is far from the expectation on recent
1325          * firmware versions. The fix for this issue may not be integrated in
1326          * the following firmware version. So the workaround in software driver
1327          * is needed. It needs to modify the initial values of 3 internal only
1328          * registers. Note that the workaround can be removed when it is fixed
1329          * in firmware in the future.
1330          */
1331         i40e_configure_registers(hw);
1332
1333         /* Get hw capabilities */
1334         ret = i40e_get_cap(hw);
1335         if (ret != I40E_SUCCESS) {
1336                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1337                 goto err_get_capabilities;
1338         }
1339
1340         /* Initialize parameters for PF */
1341         ret = i40e_pf_parameter_init(dev);
1342         if (ret != 0) {
1343                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1344                 goto err_parameter_init;
1345         }
1346
1347         /* Initialize the queue management */
1348         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1349         if (ret < 0) {
1350                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1351                 goto err_qp_pool_init;
1352         }
1353         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1354                                 hw->func_caps.num_msix_vectors - 1);
1355         if (ret < 0) {
1356                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1357                 goto err_msix_pool_init;
1358         }
1359
1360         /* Initialize lan hmc */
1361         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1362                                 hw->func_caps.num_rx_qp, 0, 0);
1363         if (ret != I40E_SUCCESS) {
1364                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1365                 goto err_init_lan_hmc;
1366         }
1367
1368         /* Configure lan hmc */
1369         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1370         if (ret != I40E_SUCCESS) {
1371                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1372                 goto err_configure_lan_hmc;
1373         }
1374
1375         /* Get and check the mac address */
1376         i40e_get_mac_addr(hw, hw->mac.addr);
1377         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1378                 PMD_INIT_LOG(ERR, "mac address is not valid");
1379                 ret = -EIO;
1380                 goto err_get_mac_addr;
1381         }
1382         /* Copy the permanent MAC address */
1383         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1384                         (struct ether_addr *) hw->mac.perm_addr);
1385
1386         /* Disable flow control */
1387         hw->fc.requested_mode = I40E_FC_NONE;
1388         i40e_set_fc(hw, &aq_fail, TRUE);
1389
1390         /* Set the global registers with default ether type value */
1391         if (!pf->support_multi_driver) {
1392                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1393                                          ETHER_TYPE_VLAN);
1394                 if (ret != I40E_SUCCESS) {
1395                         PMD_INIT_LOG(ERR,
1396                                      "Failed to set the default outer "
1397                                      "VLAN ether type");
1398                         goto err_setup_pf_switch;
1399                 }
1400         }
1401
1402         /* PF setup, which includes VSI setup */
1403         ret = i40e_pf_setup(pf);
1404         if (ret) {
1405                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1406                 goto err_setup_pf_switch;
1407         }
1408
1409         /* reset all stats of the device, including pf and main vsi */
1410         i40e_dev_stats_reset(dev);
1411
1412         vsi = pf->main_vsi;
1413
1414         /* Disable double vlan by default */
1415         i40e_vsi_config_double_vlan(vsi, FALSE);
1416
1417         /* Disable S-TAG identification when floating_veb is disabled */
1418         if (!pf->floating_veb) {
1419                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1420                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1421                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1422                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1423                 }
1424         }
1425
1426         if (!vsi->max_macaddrs)
1427                 len = ETHER_ADDR_LEN;
1428         else
1429                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1430
1431         /* Should be after VSI initialized */
1432         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1433         if (!dev->data->mac_addrs) {
1434                 PMD_INIT_LOG(ERR,
1435                         "Failed to allocated memory for storing mac address");
1436                 goto err_mac_alloc;
1437         }
1438         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1439                                         &dev->data->mac_addrs[0]);
1440
1441         /* Init dcb to sw mode by default */
1442         ret = i40e_dcb_init_configure(dev, TRUE);
1443         if (ret != I40E_SUCCESS) {
1444                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1445                 pf->flags &= ~I40E_FLAG_DCB;
1446         }
1447         /* Update HW struct after DCB configuration */
1448         i40e_get_cap(hw);
1449
1450         /* initialize pf host driver to setup SRIOV resource if applicable */
1451         i40e_pf_host_init(dev);
1452
1453         /* register callback func to eal lib */
1454         rte_intr_callback_register(intr_handle,
1455                                    i40e_dev_interrupt_handler, dev);
1456
1457         /* configure and enable device interrupt */
1458         i40e_pf_config_irq0(hw, TRUE);
1459         i40e_pf_enable_irq0(hw);
1460
1461         /* enable uio intr after callback register */
1462         rte_intr_enable(intr_handle);
1463
1464         /* By default disable flexible payload in global configuration */
1465         if (!pf->support_multi_driver)
1466                 i40e_flex_payload_reg_set_default(hw);
1467
1468         /*
1469          * Add an ethertype filter to drop all flow control frames transmitted
1470          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1471          * frames to wire.
1472          */
1473         i40e_add_tx_flow_control_drop_filter(pf);
1474
1475         /* Set the max frame size to 0x2600 by default,
1476          * in case other drivers changed the default value.
1477          */
1478         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1479
1480         /* initialize mirror rule list */
1481         TAILQ_INIT(&pf->mirror_list);
1482
1483         /* initialize Traffic Manager configuration */
1484         i40e_tm_conf_init(dev);
1485
1486         /* Initialize customized information */
1487         i40e_init_customized_info(pf);
1488
1489         ret = i40e_init_ethtype_filter_list(dev);
1490         if (ret < 0)
1491                 goto err_init_ethtype_filter_list;
1492         ret = i40e_init_tunnel_filter_list(dev);
1493         if (ret < 0)
1494                 goto err_init_tunnel_filter_list;
1495         ret = i40e_init_fdir_filter_list(dev);
1496         if (ret < 0)
1497                 goto err_init_fdir_filter_list;
1498
1499         /* initialize queue region configuration */
1500         i40e_init_queue_region_conf(dev);
1501
1502         /* initialize rss configuration from rte_flow */
1503         memset(&pf->rss_info, 0,
1504                 sizeof(struct i40e_rte_flow_rss_conf));
1505
1506         return 0;
1507
1508 err_init_fdir_filter_list:
1509         rte_free(pf->tunnel.hash_table);
1510         rte_free(pf->tunnel.hash_map);
1511 err_init_tunnel_filter_list:
1512         rte_free(pf->ethertype.hash_table);
1513         rte_free(pf->ethertype.hash_map);
1514 err_init_ethtype_filter_list:
1515         rte_free(dev->data->mac_addrs);
1516 err_mac_alloc:
1517         i40e_vsi_release(pf->main_vsi);
1518 err_setup_pf_switch:
1519 err_get_mac_addr:
1520 err_configure_lan_hmc:
1521         (void)i40e_shutdown_lan_hmc(hw);
1522 err_init_lan_hmc:
1523         i40e_res_pool_destroy(&pf->msix_pool);
1524 err_msix_pool_init:
1525         i40e_res_pool_destroy(&pf->qp_pool);
1526 err_qp_pool_init:
1527 err_parameter_init:
1528 err_get_capabilities:
1529         (void)i40e_shutdown_adminq(hw);
1530
1531         return ret;
1532 }
1533
1534 static void
1535 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1536 {
1537         struct i40e_ethertype_filter *p_ethertype;
1538         struct i40e_ethertype_rule *ethertype_rule;
1539
1540         ethertype_rule = &pf->ethertype;
1541         /* Remove all ethertype filter rules and hash */
1542         if (ethertype_rule->hash_map)
1543                 rte_free(ethertype_rule->hash_map);
1544         if (ethertype_rule->hash_table)
1545                 rte_hash_free(ethertype_rule->hash_table);
1546
1547         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1548                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1549                              p_ethertype, rules);
1550                 rte_free(p_ethertype);
1551         }
1552 }
1553
1554 static void
1555 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1556 {
1557         struct i40e_tunnel_filter *p_tunnel;
1558         struct i40e_tunnel_rule *tunnel_rule;
1559
1560         tunnel_rule = &pf->tunnel;
1561         /* Remove all tunnel director rules and hash */
1562         if (tunnel_rule->hash_map)
1563                 rte_free(tunnel_rule->hash_map);
1564         if (tunnel_rule->hash_table)
1565                 rte_hash_free(tunnel_rule->hash_table);
1566
1567         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1568                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1569                 rte_free(p_tunnel);
1570         }
1571 }
1572
1573 static void
1574 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1575 {
1576         struct i40e_fdir_filter *p_fdir;
1577         struct i40e_fdir_info *fdir_info;
1578
1579         fdir_info = &pf->fdir;
1580         /* Remove all flow director rules and hash */
1581         if (fdir_info->hash_map)
1582                 rte_free(fdir_info->hash_map);
1583         if (fdir_info->hash_table)
1584                 rte_hash_free(fdir_info->hash_table);
1585
1586         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1587                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1588                 rte_free(p_fdir);
1589         }
1590 }
1591
1592 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1593 {
1594         /*
1595          * Disable by default flexible payload
1596          * for corresponding L2/L3/L4 layers.
1597          */
1598         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1599         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1600         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1601 }
1602
1603 static int
1604 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1605 {
1606         struct i40e_pf *pf;
1607         struct rte_pci_device *pci_dev;
1608         struct rte_intr_handle *intr_handle;
1609         struct i40e_hw *hw;
1610         struct i40e_filter_control_settings settings;
1611         struct rte_flow *p_flow;
1612         int ret;
1613         uint8_t aq_fail = 0;
1614         int retries = 0;
1615
1616         PMD_INIT_FUNC_TRACE();
1617
1618         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1619                 return 0;
1620
1621         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1622         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1623         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1624         intr_handle = &pci_dev->intr_handle;
1625
1626         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1627         if (ret)
1628                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1629
1630         if (hw->adapter_stopped == 0)
1631                 i40e_dev_close(dev);
1632
1633         dev->dev_ops = NULL;
1634         dev->rx_pkt_burst = NULL;
1635         dev->tx_pkt_burst = NULL;
1636
1637         /* Clear PXE mode */
1638         i40e_clear_pxe_mode(hw);
1639
1640         /* Unconfigure filter control */
1641         memset(&settings, 0, sizeof(settings));
1642         ret = i40e_set_filter_control(hw, &settings);
1643         if (ret)
1644                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1645                                         ret);
1646
1647         /* Disable flow control */
1648         hw->fc.requested_mode = I40E_FC_NONE;
1649         i40e_set_fc(hw, &aq_fail, TRUE);
1650
1651         /* uninitialize pf host driver */
1652         i40e_pf_host_uninit(dev);
1653
1654         rte_free(dev->data->mac_addrs);
1655         dev->data->mac_addrs = NULL;
1656
1657         /* disable uio intr before callback unregister */
1658         rte_intr_disable(intr_handle);
1659
1660         /* unregister callback func to eal lib */
1661         do {
1662                 ret = rte_intr_callback_unregister(intr_handle,
1663                                 i40e_dev_interrupt_handler, dev);
1664                 if (ret >= 0) {
1665                         break;
1666                 } else if (ret != -EAGAIN) {
1667                         PMD_INIT_LOG(ERR,
1668                                  "intr callback unregister failed: %d",
1669                                  ret);
1670                         return ret;
1671                 }
1672                 i40e_msec_delay(500);
1673         } while (retries++ < 5);
1674
1675         i40e_rm_ethtype_filter_list(pf);
1676         i40e_rm_tunnel_filter_list(pf);
1677         i40e_rm_fdir_filter_list(pf);
1678
1679         /* Remove all flows */
1680         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1681                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1682                 rte_free(p_flow);
1683         }
1684
1685         /* Remove all Traffic Manager configuration */
1686         i40e_tm_conf_uninit(dev);
1687
1688         return 0;
1689 }
1690
1691 static int
1692 i40e_dev_configure(struct rte_eth_dev *dev)
1693 {
1694         struct i40e_adapter *ad =
1695                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1696         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1697         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1698         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1699         int i, ret;
1700
1701         ret = i40e_dev_sync_phy_type(hw);
1702         if (ret)
1703                 return ret;
1704
1705         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1706          * bulk allocation or vector Rx preconditions we will reset it.
1707          */
1708         ad->rx_bulk_alloc_allowed = true;
1709         ad->rx_vec_allowed = true;
1710         ad->tx_simple_allowed = true;
1711         ad->tx_vec_allowed = true;
1712
1713         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1714                 ret = i40e_fdir_setup(pf);
1715                 if (ret != I40E_SUCCESS) {
1716                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1717                         return -ENOTSUP;
1718                 }
1719                 ret = i40e_fdir_configure(dev);
1720                 if (ret < 0) {
1721                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1722                         goto err;
1723                 }
1724         } else
1725                 i40e_fdir_teardown(pf);
1726
1727         ret = i40e_dev_init_vlan(dev);
1728         if (ret < 0)
1729                 goto err;
1730
1731         /* VMDQ setup.
1732          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1733          *  RSS setting have different requirements.
1734          *  General PMD driver call sequence are NIC init, configure,
1735          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1736          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1737          *  applicable. So, VMDQ setting has to be done before
1738          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1739          *  For RSS setting, it will try to calculate actual configured RX queue
1740          *  number, which will be available after rx_queue_setup(). dev_start()
1741          *  function is good to place RSS setup.
1742          */
1743         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1744                 ret = i40e_vmdq_setup(dev);
1745                 if (ret)
1746                         goto err;
1747         }
1748
1749         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1750                 ret = i40e_dcb_setup(dev);
1751                 if (ret) {
1752                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1753                         goto err_dcb;
1754                 }
1755         }
1756
1757         TAILQ_INIT(&pf->flow_list);
1758
1759         return 0;
1760
1761 err_dcb:
1762         /* need to release vmdq resource if exists */
1763         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1764                 i40e_vsi_release(pf->vmdq[i].vsi);
1765                 pf->vmdq[i].vsi = NULL;
1766         }
1767         rte_free(pf->vmdq);
1768         pf->vmdq = NULL;
1769 err:
1770         /* need to release fdir resource if exists */
1771         i40e_fdir_teardown(pf);
1772         return ret;
1773 }
1774
1775 void
1776 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1777 {
1778         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1779         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1780         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1781         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1782         uint16_t msix_vect = vsi->msix_intr;
1783         uint16_t i;
1784
1785         for (i = 0; i < vsi->nb_qps; i++) {
1786                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1787                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1788                 rte_wmb();
1789         }
1790
1791         if (vsi->type != I40E_VSI_SRIOV) {
1792                 if (!rte_intr_allow_others(intr_handle)) {
1793                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1794                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1795                         I40E_WRITE_REG(hw,
1796                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1797                                        0);
1798                 } else {
1799                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1800                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1801                         I40E_WRITE_REG(hw,
1802                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1803                                                        msix_vect - 1), 0);
1804                 }
1805         } else {
1806                 uint32_t reg;
1807                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1808                         vsi->user_param + (msix_vect - 1);
1809
1810                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1811                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1812         }
1813         I40E_WRITE_FLUSH(hw);
1814 }
1815
1816 static void
1817 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1818                        int base_queue, int nb_queue,
1819                        uint16_t itr_idx)
1820 {
1821         int i;
1822         uint32_t val;
1823         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1824         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1825
1826         /* Bind all RX queues to allocated MSIX interrupt */
1827         for (i = 0; i < nb_queue; i++) {
1828                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1829                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1830                         ((base_queue + i + 1) <<
1831                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1832                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1833                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1834
1835                 if (i == nb_queue - 1)
1836                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1837                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1838         }
1839
1840         /* Write first RX queue to Link list register as the head element */
1841         if (vsi->type != I40E_VSI_SRIOV) {
1842                 uint16_t interval =
1843                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1844
1845                 if (msix_vect == I40E_MISC_VEC_ID) {
1846                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1847                                        (base_queue <<
1848                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1849                                        (0x0 <<
1850                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1851                         I40E_WRITE_REG(hw,
1852                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1853                                        interval);
1854                 } else {
1855                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1856                                        (base_queue <<
1857                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1858                                        (0x0 <<
1859                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1860                         I40E_WRITE_REG(hw,
1861                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1862                                                        msix_vect - 1),
1863                                        interval);
1864                 }
1865         } else {
1866                 uint32_t reg;
1867
1868                 if (msix_vect == I40E_MISC_VEC_ID) {
1869                         I40E_WRITE_REG(hw,
1870                                        I40E_VPINT_LNKLST0(vsi->user_param),
1871                                        (base_queue <<
1872                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1873                                        (0x0 <<
1874                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1875                 } else {
1876                         /* num_msix_vectors_vf needs to minus irq0 */
1877                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1878                                 vsi->user_param + (msix_vect - 1);
1879
1880                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1881                                        (base_queue <<
1882                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1883                                        (0x0 <<
1884                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1885                 }
1886         }
1887
1888         I40E_WRITE_FLUSH(hw);
1889 }
1890
1891 void
1892 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1893 {
1894         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1895         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1896         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1897         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1898         uint16_t msix_vect = vsi->msix_intr;
1899         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1900         uint16_t queue_idx = 0;
1901         int record = 0;
1902         int i;
1903
1904         for (i = 0; i < vsi->nb_qps; i++) {
1905                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1906                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1907         }
1908
1909         /* VF bind interrupt */
1910         if (vsi->type == I40E_VSI_SRIOV) {
1911                 __vsi_queues_bind_intr(vsi, msix_vect,
1912                                        vsi->base_queue, vsi->nb_qps,
1913                                        itr_idx);
1914                 return;
1915         }
1916
1917         /* PF & VMDq bind interrupt */
1918         if (rte_intr_dp_is_en(intr_handle)) {
1919                 if (vsi->type == I40E_VSI_MAIN) {
1920                         queue_idx = 0;
1921                         record = 1;
1922                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1923                         struct i40e_vsi *main_vsi =
1924                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1925                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1926                         record = 1;
1927                 }
1928         }
1929
1930         for (i = 0; i < vsi->nb_used_qps; i++) {
1931                 if (nb_msix <= 1) {
1932                         if (!rte_intr_allow_others(intr_handle))
1933                                 /* allow to share MISC_VEC_ID */
1934                                 msix_vect = I40E_MISC_VEC_ID;
1935
1936                         /* no enough msix_vect, map all to one */
1937                         __vsi_queues_bind_intr(vsi, msix_vect,
1938                                                vsi->base_queue + i,
1939                                                vsi->nb_used_qps - i,
1940                                                itr_idx);
1941                         for (; !!record && i < vsi->nb_used_qps; i++)
1942                                 intr_handle->intr_vec[queue_idx + i] =
1943                                         msix_vect;
1944                         break;
1945                 }
1946                 /* 1:1 queue/msix_vect mapping */
1947                 __vsi_queues_bind_intr(vsi, msix_vect,
1948                                        vsi->base_queue + i, 1,
1949                                        itr_idx);
1950                 if (!!record)
1951                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1952
1953                 msix_vect++;
1954                 nb_msix--;
1955         }
1956 }
1957
1958 static void
1959 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1960 {
1961         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1962         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1963         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1964         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1965         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1966         uint16_t msix_intr, i;
1967
1968         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1969                 for (i = 0; i < vsi->nb_msix; i++) {
1970                         msix_intr = vsi->msix_intr + i;
1971                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1972                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1973                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1974                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1975                 }
1976         else
1977                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1978                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1979                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1980                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1981
1982         I40E_WRITE_FLUSH(hw);
1983 }
1984
1985 static void
1986 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1987 {
1988         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1989         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1990         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1991         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1992         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1993         uint16_t msix_intr, i;
1994
1995         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1996                 for (i = 0; i < vsi->nb_msix; i++) {
1997                         msix_intr = vsi->msix_intr + i;
1998                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1999                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2000                 }
2001         else
2002                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2003                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2004
2005         I40E_WRITE_FLUSH(hw);
2006 }
2007
2008 static inline uint8_t
2009 i40e_parse_link_speeds(uint16_t link_speeds)
2010 {
2011         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2012
2013         if (link_speeds & ETH_LINK_SPEED_40G)
2014                 link_speed |= I40E_LINK_SPEED_40GB;
2015         if (link_speeds & ETH_LINK_SPEED_25G)
2016                 link_speed |= I40E_LINK_SPEED_25GB;
2017         if (link_speeds & ETH_LINK_SPEED_20G)
2018                 link_speed |= I40E_LINK_SPEED_20GB;
2019         if (link_speeds & ETH_LINK_SPEED_10G)
2020                 link_speed |= I40E_LINK_SPEED_10GB;
2021         if (link_speeds & ETH_LINK_SPEED_1G)
2022                 link_speed |= I40E_LINK_SPEED_1GB;
2023         if (link_speeds & ETH_LINK_SPEED_100M)
2024                 link_speed |= I40E_LINK_SPEED_100MB;
2025
2026         return link_speed;
2027 }
2028
2029 static int
2030 i40e_phy_conf_link(struct i40e_hw *hw,
2031                    uint8_t abilities,
2032                    uint8_t force_speed,
2033                    bool is_up)
2034 {
2035         enum i40e_status_code status;
2036         struct i40e_aq_get_phy_abilities_resp phy_ab;
2037         struct i40e_aq_set_phy_config phy_conf;
2038         enum i40e_aq_phy_type cnt;
2039         uint32_t phy_type_mask = 0;
2040
2041         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2042                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2043                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2044                         I40E_AQ_PHY_FLAG_LOW_POWER;
2045         const uint8_t advt = I40E_LINK_SPEED_40GB |
2046                         I40E_LINK_SPEED_25GB |
2047                         I40E_LINK_SPEED_10GB |
2048                         I40E_LINK_SPEED_1GB |
2049                         I40E_LINK_SPEED_100MB;
2050         int ret = -ENOTSUP;
2051
2052
2053         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2054                                               NULL);
2055         if (status)
2056                 return ret;
2057
2058         /* If link already up, no need to set up again */
2059         if (is_up && phy_ab.phy_type != 0)
2060                 return I40E_SUCCESS;
2061
2062         memset(&phy_conf, 0, sizeof(phy_conf));
2063
2064         /* bits 0-2 use the values from get_phy_abilities_resp */
2065         abilities &= ~mask;
2066         abilities |= phy_ab.abilities & mask;
2067
2068         /* update ablities and speed */
2069         if (abilities & I40E_AQ_PHY_AN_ENABLED)
2070                 phy_conf.link_speed = advt;
2071         else
2072                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
2073
2074         phy_conf.abilities = abilities;
2075
2076
2077
2078         /* PHY type mask needs to include each type except PHY type extension */
2079         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2080                 phy_type_mask |= 1 << cnt;
2081
2082         /* use get_phy_abilities_resp value for the rest */
2083         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2084         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2085                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2086                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2087         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2088         phy_conf.eee_capability = phy_ab.eee_capability;
2089         phy_conf.eeer = phy_ab.eeer_val;
2090         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2091
2092         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2093                     phy_ab.abilities, phy_ab.link_speed);
2094         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2095                     phy_conf.abilities, phy_conf.link_speed);
2096
2097         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2098         if (status)
2099                 return ret;
2100
2101         return I40E_SUCCESS;
2102 }
2103
2104 static int
2105 i40e_apply_link_speed(struct rte_eth_dev *dev)
2106 {
2107         uint8_t speed;
2108         uint8_t abilities = 0;
2109         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110         struct rte_eth_conf *conf = &dev->data->dev_conf;
2111
2112         speed = i40e_parse_link_speeds(conf->link_speeds);
2113         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2114         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2115                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2116         abilities |= I40E_AQ_PHY_LINK_ENABLED;
2117
2118         return i40e_phy_conf_link(hw, abilities, speed, true);
2119 }
2120
2121 static int
2122 i40e_dev_start(struct rte_eth_dev *dev)
2123 {
2124         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2125         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2126         struct i40e_vsi *main_vsi = pf->main_vsi;
2127         int ret, i;
2128         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2129         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2130         uint32_t intr_vector = 0;
2131         struct i40e_vsi *vsi;
2132
2133         hw->adapter_stopped = 0;
2134
2135         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2136                 PMD_INIT_LOG(ERR,
2137                 "Invalid link_speeds for port %u, autonegotiation disabled",
2138                               dev->data->port_id);
2139                 return -EINVAL;
2140         }
2141
2142         rte_intr_disable(intr_handle);
2143
2144         if ((rte_intr_cap_multiple(intr_handle) ||
2145              !RTE_ETH_DEV_SRIOV(dev).active) &&
2146             dev->data->dev_conf.intr_conf.rxq != 0) {
2147                 intr_vector = dev->data->nb_rx_queues;
2148                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2149                 if (ret)
2150                         return ret;
2151         }
2152
2153         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2154                 intr_handle->intr_vec =
2155                         rte_zmalloc("intr_vec",
2156                                     dev->data->nb_rx_queues * sizeof(int),
2157                                     0);
2158                 if (!intr_handle->intr_vec) {
2159                         PMD_INIT_LOG(ERR,
2160                                 "Failed to allocate %d rx_queues intr_vec",
2161                                 dev->data->nb_rx_queues);
2162                         return -ENOMEM;
2163                 }
2164         }
2165
2166         /* Initialize VSI */
2167         ret = i40e_dev_rxtx_init(pf);
2168         if (ret != I40E_SUCCESS) {
2169                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2170                 goto err_up;
2171         }
2172
2173         /* Map queues with MSIX interrupt */
2174         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2175                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2176         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2177         i40e_vsi_enable_queues_intr(main_vsi);
2178
2179         /* Map VMDQ VSI queues with MSIX interrupt */
2180         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2181                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2182                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2183                                           I40E_ITR_INDEX_DEFAULT);
2184                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2185         }
2186
2187         /* enable FDIR MSIX interrupt */
2188         if (pf->fdir.fdir_vsi) {
2189                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2190                                           I40E_ITR_INDEX_NONE);
2191                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2192         }
2193
2194         /* Enable all queues which have been configured */
2195         ret = i40e_dev_switch_queues(pf, TRUE);
2196         if (ret != I40E_SUCCESS) {
2197                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2198                 goto err_up;
2199         }
2200
2201         /* Enable receiving broadcast packets */
2202         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2203         if (ret != I40E_SUCCESS)
2204                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2205
2206         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2207                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2208                                                 true, NULL);
2209                 if (ret != I40E_SUCCESS)
2210                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2211         }
2212
2213         /* Enable the VLAN promiscuous mode. */
2214         if (pf->vfs) {
2215                 for (i = 0; i < pf->vf_num; i++) {
2216                         vsi = pf->vfs[i].vsi;
2217                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2218                                                      true, NULL);
2219                 }
2220         }
2221
2222         /* Enable mac loopback mode */
2223         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2224             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2225                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2226                 if (ret != I40E_SUCCESS) {
2227                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2228                         goto err_up;
2229                 }
2230         }
2231
2232         /* Apply link configure */
2233         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2234                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2235                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2236                                 ETH_LINK_SPEED_40G)) {
2237                 PMD_DRV_LOG(ERR, "Invalid link setting");
2238                 goto err_up;
2239         }
2240         ret = i40e_apply_link_speed(dev);
2241         if (I40E_SUCCESS != ret) {
2242                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2243                 goto err_up;
2244         }
2245
2246         if (!rte_intr_allow_others(intr_handle)) {
2247                 rte_intr_callback_unregister(intr_handle,
2248                                              i40e_dev_interrupt_handler,
2249                                              (void *)dev);
2250                 /* configure and enable device interrupt */
2251                 i40e_pf_config_irq0(hw, FALSE);
2252                 i40e_pf_enable_irq0(hw);
2253
2254                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2255                         PMD_INIT_LOG(INFO,
2256                                 "lsc won't enable because of no intr multiplex");
2257         } else {
2258                 ret = i40e_aq_set_phy_int_mask(hw,
2259                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2260                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2261                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2262                 if (ret != I40E_SUCCESS)
2263                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2264
2265                 /* Call get_link_info aq commond to enable/disable LSE */
2266                 i40e_dev_link_update(dev, 0);
2267         }
2268
2269         /* enable uio intr after callback register */
2270         rte_intr_enable(intr_handle);
2271
2272         i40e_filter_restore(pf);
2273
2274         if (pf->tm_conf.root && !pf->tm_conf.committed)
2275                 PMD_DRV_LOG(WARNING,
2276                             "please call hierarchy_commit() "
2277                             "before starting the port");
2278
2279         return I40E_SUCCESS;
2280
2281 err_up:
2282         i40e_dev_switch_queues(pf, FALSE);
2283         i40e_dev_clear_queues(dev);
2284
2285         return ret;
2286 }
2287
2288 static void
2289 i40e_dev_stop(struct rte_eth_dev *dev)
2290 {
2291         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2292         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2293         struct i40e_vsi *main_vsi = pf->main_vsi;
2294         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2295         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2296         int i;
2297
2298         if (hw->adapter_stopped == 1)
2299                 return;
2300         /* Disable all queues */
2301         i40e_dev_switch_queues(pf, FALSE);
2302
2303         /* un-map queues with interrupt registers */
2304         i40e_vsi_disable_queues_intr(main_vsi);
2305         i40e_vsi_queues_unbind_intr(main_vsi);
2306
2307         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2308                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2309                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2310         }
2311
2312         if (pf->fdir.fdir_vsi) {
2313                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2314                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2315         }
2316         /* Clear all queues and release memory */
2317         i40e_dev_clear_queues(dev);
2318
2319         /* Set link down */
2320         i40e_dev_set_link_down(dev);
2321
2322         if (!rte_intr_allow_others(intr_handle))
2323                 /* resume to the default handler */
2324                 rte_intr_callback_register(intr_handle,
2325                                            i40e_dev_interrupt_handler,
2326                                            (void *)dev);
2327
2328         /* Clean datapath event and queue/vec mapping */
2329         rte_intr_efd_disable(intr_handle);
2330         if (intr_handle->intr_vec) {
2331                 rte_free(intr_handle->intr_vec);
2332                 intr_handle->intr_vec = NULL;
2333         }
2334
2335         /* reset hierarchy commit */
2336         pf->tm_conf.committed = false;
2337
2338         hw->adapter_stopped = 1;
2339 }
2340
2341 static void
2342 i40e_dev_close(struct rte_eth_dev *dev)
2343 {
2344         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2345         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2346         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2347         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2348         struct i40e_mirror_rule *p_mirror;
2349         uint32_t reg;
2350         int i;
2351         int ret;
2352
2353         PMD_INIT_FUNC_TRACE();
2354
2355         i40e_dev_stop(dev);
2356
2357         /* Remove all mirror rules */
2358         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2359                 ret = i40e_aq_del_mirror_rule(hw,
2360                                               pf->main_vsi->veb->seid,
2361                                               p_mirror->rule_type,
2362                                               p_mirror->entries,
2363                                               p_mirror->num_entries,
2364                                               p_mirror->id);
2365                 if (ret < 0)
2366                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2367                                     "status = %d, aq_err = %d.", ret,
2368                                     hw->aq.asq_last_status);
2369
2370                 /* remove mirror software resource anyway */
2371                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2372                 rte_free(p_mirror);
2373                 pf->nb_mirror_rule--;
2374         }
2375
2376         i40e_dev_free_queues(dev);
2377
2378         /* Disable interrupt */
2379         i40e_pf_disable_irq0(hw);
2380         rte_intr_disable(intr_handle);
2381
2382         i40e_fdir_teardown(pf);
2383
2384         /* shutdown and destroy the HMC */
2385         i40e_shutdown_lan_hmc(hw);
2386
2387         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2388                 i40e_vsi_release(pf->vmdq[i].vsi);
2389                 pf->vmdq[i].vsi = NULL;
2390         }
2391         rte_free(pf->vmdq);
2392         pf->vmdq = NULL;
2393
2394         /* release all the existing VSIs and VEBs */
2395         i40e_vsi_release(pf->main_vsi);
2396
2397         /* shutdown the adminq */
2398         i40e_aq_queue_shutdown(hw, true);
2399         i40e_shutdown_adminq(hw);
2400
2401         i40e_res_pool_destroy(&pf->qp_pool);
2402         i40e_res_pool_destroy(&pf->msix_pool);
2403
2404         /* Disable flexible payload in global configuration */
2405         if (!pf->support_multi_driver)
2406                 i40e_flex_payload_reg_set_default(hw);
2407
2408         /* force a PF reset to clean anything leftover */
2409         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2410         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2411                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2412         I40E_WRITE_FLUSH(hw);
2413 }
2414
2415 /*
2416  * Reset PF device only to re-initialize resources in PMD layer
2417  */
2418 static int
2419 i40e_dev_reset(struct rte_eth_dev *dev)
2420 {
2421         int ret;
2422
2423         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2424          * its VF to make them align with it. The detailed notification
2425          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2426          * To avoid unexpected behavior in VF, currently reset of PF with
2427          * SR-IOV activation is not supported. It might be supported later.
2428          */
2429         if (dev->data->sriov.active)
2430                 return -ENOTSUP;
2431
2432         ret = eth_i40e_dev_uninit(dev);
2433         if (ret)
2434                 return ret;
2435
2436         ret = eth_i40e_dev_init(dev, NULL);
2437
2438         return ret;
2439 }
2440
2441 static void
2442 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2443 {
2444         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2445         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2446         struct i40e_vsi *vsi = pf->main_vsi;
2447         int status;
2448
2449         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2450                                                      true, NULL, true);
2451         if (status != I40E_SUCCESS)
2452                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2453
2454         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2455                                                         TRUE, NULL);
2456         if (status != I40E_SUCCESS)
2457                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2458
2459 }
2460
2461 static void
2462 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2463 {
2464         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2465         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466         struct i40e_vsi *vsi = pf->main_vsi;
2467         int status;
2468
2469         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2470                                                      false, NULL, true);
2471         if (status != I40E_SUCCESS)
2472                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2473
2474         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2475                                                         false, NULL);
2476         if (status != I40E_SUCCESS)
2477                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2478 }
2479
2480 static void
2481 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2482 {
2483         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2484         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2485         struct i40e_vsi *vsi = pf->main_vsi;
2486         int ret;
2487
2488         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2489         if (ret != I40E_SUCCESS)
2490                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2491 }
2492
2493 static void
2494 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2495 {
2496         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2497         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2498         struct i40e_vsi *vsi = pf->main_vsi;
2499         int ret;
2500
2501         if (dev->data->promiscuous == 1)
2502                 return; /* must remain in all_multicast mode */
2503
2504         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2505                                 vsi->seid, FALSE, NULL);
2506         if (ret != I40E_SUCCESS)
2507                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2508 }
2509
2510 /*
2511  * Set device link up.
2512  */
2513 static int
2514 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2515 {
2516         /* re-apply link speed setting */
2517         return i40e_apply_link_speed(dev);
2518 }
2519
2520 /*
2521  * Set device link down.
2522  */
2523 static int
2524 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2525 {
2526         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2527         uint8_t abilities = 0;
2528         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2529
2530         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2531         return i40e_phy_conf_link(hw, abilities, speed, false);
2532 }
2533
2534 static __rte_always_inline void
2535 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2536 {
2537 /* Link status registers and values*/
2538 #define I40E_PRTMAC_LINKSTA             0x001E2420
2539 #define I40E_REG_LINK_UP                0x40000080
2540 #define I40E_PRTMAC_MACC                0x001E24E0
2541 #define I40E_REG_MACC_25GB              0x00020000
2542 #define I40E_REG_SPEED_MASK             0x38000000
2543 #define I40E_REG_SPEED_100MB            0x00000000
2544 #define I40E_REG_SPEED_1GB              0x08000000
2545 #define I40E_REG_SPEED_10GB             0x10000000
2546 #define I40E_REG_SPEED_20GB             0x20000000
2547 #define I40E_REG_SPEED_25_40GB          0x18000000
2548         uint32_t link_speed;
2549         uint32_t reg_val;
2550
2551         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2552         link_speed = reg_val & I40E_REG_SPEED_MASK;
2553         reg_val &= I40E_REG_LINK_UP;
2554         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2555
2556         if (unlikely(link->link_status == 0))
2557                 return;
2558
2559         /* Parse the link status */
2560         switch (link_speed) {
2561         case I40E_REG_SPEED_100MB:
2562                 link->link_speed = ETH_SPEED_NUM_100M;
2563                 break;
2564         case I40E_REG_SPEED_1GB:
2565                 link->link_speed = ETH_SPEED_NUM_1G;
2566                 break;
2567         case I40E_REG_SPEED_10GB:
2568                 link->link_speed = ETH_SPEED_NUM_10G;
2569                 break;
2570         case I40E_REG_SPEED_20GB:
2571                 link->link_speed = ETH_SPEED_NUM_20G;
2572                 break;
2573         case I40E_REG_SPEED_25_40GB:
2574                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2575
2576                 if (reg_val & I40E_REG_MACC_25GB)
2577                         link->link_speed = ETH_SPEED_NUM_25G;
2578                 else
2579                         link->link_speed = ETH_SPEED_NUM_40G;
2580
2581                 break;
2582         default:
2583                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2584                 break;
2585         }
2586 }
2587
2588 static __rte_always_inline void
2589 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2590         bool enable_lse, int wait_to_complete)
2591 {
2592 #define CHECK_INTERVAL             100  /* 100ms */
2593 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2594         uint32_t rep_cnt = MAX_REPEAT_TIME;
2595         struct i40e_link_status link_status;
2596         int status;
2597
2598         memset(&link_status, 0, sizeof(link_status));
2599
2600         do {
2601                 memset(&link_status, 0, sizeof(link_status));
2602
2603                 /* Get link status information from hardware */
2604                 status = i40e_aq_get_link_info(hw, enable_lse,
2605                                                 &link_status, NULL);
2606                 if (unlikely(status != I40E_SUCCESS)) {
2607                         link->link_speed = ETH_SPEED_NUM_100M;
2608                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2609                         PMD_DRV_LOG(ERR, "Failed to get link info");
2610                         return;
2611                 }
2612
2613                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2614                 if (!wait_to_complete || link->link_status)
2615                         break;
2616
2617                 rte_delay_ms(CHECK_INTERVAL);
2618         } while (--rep_cnt);
2619
2620         /* Parse the link status */
2621         switch (link_status.link_speed) {
2622         case I40E_LINK_SPEED_100MB:
2623                 link->link_speed = ETH_SPEED_NUM_100M;
2624                 break;
2625         case I40E_LINK_SPEED_1GB:
2626                 link->link_speed = ETH_SPEED_NUM_1G;
2627                 break;
2628         case I40E_LINK_SPEED_10GB:
2629                 link->link_speed = ETH_SPEED_NUM_10G;
2630                 break;
2631         case I40E_LINK_SPEED_20GB:
2632                 link->link_speed = ETH_SPEED_NUM_20G;
2633                 break;
2634         case I40E_LINK_SPEED_25GB:
2635                 link->link_speed = ETH_SPEED_NUM_25G;
2636                 break;
2637         case I40E_LINK_SPEED_40GB:
2638                 link->link_speed = ETH_SPEED_NUM_40G;
2639                 break;
2640         default:
2641                 link->link_speed = ETH_SPEED_NUM_100M;
2642                 break;
2643         }
2644 }
2645
2646 int
2647 i40e_dev_link_update(struct rte_eth_dev *dev,
2648                      int wait_to_complete)
2649 {
2650         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2651         struct rte_eth_link link;
2652         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2653         int ret;
2654
2655         memset(&link, 0, sizeof(link));
2656
2657         /* i40e uses full duplex only */
2658         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2659         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2660                         ETH_LINK_SPEED_FIXED);
2661
2662         if (!wait_to_complete && !enable_lse)
2663                 update_link_reg(hw, &link);
2664         else
2665                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2666
2667         ret = rte_eth_linkstatus_set(dev, &link);
2668         i40e_notify_all_vfs_link_status(dev);
2669
2670         return ret;
2671 }
2672
2673 /* Get all the statistics of a VSI */
2674 void
2675 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2676 {
2677         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2678         struct i40e_eth_stats *nes = &vsi->eth_stats;
2679         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2680         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2681
2682         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2683                             vsi->offset_loaded, &oes->rx_bytes,
2684                             &nes->rx_bytes);
2685         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2686                             vsi->offset_loaded, &oes->rx_unicast,
2687                             &nes->rx_unicast);
2688         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2689                             vsi->offset_loaded, &oes->rx_multicast,
2690                             &nes->rx_multicast);
2691         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2692                             vsi->offset_loaded, &oes->rx_broadcast,
2693                             &nes->rx_broadcast);
2694         /* exclude CRC bytes */
2695         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2696                 nes->rx_broadcast) * ETHER_CRC_LEN;
2697
2698         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2699                             &oes->rx_discards, &nes->rx_discards);
2700         /* GLV_REPC not supported */
2701         /* GLV_RMPC not supported */
2702         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2703                             &oes->rx_unknown_protocol,
2704                             &nes->rx_unknown_protocol);
2705         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2706                             vsi->offset_loaded, &oes->tx_bytes,
2707                             &nes->tx_bytes);
2708         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2709                             vsi->offset_loaded, &oes->tx_unicast,
2710                             &nes->tx_unicast);
2711         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2712                             vsi->offset_loaded, &oes->tx_multicast,
2713                             &nes->tx_multicast);
2714         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2715                             vsi->offset_loaded,  &oes->tx_broadcast,
2716                             &nes->tx_broadcast);
2717         /* GLV_TDPC not supported */
2718         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2719                             &oes->tx_errors, &nes->tx_errors);
2720         vsi->offset_loaded = true;
2721
2722         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2723                     vsi->vsi_id);
2724         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2725         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2726         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2727         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2728         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2729         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2730                     nes->rx_unknown_protocol);
2731         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2732         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2733         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2734         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2735         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2736         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2737         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2738                     vsi->vsi_id);
2739 }
2740
2741 static void
2742 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2743 {
2744         unsigned int i;
2745         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2746         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2747
2748         /* Get rx/tx bytes of internal transfer packets */
2749         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2750                         I40E_GLV_GORCL(hw->port),
2751                         pf->offset_loaded,
2752                         &pf->internal_stats_offset.rx_bytes,
2753                         &pf->internal_stats.rx_bytes);
2754
2755         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2756                         I40E_GLV_GOTCL(hw->port),
2757                         pf->offset_loaded,
2758                         &pf->internal_stats_offset.tx_bytes,
2759                         &pf->internal_stats.tx_bytes);
2760         /* Get total internal rx packet count */
2761         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2762                             I40E_GLV_UPRCL(hw->port),
2763                             pf->offset_loaded,
2764                             &pf->internal_stats_offset.rx_unicast,
2765                             &pf->internal_stats.rx_unicast);
2766         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2767                             I40E_GLV_MPRCL(hw->port),
2768                             pf->offset_loaded,
2769                             &pf->internal_stats_offset.rx_multicast,
2770                             &pf->internal_stats.rx_multicast);
2771         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2772                             I40E_GLV_BPRCL(hw->port),
2773                             pf->offset_loaded,
2774                             &pf->internal_stats_offset.rx_broadcast,
2775                             &pf->internal_stats.rx_broadcast);
2776         /* Get total internal tx packet count */
2777         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2778                             I40E_GLV_UPTCL(hw->port),
2779                             pf->offset_loaded,
2780                             &pf->internal_stats_offset.tx_unicast,
2781                             &pf->internal_stats.tx_unicast);
2782         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2783                             I40E_GLV_MPTCL(hw->port),
2784                             pf->offset_loaded,
2785                             &pf->internal_stats_offset.tx_multicast,
2786                             &pf->internal_stats.tx_multicast);
2787         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2788                             I40E_GLV_BPTCL(hw->port),
2789                             pf->offset_loaded,
2790                             &pf->internal_stats_offset.tx_broadcast,
2791                             &pf->internal_stats.tx_broadcast);
2792
2793         /* exclude CRC size */
2794         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2795                 pf->internal_stats.rx_multicast +
2796                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2797
2798         /* Get statistics of struct i40e_eth_stats */
2799         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2800                             I40E_GLPRT_GORCL(hw->port),
2801                             pf->offset_loaded, &os->eth.rx_bytes,
2802                             &ns->eth.rx_bytes);
2803         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2804                             I40E_GLPRT_UPRCL(hw->port),
2805                             pf->offset_loaded, &os->eth.rx_unicast,
2806                             &ns->eth.rx_unicast);
2807         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2808                             I40E_GLPRT_MPRCL(hw->port),
2809                             pf->offset_loaded, &os->eth.rx_multicast,
2810                             &ns->eth.rx_multicast);
2811         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2812                             I40E_GLPRT_BPRCL(hw->port),
2813                             pf->offset_loaded, &os->eth.rx_broadcast,
2814                             &ns->eth.rx_broadcast);
2815         /* Workaround: CRC size should not be included in byte statistics,
2816          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2817          */
2818         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2819                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2820
2821         /* exclude internal rx bytes
2822          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2823          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2824          * value.
2825          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2826          */
2827         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2828                 ns->eth.rx_bytes = 0;
2829         else
2830                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2831
2832         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2833                 ns->eth.rx_unicast = 0;
2834         else
2835                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2836
2837         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2838                 ns->eth.rx_multicast = 0;
2839         else
2840                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2841
2842         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2843                 ns->eth.rx_broadcast = 0;
2844         else
2845                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2846
2847         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2848                             pf->offset_loaded, &os->eth.rx_discards,
2849                             &ns->eth.rx_discards);
2850         /* GLPRT_REPC not supported */
2851         /* GLPRT_RMPC not supported */
2852         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2853                             pf->offset_loaded,
2854                             &os->eth.rx_unknown_protocol,
2855                             &ns->eth.rx_unknown_protocol);
2856         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2857                             I40E_GLPRT_GOTCL(hw->port),
2858                             pf->offset_loaded, &os->eth.tx_bytes,
2859                             &ns->eth.tx_bytes);
2860         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2861                             I40E_GLPRT_UPTCL(hw->port),
2862                             pf->offset_loaded, &os->eth.tx_unicast,
2863                             &ns->eth.tx_unicast);
2864         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2865                             I40E_GLPRT_MPTCL(hw->port),
2866                             pf->offset_loaded, &os->eth.tx_multicast,
2867                             &ns->eth.tx_multicast);
2868         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2869                             I40E_GLPRT_BPTCL(hw->port),
2870                             pf->offset_loaded, &os->eth.tx_broadcast,
2871                             &ns->eth.tx_broadcast);
2872         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2873                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2874
2875         /* exclude internal tx bytes
2876          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2877          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2878          * value.
2879          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2880          */
2881         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2882                 ns->eth.tx_bytes = 0;
2883         else
2884                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2885
2886         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2887                 ns->eth.tx_unicast = 0;
2888         else
2889                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2890
2891         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2892                 ns->eth.tx_multicast = 0;
2893         else
2894                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2895
2896         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2897                 ns->eth.tx_broadcast = 0;
2898         else
2899                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2900
2901         /* GLPRT_TEPC not supported */
2902
2903         /* additional port specific stats */
2904         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2905                             pf->offset_loaded, &os->tx_dropped_link_down,
2906                             &ns->tx_dropped_link_down);
2907         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2908                             pf->offset_loaded, &os->crc_errors,
2909                             &ns->crc_errors);
2910         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2911                             pf->offset_loaded, &os->illegal_bytes,
2912                             &ns->illegal_bytes);
2913         /* GLPRT_ERRBC not supported */
2914         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2915                             pf->offset_loaded, &os->mac_local_faults,
2916                             &ns->mac_local_faults);
2917         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2918                             pf->offset_loaded, &os->mac_remote_faults,
2919                             &ns->mac_remote_faults);
2920         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2921                             pf->offset_loaded, &os->rx_length_errors,
2922                             &ns->rx_length_errors);
2923         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2924                             pf->offset_loaded, &os->link_xon_rx,
2925                             &ns->link_xon_rx);
2926         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2927                             pf->offset_loaded, &os->link_xoff_rx,
2928                             &ns->link_xoff_rx);
2929         for (i = 0; i < 8; i++) {
2930                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2931                                     pf->offset_loaded,
2932                                     &os->priority_xon_rx[i],
2933                                     &ns->priority_xon_rx[i]);
2934                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2935                                     pf->offset_loaded,
2936                                     &os->priority_xoff_rx[i],
2937                                     &ns->priority_xoff_rx[i]);
2938         }
2939         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2940                             pf->offset_loaded, &os->link_xon_tx,
2941                             &ns->link_xon_tx);
2942         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2943                             pf->offset_loaded, &os->link_xoff_tx,
2944                             &ns->link_xoff_tx);
2945         for (i = 0; i < 8; i++) {
2946                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2947                                     pf->offset_loaded,
2948                                     &os->priority_xon_tx[i],
2949                                     &ns->priority_xon_tx[i]);
2950                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2951                                     pf->offset_loaded,
2952                                     &os->priority_xoff_tx[i],
2953                                     &ns->priority_xoff_tx[i]);
2954                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2955                                     pf->offset_loaded,
2956                                     &os->priority_xon_2_xoff[i],
2957                                     &ns->priority_xon_2_xoff[i]);
2958         }
2959         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2960                             I40E_GLPRT_PRC64L(hw->port),
2961                             pf->offset_loaded, &os->rx_size_64,
2962                             &ns->rx_size_64);
2963         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2964                             I40E_GLPRT_PRC127L(hw->port),
2965                             pf->offset_loaded, &os->rx_size_127,
2966                             &ns->rx_size_127);
2967         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2968                             I40E_GLPRT_PRC255L(hw->port),
2969                             pf->offset_loaded, &os->rx_size_255,
2970                             &ns->rx_size_255);
2971         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2972                             I40E_GLPRT_PRC511L(hw->port),
2973                             pf->offset_loaded, &os->rx_size_511,
2974                             &ns->rx_size_511);
2975         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2976                             I40E_GLPRT_PRC1023L(hw->port),
2977                             pf->offset_loaded, &os->rx_size_1023,
2978                             &ns->rx_size_1023);
2979         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2980                             I40E_GLPRT_PRC1522L(hw->port),
2981                             pf->offset_loaded, &os->rx_size_1522,
2982                             &ns->rx_size_1522);
2983         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2984                             I40E_GLPRT_PRC9522L(hw->port),
2985                             pf->offset_loaded, &os->rx_size_big,
2986                             &ns->rx_size_big);
2987         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2988                             pf->offset_loaded, &os->rx_undersize,
2989                             &ns->rx_undersize);
2990         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2991                             pf->offset_loaded, &os->rx_fragments,
2992                             &ns->rx_fragments);
2993         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2994                             pf->offset_loaded, &os->rx_oversize,
2995                             &ns->rx_oversize);
2996         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2997                             pf->offset_loaded, &os->rx_jabber,
2998                             &ns->rx_jabber);
2999         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3000                             I40E_GLPRT_PTC64L(hw->port),
3001                             pf->offset_loaded, &os->tx_size_64,
3002                             &ns->tx_size_64);
3003         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3004                             I40E_GLPRT_PTC127L(hw->port),
3005                             pf->offset_loaded, &os->tx_size_127,
3006                             &ns->tx_size_127);
3007         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3008                             I40E_GLPRT_PTC255L(hw->port),
3009                             pf->offset_loaded, &os->tx_size_255,
3010                             &ns->tx_size_255);
3011         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3012                             I40E_GLPRT_PTC511L(hw->port),
3013                             pf->offset_loaded, &os->tx_size_511,
3014                             &ns->tx_size_511);
3015         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3016                             I40E_GLPRT_PTC1023L(hw->port),
3017                             pf->offset_loaded, &os->tx_size_1023,
3018                             &ns->tx_size_1023);
3019         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3020                             I40E_GLPRT_PTC1522L(hw->port),
3021                             pf->offset_loaded, &os->tx_size_1522,
3022                             &ns->tx_size_1522);
3023         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3024                             I40E_GLPRT_PTC9522L(hw->port),
3025                             pf->offset_loaded, &os->tx_size_big,
3026                             &ns->tx_size_big);
3027         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3028                            pf->offset_loaded,
3029                            &os->fd_sb_match, &ns->fd_sb_match);
3030         /* GLPRT_MSPDC not supported */
3031         /* GLPRT_XEC not supported */
3032
3033         pf->offset_loaded = true;
3034
3035         if (pf->main_vsi)
3036                 i40e_update_vsi_stats(pf->main_vsi);
3037 }
3038
3039 /* Get all statistics of a port */
3040 static int
3041 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3042 {
3043         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3044         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3045         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3046         unsigned i;
3047
3048         /* call read registers - updates values, now write them to struct */
3049         i40e_read_stats_registers(pf, hw);
3050
3051         stats->ipackets = ns->eth.rx_unicast +
3052                         ns->eth.rx_multicast +
3053                         ns->eth.rx_broadcast -
3054                         ns->eth.rx_discards -
3055                         pf->main_vsi->eth_stats.rx_discards;
3056         stats->opackets = ns->eth.tx_unicast +
3057                         ns->eth.tx_multicast +
3058                         ns->eth.tx_broadcast;
3059         stats->ibytes   = ns->eth.rx_bytes;
3060         stats->obytes   = ns->eth.tx_bytes;
3061         stats->oerrors  = ns->eth.tx_errors +
3062                         pf->main_vsi->eth_stats.tx_errors;
3063
3064         /* Rx Errors */
3065         stats->imissed  = ns->eth.rx_discards +
3066                         pf->main_vsi->eth_stats.rx_discards;
3067         stats->ierrors  = ns->crc_errors +
3068                         ns->rx_length_errors + ns->rx_undersize +
3069                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3070
3071         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3072         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3073         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3074         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3075         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3076         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3077         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3078                     ns->eth.rx_unknown_protocol);
3079         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3080         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3081         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3082         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3083         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3084         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3085
3086         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3087                     ns->tx_dropped_link_down);
3088         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3089         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3090                     ns->illegal_bytes);
3091         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3092         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3093                     ns->mac_local_faults);
3094         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3095                     ns->mac_remote_faults);
3096         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3097                     ns->rx_length_errors);
3098         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3099         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3100         for (i = 0; i < 8; i++) {
3101                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3102                                 i, ns->priority_xon_rx[i]);
3103                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3104                                 i, ns->priority_xoff_rx[i]);
3105         }
3106         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3107         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3108         for (i = 0; i < 8; i++) {
3109                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3110                                 i, ns->priority_xon_tx[i]);
3111                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3112                                 i, ns->priority_xoff_tx[i]);
3113                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3114                                 i, ns->priority_xon_2_xoff[i]);
3115         }
3116         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3117         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3118         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3119         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3120         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3121         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3122         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3123         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3124         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3125         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3126         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3127         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3128         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3129         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3130         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3131         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3132         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3133         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3134         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3135                         ns->mac_short_packet_dropped);
3136         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3137                     ns->checksum_error);
3138         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3139         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3140         return 0;
3141 }
3142
3143 /* Reset the statistics */
3144 static void
3145 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3146 {
3147         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3148         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3149
3150         /* Mark PF and VSI stats to update the offset, aka "reset" */
3151         pf->offset_loaded = false;
3152         if (pf->main_vsi)
3153                 pf->main_vsi->offset_loaded = false;
3154
3155         /* read the stats, reading current register values into offset */
3156         i40e_read_stats_registers(pf, hw);
3157 }
3158
3159 static uint32_t
3160 i40e_xstats_calc_num(void)
3161 {
3162         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3163                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3164                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3165 }
3166
3167 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3168                                      struct rte_eth_xstat_name *xstats_names,
3169                                      __rte_unused unsigned limit)
3170 {
3171         unsigned count = 0;
3172         unsigned i, prio;
3173
3174         if (xstats_names == NULL)
3175                 return i40e_xstats_calc_num();
3176
3177         /* Note: limit checked in rte_eth_xstats_names() */
3178
3179         /* Get stats from i40e_eth_stats struct */
3180         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3181                 snprintf(xstats_names[count].name,
3182                          sizeof(xstats_names[count].name),
3183                          "%s", rte_i40e_stats_strings[i].name);
3184                 count++;
3185         }
3186
3187         /* Get individiual stats from i40e_hw_port struct */
3188         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3189                 snprintf(xstats_names[count].name,
3190                         sizeof(xstats_names[count].name),
3191                          "%s", rte_i40e_hw_port_strings[i].name);
3192                 count++;
3193         }
3194
3195         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3196                 for (prio = 0; prio < 8; prio++) {
3197                         snprintf(xstats_names[count].name,
3198                                  sizeof(xstats_names[count].name),
3199                                  "rx_priority%u_%s", prio,
3200                                  rte_i40e_rxq_prio_strings[i].name);
3201                         count++;
3202                 }
3203         }
3204
3205         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3206                 for (prio = 0; prio < 8; prio++) {
3207                         snprintf(xstats_names[count].name,
3208                                  sizeof(xstats_names[count].name),
3209                                  "tx_priority%u_%s", prio,
3210                                  rte_i40e_txq_prio_strings[i].name);
3211                         count++;
3212                 }
3213         }
3214         return count;
3215 }
3216
3217 static int
3218 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3219                     unsigned n)
3220 {
3221         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3222         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3223         unsigned i, count, prio;
3224         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3225
3226         count = i40e_xstats_calc_num();
3227         if (n < count)
3228                 return count;
3229
3230         i40e_read_stats_registers(pf, hw);
3231
3232         if (xstats == NULL)
3233                 return 0;
3234
3235         count = 0;
3236
3237         /* Get stats from i40e_eth_stats struct */
3238         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3239                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3240                         rte_i40e_stats_strings[i].offset);
3241                 xstats[count].id = count;
3242                 count++;
3243         }
3244
3245         /* Get individiual stats from i40e_hw_port struct */
3246         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3247                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3248                         rte_i40e_hw_port_strings[i].offset);
3249                 xstats[count].id = count;
3250                 count++;
3251         }
3252
3253         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3254                 for (prio = 0; prio < 8; prio++) {
3255                         xstats[count].value =
3256                                 *(uint64_t *)(((char *)hw_stats) +
3257                                 rte_i40e_rxq_prio_strings[i].offset +
3258                                 (sizeof(uint64_t) * prio));
3259                         xstats[count].id = count;
3260                         count++;
3261                 }
3262         }
3263
3264         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3265                 for (prio = 0; prio < 8; prio++) {
3266                         xstats[count].value =
3267                                 *(uint64_t *)(((char *)hw_stats) +
3268                                 rte_i40e_txq_prio_strings[i].offset +
3269                                 (sizeof(uint64_t) * prio));
3270                         xstats[count].id = count;
3271                         count++;
3272                 }
3273         }
3274
3275         return count;
3276 }
3277
3278 static int
3279 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3280                                  __rte_unused uint16_t queue_id,
3281                                  __rte_unused uint8_t stat_idx,
3282                                  __rte_unused uint8_t is_rx)
3283 {
3284         PMD_INIT_FUNC_TRACE();
3285
3286         return -ENOSYS;
3287 }
3288
3289 static int
3290 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3291 {
3292         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3293         u32 full_ver;
3294         u8 ver, patch;
3295         u16 build;
3296         int ret;
3297
3298         full_ver = hw->nvm.oem_ver;
3299         ver = (u8)(full_ver >> 24);
3300         build = (u16)((full_ver >> 8) & 0xffff);
3301         patch = (u8)(full_ver & 0xff);
3302
3303         ret = snprintf(fw_version, fw_size,
3304                  "%d.%d%d 0x%08x %d.%d.%d",
3305                  ((hw->nvm.version >> 12) & 0xf),
3306                  ((hw->nvm.version >> 4) & 0xff),
3307                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3308                  ver, build, patch);
3309
3310         ret += 1; /* add the size of '\0' */
3311         if (fw_size < (u32)ret)
3312                 return ret;
3313         else
3314                 return 0;
3315 }
3316
3317 static void
3318 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3319 {
3320         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3321         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3322         struct i40e_vsi *vsi = pf->main_vsi;
3323         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3324
3325         dev_info->max_rx_queues = vsi->nb_qps;
3326         dev_info->max_tx_queues = vsi->nb_qps;
3327         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3328         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3329         dev_info->max_mac_addrs = vsi->max_macaddrs;
3330         dev_info->max_vfs = pci_dev->max_vfs;
3331         dev_info->rx_queue_offload_capa = 0;
3332         dev_info->rx_offload_capa =
3333                 DEV_RX_OFFLOAD_VLAN_STRIP |
3334                 DEV_RX_OFFLOAD_QINQ_STRIP |
3335                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3336                 DEV_RX_OFFLOAD_UDP_CKSUM |
3337                 DEV_RX_OFFLOAD_TCP_CKSUM |
3338                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3339                 DEV_RX_OFFLOAD_CRC_STRIP |
3340                 DEV_RX_OFFLOAD_KEEP_CRC |
3341                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3342                 DEV_RX_OFFLOAD_VLAN_FILTER |
3343                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3344
3345         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3346         dev_info->tx_offload_capa =
3347                 DEV_TX_OFFLOAD_VLAN_INSERT |
3348                 DEV_TX_OFFLOAD_QINQ_INSERT |
3349                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3350                 DEV_TX_OFFLOAD_UDP_CKSUM |
3351                 DEV_TX_OFFLOAD_TCP_CKSUM |
3352                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3353                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3354                 DEV_TX_OFFLOAD_TCP_TSO |
3355                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3356                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3357                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3358                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3359                 DEV_TX_OFFLOAD_MULTI_SEGS |
3360                 dev_info->tx_queue_offload_capa;
3361         dev_info->dev_capa =
3362                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3363                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3364
3365         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3366                                                 sizeof(uint32_t);
3367         dev_info->reta_size = pf->hash_lut_size;
3368         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3369
3370         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3371                 .rx_thresh = {
3372                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3373                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3374                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3375                 },
3376                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3377                 .rx_drop_en = 0,
3378                 .offloads = 0,
3379         };
3380
3381         dev_info->default_txconf = (struct rte_eth_txconf) {
3382                 .tx_thresh = {
3383                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3384                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3385                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3386                 },
3387                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3388                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3389                 .offloads = 0,
3390         };
3391
3392         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3393                 .nb_max = I40E_MAX_RING_DESC,
3394                 .nb_min = I40E_MIN_RING_DESC,
3395                 .nb_align = I40E_ALIGN_RING_DESC,
3396         };
3397
3398         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3399                 .nb_max = I40E_MAX_RING_DESC,
3400                 .nb_min = I40E_MIN_RING_DESC,
3401                 .nb_align = I40E_ALIGN_RING_DESC,
3402                 .nb_seg_max = I40E_TX_MAX_SEG,
3403                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3404         };
3405
3406         if (pf->flags & I40E_FLAG_VMDQ) {
3407                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3408                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3409                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3410                                                 pf->max_nb_vmdq_vsi;
3411                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3412                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3413                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3414         }
3415
3416         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3417                 /* For XL710 */
3418                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3419                 dev_info->default_rxportconf.nb_queues = 2;
3420                 dev_info->default_txportconf.nb_queues = 2;
3421                 if (dev->data->nb_rx_queues == 1)
3422                         dev_info->default_rxportconf.ring_size = 2048;
3423                 else
3424                         dev_info->default_rxportconf.ring_size = 1024;
3425                 if (dev->data->nb_tx_queues == 1)
3426                         dev_info->default_txportconf.ring_size = 1024;
3427                 else
3428                         dev_info->default_txportconf.ring_size = 512;
3429
3430         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3431                 /* For XXV710 */
3432                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3433                 dev_info->default_rxportconf.nb_queues = 1;
3434                 dev_info->default_txportconf.nb_queues = 1;
3435                 dev_info->default_rxportconf.ring_size = 256;
3436                 dev_info->default_txportconf.ring_size = 256;
3437         } else {
3438                 /* For X710 */
3439                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3440                 dev_info->default_rxportconf.nb_queues = 1;
3441                 dev_info->default_txportconf.nb_queues = 1;
3442                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3443                         dev_info->default_rxportconf.ring_size = 512;
3444                         dev_info->default_txportconf.ring_size = 256;
3445                 } else {
3446                         dev_info->default_rxportconf.ring_size = 256;
3447                         dev_info->default_txportconf.ring_size = 256;
3448                 }
3449         }
3450         dev_info->default_rxportconf.burst_size = 32;
3451         dev_info->default_txportconf.burst_size = 32;
3452 }
3453
3454 static int
3455 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3456 {
3457         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3458         struct i40e_vsi *vsi = pf->main_vsi;
3459         PMD_INIT_FUNC_TRACE();
3460
3461         if (on)
3462                 return i40e_vsi_add_vlan(vsi, vlan_id);
3463         else
3464                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3465 }
3466
3467 static int
3468 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3469                                 enum rte_vlan_type vlan_type,
3470                                 uint16_t tpid, int qinq)
3471 {
3472         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3473         uint64_t reg_r = 0;
3474         uint64_t reg_w = 0;
3475         uint16_t reg_id = 3;
3476         int ret;
3477
3478         if (qinq) {
3479                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3480                         reg_id = 2;
3481         }
3482
3483         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3484                                           &reg_r, NULL);
3485         if (ret != I40E_SUCCESS) {
3486                 PMD_DRV_LOG(ERR,
3487                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3488                            reg_id);
3489                 return -EIO;
3490         }
3491         PMD_DRV_LOG(DEBUG,
3492                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3493                     reg_id, reg_r);
3494
3495         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3496         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3497         if (reg_r == reg_w) {
3498                 PMD_DRV_LOG(DEBUG, "No need to write");
3499                 return 0;
3500         }
3501
3502         ret = i40e_aq_debug_write_global_register(hw,
3503                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3504                                            reg_w, NULL);
3505         if (ret != I40E_SUCCESS) {
3506                 PMD_DRV_LOG(ERR,
3507                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3508                             reg_id);
3509                 return -EIO;
3510         }
3511         PMD_DRV_LOG(DEBUG,
3512                     "Global register 0x%08x is changed with value 0x%08x",
3513                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3514
3515         return 0;
3516 }
3517
3518 static int
3519 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3520                    enum rte_vlan_type vlan_type,
3521                    uint16_t tpid)
3522 {
3523         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3524         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3525         int qinq = dev->data->dev_conf.rxmode.offloads &
3526                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3527         int ret = 0;
3528
3529         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3530              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3531             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3532                 PMD_DRV_LOG(ERR,
3533                             "Unsupported vlan type.");
3534                 return -EINVAL;
3535         }
3536
3537         if (pf->support_multi_driver) {
3538                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3539                 return -ENOTSUP;
3540         }
3541
3542         /* 802.1ad frames ability is added in NVM API 1.7*/
3543         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3544                 if (qinq) {
3545                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3546                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3547                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3548                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3549                 } else {
3550                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3551                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3552                 }
3553                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3554                 if (ret != I40E_SUCCESS) {
3555                         PMD_DRV_LOG(ERR,
3556                                     "Set switch config failed aq_err: %d",
3557                                     hw->aq.asq_last_status);
3558                         ret = -EIO;
3559                 }
3560         } else
3561                 /* If NVM API < 1.7, keep the register setting */
3562                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3563                                                       tpid, qinq);
3564
3565         return ret;
3566 }
3567
3568 static int
3569 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3570 {
3571         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3572         struct i40e_vsi *vsi = pf->main_vsi;
3573         struct rte_eth_rxmode *rxmode;
3574
3575         rxmode = &dev->data->dev_conf.rxmode;
3576         if (mask & ETH_VLAN_FILTER_MASK) {
3577                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3578                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3579                 else
3580                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3581         }
3582
3583         if (mask & ETH_VLAN_STRIP_MASK) {
3584                 /* Enable or disable VLAN stripping */
3585                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3586                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3587                 else
3588                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3589         }
3590
3591         if (mask & ETH_VLAN_EXTEND_MASK) {
3592                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3593                         i40e_vsi_config_double_vlan(vsi, TRUE);
3594                         /* Set global registers with default ethertype. */
3595                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3596                                            ETHER_TYPE_VLAN);
3597                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3598                                            ETHER_TYPE_VLAN);
3599                 }
3600                 else
3601                         i40e_vsi_config_double_vlan(vsi, FALSE);
3602         }
3603
3604         return 0;
3605 }
3606
3607 static void
3608 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3609                           __rte_unused uint16_t queue,
3610                           __rte_unused int on)
3611 {
3612         PMD_INIT_FUNC_TRACE();
3613 }
3614
3615 static int
3616 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3617 {
3618         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3619         struct i40e_vsi *vsi = pf->main_vsi;
3620         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3621         struct i40e_vsi_vlan_pvid_info info;
3622
3623         memset(&info, 0, sizeof(info));
3624         info.on = on;
3625         if (info.on)
3626                 info.config.pvid = pvid;
3627         else {
3628                 info.config.reject.tagged =
3629                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3630                 info.config.reject.untagged =
3631                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3632         }
3633
3634         return i40e_vsi_vlan_pvid_set(vsi, &info);
3635 }
3636
3637 static int
3638 i40e_dev_led_on(struct rte_eth_dev *dev)
3639 {
3640         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3641         uint32_t mode = i40e_led_get(hw);
3642
3643         if (mode == 0)
3644                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3645
3646         return 0;
3647 }
3648
3649 static int
3650 i40e_dev_led_off(struct rte_eth_dev *dev)
3651 {
3652         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3653         uint32_t mode = i40e_led_get(hw);
3654
3655         if (mode != 0)
3656                 i40e_led_set(hw, 0, false);
3657
3658         return 0;
3659 }
3660
3661 static int
3662 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3663 {
3664         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3665         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3666
3667         fc_conf->pause_time = pf->fc_conf.pause_time;
3668
3669         /* read out from register, in case they are modified by other port */
3670         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3671                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3672         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3673                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3674
3675         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3676         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3677
3678          /* Return current mode according to actual setting*/
3679         switch (hw->fc.current_mode) {
3680         case I40E_FC_FULL:
3681                 fc_conf->mode = RTE_FC_FULL;
3682                 break;
3683         case I40E_FC_TX_PAUSE:
3684                 fc_conf->mode = RTE_FC_TX_PAUSE;
3685                 break;
3686         case I40E_FC_RX_PAUSE:
3687                 fc_conf->mode = RTE_FC_RX_PAUSE;
3688                 break;
3689         case I40E_FC_NONE:
3690         default:
3691                 fc_conf->mode = RTE_FC_NONE;
3692         };
3693
3694         return 0;
3695 }
3696
3697 static int
3698 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3699 {
3700         uint32_t mflcn_reg, fctrl_reg, reg;
3701         uint32_t max_high_water;
3702         uint8_t i, aq_failure;
3703         int err;
3704         struct i40e_hw *hw;
3705         struct i40e_pf *pf;
3706         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3707                 [RTE_FC_NONE] = I40E_FC_NONE,
3708                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3709                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3710                 [RTE_FC_FULL] = I40E_FC_FULL
3711         };
3712
3713         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3714
3715         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3716         if ((fc_conf->high_water > max_high_water) ||
3717                         (fc_conf->high_water < fc_conf->low_water)) {
3718                 PMD_INIT_LOG(ERR,
3719                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3720                         max_high_water);
3721                 return -EINVAL;
3722         }
3723
3724         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3725         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3726         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3727
3728         pf->fc_conf.pause_time = fc_conf->pause_time;
3729         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3730         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3731
3732         PMD_INIT_FUNC_TRACE();
3733
3734         /* All the link flow control related enable/disable register
3735          * configuration is handle by the F/W
3736          */
3737         err = i40e_set_fc(hw, &aq_failure, true);
3738         if (err < 0)
3739                 return -ENOSYS;
3740
3741         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3742                 /* Configure flow control refresh threshold,
3743                  * the value for stat_tx_pause_refresh_timer[8]
3744                  * is used for global pause operation.
3745                  */
3746
3747                 I40E_WRITE_REG(hw,
3748                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3749                                pf->fc_conf.pause_time);
3750
3751                 /* configure the timer value included in transmitted pause
3752                  * frame,
3753                  * the value for stat_tx_pause_quanta[8] is used for global
3754                  * pause operation
3755                  */
3756                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3757                                pf->fc_conf.pause_time);
3758
3759                 fctrl_reg = I40E_READ_REG(hw,
3760                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3761
3762                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3763                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3764                 else
3765                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3766
3767                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3768                                fctrl_reg);
3769         } else {
3770                 /* Configure pause time (2 TCs per register) */
3771                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3772                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3773                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3774
3775                 /* Configure flow control refresh threshold value */
3776                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3777                                pf->fc_conf.pause_time / 2);
3778
3779                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3780
3781                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3782                  *depending on configuration
3783                  */
3784                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3785                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3786                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3787                 } else {
3788                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3789                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3790                 }
3791
3792                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3793         }
3794
3795         if (!pf->support_multi_driver) {
3796                 /* config water marker both based on the packets and bytes */
3797                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3798                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3799                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3800                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3801                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3802                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3803                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3804                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3805                                   << I40E_KILOSHIFT);
3806                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3807                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3808                                    << I40E_KILOSHIFT);
3809         } else {
3810                 PMD_DRV_LOG(ERR,
3811                             "Water marker configuration is not supported.");
3812         }
3813
3814         I40E_WRITE_FLUSH(hw);
3815
3816         return 0;
3817 }
3818
3819 static int
3820 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3821                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3822 {
3823         PMD_INIT_FUNC_TRACE();
3824
3825         return -ENOSYS;
3826 }
3827
3828 /* Add a MAC address, and update filters */
3829 static int
3830 i40e_macaddr_add(struct rte_eth_dev *dev,
3831                  struct ether_addr *mac_addr,
3832                  __rte_unused uint32_t index,
3833                  uint32_t pool)
3834 {
3835         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3836         struct i40e_mac_filter_info mac_filter;
3837         struct i40e_vsi *vsi;
3838         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3839         int ret;
3840
3841         /* If VMDQ not enabled or configured, return */
3842         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3843                           !pf->nb_cfg_vmdq_vsi)) {
3844                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3845                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3846                         pool);
3847                 return -ENOTSUP;
3848         }
3849
3850         if (pool > pf->nb_cfg_vmdq_vsi) {
3851                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3852                                 pool, pf->nb_cfg_vmdq_vsi);
3853                 return -EINVAL;
3854         }
3855
3856         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3857         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3858                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3859         else
3860                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3861
3862         if (pool == 0)
3863                 vsi = pf->main_vsi;
3864         else
3865                 vsi = pf->vmdq[pool - 1].vsi;
3866
3867         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3868         if (ret != I40E_SUCCESS) {
3869                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3870                 return -ENODEV;
3871         }
3872         return 0;
3873 }
3874
3875 /* Remove a MAC address, and update filters */
3876 static void
3877 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3878 {
3879         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3880         struct i40e_vsi *vsi;
3881         struct rte_eth_dev_data *data = dev->data;
3882         struct ether_addr *macaddr;
3883         int ret;
3884         uint32_t i;
3885         uint64_t pool_sel;
3886
3887         macaddr = &(data->mac_addrs[index]);
3888
3889         pool_sel = dev->data->mac_pool_sel[index];
3890
3891         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3892                 if (pool_sel & (1ULL << i)) {
3893                         if (i == 0)
3894                                 vsi = pf->main_vsi;
3895                         else {
3896                                 /* No VMDQ pool enabled or configured */
3897                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3898                                         (i > pf->nb_cfg_vmdq_vsi)) {
3899                                         PMD_DRV_LOG(ERR,
3900                                                 "No VMDQ pool enabled/configured");
3901                                         return;
3902                                 }
3903                                 vsi = pf->vmdq[i - 1].vsi;
3904                         }
3905                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3906
3907                         if (ret) {
3908                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3909                                 return;
3910                         }
3911                 }
3912         }
3913 }
3914
3915 /* Set perfect match or hash match of MAC and VLAN for a VF */
3916 static int
3917 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3918                  struct rte_eth_mac_filter *filter,
3919                  bool add)
3920 {
3921         struct i40e_hw *hw;
3922         struct i40e_mac_filter_info mac_filter;
3923         struct ether_addr old_mac;
3924         struct ether_addr *new_mac;
3925         struct i40e_pf_vf *vf = NULL;
3926         uint16_t vf_id;
3927         int ret;
3928
3929         if (pf == NULL) {
3930                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3931                 return -EINVAL;
3932         }
3933         hw = I40E_PF_TO_HW(pf);
3934
3935         if (filter == NULL) {
3936                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3937                 return -EINVAL;
3938         }
3939
3940         new_mac = &filter->mac_addr;
3941
3942         if (is_zero_ether_addr(new_mac)) {
3943                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3944                 return -EINVAL;
3945         }
3946
3947         vf_id = filter->dst_id;
3948
3949         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3950                 PMD_DRV_LOG(ERR, "Invalid argument.");
3951                 return -EINVAL;
3952         }
3953         vf = &pf->vfs[vf_id];
3954
3955         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3956                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3957                 return -EINVAL;
3958         }
3959
3960         if (add) {
3961                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3962                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3963                                 ETHER_ADDR_LEN);
3964                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3965                                  ETHER_ADDR_LEN);
3966
3967                 mac_filter.filter_type = filter->filter_type;
3968                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3969                 if (ret != I40E_SUCCESS) {
3970                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3971                         return -1;
3972                 }
3973                 ether_addr_copy(new_mac, &pf->dev_addr);
3974         } else {
3975                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3976                                 ETHER_ADDR_LEN);
3977                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3978                 if (ret != I40E_SUCCESS) {
3979                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3980                         return -1;
3981                 }
3982
3983                 /* Clear device address as it has been removed */
3984                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3985                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3986         }
3987
3988         return 0;
3989 }
3990
3991 /* MAC filter handle */
3992 static int
3993 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3994                 void *arg)
3995 {
3996         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3997         struct rte_eth_mac_filter *filter;
3998         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3999         int ret = I40E_NOT_SUPPORTED;
4000
4001         filter = (struct rte_eth_mac_filter *)(arg);
4002
4003         switch (filter_op) {
4004         case RTE_ETH_FILTER_NOP:
4005                 ret = I40E_SUCCESS;
4006                 break;
4007         case RTE_ETH_FILTER_ADD:
4008                 i40e_pf_disable_irq0(hw);
4009                 if (filter->is_vf)
4010                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4011                 i40e_pf_enable_irq0(hw);
4012                 break;
4013         case RTE_ETH_FILTER_DELETE:
4014                 i40e_pf_disable_irq0(hw);
4015                 if (filter->is_vf)
4016                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4017                 i40e_pf_enable_irq0(hw);
4018                 break;
4019         default:
4020                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4021                 ret = I40E_ERR_PARAM;
4022                 break;
4023         }
4024
4025         return ret;
4026 }
4027
4028 static int
4029 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4030 {
4031         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4032         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4033         uint32_t reg;
4034         int ret;
4035
4036         if (!lut)
4037                 return -EINVAL;
4038
4039         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4040                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4041                                           lut, lut_size);
4042                 if (ret) {
4043                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4044                         return ret;
4045                 }
4046         } else {
4047                 uint32_t *lut_dw = (uint32_t *)lut;
4048                 uint16_t i, lut_size_dw = lut_size / 4;
4049
4050                 if (vsi->type == I40E_VSI_SRIOV) {
4051                         for (i = 0; i <= lut_size_dw; i++) {
4052                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4053                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4054                         }
4055                 } else {
4056                         for (i = 0; i < lut_size_dw; i++)
4057                                 lut_dw[i] = I40E_READ_REG(hw,
4058                                                           I40E_PFQF_HLUT(i));
4059                 }
4060         }
4061
4062         return 0;
4063 }
4064
4065 int
4066 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4067 {
4068         struct i40e_pf *pf;
4069         struct i40e_hw *hw;
4070         int ret;
4071
4072         if (!vsi || !lut)
4073                 return -EINVAL;
4074
4075         pf = I40E_VSI_TO_PF(vsi);
4076         hw = I40E_VSI_TO_HW(vsi);
4077
4078         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4079                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4080                                           lut, lut_size);
4081                 if (ret) {
4082                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4083                         return ret;
4084                 }
4085         } else {
4086                 uint32_t *lut_dw = (uint32_t *)lut;
4087                 uint16_t i, lut_size_dw = lut_size / 4;
4088
4089                 if (vsi->type == I40E_VSI_SRIOV) {
4090                         for (i = 0; i < lut_size_dw; i++)
4091                                 I40E_WRITE_REG(
4092                                         hw,
4093                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4094                                         lut_dw[i]);
4095                 } else {
4096                         for (i = 0; i < lut_size_dw; i++)
4097                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4098                                                lut_dw[i]);
4099                 }
4100                 I40E_WRITE_FLUSH(hw);
4101         }
4102
4103         return 0;
4104 }
4105
4106 static int
4107 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4108                          struct rte_eth_rss_reta_entry64 *reta_conf,
4109                          uint16_t reta_size)
4110 {
4111         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4112         uint16_t i, lut_size = pf->hash_lut_size;
4113         uint16_t idx, shift;
4114         uint8_t *lut;
4115         int ret;
4116
4117         if (reta_size != lut_size ||
4118                 reta_size > ETH_RSS_RETA_SIZE_512) {
4119                 PMD_DRV_LOG(ERR,
4120                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4121                         reta_size, lut_size);
4122                 return -EINVAL;
4123         }
4124
4125         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4126         if (!lut) {
4127                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4128                 return -ENOMEM;
4129         }
4130         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4131         if (ret)
4132                 goto out;
4133         for (i = 0; i < reta_size; i++) {
4134                 idx = i / RTE_RETA_GROUP_SIZE;
4135                 shift = i % RTE_RETA_GROUP_SIZE;
4136                 if (reta_conf[idx].mask & (1ULL << shift))
4137                         lut[i] = reta_conf[idx].reta[shift];
4138         }
4139         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4140
4141 out:
4142         rte_free(lut);
4143
4144         return ret;
4145 }
4146
4147 static int
4148 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4149                         struct rte_eth_rss_reta_entry64 *reta_conf,
4150                         uint16_t reta_size)
4151 {
4152         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4153         uint16_t i, lut_size = pf->hash_lut_size;
4154         uint16_t idx, shift;
4155         uint8_t *lut;
4156         int ret;
4157
4158         if (reta_size != lut_size ||
4159                 reta_size > ETH_RSS_RETA_SIZE_512) {
4160                 PMD_DRV_LOG(ERR,
4161                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4162                         reta_size, lut_size);
4163                 return -EINVAL;
4164         }
4165
4166         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4167         if (!lut) {
4168                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4169                 return -ENOMEM;
4170         }
4171
4172         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4173         if (ret)
4174                 goto out;
4175         for (i = 0; i < reta_size; i++) {
4176                 idx = i / RTE_RETA_GROUP_SIZE;
4177                 shift = i % RTE_RETA_GROUP_SIZE;
4178                 if (reta_conf[idx].mask & (1ULL << shift))
4179                         reta_conf[idx].reta[shift] = lut[i];
4180         }
4181
4182 out:
4183         rte_free(lut);
4184
4185         return ret;
4186 }
4187
4188 /**
4189  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4190  * @hw:   pointer to the HW structure
4191  * @mem:  pointer to mem struct to fill out
4192  * @size: size of memory requested
4193  * @alignment: what to align the allocation to
4194  **/
4195 enum i40e_status_code
4196 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4197                         struct i40e_dma_mem *mem,
4198                         u64 size,
4199                         u32 alignment)
4200 {
4201         const struct rte_memzone *mz = NULL;
4202         char z_name[RTE_MEMZONE_NAMESIZE];
4203
4204         if (!mem)
4205                 return I40E_ERR_PARAM;
4206
4207         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4208         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4209                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4210         if (!mz)
4211                 return I40E_ERR_NO_MEMORY;
4212
4213         mem->size = size;
4214         mem->va = mz->addr;
4215         mem->pa = mz->iova;
4216         mem->zone = (const void *)mz;
4217         PMD_DRV_LOG(DEBUG,
4218                 "memzone %s allocated with physical address: %"PRIu64,
4219                 mz->name, mem->pa);
4220
4221         return I40E_SUCCESS;
4222 }
4223
4224 /**
4225  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4226  * @hw:   pointer to the HW structure
4227  * @mem:  ptr to mem struct to free
4228  **/
4229 enum i40e_status_code
4230 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4231                     struct i40e_dma_mem *mem)
4232 {
4233         if (!mem)
4234                 return I40E_ERR_PARAM;
4235
4236         PMD_DRV_LOG(DEBUG,
4237                 "memzone %s to be freed with physical address: %"PRIu64,
4238                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4239         rte_memzone_free((const struct rte_memzone *)mem->zone);
4240         mem->zone = NULL;
4241         mem->va = NULL;
4242         mem->pa = (u64)0;
4243
4244         return I40E_SUCCESS;
4245 }
4246
4247 /**
4248  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4249  * @hw:   pointer to the HW structure
4250  * @mem:  pointer to mem struct to fill out
4251  * @size: size of memory requested
4252  **/
4253 enum i40e_status_code
4254 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4255                          struct i40e_virt_mem *mem,
4256                          u32 size)
4257 {
4258         if (!mem)
4259                 return I40E_ERR_PARAM;
4260
4261         mem->size = size;
4262         mem->va = rte_zmalloc("i40e", size, 0);
4263
4264         if (mem->va)
4265                 return I40E_SUCCESS;
4266         else
4267                 return I40E_ERR_NO_MEMORY;
4268 }
4269
4270 /**
4271  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4272  * @hw:   pointer to the HW structure
4273  * @mem:  pointer to mem struct to free
4274  **/
4275 enum i40e_status_code
4276 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4277                      struct i40e_virt_mem *mem)
4278 {
4279         if (!mem)
4280                 return I40E_ERR_PARAM;
4281
4282         rte_free(mem->va);
4283         mem->va = NULL;
4284
4285         return I40E_SUCCESS;
4286 }
4287
4288 void
4289 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4290 {
4291         rte_spinlock_init(&sp->spinlock);
4292 }
4293
4294 void
4295 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4296 {
4297         rte_spinlock_lock(&sp->spinlock);
4298 }
4299
4300 void
4301 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4302 {
4303         rte_spinlock_unlock(&sp->spinlock);
4304 }
4305
4306 void
4307 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4308 {
4309         return;
4310 }
4311
4312 /**
4313  * Get the hardware capabilities, which will be parsed
4314  * and saved into struct i40e_hw.
4315  */
4316 static int
4317 i40e_get_cap(struct i40e_hw *hw)
4318 {
4319         struct i40e_aqc_list_capabilities_element_resp *buf;
4320         uint16_t len, size = 0;
4321         int ret;
4322
4323         /* Calculate a huge enough buff for saving response data temporarily */
4324         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4325                                                 I40E_MAX_CAP_ELE_NUM;
4326         buf = rte_zmalloc("i40e", len, 0);
4327         if (!buf) {
4328                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4329                 return I40E_ERR_NO_MEMORY;
4330         }
4331
4332         /* Get, parse the capabilities and save it to hw */
4333         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4334                         i40e_aqc_opc_list_func_capabilities, NULL);
4335         if (ret != I40E_SUCCESS)
4336                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4337
4338         /* Free the temporary buffer after being used */
4339         rte_free(buf);
4340
4341         return ret;
4342 }
4343
4344 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4345 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
4346
4347 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4348                 const char *value,
4349                 void *opaque)
4350 {
4351         struct i40e_pf *pf;
4352         unsigned long num;
4353         char *end;
4354
4355         pf = (struct i40e_pf *)opaque;
4356         RTE_SET_USED(key);
4357
4358         errno = 0;
4359         num = strtoul(value, &end, 0);
4360         if (errno != 0 || end == value || *end != 0) {
4361                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4362                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4363                 return -(EINVAL);
4364         }
4365
4366         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4367                 pf->vf_nb_qp_max = (uint16_t)num;
4368         else
4369                 /* here return 0 to make next valid same argument work */
4370                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4371                             "power of 2 and equal or less than 16 !, Now it is "
4372                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4373
4374         return 0;
4375 }
4376
4377 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4378 {
4379         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4380         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4381         struct rte_kvargs *kvlist;
4382
4383         /* set default queue number per VF as 4 */
4384         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4385
4386         if (dev->device->devargs == NULL)
4387                 return 0;
4388
4389         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4390         if (kvlist == NULL)
4391                 return -(EINVAL);
4392
4393         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4394                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4395                             "the first invalid or last valid one is used !",
4396                             QUEUE_NUM_PER_VF_ARG);
4397
4398         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4399                            i40e_pf_parse_vf_queue_number_handler, pf);
4400
4401         rte_kvargs_free(kvlist);
4402
4403         return 0;
4404 }
4405
4406 static int
4407 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4408 {
4409         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4410         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4411         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4412         uint16_t qp_count = 0, vsi_count = 0;
4413
4414         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4415                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4416                 return -EINVAL;
4417         }
4418
4419         i40e_pf_config_vf_rxq_number(dev);
4420
4421         /* Add the parameter init for LFC */
4422         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4423         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4424         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4425
4426         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4427         pf->max_num_vsi = hw->func_caps.num_vsis;
4428         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4429         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4430
4431         /* FDir queue/VSI allocation */
4432         pf->fdir_qp_offset = 0;
4433         if (hw->func_caps.fd) {
4434                 pf->flags |= I40E_FLAG_FDIR;
4435                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4436         } else {
4437                 pf->fdir_nb_qps = 0;
4438         }
4439         qp_count += pf->fdir_nb_qps;
4440         vsi_count += 1;
4441
4442         /* LAN queue/VSI allocation */
4443         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4444         if (!hw->func_caps.rss) {
4445                 pf->lan_nb_qps = 1;
4446         } else {
4447                 pf->flags |= I40E_FLAG_RSS;
4448                 if (hw->mac.type == I40E_MAC_X722)
4449                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4450                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4451         }
4452         qp_count += pf->lan_nb_qps;
4453         vsi_count += 1;
4454
4455         /* VF queue/VSI allocation */
4456         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4457         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4458                 pf->flags |= I40E_FLAG_SRIOV;
4459                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4460                 pf->vf_num = pci_dev->max_vfs;
4461                 PMD_DRV_LOG(DEBUG,
4462                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4463                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4464         } else {
4465                 pf->vf_nb_qps = 0;
4466                 pf->vf_num = 0;
4467         }
4468         qp_count += pf->vf_nb_qps * pf->vf_num;
4469         vsi_count += pf->vf_num;
4470
4471         /* VMDq queue/VSI allocation */
4472         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4473         pf->vmdq_nb_qps = 0;
4474         pf->max_nb_vmdq_vsi = 0;
4475         if (hw->func_caps.vmdq) {
4476                 if (qp_count < hw->func_caps.num_tx_qp &&
4477                         vsi_count < hw->func_caps.num_vsis) {
4478                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4479                                 qp_count) / pf->vmdq_nb_qp_max;
4480
4481                         /* Limit the maximum number of VMDq vsi to the maximum
4482                          * ethdev can support
4483                          */
4484                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4485                                 hw->func_caps.num_vsis - vsi_count);
4486                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4487                                 ETH_64_POOLS);
4488                         if (pf->max_nb_vmdq_vsi) {
4489                                 pf->flags |= I40E_FLAG_VMDQ;
4490                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4491                                 PMD_DRV_LOG(DEBUG,
4492                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4493                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4494                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4495                         } else {
4496                                 PMD_DRV_LOG(INFO,
4497                                         "No enough queues left for VMDq");
4498                         }
4499                 } else {
4500                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4501                 }
4502         }
4503         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4504         vsi_count += pf->max_nb_vmdq_vsi;
4505
4506         if (hw->func_caps.dcb)
4507                 pf->flags |= I40E_FLAG_DCB;
4508
4509         if (qp_count > hw->func_caps.num_tx_qp) {
4510                 PMD_DRV_LOG(ERR,
4511                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4512                         qp_count, hw->func_caps.num_tx_qp);
4513                 return -EINVAL;
4514         }
4515         if (vsi_count > hw->func_caps.num_vsis) {
4516                 PMD_DRV_LOG(ERR,
4517                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4518                         vsi_count, hw->func_caps.num_vsis);
4519                 return -EINVAL;
4520         }
4521
4522         return 0;
4523 }
4524
4525 static int
4526 i40e_pf_get_switch_config(struct i40e_pf *pf)
4527 {
4528         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4529         struct i40e_aqc_get_switch_config_resp *switch_config;
4530         struct i40e_aqc_switch_config_element_resp *element;
4531         uint16_t start_seid = 0, num_reported;
4532         int ret;
4533
4534         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4535                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4536         if (!switch_config) {
4537                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4538                 return -ENOMEM;
4539         }
4540
4541         /* Get the switch configurations */
4542         ret = i40e_aq_get_switch_config(hw, switch_config,
4543                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4544         if (ret != I40E_SUCCESS) {
4545                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4546                 goto fail;
4547         }
4548         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4549         if (num_reported != 1) { /* The number should be 1 */
4550                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4551                 goto fail;
4552         }
4553
4554         /* Parse the switch configuration elements */
4555         element = &(switch_config->element[0]);
4556         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4557                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4558                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4559         } else
4560                 PMD_DRV_LOG(INFO, "Unknown element type");
4561
4562 fail:
4563         rte_free(switch_config);
4564
4565         return ret;
4566 }
4567
4568 static int
4569 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4570                         uint32_t num)
4571 {
4572         struct pool_entry *entry;
4573
4574         if (pool == NULL || num == 0)
4575                 return -EINVAL;
4576
4577         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4578         if (entry == NULL) {
4579                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4580                 return -ENOMEM;
4581         }
4582
4583         /* queue heap initialize */
4584         pool->num_free = num;
4585         pool->num_alloc = 0;
4586         pool->base = base;
4587         LIST_INIT(&pool->alloc_list);
4588         LIST_INIT(&pool->free_list);
4589
4590         /* Initialize element  */
4591         entry->base = 0;
4592         entry->len = num;
4593
4594         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4595         return 0;
4596 }
4597
4598 static void
4599 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4600 {
4601         struct pool_entry *entry, *next_entry;
4602
4603         if (pool == NULL)
4604                 return;
4605
4606         for (entry = LIST_FIRST(&pool->alloc_list);
4607                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4608                         entry = next_entry) {
4609                 LIST_REMOVE(entry, next);
4610                 rte_free(entry);
4611         }
4612
4613         for (entry = LIST_FIRST(&pool->free_list);
4614                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4615                         entry = next_entry) {
4616                 LIST_REMOVE(entry, next);
4617                 rte_free(entry);
4618         }
4619
4620         pool->num_free = 0;
4621         pool->num_alloc = 0;
4622         pool->base = 0;
4623         LIST_INIT(&pool->alloc_list);
4624         LIST_INIT(&pool->free_list);
4625 }
4626
4627 static int
4628 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4629                        uint32_t base)
4630 {
4631         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4632         uint32_t pool_offset;
4633         int insert;
4634
4635         if (pool == NULL) {
4636                 PMD_DRV_LOG(ERR, "Invalid parameter");
4637                 return -EINVAL;
4638         }
4639
4640         pool_offset = base - pool->base;
4641         /* Lookup in alloc list */
4642         LIST_FOREACH(entry, &pool->alloc_list, next) {
4643                 if (entry->base == pool_offset) {
4644                         valid_entry = entry;
4645                         LIST_REMOVE(entry, next);
4646                         break;
4647                 }
4648         }
4649
4650         /* Not find, return */
4651         if (valid_entry == NULL) {
4652                 PMD_DRV_LOG(ERR, "Failed to find entry");
4653                 return -EINVAL;
4654         }
4655
4656         /**
4657          * Found it, move it to free list  and try to merge.
4658          * In order to make merge easier, always sort it by qbase.
4659          * Find adjacent prev and last entries.
4660          */
4661         prev = next = NULL;
4662         LIST_FOREACH(entry, &pool->free_list, next) {
4663                 if (entry->base > valid_entry->base) {
4664                         next = entry;
4665                         break;
4666                 }
4667                 prev = entry;
4668         }
4669
4670         insert = 0;
4671         /* Try to merge with next one*/
4672         if (next != NULL) {
4673                 /* Merge with next one */
4674                 if (valid_entry->base + valid_entry->len == next->base) {
4675                         next->base = valid_entry->base;
4676                         next->len += valid_entry->len;
4677                         rte_free(valid_entry);
4678                         valid_entry = next;
4679                         insert = 1;
4680                 }
4681         }
4682
4683         if (prev != NULL) {
4684                 /* Merge with previous one */
4685                 if (prev->base + prev->len == valid_entry->base) {
4686                         prev->len += valid_entry->len;
4687                         /* If it merge with next one, remove next node */
4688                         if (insert == 1) {
4689                                 LIST_REMOVE(valid_entry, next);
4690                                 rte_free(valid_entry);
4691                         } else {
4692                                 rte_free(valid_entry);
4693                                 insert = 1;
4694                         }
4695                 }
4696         }
4697
4698         /* Not find any entry to merge, insert */
4699         if (insert == 0) {
4700                 if (prev != NULL)
4701                         LIST_INSERT_AFTER(prev, valid_entry, next);
4702                 else if (next != NULL)
4703                         LIST_INSERT_BEFORE(next, valid_entry, next);
4704                 else /* It's empty list, insert to head */
4705                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4706         }
4707
4708         pool->num_free += valid_entry->len;
4709         pool->num_alloc -= valid_entry->len;
4710
4711         return 0;
4712 }
4713
4714 static int
4715 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4716                        uint16_t num)
4717 {
4718         struct pool_entry *entry, *valid_entry;
4719
4720         if (pool == NULL || num == 0) {
4721                 PMD_DRV_LOG(ERR, "Invalid parameter");
4722                 return -EINVAL;
4723         }
4724
4725         if (pool->num_free < num) {
4726                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4727                             num, pool->num_free);
4728                 return -ENOMEM;
4729         }
4730
4731         valid_entry = NULL;
4732         /* Lookup  in free list and find most fit one */
4733         LIST_FOREACH(entry, &pool->free_list, next) {
4734                 if (entry->len >= num) {
4735                         /* Find best one */
4736                         if (entry->len == num) {
4737                                 valid_entry = entry;
4738                                 break;
4739                         }
4740                         if (valid_entry == NULL || valid_entry->len > entry->len)
4741                                 valid_entry = entry;
4742                 }
4743         }
4744
4745         /* Not find one to satisfy the request, return */
4746         if (valid_entry == NULL) {
4747                 PMD_DRV_LOG(ERR, "No valid entry found");
4748                 return -ENOMEM;
4749         }
4750         /**
4751          * The entry have equal queue number as requested,
4752          * remove it from alloc_list.
4753          */
4754         if (valid_entry->len == num) {
4755                 LIST_REMOVE(valid_entry, next);
4756         } else {
4757                 /**
4758                  * The entry have more numbers than requested,
4759                  * create a new entry for alloc_list and minus its
4760                  * queue base and number in free_list.
4761                  */
4762                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4763                 if (entry == NULL) {
4764                         PMD_DRV_LOG(ERR,
4765                                 "Failed to allocate memory for resource pool");
4766                         return -ENOMEM;
4767                 }
4768                 entry->base = valid_entry->base;
4769                 entry->len = num;
4770                 valid_entry->base += num;
4771                 valid_entry->len -= num;
4772                 valid_entry = entry;
4773         }
4774
4775         /* Insert it into alloc list, not sorted */
4776         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4777
4778         pool->num_free -= valid_entry->len;
4779         pool->num_alloc += valid_entry->len;
4780
4781         return valid_entry->base + pool->base;
4782 }
4783
4784 /**
4785  * bitmap_is_subset - Check whether src2 is subset of src1
4786  **/
4787 static inline int
4788 bitmap_is_subset(uint8_t src1, uint8_t src2)
4789 {
4790         return !((src1 ^ src2) & src2);
4791 }
4792
4793 static enum i40e_status_code
4794 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4795 {
4796         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4797
4798         /* If DCB is not supported, only default TC is supported */
4799         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4800                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4801                 return I40E_NOT_SUPPORTED;
4802         }
4803
4804         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4805                 PMD_DRV_LOG(ERR,
4806                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4807                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4808                 return I40E_NOT_SUPPORTED;
4809         }
4810         return I40E_SUCCESS;
4811 }
4812
4813 int
4814 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4815                                 struct i40e_vsi_vlan_pvid_info *info)
4816 {
4817         struct i40e_hw *hw;
4818         struct i40e_vsi_context ctxt;
4819         uint8_t vlan_flags = 0;
4820         int ret;
4821
4822         if (vsi == NULL || info == NULL) {
4823                 PMD_DRV_LOG(ERR, "invalid parameters");
4824                 return I40E_ERR_PARAM;
4825         }
4826
4827         if (info->on) {
4828                 vsi->info.pvid = info->config.pvid;
4829                 /**
4830                  * If insert pvid is enabled, only tagged pkts are
4831                  * allowed to be sent out.
4832                  */
4833                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4834                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4835         } else {
4836                 vsi->info.pvid = 0;
4837                 if (info->config.reject.tagged == 0)
4838                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4839
4840                 if (info->config.reject.untagged == 0)
4841                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4842         }
4843         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4844                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4845         vsi->info.port_vlan_flags |= vlan_flags;
4846         vsi->info.valid_sections =
4847                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4848         memset(&ctxt, 0, sizeof(ctxt));
4849         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4850         ctxt.seid = vsi->seid;
4851
4852         hw = I40E_VSI_TO_HW(vsi);
4853         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4854         if (ret != I40E_SUCCESS)
4855                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4856
4857         return ret;
4858 }
4859
4860 static int
4861 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4862 {
4863         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4864         int i, ret;
4865         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4866
4867         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4868         if (ret != I40E_SUCCESS)
4869                 return ret;
4870
4871         if (!vsi->seid) {
4872                 PMD_DRV_LOG(ERR, "seid not valid");
4873                 return -EINVAL;
4874         }
4875
4876         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4877         tc_bw_data.tc_valid_bits = enabled_tcmap;
4878         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4879                 tc_bw_data.tc_bw_credits[i] =
4880                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4881
4882         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4883         if (ret != I40E_SUCCESS) {
4884                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4885                 return ret;
4886         }
4887
4888         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4889                                         sizeof(vsi->info.qs_handle));
4890         return I40E_SUCCESS;
4891 }
4892
4893 static enum i40e_status_code
4894 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4895                                  struct i40e_aqc_vsi_properties_data *info,
4896                                  uint8_t enabled_tcmap)
4897 {
4898         enum i40e_status_code ret;
4899         int i, total_tc = 0;
4900         uint16_t qpnum_per_tc, bsf, qp_idx;
4901
4902         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4903         if (ret != I40E_SUCCESS)
4904                 return ret;
4905
4906         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4907                 if (enabled_tcmap & (1 << i))
4908                         total_tc++;
4909         if (total_tc == 0)
4910                 total_tc = 1;
4911         vsi->enabled_tc = enabled_tcmap;
4912
4913         /* Number of queues per enabled TC */
4914         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4915         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4916         bsf = rte_bsf32(qpnum_per_tc);
4917
4918         /* Adjust the queue number to actual queues that can be applied */
4919         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4920                 vsi->nb_qps = qpnum_per_tc * total_tc;
4921
4922         /**
4923          * Configure TC and queue mapping parameters, for enabled TC,
4924          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4925          * default queue will serve it.
4926          */
4927         qp_idx = 0;
4928         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4929                 if (vsi->enabled_tc & (1 << i)) {
4930                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4931                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4932                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4933                         qp_idx += qpnum_per_tc;
4934                 } else
4935                         info->tc_mapping[i] = 0;
4936         }
4937
4938         /* Associate queue number with VSI */
4939         if (vsi->type == I40E_VSI_SRIOV) {
4940                 info->mapping_flags |=
4941                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4942                 for (i = 0; i < vsi->nb_qps; i++)
4943                         info->queue_mapping[i] =
4944                                 rte_cpu_to_le_16(vsi->base_queue + i);
4945         } else {
4946                 info->mapping_flags |=
4947                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4948                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4949         }
4950         info->valid_sections |=
4951                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4952
4953         return I40E_SUCCESS;
4954 }
4955
4956 static int
4957 i40e_veb_release(struct i40e_veb *veb)
4958 {
4959         struct i40e_vsi *vsi;
4960         struct i40e_hw *hw;
4961
4962         if (veb == NULL)
4963                 return -EINVAL;
4964
4965         if (!TAILQ_EMPTY(&veb->head)) {
4966                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4967                 return -EACCES;
4968         }
4969         /* associate_vsi field is NULL for floating VEB */
4970         if (veb->associate_vsi != NULL) {
4971                 vsi = veb->associate_vsi;
4972                 hw = I40E_VSI_TO_HW(vsi);
4973
4974                 vsi->uplink_seid = veb->uplink_seid;
4975                 vsi->veb = NULL;
4976         } else {
4977                 veb->associate_pf->main_vsi->floating_veb = NULL;
4978                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4979         }
4980
4981         i40e_aq_delete_element(hw, veb->seid, NULL);
4982         rte_free(veb);
4983         return I40E_SUCCESS;
4984 }
4985
4986 /* Setup a veb */
4987 static struct i40e_veb *
4988 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4989 {
4990         struct i40e_veb *veb;
4991         int ret;
4992         struct i40e_hw *hw;
4993
4994         if (pf == NULL) {
4995                 PMD_DRV_LOG(ERR,
4996                             "veb setup failed, associated PF shouldn't null");
4997                 return NULL;
4998         }
4999         hw = I40E_PF_TO_HW(pf);
5000
5001         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5002         if (!veb) {
5003                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5004                 goto fail;
5005         }
5006
5007         veb->associate_vsi = vsi;
5008         veb->associate_pf = pf;
5009         TAILQ_INIT(&veb->head);
5010         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5011
5012         /* create floating veb if vsi is NULL */
5013         if (vsi != NULL) {
5014                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5015                                       I40E_DEFAULT_TCMAP, false,
5016                                       &veb->seid, false, NULL);
5017         } else {
5018                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5019                                       true, &veb->seid, false, NULL);
5020         }
5021
5022         if (ret != I40E_SUCCESS) {
5023                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5024                             hw->aq.asq_last_status);
5025                 goto fail;
5026         }
5027         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5028
5029         /* get statistics index */
5030         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5031                                 &veb->stats_idx, NULL, NULL, NULL);
5032         if (ret != I40E_SUCCESS) {
5033                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5034                             hw->aq.asq_last_status);
5035                 goto fail;
5036         }
5037         /* Get VEB bandwidth, to be implemented */
5038         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5039         if (vsi)
5040                 vsi->uplink_seid = veb->seid;
5041
5042         return veb;
5043 fail:
5044         rte_free(veb);
5045         return NULL;
5046 }
5047
5048 int
5049 i40e_vsi_release(struct i40e_vsi *vsi)
5050 {
5051         struct i40e_pf *pf;
5052         struct i40e_hw *hw;
5053         struct i40e_vsi_list *vsi_list;
5054         void *temp;
5055         int ret;
5056         struct i40e_mac_filter *f;
5057         uint16_t user_param;
5058
5059         if (!vsi)
5060                 return I40E_SUCCESS;
5061
5062         if (!vsi->adapter)
5063                 return -EFAULT;
5064
5065         user_param = vsi->user_param;
5066
5067         pf = I40E_VSI_TO_PF(vsi);
5068         hw = I40E_VSI_TO_HW(vsi);
5069
5070         /* VSI has child to attach, release child first */
5071         if (vsi->veb) {
5072                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5073                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5074                                 return -1;
5075                 }
5076                 i40e_veb_release(vsi->veb);
5077         }
5078
5079         if (vsi->floating_veb) {
5080                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5081                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5082                                 return -1;
5083                 }
5084         }
5085
5086         /* Remove all macvlan filters of the VSI */
5087         i40e_vsi_remove_all_macvlan_filter(vsi);
5088         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5089                 rte_free(f);
5090
5091         if (vsi->type != I40E_VSI_MAIN &&
5092             ((vsi->type != I40E_VSI_SRIOV) ||
5093             !pf->floating_veb_list[user_param])) {
5094                 /* Remove vsi from parent's sibling list */
5095                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5096                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5097                         return I40E_ERR_PARAM;
5098                 }
5099                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5100                                 &vsi->sib_vsi_list, list);
5101
5102                 /* Remove all switch element of the VSI */
5103                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5104                 if (ret != I40E_SUCCESS)
5105                         PMD_DRV_LOG(ERR, "Failed to delete element");
5106         }
5107
5108         if ((vsi->type == I40E_VSI_SRIOV) &&
5109             pf->floating_veb_list[user_param]) {
5110                 /* Remove vsi from parent's sibling list */
5111                 if (vsi->parent_vsi == NULL ||
5112                     vsi->parent_vsi->floating_veb == NULL) {
5113                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5114                         return I40E_ERR_PARAM;
5115                 }
5116                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5117                              &vsi->sib_vsi_list, list);
5118
5119                 /* Remove all switch element of the VSI */
5120                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5121                 if (ret != I40E_SUCCESS)
5122                         PMD_DRV_LOG(ERR, "Failed to delete element");
5123         }
5124
5125         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5126
5127         if (vsi->type != I40E_VSI_SRIOV)
5128                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5129         rte_free(vsi);
5130
5131         return I40E_SUCCESS;
5132 }
5133
5134 static int
5135 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5136 {
5137         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5138         struct i40e_aqc_remove_macvlan_element_data def_filter;
5139         struct i40e_mac_filter_info filter;
5140         int ret;
5141
5142         if (vsi->type != I40E_VSI_MAIN)
5143                 return I40E_ERR_CONFIG;
5144         memset(&def_filter, 0, sizeof(def_filter));
5145         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5146                                         ETH_ADDR_LEN);
5147         def_filter.vlan_tag = 0;
5148         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5149                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5150         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5151         if (ret != I40E_SUCCESS) {
5152                 struct i40e_mac_filter *f;
5153                 struct ether_addr *mac;
5154
5155                 PMD_DRV_LOG(DEBUG,
5156                             "Cannot remove the default macvlan filter");
5157                 /* It needs to add the permanent mac into mac list */
5158                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5159                 if (f == NULL) {
5160                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5161                         return I40E_ERR_NO_MEMORY;
5162                 }
5163                 mac = &f->mac_info.mac_addr;
5164                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5165                                 ETH_ADDR_LEN);
5166                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5167                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5168                 vsi->mac_num++;
5169
5170                 return ret;
5171         }
5172         rte_memcpy(&filter.mac_addr,
5173                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5174         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5175         return i40e_vsi_add_mac(vsi, &filter);
5176 }
5177
5178 /*
5179  * i40e_vsi_get_bw_config - Query VSI BW Information
5180  * @vsi: the VSI to be queried
5181  *
5182  * Returns 0 on success, negative value on failure
5183  */
5184 static enum i40e_status_code
5185 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5186 {
5187         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5188         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5189         struct i40e_hw *hw = &vsi->adapter->hw;
5190         i40e_status ret;
5191         int i;
5192         uint32_t bw_max;
5193
5194         memset(&bw_config, 0, sizeof(bw_config));
5195         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5196         if (ret != I40E_SUCCESS) {
5197                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5198                             hw->aq.asq_last_status);
5199                 return ret;
5200         }
5201
5202         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5203         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5204                                         &ets_sla_config, NULL);
5205         if (ret != I40E_SUCCESS) {
5206                 PMD_DRV_LOG(ERR,
5207                         "VSI failed to get TC bandwdith configuration %u",
5208                         hw->aq.asq_last_status);
5209                 return ret;
5210         }
5211
5212         /* store and print out BW info */
5213         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5214         vsi->bw_info.bw_max = bw_config.max_bw;
5215         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5216         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5217         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5218                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5219                      I40E_16_BIT_WIDTH);
5220         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5221                 vsi->bw_info.bw_ets_share_credits[i] =
5222                                 ets_sla_config.share_credits[i];
5223                 vsi->bw_info.bw_ets_credits[i] =
5224                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5225                 /* 4 bits per TC, 4th bit is reserved */
5226                 vsi->bw_info.bw_ets_max[i] =
5227                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5228                                   RTE_LEN2MASK(3, uint8_t));
5229                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5230                             vsi->bw_info.bw_ets_share_credits[i]);
5231                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5232                             vsi->bw_info.bw_ets_credits[i]);
5233                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5234                             vsi->bw_info.bw_ets_max[i]);
5235         }
5236
5237         return I40E_SUCCESS;
5238 }
5239
5240 /* i40e_enable_pf_lb
5241  * @pf: pointer to the pf structure
5242  *
5243  * allow loopback on pf
5244  */
5245 static inline void
5246 i40e_enable_pf_lb(struct i40e_pf *pf)
5247 {
5248         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5249         struct i40e_vsi_context ctxt;
5250         int ret;
5251
5252         /* Use the FW API if FW >= v5.0 */
5253         if (hw->aq.fw_maj_ver < 5) {
5254                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5255                 return;
5256         }
5257
5258         memset(&ctxt, 0, sizeof(ctxt));
5259         ctxt.seid = pf->main_vsi_seid;
5260         ctxt.pf_num = hw->pf_id;
5261         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5262         if (ret) {
5263                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5264                             ret, hw->aq.asq_last_status);
5265                 return;
5266         }
5267         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5268         ctxt.info.valid_sections =
5269                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5270         ctxt.info.switch_id |=
5271                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5272
5273         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5274         if (ret)
5275                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5276                             hw->aq.asq_last_status);
5277 }
5278
5279 /* Setup a VSI */
5280 struct i40e_vsi *
5281 i40e_vsi_setup(struct i40e_pf *pf,
5282                enum i40e_vsi_type type,
5283                struct i40e_vsi *uplink_vsi,
5284                uint16_t user_param)
5285 {
5286         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5287         struct i40e_vsi *vsi;
5288         struct i40e_mac_filter_info filter;
5289         int ret;
5290         struct i40e_vsi_context ctxt;
5291         struct ether_addr broadcast =
5292                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5293
5294         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5295             uplink_vsi == NULL) {
5296                 PMD_DRV_LOG(ERR,
5297                         "VSI setup failed, VSI link shouldn't be NULL");
5298                 return NULL;
5299         }
5300
5301         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5302                 PMD_DRV_LOG(ERR,
5303                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5304                 return NULL;
5305         }
5306
5307         /* two situations
5308          * 1.type is not MAIN and uplink vsi is not NULL
5309          * If uplink vsi didn't setup VEB, create one first under veb field
5310          * 2.type is SRIOV and the uplink is NULL
5311          * If floating VEB is NULL, create one veb under floating veb field
5312          */
5313
5314         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5315             uplink_vsi->veb == NULL) {
5316                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5317
5318                 if (uplink_vsi->veb == NULL) {
5319                         PMD_DRV_LOG(ERR, "VEB setup failed");
5320                         return NULL;
5321                 }
5322                 /* set ALLOWLOOPBACk on pf, when veb is created */
5323                 i40e_enable_pf_lb(pf);
5324         }
5325
5326         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5327             pf->main_vsi->floating_veb == NULL) {
5328                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5329
5330                 if (pf->main_vsi->floating_veb == NULL) {
5331                         PMD_DRV_LOG(ERR, "VEB setup failed");
5332                         return NULL;
5333                 }
5334         }
5335
5336         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5337         if (!vsi) {
5338                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5339                 return NULL;
5340         }
5341         TAILQ_INIT(&vsi->mac_list);
5342         vsi->type = type;
5343         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5344         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5345         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5346         vsi->user_param = user_param;
5347         vsi->vlan_anti_spoof_on = 0;
5348         vsi->vlan_filter_on = 0;
5349         /* Allocate queues */
5350         switch (vsi->type) {
5351         case I40E_VSI_MAIN  :
5352                 vsi->nb_qps = pf->lan_nb_qps;
5353                 break;
5354         case I40E_VSI_SRIOV :
5355                 vsi->nb_qps = pf->vf_nb_qps;
5356                 break;
5357         case I40E_VSI_VMDQ2:
5358                 vsi->nb_qps = pf->vmdq_nb_qps;
5359                 break;
5360         case I40E_VSI_FDIR:
5361                 vsi->nb_qps = pf->fdir_nb_qps;
5362                 break;
5363         default:
5364                 goto fail_mem;
5365         }
5366         /*
5367          * The filter status descriptor is reported in rx queue 0,
5368          * while the tx queue for fdir filter programming has no
5369          * such constraints, can be non-zero queues.
5370          * To simplify it, choose FDIR vsi use queue 0 pair.
5371          * To make sure it will use queue 0 pair, queue allocation
5372          * need be done before this function is called
5373          */
5374         if (type != I40E_VSI_FDIR) {
5375                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5376                         if (ret < 0) {
5377                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5378                                                 vsi->seid, ret);
5379                                 goto fail_mem;
5380                         }
5381                         vsi->base_queue = ret;
5382         } else
5383                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5384
5385         /* VF has MSIX interrupt in VF range, don't allocate here */
5386         if (type == I40E_VSI_MAIN) {
5387                 if (pf->support_multi_driver) {
5388                         /* If support multi-driver, need to use INT0 instead of
5389                          * allocating from msix pool. The Msix pool is init from
5390                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5391                          * to 1 without calling i40e_res_pool_alloc.
5392                          */
5393                         vsi->msix_intr = 0;
5394                         vsi->nb_msix = 1;
5395                 } else {
5396                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5397                                                   RTE_MIN(vsi->nb_qps,
5398                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5399                         if (ret < 0) {
5400                                 PMD_DRV_LOG(ERR,
5401                                             "VSI MAIN %d get heap failed %d",
5402                                             vsi->seid, ret);
5403                                 goto fail_queue_alloc;
5404                         }
5405                         vsi->msix_intr = ret;
5406                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5407                                                RTE_MAX_RXTX_INTR_VEC_ID);
5408                 }
5409         } else if (type != I40E_VSI_SRIOV) {
5410                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5411                 if (ret < 0) {
5412                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5413                         goto fail_queue_alloc;
5414                 }
5415                 vsi->msix_intr = ret;
5416                 vsi->nb_msix = 1;
5417         } else {
5418                 vsi->msix_intr = 0;
5419                 vsi->nb_msix = 0;
5420         }
5421
5422         /* Add VSI */
5423         if (type == I40E_VSI_MAIN) {
5424                 /* For main VSI, no need to add since it's default one */
5425                 vsi->uplink_seid = pf->mac_seid;
5426                 vsi->seid = pf->main_vsi_seid;
5427                 /* Bind queues with specific MSIX interrupt */
5428                 /**
5429                  * Needs 2 interrupt at least, one for misc cause which will
5430                  * enabled from OS side, Another for queues binding the
5431                  * interrupt from device side only.
5432                  */
5433
5434                 /* Get default VSI parameters from hardware */
5435                 memset(&ctxt, 0, sizeof(ctxt));
5436                 ctxt.seid = vsi->seid;
5437                 ctxt.pf_num = hw->pf_id;
5438                 ctxt.uplink_seid = vsi->uplink_seid;
5439                 ctxt.vf_num = 0;
5440                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5441                 if (ret != I40E_SUCCESS) {
5442                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5443                         goto fail_msix_alloc;
5444                 }
5445                 rte_memcpy(&vsi->info, &ctxt.info,
5446                         sizeof(struct i40e_aqc_vsi_properties_data));
5447                 vsi->vsi_id = ctxt.vsi_number;
5448                 vsi->info.valid_sections = 0;
5449
5450                 /* Configure tc, enabled TC0 only */
5451                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5452                         I40E_SUCCESS) {
5453                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5454                         goto fail_msix_alloc;
5455                 }
5456
5457                 /* TC, queue mapping */
5458                 memset(&ctxt, 0, sizeof(ctxt));
5459                 vsi->info.valid_sections |=
5460                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5461                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5462                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5463                 rte_memcpy(&ctxt.info, &vsi->info,
5464                         sizeof(struct i40e_aqc_vsi_properties_data));
5465                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5466                                                 I40E_DEFAULT_TCMAP);
5467                 if (ret != I40E_SUCCESS) {
5468                         PMD_DRV_LOG(ERR,
5469                                 "Failed to configure TC queue mapping");
5470                         goto fail_msix_alloc;
5471                 }
5472                 ctxt.seid = vsi->seid;
5473                 ctxt.pf_num = hw->pf_id;
5474                 ctxt.uplink_seid = vsi->uplink_seid;
5475                 ctxt.vf_num = 0;
5476
5477                 /* Update VSI parameters */
5478                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5479                 if (ret != I40E_SUCCESS) {
5480                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5481                         goto fail_msix_alloc;
5482                 }
5483
5484                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5485                                                 sizeof(vsi->info.tc_mapping));
5486                 rte_memcpy(&vsi->info.queue_mapping,
5487                                 &ctxt.info.queue_mapping,
5488                         sizeof(vsi->info.queue_mapping));
5489                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5490                 vsi->info.valid_sections = 0;
5491
5492                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5493                                 ETH_ADDR_LEN);
5494
5495                 /**
5496                  * Updating default filter settings are necessary to prevent
5497                  * reception of tagged packets.
5498                  * Some old firmware configurations load a default macvlan
5499                  * filter which accepts both tagged and untagged packets.
5500                  * The updating is to use a normal filter instead if needed.
5501                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5502                  * The firmware with correct configurations load the default
5503                  * macvlan filter which is expected and cannot be removed.
5504                  */
5505                 i40e_update_default_filter_setting(vsi);
5506                 i40e_config_qinq(hw, vsi);
5507         } else if (type == I40E_VSI_SRIOV) {
5508                 memset(&ctxt, 0, sizeof(ctxt));
5509                 /**
5510                  * For other VSI, the uplink_seid equals to uplink VSI's
5511                  * uplink_seid since they share same VEB
5512                  */
5513                 if (uplink_vsi == NULL)
5514                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5515                 else
5516                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5517                 ctxt.pf_num = hw->pf_id;
5518                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5519                 ctxt.uplink_seid = vsi->uplink_seid;
5520                 ctxt.connection_type = 0x1;
5521                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5522
5523                 /* Use the VEB configuration if FW >= v5.0 */
5524                 if (hw->aq.fw_maj_ver >= 5) {
5525                         /* Configure switch ID */
5526                         ctxt.info.valid_sections |=
5527                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5528                         ctxt.info.switch_id =
5529                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5530                 }
5531
5532                 /* Configure port/vlan */
5533                 ctxt.info.valid_sections |=
5534                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5535                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5536                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5537                                                 hw->func_caps.enabled_tcmap);
5538                 if (ret != I40E_SUCCESS) {
5539                         PMD_DRV_LOG(ERR,
5540                                 "Failed to configure TC queue mapping");
5541                         goto fail_msix_alloc;
5542                 }
5543
5544                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5545                 ctxt.info.valid_sections |=
5546                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5547                 /**
5548                  * Since VSI is not created yet, only configure parameter,
5549                  * will add vsi below.
5550                  */
5551
5552                 i40e_config_qinq(hw, vsi);
5553         } else if (type == I40E_VSI_VMDQ2) {
5554                 memset(&ctxt, 0, sizeof(ctxt));
5555                 /*
5556                  * For other VSI, the uplink_seid equals to uplink VSI's
5557                  * uplink_seid since they share same VEB
5558                  */
5559                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5560                 ctxt.pf_num = hw->pf_id;
5561                 ctxt.vf_num = 0;
5562                 ctxt.uplink_seid = vsi->uplink_seid;
5563                 ctxt.connection_type = 0x1;
5564                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5565
5566                 ctxt.info.valid_sections |=
5567                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5568                 /* user_param carries flag to enable loop back */
5569                 if (user_param) {
5570                         ctxt.info.switch_id =
5571                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5572                         ctxt.info.switch_id |=
5573                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5574                 }
5575
5576                 /* Configure port/vlan */
5577                 ctxt.info.valid_sections |=
5578                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5579                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5580                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5581                                                 I40E_DEFAULT_TCMAP);
5582                 if (ret != I40E_SUCCESS) {
5583                         PMD_DRV_LOG(ERR,
5584                                 "Failed to configure TC queue mapping");
5585                         goto fail_msix_alloc;
5586                 }
5587                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5588                 ctxt.info.valid_sections |=
5589                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5590         } else if (type == I40E_VSI_FDIR) {
5591                 memset(&ctxt, 0, sizeof(ctxt));
5592                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5593                 ctxt.pf_num = hw->pf_id;
5594                 ctxt.vf_num = 0;
5595                 ctxt.uplink_seid = vsi->uplink_seid;
5596                 ctxt.connection_type = 0x1;     /* regular data port */
5597                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5598                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5599                                                 I40E_DEFAULT_TCMAP);
5600                 if (ret != I40E_SUCCESS) {
5601                         PMD_DRV_LOG(ERR,
5602                                 "Failed to configure TC queue mapping.");
5603                         goto fail_msix_alloc;
5604                 }
5605                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5606                 ctxt.info.valid_sections |=
5607                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5608         } else {
5609                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5610                 goto fail_msix_alloc;
5611         }
5612
5613         if (vsi->type != I40E_VSI_MAIN) {
5614                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5615                 if (ret != I40E_SUCCESS) {
5616                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5617                                     hw->aq.asq_last_status);
5618                         goto fail_msix_alloc;
5619                 }
5620                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5621                 vsi->info.valid_sections = 0;
5622                 vsi->seid = ctxt.seid;
5623                 vsi->vsi_id = ctxt.vsi_number;
5624                 vsi->sib_vsi_list.vsi = vsi;
5625                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5626                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5627                                           &vsi->sib_vsi_list, list);
5628                 } else {
5629                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5630                                           &vsi->sib_vsi_list, list);
5631                 }
5632         }
5633
5634         /* MAC/VLAN configuration */
5635         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5636         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5637
5638         ret = i40e_vsi_add_mac(vsi, &filter);
5639         if (ret != I40E_SUCCESS) {
5640                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5641                 goto fail_msix_alloc;
5642         }
5643
5644         /* Get VSI BW information */
5645         i40e_vsi_get_bw_config(vsi);
5646         return vsi;
5647 fail_msix_alloc:
5648         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5649 fail_queue_alloc:
5650         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5651 fail_mem:
5652         rte_free(vsi);
5653         return NULL;
5654 }
5655
5656 /* Configure vlan filter on or off */
5657 int
5658 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5659 {
5660         int i, num;
5661         struct i40e_mac_filter *f;
5662         void *temp;
5663         struct i40e_mac_filter_info *mac_filter;
5664         enum rte_mac_filter_type desired_filter;
5665         int ret = I40E_SUCCESS;
5666
5667         if (on) {
5668                 /* Filter to match MAC and VLAN */
5669                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5670         } else {
5671                 /* Filter to match only MAC */
5672                 desired_filter = RTE_MAC_PERFECT_MATCH;
5673         }
5674
5675         num = vsi->mac_num;
5676
5677         mac_filter = rte_zmalloc("mac_filter_info_data",
5678                                  num * sizeof(*mac_filter), 0);
5679         if (mac_filter == NULL) {
5680                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5681                 return I40E_ERR_NO_MEMORY;
5682         }
5683
5684         i = 0;
5685
5686         /* Remove all existing mac */
5687         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5688                 mac_filter[i] = f->mac_info;
5689                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5690                 if (ret) {
5691                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5692                                     on ? "enable" : "disable");
5693                         goto DONE;
5694                 }
5695                 i++;
5696         }
5697
5698         /* Override with new filter */
5699         for (i = 0; i < num; i++) {
5700                 mac_filter[i].filter_type = desired_filter;
5701                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5702                 if (ret) {
5703                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5704                                     on ? "enable" : "disable");
5705                         goto DONE;
5706                 }
5707         }
5708
5709 DONE:
5710         rte_free(mac_filter);
5711         return ret;
5712 }
5713
5714 /* Configure vlan stripping on or off */
5715 int
5716 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5717 {
5718         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5719         struct i40e_vsi_context ctxt;
5720         uint8_t vlan_flags;
5721         int ret = I40E_SUCCESS;
5722
5723         /* Check if it has been already on or off */
5724         if (vsi->info.valid_sections &
5725                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5726                 if (on) {
5727                         if ((vsi->info.port_vlan_flags &
5728                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5729                                 return 0; /* already on */
5730                 } else {
5731                         if ((vsi->info.port_vlan_flags &
5732                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5733                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5734                                 return 0; /* already off */
5735                 }
5736         }
5737
5738         if (on)
5739                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5740         else
5741                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5742         vsi->info.valid_sections =
5743                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5744         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5745         vsi->info.port_vlan_flags |= vlan_flags;
5746         ctxt.seid = vsi->seid;
5747         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5748         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5749         if (ret)
5750                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5751                             on ? "enable" : "disable");
5752
5753         return ret;
5754 }
5755
5756 static int
5757 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5758 {
5759         struct rte_eth_dev_data *data = dev->data;
5760         int ret;
5761         int mask = 0;
5762
5763         /* Apply vlan offload setting */
5764         mask = ETH_VLAN_STRIP_MASK |
5765                ETH_VLAN_FILTER_MASK |
5766                ETH_VLAN_EXTEND_MASK;
5767         ret = i40e_vlan_offload_set(dev, mask);
5768         if (ret) {
5769                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5770                 return ret;
5771         }
5772
5773         /* Apply pvid setting */
5774         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5775                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5776         if (ret)
5777                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5778
5779         return ret;
5780 }
5781
5782 static int
5783 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5784 {
5785         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5786
5787         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5788 }
5789
5790 static int
5791 i40e_update_flow_control(struct i40e_hw *hw)
5792 {
5793 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5794         struct i40e_link_status link_status;
5795         uint32_t rxfc = 0, txfc = 0, reg;
5796         uint8_t an_info;
5797         int ret;
5798
5799         memset(&link_status, 0, sizeof(link_status));
5800         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5801         if (ret != I40E_SUCCESS) {
5802                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5803                 goto write_reg; /* Disable flow control */
5804         }
5805
5806         an_info = hw->phy.link_info.an_info;
5807         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5808                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5809                 ret = I40E_ERR_NOT_READY;
5810                 goto write_reg; /* Disable flow control */
5811         }
5812         /**
5813          * If link auto negotiation is enabled, flow control needs to
5814          * be configured according to it
5815          */
5816         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5817         case I40E_LINK_PAUSE_RXTX:
5818                 rxfc = 1;
5819                 txfc = 1;
5820                 hw->fc.current_mode = I40E_FC_FULL;
5821                 break;
5822         case I40E_AQ_LINK_PAUSE_RX:
5823                 rxfc = 1;
5824                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5825                 break;
5826         case I40E_AQ_LINK_PAUSE_TX:
5827                 txfc = 1;
5828                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5829                 break;
5830         default:
5831                 hw->fc.current_mode = I40E_FC_NONE;
5832                 break;
5833         }
5834
5835 write_reg:
5836         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5837                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5838         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5839         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5840         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5841         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5842
5843         return ret;
5844 }
5845
5846 /* PF setup */
5847 static int
5848 i40e_pf_setup(struct i40e_pf *pf)
5849 {
5850         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5851         struct i40e_filter_control_settings settings;
5852         struct i40e_vsi *vsi;
5853         int ret;
5854
5855         /* Clear all stats counters */
5856         pf->offset_loaded = FALSE;
5857         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5858         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5859         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5860         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5861
5862         ret = i40e_pf_get_switch_config(pf);
5863         if (ret != I40E_SUCCESS) {
5864                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5865                 return ret;
5866         }
5867
5868         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
5869         if (ret)
5870                 PMD_INIT_LOG(WARNING,
5871                         "failed to allocate switch domain for device %d", ret);
5872
5873         if (pf->flags & I40E_FLAG_FDIR) {
5874                 /* make queue allocated first, let FDIR use queue pair 0*/
5875                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5876                 if (ret != I40E_FDIR_QUEUE_ID) {
5877                         PMD_DRV_LOG(ERR,
5878                                 "queue allocation fails for FDIR: ret =%d",
5879                                 ret);
5880                         pf->flags &= ~I40E_FLAG_FDIR;
5881                 }
5882         }
5883         /*  main VSI setup */
5884         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5885         if (!vsi) {
5886                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5887                 return I40E_ERR_NOT_READY;
5888         }
5889         pf->main_vsi = vsi;
5890
5891         /* Configure filter control */
5892         memset(&settings, 0, sizeof(settings));
5893         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5894                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5895         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5896                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5897         else {
5898                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5899                         hw->func_caps.rss_table_size);
5900                 return I40E_ERR_PARAM;
5901         }
5902         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5903                 hw->func_caps.rss_table_size);
5904         pf->hash_lut_size = hw->func_caps.rss_table_size;
5905
5906         /* Enable ethtype and macvlan filters */
5907         settings.enable_ethtype = TRUE;
5908         settings.enable_macvlan = TRUE;
5909         ret = i40e_set_filter_control(hw, &settings);
5910         if (ret)
5911                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5912                                                                 ret);
5913
5914         /* Update flow control according to the auto negotiation */
5915         i40e_update_flow_control(hw);
5916
5917         return I40E_SUCCESS;
5918 }
5919
5920 int
5921 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5922 {
5923         uint32_t reg;
5924         uint16_t j;
5925
5926         /**
5927          * Set or clear TX Queue Disable flags,
5928          * which is required by hardware.
5929          */
5930         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5931         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5932
5933         /* Wait until the request is finished */
5934         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5935                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5936                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5937                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5938                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5939                                                         & 0x1))) {
5940                         break;
5941                 }
5942         }
5943         if (on) {
5944                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5945                         return I40E_SUCCESS; /* already on, skip next steps */
5946
5947                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5948                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5949         } else {
5950                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5951                         return I40E_SUCCESS; /* already off, skip next steps */
5952                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5953         }
5954         /* Write the register */
5955         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5956         /* Check the result */
5957         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5958                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5959                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5960                 if (on) {
5961                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5962                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5963                                 break;
5964                 } else {
5965                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5966                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5967                                 break;
5968                 }
5969         }
5970         /* Check if it is timeout */
5971         if (j >= I40E_CHK_Q_ENA_COUNT) {
5972                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5973                             (on ? "enable" : "disable"), q_idx);
5974                 return I40E_ERR_TIMEOUT;
5975         }
5976
5977         return I40E_SUCCESS;
5978 }
5979
5980 /* Swith on or off the tx queues */
5981 static int
5982 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5983 {
5984         struct rte_eth_dev_data *dev_data = pf->dev_data;
5985         struct i40e_tx_queue *txq;
5986         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5987         uint16_t i;
5988         int ret;
5989
5990         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5991                 txq = dev_data->tx_queues[i];
5992                 /* Don't operate the queue if not configured or
5993                  * if starting only per queue */
5994                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5995                         continue;
5996                 if (on)
5997                         ret = i40e_dev_tx_queue_start(dev, i);
5998                 else
5999                         ret = i40e_dev_tx_queue_stop(dev, i);
6000                 if ( ret != I40E_SUCCESS)
6001                         return ret;
6002         }
6003
6004         return I40E_SUCCESS;
6005 }
6006
6007 int
6008 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6009 {
6010         uint32_t reg;
6011         uint16_t j;
6012
6013         /* Wait until the request is finished */
6014         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6015                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6016                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6017                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6018                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6019                         break;
6020         }
6021
6022         if (on) {
6023                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6024                         return I40E_SUCCESS; /* Already on, skip next steps */
6025                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6026         } else {
6027                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6028                         return I40E_SUCCESS; /* Already off, skip next steps */
6029                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6030         }
6031
6032         /* Write the register */
6033         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6034         /* Check the result */
6035         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6036                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6037                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6038                 if (on) {
6039                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6040                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6041                                 break;
6042                 } else {
6043                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6044                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6045                                 break;
6046                 }
6047         }
6048
6049         /* Check if it is timeout */
6050         if (j >= I40E_CHK_Q_ENA_COUNT) {
6051                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6052                             (on ? "enable" : "disable"), q_idx);
6053                 return I40E_ERR_TIMEOUT;
6054         }
6055
6056         return I40E_SUCCESS;
6057 }
6058 /* Switch on or off the rx queues */
6059 static int
6060 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6061 {
6062         struct rte_eth_dev_data *dev_data = pf->dev_data;
6063         struct i40e_rx_queue *rxq;
6064         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6065         uint16_t i;
6066         int ret;
6067
6068         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6069                 rxq = dev_data->rx_queues[i];
6070                 /* Don't operate the queue if not configured or
6071                  * if starting only per queue */
6072                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6073                         continue;
6074                 if (on)
6075                         ret = i40e_dev_rx_queue_start(dev, i);
6076                 else
6077                         ret = i40e_dev_rx_queue_stop(dev, i);
6078                 if (ret != I40E_SUCCESS)
6079                         return ret;
6080         }
6081
6082         return I40E_SUCCESS;
6083 }
6084
6085 /* Switch on or off all the rx/tx queues */
6086 int
6087 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6088 {
6089         int ret;
6090
6091         if (on) {
6092                 /* enable rx queues before enabling tx queues */
6093                 ret = i40e_dev_switch_rx_queues(pf, on);
6094                 if (ret) {
6095                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6096                         return ret;
6097                 }
6098                 ret = i40e_dev_switch_tx_queues(pf, on);
6099         } else {
6100                 /* Stop tx queues before stopping rx queues */
6101                 ret = i40e_dev_switch_tx_queues(pf, on);
6102                 if (ret) {
6103                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6104                         return ret;
6105                 }
6106                 ret = i40e_dev_switch_rx_queues(pf, on);
6107         }
6108
6109         return ret;
6110 }
6111
6112 /* Initialize VSI for TX */
6113 static int
6114 i40e_dev_tx_init(struct i40e_pf *pf)
6115 {
6116         struct rte_eth_dev_data *data = pf->dev_data;
6117         uint16_t i;
6118         uint32_t ret = I40E_SUCCESS;
6119         struct i40e_tx_queue *txq;
6120
6121         for (i = 0; i < data->nb_tx_queues; i++) {
6122                 txq = data->tx_queues[i];
6123                 if (!txq || !txq->q_set)
6124                         continue;
6125                 ret = i40e_tx_queue_init(txq);
6126                 if (ret != I40E_SUCCESS)
6127                         break;
6128         }
6129         if (ret == I40E_SUCCESS)
6130                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6131                                      ->eth_dev);
6132
6133         return ret;
6134 }
6135
6136 /* Initialize VSI for RX */
6137 static int
6138 i40e_dev_rx_init(struct i40e_pf *pf)
6139 {
6140         struct rte_eth_dev_data *data = pf->dev_data;
6141         int ret = I40E_SUCCESS;
6142         uint16_t i;
6143         struct i40e_rx_queue *rxq;
6144
6145         i40e_pf_config_mq_rx(pf);
6146         for (i = 0; i < data->nb_rx_queues; i++) {
6147                 rxq = data->rx_queues[i];
6148                 if (!rxq || !rxq->q_set)
6149                         continue;
6150
6151                 ret = i40e_rx_queue_init(rxq);
6152                 if (ret != I40E_SUCCESS) {
6153                         PMD_DRV_LOG(ERR,
6154                                 "Failed to do RX queue initialization");
6155                         break;
6156                 }
6157         }
6158         if (ret == I40E_SUCCESS)
6159                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6160                                      ->eth_dev);
6161
6162         return ret;
6163 }
6164
6165 static int
6166 i40e_dev_rxtx_init(struct i40e_pf *pf)
6167 {
6168         int err;
6169
6170         err = i40e_dev_tx_init(pf);
6171         if (err) {
6172                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6173                 return err;
6174         }
6175         err = i40e_dev_rx_init(pf);
6176         if (err) {
6177                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6178                 return err;
6179         }
6180
6181         return err;
6182 }
6183
6184 static int
6185 i40e_vmdq_setup(struct rte_eth_dev *dev)
6186 {
6187         struct rte_eth_conf *conf = &dev->data->dev_conf;
6188         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6189         int i, err, conf_vsis, j, loop;
6190         struct i40e_vsi *vsi;
6191         struct i40e_vmdq_info *vmdq_info;
6192         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6193         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6194
6195         /*
6196          * Disable interrupt to avoid message from VF. Furthermore, it will
6197          * avoid race condition in VSI creation/destroy.
6198          */
6199         i40e_pf_disable_irq0(hw);
6200
6201         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6202                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6203                 return -ENOTSUP;
6204         }
6205
6206         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6207         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6208                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6209                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6210                         pf->max_nb_vmdq_vsi);
6211                 return -ENOTSUP;
6212         }
6213
6214         if (pf->vmdq != NULL) {
6215                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6216                 return 0;
6217         }
6218
6219         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6220                                 sizeof(*vmdq_info) * conf_vsis, 0);
6221
6222         if (pf->vmdq == NULL) {
6223                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6224                 return -ENOMEM;
6225         }
6226
6227         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6228
6229         /* Create VMDQ VSI */
6230         for (i = 0; i < conf_vsis; i++) {
6231                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6232                                 vmdq_conf->enable_loop_back);
6233                 if (vsi == NULL) {
6234                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6235                         err = -1;
6236                         goto err_vsi_setup;
6237                 }
6238                 vmdq_info = &pf->vmdq[i];
6239                 vmdq_info->pf = pf;
6240                 vmdq_info->vsi = vsi;
6241         }
6242         pf->nb_cfg_vmdq_vsi = conf_vsis;
6243
6244         /* Configure Vlan */
6245         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6246         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6247                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6248                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6249                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6250                                         vmdq_conf->pool_map[i].vlan_id, j);
6251
6252                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6253                                                 vmdq_conf->pool_map[i].vlan_id);
6254                                 if (err) {
6255                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6256                                         err = -1;
6257                                         goto err_vsi_setup;
6258                                 }
6259                         }
6260                 }
6261         }
6262
6263         i40e_pf_enable_irq0(hw);
6264
6265         return 0;
6266
6267 err_vsi_setup:
6268         for (i = 0; i < conf_vsis; i++)
6269                 if (pf->vmdq[i].vsi == NULL)
6270                         break;
6271                 else
6272                         i40e_vsi_release(pf->vmdq[i].vsi);
6273
6274         rte_free(pf->vmdq);
6275         pf->vmdq = NULL;
6276         i40e_pf_enable_irq0(hw);
6277         return err;
6278 }
6279
6280 static void
6281 i40e_stat_update_32(struct i40e_hw *hw,
6282                    uint32_t reg,
6283                    bool offset_loaded,
6284                    uint64_t *offset,
6285                    uint64_t *stat)
6286 {
6287         uint64_t new_data;
6288
6289         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6290         if (!offset_loaded)
6291                 *offset = new_data;
6292
6293         if (new_data >= *offset)
6294                 *stat = (uint64_t)(new_data - *offset);
6295         else
6296                 *stat = (uint64_t)((new_data +
6297                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6298 }
6299
6300 static void
6301 i40e_stat_update_48(struct i40e_hw *hw,
6302                    uint32_t hireg,
6303                    uint32_t loreg,
6304                    bool offset_loaded,
6305                    uint64_t *offset,
6306                    uint64_t *stat)
6307 {
6308         uint64_t new_data;
6309
6310         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6311         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6312                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6313
6314         if (!offset_loaded)
6315                 *offset = new_data;
6316
6317         if (new_data >= *offset)
6318                 *stat = new_data - *offset;
6319         else
6320                 *stat = (uint64_t)((new_data +
6321                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6322
6323         *stat &= I40E_48_BIT_MASK;
6324 }
6325
6326 /* Disable IRQ0 */
6327 void
6328 i40e_pf_disable_irq0(struct i40e_hw *hw)
6329 {
6330         /* Disable all interrupt types */
6331         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6332                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6333         I40E_WRITE_FLUSH(hw);
6334 }
6335
6336 /* Enable IRQ0 */
6337 void
6338 i40e_pf_enable_irq0(struct i40e_hw *hw)
6339 {
6340         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6341                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6342                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6343                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6344         I40E_WRITE_FLUSH(hw);
6345 }
6346
6347 static void
6348 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6349 {
6350         /* read pending request and disable first */
6351         i40e_pf_disable_irq0(hw);
6352         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6353         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6354                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6355
6356         if (no_queue)
6357                 /* Link no queues with irq0 */
6358                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6359                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6360 }
6361
6362 static void
6363 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6364 {
6365         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6366         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6367         int i;
6368         uint16_t abs_vf_id;
6369         uint32_t index, offset, val;
6370
6371         if (!pf->vfs)
6372                 return;
6373         /**
6374          * Try to find which VF trigger a reset, use absolute VF id to access
6375          * since the reg is global register.
6376          */
6377         for (i = 0; i < pf->vf_num; i++) {
6378                 abs_vf_id = hw->func_caps.vf_base_id + i;
6379                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6380                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6381                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6382                 /* VFR event occurred */
6383                 if (val & (0x1 << offset)) {
6384                         int ret;
6385
6386                         /* Clear the event first */
6387                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6388                                                         (0x1 << offset));
6389                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6390                         /**
6391                          * Only notify a VF reset event occurred,
6392                          * don't trigger another SW reset
6393                          */
6394                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6395                         if (ret != I40E_SUCCESS)
6396                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6397                 }
6398         }
6399 }
6400
6401 static void
6402 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6403 {
6404         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6405         int i;
6406
6407         for (i = 0; i < pf->vf_num; i++)
6408                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6409 }
6410
6411 static void
6412 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6413 {
6414         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6415         struct i40e_arq_event_info info;
6416         uint16_t pending, opcode;
6417         int ret;
6418
6419         info.buf_len = I40E_AQ_BUF_SZ;
6420         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6421         if (!info.msg_buf) {
6422                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6423                 return;
6424         }
6425
6426         pending = 1;
6427         while (pending) {
6428                 ret = i40e_clean_arq_element(hw, &info, &pending);
6429
6430                 if (ret != I40E_SUCCESS) {
6431                         PMD_DRV_LOG(INFO,
6432                                 "Failed to read msg from AdminQ, aq_err: %u",
6433                                 hw->aq.asq_last_status);
6434                         break;
6435                 }
6436                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6437
6438                 switch (opcode) {
6439                 case i40e_aqc_opc_send_msg_to_pf:
6440                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6441                         i40e_pf_host_handle_vf_msg(dev,
6442                                         rte_le_to_cpu_16(info.desc.retval),
6443                                         rte_le_to_cpu_32(info.desc.cookie_high),
6444                                         rte_le_to_cpu_32(info.desc.cookie_low),
6445                                         info.msg_buf,
6446                                         info.msg_len);
6447                         break;
6448                 case i40e_aqc_opc_get_link_status:
6449                         ret = i40e_dev_link_update(dev, 0);
6450                         if (!ret)
6451                                 _rte_eth_dev_callback_process(dev,
6452                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6453                         break;
6454                 default:
6455                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6456                                     opcode);
6457                         break;
6458                 }
6459         }
6460         rte_free(info.msg_buf);
6461 }
6462
6463 /**
6464  * Interrupt handler triggered by NIC  for handling
6465  * specific interrupt.
6466  *
6467  * @param handle
6468  *  Pointer to interrupt handle.
6469  * @param param
6470  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6471  *
6472  * @return
6473  *  void
6474  */
6475 static void
6476 i40e_dev_interrupt_handler(void *param)
6477 {
6478         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6479         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6480         uint32_t icr0;
6481
6482         /* Disable interrupt */
6483         i40e_pf_disable_irq0(hw);
6484
6485         /* read out interrupt causes */
6486         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6487
6488         /* No interrupt event indicated */
6489         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6490                 PMD_DRV_LOG(INFO, "No interrupt event");
6491                 goto done;
6492         }
6493         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6494                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6495         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6496                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6497         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6498                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6499         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6500                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6501         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6502                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6503         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6504                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6505         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6506                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6507
6508         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6509                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6510                 i40e_dev_handle_vfr_event(dev);
6511         }
6512         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6513                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6514                 i40e_dev_handle_aq_msg(dev);
6515         }
6516
6517 done:
6518         /* Enable interrupt */
6519         i40e_pf_enable_irq0(hw);
6520         rte_intr_enable(dev->intr_handle);
6521 }
6522
6523 int
6524 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6525                          struct i40e_macvlan_filter *filter,
6526                          int total)
6527 {
6528         int ele_num, ele_buff_size;
6529         int num, actual_num, i;
6530         uint16_t flags;
6531         int ret = I40E_SUCCESS;
6532         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6533         struct i40e_aqc_add_macvlan_element_data *req_list;
6534
6535         if (filter == NULL  || total == 0)
6536                 return I40E_ERR_PARAM;
6537         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6538         ele_buff_size = hw->aq.asq_buf_size;
6539
6540         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6541         if (req_list == NULL) {
6542                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6543                 return I40E_ERR_NO_MEMORY;
6544         }
6545
6546         num = 0;
6547         do {
6548                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6549                 memset(req_list, 0, ele_buff_size);
6550
6551                 for (i = 0; i < actual_num; i++) {
6552                         rte_memcpy(req_list[i].mac_addr,
6553                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6554                         req_list[i].vlan_tag =
6555                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6556
6557                         switch (filter[num + i].filter_type) {
6558                         case RTE_MAC_PERFECT_MATCH:
6559                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6560                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6561                                 break;
6562                         case RTE_MACVLAN_PERFECT_MATCH:
6563                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6564                                 break;
6565                         case RTE_MAC_HASH_MATCH:
6566                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6567                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6568                                 break;
6569                         case RTE_MACVLAN_HASH_MATCH:
6570                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6571                                 break;
6572                         default:
6573                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6574                                 ret = I40E_ERR_PARAM;
6575                                 goto DONE;
6576                         }
6577
6578                         req_list[i].queue_number = 0;
6579
6580                         req_list[i].flags = rte_cpu_to_le_16(flags);
6581                 }
6582
6583                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6584                                                 actual_num, NULL);
6585                 if (ret != I40E_SUCCESS) {
6586                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6587                         goto DONE;
6588                 }
6589                 num += actual_num;
6590         } while (num < total);
6591
6592 DONE:
6593         rte_free(req_list);
6594         return ret;
6595 }
6596
6597 int
6598 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6599                             struct i40e_macvlan_filter *filter,
6600                             int total)
6601 {
6602         int ele_num, ele_buff_size;
6603         int num, actual_num, i;
6604         uint16_t flags;
6605         int ret = I40E_SUCCESS;
6606         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6607         struct i40e_aqc_remove_macvlan_element_data *req_list;
6608
6609         if (filter == NULL  || total == 0)
6610                 return I40E_ERR_PARAM;
6611
6612         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6613         ele_buff_size = hw->aq.asq_buf_size;
6614
6615         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6616         if (req_list == NULL) {
6617                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6618                 return I40E_ERR_NO_MEMORY;
6619         }
6620
6621         num = 0;
6622         do {
6623                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6624                 memset(req_list, 0, ele_buff_size);
6625
6626                 for (i = 0; i < actual_num; i++) {
6627                         rte_memcpy(req_list[i].mac_addr,
6628                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6629                         req_list[i].vlan_tag =
6630                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6631
6632                         switch (filter[num + i].filter_type) {
6633                         case RTE_MAC_PERFECT_MATCH:
6634                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6635                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6636                                 break;
6637                         case RTE_MACVLAN_PERFECT_MATCH:
6638                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6639                                 break;
6640                         case RTE_MAC_HASH_MATCH:
6641                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6642                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6643                                 break;
6644                         case RTE_MACVLAN_HASH_MATCH:
6645                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6646                                 break;
6647                         default:
6648                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6649                                 ret = I40E_ERR_PARAM;
6650                                 goto DONE;
6651                         }
6652                         req_list[i].flags = rte_cpu_to_le_16(flags);
6653                 }
6654
6655                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6656                                                 actual_num, NULL);
6657                 if (ret != I40E_SUCCESS) {
6658                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6659                         goto DONE;
6660                 }
6661                 num += actual_num;
6662         } while (num < total);
6663
6664 DONE:
6665         rte_free(req_list);
6666         return ret;
6667 }
6668
6669 /* Find out specific MAC filter */
6670 static struct i40e_mac_filter *
6671 i40e_find_mac_filter(struct i40e_vsi *vsi,
6672                          struct ether_addr *macaddr)
6673 {
6674         struct i40e_mac_filter *f;
6675
6676         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6677                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6678                         return f;
6679         }
6680
6681         return NULL;
6682 }
6683
6684 static bool
6685 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6686                          uint16_t vlan_id)
6687 {
6688         uint32_t vid_idx, vid_bit;
6689
6690         if (vlan_id > ETH_VLAN_ID_MAX)
6691                 return 0;
6692
6693         vid_idx = I40E_VFTA_IDX(vlan_id);
6694         vid_bit = I40E_VFTA_BIT(vlan_id);
6695
6696         if (vsi->vfta[vid_idx] & vid_bit)
6697                 return 1;
6698         else
6699                 return 0;
6700 }
6701
6702 static void
6703 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6704                        uint16_t vlan_id, bool on)
6705 {
6706         uint32_t vid_idx, vid_bit;
6707
6708         vid_idx = I40E_VFTA_IDX(vlan_id);
6709         vid_bit = I40E_VFTA_BIT(vlan_id);
6710
6711         if (on)
6712                 vsi->vfta[vid_idx] |= vid_bit;
6713         else
6714                 vsi->vfta[vid_idx] &= ~vid_bit;
6715 }
6716
6717 void
6718 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6719                      uint16_t vlan_id, bool on)
6720 {
6721         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6722         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6723         int ret;
6724
6725         if (vlan_id > ETH_VLAN_ID_MAX)
6726                 return;
6727
6728         i40e_store_vlan_filter(vsi, vlan_id, on);
6729
6730         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6731                 return;
6732
6733         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6734
6735         if (on) {
6736                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6737                                        &vlan_data, 1, NULL);
6738                 if (ret != I40E_SUCCESS)
6739                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6740         } else {
6741                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6742                                           &vlan_data, 1, NULL);
6743                 if (ret != I40E_SUCCESS)
6744                         PMD_DRV_LOG(ERR,
6745                                     "Failed to remove vlan filter");
6746         }
6747 }
6748
6749 /**
6750  * Find all vlan options for specific mac addr,
6751  * return with actual vlan found.
6752  */
6753 int
6754 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6755                            struct i40e_macvlan_filter *mv_f,
6756                            int num, struct ether_addr *addr)
6757 {
6758         int i;
6759         uint32_t j, k;
6760
6761         /**
6762          * Not to use i40e_find_vlan_filter to decrease the loop time,
6763          * although the code looks complex.
6764           */
6765         if (num < vsi->vlan_num)
6766                 return I40E_ERR_PARAM;
6767
6768         i = 0;
6769         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6770                 if (vsi->vfta[j]) {
6771                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6772                                 if (vsi->vfta[j] & (1 << k)) {
6773                                         if (i > num - 1) {
6774                                                 PMD_DRV_LOG(ERR,
6775                                                         "vlan number doesn't match");
6776                                                 return I40E_ERR_PARAM;
6777                                         }
6778                                         rte_memcpy(&mv_f[i].macaddr,
6779                                                         addr, ETH_ADDR_LEN);
6780                                         mv_f[i].vlan_id =
6781                                                 j * I40E_UINT32_BIT_SIZE + k;
6782                                         i++;
6783                                 }
6784                         }
6785                 }
6786         }
6787         return I40E_SUCCESS;
6788 }
6789
6790 static inline int
6791 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6792                            struct i40e_macvlan_filter *mv_f,
6793                            int num,
6794                            uint16_t vlan)
6795 {
6796         int i = 0;
6797         struct i40e_mac_filter *f;
6798
6799         if (num < vsi->mac_num)
6800                 return I40E_ERR_PARAM;
6801
6802         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6803                 if (i > num - 1) {
6804                         PMD_DRV_LOG(ERR, "buffer number not match");
6805                         return I40E_ERR_PARAM;
6806                 }
6807                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6808                                 ETH_ADDR_LEN);
6809                 mv_f[i].vlan_id = vlan;
6810                 mv_f[i].filter_type = f->mac_info.filter_type;
6811                 i++;
6812         }
6813
6814         return I40E_SUCCESS;
6815 }
6816
6817 static int
6818 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6819 {
6820         int i, j, num;
6821         struct i40e_mac_filter *f;
6822         struct i40e_macvlan_filter *mv_f;
6823         int ret = I40E_SUCCESS;
6824
6825         if (vsi == NULL || vsi->mac_num == 0)
6826                 return I40E_ERR_PARAM;
6827
6828         /* Case that no vlan is set */
6829         if (vsi->vlan_num == 0)
6830                 num = vsi->mac_num;
6831         else
6832                 num = vsi->mac_num * vsi->vlan_num;
6833
6834         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6835         if (mv_f == NULL) {
6836                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6837                 return I40E_ERR_NO_MEMORY;
6838         }
6839
6840         i = 0;
6841         if (vsi->vlan_num == 0) {
6842                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6843                         rte_memcpy(&mv_f[i].macaddr,
6844                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6845                         mv_f[i].filter_type = f->mac_info.filter_type;
6846                         mv_f[i].vlan_id = 0;
6847                         i++;
6848                 }
6849         } else {
6850                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6851                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6852                                         vsi->vlan_num, &f->mac_info.mac_addr);
6853                         if (ret != I40E_SUCCESS)
6854                                 goto DONE;
6855                         for (j = i; j < i + vsi->vlan_num; j++)
6856                                 mv_f[j].filter_type = f->mac_info.filter_type;
6857                         i += vsi->vlan_num;
6858                 }
6859         }
6860
6861         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6862 DONE:
6863         rte_free(mv_f);
6864
6865         return ret;
6866 }
6867
6868 int
6869 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6870 {
6871         struct i40e_macvlan_filter *mv_f;
6872         int mac_num;
6873         int ret = I40E_SUCCESS;
6874
6875         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6876                 return I40E_ERR_PARAM;
6877
6878         /* If it's already set, just return */
6879         if (i40e_find_vlan_filter(vsi,vlan))
6880                 return I40E_SUCCESS;
6881
6882         mac_num = vsi->mac_num;
6883
6884         if (mac_num == 0) {
6885                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6886                 return I40E_ERR_PARAM;
6887         }
6888
6889         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6890
6891         if (mv_f == NULL) {
6892                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6893                 return I40E_ERR_NO_MEMORY;
6894         }
6895
6896         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6897
6898         if (ret != I40E_SUCCESS)
6899                 goto DONE;
6900
6901         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6902
6903         if (ret != I40E_SUCCESS)
6904                 goto DONE;
6905
6906         i40e_set_vlan_filter(vsi, vlan, 1);
6907
6908         vsi->vlan_num++;
6909         ret = I40E_SUCCESS;
6910 DONE:
6911         rte_free(mv_f);
6912         return ret;
6913 }
6914
6915 int
6916 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6917 {
6918         struct i40e_macvlan_filter *mv_f;
6919         int mac_num;
6920         int ret = I40E_SUCCESS;
6921
6922         /**
6923          * Vlan 0 is the generic filter for untagged packets
6924          * and can't be removed.
6925          */
6926         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6927                 return I40E_ERR_PARAM;
6928
6929         /* If can't find it, just return */
6930         if (!i40e_find_vlan_filter(vsi, vlan))
6931                 return I40E_ERR_PARAM;
6932
6933         mac_num = vsi->mac_num;
6934
6935         if (mac_num == 0) {
6936                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6937                 return I40E_ERR_PARAM;
6938         }
6939
6940         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6941
6942         if (mv_f == NULL) {
6943                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6944                 return I40E_ERR_NO_MEMORY;
6945         }
6946
6947         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6948
6949         if (ret != I40E_SUCCESS)
6950                 goto DONE;
6951
6952         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6953
6954         if (ret != I40E_SUCCESS)
6955                 goto DONE;
6956
6957         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6958         if (vsi->vlan_num == 1) {
6959                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6960                 if (ret != I40E_SUCCESS)
6961                         goto DONE;
6962
6963                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6964                 if (ret != I40E_SUCCESS)
6965                         goto DONE;
6966         }
6967
6968         i40e_set_vlan_filter(vsi, vlan, 0);
6969
6970         vsi->vlan_num--;
6971         ret = I40E_SUCCESS;
6972 DONE:
6973         rte_free(mv_f);
6974         return ret;
6975 }
6976
6977 int
6978 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6979 {
6980         struct i40e_mac_filter *f;
6981         struct i40e_macvlan_filter *mv_f;
6982         int i, vlan_num = 0;
6983         int ret = I40E_SUCCESS;
6984
6985         /* If it's add and we've config it, return */
6986         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6987         if (f != NULL)
6988                 return I40E_SUCCESS;
6989         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6990                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6991
6992                 /**
6993                  * If vlan_num is 0, that's the first time to add mac,
6994                  * set mask for vlan_id 0.
6995                  */
6996                 if (vsi->vlan_num == 0) {
6997                         i40e_set_vlan_filter(vsi, 0, 1);
6998                         vsi->vlan_num = 1;
6999                 }
7000                 vlan_num = vsi->vlan_num;
7001         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7002                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7003                 vlan_num = 1;
7004
7005         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7006         if (mv_f == NULL) {
7007                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7008                 return I40E_ERR_NO_MEMORY;
7009         }
7010
7011         for (i = 0; i < vlan_num; i++) {
7012                 mv_f[i].filter_type = mac_filter->filter_type;
7013                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7014                                 ETH_ADDR_LEN);
7015         }
7016
7017         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7018                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7019                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7020                                         &mac_filter->mac_addr);
7021                 if (ret != I40E_SUCCESS)
7022                         goto DONE;
7023         }
7024
7025         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7026         if (ret != I40E_SUCCESS)
7027                 goto DONE;
7028
7029         /* Add the mac addr into mac list */
7030         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7031         if (f == NULL) {
7032                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7033                 ret = I40E_ERR_NO_MEMORY;
7034                 goto DONE;
7035         }
7036         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7037                         ETH_ADDR_LEN);
7038         f->mac_info.filter_type = mac_filter->filter_type;
7039         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7040         vsi->mac_num++;
7041
7042         ret = I40E_SUCCESS;
7043 DONE:
7044         rte_free(mv_f);
7045
7046         return ret;
7047 }
7048
7049 int
7050 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7051 {
7052         struct i40e_mac_filter *f;
7053         struct i40e_macvlan_filter *mv_f;
7054         int i, vlan_num;
7055         enum rte_mac_filter_type filter_type;
7056         int ret = I40E_SUCCESS;
7057
7058         /* Can't find it, return an error */
7059         f = i40e_find_mac_filter(vsi, addr);
7060         if (f == NULL)
7061                 return I40E_ERR_PARAM;
7062
7063         vlan_num = vsi->vlan_num;
7064         filter_type = f->mac_info.filter_type;
7065         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7066                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7067                 if (vlan_num == 0) {
7068                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7069                         return I40E_ERR_PARAM;
7070                 }
7071         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7072                         filter_type == RTE_MAC_HASH_MATCH)
7073                 vlan_num = 1;
7074
7075         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7076         if (mv_f == NULL) {
7077                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7078                 return I40E_ERR_NO_MEMORY;
7079         }
7080
7081         for (i = 0; i < vlan_num; i++) {
7082                 mv_f[i].filter_type = filter_type;
7083                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7084                                 ETH_ADDR_LEN);
7085         }
7086         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7087                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7088                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7089                 if (ret != I40E_SUCCESS)
7090                         goto DONE;
7091         }
7092
7093         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7094         if (ret != I40E_SUCCESS)
7095                 goto DONE;
7096
7097         /* Remove the mac addr into mac list */
7098         TAILQ_REMOVE(&vsi->mac_list, f, next);
7099         rte_free(f);
7100         vsi->mac_num--;
7101
7102         ret = I40E_SUCCESS;
7103 DONE:
7104         rte_free(mv_f);
7105         return ret;
7106 }
7107
7108 /* Configure hash enable flags for RSS */
7109 uint64_t
7110 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7111 {
7112         uint64_t hena = 0;
7113         int i;
7114
7115         if (!flags)
7116                 return hena;
7117
7118         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7119                 if (flags & (1ULL << i))
7120                         hena |= adapter->pctypes_tbl[i];
7121         }
7122
7123         return hena;
7124 }
7125
7126 /* Parse the hash enable flags */
7127 uint64_t
7128 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7129 {
7130         uint64_t rss_hf = 0;
7131
7132         if (!flags)
7133                 return rss_hf;
7134         int i;
7135
7136         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7137                 if (flags & adapter->pctypes_tbl[i])
7138                         rss_hf |= (1ULL << i);
7139         }
7140         return rss_hf;
7141 }
7142
7143 /* Disable RSS */
7144 static void
7145 i40e_pf_disable_rss(struct i40e_pf *pf)
7146 {
7147         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7148
7149         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7150         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7151         I40E_WRITE_FLUSH(hw);
7152 }
7153
7154 int
7155 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7156 {
7157         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7158         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7159         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7160                            I40E_VFQF_HKEY_MAX_INDEX :
7161                            I40E_PFQF_HKEY_MAX_INDEX;
7162         int ret = 0;
7163
7164         if (!key || key_len == 0) {
7165                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7166                 return 0;
7167         } else if (key_len != (key_idx + 1) *
7168                 sizeof(uint32_t)) {
7169                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7170                 return -EINVAL;
7171         }
7172
7173         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7174                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7175                         (struct i40e_aqc_get_set_rss_key_data *)key;
7176
7177                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7178                 if (ret)
7179                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7180         } else {
7181                 uint32_t *hash_key = (uint32_t *)key;
7182                 uint16_t i;
7183
7184                 if (vsi->type == I40E_VSI_SRIOV) {
7185                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7186                                 I40E_WRITE_REG(
7187                                         hw,
7188                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7189                                         hash_key[i]);
7190
7191                 } else {
7192                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7193                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7194                                                hash_key[i]);
7195                 }
7196                 I40E_WRITE_FLUSH(hw);
7197         }
7198
7199         return ret;
7200 }
7201
7202 static int
7203 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7204 {
7205         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7206         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7207         uint32_t reg;
7208         int ret;
7209
7210         if (!key || !key_len)
7211                 return -EINVAL;
7212
7213         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7214                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7215                         (struct i40e_aqc_get_set_rss_key_data *)key);
7216                 if (ret) {
7217                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7218                         return ret;
7219                 }
7220         } else {
7221                 uint32_t *key_dw = (uint32_t *)key;
7222                 uint16_t i;
7223
7224                 if (vsi->type == I40E_VSI_SRIOV) {
7225                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7226                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7227                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7228                         }
7229                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7230                                    sizeof(uint32_t);
7231                 } else {
7232                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7233                                 reg = I40E_PFQF_HKEY(i);
7234                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7235                         }
7236                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7237                                    sizeof(uint32_t);
7238                 }
7239         }
7240         return 0;
7241 }
7242
7243 static int
7244 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7245 {
7246         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7247         uint64_t hena;
7248         int ret;
7249
7250         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7251                                rss_conf->rss_key_len);
7252         if (ret)
7253                 return ret;
7254
7255         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7256         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7257         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7258         I40E_WRITE_FLUSH(hw);
7259
7260         return 0;
7261 }
7262
7263 static int
7264 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7265                          struct rte_eth_rss_conf *rss_conf)
7266 {
7267         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7268         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7269         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7270         uint64_t hena;
7271
7272         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7273         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7274
7275         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7276                 if (rss_hf != 0) /* Enable RSS */
7277                         return -EINVAL;
7278                 return 0; /* Nothing to do */
7279         }
7280         /* RSS enabled */
7281         if (rss_hf == 0) /* Disable RSS */
7282                 return -EINVAL;
7283
7284         return i40e_hw_rss_hash_set(pf, rss_conf);
7285 }
7286
7287 static int
7288 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7289                            struct rte_eth_rss_conf *rss_conf)
7290 {
7291         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7292         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7293         uint64_t hena;
7294
7295         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7296                          &rss_conf->rss_key_len);
7297
7298         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7299         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7300         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7301
7302         return 0;
7303 }
7304
7305 static int
7306 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7307 {
7308         switch (filter_type) {
7309         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7310                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7311                 break;
7312         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7313                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7314                 break;
7315         case RTE_TUNNEL_FILTER_IMAC_TENID:
7316                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7317                 break;
7318         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7319                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7320                 break;
7321         case ETH_TUNNEL_FILTER_IMAC:
7322                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7323                 break;
7324         case ETH_TUNNEL_FILTER_OIP:
7325                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7326                 break;
7327         case ETH_TUNNEL_FILTER_IIP:
7328                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7329                 break;
7330         default:
7331                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7332                 return -EINVAL;
7333         }
7334
7335         return 0;
7336 }
7337
7338 /* Convert tunnel filter structure */
7339 static int
7340 i40e_tunnel_filter_convert(
7341         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7342         struct i40e_tunnel_filter *tunnel_filter)
7343 {
7344         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7345                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7346         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7347                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7348         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7349         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7350              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7351             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7352                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7353         else
7354                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7355         tunnel_filter->input.flags = cld_filter->element.flags;
7356         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7357         tunnel_filter->queue = cld_filter->element.queue_number;
7358         rte_memcpy(tunnel_filter->input.general_fields,
7359                    cld_filter->general_fields,
7360                    sizeof(cld_filter->general_fields));
7361
7362         return 0;
7363 }
7364
7365 /* Check if there exists the tunnel filter */
7366 struct i40e_tunnel_filter *
7367 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7368                              const struct i40e_tunnel_filter_input *input)
7369 {
7370         int ret;
7371
7372         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7373         if (ret < 0)
7374                 return NULL;
7375
7376         return tunnel_rule->hash_map[ret];
7377 }
7378
7379 /* Add a tunnel filter into the SW list */
7380 static int
7381 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7382                              struct i40e_tunnel_filter *tunnel_filter)
7383 {
7384         struct i40e_tunnel_rule *rule = &pf->tunnel;
7385         int ret;
7386
7387         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7388         if (ret < 0) {
7389                 PMD_DRV_LOG(ERR,
7390                             "Failed to insert tunnel filter to hash table %d!",
7391                             ret);
7392                 return ret;
7393         }
7394         rule->hash_map[ret] = tunnel_filter;
7395
7396         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7397
7398         return 0;
7399 }
7400
7401 /* Delete a tunnel filter from the SW list */
7402 int
7403 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7404                           struct i40e_tunnel_filter_input *input)
7405 {
7406         struct i40e_tunnel_rule *rule = &pf->tunnel;
7407         struct i40e_tunnel_filter *tunnel_filter;
7408         int ret;
7409
7410         ret = rte_hash_del_key(rule->hash_table, input);
7411         if (ret < 0) {
7412                 PMD_DRV_LOG(ERR,
7413                             "Failed to delete tunnel filter to hash table %d!",
7414                             ret);
7415                 return ret;
7416         }
7417         tunnel_filter = rule->hash_map[ret];
7418         rule->hash_map[ret] = NULL;
7419
7420         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7421         rte_free(tunnel_filter);
7422
7423         return 0;
7424 }
7425
7426 int
7427 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7428                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7429                         uint8_t add)
7430 {
7431         uint16_t ip_type;
7432         uint32_t ipv4_addr, ipv4_addr_le;
7433         uint8_t i, tun_type = 0;
7434         /* internal varialbe to convert ipv6 byte order */
7435         uint32_t convert_ipv6[4];
7436         int val, ret = 0;
7437         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7438         struct i40e_vsi *vsi = pf->main_vsi;
7439         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7440         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7441         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7442         struct i40e_tunnel_filter *tunnel, *node;
7443         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7444
7445         cld_filter = rte_zmalloc("tunnel_filter",
7446                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7447         0);
7448
7449         if (NULL == cld_filter) {
7450                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7451                 return -ENOMEM;
7452         }
7453         pfilter = cld_filter;
7454
7455         ether_addr_copy(&tunnel_filter->outer_mac,
7456                         (struct ether_addr *)&pfilter->element.outer_mac);
7457         ether_addr_copy(&tunnel_filter->inner_mac,
7458                         (struct ether_addr *)&pfilter->element.inner_mac);
7459
7460         pfilter->element.inner_vlan =
7461                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7462         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7463                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7464                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7465                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7466                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7467                                 &ipv4_addr_le,
7468                                 sizeof(pfilter->element.ipaddr.v4.data));
7469         } else {
7470                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7471                 for (i = 0; i < 4; i++) {
7472                         convert_ipv6[i] =
7473                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7474                 }
7475                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7476                            &convert_ipv6,
7477                            sizeof(pfilter->element.ipaddr.v6.data));
7478         }
7479
7480         /* check tunneled type */
7481         switch (tunnel_filter->tunnel_type) {
7482         case RTE_TUNNEL_TYPE_VXLAN:
7483                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7484                 break;
7485         case RTE_TUNNEL_TYPE_NVGRE:
7486                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7487                 break;
7488         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7489                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7490                 break;
7491         default:
7492                 /* Other tunnel types is not supported. */
7493                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7494                 rte_free(cld_filter);
7495                 return -EINVAL;
7496         }
7497
7498         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7499                                        &pfilter->element.flags);
7500         if (val < 0) {
7501                 rte_free(cld_filter);
7502                 return -EINVAL;
7503         }
7504
7505         pfilter->element.flags |= rte_cpu_to_le_16(
7506                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7507                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7508         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7509         pfilter->element.queue_number =
7510                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7511
7512         /* Check if there is the filter in SW list */
7513         memset(&check_filter, 0, sizeof(check_filter));
7514         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7515         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7516         if (add && node) {
7517                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7518                 rte_free(cld_filter);
7519                 return -EINVAL;
7520         }
7521
7522         if (!add && !node) {
7523                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7524                 rte_free(cld_filter);
7525                 return -EINVAL;
7526         }
7527
7528         if (add) {
7529                 ret = i40e_aq_add_cloud_filters(hw,
7530                                         vsi->seid, &cld_filter->element, 1);
7531                 if (ret < 0) {
7532                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7533                         rte_free(cld_filter);
7534                         return -ENOTSUP;
7535                 }
7536                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7537                 if (tunnel == NULL) {
7538                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7539                         rte_free(cld_filter);
7540                         return -ENOMEM;
7541                 }
7542
7543                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7544                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7545                 if (ret < 0)
7546                         rte_free(tunnel);
7547         } else {
7548                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7549                                                    &cld_filter->element, 1);
7550                 if (ret < 0) {
7551                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7552                         rte_free(cld_filter);
7553                         return -ENOTSUP;
7554                 }
7555                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7556         }
7557
7558         rte_free(cld_filter);
7559         return ret;
7560 }
7561
7562 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7563 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7564 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7565 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7566 #define I40E_TR_GRE_KEY_MASK                    0x400
7567 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7568 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7569
7570 static enum
7571 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7572 {
7573         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7574         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7575         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7576         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7577         enum i40e_status_code status = I40E_SUCCESS;
7578
7579         if (pf->support_multi_driver) {
7580                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7581                 return I40E_NOT_SUPPORTED;
7582         }
7583
7584         memset(&filter_replace, 0,
7585                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7586         memset(&filter_replace_buf, 0,
7587                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7588
7589         /* create L1 filter */
7590         filter_replace.old_filter_type =
7591                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7592         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7593         filter_replace.tr_bit = 0;
7594
7595         /* Prepare the buffer, 3 entries */
7596         filter_replace_buf.data[0] =
7597                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7598         filter_replace_buf.data[0] |=
7599                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7600         filter_replace_buf.data[2] = 0xFF;
7601         filter_replace_buf.data[3] = 0xFF;
7602         filter_replace_buf.data[4] =
7603                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7604         filter_replace_buf.data[4] |=
7605                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7606         filter_replace_buf.data[7] = 0xF0;
7607         filter_replace_buf.data[8]
7608                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7609         filter_replace_buf.data[8] |=
7610                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7611         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7612                 I40E_TR_GENEVE_KEY_MASK |
7613                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7614         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7615                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7616                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7617
7618         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7619                                                &filter_replace_buf);
7620         if (!status && (filter_replace.old_filter_type !=
7621                         filter_replace.new_filter_type))
7622                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7623                             " original: 0x%x, new: 0x%x",
7624                             dev->device->name,
7625                             filter_replace.old_filter_type,
7626                             filter_replace.new_filter_type);
7627
7628         return status;
7629 }
7630
7631 static enum
7632 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7633 {
7634         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7635         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7636         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7637         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7638         enum i40e_status_code status = I40E_SUCCESS;
7639
7640         if (pf->support_multi_driver) {
7641                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7642                 return I40E_NOT_SUPPORTED;
7643         }
7644
7645         /* For MPLSoUDP */
7646         memset(&filter_replace, 0,
7647                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7648         memset(&filter_replace_buf, 0,
7649                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7650         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7651                 I40E_AQC_MIRROR_CLOUD_FILTER;
7652         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7653         filter_replace.new_filter_type =
7654                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7655         /* Prepare the buffer, 2 entries */
7656         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7657         filter_replace_buf.data[0] |=
7658                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7659         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7660         filter_replace_buf.data[4] |=
7661                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7662         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7663                                                &filter_replace_buf);
7664         if (status < 0)
7665                 return status;
7666         if (filter_replace.old_filter_type !=
7667             filter_replace.new_filter_type)
7668                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7669                             " original: 0x%x, new: 0x%x",
7670                             dev->device->name,
7671                             filter_replace.old_filter_type,
7672                             filter_replace.new_filter_type);
7673
7674         /* For MPLSoGRE */
7675         memset(&filter_replace, 0,
7676                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7677         memset(&filter_replace_buf, 0,
7678                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7679
7680         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7681                 I40E_AQC_MIRROR_CLOUD_FILTER;
7682         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7683         filter_replace.new_filter_type =
7684                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7685         /* Prepare the buffer, 2 entries */
7686         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7687         filter_replace_buf.data[0] |=
7688                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7689         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7690         filter_replace_buf.data[4] |=
7691                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7692
7693         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7694                                                &filter_replace_buf);
7695         if (!status && (filter_replace.old_filter_type !=
7696                         filter_replace.new_filter_type))
7697                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7698                             " original: 0x%x, new: 0x%x",
7699                             dev->device->name,
7700                             filter_replace.old_filter_type,
7701                             filter_replace.new_filter_type);
7702
7703         return status;
7704 }
7705
7706 static enum i40e_status_code
7707 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7708 {
7709         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7710         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7711         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7712         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7713         enum i40e_status_code status = I40E_SUCCESS;
7714
7715         if (pf->support_multi_driver) {
7716                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7717                 return I40E_NOT_SUPPORTED;
7718         }
7719
7720         /* For GTP-C */
7721         memset(&filter_replace, 0,
7722                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7723         memset(&filter_replace_buf, 0,
7724                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7725         /* create L1 filter */
7726         filter_replace.old_filter_type =
7727                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7728         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7729         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7730                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7731         /* Prepare the buffer, 2 entries */
7732         filter_replace_buf.data[0] =
7733                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7734         filter_replace_buf.data[0] |=
7735                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7736         filter_replace_buf.data[2] = 0xFF;
7737         filter_replace_buf.data[3] = 0xFF;
7738         filter_replace_buf.data[4] =
7739                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7740         filter_replace_buf.data[4] |=
7741                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7742         filter_replace_buf.data[6] = 0xFF;
7743         filter_replace_buf.data[7] = 0xFF;
7744         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7745                                                &filter_replace_buf);
7746         if (status < 0)
7747                 return status;
7748         if (filter_replace.old_filter_type !=
7749             filter_replace.new_filter_type)
7750                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7751                             " original: 0x%x, new: 0x%x",
7752                             dev->device->name,
7753                             filter_replace.old_filter_type,
7754                             filter_replace.new_filter_type);
7755
7756         /* for GTP-U */
7757         memset(&filter_replace, 0,
7758                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7759         memset(&filter_replace_buf, 0,
7760                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7761         /* create L1 filter */
7762         filter_replace.old_filter_type =
7763                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7764         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7765         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7766                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7767         /* Prepare the buffer, 2 entries */
7768         filter_replace_buf.data[0] =
7769                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7770         filter_replace_buf.data[0] |=
7771                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7772         filter_replace_buf.data[2] = 0xFF;
7773         filter_replace_buf.data[3] = 0xFF;
7774         filter_replace_buf.data[4] =
7775                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7776         filter_replace_buf.data[4] |=
7777                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7778         filter_replace_buf.data[6] = 0xFF;
7779         filter_replace_buf.data[7] = 0xFF;
7780
7781         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7782                                                &filter_replace_buf);
7783         if (!status && (filter_replace.old_filter_type !=
7784                         filter_replace.new_filter_type))
7785                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7786                             " original: 0x%x, new: 0x%x",
7787                             dev->device->name,
7788                             filter_replace.old_filter_type,
7789                             filter_replace.new_filter_type);
7790
7791         return status;
7792 }
7793
7794 static enum
7795 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7796 {
7797         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7798         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7799         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7800         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7801         enum i40e_status_code status = I40E_SUCCESS;
7802
7803         if (pf->support_multi_driver) {
7804                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7805                 return I40E_NOT_SUPPORTED;
7806         }
7807
7808         /* for GTP-C */
7809         memset(&filter_replace, 0,
7810                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7811         memset(&filter_replace_buf, 0,
7812                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7813         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7814         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7815         filter_replace.new_filter_type =
7816                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7817         /* Prepare the buffer, 2 entries */
7818         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7819         filter_replace_buf.data[0] |=
7820                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7821         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7822         filter_replace_buf.data[4] |=
7823                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7824         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7825                                                &filter_replace_buf);
7826         if (status < 0)
7827                 return status;
7828         if (filter_replace.old_filter_type !=
7829             filter_replace.new_filter_type)
7830                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7831                             " original: 0x%x, new: 0x%x",
7832                             dev->device->name,
7833                             filter_replace.old_filter_type,
7834                             filter_replace.new_filter_type);
7835
7836         /* for GTP-U */
7837         memset(&filter_replace, 0,
7838                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7839         memset(&filter_replace_buf, 0,
7840                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7841         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7842         filter_replace.old_filter_type =
7843                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7844         filter_replace.new_filter_type =
7845                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7846         /* Prepare the buffer, 2 entries */
7847         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7848         filter_replace_buf.data[0] |=
7849                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7850         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7851         filter_replace_buf.data[4] |=
7852                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7853
7854         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7855                                                &filter_replace_buf);
7856         if (!status && (filter_replace.old_filter_type !=
7857                         filter_replace.new_filter_type))
7858                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7859                             " original: 0x%x, new: 0x%x",
7860                             dev->device->name,
7861                             filter_replace.old_filter_type,
7862                             filter_replace.new_filter_type);
7863
7864         return status;
7865 }
7866
7867 int
7868 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7869                       struct i40e_tunnel_filter_conf *tunnel_filter,
7870                       uint8_t add)
7871 {
7872         uint16_t ip_type;
7873         uint32_t ipv4_addr, ipv4_addr_le;
7874         uint8_t i, tun_type = 0;
7875         /* internal variable to convert ipv6 byte order */
7876         uint32_t convert_ipv6[4];
7877         int val, ret = 0;
7878         struct i40e_pf_vf *vf = NULL;
7879         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7880         struct i40e_vsi *vsi;
7881         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7882         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7883         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7884         struct i40e_tunnel_filter *tunnel, *node;
7885         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7886         uint32_t teid_le;
7887         bool big_buffer = 0;
7888
7889         cld_filter = rte_zmalloc("tunnel_filter",
7890                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7891                          0);
7892
7893         if (cld_filter == NULL) {
7894                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7895                 return -ENOMEM;
7896         }
7897         pfilter = cld_filter;
7898
7899         ether_addr_copy(&tunnel_filter->outer_mac,
7900                         (struct ether_addr *)&pfilter->element.outer_mac);
7901         ether_addr_copy(&tunnel_filter->inner_mac,
7902                         (struct ether_addr *)&pfilter->element.inner_mac);
7903
7904         pfilter->element.inner_vlan =
7905                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7906         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7907                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7908                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7909                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7910                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7911                                 &ipv4_addr_le,
7912                                 sizeof(pfilter->element.ipaddr.v4.data));
7913         } else {
7914                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7915                 for (i = 0; i < 4; i++) {
7916                         convert_ipv6[i] =
7917                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7918                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7919                 }
7920                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7921                            &convert_ipv6,
7922                            sizeof(pfilter->element.ipaddr.v6.data));
7923         }
7924
7925         /* check tunneled type */
7926         switch (tunnel_filter->tunnel_type) {
7927         case I40E_TUNNEL_TYPE_VXLAN:
7928                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7929                 break;
7930         case I40E_TUNNEL_TYPE_NVGRE:
7931                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7932                 break;
7933         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7934                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7935                 break;
7936         case I40E_TUNNEL_TYPE_MPLSoUDP:
7937                 if (!pf->mpls_replace_flag) {
7938                         i40e_replace_mpls_l1_filter(pf);
7939                         i40e_replace_mpls_cloud_filter(pf);
7940                         pf->mpls_replace_flag = 1;
7941                 }
7942                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7943                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7944                         teid_le >> 4;
7945                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7946                         (teid_le & 0xF) << 12;
7947                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7948                         0x40;
7949                 big_buffer = 1;
7950                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7951                 break;
7952         case I40E_TUNNEL_TYPE_MPLSoGRE:
7953                 if (!pf->mpls_replace_flag) {
7954                         i40e_replace_mpls_l1_filter(pf);
7955                         i40e_replace_mpls_cloud_filter(pf);
7956                         pf->mpls_replace_flag = 1;
7957                 }
7958                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7959                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7960                         teid_le >> 4;
7961                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7962                         (teid_le & 0xF) << 12;
7963                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7964                         0x0;
7965                 big_buffer = 1;
7966                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7967                 break;
7968         case I40E_TUNNEL_TYPE_GTPC:
7969                 if (!pf->gtp_replace_flag) {
7970                         i40e_replace_gtp_l1_filter(pf);
7971                         i40e_replace_gtp_cloud_filter(pf);
7972                         pf->gtp_replace_flag = 1;
7973                 }
7974                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7975                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7976                         (teid_le >> 16) & 0xFFFF;
7977                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7978                         teid_le & 0xFFFF;
7979                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7980                         0x0;
7981                 big_buffer = 1;
7982                 break;
7983         case I40E_TUNNEL_TYPE_GTPU:
7984                 if (!pf->gtp_replace_flag) {
7985                         i40e_replace_gtp_l1_filter(pf);
7986                         i40e_replace_gtp_cloud_filter(pf);
7987                         pf->gtp_replace_flag = 1;
7988                 }
7989                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7990                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7991                         (teid_le >> 16) & 0xFFFF;
7992                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7993                         teid_le & 0xFFFF;
7994                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7995                         0x0;
7996                 big_buffer = 1;
7997                 break;
7998         case I40E_TUNNEL_TYPE_QINQ:
7999                 if (!pf->qinq_replace_flag) {
8000                         ret = i40e_cloud_filter_qinq_create(pf);
8001                         if (ret < 0)
8002                                 PMD_DRV_LOG(DEBUG,
8003                                             "QinQ tunnel filter already created.");
8004                         pf->qinq_replace_flag = 1;
8005                 }
8006                 /*      Add in the General fields the values of
8007                  *      the Outer and Inner VLAN
8008                  *      Big Buffer should be set, see changes in
8009                  *      i40e_aq_add_cloud_filters
8010                  */
8011                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8012                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8013                 big_buffer = 1;
8014                 break;
8015         default:
8016                 /* Other tunnel types is not supported. */
8017                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8018                 rte_free(cld_filter);
8019                 return -EINVAL;
8020         }
8021
8022         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8023                 pfilter->element.flags =
8024                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8025         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8026                 pfilter->element.flags =
8027                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8028         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8029                 pfilter->element.flags =
8030                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8031         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8032                 pfilter->element.flags =
8033                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8034         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8035                 pfilter->element.flags |=
8036                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8037         else {
8038                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8039                                                 &pfilter->element.flags);
8040                 if (val < 0) {
8041                         rte_free(cld_filter);
8042                         return -EINVAL;
8043                 }
8044         }
8045
8046         pfilter->element.flags |= rte_cpu_to_le_16(
8047                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8048                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8049         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8050         pfilter->element.queue_number =
8051                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8052
8053         if (!tunnel_filter->is_to_vf)
8054                 vsi = pf->main_vsi;
8055         else {
8056                 if (tunnel_filter->vf_id >= pf->vf_num) {
8057                         PMD_DRV_LOG(ERR, "Invalid argument.");
8058                         rte_free(cld_filter);
8059                         return -EINVAL;
8060                 }
8061                 vf = &pf->vfs[tunnel_filter->vf_id];
8062                 vsi = vf->vsi;
8063         }
8064
8065         /* Check if there is the filter in SW list */
8066         memset(&check_filter, 0, sizeof(check_filter));
8067         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8068         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8069         check_filter.vf_id = tunnel_filter->vf_id;
8070         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8071         if (add && node) {
8072                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8073                 rte_free(cld_filter);
8074                 return -EINVAL;
8075         }
8076
8077         if (!add && !node) {
8078                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8079                 rte_free(cld_filter);
8080                 return -EINVAL;
8081         }
8082
8083         if (add) {
8084                 if (big_buffer)
8085                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
8086                                                    vsi->seid, cld_filter, 1);
8087                 else
8088                         ret = i40e_aq_add_cloud_filters(hw,
8089                                         vsi->seid, &cld_filter->element, 1);
8090                 if (ret < 0) {
8091                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8092                         rte_free(cld_filter);
8093                         return -ENOTSUP;
8094                 }
8095                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8096                 if (tunnel == NULL) {
8097                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8098                         rte_free(cld_filter);
8099                         return -ENOMEM;
8100                 }
8101
8102                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8103                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8104                 if (ret < 0)
8105                         rte_free(tunnel);
8106         } else {
8107                 if (big_buffer)
8108                         ret = i40e_aq_remove_cloud_filters_big_buffer(
8109                                 hw, vsi->seid, cld_filter, 1);
8110                 else
8111                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
8112                                                    &cld_filter->element, 1);
8113                 if (ret < 0) {
8114                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8115                         rte_free(cld_filter);
8116                         return -ENOTSUP;
8117                 }
8118                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8119         }
8120
8121         rte_free(cld_filter);
8122         return ret;
8123 }
8124
8125 static int
8126 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8127 {
8128         uint8_t i;
8129
8130         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8131                 if (pf->vxlan_ports[i] == port)
8132                         return i;
8133         }
8134
8135         return -1;
8136 }
8137
8138 static int
8139 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8140 {
8141         int  idx, ret;
8142         uint8_t filter_idx;
8143         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8144
8145         idx = i40e_get_vxlan_port_idx(pf, port);
8146
8147         /* Check if port already exists */
8148         if (idx >= 0) {
8149                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8150                 return -EINVAL;
8151         }
8152
8153         /* Now check if there is space to add the new port */
8154         idx = i40e_get_vxlan_port_idx(pf, 0);
8155         if (idx < 0) {
8156                 PMD_DRV_LOG(ERR,
8157                         "Maximum number of UDP ports reached, not adding port %d",
8158                         port);
8159                 return -ENOSPC;
8160         }
8161
8162         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8163                                         &filter_idx, NULL);
8164         if (ret < 0) {
8165                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8166                 return -1;
8167         }
8168
8169         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8170                          port,  filter_idx);
8171
8172         /* New port: add it and mark its index in the bitmap */
8173         pf->vxlan_ports[idx] = port;
8174         pf->vxlan_bitmap |= (1 << idx);
8175
8176         if (!(pf->flags & I40E_FLAG_VXLAN))
8177                 pf->flags |= I40E_FLAG_VXLAN;
8178
8179         return 0;
8180 }
8181
8182 static int
8183 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8184 {
8185         int idx;
8186         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8187
8188         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8189                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8190                 return -EINVAL;
8191         }
8192
8193         idx = i40e_get_vxlan_port_idx(pf, port);
8194
8195         if (idx < 0) {
8196                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8197                 return -EINVAL;
8198         }
8199
8200         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8201                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8202                 return -1;
8203         }
8204
8205         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8206                         port, idx);
8207
8208         pf->vxlan_ports[idx] = 0;
8209         pf->vxlan_bitmap &= ~(1 << idx);
8210
8211         if (!pf->vxlan_bitmap)
8212                 pf->flags &= ~I40E_FLAG_VXLAN;
8213
8214         return 0;
8215 }
8216
8217 /* Add UDP tunneling port */
8218 static int
8219 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8220                              struct rte_eth_udp_tunnel *udp_tunnel)
8221 {
8222         int ret = 0;
8223         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8224
8225         if (udp_tunnel == NULL)
8226                 return -EINVAL;
8227
8228         switch (udp_tunnel->prot_type) {
8229         case RTE_TUNNEL_TYPE_VXLAN:
8230                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8231                 break;
8232
8233         case RTE_TUNNEL_TYPE_GENEVE:
8234         case RTE_TUNNEL_TYPE_TEREDO:
8235                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8236                 ret = -1;
8237                 break;
8238
8239         default:
8240                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8241                 ret = -1;
8242                 break;
8243         }
8244
8245         return ret;
8246 }
8247
8248 /* Remove UDP tunneling port */
8249 static int
8250 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8251                              struct rte_eth_udp_tunnel *udp_tunnel)
8252 {
8253         int ret = 0;
8254         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8255
8256         if (udp_tunnel == NULL)
8257                 return -EINVAL;
8258
8259         switch (udp_tunnel->prot_type) {
8260         case RTE_TUNNEL_TYPE_VXLAN:
8261                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8262                 break;
8263         case RTE_TUNNEL_TYPE_GENEVE:
8264         case RTE_TUNNEL_TYPE_TEREDO:
8265                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8266                 ret = -1;
8267                 break;
8268         default:
8269                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8270                 ret = -1;
8271                 break;
8272         }
8273
8274         return ret;
8275 }
8276
8277 /* Calculate the maximum number of contiguous PF queues that are configured */
8278 static int
8279 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8280 {
8281         struct rte_eth_dev_data *data = pf->dev_data;
8282         int i, num;
8283         struct i40e_rx_queue *rxq;
8284
8285         num = 0;
8286         for (i = 0; i < pf->lan_nb_qps; i++) {
8287                 rxq = data->rx_queues[i];
8288                 if (rxq && rxq->q_set)
8289                         num++;
8290                 else
8291                         break;
8292         }
8293
8294         return num;
8295 }
8296
8297 /* Configure RSS */
8298 static int
8299 i40e_pf_config_rss(struct i40e_pf *pf)
8300 {
8301         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8302         struct rte_eth_rss_conf rss_conf;
8303         uint32_t i, lut = 0;
8304         uint16_t j, num;
8305
8306         /*
8307          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8308          * It's necessary to calculate the actual PF queues that are configured.
8309          */
8310         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8311                 num = i40e_pf_calc_configured_queues_num(pf);
8312         else
8313                 num = pf->dev_data->nb_rx_queues;
8314
8315         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8316         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8317                         num);
8318
8319         if (num == 0) {
8320                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8321                 return -ENOTSUP;
8322         }
8323
8324         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8325                 if (j == num)
8326                         j = 0;
8327                 lut = (lut << 8) | (j & ((0x1 <<
8328                         hw->func_caps.rss_table_entry_width) - 1));
8329                 if ((i & 3) == 3)
8330                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8331         }
8332
8333         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8334         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8335                 i40e_pf_disable_rss(pf);
8336                 return 0;
8337         }
8338         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8339                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8340                 /* Random default keys */
8341                 static uint32_t rss_key_default[] = {0x6b793944,
8342                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8343                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8344                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8345
8346                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8347                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8348                                                         sizeof(uint32_t);
8349         }
8350
8351         return i40e_hw_rss_hash_set(pf, &rss_conf);
8352 }
8353
8354 static int
8355 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8356                                struct rte_eth_tunnel_filter_conf *filter)
8357 {
8358         if (pf == NULL || filter == NULL) {
8359                 PMD_DRV_LOG(ERR, "Invalid parameter");
8360                 return -EINVAL;
8361         }
8362
8363         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8364                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8365                 return -EINVAL;
8366         }
8367
8368         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8369                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8370                 return -EINVAL;
8371         }
8372
8373         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8374                 (is_zero_ether_addr(&filter->outer_mac))) {
8375                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8376                 return -EINVAL;
8377         }
8378
8379         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8380                 (is_zero_ether_addr(&filter->inner_mac))) {
8381                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8382                 return -EINVAL;
8383         }
8384
8385         return 0;
8386 }
8387
8388 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8389 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8390 static int
8391 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8392 {
8393         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8394         uint32_t val, reg;
8395         int ret = -EINVAL;
8396
8397         if (pf->support_multi_driver) {
8398                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8399                 return -ENOTSUP;
8400         }
8401
8402         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8403         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8404
8405         if (len == 3) {
8406                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8407         } else if (len == 4) {
8408                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8409         } else {
8410                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8411                 return ret;
8412         }
8413
8414         if (reg != val) {
8415                 ret = i40e_aq_debug_write_global_register(hw,
8416                                                    I40E_GL_PRS_FVBM(2),
8417                                                    reg, NULL);
8418                 if (ret != 0)
8419                         return ret;
8420                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8421                             "with value 0x%08x",
8422                             I40E_GL_PRS_FVBM(2), reg);
8423         } else {
8424                 ret = 0;
8425         }
8426         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8427                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8428
8429         return ret;
8430 }
8431
8432 static int
8433 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8434 {
8435         int ret = -EINVAL;
8436
8437         if (!hw || !cfg)
8438                 return -EINVAL;
8439
8440         switch (cfg->cfg_type) {
8441         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8442                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8443                 break;
8444         default:
8445                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8446                 break;
8447         }
8448
8449         return ret;
8450 }
8451
8452 static int
8453 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8454                                enum rte_filter_op filter_op,
8455                                void *arg)
8456 {
8457         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8458         int ret = I40E_ERR_PARAM;
8459
8460         switch (filter_op) {
8461         case RTE_ETH_FILTER_SET:
8462                 ret = i40e_dev_global_config_set(hw,
8463                         (struct rte_eth_global_cfg *)arg);
8464                 break;
8465         default:
8466                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8467                 break;
8468         }
8469
8470         return ret;
8471 }
8472
8473 static int
8474 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8475                           enum rte_filter_op filter_op,
8476                           void *arg)
8477 {
8478         struct rte_eth_tunnel_filter_conf *filter;
8479         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8480         int ret = I40E_SUCCESS;
8481
8482         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8483
8484         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8485                 return I40E_ERR_PARAM;
8486
8487         switch (filter_op) {
8488         case RTE_ETH_FILTER_NOP:
8489                 if (!(pf->flags & I40E_FLAG_VXLAN))
8490                         ret = I40E_NOT_SUPPORTED;
8491                 break;
8492         case RTE_ETH_FILTER_ADD:
8493                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8494                 break;
8495         case RTE_ETH_FILTER_DELETE:
8496                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8497                 break;
8498         default:
8499                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8500                 ret = I40E_ERR_PARAM;
8501                 break;
8502         }
8503
8504         return ret;
8505 }
8506
8507 static int
8508 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8509 {
8510         int ret = 0;
8511         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8512
8513         /* RSS setup */
8514         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8515                 ret = i40e_pf_config_rss(pf);
8516         else
8517                 i40e_pf_disable_rss(pf);
8518
8519         return ret;
8520 }
8521
8522 /* Get the symmetric hash enable configurations per port */
8523 static void
8524 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8525 {
8526         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8527
8528         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8529 }
8530
8531 /* Set the symmetric hash enable configurations per port */
8532 static void
8533 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8534 {
8535         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8536
8537         if (enable > 0) {
8538                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8539                         PMD_DRV_LOG(INFO,
8540                                 "Symmetric hash has already been enabled");
8541                         return;
8542                 }
8543                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8544         } else {
8545                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8546                         PMD_DRV_LOG(INFO,
8547                                 "Symmetric hash has already been disabled");
8548                         return;
8549                 }
8550                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8551         }
8552         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8553         I40E_WRITE_FLUSH(hw);
8554 }
8555
8556 /*
8557  * Get global configurations of hash function type and symmetric hash enable
8558  * per flow type (pctype). Note that global configuration means it affects all
8559  * the ports on the same NIC.
8560  */
8561 static int
8562 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8563                                    struct rte_eth_hash_global_conf *g_cfg)
8564 {
8565         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8566         uint32_t reg;
8567         uint16_t i, j;
8568
8569         memset(g_cfg, 0, sizeof(*g_cfg));
8570         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8571         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8572                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8573         else
8574                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8575         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8576                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8577
8578         /*
8579          * As i40e supports less than 64 flow types, only first 64 bits need to
8580          * be checked.
8581          */
8582         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8583                 g_cfg->valid_bit_mask[i] = 0ULL;
8584                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8585         }
8586
8587         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8588
8589         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8590                 if (!adapter->pctypes_tbl[i])
8591                         continue;
8592                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8593                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8594                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8595                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8596                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8597                                         g_cfg->sym_hash_enable_mask[0] |=
8598                                                                 (1ULL << i);
8599                                 }
8600                         }
8601                 }
8602         }
8603
8604         return 0;
8605 }
8606
8607 static int
8608 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8609                               const struct rte_eth_hash_global_conf *g_cfg)
8610 {
8611         uint32_t i;
8612         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8613
8614         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8615                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8616                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8617                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8618                                                 g_cfg->hash_func);
8619                 return -EINVAL;
8620         }
8621
8622         /*
8623          * As i40e supports less than 64 flow types, only first 64 bits need to
8624          * be checked.
8625          */
8626         mask0 = g_cfg->valid_bit_mask[0];
8627         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8628                 if (i == 0) {
8629                         /* Check if any unsupported flow type configured */
8630                         if ((mask0 | i40e_mask) ^ i40e_mask)
8631                                 goto mask_err;
8632                 } else {
8633                         if (g_cfg->valid_bit_mask[i])
8634                                 goto mask_err;
8635                 }
8636         }
8637
8638         return 0;
8639
8640 mask_err:
8641         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8642
8643         return -EINVAL;
8644 }
8645
8646 /*
8647  * Set global configurations of hash function type and symmetric hash enable
8648  * per flow type (pctype). Note any modifying global configuration will affect
8649  * all the ports on the same NIC.
8650  */
8651 static int
8652 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8653                                    struct rte_eth_hash_global_conf *g_cfg)
8654 {
8655         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8656         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8657         int ret;
8658         uint16_t i, j;
8659         uint32_t reg;
8660         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8661
8662         if (pf->support_multi_driver) {
8663                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8664                 return -ENOTSUP;
8665         }
8666
8667         /* Check the input parameters */
8668         ret = i40e_hash_global_config_check(adapter, g_cfg);
8669         if (ret < 0)
8670                 return ret;
8671
8672         /*
8673          * As i40e supports less than 64 flow types, only first 64 bits need to
8674          * be configured.
8675          */
8676         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8677                 if (mask0 & (1UL << i)) {
8678                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8679                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8680
8681                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8682                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8683                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8684                                         i40e_write_global_rx_ctl(hw,
8685                                                           I40E_GLQF_HSYM(j),
8686                                                           reg);
8687                         }
8688                 }
8689         }
8690
8691         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8692         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8693                 /* Toeplitz */
8694                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8695                         PMD_DRV_LOG(DEBUG,
8696                                 "Hash function already set to Toeplitz");
8697                         goto out;
8698                 }
8699                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8700         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8701                 /* Simple XOR */
8702                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8703                         PMD_DRV_LOG(DEBUG,
8704                                 "Hash function already set to Simple XOR");
8705                         goto out;
8706                 }
8707                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8708         } else
8709                 /* Use the default, and keep it as it is */
8710                 goto out;
8711
8712         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8713
8714 out:
8715         I40E_WRITE_FLUSH(hw);
8716
8717         return 0;
8718 }
8719
8720 /**
8721  * Valid input sets for hash and flow director filters per PCTYPE
8722  */
8723 static uint64_t
8724 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8725                 enum rte_filter_type filter)
8726 {
8727         uint64_t valid;
8728
8729         static const uint64_t valid_hash_inset_table[] = {
8730                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8731                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8732                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8733                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8734                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8735                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8736                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8737                         I40E_INSET_FLEX_PAYLOAD,
8738                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8739                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8740                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8741                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8742                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8743                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8744                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8745                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8746                         I40E_INSET_FLEX_PAYLOAD,
8747                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8748                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8749                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8750                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8751                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8752                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8753                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8754                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8755                         I40E_INSET_FLEX_PAYLOAD,
8756                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8757                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8758                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8759                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8760                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8761                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8762                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8763                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8764                         I40E_INSET_FLEX_PAYLOAD,
8765                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8766                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8767                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8768                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8769                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8770                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8771                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8772                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8773                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8774                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8775                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8776                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8777                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8778                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8779                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8780                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8781                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8782                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8783                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8784                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8785                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8786                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8787                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8788                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8789                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8790                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8791                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8792                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8793                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8794                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8795                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8796                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8797                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8798                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8799                         I40E_INSET_FLEX_PAYLOAD,
8800                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8801                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8802                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8803                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8804                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8805                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8806                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8807                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8808                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8809                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8810                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8811                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8812                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8813                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8814                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8815                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8816                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8817                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8818                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8819                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8820                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8821                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8822                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8823                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8824                         I40E_INSET_FLEX_PAYLOAD,
8825                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8826                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8827                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8828                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8829                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8830                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8831                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8832                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8833                         I40E_INSET_FLEX_PAYLOAD,
8834                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8835                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8836                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8837                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8838                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8839                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8840                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8841                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8842                         I40E_INSET_FLEX_PAYLOAD,
8843                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8844                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8845                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8846                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8847                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8848                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8849                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8850                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8851                         I40E_INSET_FLEX_PAYLOAD,
8852                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8853                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8854                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8855                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8856                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8857                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8858                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8859                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8860                         I40E_INSET_FLEX_PAYLOAD,
8861                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8862                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8863                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8864                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8865                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8866                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8867                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8868                         I40E_INSET_FLEX_PAYLOAD,
8869                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8870                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8871                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8872                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8873                         I40E_INSET_FLEX_PAYLOAD,
8874         };
8875
8876         /**
8877          * Flow director supports only fields defined in
8878          * union rte_eth_fdir_flow.
8879          */
8880         static const uint64_t valid_fdir_inset_table[] = {
8881                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8882                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8883                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8884                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8885                 I40E_INSET_IPV4_TTL,
8886                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8887                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8888                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8889                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8890                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8891                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8892                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8893                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8894                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8895                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8896                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8897                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8898                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8899                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8900                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8901                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8902                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8903                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8904                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8905                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8906                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8907                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8908                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8909                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8910                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8911                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8912                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8913                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8914                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8915                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8916                 I40E_INSET_SCTP_VT,
8917                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8918                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8919                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8920                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8921                 I40E_INSET_IPV4_TTL,
8922                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8923                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8924                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8925                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8926                 I40E_INSET_IPV6_HOP_LIMIT,
8927                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8928                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8929                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8930                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8931                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8932                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8933                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8934                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8935                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8936                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8937                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8938                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8939                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8940                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8941                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8942                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8943                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8944                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8945                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8946                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8947                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8948                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8949                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8950                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8951                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8952                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8953                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8954                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8955                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8956                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8957                 I40E_INSET_SCTP_VT,
8958                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8959                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8960                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8961                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8962                 I40E_INSET_IPV6_HOP_LIMIT,
8963                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8964                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8965                 I40E_INSET_LAST_ETHER_TYPE,
8966         };
8967
8968         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8969                 return 0;
8970         if (filter == RTE_ETH_FILTER_HASH)
8971                 valid = valid_hash_inset_table[pctype];
8972         else
8973                 valid = valid_fdir_inset_table[pctype];
8974
8975         return valid;
8976 }
8977
8978 /**
8979  * Validate if the input set is allowed for a specific PCTYPE
8980  */
8981 int
8982 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8983                 enum rte_filter_type filter, uint64_t inset)
8984 {
8985         uint64_t valid;
8986
8987         valid = i40e_get_valid_input_set(pctype, filter);
8988         if (inset & (~valid))
8989                 return -EINVAL;
8990
8991         return 0;
8992 }
8993
8994 /* default input set fields combination per pctype */
8995 uint64_t
8996 i40e_get_default_input_set(uint16_t pctype)
8997 {
8998         static const uint64_t default_inset_table[] = {
8999                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9000                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9001                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9002                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9003                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9004                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9005                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9006                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9007                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9008                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9009                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9010                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9011                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9012                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9013                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9014                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9015                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9016                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9017                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9018                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9019                         I40E_INSET_SCTP_VT,
9020                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9021                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9022                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9023                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9024                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9025                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9026                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9027                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9028                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9029                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9030                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9031                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9032                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9033                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9034                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9035                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9036                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9037                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9038                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9039                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9040                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9041                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9042                         I40E_INSET_SCTP_VT,
9043                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9044                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9045                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9046                         I40E_INSET_LAST_ETHER_TYPE,
9047         };
9048
9049         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9050                 return 0;
9051
9052         return default_inset_table[pctype];
9053 }
9054
9055 /**
9056  * Parse the input set from index to logical bit masks
9057  */
9058 static int
9059 i40e_parse_input_set(uint64_t *inset,
9060                      enum i40e_filter_pctype pctype,
9061                      enum rte_eth_input_set_field *field,
9062                      uint16_t size)
9063 {
9064         uint16_t i, j;
9065         int ret = -EINVAL;
9066
9067         static const struct {
9068                 enum rte_eth_input_set_field field;
9069                 uint64_t inset;
9070         } inset_convert_table[] = {
9071                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9072                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9073                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9074                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9075                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9076                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9077                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9078                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9079                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9080                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9081                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9082                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9083                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9084                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9085                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9086                         I40E_INSET_IPV6_NEXT_HDR},
9087                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9088                         I40E_INSET_IPV6_HOP_LIMIT},
9089                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9090                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9091                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9092                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9093                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9094                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9095                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9096                         I40E_INSET_SCTP_VT},
9097                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9098                         I40E_INSET_TUNNEL_DMAC},
9099                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9100                         I40E_INSET_VLAN_TUNNEL},
9101                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9102                         I40E_INSET_TUNNEL_ID},
9103                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9104                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9105                         I40E_INSET_FLEX_PAYLOAD_W1},
9106                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9107                         I40E_INSET_FLEX_PAYLOAD_W2},
9108                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9109                         I40E_INSET_FLEX_PAYLOAD_W3},
9110                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9111                         I40E_INSET_FLEX_PAYLOAD_W4},
9112                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9113                         I40E_INSET_FLEX_PAYLOAD_W5},
9114                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9115                         I40E_INSET_FLEX_PAYLOAD_W6},
9116                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9117                         I40E_INSET_FLEX_PAYLOAD_W7},
9118                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9119                         I40E_INSET_FLEX_PAYLOAD_W8},
9120         };
9121
9122         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9123                 return ret;
9124
9125         /* Only one item allowed for default or all */
9126         if (size == 1) {
9127                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9128                         *inset = i40e_get_default_input_set(pctype);
9129                         return 0;
9130                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9131                         *inset = I40E_INSET_NONE;
9132                         return 0;
9133                 }
9134         }
9135
9136         for (i = 0, *inset = 0; i < size; i++) {
9137                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9138                         if (field[i] == inset_convert_table[j].field) {
9139                                 *inset |= inset_convert_table[j].inset;
9140                                 break;
9141                         }
9142                 }
9143
9144                 /* It contains unsupported input set, return immediately */
9145                 if (j == RTE_DIM(inset_convert_table))
9146                         return ret;
9147         }
9148
9149         return 0;
9150 }
9151
9152 /**
9153  * Translate the input set from bit masks to register aware bit masks
9154  * and vice versa
9155  */
9156 uint64_t
9157 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9158 {
9159         uint64_t val = 0;
9160         uint16_t i;
9161
9162         struct inset_map {
9163                 uint64_t inset;
9164                 uint64_t inset_reg;
9165         };
9166
9167         static const struct inset_map inset_map_common[] = {
9168                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9169                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9170                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9171                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9172                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9173                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9174                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9175                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9176                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9177                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9178                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9179                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9180                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9181                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9182                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9183                 {I40E_INSET_TUNNEL_DMAC,
9184                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9185                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9186                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9187                 {I40E_INSET_TUNNEL_SRC_PORT,
9188                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9189                 {I40E_INSET_TUNNEL_DST_PORT,
9190                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9191                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9192                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9193                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9194                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9195                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9196                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9197                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9198                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9199                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9200         };
9201
9202     /* some different registers map in x722*/
9203         static const struct inset_map inset_map_diff_x722[] = {
9204                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9205                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9206                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9207                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9208         };
9209
9210         static const struct inset_map inset_map_diff_not_x722[] = {
9211                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9212                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9213                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9214                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9215         };
9216
9217         if (input == 0)
9218                 return val;
9219
9220         /* Translate input set to register aware inset */
9221         if (type == I40E_MAC_X722) {
9222                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9223                         if (input & inset_map_diff_x722[i].inset)
9224                                 val |= inset_map_diff_x722[i].inset_reg;
9225                 }
9226         } else {
9227                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9228                         if (input & inset_map_diff_not_x722[i].inset)
9229                                 val |= inset_map_diff_not_x722[i].inset_reg;
9230                 }
9231         }
9232
9233         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9234                 if (input & inset_map_common[i].inset)
9235                         val |= inset_map_common[i].inset_reg;
9236         }
9237
9238         return val;
9239 }
9240
9241 int
9242 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9243 {
9244         uint8_t i, idx = 0;
9245         uint64_t inset_need_mask = inset;
9246
9247         static const struct {
9248                 uint64_t inset;
9249                 uint32_t mask;
9250         } inset_mask_map[] = {
9251                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9252                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9253                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9254                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9255                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9256                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9257                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9258                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9259         };
9260
9261         if (!inset || !mask || !nb_elem)
9262                 return 0;
9263
9264         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9265                 /* Clear the inset bit, if no MASK is required,
9266                  * for example proto + ttl
9267                  */
9268                 if ((inset & inset_mask_map[i].inset) ==
9269                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9270                         inset_need_mask &= ~inset_mask_map[i].inset;
9271                 if (!inset_need_mask)
9272                         return 0;
9273         }
9274         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9275                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9276                     inset_mask_map[i].inset) {
9277                         if (idx >= nb_elem) {
9278                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9279                                 return -EINVAL;
9280                         }
9281                         mask[idx] = inset_mask_map[i].mask;
9282                         idx++;
9283                 }
9284         }
9285
9286         return idx;
9287 }
9288
9289 void
9290 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9291 {
9292         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9293
9294         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9295         if (reg != val)
9296                 i40e_write_rx_ctl(hw, addr, val);
9297         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9298                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9299 }
9300
9301 void
9302 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9303 {
9304         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9305         struct rte_eth_dev *dev;
9306
9307         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9308         if (reg != val) {
9309                 i40e_write_rx_ctl(hw, addr, val);
9310                 PMD_DRV_LOG(WARNING,
9311                             "i40e device %s changed global register [0x%08x]."
9312                             " original: 0x%08x, new: 0x%08x",
9313                             dev->device->name, addr, reg,
9314                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9315         }
9316 }
9317
9318 static void
9319 i40e_filter_input_set_init(struct i40e_pf *pf)
9320 {
9321         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9322         enum i40e_filter_pctype pctype;
9323         uint64_t input_set, inset_reg;
9324         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9325         int num, i;
9326         uint16_t flow_type;
9327
9328         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9329              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9330                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9331
9332                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9333                         continue;
9334
9335                 input_set = i40e_get_default_input_set(pctype);
9336
9337                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9338                                                    I40E_INSET_MASK_NUM_REG);
9339                 if (num < 0)
9340                         return;
9341                 if (pf->support_multi_driver && num > 0) {
9342                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9343                         return;
9344                 }
9345                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9346                                         input_set);
9347
9348                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9349                                       (uint32_t)(inset_reg & UINT32_MAX));
9350                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9351                                      (uint32_t)((inset_reg >>
9352                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9353                 if (!pf->support_multi_driver) {
9354                         i40e_check_write_global_reg(hw,
9355                                             I40E_GLQF_HASH_INSET(0, pctype),
9356                                             (uint32_t)(inset_reg & UINT32_MAX));
9357                         i40e_check_write_global_reg(hw,
9358                                              I40E_GLQF_HASH_INSET(1, pctype),
9359                                              (uint32_t)((inset_reg >>
9360                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9361
9362                         for (i = 0; i < num; i++) {
9363                                 i40e_check_write_global_reg(hw,
9364                                                     I40E_GLQF_FD_MSK(i, pctype),
9365                                                     mask_reg[i]);
9366                                 i40e_check_write_global_reg(hw,
9367                                                   I40E_GLQF_HASH_MSK(i, pctype),
9368                                                   mask_reg[i]);
9369                         }
9370                         /*clear unused mask registers of the pctype */
9371                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9372                                 i40e_check_write_global_reg(hw,
9373                                                     I40E_GLQF_FD_MSK(i, pctype),
9374                                                     0);
9375                                 i40e_check_write_global_reg(hw,
9376                                                   I40E_GLQF_HASH_MSK(i, pctype),
9377                                                   0);
9378                         }
9379                 } else {
9380                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9381                 }
9382                 I40E_WRITE_FLUSH(hw);
9383
9384                 /* store the default input set */
9385                 if (!pf->support_multi_driver)
9386                         pf->hash_input_set[pctype] = input_set;
9387                 pf->fdir.input_set[pctype] = input_set;
9388         }
9389 }
9390
9391 int
9392 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9393                          struct rte_eth_input_set_conf *conf)
9394 {
9395         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9396         enum i40e_filter_pctype pctype;
9397         uint64_t input_set, inset_reg = 0;
9398         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9399         int ret, i, num;
9400
9401         if (!conf) {
9402                 PMD_DRV_LOG(ERR, "Invalid pointer");
9403                 return -EFAULT;
9404         }
9405         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9406             conf->op != RTE_ETH_INPUT_SET_ADD) {
9407                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9408                 return -EINVAL;
9409         }
9410
9411         if (pf->support_multi_driver) {
9412                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9413                 return -ENOTSUP;
9414         }
9415
9416         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9417         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9418                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9419                 return -EINVAL;
9420         }
9421
9422         if (hw->mac.type == I40E_MAC_X722) {
9423                 /* get translated pctype value in fd pctype register */
9424                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9425                         I40E_GLQF_FD_PCTYPES((int)pctype));
9426         }
9427
9428         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9429                                    conf->inset_size);
9430         if (ret) {
9431                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9432                 return -EINVAL;
9433         }
9434
9435         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9436                 /* get inset value in register */
9437                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9438                 inset_reg <<= I40E_32_BIT_WIDTH;
9439                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9440                 input_set |= pf->hash_input_set[pctype];
9441         }
9442         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9443                                            I40E_INSET_MASK_NUM_REG);
9444         if (num < 0)
9445                 return -EINVAL;
9446
9447         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9448
9449         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9450                                     (uint32_t)(inset_reg & UINT32_MAX));
9451         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9452                                     (uint32_t)((inset_reg >>
9453                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9454
9455         for (i = 0; i < num; i++)
9456                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9457                                             mask_reg[i]);
9458         /*clear unused mask registers of the pctype */
9459         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9460                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9461                                             0);
9462         I40E_WRITE_FLUSH(hw);
9463
9464         pf->hash_input_set[pctype] = input_set;
9465         return 0;
9466 }
9467
9468 int
9469 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9470                          struct rte_eth_input_set_conf *conf)
9471 {
9472         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9473         enum i40e_filter_pctype pctype;
9474         uint64_t input_set, inset_reg = 0;
9475         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9476         int ret, i, num;
9477
9478         if (!hw || !conf) {
9479                 PMD_DRV_LOG(ERR, "Invalid pointer");
9480                 return -EFAULT;
9481         }
9482         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9483             conf->op != RTE_ETH_INPUT_SET_ADD) {
9484                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9485                 return -EINVAL;
9486         }
9487
9488         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9489
9490         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9491                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9492                 return -EINVAL;
9493         }
9494
9495         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9496                                    conf->inset_size);
9497         if (ret) {
9498                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9499                 return -EINVAL;
9500         }
9501
9502         /* get inset value in register */
9503         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9504         inset_reg <<= I40E_32_BIT_WIDTH;
9505         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9506
9507         /* Can not change the inset reg for flex payload for fdir,
9508          * it is done by writing I40E_PRTQF_FD_FLXINSET
9509          * in i40e_set_flex_mask_on_pctype.
9510          */
9511         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9512                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9513         else
9514                 input_set |= pf->fdir.input_set[pctype];
9515         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9516                                            I40E_INSET_MASK_NUM_REG);
9517         if (num < 0)
9518                 return -EINVAL;
9519         if (pf->support_multi_driver && num > 0) {
9520                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9521                 return -ENOTSUP;
9522         }
9523
9524         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9525
9526         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9527                               (uint32_t)(inset_reg & UINT32_MAX));
9528         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9529                              (uint32_t)((inset_reg >>
9530                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9531
9532         if (!pf->support_multi_driver) {
9533                 for (i = 0; i < num; i++)
9534                         i40e_check_write_global_reg(hw,
9535                                                     I40E_GLQF_FD_MSK(i, pctype),
9536                                                     mask_reg[i]);
9537                 /*clear unused mask registers of the pctype */
9538                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9539                         i40e_check_write_global_reg(hw,
9540                                                     I40E_GLQF_FD_MSK(i, pctype),
9541                                                     0);
9542         } else {
9543                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9544         }
9545         I40E_WRITE_FLUSH(hw);
9546
9547         pf->fdir.input_set[pctype] = input_set;
9548         return 0;
9549 }
9550
9551 static int
9552 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9553 {
9554         int ret = 0;
9555
9556         if (!hw || !info) {
9557                 PMD_DRV_LOG(ERR, "Invalid pointer");
9558                 return -EFAULT;
9559         }
9560
9561         switch (info->info_type) {
9562         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9563                 i40e_get_symmetric_hash_enable_per_port(hw,
9564                                         &(info->info.enable));
9565                 break;
9566         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9567                 ret = i40e_get_hash_filter_global_config(hw,
9568                                 &(info->info.global_conf));
9569                 break;
9570         default:
9571                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9572                                                         info->info_type);
9573                 ret = -EINVAL;
9574                 break;
9575         }
9576
9577         return ret;
9578 }
9579
9580 static int
9581 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9582 {
9583         int ret = 0;
9584
9585         if (!hw || !info) {
9586                 PMD_DRV_LOG(ERR, "Invalid pointer");
9587                 return -EFAULT;
9588         }
9589
9590         switch (info->info_type) {
9591         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9592                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9593                 break;
9594         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9595                 ret = i40e_set_hash_filter_global_config(hw,
9596                                 &(info->info.global_conf));
9597                 break;
9598         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9599                 ret = i40e_hash_filter_inset_select(hw,
9600                                                &(info->info.input_set_conf));
9601                 break;
9602
9603         default:
9604                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9605                                                         info->info_type);
9606                 ret = -EINVAL;
9607                 break;
9608         }
9609
9610         return ret;
9611 }
9612
9613 /* Operations for hash function */
9614 static int
9615 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9616                       enum rte_filter_op filter_op,
9617                       void *arg)
9618 {
9619         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9620         int ret = 0;
9621
9622         switch (filter_op) {
9623         case RTE_ETH_FILTER_NOP:
9624                 break;
9625         case RTE_ETH_FILTER_GET:
9626                 ret = i40e_hash_filter_get(hw,
9627                         (struct rte_eth_hash_filter_info *)arg);
9628                 break;
9629         case RTE_ETH_FILTER_SET:
9630                 ret = i40e_hash_filter_set(hw,
9631                         (struct rte_eth_hash_filter_info *)arg);
9632                 break;
9633         default:
9634                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9635                                                                 filter_op);
9636                 ret = -ENOTSUP;
9637                 break;
9638         }
9639
9640         return ret;
9641 }
9642
9643 /* Convert ethertype filter structure */
9644 static int
9645 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9646                               struct i40e_ethertype_filter *filter)
9647 {
9648         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9649         filter->input.ether_type = input->ether_type;
9650         filter->flags = input->flags;
9651         filter->queue = input->queue;
9652
9653         return 0;
9654 }
9655
9656 /* Check if there exists the ehtertype filter */
9657 struct i40e_ethertype_filter *
9658 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9659                                 const struct i40e_ethertype_filter_input *input)
9660 {
9661         int ret;
9662
9663         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9664         if (ret < 0)
9665                 return NULL;
9666
9667         return ethertype_rule->hash_map[ret];
9668 }
9669
9670 /* Add ethertype filter in SW list */
9671 static int
9672 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9673                                 struct i40e_ethertype_filter *filter)
9674 {
9675         struct i40e_ethertype_rule *rule = &pf->ethertype;
9676         int ret;
9677
9678         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9679         if (ret < 0) {
9680                 PMD_DRV_LOG(ERR,
9681                             "Failed to insert ethertype filter"
9682                             " to hash table %d!",
9683                             ret);
9684                 return ret;
9685         }
9686         rule->hash_map[ret] = filter;
9687
9688         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9689
9690         return 0;
9691 }
9692
9693 /* Delete ethertype filter in SW list */
9694 int
9695 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9696                              struct i40e_ethertype_filter_input *input)
9697 {
9698         struct i40e_ethertype_rule *rule = &pf->ethertype;
9699         struct i40e_ethertype_filter *filter;
9700         int ret;
9701
9702         ret = rte_hash_del_key(rule->hash_table, input);
9703         if (ret < 0) {
9704                 PMD_DRV_LOG(ERR,
9705                             "Failed to delete ethertype filter"
9706                             " to hash table %d!",
9707                             ret);
9708                 return ret;
9709         }
9710         filter = rule->hash_map[ret];
9711         rule->hash_map[ret] = NULL;
9712
9713         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9714         rte_free(filter);
9715
9716         return 0;
9717 }
9718
9719 /*
9720  * Configure ethertype filter, which can director packet by filtering
9721  * with mac address and ether_type or only ether_type
9722  */
9723 int
9724 i40e_ethertype_filter_set(struct i40e_pf *pf,
9725                         struct rte_eth_ethertype_filter *filter,
9726                         bool add)
9727 {
9728         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9729         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9730         struct i40e_ethertype_filter *ethertype_filter, *node;
9731         struct i40e_ethertype_filter check_filter;
9732         struct i40e_control_filter_stats stats;
9733         uint16_t flags = 0;
9734         int ret;
9735
9736         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9737                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9738                 return -EINVAL;
9739         }
9740         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9741                 filter->ether_type == ETHER_TYPE_IPv6) {
9742                 PMD_DRV_LOG(ERR,
9743                         "unsupported ether_type(0x%04x) in control packet filter.",
9744                         filter->ether_type);
9745                 return -EINVAL;
9746         }
9747         if (filter->ether_type == ETHER_TYPE_VLAN)
9748                 PMD_DRV_LOG(WARNING,
9749                         "filter vlan ether_type in first tag is not supported.");
9750
9751         /* Check if there is the filter in SW list */
9752         memset(&check_filter, 0, sizeof(check_filter));
9753         i40e_ethertype_filter_convert(filter, &check_filter);
9754         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9755                                                &check_filter.input);
9756         if (add && node) {
9757                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9758                 return -EINVAL;
9759         }
9760
9761         if (!add && !node) {
9762                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9763                 return -EINVAL;
9764         }
9765
9766         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9767                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9768         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9769                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9770         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9771
9772         memset(&stats, 0, sizeof(stats));
9773         ret = i40e_aq_add_rem_control_packet_filter(hw,
9774                         filter->mac_addr.addr_bytes,
9775                         filter->ether_type, flags,
9776                         pf->main_vsi->seid,
9777                         filter->queue, add, &stats, NULL);
9778
9779         PMD_DRV_LOG(INFO,
9780                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9781                 ret, stats.mac_etype_used, stats.etype_used,
9782                 stats.mac_etype_free, stats.etype_free);
9783         if (ret < 0)
9784                 return -ENOSYS;
9785
9786         /* Add or delete a filter in SW list */
9787         if (add) {
9788                 ethertype_filter = rte_zmalloc("ethertype_filter",
9789                                        sizeof(*ethertype_filter), 0);
9790                 if (ethertype_filter == NULL) {
9791                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9792                         return -ENOMEM;
9793                 }
9794
9795                 rte_memcpy(ethertype_filter, &check_filter,
9796                            sizeof(check_filter));
9797                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9798                 if (ret < 0)
9799                         rte_free(ethertype_filter);
9800         } else {
9801                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9802         }
9803
9804         return ret;
9805 }
9806
9807 /*
9808  * Handle operations for ethertype filter.
9809  */
9810 static int
9811 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9812                                 enum rte_filter_op filter_op,
9813                                 void *arg)
9814 {
9815         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9816         int ret = 0;
9817
9818         if (filter_op == RTE_ETH_FILTER_NOP)
9819                 return ret;
9820
9821         if (arg == NULL) {
9822                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9823                             filter_op);
9824                 return -EINVAL;
9825         }
9826
9827         switch (filter_op) {
9828         case RTE_ETH_FILTER_ADD:
9829                 ret = i40e_ethertype_filter_set(pf,
9830                         (struct rte_eth_ethertype_filter *)arg,
9831                         TRUE);
9832                 break;
9833         case RTE_ETH_FILTER_DELETE:
9834                 ret = i40e_ethertype_filter_set(pf,
9835                         (struct rte_eth_ethertype_filter *)arg,
9836                         FALSE);
9837                 break;
9838         default:
9839                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9840                 ret = -ENOSYS;
9841                 break;
9842         }
9843         return ret;
9844 }
9845
9846 static int
9847 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9848                      enum rte_filter_type filter_type,
9849                      enum rte_filter_op filter_op,
9850                      void *arg)
9851 {
9852         int ret = 0;
9853
9854         if (dev == NULL)
9855                 return -EINVAL;
9856
9857         switch (filter_type) {
9858         case RTE_ETH_FILTER_NONE:
9859                 /* For global configuration */
9860                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9861                 break;
9862         case RTE_ETH_FILTER_HASH:
9863                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9864                 break;
9865         case RTE_ETH_FILTER_MACVLAN:
9866                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9867                 break;
9868         case RTE_ETH_FILTER_ETHERTYPE:
9869                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9870                 break;
9871         case RTE_ETH_FILTER_TUNNEL:
9872                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9873                 break;
9874         case RTE_ETH_FILTER_FDIR:
9875                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9876                 break;
9877         case RTE_ETH_FILTER_GENERIC:
9878                 if (filter_op != RTE_ETH_FILTER_GET)
9879                         return -EINVAL;
9880                 *(const void **)arg = &i40e_flow_ops;
9881                 break;
9882         default:
9883                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9884                                                         filter_type);
9885                 ret = -EINVAL;
9886                 break;
9887         }
9888
9889         return ret;
9890 }
9891
9892 /*
9893  * Check and enable Extended Tag.
9894  * Enabling Extended Tag is important for 40G performance.
9895  */
9896 static void
9897 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9898 {
9899         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9900         uint32_t buf = 0;
9901         int ret;
9902
9903         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9904                                       PCI_DEV_CAP_REG);
9905         if (ret < 0) {
9906                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9907                             PCI_DEV_CAP_REG);
9908                 return;
9909         }
9910         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9911                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9912                 return;
9913         }
9914
9915         buf = 0;
9916         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9917                                       PCI_DEV_CTRL_REG);
9918         if (ret < 0) {
9919                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9920                             PCI_DEV_CTRL_REG);
9921                 return;
9922         }
9923         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9924                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9925                 return;
9926         }
9927         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9928         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9929                                        PCI_DEV_CTRL_REG);
9930         if (ret < 0) {
9931                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9932                             PCI_DEV_CTRL_REG);
9933                 return;
9934         }
9935 }
9936
9937 /*
9938  * As some registers wouldn't be reset unless a global hardware reset,
9939  * hardware initialization is needed to put those registers into an
9940  * expected initial state.
9941  */
9942 static void
9943 i40e_hw_init(struct rte_eth_dev *dev)
9944 {
9945         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9946
9947         i40e_enable_extended_tag(dev);
9948
9949         /* clear the PF Queue Filter control register */
9950         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9951
9952         /* Disable symmetric hash per port */
9953         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9954 }
9955
9956 /*
9957  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9958  * however this function will return only one highest pctype index,
9959  * which is not quite correct. This is known problem of i40e driver
9960  * and needs to be fixed later.
9961  */
9962 enum i40e_filter_pctype
9963 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9964 {
9965         int i;
9966         uint64_t pctype_mask;
9967
9968         if (flow_type < I40E_FLOW_TYPE_MAX) {
9969                 pctype_mask = adapter->pctypes_tbl[flow_type];
9970                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9971                         if (pctype_mask & (1ULL << i))
9972                                 return (enum i40e_filter_pctype)i;
9973                 }
9974         }
9975         return I40E_FILTER_PCTYPE_INVALID;
9976 }
9977
9978 uint16_t
9979 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9980                         enum i40e_filter_pctype pctype)
9981 {
9982         uint16_t flowtype;
9983         uint64_t pctype_mask = 1ULL << pctype;
9984
9985         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9986              flowtype++) {
9987                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9988                         return flowtype;
9989         }
9990
9991         return RTE_ETH_FLOW_UNKNOWN;
9992 }
9993
9994 /*
9995  * On X710, performance number is far from the expectation on recent firmware
9996  * versions; on XL710, performance number is also far from the expectation on
9997  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9998  * mode is enabled and port MAC address is equal to the packet destination MAC
9999  * address. The fix for this issue may not be integrated in the following
10000  * firmware version. So the workaround in software driver is needed. It needs
10001  * to modify the initial values of 3 internal only registers for both X710 and
10002  * XL710. Note that the values for X710 or XL710 could be different, and the
10003  * workaround can be removed when it is fixed in firmware in the future.
10004  */
10005
10006 /* For both X710 and XL710 */
10007 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10008 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10009 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10010
10011 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10012 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10013
10014 /* For X722 */
10015 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10016 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10017
10018 /* For X710 */
10019 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10020 /* For XL710 */
10021 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10022 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10023
10024 /*
10025  * GL_SWR_PM_UP_THR:
10026  * The value is not impacted from the link speed, its value is set according
10027  * to the total number of ports for a better pipe-monitor configuration.
10028  */
10029 static bool
10030 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10031 {
10032 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10033                 .device_id = (dev),   \
10034                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10035
10036 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10037                 .device_id = (dev),   \
10038                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10039
10040         static const struct {
10041                 uint16_t device_id;
10042                 uint32_t val;
10043         } swr_pm_table[] = {
10044                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10045                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10046                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10047                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10048
10049                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10050                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10051                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10052                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10053                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10054                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10055                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10056         };
10057         uint32_t i;
10058
10059         if (value == NULL) {
10060                 PMD_DRV_LOG(ERR, "value is NULL");
10061                 return false;
10062         }
10063
10064         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10065                 if (hw->device_id == swr_pm_table[i].device_id) {
10066                         *value = swr_pm_table[i].val;
10067
10068                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10069                                     "value - 0x%08x",
10070                                     hw->device_id, *value);
10071                         return true;
10072                 }
10073         }
10074
10075         return false;
10076 }
10077
10078 static int
10079 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10080 {
10081         enum i40e_status_code status;
10082         struct i40e_aq_get_phy_abilities_resp phy_ab;
10083         int ret = -ENOTSUP;
10084         int retries = 0;
10085
10086         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10087                                               NULL);
10088
10089         while (status) {
10090                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10091                         status);
10092                 retries++;
10093                 rte_delay_us(100000);
10094                 if  (retries < 5)
10095                         status = i40e_aq_get_phy_capabilities(hw, false,
10096                                         true, &phy_ab, NULL);
10097                 else
10098                         return ret;
10099         }
10100         return 0;
10101 }
10102
10103 static void
10104 i40e_configure_registers(struct i40e_hw *hw)
10105 {
10106         static struct {
10107                 uint32_t addr;
10108                 uint64_t val;
10109         } reg_table[] = {
10110                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10111                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10112                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10113         };
10114         uint64_t reg;
10115         uint32_t i;
10116         int ret;
10117
10118         for (i = 0; i < RTE_DIM(reg_table); i++) {
10119                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10120                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10121                                 reg_table[i].val =
10122                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10123                         else /* For X710/XL710/XXV710 */
10124                                 if (hw->aq.fw_maj_ver < 6)
10125                                         reg_table[i].val =
10126                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10127                                 else
10128                                         reg_table[i].val =
10129                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10130                 }
10131
10132                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10133                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10134                                 reg_table[i].val =
10135                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10136                         else /* For X710/XL710/XXV710 */
10137                                 reg_table[i].val =
10138                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10139                 }
10140
10141                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10142                         uint32_t cfg_val;
10143
10144                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10145                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10146                                             "GL_SWR_PM_UP_THR value fixup",
10147                                             hw->device_id);
10148                                 continue;
10149                         }
10150
10151                         reg_table[i].val = cfg_val;
10152                 }
10153
10154                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10155                                                         &reg, NULL);
10156                 if (ret < 0) {
10157                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10158                                                         reg_table[i].addr);
10159                         break;
10160                 }
10161                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10162                                                 reg_table[i].addr, reg);
10163                 if (reg == reg_table[i].val)
10164                         continue;
10165
10166                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10167                                                 reg_table[i].val, NULL);
10168                 if (ret < 0) {
10169                         PMD_DRV_LOG(ERR,
10170                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10171                                 reg_table[i].val, reg_table[i].addr);
10172                         break;
10173                 }
10174                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10175                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10176         }
10177 }
10178
10179 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10180 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10181 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10182 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10183 static int
10184 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10185 {
10186         uint32_t reg;
10187         int ret;
10188
10189         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10190                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10191                 return -EINVAL;
10192         }
10193
10194         /* Configure for double VLAN RX stripping */
10195         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10196         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10197                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10198                 ret = i40e_aq_debug_write_register(hw,
10199                                                    I40E_VSI_TSR(vsi->vsi_id),
10200                                                    reg, NULL);
10201                 if (ret < 0) {
10202                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10203                                     vsi->vsi_id);
10204                         return I40E_ERR_CONFIG;
10205                 }
10206         }
10207
10208         /* Configure for double VLAN TX insertion */
10209         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10210         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10211                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10212                 ret = i40e_aq_debug_write_register(hw,
10213                                                    I40E_VSI_L2TAGSTXVALID(
10214                                                    vsi->vsi_id), reg, NULL);
10215                 if (ret < 0) {
10216                         PMD_DRV_LOG(ERR,
10217                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10218                                 vsi->vsi_id);
10219                         return I40E_ERR_CONFIG;
10220                 }
10221         }
10222
10223         return 0;
10224 }
10225
10226 /**
10227  * i40e_aq_add_mirror_rule
10228  * @hw: pointer to the hardware structure
10229  * @seid: VEB seid to add mirror rule to
10230  * @dst_id: destination vsi seid
10231  * @entries: Buffer which contains the entities to be mirrored
10232  * @count: number of entities contained in the buffer
10233  * @rule_id:the rule_id of the rule to be added
10234  *
10235  * Add a mirror rule for a given veb.
10236  *
10237  **/
10238 static enum i40e_status_code
10239 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10240                         uint16_t seid, uint16_t dst_id,
10241                         uint16_t rule_type, uint16_t *entries,
10242                         uint16_t count, uint16_t *rule_id)
10243 {
10244         struct i40e_aq_desc desc;
10245         struct i40e_aqc_add_delete_mirror_rule cmd;
10246         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10247                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10248                 &desc.params.raw;
10249         uint16_t buff_len;
10250         enum i40e_status_code status;
10251
10252         i40e_fill_default_direct_cmd_desc(&desc,
10253                                           i40e_aqc_opc_add_mirror_rule);
10254         memset(&cmd, 0, sizeof(cmd));
10255
10256         buff_len = sizeof(uint16_t) * count;
10257         desc.datalen = rte_cpu_to_le_16(buff_len);
10258         if (buff_len > 0)
10259                 desc.flags |= rte_cpu_to_le_16(
10260                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10261         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10262                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10263         cmd.num_entries = rte_cpu_to_le_16(count);
10264         cmd.seid = rte_cpu_to_le_16(seid);
10265         cmd.destination = rte_cpu_to_le_16(dst_id);
10266
10267         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10268         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10269         PMD_DRV_LOG(INFO,
10270                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10271                 hw->aq.asq_last_status, resp->rule_id,
10272                 resp->mirror_rules_used, resp->mirror_rules_free);
10273         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10274
10275         return status;
10276 }
10277
10278 /**
10279  * i40e_aq_del_mirror_rule
10280  * @hw: pointer to the hardware structure
10281  * @seid: VEB seid to add mirror rule to
10282  * @entries: Buffer which contains the entities to be mirrored
10283  * @count: number of entities contained in the buffer
10284  * @rule_id:the rule_id of the rule to be delete
10285  *
10286  * Delete a mirror rule for a given veb.
10287  *
10288  **/
10289 static enum i40e_status_code
10290 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10291                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10292                 uint16_t count, uint16_t rule_id)
10293 {
10294         struct i40e_aq_desc desc;
10295         struct i40e_aqc_add_delete_mirror_rule cmd;
10296         uint16_t buff_len = 0;
10297         enum i40e_status_code status;
10298         void *buff = NULL;
10299
10300         i40e_fill_default_direct_cmd_desc(&desc,
10301                                           i40e_aqc_opc_delete_mirror_rule);
10302         memset(&cmd, 0, sizeof(cmd));
10303         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10304                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10305                                                           I40E_AQ_FLAG_RD));
10306                 cmd.num_entries = count;
10307                 buff_len = sizeof(uint16_t) * count;
10308                 desc.datalen = rte_cpu_to_le_16(buff_len);
10309                 buff = (void *)entries;
10310         } else
10311                 /* rule id is filled in destination field for deleting mirror rule */
10312                 cmd.destination = rte_cpu_to_le_16(rule_id);
10313
10314         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10315                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10316         cmd.seid = rte_cpu_to_le_16(seid);
10317
10318         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10319         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10320
10321         return status;
10322 }
10323
10324 /**
10325  * i40e_mirror_rule_set
10326  * @dev: pointer to the hardware structure
10327  * @mirror_conf: mirror rule info
10328  * @sw_id: mirror rule's sw_id
10329  * @on: enable/disable
10330  *
10331  * set a mirror rule.
10332  *
10333  **/
10334 static int
10335 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10336                         struct rte_eth_mirror_conf *mirror_conf,
10337                         uint8_t sw_id, uint8_t on)
10338 {
10339         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10340         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10341         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10342         struct i40e_mirror_rule *parent = NULL;
10343         uint16_t seid, dst_seid, rule_id;
10344         uint16_t i, j = 0;
10345         int ret;
10346
10347         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10348
10349         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10350                 PMD_DRV_LOG(ERR,
10351                         "mirror rule can not be configured without veb or vfs.");
10352                 return -ENOSYS;
10353         }
10354         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10355                 PMD_DRV_LOG(ERR, "mirror table is full.");
10356                 return -ENOSPC;
10357         }
10358         if (mirror_conf->dst_pool > pf->vf_num) {
10359                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10360                                  mirror_conf->dst_pool);
10361                 return -EINVAL;
10362         }
10363
10364         seid = pf->main_vsi->veb->seid;
10365
10366         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10367                 if (sw_id <= it->index) {
10368                         mirr_rule = it;
10369                         break;
10370                 }
10371                 parent = it;
10372         }
10373         if (mirr_rule && sw_id == mirr_rule->index) {
10374                 if (on) {
10375                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10376                         return -EEXIST;
10377                 } else {
10378                         ret = i40e_aq_del_mirror_rule(hw, seid,
10379                                         mirr_rule->rule_type,
10380                                         mirr_rule->entries,
10381                                         mirr_rule->num_entries, mirr_rule->id);
10382                         if (ret < 0) {
10383                                 PMD_DRV_LOG(ERR,
10384                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10385                                         ret, hw->aq.asq_last_status);
10386                                 return -ENOSYS;
10387                         }
10388                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10389                         rte_free(mirr_rule);
10390                         pf->nb_mirror_rule--;
10391                         return 0;
10392                 }
10393         } else if (!on) {
10394                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10395                 return -ENOENT;
10396         }
10397
10398         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10399                                 sizeof(struct i40e_mirror_rule) , 0);
10400         if (!mirr_rule) {
10401                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10402                 return I40E_ERR_NO_MEMORY;
10403         }
10404         switch (mirror_conf->rule_type) {
10405         case ETH_MIRROR_VLAN:
10406                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10407                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10408                                 mirr_rule->entries[j] =
10409                                         mirror_conf->vlan.vlan_id[i];
10410                                 j++;
10411                         }
10412                 }
10413                 if (j == 0) {
10414                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10415                         rte_free(mirr_rule);
10416                         return -EINVAL;
10417                 }
10418                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10419                 break;
10420         case ETH_MIRROR_VIRTUAL_POOL_UP:
10421         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10422                 /* check if the specified pool bit is out of range */
10423                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10424                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10425                         rte_free(mirr_rule);
10426                         return -EINVAL;
10427                 }
10428                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10429                         if (mirror_conf->pool_mask & (1ULL << i)) {
10430                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10431                                 j++;
10432                         }
10433                 }
10434                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10435                         /* add pf vsi to entries */
10436                         mirr_rule->entries[j] = pf->main_vsi_seid;
10437                         j++;
10438                 }
10439                 if (j == 0) {
10440                         PMD_DRV_LOG(ERR, "pool is not specified.");
10441                         rte_free(mirr_rule);
10442                         return -EINVAL;
10443                 }
10444                 /* egress and ingress in aq commands means from switch but not port */
10445                 mirr_rule->rule_type =
10446                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10447                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10448                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10449                 break;
10450         case ETH_MIRROR_UPLINK_PORT:
10451                 /* egress and ingress in aq commands means from switch but not port*/
10452                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10453                 break;
10454         case ETH_MIRROR_DOWNLINK_PORT:
10455                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10456                 break;
10457         default:
10458                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10459                         mirror_conf->rule_type);
10460                 rte_free(mirr_rule);
10461                 return -EINVAL;
10462         }
10463
10464         /* If the dst_pool is equal to vf_num, consider it as PF */
10465         if (mirror_conf->dst_pool == pf->vf_num)
10466                 dst_seid = pf->main_vsi_seid;
10467         else
10468                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10469
10470         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10471                                       mirr_rule->rule_type, mirr_rule->entries,
10472                                       j, &rule_id);
10473         if (ret < 0) {
10474                 PMD_DRV_LOG(ERR,
10475                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10476                         ret, hw->aq.asq_last_status);
10477                 rte_free(mirr_rule);
10478                 return -ENOSYS;
10479         }
10480
10481         mirr_rule->index = sw_id;
10482         mirr_rule->num_entries = j;
10483         mirr_rule->id = rule_id;
10484         mirr_rule->dst_vsi_seid = dst_seid;
10485
10486         if (parent)
10487                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10488         else
10489                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10490
10491         pf->nb_mirror_rule++;
10492         return 0;
10493 }
10494
10495 /**
10496  * i40e_mirror_rule_reset
10497  * @dev: pointer to the device
10498  * @sw_id: mirror rule's sw_id
10499  *
10500  * reset a mirror rule.
10501  *
10502  **/
10503 static int
10504 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10505 {
10506         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10507         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10508         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10509         uint16_t seid;
10510         int ret;
10511
10512         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10513
10514         seid = pf->main_vsi->veb->seid;
10515
10516         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10517                 if (sw_id == it->index) {
10518                         mirr_rule = it;
10519                         break;
10520                 }
10521         }
10522         if (mirr_rule) {
10523                 ret = i40e_aq_del_mirror_rule(hw, seid,
10524                                 mirr_rule->rule_type,
10525                                 mirr_rule->entries,
10526                                 mirr_rule->num_entries, mirr_rule->id);
10527                 if (ret < 0) {
10528                         PMD_DRV_LOG(ERR,
10529                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10530                                 ret, hw->aq.asq_last_status);
10531                         return -ENOSYS;
10532                 }
10533                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10534                 rte_free(mirr_rule);
10535                 pf->nb_mirror_rule--;
10536         } else {
10537                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10538                 return -ENOENT;
10539         }
10540         return 0;
10541 }
10542
10543 static uint64_t
10544 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10545 {
10546         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10547         uint64_t systim_cycles;
10548
10549         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10550         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10551                         << 32;
10552
10553         return systim_cycles;
10554 }
10555
10556 static uint64_t
10557 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10558 {
10559         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10560         uint64_t rx_tstamp;
10561
10562         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10563         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10564                         << 32;
10565
10566         return rx_tstamp;
10567 }
10568
10569 static uint64_t
10570 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10571 {
10572         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10573         uint64_t tx_tstamp;
10574
10575         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10576         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10577                         << 32;
10578
10579         return tx_tstamp;
10580 }
10581
10582 static void
10583 i40e_start_timecounters(struct rte_eth_dev *dev)
10584 {
10585         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10586         struct i40e_adapter *adapter =
10587                         (struct i40e_adapter *)dev->data->dev_private;
10588         struct rte_eth_link link;
10589         uint32_t tsync_inc_l;
10590         uint32_t tsync_inc_h;
10591
10592         /* Get current link speed. */
10593         i40e_dev_link_update(dev, 1);
10594         rte_eth_linkstatus_get(dev, &link);
10595
10596         switch (link.link_speed) {
10597         case ETH_SPEED_NUM_40G:
10598                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10599                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10600                 break;
10601         case ETH_SPEED_NUM_10G:
10602                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10603                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10604                 break;
10605         case ETH_SPEED_NUM_1G:
10606                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10607                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10608                 break;
10609         default:
10610                 tsync_inc_l = 0x0;
10611                 tsync_inc_h = 0x0;
10612         }
10613
10614         /* Set the timesync increment value. */
10615         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10616         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10617
10618         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10619         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10620         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10621
10622         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10623         adapter->systime_tc.cc_shift = 0;
10624         adapter->systime_tc.nsec_mask = 0;
10625
10626         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10627         adapter->rx_tstamp_tc.cc_shift = 0;
10628         adapter->rx_tstamp_tc.nsec_mask = 0;
10629
10630         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10631         adapter->tx_tstamp_tc.cc_shift = 0;
10632         adapter->tx_tstamp_tc.nsec_mask = 0;
10633 }
10634
10635 static int
10636 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10637 {
10638         struct i40e_adapter *adapter =
10639                         (struct i40e_adapter *)dev->data->dev_private;
10640
10641         adapter->systime_tc.nsec += delta;
10642         adapter->rx_tstamp_tc.nsec += delta;
10643         adapter->tx_tstamp_tc.nsec += delta;
10644
10645         return 0;
10646 }
10647
10648 static int
10649 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10650 {
10651         uint64_t ns;
10652         struct i40e_adapter *adapter =
10653                         (struct i40e_adapter *)dev->data->dev_private;
10654
10655         ns = rte_timespec_to_ns(ts);
10656
10657         /* Set the timecounters to a new value. */
10658         adapter->systime_tc.nsec = ns;
10659         adapter->rx_tstamp_tc.nsec = ns;
10660         adapter->tx_tstamp_tc.nsec = ns;
10661
10662         return 0;
10663 }
10664
10665 static int
10666 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10667 {
10668         uint64_t ns, systime_cycles;
10669         struct i40e_adapter *adapter =
10670                         (struct i40e_adapter *)dev->data->dev_private;
10671
10672         systime_cycles = i40e_read_systime_cyclecounter(dev);
10673         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10674         *ts = rte_ns_to_timespec(ns);
10675
10676         return 0;
10677 }
10678
10679 static int
10680 i40e_timesync_enable(struct rte_eth_dev *dev)
10681 {
10682         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10683         uint32_t tsync_ctl_l;
10684         uint32_t tsync_ctl_h;
10685
10686         /* Stop the timesync system time. */
10687         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10688         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10689         /* Reset the timesync system time value. */
10690         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10691         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10692
10693         i40e_start_timecounters(dev);
10694
10695         /* Clear timesync registers. */
10696         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10697         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10698         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10699         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10700         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10701         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10702
10703         /* Enable timestamping of PTP packets. */
10704         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10705         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10706
10707         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10708         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10709         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10710
10711         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10712         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10713
10714         return 0;
10715 }
10716
10717 static int
10718 i40e_timesync_disable(struct rte_eth_dev *dev)
10719 {
10720         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10721         uint32_t tsync_ctl_l;
10722         uint32_t tsync_ctl_h;
10723
10724         /* Disable timestamping of transmitted PTP packets. */
10725         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10726         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10727
10728         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10729         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10730
10731         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10732         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10733
10734         /* Reset the timesync increment value. */
10735         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10736         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10737
10738         return 0;
10739 }
10740
10741 static int
10742 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10743                                 struct timespec *timestamp, uint32_t flags)
10744 {
10745         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10746         struct i40e_adapter *adapter =
10747                 (struct i40e_adapter *)dev->data->dev_private;
10748
10749         uint32_t sync_status;
10750         uint32_t index = flags & 0x03;
10751         uint64_t rx_tstamp_cycles;
10752         uint64_t ns;
10753
10754         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10755         if ((sync_status & (1 << index)) == 0)
10756                 return -EINVAL;
10757
10758         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10759         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10760         *timestamp = rte_ns_to_timespec(ns);
10761
10762         return 0;
10763 }
10764
10765 static int
10766 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10767                                 struct timespec *timestamp)
10768 {
10769         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10770         struct i40e_adapter *adapter =
10771                 (struct i40e_adapter *)dev->data->dev_private;
10772
10773         uint32_t sync_status;
10774         uint64_t tx_tstamp_cycles;
10775         uint64_t ns;
10776
10777         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10778         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10779                 return -EINVAL;
10780
10781         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10782         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10783         *timestamp = rte_ns_to_timespec(ns);
10784
10785         return 0;
10786 }
10787
10788 /*
10789  * i40e_parse_dcb_configure - parse dcb configure from user
10790  * @dev: the device being configured
10791  * @dcb_cfg: pointer of the result of parse
10792  * @*tc_map: bit map of enabled traffic classes
10793  *
10794  * Returns 0 on success, negative value on failure
10795  */
10796 static int
10797 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10798                          struct i40e_dcbx_config *dcb_cfg,
10799                          uint8_t *tc_map)
10800 {
10801         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10802         uint8_t i, tc_bw, bw_lf;
10803
10804         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10805
10806         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10807         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10808                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10809                 return -EINVAL;
10810         }
10811
10812         /* assume each tc has the same bw */
10813         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10814         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10815                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10816         /* to ensure the sum of tcbw is equal to 100 */
10817         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10818         for (i = 0; i < bw_lf; i++)
10819                 dcb_cfg->etscfg.tcbwtable[i]++;
10820
10821         /* assume each tc has the same Transmission Selection Algorithm */
10822         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10823                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10824
10825         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10826                 dcb_cfg->etscfg.prioritytable[i] =
10827                                 dcb_rx_conf->dcb_tc[i];
10828
10829         /* FW needs one App to configure HW */
10830         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10831         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10832         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10833         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10834
10835         if (dcb_rx_conf->nb_tcs == 0)
10836                 *tc_map = 1; /* tc0 only */
10837         else
10838                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10839
10840         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10841                 dcb_cfg->pfc.willing = 0;
10842                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10843                 dcb_cfg->pfc.pfcenable = *tc_map;
10844         }
10845         return 0;
10846 }
10847
10848
10849 static enum i40e_status_code
10850 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10851                               struct i40e_aqc_vsi_properties_data *info,
10852                               uint8_t enabled_tcmap)
10853 {
10854         enum i40e_status_code ret;
10855         int i, total_tc = 0;
10856         uint16_t qpnum_per_tc, bsf, qp_idx;
10857         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10858         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10859         uint16_t used_queues;
10860
10861         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10862         if (ret != I40E_SUCCESS)
10863                 return ret;
10864
10865         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10866                 if (enabled_tcmap & (1 << i))
10867                         total_tc++;
10868         }
10869         if (total_tc == 0)
10870                 total_tc = 1;
10871         vsi->enabled_tc = enabled_tcmap;
10872
10873         /* different VSI has different queues assigned */
10874         if (vsi->type == I40E_VSI_MAIN)
10875                 used_queues = dev_data->nb_rx_queues -
10876                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10877         else if (vsi->type == I40E_VSI_VMDQ2)
10878                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10879         else {
10880                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10881                 return I40E_ERR_NO_AVAILABLE_VSI;
10882         }
10883
10884         qpnum_per_tc = used_queues / total_tc;
10885         /* Number of queues per enabled TC */
10886         if (qpnum_per_tc == 0) {
10887                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10888                 return I40E_ERR_INVALID_QP_ID;
10889         }
10890         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10891                                 I40E_MAX_Q_PER_TC);
10892         bsf = rte_bsf32(qpnum_per_tc);
10893
10894         /**
10895          * Configure TC and queue mapping parameters, for enabled TC,
10896          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10897          * default queue will serve it.
10898          */
10899         qp_idx = 0;
10900         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10901                 if (vsi->enabled_tc & (1 << i)) {
10902                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10903                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10904                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10905                         qp_idx += qpnum_per_tc;
10906                 } else
10907                         info->tc_mapping[i] = 0;
10908         }
10909
10910         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10911         if (vsi->type == I40E_VSI_SRIOV) {
10912                 info->mapping_flags |=
10913                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10914                 for (i = 0; i < vsi->nb_qps; i++)
10915                         info->queue_mapping[i] =
10916                                 rte_cpu_to_le_16(vsi->base_queue + i);
10917         } else {
10918                 info->mapping_flags |=
10919                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10920                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10921         }
10922         info->valid_sections |=
10923                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10924
10925         return I40E_SUCCESS;
10926 }
10927
10928 /*
10929  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10930  * @veb: VEB to be configured
10931  * @tc_map: enabled TC bitmap
10932  *
10933  * Returns 0 on success, negative value on failure
10934  */
10935 static enum i40e_status_code
10936 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10937 {
10938         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10939         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10940         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10941         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10942         enum i40e_status_code ret = I40E_SUCCESS;
10943         int i;
10944         uint32_t bw_max;
10945
10946         /* Check if enabled_tc is same as existing or new TCs */
10947         if (veb->enabled_tc == tc_map)
10948                 return ret;
10949
10950         /* configure tc bandwidth */
10951         memset(&veb_bw, 0, sizeof(veb_bw));
10952         veb_bw.tc_valid_bits = tc_map;
10953         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10954         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10955                 if (tc_map & BIT_ULL(i))
10956                         veb_bw.tc_bw_share_credits[i] = 1;
10957         }
10958         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10959                                                    &veb_bw, NULL);
10960         if (ret) {
10961                 PMD_INIT_LOG(ERR,
10962                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10963                         hw->aq.asq_last_status);
10964                 return ret;
10965         }
10966
10967         memset(&ets_query, 0, sizeof(ets_query));
10968         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10969                                                    &ets_query, NULL);
10970         if (ret != I40E_SUCCESS) {
10971                 PMD_DRV_LOG(ERR,
10972                         "Failed to get switch_comp ETS configuration %u",
10973                         hw->aq.asq_last_status);
10974                 return ret;
10975         }
10976         memset(&bw_query, 0, sizeof(bw_query));
10977         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10978                                                   &bw_query, NULL);
10979         if (ret != I40E_SUCCESS) {
10980                 PMD_DRV_LOG(ERR,
10981                         "Failed to get switch_comp bandwidth configuration %u",
10982                         hw->aq.asq_last_status);
10983                 return ret;
10984         }
10985
10986         /* store and print out BW info */
10987         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10988         veb->bw_info.bw_max = ets_query.tc_bw_max;
10989         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10990         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10991         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10992                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10993                      I40E_16_BIT_WIDTH);
10994         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10995                 veb->bw_info.bw_ets_share_credits[i] =
10996                                 bw_query.tc_bw_share_credits[i];
10997                 veb->bw_info.bw_ets_credits[i] =
10998                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10999                 /* 4 bits per TC, 4th bit is reserved */
11000                 veb->bw_info.bw_ets_max[i] =
11001                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11002                                   RTE_LEN2MASK(3, uint8_t));
11003                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11004                             veb->bw_info.bw_ets_share_credits[i]);
11005                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11006                             veb->bw_info.bw_ets_credits[i]);
11007                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11008                             veb->bw_info.bw_ets_max[i]);
11009         }
11010
11011         veb->enabled_tc = tc_map;
11012
11013         return ret;
11014 }
11015
11016
11017 /*
11018  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11019  * @vsi: VSI to be configured
11020  * @tc_map: enabled TC bitmap
11021  *
11022  * Returns 0 on success, negative value on failure
11023  */
11024 static enum i40e_status_code
11025 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11026 {
11027         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11028         struct i40e_vsi_context ctxt;
11029         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11030         enum i40e_status_code ret = I40E_SUCCESS;
11031         int i;
11032
11033         /* Check if enabled_tc is same as existing or new TCs */
11034         if (vsi->enabled_tc == tc_map)
11035                 return ret;
11036
11037         /* configure tc bandwidth */
11038         memset(&bw_data, 0, sizeof(bw_data));
11039         bw_data.tc_valid_bits = tc_map;
11040         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11041         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11042                 if (tc_map & BIT_ULL(i))
11043                         bw_data.tc_bw_credits[i] = 1;
11044         }
11045         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11046         if (ret) {
11047                 PMD_INIT_LOG(ERR,
11048                         "AQ command Config VSI BW allocation per TC failed = %d",
11049                         hw->aq.asq_last_status);
11050                 goto out;
11051         }
11052         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11053                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11054
11055         /* Update Queue Pairs Mapping for currently enabled UPs */
11056         ctxt.seid = vsi->seid;
11057         ctxt.pf_num = hw->pf_id;
11058         ctxt.vf_num = 0;
11059         ctxt.uplink_seid = vsi->uplink_seid;
11060         ctxt.info = vsi->info;
11061         i40e_get_cap(hw);
11062         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11063         if (ret)
11064                 goto out;
11065
11066         /* Update the VSI after updating the VSI queue-mapping information */
11067         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11068         if (ret) {
11069                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11070                         hw->aq.asq_last_status);
11071                 goto out;
11072         }
11073         /* update the local VSI info with updated queue map */
11074         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11075                                         sizeof(vsi->info.tc_mapping));
11076         rte_memcpy(&vsi->info.queue_mapping,
11077                         &ctxt.info.queue_mapping,
11078                 sizeof(vsi->info.queue_mapping));
11079         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11080         vsi->info.valid_sections = 0;
11081
11082         /* query and update current VSI BW information */
11083         ret = i40e_vsi_get_bw_config(vsi);
11084         if (ret) {
11085                 PMD_INIT_LOG(ERR,
11086                          "Failed updating vsi bw info, err %s aq_err %s",
11087                          i40e_stat_str(hw, ret),
11088                          i40e_aq_str(hw, hw->aq.asq_last_status));
11089                 goto out;
11090         }
11091
11092         vsi->enabled_tc = tc_map;
11093
11094 out:
11095         return ret;
11096 }
11097
11098 /*
11099  * i40e_dcb_hw_configure - program the dcb setting to hw
11100  * @pf: pf the configuration is taken on
11101  * @new_cfg: new configuration
11102  * @tc_map: enabled TC bitmap
11103  *
11104  * Returns 0 on success, negative value on failure
11105  */
11106 static enum i40e_status_code
11107 i40e_dcb_hw_configure(struct i40e_pf *pf,
11108                       struct i40e_dcbx_config *new_cfg,
11109                       uint8_t tc_map)
11110 {
11111         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11112         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11113         struct i40e_vsi *main_vsi = pf->main_vsi;
11114         struct i40e_vsi_list *vsi_list;
11115         enum i40e_status_code ret;
11116         int i;
11117         uint32_t val;
11118
11119         /* Use the FW API if FW > v4.4*/
11120         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11121               (hw->aq.fw_maj_ver >= 5))) {
11122                 PMD_INIT_LOG(ERR,
11123                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11124                 return I40E_ERR_FIRMWARE_API_VERSION;
11125         }
11126
11127         /* Check if need reconfiguration */
11128         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11129                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11130                 return I40E_SUCCESS;
11131         }
11132
11133         /* Copy the new config to the current config */
11134         *old_cfg = *new_cfg;
11135         old_cfg->etsrec = old_cfg->etscfg;
11136         ret = i40e_set_dcb_config(hw);
11137         if (ret) {
11138                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11139                          i40e_stat_str(hw, ret),
11140                          i40e_aq_str(hw, hw->aq.asq_last_status));
11141                 return ret;
11142         }
11143         /* set receive Arbiter to RR mode and ETS scheme by default */
11144         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11145                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11146                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11147                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11148                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11149                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11150                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11151                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11152                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11153                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11154                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11155                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11156                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11157         }
11158         /* get local mib to check whether it is configured correctly */
11159         /* IEEE mode */
11160         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11161         /* Get Local DCB Config */
11162         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11163                                      &hw->local_dcbx_config);
11164
11165         /* if Veb is created, need to update TC of it at first */
11166         if (main_vsi->veb) {
11167                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11168                 if (ret)
11169                         PMD_INIT_LOG(WARNING,
11170                                  "Failed configuring TC for VEB seid=%d",
11171                                  main_vsi->veb->seid);
11172         }
11173         /* Update each VSI */
11174         i40e_vsi_config_tc(main_vsi, tc_map);
11175         if (main_vsi->veb) {
11176                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11177                         /* Beside main VSI and VMDQ VSIs, only enable default
11178                          * TC for other VSIs
11179                          */
11180                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11181                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11182                                                          tc_map);
11183                         else
11184                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11185                                                          I40E_DEFAULT_TCMAP);
11186                         if (ret)
11187                                 PMD_INIT_LOG(WARNING,
11188                                         "Failed configuring TC for VSI seid=%d",
11189                                         vsi_list->vsi->seid);
11190                         /* continue */
11191                 }
11192         }
11193         return I40E_SUCCESS;
11194 }
11195
11196 /*
11197  * i40e_dcb_init_configure - initial dcb config
11198  * @dev: device being configured
11199  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11200  *
11201  * Returns 0 on success, negative value on failure
11202  */
11203 int
11204 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11205 {
11206         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11207         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11208         int i, ret = 0;
11209
11210         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11211                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11212                 return -ENOTSUP;
11213         }
11214
11215         /* DCB initialization:
11216          * Update DCB configuration from the Firmware and configure
11217          * LLDP MIB change event.
11218          */
11219         if (sw_dcb == TRUE) {
11220                 ret = i40e_init_dcb(hw);
11221                 /* If lldp agent is stopped, the return value from
11222                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11223                  * adminq status. Otherwise, it should return success.
11224                  */
11225                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11226                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11227                         memset(&hw->local_dcbx_config, 0,
11228                                 sizeof(struct i40e_dcbx_config));
11229                         /* set dcb default configuration */
11230                         hw->local_dcbx_config.etscfg.willing = 0;
11231                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11232                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11233                         hw->local_dcbx_config.etscfg.tsatable[0] =
11234                                                 I40E_IEEE_TSA_ETS;
11235                         /* all UPs mapping to TC0 */
11236                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11237                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11238                         hw->local_dcbx_config.etsrec =
11239                                 hw->local_dcbx_config.etscfg;
11240                         hw->local_dcbx_config.pfc.willing = 0;
11241                         hw->local_dcbx_config.pfc.pfccap =
11242                                                 I40E_MAX_TRAFFIC_CLASS;
11243                         /* FW needs one App to configure HW */
11244                         hw->local_dcbx_config.numapps = 1;
11245                         hw->local_dcbx_config.app[0].selector =
11246                                                 I40E_APP_SEL_ETHTYPE;
11247                         hw->local_dcbx_config.app[0].priority = 3;
11248                         hw->local_dcbx_config.app[0].protocolid =
11249                                                 I40E_APP_PROTOID_FCOE;
11250                         ret = i40e_set_dcb_config(hw);
11251                         if (ret) {
11252                                 PMD_INIT_LOG(ERR,
11253                                         "default dcb config fails. err = %d, aq_err = %d.",
11254                                         ret, hw->aq.asq_last_status);
11255                                 return -ENOSYS;
11256                         }
11257                 } else {
11258                         PMD_INIT_LOG(ERR,
11259                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11260                                 ret, hw->aq.asq_last_status);
11261                         return -ENOTSUP;
11262                 }
11263         } else {
11264                 ret = i40e_aq_start_lldp(hw, NULL);
11265                 if (ret != I40E_SUCCESS)
11266                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11267
11268                 ret = i40e_init_dcb(hw);
11269                 if (!ret) {
11270                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11271                                 PMD_INIT_LOG(ERR,
11272                                         "HW doesn't support DCBX offload.");
11273                                 return -ENOTSUP;
11274                         }
11275                 } else {
11276                         PMD_INIT_LOG(ERR,
11277                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11278                                 ret, hw->aq.asq_last_status);
11279                         return -ENOTSUP;
11280                 }
11281         }
11282         return 0;
11283 }
11284
11285 /*
11286  * i40e_dcb_setup - setup dcb related config
11287  * @dev: device being configured
11288  *
11289  * Returns 0 on success, negative value on failure
11290  */
11291 static int
11292 i40e_dcb_setup(struct rte_eth_dev *dev)
11293 {
11294         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11295         struct i40e_dcbx_config dcb_cfg;
11296         uint8_t tc_map = 0;
11297         int ret = 0;
11298
11299         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11300                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11301                 return -ENOTSUP;
11302         }
11303
11304         if (pf->vf_num != 0)
11305                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11306
11307         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11308         if (ret) {
11309                 PMD_INIT_LOG(ERR, "invalid dcb config");
11310                 return -EINVAL;
11311         }
11312         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11313         if (ret) {
11314                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11315                 return -ENOSYS;
11316         }
11317
11318         return 0;
11319 }
11320
11321 static int
11322 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11323                       struct rte_eth_dcb_info *dcb_info)
11324 {
11325         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11326         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11327         struct i40e_vsi *vsi = pf->main_vsi;
11328         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11329         uint16_t bsf, tc_mapping;
11330         int i, j = 0;
11331
11332         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11333                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11334         else
11335                 dcb_info->nb_tcs = 1;
11336         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11337                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11338         for (i = 0; i < dcb_info->nb_tcs; i++)
11339                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11340
11341         /* get queue mapping if vmdq is disabled */
11342         if (!pf->nb_cfg_vmdq_vsi) {
11343                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11344                         if (!(vsi->enabled_tc & (1 << i)))
11345                                 continue;
11346                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11347                         dcb_info->tc_queue.tc_rxq[j][i].base =
11348                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11349                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11350                         dcb_info->tc_queue.tc_txq[j][i].base =
11351                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11352                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11353                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11354                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11355                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11356                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11357                 }
11358                 return 0;
11359         }
11360
11361         /* get queue mapping if vmdq is enabled */
11362         do {
11363                 vsi = pf->vmdq[j].vsi;
11364                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11365                         if (!(vsi->enabled_tc & (1 << i)))
11366                                 continue;
11367                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11368                         dcb_info->tc_queue.tc_rxq[j][i].base =
11369                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11370                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11371                         dcb_info->tc_queue.tc_txq[j][i].base =
11372                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11373                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11374                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11375                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11376                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11377                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11378                 }
11379                 j++;
11380         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11381         return 0;
11382 }
11383
11384 static int
11385 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11386 {
11387         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11388         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11389         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11390         uint16_t msix_intr;
11391
11392         msix_intr = intr_handle->intr_vec[queue_id];
11393         if (msix_intr == I40E_MISC_VEC_ID)
11394                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11395                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11396                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11397                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11398         else
11399                 I40E_WRITE_REG(hw,
11400                                I40E_PFINT_DYN_CTLN(msix_intr -
11401                                                    I40E_RX_VEC_START),
11402                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11403                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11404                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11405
11406         I40E_WRITE_FLUSH(hw);
11407         rte_intr_enable(&pci_dev->intr_handle);
11408
11409         return 0;
11410 }
11411
11412 static int
11413 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11414 {
11415         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11416         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11417         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11418         uint16_t msix_intr;
11419
11420         msix_intr = intr_handle->intr_vec[queue_id];
11421         if (msix_intr == I40E_MISC_VEC_ID)
11422                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11423                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11424         else
11425                 I40E_WRITE_REG(hw,
11426                                I40E_PFINT_DYN_CTLN(msix_intr -
11427                                                    I40E_RX_VEC_START),
11428                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11429         I40E_WRITE_FLUSH(hw);
11430
11431         return 0;
11432 }
11433
11434 static int i40e_get_regs(struct rte_eth_dev *dev,
11435                          struct rte_dev_reg_info *regs)
11436 {
11437         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11438         uint32_t *ptr_data = regs->data;
11439         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11440         const struct i40e_reg_info *reg_info;
11441
11442         if (ptr_data == NULL) {
11443                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11444                 regs->width = sizeof(uint32_t);
11445                 return 0;
11446         }
11447
11448         /* The first few registers have to be read using AQ operations */
11449         reg_idx = 0;
11450         while (i40e_regs_adminq[reg_idx].name) {
11451                 reg_info = &i40e_regs_adminq[reg_idx++];
11452                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11453                         for (arr_idx2 = 0;
11454                                         arr_idx2 <= reg_info->count2;
11455                                         arr_idx2++) {
11456                                 reg_offset = arr_idx * reg_info->stride1 +
11457                                         arr_idx2 * reg_info->stride2;
11458                                 reg_offset += reg_info->base_addr;
11459                                 ptr_data[reg_offset >> 2] =
11460                                         i40e_read_rx_ctl(hw, reg_offset);
11461                         }
11462         }
11463
11464         /* The remaining registers can be read using primitives */
11465         reg_idx = 0;
11466         while (i40e_regs_others[reg_idx].name) {
11467                 reg_info = &i40e_regs_others[reg_idx++];
11468                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11469                         for (arr_idx2 = 0;
11470                                         arr_idx2 <= reg_info->count2;
11471                                         arr_idx2++) {
11472                                 reg_offset = arr_idx * reg_info->stride1 +
11473                                         arr_idx2 * reg_info->stride2;
11474                                 reg_offset += reg_info->base_addr;
11475                                 ptr_data[reg_offset >> 2] =
11476                                         I40E_READ_REG(hw, reg_offset);
11477                         }
11478         }
11479
11480         return 0;
11481 }
11482
11483 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11484 {
11485         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11486
11487         /* Convert word count to byte count */
11488         return hw->nvm.sr_size << 1;
11489 }
11490
11491 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11492                            struct rte_dev_eeprom_info *eeprom)
11493 {
11494         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11495         uint16_t *data = eeprom->data;
11496         uint16_t offset, length, cnt_words;
11497         int ret_code;
11498
11499         offset = eeprom->offset >> 1;
11500         length = eeprom->length >> 1;
11501         cnt_words = length;
11502
11503         if (offset > hw->nvm.sr_size ||
11504                 offset + length > hw->nvm.sr_size) {
11505                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11506                 return -EINVAL;
11507         }
11508
11509         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11510
11511         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11512         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11513                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11514                 return -EIO;
11515         }
11516
11517         return 0;
11518 }
11519
11520 static int i40e_get_module_info(struct rte_eth_dev *dev,
11521                                 struct rte_eth_dev_module_info *modinfo)
11522 {
11523         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11524         uint32_t sff8472_comp = 0;
11525         uint32_t sff8472_swap = 0;
11526         uint32_t sff8636_rev = 0;
11527         i40e_status status;
11528         uint32_t type = 0;
11529
11530         /* Check if firmware supports reading module EEPROM. */
11531         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11532                 PMD_DRV_LOG(ERR,
11533                             "Module EEPROM memory read not supported. "
11534                             "Please update the NVM image.\n");
11535                 return -EINVAL;
11536         }
11537
11538         status = i40e_update_link_info(hw);
11539         if (status)
11540                 return -EIO;
11541
11542         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11543                 PMD_DRV_LOG(ERR,
11544                             "Cannot read module EEPROM memory. "
11545                             "No module connected.\n");
11546                 return -EINVAL;
11547         }
11548
11549         type = hw->phy.link_info.module_type[0];
11550
11551         switch (type) {
11552         case I40E_MODULE_TYPE_SFP:
11553                 status = i40e_aq_get_phy_register(hw,
11554                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11555                                 I40E_I2C_EEPROM_DEV_ADDR,
11556                                 I40E_MODULE_SFF_8472_COMP,
11557                                 &sff8472_comp, NULL);
11558                 if (status)
11559                         return -EIO;
11560
11561                 status = i40e_aq_get_phy_register(hw,
11562                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11563                                 I40E_I2C_EEPROM_DEV_ADDR,
11564                                 I40E_MODULE_SFF_8472_SWAP,
11565                                 &sff8472_swap, NULL);
11566                 if (status)
11567                         return -EIO;
11568
11569                 /* Check if the module requires address swap to access
11570                  * the other EEPROM memory page.
11571                  */
11572                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11573                         PMD_DRV_LOG(WARNING,
11574                                     "Module address swap to access "
11575                                     "page 0xA2 is not supported.\n");
11576                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11577                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11578                 } else if (sff8472_comp == 0x00) {
11579                         /* Module is not SFF-8472 compliant */
11580                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11581                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11582                 } else {
11583                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11584                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11585                 }
11586                 break;
11587         case I40E_MODULE_TYPE_QSFP_PLUS:
11588                 /* Read from memory page 0. */
11589                 status = i40e_aq_get_phy_register(hw,
11590                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11591                                 0,
11592                                 I40E_MODULE_REVISION_ADDR,
11593                                 &sff8636_rev, NULL);
11594                 if (status)
11595                         return -EIO;
11596                 /* Determine revision compliance byte */
11597                 if (sff8636_rev > 0x02) {
11598                         /* Module is SFF-8636 compliant */
11599                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11600                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11601                 } else {
11602                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11603                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11604                 }
11605                 break;
11606         case I40E_MODULE_TYPE_QSFP28:
11607                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11608                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11609                 break;
11610         default:
11611                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11612                 return -EINVAL;
11613         }
11614         return 0;
11615 }
11616
11617 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11618                                   struct rte_dev_eeprom_info *info)
11619 {
11620         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11621         bool is_sfp = false;
11622         i40e_status status;
11623         uint8_t *data = info->data;
11624         uint32_t value = 0;
11625         uint32_t i;
11626
11627         if (!info || !info->length || !data)
11628                 return -EINVAL;
11629
11630         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11631                 is_sfp = true;
11632
11633         for (i = 0; i < info->length; i++) {
11634                 u32 offset = i + info->offset;
11635                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11636
11637                 /* Check if we need to access the other memory page */
11638                 if (is_sfp) {
11639                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11640                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11641                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11642                         }
11643                 } else {
11644                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11645                                 /* Compute memory page number and offset. */
11646                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11647                                 addr++;
11648                         }
11649                 }
11650                 status = i40e_aq_get_phy_register(hw,
11651                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11652                                 addr, offset, &value, NULL);
11653                 if (status)
11654                         return -EIO;
11655                 data[i] = (uint8_t)value;
11656         }
11657         return 0;
11658 }
11659
11660 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11661                                      struct ether_addr *mac_addr)
11662 {
11663         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11664         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11665         struct i40e_vsi *vsi = pf->main_vsi;
11666         struct i40e_mac_filter_info mac_filter;
11667         struct i40e_mac_filter *f;
11668         int ret;
11669
11670         if (!is_valid_assigned_ether_addr(mac_addr)) {
11671                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11672                 return -EINVAL;
11673         }
11674
11675         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11676                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11677                         break;
11678         }
11679
11680         if (f == NULL) {
11681                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11682                 return -EIO;
11683         }
11684
11685         mac_filter = f->mac_info;
11686         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11687         if (ret != I40E_SUCCESS) {
11688                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11689                 return -EIO;
11690         }
11691         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11692         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11693         if (ret != I40E_SUCCESS) {
11694                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11695                 return -EIO;
11696         }
11697         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11698
11699         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11700                                         mac_addr->addr_bytes, NULL);
11701         if (ret != I40E_SUCCESS) {
11702                 PMD_DRV_LOG(ERR, "Failed to change mac");
11703                 return -EIO;
11704         }
11705
11706         return 0;
11707 }
11708
11709 static int
11710 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11711 {
11712         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11713         struct rte_eth_dev_data *dev_data = pf->dev_data;
11714         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11715         int ret = 0;
11716
11717         /* check if mtu is within the allowed range */
11718         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11719                 return -EINVAL;
11720
11721         /* mtu setting is forbidden if port is start */
11722         if (dev_data->dev_started) {
11723                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11724                             dev_data->port_id);
11725                 return -EBUSY;
11726         }
11727
11728         if (frame_size > ETHER_MAX_LEN)
11729                 dev_data->dev_conf.rxmode.offloads |=
11730                         DEV_RX_OFFLOAD_JUMBO_FRAME;
11731         else
11732                 dev_data->dev_conf.rxmode.offloads &=
11733                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11734
11735         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11736
11737         return ret;
11738 }
11739
11740 /* Restore ethertype filter */
11741 static void
11742 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11743 {
11744         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11745         struct i40e_ethertype_filter_list
11746                 *ethertype_list = &pf->ethertype.ethertype_list;
11747         struct i40e_ethertype_filter *f;
11748         struct i40e_control_filter_stats stats;
11749         uint16_t flags;
11750
11751         TAILQ_FOREACH(f, ethertype_list, rules) {
11752                 flags = 0;
11753                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11754                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11755                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11756                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11757                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11758
11759                 memset(&stats, 0, sizeof(stats));
11760                 i40e_aq_add_rem_control_packet_filter(hw,
11761                                             f->input.mac_addr.addr_bytes,
11762                                             f->input.ether_type,
11763                                             flags, pf->main_vsi->seid,
11764                                             f->queue, 1, &stats, NULL);
11765         }
11766         PMD_DRV_LOG(INFO, "Ethertype filter:"
11767                     " mac_etype_used = %u, etype_used = %u,"
11768                     " mac_etype_free = %u, etype_free = %u",
11769                     stats.mac_etype_used, stats.etype_used,
11770                     stats.mac_etype_free, stats.etype_free);
11771 }
11772
11773 /* Restore tunnel filter */
11774 static void
11775 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11776 {
11777         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11778         struct i40e_vsi *vsi;
11779         struct i40e_pf_vf *vf;
11780         struct i40e_tunnel_filter_list
11781                 *tunnel_list = &pf->tunnel.tunnel_list;
11782         struct i40e_tunnel_filter *f;
11783         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11784         bool big_buffer = 0;
11785
11786         TAILQ_FOREACH(f, tunnel_list, rules) {
11787                 if (!f->is_to_vf)
11788                         vsi = pf->main_vsi;
11789                 else {
11790                         vf = &pf->vfs[f->vf_id];
11791                         vsi = vf->vsi;
11792                 }
11793                 memset(&cld_filter, 0, sizeof(cld_filter));
11794                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11795                         (struct ether_addr *)&cld_filter.element.outer_mac);
11796                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11797                         (struct ether_addr *)&cld_filter.element.inner_mac);
11798                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11799                 cld_filter.element.flags = f->input.flags;
11800                 cld_filter.element.tenant_id = f->input.tenant_id;
11801                 cld_filter.element.queue_number = f->queue;
11802                 rte_memcpy(cld_filter.general_fields,
11803                            f->input.general_fields,
11804                            sizeof(f->input.general_fields));
11805
11806                 if (((f->input.flags &
11807                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11808                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11809                     ((f->input.flags &
11810                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11811                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11812                     ((f->input.flags &
11813                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11814                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11815                         big_buffer = 1;
11816
11817                 if (big_buffer)
11818                         i40e_aq_add_cloud_filters_big_buffer(hw,
11819                                              vsi->seid, &cld_filter, 1);
11820                 else
11821                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11822                                                   &cld_filter.element, 1);
11823         }
11824 }
11825
11826 /* Restore rss filter */
11827 static inline void
11828 i40e_rss_filter_restore(struct i40e_pf *pf)
11829 {
11830         struct i40e_rte_flow_rss_conf *conf =
11831                                         &pf->rss_info;
11832         if (conf->conf.queue_num)
11833                 i40e_config_rss_filter(pf, conf, TRUE);
11834 }
11835
11836 static void
11837 i40e_filter_restore(struct i40e_pf *pf)
11838 {
11839         i40e_ethertype_filter_restore(pf);
11840         i40e_tunnel_filter_restore(pf);
11841         i40e_fdir_filter_restore(pf);
11842         i40e_rss_filter_restore(pf);
11843 }
11844
11845 static bool
11846 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11847 {
11848         if (strcmp(dev->device->driver->name, drv->driver.name))
11849                 return false;
11850
11851         return true;
11852 }
11853
11854 bool
11855 is_i40e_supported(struct rte_eth_dev *dev)
11856 {
11857         return is_device_supported(dev, &rte_i40e_pmd);
11858 }
11859
11860 struct i40e_customized_pctype*
11861 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11862 {
11863         int i;
11864
11865         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11866                 if (pf->customized_pctype[i].index == index)
11867                         return &pf->customized_pctype[i];
11868         }
11869         return NULL;
11870 }
11871
11872 static int
11873 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11874                               uint32_t pkg_size, uint32_t proto_num,
11875                               struct rte_pmd_i40e_proto_info *proto,
11876                               enum rte_pmd_i40e_package_op op)
11877 {
11878         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11879         uint32_t pctype_num;
11880         struct rte_pmd_i40e_ptype_info *pctype;
11881         uint32_t buff_size;
11882         struct i40e_customized_pctype *new_pctype = NULL;
11883         uint8_t proto_id;
11884         uint8_t pctype_value;
11885         char name[64];
11886         uint32_t i, j, n;
11887         int ret;
11888
11889         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11890             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11891                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11892                 return -1;
11893         }
11894
11895         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11896                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11897                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11898         if (ret) {
11899                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11900                 return -1;
11901         }
11902         if (!pctype_num) {
11903                 PMD_DRV_LOG(INFO, "No new pctype added");
11904                 return -1;
11905         }
11906
11907         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11908         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11909         if (!pctype) {
11910                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11911                 return -1;
11912         }
11913         /* get information about new pctype list */
11914         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11915                                         (uint8_t *)pctype, buff_size,
11916                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11917         if (ret) {
11918                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11919                 rte_free(pctype);
11920                 return -1;
11921         }
11922
11923         /* Update customized pctype. */
11924         for (i = 0; i < pctype_num; i++) {
11925                 pctype_value = pctype[i].ptype_id;
11926                 memset(name, 0, sizeof(name));
11927                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11928                         proto_id = pctype[i].protocols[j];
11929                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11930                                 continue;
11931                         for (n = 0; n < proto_num; n++) {
11932                                 if (proto[n].proto_id != proto_id)
11933                                         continue;
11934                                 strcat(name, proto[n].name);
11935                                 strcat(name, "_");
11936                                 break;
11937                         }
11938                 }
11939                 name[strlen(name) - 1] = '\0';
11940                 if (!strcmp(name, "GTPC"))
11941                         new_pctype =
11942                                 i40e_find_customized_pctype(pf,
11943                                                       I40E_CUSTOMIZED_GTPC);
11944                 else if (!strcmp(name, "GTPU_IPV4"))
11945                         new_pctype =
11946                                 i40e_find_customized_pctype(pf,
11947                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11948                 else if (!strcmp(name, "GTPU_IPV6"))
11949                         new_pctype =
11950                                 i40e_find_customized_pctype(pf,
11951                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11952                 else if (!strcmp(name, "GTPU"))
11953                         new_pctype =
11954                                 i40e_find_customized_pctype(pf,
11955                                                       I40E_CUSTOMIZED_GTPU);
11956                 if (new_pctype) {
11957                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11958                                 new_pctype->pctype = pctype_value;
11959                                 new_pctype->valid = true;
11960                         } else {
11961                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11962                                 new_pctype->valid = false;
11963                         }
11964                 }
11965         }
11966
11967         rte_free(pctype);
11968         return 0;
11969 }
11970
11971 static int
11972 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11973                              uint32_t pkg_size, uint32_t proto_num,
11974                              struct rte_pmd_i40e_proto_info *proto,
11975                              enum rte_pmd_i40e_package_op op)
11976 {
11977         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11978         uint16_t port_id = dev->data->port_id;
11979         uint32_t ptype_num;
11980         struct rte_pmd_i40e_ptype_info *ptype;
11981         uint32_t buff_size;
11982         uint8_t proto_id;
11983         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11984         uint32_t i, j, n;
11985         bool in_tunnel;
11986         int ret;
11987
11988         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11989             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11990                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11991                 return -1;
11992         }
11993
11994         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11995                 rte_pmd_i40e_ptype_mapping_reset(port_id);
11996                 return 0;
11997         }
11998
11999         /* get information about new ptype num */
12000         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12001                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12002                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12003         if (ret) {
12004                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12005                 return ret;
12006         }
12007         if (!ptype_num) {
12008                 PMD_DRV_LOG(INFO, "No new ptype added");
12009                 return -1;
12010         }
12011
12012         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12013         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12014         if (!ptype) {
12015                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12016                 return -1;
12017         }
12018
12019         /* get information about new ptype list */
12020         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12021                                         (uint8_t *)ptype, buff_size,
12022                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12023         if (ret) {
12024                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12025                 rte_free(ptype);
12026                 return ret;
12027         }
12028
12029         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12030         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12031         if (!ptype_mapping) {
12032                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12033                 rte_free(ptype);
12034                 return -1;
12035         }
12036
12037         /* Update ptype mapping table. */
12038         for (i = 0; i < ptype_num; i++) {
12039                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12040                 ptype_mapping[i].sw_ptype = 0;
12041                 in_tunnel = false;
12042                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12043                         proto_id = ptype[i].protocols[j];
12044                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12045                                 continue;
12046                         for (n = 0; n < proto_num; n++) {
12047                                 if (proto[n].proto_id != proto_id)
12048                                         continue;
12049                                 memset(name, 0, sizeof(name));
12050                                 strcpy(name, proto[n].name);
12051                                 if (!strncasecmp(name, "PPPOE", 5))
12052                                         ptype_mapping[i].sw_ptype |=
12053                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12054                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12055                                          !in_tunnel) {
12056                                         ptype_mapping[i].sw_ptype |=
12057                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12058                                         ptype_mapping[i].sw_ptype |=
12059                                                 RTE_PTYPE_L4_FRAG;
12060                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12061                                            in_tunnel) {
12062                                         ptype_mapping[i].sw_ptype |=
12063                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12064                                         ptype_mapping[i].sw_ptype |=
12065                                                 RTE_PTYPE_INNER_L4_FRAG;
12066                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12067                                         ptype_mapping[i].sw_ptype |=
12068                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12069                                         in_tunnel = true;
12070                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12071                                            !in_tunnel)
12072                                         ptype_mapping[i].sw_ptype |=
12073                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12074                                 else if (!strncasecmp(name, "IPV4", 4) &&
12075                                          in_tunnel)
12076                                         ptype_mapping[i].sw_ptype |=
12077                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12078                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12079                                          !in_tunnel) {
12080                                         ptype_mapping[i].sw_ptype |=
12081                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12082                                         ptype_mapping[i].sw_ptype |=
12083                                                 RTE_PTYPE_L4_FRAG;
12084                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12085                                            in_tunnel) {
12086                                         ptype_mapping[i].sw_ptype |=
12087                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12088                                         ptype_mapping[i].sw_ptype |=
12089                                                 RTE_PTYPE_INNER_L4_FRAG;
12090                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12091                                         ptype_mapping[i].sw_ptype |=
12092                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12093                                         in_tunnel = true;
12094                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12095                                            !in_tunnel)
12096                                         ptype_mapping[i].sw_ptype |=
12097                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12098                                 else if (!strncasecmp(name, "IPV6", 4) &&
12099                                          in_tunnel)
12100                                         ptype_mapping[i].sw_ptype |=
12101                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12102                                 else if (!strncasecmp(name, "UDP", 3) &&
12103                                          !in_tunnel)
12104                                         ptype_mapping[i].sw_ptype |=
12105                                                 RTE_PTYPE_L4_UDP;
12106                                 else if (!strncasecmp(name, "UDP", 3) &&
12107                                          in_tunnel)
12108                                         ptype_mapping[i].sw_ptype |=
12109                                                 RTE_PTYPE_INNER_L4_UDP;
12110                                 else if (!strncasecmp(name, "TCP", 3) &&
12111                                          !in_tunnel)
12112                                         ptype_mapping[i].sw_ptype |=
12113                                                 RTE_PTYPE_L4_TCP;
12114                                 else if (!strncasecmp(name, "TCP", 3) &&
12115                                          in_tunnel)
12116                                         ptype_mapping[i].sw_ptype |=
12117                                                 RTE_PTYPE_INNER_L4_TCP;
12118                                 else if (!strncasecmp(name, "SCTP", 4) &&
12119                                          !in_tunnel)
12120                                         ptype_mapping[i].sw_ptype |=
12121                                                 RTE_PTYPE_L4_SCTP;
12122                                 else if (!strncasecmp(name, "SCTP", 4) &&
12123                                          in_tunnel)
12124                                         ptype_mapping[i].sw_ptype |=
12125                                                 RTE_PTYPE_INNER_L4_SCTP;
12126                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12127                                           !strncasecmp(name, "ICMPV6", 6)) &&
12128                                          !in_tunnel)
12129                                         ptype_mapping[i].sw_ptype |=
12130                                                 RTE_PTYPE_L4_ICMP;
12131                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12132                                           !strncasecmp(name, "ICMPV6", 6)) &&
12133                                          in_tunnel)
12134                                         ptype_mapping[i].sw_ptype |=
12135                                                 RTE_PTYPE_INNER_L4_ICMP;
12136                                 else if (!strncasecmp(name, "GTPC", 4)) {
12137                                         ptype_mapping[i].sw_ptype |=
12138                                                 RTE_PTYPE_TUNNEL_GTPC;
12139                                         in_tunnel = true;
12140                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12141                                         ptype_mapping[i].sw_ptype |=
12142                                                 RTE_PTYPE_TUNNEL_GTPU;
12143                                         in_tunnel = true;
12144                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12145                                         ptype_mapping[i].sw_ptype |=
12146                                                 RTE_PTYPE_TUNNEL_GRENAT;
12147                                         in_tunnel = true;
12148                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12149                                            !strncasecmp(name, "L2TPV2", 6)) {
12150                                         ptype_mapping[i].sw_ptype |=
12151                                                 RTE_PTYPE_TUNNEL_L2TP;
12152                                         in_tunnel = true;
12153                                 }
12154
12155                                 break;
12156                         }
12157                 }
12158         }
12159
12160         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12161                                                 ptype_num, 0);
12162         if (ret)
12163                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12164
12165         rte_free(ptype_mapping);
12166         rte_free(ptype);
12167         return ret;
12168 }
12169
12170 void
12171 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12172                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12173 {
12174         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12175         uint32_t proto_num;
12176         struct rte_pmd_i40e_proto_info *proto;
12177         uint32_t buff_size;
12178         uint32_t i;
12179         int ret;
12180
12181         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12182             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12183                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12184                 return;
12185         }
12186
12187         /* get information about protocol number */
12188         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12189                                        (uint8_t *)&proto_num, sizeof(proto_num),
12190                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12191         if (ret) {
12192                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12193                 return;
12194         }
12195         if (!proto_num) {
12196                 PMD_DRV_LOG(INFO, "No new protocol added");
12197                 return;
12198         }
12199
12200         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12201         proto = rte_zmalloc("new_proto", buff_size, 0);
12202         if (!proto) {
12203                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12204                 return;
12205         }
12206
12207         /* get information about protocol list */
12208         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12209                                         (uint8_t *)proto, buff_size,
12210                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12211         if (ret) {
12212                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12213                 rte_free(proto);
12214                 return;
12215         }
12216
12217         /* Check if GTP is supported. */
12218         for (i = 0; i < proto_num; i++) {
12219                 if (!strncmp(proto[i].name, "GTP", 3)) {
12220                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12221                                 pf->gtp_support = true;
12222                         else
12223                                 pf->gtp_support = false;
12224                         break;
12225                 }
12226         }
12227
12228         /* Update customized pctype info */
12229         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12230                                             proto_num, proto, op);
12231         if (ret)
12232                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12233
12234         /* Update customized ptype info */
12235         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12236                                            proto_num, proto, op);
12237         if (ret)
12238                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12239
12240         rte_free(proto);
12241 }
12242
12243 /* Create a QinQ cloud filter
12244  *
12245  * The Fortville NIC has limited resources for tunnel filters,
12246  * so we can only reuse existing filters.
12247  *
12248  * In step 1 we define which Field Vector fields can be used for
12249  * filter types.
12250  * As we do not have the inner tag defined as a field,
12251  * we have to define it first, by reusing one of L1 entries.
12252  *
12253  * In step 2 we are replacing one of existing filter types with
12254  * a new one for QinQ.
12255  * As we reusing L1 and replacing L2, some of the default filter
12256  * types will disappear,which depends on L1 and L2 entries we reuse.
12257  *
12258  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12259  *
12260  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12261  *              later when we define the cloud filter.
12262  *      a.      Valid_flags.replace_cloud = 0
12263  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12264  *      c.      New_filter = 0x10
12265  *      d.      TR bit = 0xff (optional, not used here)
12266  *      e.      Buffer – 2 entries:
12267  *              i.      Byte 0 = 8 (outer vlan FV index).
12268  *                      Byte 1 = 0 (rsv)
12269  *                      Byte 2-3 = 0x0fff
12270  *              ii.     Byte 0 = 37 (inner vlan FV index).
12271  *                      Byte 1 =0 (rsv)
12272  *                      Byte 2-3 = 0x0fff
12273  *
12274  * Step 2:
12275  * 2.   Create cloud filter using two L1 filters entries: stag and
12276  *              new filter(outer vlan+ inner vlan)
12277  *      a.      Valid_flags.replace_cloud = 1
12278  *      b.      Old_filter = 1 (instead of outer IP)
12279  *      c.      New_filter = 0x10
12280  *      d.      Buffer – 2 entries:
12281  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12282  *                      Byte 1-3 = 0 (rsv)
12283  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12284  *                      Byte 9-11 = 0 (rsv)
12285  */
12286 static int
12287 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12288 {
12289         int ret = -ENOTSUP;
12290         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12291         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12292         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12293         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12294
12295         if (pf->support_multi_driver) {
12296                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12297                 return ret;
12298         }
12299
12300         /* Init */
12301         memset(&filter_replace, 0,
12302                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12303         memset(&filter_replace_buf, 0,
12304                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12305
12306         /* create L1 filter */
12307         filter_replace.old_filter_type =
12308                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12309         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12310         filter_replace.tr_bit = 0;
12311
12312         /* Prepare the buffer, 2 entries */
12313         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12314         filter_replace_buf.data[0] |=
12315                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12316         /* Field Vector 12b mask */
12317         filter_replace_buf.data[2] = 0xff;
12318         filter_replace_buf.data[3] = 0x0f;
12319         filter_replace_buf.data[4] =
12320                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12321         filter_replace_buf.data[4] |=
12322                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12323         /* Field Vector 12b mask */
12324         filter_replace_buf.data[6] = 0xff;
12325         filter_replace_buf.data[7] = 0x0f;
12326         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12327                         &filter_replace_buf);
12328         if (ret != I40E_SUCCESS)
12329                 return ret;
12330
12331         if (filter_replace.old_filter_type !=
12332             filter_replace.new_filter_type)
12333                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12334                             " original: 0x%x, new: 0x%x",
12335                             dev->device->name,
12336                             filter_replace.old_filter_type,
12337                             filter_replace.new_filter_type);
12338
12339         /* Apply the second L2 cloud filter */
12340         memset(&filter_replace, 0,
12341                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12342         memset(&filter_replace_buf, 0,
12343                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12344
12345         /* create L2 filter, input for L2 filter will be L1 filter  */
12346         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12347         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12348         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12349
12350         /* Prepare the buffer, 2 entries */
12351         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12352         filter_replace_buf.data[0] |=
12353                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12354         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12355         filter_replace_buf.data[4] |=
12356                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12357         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12358                         &filter_replace_buf);
12359         if (!ret && (filter_replace.old_filter_type !=
12360                      filter_replace.new_filter_type))
12361                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12362                             " original: 0x%x, new: 0x%x",
12363                             dev->device->name,
12364                             filter_replace.old_filter_type,
12365                             filter_replace.new_filter_type);
12366
12367         return ret;
12368 }
12369
12370 int
12371 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12372                    const struct rte_flow_action_rss *in)
12373 {
12374         if (in->key_len > RTE_DIM(out->key) ||
12375             in->queue_num > RTE_DIM(out->queue))
12376                 return -EINVAL;
12377         out->conf = (struct rte_flow_action_rss){
12378                 .func = in->func,
12379                 .level = in->level,
12380                 .types = in->types,
12381                 .key_len = in->key_len,
12382                 .queue_num = in->queue_num,
12383                 .key = memcpy(out->key, in->key, in->key_len),
12384                 .queue = memcpy(out->queue, in->queue,
12385                                 sizeof(*in->queue) * in->queue_num),
12386         };
12387         return 0;
12388 }
12389
12390 int
12391 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12392                      const struct rte_flow_action_rss *with)
12393 {
12394         return (comp->func == with->func &&
12395                 comp->level == with->level &&
12396                 comp->types == with->types &&
12397                 comp->key_len == with->key_len &&
12398                 comp->queue_num == with->queue_num &&
12399                 !memcmp(comp->key, with->key, with->key_len) &&
12400                 !memcmp(comp->queue, with->queue,
12401                         sizeof(*with->queue) * with->queue_num));
12402 }
12403
12404 int
12405 i40e_config_rss_filter(struct i40e_pf *pf,
12406                 struct i40e_rte_flow_rss_conf *conf, bool add)
12407 {
12408         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12409         uint32_t i, lut = 0;
12410         uint16_t j, num;
12411         struct rte_eth_rss_conf rss_conf = {
12412                 .rss_key = conf->conf.key_len ?
12413                         (void *)(uintptr_t)conf->conf.key : NULL,
12414                 .rss_key_len = conf->conf.key_len,
12415                 .rss_hf = conf->conf.types,
12416         };
12417         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12418
12419         if (!add) {
12420                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12421                         i40e_pf_disable_rss(pf);
12422                         memset(rss_info, 0,
12423                                 sizeof(struct i40e_rte_flow_rss_conf));
12424                         return 0;
12425                 }
12426                 return -EINVAL;
12427         }
12428
12429         if (rss_info->conf.queue_num)
12430                 return -EINVAL;
12431
12432         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12433          * It's necessary to calculate the actual PF queues that are configured.
12434          */
12435         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12436                 num = i40e_pf_calc_configured_queues_num(pf);
12437         else
12438                 num = pf->dev_data->nb_rx_queues;
12439
12440         num = RTE_MIN(num, conf->conf.queue_num);
12441         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12442                         num);
12443
12444         if (num == 0) {
12445                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12446                 return -ENOTSUP;
12447         }
12448
12449         /* Fill in redirection table */
12450         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12451                 if (j == num)
12452                         j = 0;
12453                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12454                         hw->func_caps.rss_table_entry_width) - 1));
12455                 if ((i & 3) == 3)
12456                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12457         }
12458
12459         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12460                 i40e_pf_disable_rss(pf);
12461                 return 0;
12462         }
12463         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12464                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12465                 /* Random default keys */
12466                 static uint32_t rss_key_default[] = {0x6b793944,
12467                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12468                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12469                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12470
12471                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12472                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12473                                                         sizeof(uint32_t);
12474         }
12475
12476         i40e_hw_rss_hash_set(pf, &rss_conf);
12477
12478         if (i40e_rss_conf_init(rss_info, &conf->conf))
12479                 return -EINVAL;
12480
12481         return 0;
12482 }
12483
12484 RTE_INIT(i40e_init_log)
12485 {
12486         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12487         if (i40e_logtype_init >= 0)
12488                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12489         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12490         if (i40e_logtype_driver >= 0)
12491                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12492 }
12493
12494 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12495                               QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12496                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");