drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_eth_ctrl.h>
  28 #include <rte_tailq.h>
  29 #include <rte_hash_crc.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  47
  48 #define I40E_CLEAR_PXE_WAIT_MS     200
  49
  50 /* Maximun number of capability elements */
  51 #define I40E_MAX_CAP_ELE_NUM       128
  52
  53 /* Wait count and interval */
  54 #define I40E_CHK_Q_ENA_COUNT       1000
  55 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  56
  57 /* Maximun number of VSI */
  58 #define I40E_MAX_NUM_VSIS          (384UL)
  59
  60 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  61
  62 /* Flow control default timer */
  63 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  64
  65 /* Flow control enable fwd bit */
  66 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  67
  68 /* Receive Packet Buffer size */
  69 #define I40E_RXPBSIZE (968 * 1024)
  70
  71 /* Kilobytes shift */
  72 #define I40E_KILOSHIFT 10
  73
  74 /* Flow control default high water */
  75 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Flow control default low water */
  78 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  79
  80 /* Receive Average Packet Size in Byte*/
  81 #define I40E_PACKET_AVERAGE_SIZE 128
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  94
  95 #define I40E_FLOW_TYPES ( \
  96         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 101         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 106         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 107
 108 /* Additional timesync values. */
 109 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 110 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 111 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 112 #define I40E_PRTTSYN_TSYNENA     0x80000000
 113 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 114 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 115
 116 /**
 117  * Below are values for writing un-exposed registers suggested
 118  * by silicon experts
 119  */
 120 /* Destination MAC address */
 121 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 122 /* Source MAC address */
 123 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 124 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 125 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 126 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 127 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 128 /* Single VLAN tag in the inner L2 header */
 129 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 130 /* Source IPv4 address */
 131 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 132 /* Destination IPv4 address */
 133 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 134 /* Source IPv4 address for X722 */
 135 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 136 /* Destination IPv4 address for X722 */
 137 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 138 /* IPv4 Protocol for X722 */
 139 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 140 /* IPv4 Time to Live for X722 */
 141 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 142 /* IPv4 Type of Service (TOS) */
 143 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 144 /* IPv4 Protocol */
 145 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 146 /* IPv4 Time to Live */
 147 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 148 /* Source IPv6 address */
 149 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 150 /* Destination IPv6 address */
 151 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 152 /* IPv6 Traffic Class (TC) */
 153 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 154 /* IPv6 Next Header */
 155 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 156 /* IPv6 Hop Limit */
 157 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 158 /* Source L4 port */
 159 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 160 /* Destination L4 port */
 161 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 162 /* SCTP verification tag */
 163 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 164 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 165 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 166 /* Source port of tunneling UDP */
 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 168 /* Destination port of tunneling UDP */
 169 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 170 /* UDP Tunneling ID, NVGRE/GRE key */
 171 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 172 /* Last ether type */
 173 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 174 /* Tunneling outer destination IPv4 address */
 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 176 /* Tunneling outer destination IPv6 address */
 177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 178 /* 1st word of flex payload */
 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 180 /* 2nd word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 182 /* 3rd word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 184 /* 4th word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 186 /* 5th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 188 /* 6th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 190 /* 7th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 192 /* 8th word of flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 194 /* all 8 words flex payload */
 195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 196 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 197
 198 #define I40E_TRANSLATE_INSET 0
 199 #define I40E_TRANSLATE_REG   1
 200
 201 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 202 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 203 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 204 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 205 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 206 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 207
 208 /* PCI offset for querying capability */
 209 #define PCI_DEV_CAP_REG            0xA4
 210 /* PCI offset for enabling/disabling Extended Tag */
 211 #define PCI_DEV_CTRL_REG           0xA8
 212 /* Bit mask of Extended Tag capability */
 213 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 214 /* Bit shift of Extended Tag enable/disable */
 215 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 216 /* Bit mask of Extended Tag enable/disable */
 217 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 218
 219 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 220 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 221 static int i40e_dev_configure(struct rte_eth_dev *dev);
 222 static int i40e_dev_start(struct rte_eth_dev *dev);
 223 static void i40e_dev_stop(struct rte_eth_dev *dev);
 224 static void i40e_dev_close(struct rte_eth_dev *dev);
 225 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 226 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 227 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 228 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 229 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 230 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 232 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 233                                struct rte_eth_stats *stats);
 234 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 235                                struct rte_eth_xstat *xstats, unsigned n);
 236 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 237                                      struct rte_eth_xstat_name *xstats_names,
 238                                      unsigned limit);
 239 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 240 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 241                                             uint16_t queue_id,
 242                                             uint8_t stat_idx,
 243                                             uint8_t is_rx);
 244 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 245                                 char *fw_version, size_t fw_size);
 246 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 247                               struct rte_eth_dev_info *dev_info);
 248 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 249                                 uint16_t vlan_id,
 250                                 int on);
 251 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 252                               enum rte_vlan_type vlan_type,
 253                               uint16_t tpid);
 254 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 255 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 256                                       uint16_t queue,
 257                                       int on);
 258 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 259 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 260 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 261 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 264                               struct rte_eth_fc_conf *fc_conf);
 265 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 266                                        struct rte_eth_pfc_conf *pfc_conf);
 267 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 268                             struct ether_addr *mac_addr,
 269                             uint32_t index,
 270                             uint32_t pool);
 271 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 272 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 273                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                     uint16_t reta_size);
 275 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 276                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 277                                    uint16_t reta_size);
 278
 279 static int i40e_get_cap(struct i40e_hw *hw);
 280 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 281 static int i40e_pf_setup(struct i40e_pf *pf);
 282 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 283 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 284 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 285 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 286                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 287 static void i40e_stat_update_48(struct i40e_hw *hw,
 288                                uint32_t hireg,
 289                                uint32_t loreg,
 290                                bool offset_loaded,
 291                                uint64_t *offset,
 292                                uint64_t *stat);
 293 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 294 static void i40e_dev_interrupt_handler(void *param);
 295 static void i40e_dev_alarm_handler(void *param);
 296 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 297                                 uint32_t base, uint32_t num);
 298 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 299 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 300                         uint32_t base);
 301 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 302                         uint16_t num);
 303 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 304 static int i40e_veb_release(struct i40e_veb *veb);
 305 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 306                                                 struct i40e_vsi *vsi);
 307 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 308 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 309 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 310                                              struct i40e_macvlan_filter *mv_f,
 311                                              int num,
 312                                              uint16_t vlan);
 313 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 314 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 315                                     struct rte_eth_rss_conf *rss_conf);
 316 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 317                                       struct rte_eth_rss_conf *rss_conf);
 318 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 319                                         struct rte_eth_udp_tunnel *udp_tunnel);
 320 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 321                                         struct rte_eth_udp_tunnel *udp_tunnel);
 322 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 323 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 327                                 enum rte_filter_type filter_type,
 328                                 enum rte_filter_op filter_op,
 329                                 void *arg);
 330 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 331                                   struct rte_eth_dcb_info *dcb_info);
 332 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 333 static void i40e_configure_registers(struct i40e_hw *hw);
 334 static void i40e_hw_init(struct rte_eth_dev *dev);
 335 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 336 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 337                                                      uint16_t seid,
 338                                                      uint16_t rule_type,
 339                                                      uint16_t *entries,
 340                                                      uint16_t count,
 341                                                      uint16_t rule_id);
 342 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 343                         struct rte_eth_mirror_conf *mirror_conf,
 344                         uint8_t sw_id, uint8_t on);
 345 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 346
 347 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 348 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 349 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp,
 351                                            uint32_t flags);
 352 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 353                                            struct timespec *timestamp);
 354 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 355
 356 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 357
 358 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 359                                    struct timespec *timestamp);
 360 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 361                                     const struct timespec *timestamp);
 362
 363 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 364                                          uint16_t queue_id);
 365 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 366                                           uint16_t queue_id);
 367
 368 static int i40e_get_regs(struct rte_eth_dev *dev,
 369                          struct rte_dev_reg_info *regs);
 370
 371 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 372
 373 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 374                            struct rte_dev_eeprom_info *eeprom);
 375
 376 static int i40e_get_module_info(struct rte_eth_dev *dev,
 377                                 struct rte_eth_dev_module_info *modinfo);
 378 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 379                                   struct rte_dev_eeprom_info *info);
 380
 381 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 382                                       struct ether_addr *mac_addr);
 383
 384 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 385
 386 static int i40e_ethertype_filter_convert(
 387         const struct rte_eth_ethertype_filter *input,
 388         struct i40e_ethertype_filter *filter);
 389 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 390                                    struct i40e_ethertype_filter *filter);
 391
 392 static int i40e_tunnel_filter_convert(
 393         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 394         struct i40e_tunnel_filter *tunnel_filter);
 395 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 396                                 struct i40e_tunnel_filter *tunnel_filter);
 397 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 398
 399 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 400 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 401 static void i40e_filter_restore(struct i40e_pf *pf);
 402 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 403
 404 int i40e_logtype_init;
 405 int i40e_logtype_driver;
 406
 407 static const char *const valid_keys[] = {
 408         ETH_I40E_FLOATING_VEB_ARG,
 409         ETH_I40E_FLOATING_VEB_LIST_ARG,
 410         ETH_I40E_SUPPORT_MULTI_DRIVER,
 411         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 412         NULL};
 413
 414 static const struct rte_pci_id pci_id_i40e_map[] = {
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 435         { .vendor_id = 0, /* sentinel */ },
 436 };
 437
 438 static const struct eth_dev_ops i40e_eth_dev_ops = {
 439         .dev_configure                = i40e_dev_configure,
 440         .dev_start                    = i40e_dev_start,
 441         .dev_stop                     = i40e_dev_stop,
 442         .dev_close                    = i40e_dev_close,
 443         .dev_reset                    = i40e_dev_reset,
 444         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 445         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 446         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 447         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 448         .dev_set_link_up              = i40e_dev_set_link_up,
 449         .dev_set_link_down            = i40e_dev_set_link_down,
 450         .link_update                  = i40e_dev_link_update,
 451         .stats_get                    = i40e_dev_stats_get,
 452         .xstats_get                   = i40e_dev_xstats_get,
 453         .xstats_get_names             = i40e_dev_xstats_get_names,
 454         .stats_reset                  = i40e_dev_stats_reset,
 455         .xstats_reset                 = i40e_dev_stats_reset,
 456         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 457         .fw_version_get               = i40e_fw_version_get,
 458         .dev_infos_get                = i40e_dev_info_get,
 459         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 460         .vlan_filter_set              = i40e_vlan_filter_set,
 461         .vlan_tpid_set                = i40e_vlan_tpid_set,
 462         .vlan_offload_set             = i40e_vlan_offload_set,
 463         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 464         .vlan_pvid_set                = i40e_vlan_pvid_set,
 465         .rx_queue_start               = i40e_dev_rx_queue_start,
 466         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 467         .tx_queue_start               = i40e_dev_tx_queue_start,
 468         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 469         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 470         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 471         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 472         .rx_queue_release             = i40e_dev_rx_queue_release,
 473         .rx_queue_count               = i40e_dev_rx_queue_count,
 474         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 475         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 476         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 477         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 478         .tx_queue_release             = i40e_dev_tx_queue_release,
 479         .dev_led_on                   = i40e_dev_led_on,
 480         .dev_led_off                  = i40e_dev_led_off,
 481         .flow_ctrl_get                = i40e_flow_ctrl_get,
 482         .flow_ctrl_set                = i40e_flow_ctrl_set,
 483         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 484         .mac_addr_add                 = i40e_macaddr_add,
 485         .mac_addr_remove              = i40e_macaddr_remove,
 486         .reta_update                  = i40e_dev_rss_reta_update,
 487         .reta_query                   = i40e_dev_rss_reta_query,
 488         .rss_hash_update              = i40e_dev_rss_hash_update,
 489         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 490         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 491         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 492         .filter_ctrl                  = i40e_dev_filter_ctrl,
 493         .rxq_info_get                 = i40e_rxq_info_get,
 494         .txq_info_get                 = i40e_txq_info_get,
 495         .mirror_rule_set              = i40e_mirror_rule_set,
 496         .mirror_rule_reset            = i40e_mirror_rule_reset,
 497         .timesync_enable              = i40e_timesync_enable,
 498         .timesync_disable             = i40e_timesync_disable,
 499         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 500         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 501         .get_dcb_info                 = i40e_dev_get_dcb_info,
 502         .timesync_adjust_time         = i40e_timesync_adjust_time,
 503         .timesync_read_time           = i40e_timesync_read_time,
 504         .timesync_write_time          = i40e_timesync_write_time,
 505         .get_reg                      = i40e_get_regs,
 506         .get_eeprom_length            = i40e_get_eeprom_length,
 507         .get_eeprom                   = i40e_get_eeprom,
 508         .get_module_info              = i40e_get_module_info,
 509         .get_module_eeprom            = i40e_get_module_eeprom,
 510         .mac_addr_set                 = i40e_set_default_mac_addr,
 511         .mtu_set                      = i40e_dev_mtu_set,
 512         .tm_ops_get                   = i40e_tm_ops_get,
 513 };
 514
 515 /* store statistics names and its offset in stats structure */
 516 struct rte_i40e_xstats_name_off {
 517         char name[RTE_ETH_XSTATS_NAME_SIZE];
 518         unsigned offset;
 519 };
 520
 521 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 522         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 523         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 524         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 525         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 526         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 527                 rx_unknown_protocol)},
 528         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 529         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 530         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 531         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 532 };
 533
 534 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 535                 sizeof(rte_i40e_stats_strings[0]))
 536
 537 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 538         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 539                 tx_dropped_link_down)},
 540         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 541         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 542                 illegal_bytes)},
 543         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 544         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 545                 mac_local_faults)},
 546         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 547                 mac_remote_faults)},
 548         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 549                 rx_length_errors)},
 550         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 551         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 552         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 553         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 554         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 555         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 556                 rx_size_127)},
 557         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 558                 rx_size_255)},
 559         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_511)},
 561         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_1023)},
 563         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_1522)},
 565         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_big)},
 567         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 568                 rx_undersize)},
 569         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 570                 rx_oversize)},
 571         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 572                 mac_short_packet_dropped)},
 573         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_fragments)},
 575         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 576         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 577         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 578                 tx_size_127)},
 579         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 580                 tx_size_255)},
 581         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_511)},
 583         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_1023)},
 585         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_1522)},
 587         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_big)},
 589         {"rx_flow_director_atr_match_packets",
 590                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 591         {"rx_flow_director_sb_match_packets",
 592                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 593         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 594                 tx_lpi_status)},
 595         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 596                 rx_lpi_status)},
 597         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 598                 tx_lpi_count)},
 599         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 600                 rx_lpi_count)},
 601 };
 602
 603 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 604                 sizeof(rte_i40e_hw_port_strings[0]))
 605
 606 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 607         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 608                 priority_xon_rx)},
 609         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xoff_rx)},
 611 };
 612
 613 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 614                 sizeof(rte_i40e_rxq_prio_strings[0]))
 615
 616 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 617         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 618                 priority_xon_tx)},
 619         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xoff_tx)},
 621         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xon_2_xoff)},
 623 };
 624
 625 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 626                 sizeof(rte_i40e_txq_prio_strings[0]))
 627
 628 static int
 629 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 630         struct rte_pci_device *pci_dev)
 631 {
 632         char name[RTE_ETH_NAME_MAX_LEN];
 633         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 634         int i, retval;
 635
 636         if (pci_dev->device.devargs) {
 637                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 638                                 &eth_da);
 639                 if (retval)
 640                         return retval;
 641         }
 642
 643         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 644                 sizeof(struct i40e_adapter),
 645                 eth_dev_pci_specific_init, pci_dev,
 646                 eth_i40e_dev_init, NULL);
 647
 648         if (retval || eth_da.nb_representor_ports < 1)
 649                 return retval;
 650
 651         /* probe VF representor ports */
 652         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 653                 pci_dev->device.name);
 654
 655         if (pf_ethdev == NULL)
 656                 return -ENODEV;
 657
 658         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 659                 struct i40e_vf_representor representor = {
 660                         .vf_id = eth_da.representor_ports[i],
 661                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 662                                 pf_ethdev->data->dev_private)->switch_domain_id,
 663                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 664                                 pf_ethdev->data->dev_private)
 665                 };
 666
 667                 /* representor port net_bdf_port */
 668                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 669                         pci_dev->device.name, eth_da.representor_ports[i]);
 670
 671                 retval = rte_eth_dev_create(&pci_dev->device, name,
 672                         sizeof(struct i40e_vf_representor), NULL, NULL,
 673                         i40e_vf_representor_init, &representor);
 674
 675                 if (retval)
 676                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 677                                 "representor %s.", name);
 678         }
 679
 680         return 0;
 681 }
 682
 683 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 684 {
 685         struct rte_eth_dev *ethdev;
 686
 687         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 688         if (!ethdev)
 689                 return -ENODEV;
 690
 691
 692         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 693                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 694         else
 695                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 696 }
 697
 698 static struct rte_pci_driver rte_i40e_pmd = {
 699         .id_table = pci_id_i40e_map,
 700         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 701                      RTE_PCI_DRV_IOVA_AS_VA,
 702         .probe = eth_i40e_pci_probe,
 703         .remove = eth_i40e_pci_remove,
 704 };
 705
 706 static inline void
 707 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 708                          uint32_t reg_val)
 709 {
 710         uint32_t ori_reg_val;
 711         struct rte_eth_dev *dev;
 712
 713         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 714         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 715         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 716         if (ori_reg_val != reg_val)
 717                 PMD_DRV_LOG(WARNING,
 718                             "i40e device %s changed global register [0x%08x]."
 719                             " original: 0x%08x, new: 0x%08x",
 720                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 721 }
 722
 723 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 724 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 725 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 726
 727 #ifndef I40E_GLQF_ORT
 728 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 729 #endif
 730 #ifndef I40E_GLQF_PIT
 731 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 732 #endif
 733 #ifndef I40E_GLQF_L3_MAP
 734 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 735 #endif
 736
 737 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 738 {
 739         /*
 740          * Initialize registers for parsing packet type of QinQ
 741          * This should be removed from code once proper
 742          * configuration API is added to avoid configuration conflicts
 743          * between ports of the same device.
 744          */
 745         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 746         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 747 }
 748
 749 static inline void i40e_config_automask(struct i40e_pf *pf)
 750 {
 751         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 752         uint32_t val;
 753
 754         /* INTENA flag is not auto-cleared for interrupt */
 755         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 756         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 757                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 758
 759         /* If support multi-driver, PF will use INT0. */
 760         if (!pf->support_multi_driver)
 761                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 762
 763         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 764 }
 765
 766 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 767
 768 /*
 769  * Add a ethertype filter to drop all flow control frames transmitted
 770  * from VSIs.
 771 */
 772 static void
 773 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 774 {
 775         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 776         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 777                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 778                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 779         int ret;
 780
 781         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 782                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 783                                 pf->main_vsi_seid, 0,
 784                                 TRUE, NULL, NULL);
 785         if (ret)
 786                 PMD_INIT_LOG(ERR,
 787                         "Failed to add filter to drop flow control frames from VSIs.");
 788 }
 789
 790 static int
 791 floating_veb_list_handler(__rte_unused const char *key,
 792                           const char *floating_veb_value,
 793                           void *opaque)
 794 {
 795         int idx = 0;
 796         unsigned int count = 0;
 797         char *end = NULL;
 798         int min, max;
 799         bool *vf_floating_veb = opaque;
 800
 801         while (isblank(*floating_veb_value))
 802                 floating_veb_value++;
 803
 804         /* Reset floating VEB configuration for VFs */
 805         for (idx = 0; idx < I40E_MAX_VF; idx++)
 806                 vf_floating_veb[idx] = false;
 807
 808         min = I40E_MAX_VF;
 809         do {
 810                 while (isblank(*floating_veb_value))
 811                         floating_veb_value++;
 812                 if (*floating_veb_value == '\0')
 813                         return -1;
 814                 errno = 0;
 815                 idx = strtoul(floating_veb_value, &end, 10);
 816                 if (errno || end == NULL)
 817                         return -1;
 818                 while (isblank(*end))
 819                         end++;
 820                 if (*end == '-') {
 821                         min = idx;
 822                 } else if ((*end == ';') || (*end == '\0')) {
 823                         max = idx;
 824                         if (min == I40E_MAX_VF)
 825                                 min = idx;
 826                         if (max >= I40E_MAX_VF)
 827                                 max = I40E_MAX_VF - 1;
 828                         for (idx = min; idx <= max; idx++) {
 829                                 vf_floating_veb[idx] = true;
 830                                 count++;
 831                         }
 832                         min = I40E_MAX_VF;
 833                 } else {
 834                         return -1;
 835                 }
 836                 floating_veb_value = end + 1;
 837         } while (*end != '\0');
 838
 839         if (count == 0)
 840                 return -1;
 841
 842         return 0;
 843 }
 844
 845 static void
 846 config_vf_floating_veb(struct rte_devargs *devargs,
 847                        uint16_t floating_veb,
 848                        bool *vf_floating_veb)
 849 {
 850         struct rte_kvargs *kvlist;
 851         int i;
 852         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 853
 854         if (!floating_veb)
 855                 return;
 856         /* All the VFs attach to the floating VEB by default
 857          * when the floating VEB is enabled.
 858          */
 859         for (i = 0; i < I40E_MAX_VF; i++)
 860                 vf_floating_veb[i] = true;
 861
 862         if (devargs == NULL)
 863                 return;
 864
 865         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 866         if (kvlist == NULL)
 867                 return;
 868
 869         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 870                 rte_kvargs_free(kvlist);
 871                 return;
 872         }
 873         /* When the floating_veb_list parameter exists, all the VFs
 874          * will attach to the legacy VEB firstly, then configure VFs
 875          * to the floating VEB according to the floating_veb_list.
 876          */
 877         if (rte_kvargs_process(kvlist, floating_veb_list,
 878                                floating_veb_list_handler,
 879                                vf_floating_veb) < 0) {
 880                 rte_kvargs_free(kvlist);
 881                 return;
 882         }
 883         rte_kvargs_free(kvlist);
 884 }
 885
 886 static int
 887 i40e_check_floating_handler(__rte_unused const char *key,
 888                             const char *value,
 889                             __rte_unused void *opaque)
 890 {
 891         if (strcmp(value, "1"))
 892                 return -1;
 893
 894         return 0;
 895 }
 896
 897 static int
 898 is_floating_veb_supported(struct rte_devargs *devargs)
 899 {
 900         struct rte_kvargs *kvlist;
 901         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 902
 903         if (devargs == NULL)
 904                 return 0;
 905
 906         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 907         if (kvlist == NULL)
 908                 return 0;
 909
 910         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 911                 rte_kvargs_free(kvlist);
 912                 return 0;
 913         }
 914         /* Floating VEB is enabled when there's key-value:
 915          * enable_floating_veb=1
 916          */
 917         if (rte_kvargs_process(kvlist, floating_veb_key,
 918                                i40e_check_floating_handler, NULL) < 0) {
 919                 rte_kvargs_free(kvlist);
 920                 return 0;
 921         }
 922         rte_kvargs_free(kvlist);
 923
 924         return 1;
 925 }
 926
 927 static void
 928 config_floating_veb(struct rte_eth_dev *dev)
 929 {
 930         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 931         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 933
 934         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 935
 936         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 937                 pf->floating_veb =
 938                         is_floating_veb_supported(pci_dev->device.devargs);
 939                 config_vf_floating_veb(pci_dev->device.devargs,
 940                                        pf->floating_veb,
 941                                        pf->floating_veb_list);
 942         } else {
 943                 pf->floating_veb = false;
 944         }
 945 }
 946
 947 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 948 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 949
 950 static int
 951 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 952 {
 953         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 954         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 955         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 956         int ret;
 957
 958         struct rte_hash_parameters ethertype_hash_params = {
 959                 .name = ethertype_hash_name,
 960                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 961                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 962                 .hash_func = rte_hash_crc,
 963                 .hash_func_init_val = 0,
 964                 .socket_id = rte_socket_id(),
 965         };
 966
 967         /* Initialize ethertype filter rule list and hash */
 968         TAILQ_INIT(&ethertype_rule->ethertype_list);
 969         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 970                  "ethertype_%s", dev->device->name);
 971         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 972         if (!ethertype_rule->hash_table) {
 973                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 974                 return -EINVAL;
 975         }
 976         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 977                                        sizeof(struct i40e_ethertype_filter *) *
 978                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 979                                        0);
 980         if (!ethertype_rule->hash_map) {
 981                 PMD_INIT_LOG(ERR,
 982                              "Failed to allocate memory for ethertype hash map!");
 983                 ret = -ENOMEM;
 984                 goto err_ethertype_hash_map_alloc;
 985         }
 986
 987         return 0;
 988
 989 err_ethertype_hash_map_alloc:
 990         rte_hash_free(ethertype_rule->hash_table);
 991
 992         return ret;
 993 }
 994
 995 static int
 996 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 997 {
 998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 999         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1000         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1001         int ret;
1002
1003         struct rte_hash_parameters tunnel_hash_params = {
1004                 .name = tunnel_hash_name,
1005                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1006                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1007                 .hash_func = rte_hash_crc,
1008                 .hash_func_init_val = 0,
1009                 .socket_id = rte_socket_id(),
1010         };
1011
1012         /* Initialize tunnel filter rule list and hash */
1013         TAILQ_INIT(&tunnel_rule->tunnel_list);
1014         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1015                  "tunnel_%s", dev->device->name);
1016         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1017         if (!tunnel_rule->hash_table) {
1018                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1019                 return -EINVAL;
1020         }
1021         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1022                                     sizeof(struct i40e_tunnel_filter *) *
1023                                     I40E_MAX_TUNNEL_FILTER_NUM,
1024                                     0);
1025         if (!tunnel_rule->hash_map) {
1026                 PMD_INIT_LOG(ERR,
1027                              "Failed to allocate memory for tunnel hash map!");
1028                 ret = -ENOMEM;
1029                 goto err_tunnel_hash_map_alloc;
1030         }
1031
1032         return 0;
1033
1034 err_tunnel_hash_map_alloc:
1035         rte_hash_free(tunnel_rule->hash_table);
1036
1037         return ret;
1038 }
1039
1040 static int
1041 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1042 {
1043         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1044         struct i40e_fdir_info *fdir_info = &pf->fdir;
1045         char fdir_hash_name[RTE_HASH_NAMESIZE];
1046         int ret;
1047
1048         struct rte_hash_parameters fdir_hash_params = {
1049                 .name = fdir_hash_name,
1050                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1051                 .key_len = sizeof(struct i40e_fdir_input),
1052                 .hash_func = rte_hash_crc,
1053                 .hash_func_init_val = 0,
1054                 .socket_id = rte_socket_id(),
1055         };
1056
1057         /* Initialize flow director filter rule list and hash */
1058         TAILQ_INIT(&fdir_info->fdir_list);
1059         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1060                  "fdir_%s", dev->device->name);
1061         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1062         if (!fdir_info->hash_table) {
1063                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1064                 return -EINVAL;
1065         }
1066         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1067                                           sizeof(struct i40e_fdir_filter *) *
1068                                           I40E_MAX_FDIR_FILTER_NUM,
1069                                           0);
1070         if (!fdir_info->hash_map) {
1071                 PMD_INIT_LOG(ERR,
1072                              "Failed to allocate memory for fdir hash map!");
1073                 ret = -ENOMEM;
1074                 goto err_fdir_hash_map_alloc;
1075         }
1076         return 0;
1077
1078 err_fdir_hash_map_alloc:
1079         rte_hash_free(fdir_info->hash_table);
1080
1081         return ret;
1082 }
1083
1084 static void
1085 i40e_init_customized_info(struct i40e_pf *pf)
1086 {
1087         int i;
1088
1089         /* Initialize customized pctype */
1090         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1091                 pf->customized_pctype[i].index = i;
1092                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1093                 pf->customized_pctype[i].valid = false;
1094         }
1095
1096         pf->gtp_support = false;
1097 }
1098
1099 void
1100 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1101 {
1102         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1103         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1104         struct i40e_queue_regions *info = &pf->queue_region;
1105         uint16_t i;
1106
1107         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1108                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1109
1110         memset(info, 0, sizeof(struct i40e_queue_regions));
1111 }
1112
1113 static int
1114 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1115                                const char *value,
1116                                void *opaque)
1117 {
1118         struct i40e_pf *pf;
1119         unsigned long support_multi_driver;
1120         char *end;
1121
1122         pf = (struct i40e_pf *)opaque;
1123
1124         errno = 0;
1125         support_multi_driver = strtoul(value, &end, 10);
1126         if (errno != 0 || end == value || *end != 0) {
1127                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1128                 return -(EINVAL);
1129         }
1130
1131         if (support_multi_driver == 1 || support_multi_driver == 0)
1132                 pf->support_multi_driver = (bool)support_multi_driver;
1133         else
1134                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1135                             "enable global configuration by default."
1136                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1137         return 0;
1138 }
1139
1140 static int
1141 i40e_support_multi_driver(struct rte_eth_dev *dev)
1142 {
1143         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1144         struct rte_kvargs *kvlist;
1145         int kvargs_count;
1146
1147         /* Enable global configuration by default */
1148         pf->support_multi_driver = false;
1149
1150         if (!dev->device->devargs)
1151                 return 0;
1152
1153         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1154         if (!kvlist)
1155                 return -EINVAL;
1156
1157         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1158         if (!kvargs_count) {
1159                 rte_kvargs_free(kvlist);
1160                 return 0;
1161         }
1162
1163         if (kvargs_count > 1)
1164                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1165                             "the first invalid or last valid one is used !",
1166                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1167
1168         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1169                                i40e_parse_multi_drv_handler, pf) < 0) {
1170                 rte_kvargs_free(kvlist);
1171                 return -EINVAL;
1172         }
1173
1174         rte_kvargs_free(kvlist);
1175         return 0;
1176 }
1177
1178 static int
1179 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1180                                     uint32_t reg_addr, uint64_t reg_val,
1181                                     struct i40e_asq_cmd_details *cmd_details)
1182 {
1183         uint64_t ori_reg_val;
1184         struct rte_eth_dev *dev;
1185         int ret;
1186
1187         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1188         if (ret != I40E_SUCCESS) {
1189                 PMD_DRV_LOG(ERR,
1190                             "Fail to debug read from 0x%08x",
1191                             reg_addr);
1192                 return -EIO;
1193         }
1194         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1195
1196         if (ori_reg_val != reg_val)
1197                 PMD_DRV_LOG(WARNING,
1198                             "i40e device %s changed global register [0x%08x]."
1199                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1200                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1201
1202         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1203 }
1204
1205 #define I40E_ALARM_INTERVAL 50000 /* us */
1206
1207 static int
1208 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1209 {
1210         struct rte_pci_device *pci_dev;
1211         struct rte_intr_handle *intr_handle;
1212         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1213         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1214         struct i40e_vsi *vsi;
1215         int ret;
1216         uint32_t len;
1217         uint8_t aq_fail = 0;
1218
1219         PMD_INIT_FUNC_TRACE();
1220
1221         dev->dev_ops = &i40e_eth_dev_ops;
1222         dev->rx_pkt_burst = i40e_recv_pkts;
1223         dev->tx_pkt_burst = i40e_xmit_pkts;
1224         dev->tx_pkt_prepare = i40e_prep_pkts;
1225
1226         /* for secondary processes, we don't initialise any further as primary
1227          * has already done this work. Only check we don't need a different
1228          * RX function */
1229         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1230                 i40e_set_rx_function(dev);
1231                 i40e_set_tx_function(dev);
1232                 return 0;
1233         }
1234         i40e_set_default_ptype_table(dev);
1235         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1236         intr_handle = &pci_dev->intr_handle;
1237
1238         rte_eth_copy_pci_info(dev, pci_dev);
1239
1240         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1241         pf->adapter->eth_dev = dev;
1242         pf->dev_data = dev->data;
1243
1244         hw->back = I40E_PF_TO_ADAPTER(pf);
1245         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1246         if (!hw->hw_addr) {
1247                 PMD_INIT_LOG(ERR,
1248                         "Hardware is not available, as address is NULL");
1249                 return -ENODEV;
1250         }
1251
1252         hw->vendor_id = pci_dev->id.vendor_id;
1253         hw->device_id = pci_dev->id.device_id;
1254         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1255         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1256         hw->bus.device = pci_dev->addr.devid;
1257         hw->bus.func = pci_dev->addr.function;
1258         hw->adapter_stopped = 0;
1259
1260         /*
1261          * Switch Tag value should not be identical to either the First Tag
1262          * or Second Tag values. So set something other than common Ethertype
1263          * for internal switching.
1264          */
1265         hw->switch_tag = 0xffff;
1266
1267         /* Check if need to support multi-driver */
1268         i40e_support_multi_driver(dev);
1269
1270         /* Make sure all is clean before doing PF reset */
1271         i40e_clear_hw(hw);
1272
1273         /* Initialize the hardware */
1274         i40e_hw_init(dev);
1275
1276         /* Reset here to make sure all is clean for each PF */
1277         ret = i40e_pf_reset(hw);
1278         if (ret) {
1279                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1280                 return ret;
1281         }
1282
1283         /* Initialize the shared code (base driver) */
1284         ret = i40e_init_shared_code(hw);
1285         if (ret) {
1286                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1287                 return ret;
1288         }
1289
1290         i40e_config_automask(pf);
1291
1292         i40e_set_default_pctype_table(dev);
1293
1294         /*
1295          * To work around the NVM issue, initialize registers
1296          * for packet type of QinQ by software.
1297          * It should be removed once issues are fixed in NVM.
1298          */
1299         if (!pf->support_multi_driver)
1300                 i40e_GLQF_reg_init(hw);
1301
1302         /* Initialize the input set for filters (hash and fd) to default value */
1303         i40e_filter_input_set_init(pf);
1304
1305         /* Initialize the parameters for adminq */
1306         i40e_init_adminq_parameter(hw);
1307         ret = i40e_init_adminq(hw);
1308         if (ret != I40E_SUCCESS) {
1309                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1310                 return -EIO;
1311         }
1312         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1313                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1314                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1315                      ((hw->nvm.version >> 12) & 0xf),
1316                      ((hw->nvm.version >> 4) & 0xff),
1317                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1318
1319         /* initialise the L3_MAP register */
1320         if (!pf->support_multi_driver) {
1321                 ret = i40e_aq_debug_write_global_register(hw,
1322                                                    I40E_GLQF_L3_MAP(40),
1323                                                    0x00000028,  NULL);
1324                 if (ret)
1325                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1326                                      ret);
1327                 PMD_INIT_LOG(DEBUG,
1328                              "Global register 0x%08x is changed with 0x28",
1329                              I40E_GLQF_L3_MAP(40));
1330         }
1331
1332         /* Need the special FW version to support floating VEB */
1333         config_floating_veb(dev);
1334         /* Clear PXE mode */
1335         i40e_clear_pxe_mode(hw);
1336         i40e_dev_sync_phy_type(hw);
1337
1338         /*
1339          * On X710, performance number is far from the expectation on recent
1340          * firmware versions. The fix for this issue may not be integrated in
1341          * the following firmware version. So the workaround in software driver
1342          * is needed. It needs to modify the initial values of 3 internal only
1343          * registers. Note that the workaround can be removed when it is fixed
1344          * in firmware in the future.
1345          */
1346         i40e_configure_registers(hw);
1347
1348         /* Get hw capabilities */
1349         ret = i40e_get_cap(hw);
1350         if (ret != I40E_SUCCESS) {
1351                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1352                 goto err_get_capabilities;
1353         }
1354
1355         /* Initialize parameters for PF */
1356         ret = i40e_pf_parameter_init(dev);
1357         if (ret != 0) {
1358                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1359                 goto err_parameter_init;
1360         }
1361
1362         /* Initialize the queue management */
1363         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1364         if (ret < 0) {
1365                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1366                 goto err_qp_pool_init;
1367         }
1368         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1369                                 hw->func_caps.num_msix_vectors - 1);
1370         if (ret < 0) {
1371                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1372                 goto err_msix_pool_init;
1373         }
1374
1375         /* Initialize lan hmc */
1376         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1377                                 hw->func_caps.num_rx_qp, 0, 0);
1378         if (ret != I40E_SUCCESS) {
1379                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1380                 goto err_init_lan_hmc;
1381         }
1382
1383         /* Configure lan hmc */
1384         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1385         if (ret != I40E_SUCCESS) {
1386                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1387                 goto err_configure_lan_hmc;
1388         }
1389
1390         /* Get and check the mac address */
1391         i40e_get_mac_addr(hw, hw->mac.addr);
1392         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1393                 PMD_INIT_LOG(ERR, "mac address is not valid");
1394                 ret = -EIO;
1395                 goto err_get_mac_addr;
1396         }
1397         /* Copy the permanent MAC address */
1398         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1399                         (struct ether_addr *) hw->mac.perm_addr);
1400
1401         /* Disable flow control */
1402         hw->fc.requested_mode = I40E_FC_NONE;
1403         i40e_set_fc(hw, &aq_fail, TRUE);
1404
1405         /* Set the global registers with default ether type value */
1406         if (!pf->support_multi_driver) {
1407                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1408                                          ETHER_TYPE_VLAN);
1409                 if (ret != I40E_SUCCESS) {
1410                         PMD_INIT_LOG(ERR,
1411                                      "Failed to set the default outer "
1412                                      "VLAN ether type");
1413                         goto err_setup_pf_switch;
1414                 }
1415         }
1416
1417         /* PF setup, which includes VSI setup */
1418         ret = i40e_pf_setup(pf);
1419         if (ret) {
1420                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1421                 goto err_setup_pf_switch;
1422         }
1423
1424         /* reset all stats of the device, including pf and main vsi */
1425         i40e_dev_stats_reset(dev);
1426
1427         vsi = pf->main_vsi;
1428
1429         /* Disable double vlan by default */
1430         i40e_vsi_config_double_vlan(vsi, FALSE);
1431
1432         /* Disable S-TAG identification when floating_veb is disabled */
1433         if (!pf->floating_veb) {
1434                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1435                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1436                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1437                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1438                 }
1439         }
1440
1441         if (!vsi->max_macaddrs)
1442                 len = ETHER_ADDR_LEN;
1443         else
1444                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1445
1446         /* Should be after VSI initialized */
1447         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1448         if (!dev->data->mac_addrs) {
1449                 PMD_INIT_LOG(ERR,
1450                         "Failed to allocated memory for storing mac address");
1451                 goto err_mac_alloc;
1452         }
1453         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1454                                         &dev->data->mac_addrs[0]);
1455
1456         /* Init dcb to sw mode by default */
1457         ret = i40e_dcb_init_configure(dev, TRUE);
1458         if (ret != I40E_SUCCESS) {
1459                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1460                 pf->flags &= ~I40E_FLAG_DCB;
1461         }
1462         /* Update HW struct after DCB configuration */
1463         i40e_get_cap(hw);
1464
1465         /* initialize pf host driver to setup SRIOV resource if applicable */
1466         i40e_pf_host_init(dev);
1467
1468         /* register callback func to eal lib */
1469         rte_intr_callback_register(intr_handle,
1470                                    i40e_dev_interrupt_handler, dev);
1471
1472         /* configure and enable device interrupt */
1473         i40e_pf_config_irq0(hw, TRUE);
1474         i40e_pf_enable_irq0(hw);
1475
1476         /* enable uio intr after callback register */
1477         rte_intr_enable(intr_handle);
1478
1479         /* By default disable flexible payload in global configuration */
1480         if (!pf->support_multi_driver)
1481                 i40e_flex_payload_reg_set_default(hw);
1482
1483         /*
1484          * Add an ethertype filter to drop all flow control frames transmitted
1485          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1486          * frames to wire.
1487          */
1488         i40e_add_tx_flow_control_drop_filter(pf);
1489
1490         /* Set the max frame size to 0x2600 by default,
1491          * in case other drivers changed the default value.
1492          */
1493         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1494
1495         /* initialize mirror rule list */
1496         TAILQ_INIT(&pf->mirror_list);
1497
1498         /* initialize Traffic Manager configuration */
1499         i40e_tm_conf_init(dev);
1500
1501         /* Initialize customized information */
1502         i40e_init_customized_info(pf);
1503
1504         ret = i40e_init_ethtype_filter_list(dev);
1505         if (ret < 0)
1506                 goto err_init_ethtype_filter_list;
1507         ret = i40e_init_tunnel_filter_list(dev);
1508         if (ret < 0)
1509                 goto err_init_tunnel_filter_list;
1510         ret = i40e_init_fdir_filter_list(dev);
1511         if (ret < 0)
1512                 goto err_init_fdir_filter_list;
1513
1514         /* initialize queue region configuration */
1515         i40e_init_queue_region_conf(dev);
1516
1517         /* initialize rss configuration from rte_flow */
1518         memset(&pf->rss_info, 0,
1519                 sizeof(struct i40e_rte_flow_rss_conf));
1520
1521         return 0;
1522
1523 err_init_fdir_filter_list:
1524         rte_free(pf->tunnel.hash_table);
1525         rte_free(pf->tunnel.hash_map);
1526 err_init_tunnel_filter_list:
1527         rte_free(pf->ethertype.hash_table);
1528         rte_free(pf->ethertype.hash_map);
1529 err_init_ethtype_filter_list:
1530         rte_free(dev->data->mac_addrs);
1531 err_mac_alloc:
1532         i40e_vsi_release(pf->main_vsi);
1533 err_setup_pf_switch:
1534 err_get_mac_addr:
1535 err_configure_lan_hmc:
1536         (void)i40e_shutdown_lan_hmc(hw);
1537 err_init_lan_hmc:
1538         i40e_res_pool_destroy(&pf->msix_pool);
1539 err_msix_pool_init:
1540         i40e_res_pool_destroy(&pf->qp_pool);
1541 err_qp_pool_init:
1542 err_parameter_init:
1543 err_get_capabilities:
1544         (void)i40e_shutdown_adminq(hw);
1545
1546         return ret;
1547 }
1548
1549 static void
1550 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1551 {
1552         struct i40e_ethertype_filter *p_ethertype;
1553         struct i40e_ethertype_rule *ethertype_rule;
1554
1555         ethertype_rule = &pf->ethertype;
1556         /* Remove all ethertype filter rules and hash */
1557         if (ethertype_rule->hash_map)
1558                 rte_free(ethertype_rule->hash_map);
1559         if (ethertype_rule->hash_table)
1560                 rte_hash_free(ethertype_rule->hash_table);
1561
1562         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1563                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1564                              p_ethertype, rules);
1565                 rte_free(p_ethertype);
1566         }
1567 }
1568
1569 static void
1570 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1571 {
1572         struct i40e_tunnel_filter *p_tunnel;
1573         struct i40e_tunnel_rule *tunnel_rule;
1574
1575         tunnel_rule = &pf->tunnel;
1576         /* Remove all tunnel director rules and hash */
1577         if (tunnel_rule->hash_map)
1578                 rte_free(tunnel_rule->hash_map);
1579         if (tunnel_rule->hash_table)
1580                 rte_hash_free(tunnel_rule->hash_table);
1581
1582         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1583                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1584                 rte_free(p_tunnel);
1585         }
1586 }
1587
1588 static void
1589 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1590 {
1591         struct i40e_fdir_filter *p_fdir;
1592         struct i40e_fdir_info *fdir_info;
1593
1594         fdir_info = &pf->fdir;
1595         /* Remove all flow director rules and hash */
1596         if (fdir_info->hash_map)
1597                 rte_free(fdir_info->hash_map);
1598         if (fdir_info->hash_table)
1599                 rte_hash_free(fdir_info->hash_table);
1600
1601         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1602                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1603                 rte_free(p_fdir);
1604         }
1605 }
1606
1607 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1608 {
1609         /*
1610          * Disable by default flexible payload
1611          * for corresponding L2/L3/L4 layers.
1612          */
1613         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1614         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1615         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1616 }
1617
1618 static int
1619 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1620 {
1621         struct i40e_pf *pf;
1622         struct rte_pci_device *pci_dev;
1623         struct rte_intr_handle *intr_handle;
1624         struct i40e_hw *hw;
1625         struct i40e_filter_control_settings settings;
1626         struct rte_flow *p_flow;
1627         int ret;
1628         uint8_t aq_fail = 0;
1629         int retries = 0;
1630
1631         PMD_INIT_FUNC_TRACE();
1632
1633         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1634                 return 0;
1635
1636         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1637         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1638         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1639         intr_handle = &pci_dev->intr_handle;
1640
1641         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1642         if (ret)
1643                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1644
1645         if (hw->adapter_stopped == 0)
1646                 i40e_dev_close(dev);
1647
1648         dev->dev_ops = NULL;
1649         dev->rx_pkt_burst = NULL;
1650         dev->tx_pkt_burst = NULL;
1651
1652         /* Clear PXE mode */
1653         i40e_clear_pxe_mode(hw);
1654
1655         /* Unconfigure filter control */
1656         memset(&settings, 0, sizeof(settings));
1657         ret = i40e_set_filter_control(hw, &settings);
1658         if (ret)
1659                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1660                                         ret);
1661
1662         /* Disable flow control */
1663         hw->fc.requested_mode = I40E_FC_NONE;
1664         i40e_set_fc(hw, &aq_fail, TRUE);
1665
1666         /* uninitialize pf host driver */
1667         i40e_pf_host_uninit(dev);
1668
1669         rte_free(dev->data->mac_addrs);
1670         dev->data->mac_addrs = NULL;
1671
1672         /* disable uio intr before callback unregister */
1673         rte_intr_disable(intr_handle);
1674
1675         /* unregister callback func to eal lib */
1676         do {
1677                 ret = rte_intr_callback_unregister(intr_handle,
1678                                 i40e_dev_interrupt_handler, dev);
1679                 if (ret >= 0) {
1680                         break;
1681                 } else if (ret != -EAGAIN) {
1682                         PMD_INIT_LOG(ERR,
1683                                  "intr callback unregister failed: %d",
1684                                  ret);
1685                         return ret;
1686                 }
1687                 i40e_msec_delay(500);
1688         } while (retries++ < 5);
1689
1690         i40e_rm_ethtype_filter_list(pf);
1691         i40e_rm_tunnel_filter_list(pf);
1692         i40e_rm_fdir_filter_list(pf);
1693
1694         /* Remove all flows */
1695         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1696                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1697                 rte_free(p_flow);
1698         }
1699
1700         /* Remove all Traffic Manager configuration */
1701         i40e_tm_conf_uninit(dev);
1702
1703         return 0;
1704 }
1705
1706 static int
1707 i40e_dev_configure(struct rte_eth_dev *dev)
1708 {
1709         struct i40e_adapter *ad =
1710                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1711         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1712         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1713         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1714         int i, ret;
1715
1716         ret = i40e_dev_sync_phy_type(hw);
1717         if (ret)
1718                 return ret;
1719
1720         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1721          * bulk allocation or vector Rx preconditions we will reset it.
1722          */
1723         ad->rx_bulk_alloc_allowed = true;
1724         ad->rx_vec_allowed = true;
1725         ad->tx_simple_allowed = true;
1726         ad->tx_vec_allowed = true;
1727
1728         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1729                 ret = i40e_fdir_setup(pf);
1730                 if (ret != I40E_SUCCESS) {
1731                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1732                         return -ENOTSUP;
1733                 }
1734                 ret = i40e_fdir_configure(dev);
1735                 if (ret < 0) {
1736                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1737                         goto err;
1738                 }
1739         } else
1740                 i40e_fdir_teardown(pf);
1741
1742         ret = i40e_dev_init_vlan(dev);
1743         if (ret < 0)
1744                 goto err;
1745
1746         /* VMDQ setup.
1747          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1748          *  RSS setting have different requirements.
1749          *  General PMD driver call sequence are NIC init, configure,
1750          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1751          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1752          *  applicable. So, VMDQ setting has to be done before
1753          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1754          *  For RSS setting, it will try to calculate actual configured RX queue
1755          *  number, which will be available after rx_queue_setup(). dev_start()
1756          *  function is good to place RSS setup.
1757          */
1758         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1759                 ret = i40e_vmdq_setup(dev);
1760                 if (ret)
1761                         goto err;
1762         }
1763
1764         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1765                 ret = i40e_dcb_setup(dev);
1766                 if (ret) {
1767                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1768                         goto err_dcb;
1769                 }
1770         }
1771
1772         TAILQ_INIT(&pf->flow_list);
1773
1774         return 0;
1775
1776 err_dcb:
1777         /* need to release vmdq resource if exists */
1778         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1779                 i40e_vsi_release(pf->vmdq[i].vsi);
1780                 pf->vmdq[i].vsi = NULL;
1781         }
1782         rte_free(pf->vmdq);
1783         pf->vmdq = NULL;
1784 err:
1785         /* need to release fdir resource if exists */
1786         i40e_fdir_teardown(pf);
1787         return ret;
1788 }
1789
1790 void
1791 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1792 {
1793         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1794         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1795         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1796         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1797         uint16_t msix_vect = vsi->msix_intr;
1798         uint16_t i;
1799
1800         for (i = 0; i < vsi->nb_qps; i++) {
1801                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1802                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1803                 rte_wmb();
1804         }
1805
1806         if (vsi->type != I40E_VSI_SRIOV) {
1807                 if (!rte_intr_allow_others(intr_handle)) {
1808                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1809                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1810                         I40E_WRITE_REG(hw,
1811                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1812                                        0);
1813                 } else {
1814                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1815                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1816                         I40E_WRITE_REG(hw,
1817                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1818                                                        msix_vect - 1), 0);
1819                 }
1820         } else {
1821                 uint32_t reg;
1822                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1823                         vsi->user_param + (msix_vect - 1);
1824
1825                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1826                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1827         }
1828         I40E_WRITE_FLUSH(hw);
1829 }
1830
1831 static void
1832 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1833                        int base_queue, int nb_queue,
1834                        uint16_t itr_idx)
1835 {
1836         int i;
1837         uint32_t val;
1838         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1839         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1840
1841         /* Bind all RX queues to allocated MSIX interrupt */
1842         for (i = 0; i < nb_queue; i++) {
1843                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1844                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1845                         ((base_queue + i + 1) <<
1846                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1847                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1848                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1849
1850                 if (i == nb_queue - 1)
1851                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1852                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1853         }
1854
1855         /* Write first RX queue to Link list register as the head element */
1856         if (vsi->type != I40E_VSI_SRIOV) {
1857                 uint16_t interval =
1858                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1859
1860                 if (msix_vect == I40E_MISC_VEC_ID) {
1861                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1862                                        (base_queue <<
1863                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1864                                        (0x0 <<
1865                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1866                         I40E_WRITE_REG(hw,
1867                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1868                                        interval);
1869                 } else {
1870                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1871                                        (base_queue <<
1872                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1873                                        (0x0 <<
1874                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1875                         I40E_WRITE_REG(hw,
1876                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1877                                                        msix_vect - 1),
1878                                        interval);
1879                 }
1880         } else {
1881                 uint32_t reg;
1882
1883                 if (msix_vect == I40E_MISC_VEC_ID) {
1884                         I40E_WRITE_REG(hw,
1885                                        I40E_VPINT_LNKLST0(vsi->user_param),
1886                                        (base_queue <<
1887                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1888                                        (0x0 <<
1889                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1890                 } else {
1891                         /* num_msix_vectors_vf needs to minus irq0 */
1892                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1893                                 vsi->user_param + (msix_vect - 1);
1894
1895                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1896                                        (base_queue <<
1897                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1898                                        (0x0 <<
1899                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1900                 }
1901         }
1902
1903         I40E_WRITE_FLUSH(hw);
1904 }
1905
1906 void
1907 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1908 {
1909         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1910         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1911         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1912         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1913         uint16_t msix_vect = vsi->msix_intr;
1914         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1915         uint16_t queue_idx = 0;
1916         int record = 0;
1917         int i;
1918
1919         for (i = 0; i < vsi->nb_qps; i++) {
1920                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1921                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1922         }
1923
1924         /* VF bind interrupt */
1925         if (vsi->type == I40E_VSI_SRIOV) {
1926                 __vsi_queues_bind_intr(vsi, msix_vect,
1927                                        vsi->base_queue, vsi->nb_qps,
1928                                        itr_idx);
1929                 return;
1930         }
1931
1932         /* PF & VMDq bind interrupt */
1933         if (rte_intr_dp_is_en(intr_handle)) {
1934                 if (vsi->type == I40E_VSI_MAIN) {
1935                         queue_idx = 0;
1936                         record = 1;
1937                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1938                         struct i40e_vsi *main_vsi =
1939                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1940                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1941                         record = 1;
1942                 }
1943         }
1944
1945         for (i = 0; i < vsi->nb_used_qps; i++) {
1946                 if (nb_msix <= 1) {
1947                         if (!rte_intr_allow_others(intr_handle))
1948                                 /* allow to share MISC_VEC_ID */
1949                                 msix_vect = I40E_MISC_VEC_ID;
1950
1951                         /* no enough msix_vect, map all to one */
1952                         __vsi_queues_bind_intr(vsi, msix_vect,
1953                                                vsi->base_queue + i,
1954                                                vsi->nb_used_qps - i,
1955                                                itr_idx);
1956                         for (; !!record && i < vsi->nb_used_qps; i++)
1957                                 intr_handle->intr_vec[queue_idx + i] =
1958                                         msix_vect;
1959                         break;
1960                 }
1961                 /* 1:1 queue/msix_vect mapping */
1962                 __vsi_queues_bind_intr(vsi, msix_vect,
1963                                        vsi->base_queue + i, 1,
1964                                        itr_idx);
1965                 if (!!record)
1966                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1967
1968                 msix_vect++;
1969                 nb_msix--;
1970         }
1971 }
1972
1973 static void
1974 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1975 {
1976         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1977         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1978         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1979         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1980         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1981         uint16_t msix_intr, i;
1982
1983         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1984                 for (i = 0; i < vsi->nb_msix; i++) {
1985                         msix_intr = vsi->msix_intr + i;
1986                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1987                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1988                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1989                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1990                 }
1991         else
1992                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1993                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1994                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1995                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1996
1997         I40E_WRITE_FLUSH(hw);
1998 }
1999
2000 static void
2001 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2002 {
2003         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2004         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2005         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2006         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2007         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2008         uint16_t msix_intr, i;
2009
2010         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2011                 for (i = 0; i < vsi->nb_msix; i++) {
2012                         msix_intr = vsi->msix_intr + i;
2013                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2014                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2015                 }
2016         else
2017                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2018                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2019
2020         I40E_WRITE_FLUSH(hw);
2021 }
2022
2023 static inline uint8_t
2024 i40e_parse_link_speeds(uint16_t link_speeds)
2025 {
2026         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2027
2028         if (link_speeds & ETH_LINK_SPEED_40G)
2029                 link_speed |= I40E_LINK_SPEED_40GB;
2030         if (link_speeds & ETH_LINK_SPEED_25G)
2031                 link_speed |= I40E_LINK_SPEED_25GB;
2032         if (link_speeds & ETH_LINK_SPEED_20G)
2033                 link_speed |= I40E_LINK_SPEED_20GB;
2034         if (link_speeds & ETH_LINK_SPEED_10G)
2035                 link_speed |= I40E_LINK_SPEED_10GB;
2036         if (link_speeds & ETH_LINK_SPEED_1G)
2037                 link_speed |= I40E_LINK_SPEED_1GB;
2038         if (link_speeds & ETH_LINK_SPEED_100M)
2039                 link_speed |= I40E_LINK_SPEED_100MB;
2040
2041         return link_speed;
2042 }
2043
2044 static int
2045 i40e_phy_conf_link(struct i40e_hw *hw,
2046                    uint8_t abilities,
2047                    uint8_t force_speed,
2048                    bool is_up)
2049 {
2050         enum i40e_status_code status;
2051         struct i40e_aq_get_phy_abilities_resp phy_ab;
2052         struct i40e_aq_set_phy_config phy_conf;
2053         enum i40e_aq_phy_type cnt;
2054         uint8_t avail_speed;
2055         uint32_t phy_type_mask = 0;
2056
2057         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2058                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2059                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2060                         I40E_AQ_PHY_FLAG_LOW_POWER;
2061         int ret = -ENOTSUP;
2062
2063         /* To get phy capabilities of available speeds. */
2064         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2065                                               NULL);
2066         if (status) {
2067                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2068                                 status);
2069                 return ret;
2070         }
2071         avail_speed = phy_ab.link_speed;
2072
2073         /* To get the current phy config. */
2074         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2075                                               NULL);
2076         if (status) {
2077                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2078                                 status);
2079                 return ret;
2080         }
2081
2082         /* If link needs to go up and it is in autoneg mode the speed is OK,
2083          * no need to set up again.
2084          */
2085         if (is_up && phy_ab.phy_type != 0 &&
2086                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2087                      phy_ab.link_speed != 0)
2088                 return I40E_SUCCESS;
2089
2090         memset(&phy_conf, 0, sizeof(phy_conf));
2091
2092         /* bits 0-2 use the values from get_phy_abilities_resp */
2093         abilities &= ~mask;
2094         abilities |= phy_ab.abilities & mask;
2095
2096         phy_conf.abilities = abilities;
2097
2098         /* If link needs to go up, but the force speed is not supported,
2099          * Warn users and config the default available speeds.
2100          */
2101         if (is_up && !(force_speed & avail_speed)) {
2102                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2103                 phy_conf.link_speed = avail_speed;
2104         } else {
2105                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2106         }
2107
2108         /* PHY type mask needs to include each type except PHY type extension */
2109         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2110                 phy_type_mask |= 1 << cnt;
2111
2112         /* use get_phy_abilities_resp value for the rest */
2113         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2114         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2115                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2116                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2117         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2118         phy_conf.eee_capability = phy_ab.eee_capability;
2119         phy_conf.eeer = phy_ab.eeer_val;
2120         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2121
2122         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2123                     phy_ab.abilities, phy_ab.link_speed);
2124         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2125                     phy_conf.abilities, phy_conf.link_speed);
2126
2127         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2128         if (status)
2129                 return ret;
2130
2131         return I40E_SUCCESS;
2132 }
2133
2134 static int
2135 i40e_apply_link_speed(struct rte_eth_dev *dev)
2136 {
2137         uint8_t speed;
2138         uint8_t abilities = 0;
2139         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2140         struct rte_eth_conf *conf = &dev->data->dev_conf;
2141
2142         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2143                 conf->link_speeds = ETH_LINK_SPEED_40G |
2144                                     ETH_LINK_SPEED_25G |
2145                                     ETH_LINK_SPEED_20G |
2146                                     ETH_LINK_SPEED_10G |
2147                                     ETH_LINK_SPEED_1G |
2148                                     ETH_LINK_SPEED_100M;
2149         }
2150         speed = i40e_parse_link_speeds(conf->link_speeds);
2151         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2152                      I40E_AQ_PHY_AN_ENABLED |
2153                      I40E_AQ_PHY_LINK_ENABLED;
2154
2155         return i40e_phy_conf_link(hw, abilities, speed, true);
2156 }
2157
2158 static int
2159 i40e_dev_start(struct rte_eth_dev *dev)
2160 {
2161         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2162         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163         struct i40e_vsi *main_vsi = pf->main_vsi;
2164         int ret, i;
2165         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2166         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2167         uint32_t intr_vector = 0;
2168         struct i40e_vsi *vsi;
2169
2170         hw->adapter_stopped = 0;
2171
2172         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2173                 PMD_INIT_LOG(ERR,
2174                 "Invalid link_speeds for port %u, autonegotiation disabled",
2175                               dev->data->port_id);
2176                 return -EINVAL;
2177         }
2178
2179         rte_intr_disable(intr_handle);
2180
2181         if ((rte_intr_cap_multiple(intr_handle) ||
2182              !RTE_ETH_DEV_SRIOV(dev).active) &&
2183             dev->data->dev_conf.intr_conf.rxq != 0) {
2184                 intr_vector = dev->data->nb_rx_queues;
2185                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2186                 if (ret)
2187                         return ret;
2188         }
2189
2190         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2191                 intr_handle->intr_vec =
2192                         rte_zmalloc("intr_vec",
2193                                     dev->data->nb_rx_queues * sizeof(int),
2194                                     0);
2195                 if (!intr_handle->intr_vec) {
2196                         PMD_INIT_LOG(ERR,
2197                                 "Failed to allocate %d rx_queues intr_vec",
2198                                 dev->data->nb_rx_queues);
2199                         return -ENOMEM;
2200                 }
2201         }
2202
2203         /* Initialize VSI */
2204         ret = i40e_dev_rxtx_init(pf);
2205         if (ret != I40E_SUCCESS) {
2206                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2207                 goto err_up;
2208         }
2209
2210         /* Map queues with MSIX interrupt */
2211         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2212                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2213         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2214         i40e_vsi_enable_queues_intr(main_vsi);
2215
2216         /* Map VMDQ VSI queues with MSIX interrupt */
2217         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2218                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2219                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2220                                           I40E_ITR_INDEX_DEFAULT);
2221                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2222         }
2223
2224         /* enable FDIR MSIX interrupt */
2225         if (pf->fdir.fdir_vsi) {
2226                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2227                                           I40E_ITR_INDEX_NONE);
2228                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2229         }
2230
2231         /* Enable all queues which have been configured */
2232         ret = i40e_dev_switch_queues(pf, TRUE);
2233         if (ret != I40E_SUCCESS) {
2234                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2235                 goto err_up;
2236         }
2237
2238         /* Enable receiving broadcast packets */
2239         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2240         if (ret != I40E_SUCCESS)
2241                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2242
2243         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2244                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2245                                                 true, NULL);
2246                 if (ret != I40E_SUCCESS)
2247                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2248         }
2249
2250         /* Enable the VLAN promiscuous mode. */
2251         if (pf->vfs) {
2252                 for (i = 0; i < pf->vf_num; i++) {
2253                         vsi = pf->vfs[i].vsi;
2254                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2255                                                      true, NULL);
2256                 }
2257         }
2258
2259         /* Enable mac loopback mode */
2260         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2261             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2262                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2263                 if (ret != I40E_SUCCESS) {
2264                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2265                         goto err_up;
2266                 }
2267         }
2268
2269         /* Apply link configure */
2270         ret = i40e_apply_link_speed(dev);
2271         if (I40E_SUCCESS != ret) {
2272                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2273                 goto err_up;
2274         }
2275
2276         if (!rte_intr_allow_others(intr_handle)) {
2277                 rte_intr_callback_unregister(intr_handle,
2278                                              i40e_dev_interrupt_handler,
2279                                              (void *)dev);
2280                 /* configure and enable device interrupt */
2281                 i40e_pf_config_irq0(hw, FALSE);
2282                 i40e_pf_enable_irq0(hw);
2283
2284                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2285                         PMD_INIT_LOG(INFO,
2286                                 "lsc won't enable because of no intr multiplex");
2287         } else {
2288                 ret = i40e_aq_set_phy_int_mask(hw,
2289                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2290                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2291                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2292                 if (ret != I40E_SUCCESS)
2293                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2294
2295                 /* Call get_link_info aq commond to enable/disable LSE */
2296                 i40e_dev_link_update(dev, 0);
2297         }
2298
2299         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2300                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2301                                   i40e_dev_alarm_handler, dev);
2302         } else {
2303                 /* enable uio intr after callback register */
2304                 rte_intr_enable(intr_handle);
2305         }
2306
2307         i40e_filter_restore(pf);
2308
2309         if (pf->tm_conf.root && !pf->tm_conf.committed)
2310                 PMD_DRV_LOG(WARNING,
2311                             "please call hierarchy_commit() "
2312                             "before starting the port");
2313
2314         return I40E_SUCCESS;
2315
2316 err_up:
2317         i40e_dev_switch_queues(pf, FALSE);
2318         i40e_dev_clear_queues(dev);
2319
2320         return ret;
2321 }
2322
2323 static void
2324 i40e_dev_stop(struct rte_eth_dev *dev)
2325 {
2326         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2327         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2328         struct i40e_vsi *main_vsi = pf->main_vsi;
2329         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2330         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2331         int i;
2332
2333         if (hw->adapter_stopped == 1)
2334                 return;
2335
2336         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2337                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2338                 rte_intr_enable(intr_handle);
2339         }
2340
2341         /* Disable all queues */
2342         i40e_dev_switch_queues(pf, FALSE);
2343
2344         /* un-map queues with interrupt registers */
2345         i40e_vsi_disable_queues_intr(main_vsi);
2346         i40e_vsi_queues_unbind_intr(main_vsi);
2347
2348         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2349                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2350                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2351         }
2352
2353         if (pf->fdir.fdir_vsi) {
2354                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2355                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2356         }
2357         /* Clear all queues and release memory */
2358         i40e_dev_clear_queues(dev);
2359
2360         /* Set link down */
2361         i40e_dev_set_link_down(dev);
2362
2363         if (!rte_intr_allow_others(intr_handle))
2364                 /* resume to the default handler */
2365                 rte_intr_callback_register(intr_handle,
2366                                            i40e_dev_interrupt_handler,
2367                                            (void *)dev);
2368
2369         /* Clean datapath event and queue/vec mapping */
2370         rte_intr_efd_disable(intr_handle);
2371         if (intr_handle->intr_vec) {
2372                 rte_free(intr_handle->intr_vec);
2373                 intr_handle->intr_vec = NULL;
2374         }
2375
2376         /* reset hierarchy commit */
2377         pf->tm_conf.committed = false;
2378
2379         hw->adapter_stopped = 1;
2380 }
2381
2382 static void
2383 i40e_dev_close(struct rte_eth_dev *dev)
2384 {
2385         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2386         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2387         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2388         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2389         struct i40e_mirror_rule *p_mirror;
2390         uint32_t reg;
2391         int i;
2392         int ret;
2393
2394         PMD_INIT_FUNC_TRACE();
2395
2396         i40e_dev_stop(dev);
2397
2398         /* Remove all mirror rules */
2399         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2400                 ret = i40e_aq_del_mirror_rule(hw,
2401                                               pf->main_vsi->veb->seid,
2402                                               p_mirror->rule_type,
2403                                               p_mirror->entries,
2404                                               p_mirror->num_entries,
2405                                               p_mirror->id);
2406                 if (ret < 0)
2407                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2408                                     "status = %d, aq_err = %d.", ret,
2409                                     hw->aq.asq_last_status);
2410
2411                 /* remove mirror software resource anyway */
2412                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2413                 rte_free(p_mirror);
2414                 pf->nb_mirror_rule--;
2415         }
2416
2417         i40e_dev_free_queues(dev);
2418
2419         /* Disable interrupt */
2420         i40e_pf_disable_irq0(hw);
2421         rte_intr_disable(intr_handle);
2422
2423         i40e_fdir_teardown(pf);
2424
2425         /* shutdown and destroy the HMC */
2426         i40e_shutdown_lan_hmc(hw);
2427
2428         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2429                 i40e_vsi_release(pf->vmdq[i].vsi);
2430                 pf->vmdq[i].vsi = NULL;
2431         }
2432         rte_free(pf->vmdq);
2433         pf->vmdq = NULL;
2434
2435         /* release all the existing VSIs and VEBs */
2436         i40e_vsi_release(pf->main_vsi);
2437
2438         /* shutdown the adminq */
2439         i40e_aq_queue_shutdown(hw, true);
2440         i40e_shutdown_adminq(hw);
2441
2442         i40e_res_pool_destroy(&pf->qp_pool);
2443         i40e_res_pool_destroy(&pf->msix_pool);
2444
2445         /* Disable flexible payload in global configuration */
2446         if (!pf->support_multi_driver)
2447                 i40e_flex_payload_reg_set_default(hw);
2448
2449         /* force a PF reset to clean anything leftover */
2450         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2451         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2452                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2453         I40E_WRITE_FLUSH(hw);
2454 }
2455
2456 /*
2457  * Reset PF device only to re-initialize resources in PMD layer
2458  */
2459 static int
2460 i40e_dev_reset(struct rte_eth_dev *dev)
2461 {
2462         int ret;
2463
2464         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2465          * its VF to make them align with it. The detailed notification
2466          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2467          * To avoid unexpected behavior in VF, currently reset of PF with
2468          * SR-IOV activation is not supported. It might be supported later.
2469          */
2470         if (dev->data->sriov.active)
2471                 return -ENOTSUP;
2472
2473         ret = eth_i40e_dev_uninit(dev);
2474         if (ret)
2475                 return ret;
2476
2477         ret = eth_i40e_dev_init(dev, NULL);
2478
2479         return ret;
2480 }
2481
2482 static void
2483 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2484 {
2485         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2486         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2487         struct i40e_vsi *vsi = pf->main_vsi;
2488         int status;
2489
2490         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2491                                                      true, NULL, true);
2492         if (status != I40E_SUCCESS)
2493                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2494
2495         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2496                                                         TRUE, NULL);
2497         if (status != I40E_SUCCESS)
2498                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2499
2500 }
2501
2502 static void
2503 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2504 {
2505         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2506         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2507         struct i40e_vsi *vsi = pf->main_vsi;
2508         int status;
2509
2510         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2511                                                      false, NULL, true);
2512         if (status != I40E_SUCCESS)
2513                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2514
2515         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2516                                                         false, NULL);
2517         if (status != I40E_SUCCESS)
2518                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2519 }
2520
2521 static void
2522 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2523 {
2524         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2525         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2526         struct i40e_vsi *vsi = pf->main_vsi;
2527         int ret;
2528
2529         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2530         if (ret != I40E_SUCCESS)
2531                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2532 }
2533
2534 static void
2535 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2536 {
2537         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2538         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539         struct i40e_vsi *vsi = pf->main_vsi;
2540         int ret;
2541
2542         if (dev->data->promiscuous == 1)
2543                 return; /* must remain in all_multicast mode */
2544
2545         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2546                                 vsi->seid, FALSE, NULL);
2547         if (ret != I40E_SUCCESS)
2548                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2549 }
2550
2551 /*
2552  * Set device link up.
2553  */
2554 static int
2555 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2556 {
2557         /* re-apply link speed setting */
2558         return i40e_apply_link_speed(dev);
2559 }
2560
2561 /*
2562  * Set device link down.
2563  */
2564 static int
2565 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2566 {
2567         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2568         uint8_t abilities = 0;
2569         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570
2571         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2572         return i40e_phy_conf_link(hw, abilities, speed, false);
2573 }
2574
2575 static __rte_always_inline void
2576 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2577 {
2578 /* Link status registers and values*/
2579 #define I40E_PRTMAC_LINKSTA             0x001E2420
2580 #define I40E_REG_LINK_UP                0x40000080
2581 #define I40E_PRTMAC_MACC                0x001E24E0
2582 #define I40E_REG_MACC_25GB              0x00020000
2583 #define I40E_REG_SPEED_MASK             0x38000000
2584 #define I40E_REG_SPEED_100MB            0x00000000
2585 #define I40E_REG_SPEED_1GB              0x08000000
2586 #define I40E_REG_SPEED_10GB             0x10000000
2587 #define I40E_REG_SPEED_20GB             0x20000000
2588 #define I40E_REG_SPEED_25_40GB          0x18000000
2589         uint32_t link_speed;
2590         uint32_t reg_val;
2591
2592         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2593         link_speed = reg_val & I40E_REG_SPEED_MASK;
2594         reg_val &= I40E_REG_LINK_UP;
2595         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2596
2597         if (unlikely(link->link_status == 0))
2598                 return;
2599
2600         /* Parse the link status */
2601         switch (link_speed) {
2602         case I40E_REG_SPEED_100MB:
2603                 link->link_speed = ETH_SPEED_NUM_100M;
2604                 break;
2605         case I40E_REG_SPEED_1GB:
2606                 link->link_speed = ETH_SPEED_NUM_1G;
2607                 break;
2608         case I40E_REG_SPEED_10GB:
2609                 link->link_speed = ETH_SPEED_NUM_10G;
2610                 break;
2611         case I40E_REG_SPEED_20GB:
2612                 link->link_speed = ETH_SPEED_NUM_20G;
2613                 break;
2614         case I40E_REG_SPEED_25_40GB:
2615                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2616
2617                 if (reg_val & I40E_REG_MACC_25GB)
2618                         link->link_speed = ETH_SPEED_NUM_25G;
2619                 else
2620                         link->link_speed = ETH_SPEED_NUM_40G;
2621
2622                 break;
2623         default:
2624                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2625                 break;
2626         }
2627 }
2628
2629 static __rte_always_inline void
2630 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2631         bool enable_lse, int wait_to_complete)
2632 {
2633 #define CHECK_INTERVAL             100  /* 100ms */
2634 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2635         uint32_t rep_cnt = MAX_REPEAT_TIME;
2636         struct i40e_link_status link_status;
2637         int status;
2638
2639         memset(&link_status, 0, sizeof(link_status));
2640
2641         do {
2642                 memset(&link_status, 0, sizeof(link_status));
2643
2644                 /* Get link status information from hardware */
2645                 status = i40e_aq_get_link_info(hw, enable_lse,
2646                                                 &link_status, NULL);
2647                 if (unlikely(status != I40E_SUCCESS)) {
2648                         link->link_speed = ETH_SPEED_NUM_100M;
2649                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2650                         PMD_DRV_LOG(ERR, "Failed to get link info");
2651                         return;
2652                 }
2653
2654                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2655                 if (!wait_to_complete || link->link_status)
2656                         break;
2657
2658                 rte_delay_ms(CHECK_INTERVAL);
2659         } while (--rep_cnt);
2660
2661         /* Parse the link status */
2662         switch (link_status.link_speed) {
2663         case I40E_LINK_SPEED_100MB:
2664                 link->link_speed = ETH_SPEED_NUM_100M;
2665                 break;
2666         case I40E_LINK_SPEED_1GB:
2667                 link->link_speed = ETH_SPEED_NUM_1G;
2668                 break;
2669         case I40E_LINK_SPEED_10GB:
2670                 link->link_speed = ETH_SPEED_NUM_10G;
2671                 break;
2672         case I40E_LINK_SPEED_20GB:
2673                 link->link_speed = ETH_SPEED_NUM_20G;
2674                 break;
2675         case I40E_LINK_SPEED_25GB:
2676                 link->link_speed = ETH_SPEED_NUM_25G;
2677                 break;
2678         case I40E_LINK_SPEED_40GB:
2679                 link->link_speed = ETH_SPEED_NUM_40G;
2680                 break;
2681         default:
2682                 link->link_speed = ETH_SPEED_NUM_100M;
2683                 break;
2684         }
2685 }
2686
2687 int
2688 i40e_dev_link_update(struct rte_eth_dev *dev,
2689                      int wait_to_complete)
2690 {
2691         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2692         struct rte_eth_link link;
2693         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2694         int ret;
2695
2696         memset(&link, 0, sizeof(link));
2697
2698         /* i40e uses full duplex only */
2699         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2700         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2701                         ETH_LINK_SPEED_FIXED);
2702
2703         if (!wait_to_complete && !enable_lse)
2704                 update_link_reg(hw, &link);
2705         else
2706                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2707
2708         ret = rte_eth_linkstatus_set(dev, &link);
2709         i40e_notify_all_vfs_link_status(dev);
2710
2711         return ret;
2712 }
2713
2714 /* Get all the statistics of a VSI */
2715 void
2716 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2717 {
2718         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2719         struct i40e_eth_stats *nes = &vsi->eth_stats;
2720         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2721         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2722
2723         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2724                             vsi->offset_loaded, &oes->rx_bytes,
2725                             &nes->rx_bytes);
2726         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2727                             vsi->offset_loaded, &oes->rx_unicast,
2728                             &nes->rx_unicast);
2729         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2730                             vsi->offset_loaded, &oes->rx_multicast,
2731                             &nes->rx_multicast);
2732         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2733                             vsi->offset_loaded, &oes->rx_broadcast,
2734                             &nes->rx_broadcast);
2735         /* exclude CRC bytes */
2736         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2737                 nes->rx_broadcast) * ETHER_CRC_LEN;
2738
2739         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2740                             &oes->rx_discards, &nes->rx_discards);
2741         /* GLV_REPC not supported */
2742         /* GLV_RMPC not supported */
2743         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2744                             &oes->rx_unknown_protocol,
2745                             &nes->rx_unknown_protocol);
2746         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2747                             vsi->offset_loaded, &oes->tx_bytes,
2748                             &nes->tx_bytes);
2749         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2750                             vsi->offset_loaded, &oes->tx_unicast,
2751                             &nes->tx_unicast);
2752         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2753                             vsi->offset_loaded, &oes->tx_multicast,
2754                             &nes->tx_multicast);
2755         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2756                             vsi->offset_loaded,  &oes->tx_broadcast,
2757                             &nes->tx_broadcast);
2758         /* GLV_TDPC not supported */
2759         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2760                             &oes->tx_errors, &nes->tx_errors);
2761         vsi->offset_loaded = true;
2762
2763         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2764                     vsi->vsi_id);
2765         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2766         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2767         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2768         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2769         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2770         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2771                     nes->rx_unknown_protocol);
2772         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2773         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2774         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2775         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2776         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2777         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2778         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2779                     vsi->vsi_id);
2780 }
2781
2782 static void
2783 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2784 {
2785         unsigned int i;
2786         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2787         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2788
2789         /* Get rx/tx bytes of internal transfer packets */
2790         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2791                         I40E_GLV_GORCL(hw->port),
2792                         pf->offset_loaded,
2793                         &pf->internal_stats_offset.rx_bytes,
2794                         &pf->internal_stats.rx_bytes);
2795
2796         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2797                         I40E_GLV_GOTCL(hw->port),
2798                         pf->offset_loaded,
2799                         &pf->internal_stats_offset.tx_bytes,
2800                         &pf->internal_stats.tx_bytes);
2801         /* Get total internal rx packet count */
2802         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2803                             I40E_GLV_UPRCL(hw->port),
2804                             pf->offset_loaded,
2805                             &pf->internal_stats_offset.rx_unicast,
2806                             &pf->internal_stats.rx_unicast);
2807         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2808                             I40E_GLV_MPRCL(hw->port),
2809                             pf->offset_loaded,
2810                             &pf->internal_stats_offset.rx_multicast,
2811                             &pf->internal_stats.rx_multicast);
2812         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2813                             I40E_GLV_BPRCL(hw->port),
2814                             pf->offset_loaded,
2815                             &pf->internal_stats_offset.rx_broadcast,
2816                             &pf->internal_stats.rx_broadcast);
2817         /* Get total internal tx packet count */
2818         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2819                             I40E_GLV_UPTCL(hw->port),
2820                             pf->offset_loaded,
2821                             &pf->internal_stats_offset.tx_unicast,
2822                             &pf->internal_stats.tx_unicast);
2823         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2824                             I40E_GLV_MPTCL(hw->port),
2825                             pf->offset_loaded,
2826                             &pf->internal_stats_offset.tx_multicast,
2827                             &pf->internal_stats.tx_multicast);
2828         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2829                             I40E_GLV_BPTCL(hw->port),
2830                             pf->offset_loaded,
2831                             &pf->internal_stats_offset.tx_broadcast,
2832                             &pf->internal_stats.tx_broadcast);
2833
2834         /* exclude CRC size */
2835         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2836                 pf->internal_stats.rx_multicast +
2837                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2838
2839         /* Get statistics of struct i40e_eth_stats */
2840         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2841                             I40E_GLPRT_GORCL(hw->port),
2842                             pf->offset_loaded, &os->eth.rx_bytes,
2843                             &ns->eth.rx_bytes);
2844         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2845                             I40E_GLPRT_UPRCL(hw->port),
2846                             pf->offset_loaded, &os->eth.rx_unicast,
2847                             &ns->eth.rx_unicast);
2848         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2849                             I40E_GLPRT_MPRCL(hw->port),
2850                             pf->offset_loaded, &os->eth.rx_multicast,
2851                             &ns->eth.rx_multicast);
2852         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2853                             I40E_GLPRT_BPRCL(hw->port),
2854                             pf->offset_loaded, &os->eth.rx_broadcast,
2855                             &ns->eth.rx_broadcast);
2856         /* Workaround: CRC size should not be included in byte statistics,
2857          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2858          */
2859         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2860                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2861
2862         /* exclude internal rx bytes
2863          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2864          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2865          * value.
2866          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2867          */
2868         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2869                 ns->eth.rx_bytes = 0;
2870         else
2871                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2872
2873         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2874                 ns->eth.rx_unicast = 0;
2875         else
2876                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2877
2878         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2879                 ns->eth.rx_multicast = 0;
2880         else
2881                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2882
2883         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2884                 ns->eth.rx_broadcast = 0;
2885         else
2886                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2887
2888         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2889                             pf->offset_loaded, &os->eth.rx_discards,
2890                             &ns->eth.rx_discards);
2891         /* GLPRT_REPC not supported */
2892         /* GLPRT_RMPC not supported */
2893         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2894                             pf->offset_loaded,
2895                             &os->eth.rx_unknown_protocol,
2896                             &ns->eth.rx_unknown_protocol);
2897         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2898                             I40E_GLPRT_GOTCL(hw->port),
2899                             pf->offset_loaded, &os->eth.tx_bytes,
2900                             &ns->eth.tx_bytes);
2901         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2902                             I40E_GLPRT_UPTCL(hw->port),
2903                             pf->offset_loaded, &os->eth.tx_unicast,
2904                             &ns->eth.tx_unicast);
2905         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2906                             I40E_GLPRT_MPTCL(hw->port),
2907                             pf->offset_loaded, &os->eth.tx_multicast,
2908                             &ns->eth.tx_multicast);
2909         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2910                             I40E_GLPRT_BPTCL(hw->port),
2911                             pf->offset_loaded, &os->eth.tx_broadcast,
2912                             &ns->eth.tx_broadcast);
2913         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2914                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2915
2916         /* exclude internal tx bytes
2917          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2918          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2919          * value.
2920          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2921          */
2922         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2923                 ns->eth.tx_bytes = 0;
2924         else
2925                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2926
2927         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2928                 ns->eth.tx_unicast = 0;
2929         else
2930                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2931
2932         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2933                 ns->eth.tx_multicast = 0;
2934         else
2935                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2936
2937         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2938                 ns->eth.tx_broadcast = 0;
2939         else
2940                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2941
2942         /* GLPRT_TEPC not supported */
2943
2944         /* additional port specific stats */
2945         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2946                             pf->offset_loaded, &os->tx_dropped_link_down,
2947                             &ns->tx_dropped_link_down);
2948         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2949                             pf->offset_loaded, &os->crc_errors,
2950                             &ns->crc_errors);
2951         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2952                             pf->offset_loaded, &os->illegal_bytes,
2953                             &ns->illegal_bytes);
2954         /* GLPRT_ERRBC not supported */
2955         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2956                             pf->offset_loaded, &os->mac_local_faults,
2957                             &ns->mac_local_faults);
2958         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2959                             pf->offset_loaded, &os->mac_remote_faults,
2960                             &ns->mac_remote_faults);
2961         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2962                             pf->offset_loaded, &os->rx_length_errors,
2963                             &ns->rx_length_errors);
2964         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2965                             pf->offset_loaded, &os->link_xon_rx,
2966                             &ns->link_xon_rx);
2967         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2968                             pf->offset_loaded, &os->link_xoff_rx,
2969                             &ns->link_xoff_rx);
2970         for (i = 0; i < 8; i++) {
2971                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2972                                     pf->offset_loaded,
2973                                     &os->priority_xon_rx[i],
2974                                     &ns->priority_xon_rx[i]);
2975                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2976                                     pf->offset_loaded,
2977                                     &os->priority_xoff_rx[i],
2978                                     &ns->priority_xoff_rx[i]);
2979         }
2980         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2981                             pf->offset_loaded, &os->link_xon_tx,
2982                             &ns->link_xon_tx);
2983         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2984                             pf->offset_loaded, &os->link_xoff_tx,
2985                             &ns->link_xoff_tx);
2986         for (i = 0; i < 8; i++) {
2987                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2988                                     pf->offset_loaded,
2989                                     &os->priority_xon_tx[i],
2990                                     &ns->priority_xon_tx[i]);
2991                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2992                                     pf->offset_loaded,
2993                                     &os->priority_xoff_tx[i],
2994                                     &ns->priority_xoff_tx[i]);
2995                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2996                                     pf->offset_loaded,
2997                                     &os->priority_xon_2_xoff[i],
2998                                     &ns->priority_xon_2_xoff[i]);
2999         }
3000         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3001                             I40E_GLPRT_PRC64L(hw->port),
3002                             pf->offset_loaded, &os->rx_size_64,
3003                             &ns->rx_size_64);
3004         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3005                             I40E_GLPRT_PRC127L(hw->port),
3006                             pf->offset_loaded, &os->rx_size_127,
3007                             &ns->rx_size_127);
3008         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3009                             I40E_GLPRT_PRC255L(hw->port),
3010                             pf->offset_loaded, &os->rx_size_255,
3011                             &ns->rx_size_255);
3012         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3013                             I40E_GLPRT_PRC511L(hw->port),
3014                             pf->offset_loaded, &os->rx_size_511,
3015                             &ns->rx_size_511);
3016         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3017                             I40E_GLPRT_PRC1023L(hw->port),
3018                             pf->offset_loaded, &os->rx_size_1023,
3019                             &ns->rx_size_1023);
3020         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3021                             I40E_GLPRT_PRC1522L(hw->port),
3022                             pf->offset_loaded, &os->rx_size_1522,
3023                             &ns->rx_size_1522);
3024         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3025                             I40E_GLPRT_PRC9522L(hw->port),
3026                             pf->offset_loaded, &os->rx_size_big,
3027                             &ns->rx_size_big);
3028         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3029                             pf->offset_loaded, &os->rx_undersize,
3030                             &ns->rx_undersize);
3031         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3032                             pf->offset_loaded, &os->rx_fragments,
3033                             &ns->rx_fragments);
3034         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3035                             pf->offset_loaded, &os->rx_oversize,
3036                             &ns->rx_oversize);
3037         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3038                             pf->offset_loaded, &os->rx_jabber,
3039                             &ns->rx_jabber);
3040         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3041                             I40E_GLPRT_PTC64L(hw->port),
3042                             pf->offset_loaded, &os->tx_size_64,
3043                             &ns->tx_size_64);
3044         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3045                             I40E_GLPRT_PTC127L(hw->port),
3046                             pf->offset_loaded, &os->tx_size_127,
3047                             &ns->tx_size_127);
3048         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3049                             I40E_GLPRT_PTC255L(hw->port),
3050                             pf->offset_loaded, &os->tx_size_255,
3051                             &ns->tx_size_255);
3052         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3053                             I40E_GLPRT_PTC511L(hw->port),
3054                             pf->offset_loaded, &os->tx_size_511,
3055                             &ns->tx_size_511);
3056         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3057                             I40E_GLPRT_PTC1023L(hw->port),
3058                             pf->offset_loaded, &os->tx_size_1023,
3059                             &ns->tx_size_1023);
3060         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3061                             I40E_GLPRT_PTC1522L(hw->port),
3062                             pf->offset_loaded, &os->tx_size_1522,
3063                             &ns->tx_size_1522);
3064         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3065                             I40E_GLPRT_PTC9522L(hw->port),
3066                             pf->offset_loaded, &os->tx_size_big,
3067                             &ns->tx_size_big);
3068         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3069                            pf->offset_loaded,
3070                            &os->fd_sb_match, &ns->fd_sb_match);
3071         /* GLPRT_MSPDC not supported */
3072         /* GLPRT_XEC not supported */
3073
3074         pf->offset_loaded = true;
3075
3076         if (pf->main_vsi)
3077                 i40e_update_vsi_stats(pf->main_vsi);
3078 }
3079
3080 /* Get all statistics of a port */
3081 static int
3082 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3083 {
3084         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3085         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3086         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3087         unsigned i;
3088
3089         /* call read registers - updates values, now write them to struct */
3090         i40e_read_stats_registers(pf, hw);
3091
3092         stats->ipackets = ns->eth.rx_unicast +
3093                         ns->eth.rx_multicast +
3094                         ns->eth.rx_broadcast -
3095                         ns->eth.rx_discards -
3096                         pf->main_vsi->eth_stats.rx_discards;
3097         stats->opackets = ns->eth.tx_unicast +
3098                         ns->eth.tx_multicast +
3099                         ns->eth.tx_broadcast;
3100         stats->ibytes   = ns->eth.rx_bytes;
3101         stats->obytes   = ns->eth.tx_bytes;
3102         stats->oerrors  = ns->eth.tx_errors +
3103                         pf->main_vsi->eth_stats.tx_errors;
3104
3105         /* Rx Errors */
3106         stats->imissed  = ns->eth.rx_discards +
3107                         pf->main_vsi->eth_stats.rx_discards;
3108         stats->ierrors  = ns->crc_errors +
3109                         ns->rx_length_errors + ns->rx_undersize +
3110                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3111
3112         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3113         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3114         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3115         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3116         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3117         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3118         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3119                     ns->eth.rx_unknown_protocol);
3120         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3121         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3122         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3123         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3124         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3125         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3126
3127         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3128                     ns->tx_dropped_link_down);
3129         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3130         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3131                     ns->illegal_bytes);
3132         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3133         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3134                     ns->mac_local_faults);
3135         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3136                     ns->mac_remote_faults);
3137         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3138                     ns->rx_length_errors);
3139         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3140         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3141         for (i = 0; i < 8; i++) {
3142                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3143                                 i, ns->priority_xon_rx[i]);
3144                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3145                                 i, ns->priority_xoff_rx[i]);
3146         }
3147         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3148         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3149         for (i = 0; i < 8; i++) {
3150                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3151                                 i, ns->priority_xon_tx[i]);
3152                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3153                                 i, ns->priority_xoff_tx[i]);
3154                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3155                                 i, ns->priority_xon_2_xoff[i]);
3156         }
3157         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3158         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3159         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3160         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3161         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3162         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3163         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3164         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3165         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3166         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3167         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3168         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3169         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3170         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3171         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3172         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3173         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3174         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3175         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3176                         ns->mac_short_packet_dropped);
3177         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3178                     ns->checksum_error);
3179         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3180         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3181         return 0;
3182 }
3183
3184 /* Reset the statistics */
3185 static void
3186 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3187 {
3188         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3189         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3190
3191         /* Mark PF and VSI stats to update the offset, aka "reset" */
3192         pf->offset_loaded = false;
3193         if (pf->main_vsi)
3194                 pf->main_vsi->offset_loaded = false;
3195
3196         /* read the stats, reading current register values into offset */
3197         i40e_read_stats_registers(pf, hw);
3198 }
3199
3200 static uint32_t
3201 i40e_xstats_calc_num(void)
3202 {
3203         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3204                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3205                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3206 }
3207
3208 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3209                                      struct rte_eth_xstat_name *xstats_names,
3210                                      __rte_unused unsigned limit)
3211 {
3212         unsigned count = 0;
3213         unsigned i, prio;
3214
3215         if (xstats_names == NULL)
3216                 return i40e_xstats_calc_num();
3217
3218         /* Note: limit checked in rte_eth_xstats_names() */
3219
3220         /* Get stats from i40e_eth_stats struct */
3221         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3222                 snprintf(xstats_names[count].name,
3223                          sizeof(xstats_names[count].name),
3224                          "%s", rte_i40e_stats_strings[i].name);
3225                 count++;
3226         }
3227
3228         /* Get individiual stats from i40e_hw_port struct */
3229         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3230                 snprintf(xstats_names[count].name,
3231                         sizeof(xstats_names[count].name),
3232                          "%s", rte_i40e_hw_port_strings[i].name);
3233                 count++;
3234         }
3235
3236         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3237                 for (prio = 0; prio < 8; prio++) {
3238                         snprintf(xstats_names[count].name,
3239                                  sizeof(xstats_names[count].name),
3240                                  "rx_priority%u_%s", prio,
3241                                  rte_i40e_rxq_prio_strings[i].name);
3242                         count++;
3243                 }
3244         }
3245
3246         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3247                 for (prio = 0; prio < 8; prio++) {
3248                         snprintf(xstats_names[count].name,
3249                                  sizeof(xstats_names[count].name),
3250                                  "tx_priority%u_%s", prio,
3251                                  rte_i40e_txq_prio_strings[i].name);
3252                         count++;
3253                 }
3254         }
3255         return count;
3256 }
3257
3258 static int
3259 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3260                     unsigned n)
3261 {
3262         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3263         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3264         unsigned i, count, prio;
3265         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3266
3267         count = i40e_xstats_calc_num();
3268         if (n < count)
3269                 return count;
3270
3271         i40e_read_stats_registers(pf, hw);
3272
3273         if (xstats == NULL)
3274                 return 0;
3275
3276         count = 0;
3277
3278         /* Get stats from i40e_eth_stats struct */
3279         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3280                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3281                         rte_i40e_stats_strings[i].offset);
3282                 xstats[count].id = count;
3283                 count++;
3284         }
3285
3286         /* Get individiual stats from i40e_hw_port struct */
3287         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3288                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3289                         rte_i40e_hw_port_strings[i].offset);
3290                 xstats[count].id = count;
3291                 count++;
3292         }
3293
3294         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3295                 for (prio = 0; prio < 8; prio++) {
3296                         xstats[count].value =
3297                                 *(uint64_t *)(((char *)hw_stats) +
3298                                 rte_i40e_rxq_prio_strings[i].offset +
3299                                 (sizeof(uint64_t) * prio));
3300                         xstats[count].id = count;
3301                         count++;
3302                 }
3303         }
3304
3305         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3306                 for (prio = 0; prio < 8; prio++) {
3307                         xstats[count].value =
3308                                 *(uint64_t *)(((char *)hw_stats) +
3309                                 rte_i40e_txq_prio_strings[i].offset +
3310                                 (sizeof(uint64_t) * prio));
3311                         xstats[count].id = count;
3312                         count++;
3313                 }
3314         }
3315
3316         return count;
3317 }
3318
3319 static int
3320 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3321                                  __rte_unused uint16_t queue_id,
3322                                  __rte_unused uint8_t stat_idx,
3323                                  __rte_unused uint8_t is_rx)
3324 {
3325         PMD_INIT_FUNC_TRACE();
3326
3327         return -ENOSYS;
3328 }
3329
3330 static int
3331 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3332 {
3333         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3334         u32 full_ver;
3335         u8 ver, patch;
3336         u16 build;
3337         int ret;
3338
3339         full_ver = hw->nvm.oem_ver;
3340         ver = (u8)(full_ver >> 24);
3341         build = (u16)((full_ver >> 8) & 0xffff);
3342         patch = (u8)(full_ver & 0xff);
3343
3344         ret = snprintf(fw_version, fw_size,
3345                  "%d.%d%d 0x%08x %d.%d.%d",
3346                  ((hw->nvm.version >> 12) & 0xf),
3347                  ((hw->nvm.version >> 4) & 0xff),
3348                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3349                  ver, build, patch);
3350
3351         ret += 1; /* add the size of '\0' */
3352         if (fw_size < (u32)ret)
3353                 return ret;
3354         else
3355                 return 0;
3356 }
3357
3358 static void
3359 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3360 {
3361         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3362         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3363         struct i40e_vsi *vsi = pf->main_vsi;
3364         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3365
3366         dev_info->max_rx_queues = vsi->nb_qps;
3367         dev_info->max_tx_queues = vsi->nb_qps;
3368         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3369         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3370         dev_info->max_mac_addrs = vsi->max_macaddrs;
3371         dev_info->max_vfs = pci_dev->max_vfs;
3372         dev_info->rx_queue_offload_capa = 0;
3373         dev_info->rx_offload_capa =
3374                 DEV_RX_OFFLOAD_VLAN_STRIP |
3375                 DEV_RX_OFFLOAD_QINQ_STRIP |
3376                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3377                 DEV_RX_OFFLOAD_UDP_CKSUM |
3378                 DEV_RX_OFFLOAD_TCP_CKSUM |
3379                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3380                 DEV_RX_OFFLOAD_KEEP_CRC |
3381                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3382                 DEV_RX_OFFLOAD_VLAN_FILTER |
3383                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3384
3385         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3386         dev_info->tx_offload_capa =
3387                 DEV_TX_OFFLOAD_VLAN_INSERT |
3388                 DEV_TX_OFFLOAD_QINQ_INSERT |
3389                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3390                 DEV_TX_OFFLOAD_UDP_CKSUM |
3391                 DEV_TX_OFFLOAD_TCP_CKSUM |
3392                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3393                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3394                 DEV_TX_OFFLOAD_TCP_TSO |
3395                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3396                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3397                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3398                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3399                 DEV_TX_OFFLOAD_MULTI_SEGS |
3400                 dev_info->tx_queue_offload_capa;
3401         dev_info->dev_capa =
3402                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3403                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3404
3405         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3406                                                 sizeof(uint32_t);
3407         dev_info->reta_size = pf->hash_lut_size;
3408         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3409
3410         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3411                 .rx_thresh = {
3412                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3413                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3414                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3415                 },
3416                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3417                 .rx_drop_en = 0,
3418                 .offloads = 0,
3419         };
3420
3421         dev_info->default_txconf = (struct rte_eth_txconf) {
3422                 .tx_thresh = {
3423                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3424                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3425                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3426                 },
3427                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3428                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3429                 .offloads = 0,
3430         };
3431
3432         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3433                 .nb_max = I40E_MAX_RING_DESC,
3434                 .nb_min = I40E_MIN_RING_DESC,
3435                 .nb_align = I40E_ALIGN_RING_DESC,
3436         };
3437
3438         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3439                 .nb_max = I40E_MAX_RING_DESC,
3440                 .nb_min = I40E_MIN_RING_DESC,
3441                 .nb_align = I40E_ALIGN_RING_DESC,
3442                 .nb_seg_max = I40E_TX_MAX_SEG,
3443                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3444         };
3445
3446         if (pf->flags & I40E_FLAG_VMDQ) {
3447                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3448                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3449                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3450                                                 pf->max_nb_vmdq_vsi;
3451                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3452                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3453                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3454         }
3455
3456         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3457                 /* For XL710 */
3458                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3459                 dev_info->default_rxportconf.nb_queues = 2;
3460                 dev_info->default_txportconf.nb_queues = 2;
3461                 if (dev->data->nb_rx_queues == 1)
3462                         dev_info->default_rxportconf.ring_size = 2048;
3463                 else
3464                         dev_info->default_rxportconf.ring_size = 1024;
3465                 if (dev->data->nb_tx_queues == 1)
3466                         dev_info->default_txportconf.ring_size = 1024;
3467                 else
3468                         dev_info->default_txportconf.ring_size = 512;
3469
3470         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3471                 /* For XXV710 */
3472                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3473                 dev_info->default_rxportconf.nb_queues = 1;
3474                 dev_info->default_txportconf.nb_queues = 1;
3475                 dev_info->default_rxportconf.ring_size = 256;
3476                 dev_info->default_txportconf.ring_size = 256;
3477         } else {
3478                 /* For X710 */
3479                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3480                 dev_info->default_rxportconf.nb_queues = 1;
3481                 dev_info->default_txportconf.nb_queues = 1;
3482                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3483                         dev_info->default_rxportconf.ring_size = 512;
3484                         dev_info->default_txportconf.ring_size = 256;
3485                 } else {
3486                         dev_info->default_rxportconf.ring_size = 256;
3487                         dev_info->default_txportconf.ring_size = 256;
3488                 }
3489         }
3490         dev_info->default_rxportconf.burst_size = 32;
3491         dev_info->default_txportconf.burst_size = 32;
3492 }
3493
3494 static int
3495 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3496 {
3497         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3498         struct i40e_vsi *vsi = pf->main_vsi;
3499         PMD_INIT_FUNC_TRACE();
3500
3501         if (on)
3502                 return i40e_vsi_add_vlan(vsi, vlan_id);
3503         else
3504                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3505 }
3506
3507 static int
3508 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3509                                 enum rte_vlan_type vlan_type,
3510                                 uint16_t tpid, int qinq)
3511 {
3512         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3513         uint64_t reg_r = 0;
3514         uint64_t reg_w = 0;
3515         uint16_t reg_id = 3;
3516         int ret;
3517
3518         if (qinq) {
3519                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3520                         reg_id = 2;
3521         }
3522
3523         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3524                                           &reg_r, NULL);
3525         if (ret != I40E_SUCCESS) {
3526                 PMD_DRV_LOG(ERR,
3527                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3528                            reg_id);
3529                 return -EIO;
3530         }
3531         PMD_DRV_LOG(DEBUG,
3532                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3533                     reg_id, reg_r);
3534
3535         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3536         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3537         if (reg_r == reg_w) {
3538                 PMD_DRV_LOG(DEBUG, "No need to write");
3539                 return 0;
3540         }
3541
3542         ret = i40e_aq_debug_write_global_register(hw,
3543                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3544                                            reg_w, NULL);
3545         if (ret != I40E_SUCCESS) {
3546                 PMD_DRV_LOG(ERR,
3547                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3548                             reg_id);
3549                 return -EIO;
3550         }
3551         PMD_DRV_LOG(DEBUG,
3552                     "Global register 0x%08x is changed with value 0x%08x",
3553                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3554
3555         return 0;
3556 }
3557
3558 static int
3559 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3560                    enum rte_vlan_type vlan_type,
3561                    uint16_t tpid)
3562 {
3563         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3564         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3565         int qinq = dev->data->dev_conf.rxmode.offloads &
3566                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3567         int ret = 0;
3568
3569         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3570              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3571             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3572                 PMD_DRV_LOG(ERR,
3573                             "Unsupported vlan type.");
3574                 return -EINVAL;
3575         }
3576
3577         if (pf->support_multi_driver) {
3578                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3579                 return -ENOTSUP;
3580         }
3581
3582         /* 802.1ad frames ability is added in NVM API 1.7*/
3583         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3584                 if (qinq) {
3585                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3586                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3587                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3588                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3589                 } else {
3590                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3591                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3592                 }
3593                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3594                 if (ret != I40E_SUCCESS) {
3595                         PMD_DRV_LOG(ERR,
3596                                     "Set switch config failed aq_err: %d",
3597                                     hw->aq.asq_last_status);
3598                         ret = -EIO;
3599                 }
3600         } else
3601                 /* If NVM API < 1.7, keep the register setting */
3602                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3603                                                       tpid, qinq);
3604
3605         return ret;
3606 }
3607
3608 static int
3609 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3610 {
3611         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3612         struct i40e_vsi *vsi = pf->main_vsi;
3613         struct rte_eth_rxmode *rxmode;
3614
3615         rxmode = &dev->data->dev_conf.rxmode;
3616         if (mask & ETH_VLAN_FILTER_MASK) {
3617                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3618                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3619                 else
3620                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3621         }
3622
3623         if (mask & ETH_VLAN_STRIP_MASK) {
3624                 /* Enable or disable VLAN stripping */
3625                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3626                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3627                 else
3628                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3629         }
3630
3631         if (mask & ETH_VLAN_EXTEND_MASK) {
3632                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3633                         i40e_vsi_config_double_vlan(vsi, TRUE);
3634                         /* Set global registers with default ethertype. */
3635                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3636                                            ETHER_TYPE_VLAN);
3637                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3638                                            ETHER_TYPE_VLAN);
3639                 }
3640                 else
3641                         i40e_vsi_config_double_vlan(vsi, FALSE);
3642         }
3643
3644         return 0;
3645 }
3646
3647 static void
3648 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3649                           __rte_unused uint16_t queue,
3650                           __rte_unused int on)
3651 {
3652         PMD_INIT_FUNC_TRACE();
3653 }
3654
3655 static int
3656 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3657 {
3658         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3659         struct i40e_vsi *vsi = pf->main_vsi;
3660         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3661         struct i40e_vsi_vlan_pvid_info info;
3662
3663         memset(&info, 0, sizeof(info));
3664         info.on = on;
3665         if (info.on)
3666                 info.config.pvid = pvid;
3667         else {
3668                 info.config.reject.tagged =
3669                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3670                 info.config.reject.untagged =
3671                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3672         }
3673
3674         return i40e_vsi_vlan_pvid_set(vsi, &info);
3675 }
3676
3677 static int
3678 i40e_dev_led_on(struct rte_eth_dev *dev)
3679 {
3680         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3681         uint32_t mode = i40e_led_get(hw);
3682
3683         if (mode == 0)
3684                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3685
3686         return 0;
3687 }
3688
3689 static int
3690 i40e_dev_led_off(struct rte_eth_dev *dev)
3691 {
3692         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3693         uint32_t mode = i40e_led_get(hw);
3694
3695         if (mode != 0)
3696                 i40e_led_set(hw, 0, false);
3697
3698         return 0;
3699 }
3700
3701 static int
3702 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3703 {
3704         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3705         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3706
3707         fc_conf->pause_time = pf->fc_conf.pause_time;
3708
3709         /* read out from register, in case they are modified by other port */
3710         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3711                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3712         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3713                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3714
3715         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3716         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3717
3718          /* Return current mode according to actual setting*/
3719         switch (hw->fc.current_mode) {
3720         case I40E_FC_FULL:
3721                 fc_conf->mode = RTE_FC_FULL;
3722                 break;
3723         case I40E_FC_TX_PAUSE:
3724                 fc_conf->mode = RTE_FC_TX_PAUSE;
3725                 break;
3726         case I40E_FC_RX_PAUSE:
3727                 fc_conf->mode = RTE_FC_RX_PAUSE;
3728                 break;
3729         case I40E_FC_NONE:
3730         default:
3731                 fc_conf->mode = RTE_FC_NONE;
3732         };
3733
3734         return 0;
3735 }
3736
3737 static int
3738 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3739 {
3740         uint32_t mflcn_reg, fctrl_reg, reg;
3741         uint32_t max_high_water;
3742         uint8_t i, aq_failure;
3743         int err;
3744         struct i40e_hw *hw;
3745         struct i40e_pf *pf;
3746         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3747                 [RTE_FC_NONE] = I40E_FC_NONE,
3748                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3749                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3750                 [RTE_FC_FULL] = I40E_FC_FULL
3751         };
3752
3753         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3754
3755         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3756         if ((fc_conf->high_water > max_high_water) ||
3757                         (fc_conf->high_water < fc_conf->low_water)) {
3758                 PMD_INIT_LOG(ERR,
3759                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3760                         max_high_water);
3761                 return -EINVAL;
3762         }
3763
3764         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3765         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3766         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3767
3768         pf->fc_conf.pause_time = fc_conf->pause_time;
3769         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3770         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3771
3772         PMD_INIT_FUNC_TRACE();
3773
3774         /* All the link flow control related enable/disable register
3775          * configuration is handle by the F/W
3776          */
3777         err = i40e_set_fc(hw, &aq_failure, true);
3778         if (err < 0)
3779                 return -ENOSYS;
3780
3781         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3782                 /* Configure flow control refresh threshold,
3783                  * the value for stat_tx_pause_refresh_timer[8]
3784                  * is used for global pause operation.
3785                  */
3786
3787                 I40E_WRITE_REG(hw,
3788                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3789                                pf->fc_conf.pause_time);
3790
3791                 /* configure the timer value included in transmitted pause
3792                  * frame,
3793                  * the value for stat_tx_pause_quanta[8] is used for global
3794                  * pause operation
3795                  */
3796                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3797                                pf->fc_conf.pause_time);
3798
3799                 fctrl_reg = I40E_READ_REG(hw,
3800                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3801
3802                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3803                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3804                 else
3805                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3806
3807                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3808                                fctrl_reg);
3809         } else {
3810                 /* Configure pause time (2 TCs per register) */
3811                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3812                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3813                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3814
3815                 /* Configure flow control refresh threshold value */
3816                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3817                                pf->fc_conf.pause_time / 2);
3818
3819                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3820
3821                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3822                  *depending on configuration
3823                  */
3824                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3825                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3826                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3827                 } else {
3828                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3829                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3830                 }
3831
3832                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3833         }
3834
3835         if (!pf->support_multi_driver) {
3836                 /* config water marker both based on the packets and bytes */
3837                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3838                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3839                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3840                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3841                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3842                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3843                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3844                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3845                                   << I40E_KILOSHIFT);
3846                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3847                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3848                                    << I40E_KILOSHIFT);
3849         } else {
3850                 PMD_DRV_LOG(ERR,
3851                             "Water marker configuration is not supported.");
3852         }
3853
3854         I40E_WRITE_FLUSH(hw);
3855
3856         return 0;
3857 }
3858
3859 static int
3860 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3861                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3862 {
3863         PMD_INIT_FUNC_TRACE();
3864
3865         return -ENOSYS;
3866 }
3867
3868 /* Add a MAC address, and update filters */
3869 static int
3870 i40e_macaddr_add(struct rte_eth_dev *dev,
3871                  struct ether_addr *mac_addr,
3872                  __rte_unused uint32_t index,
3873                  uint32_t pool)
3874 {
3875         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3876         struct i40e_mac_filter_info mac_filter;
3877         struct i40e_vsi *vsi;
3878         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3879         int ret;
3880
3881         /* If VMDQ not enabled or configured, return */
3882         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3883                           !pf->nb_cfg_vmdq_vsi)) {
3884                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3885                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3886                         pool);
3887                 return -ENOTSUP;
3888         }
3889
3890         if (pool > pf->nb_cfg_vmdq_vsi) {
3891                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3892                                 pool, pf->nb_cfg_vmdq_vsi);
3893                 return -EINVAL;
3894         }
3895
3896         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3897         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3898                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3899         else
3900                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3901
3902         if (pool == 0)
3903                 vsi = pf->main_vsi;
3904         else
3905                 vsi = pf->vmdq[pool - 1].vsi;
3906
3907         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3908         if (ret != I40E_SUCCESS) {
3909                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3910                 return -ENODEV;
3911         }
3912         return 0;
3913 }
3914
3915 /* Remove a MAC address, and update filters */
3916 static void
3917 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3918 {
3919         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3920         struct i40e_vsi *vsi;
3921         struct rte_eth_dev_data *data = dev->data;
3922         struct ether_addr *macaddr;
3923         int ret;
3924         uint32_t i;
3925         uint64_t pool_sel;
3926
3927         macaddr = &(data->mac_addrs[index]);
3928
3929         pool_sel = dev->data->mac_pool_sel[index];
3930
3931         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3932                 if (pool_sel & (1ULL << i)) {
3933                         if (i == 0)
3934                                 vsi = pf->main_vsi;
3935                         else {
3936                                 /* No VMDQ pool enabled or configured */
3937                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3938                                         (i > pf->nb_cfg_vmdq_vsi)) {
3939                                         PMD_DRV_LOG(ERR,
3940                                                 "No VMDQ pool enabled/configured");
3941                                         return;
3942                                 }
3943                                 vsi = pf->vmdq[i - 1].vsi;
3944                         }
3945                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3946
3947                         if (ret) {
3948                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3949                                 return;
3950                         }
3951                 }
3952         }
3953 }
3954
3955 /* Set perfect match or hash match of MAC and VLAN for a VF */
3956 static int
3957 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3958                  struct rte_eth_mac_filter *filter,
3959                  bool add)
3960 {
3961         struct i40e_hw *hw;
3962         struct i40e_mac_filter_info mac_filter;
3963         struct ether_addr old_mac;
3964         struct ether_addr *new_mac;
3965         struct i40e_pf_vf *vf = NULL;
3966         uint16_t vf_id;
3967         int ret;
3968
3969         if (pf == NULL) {
3970                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3971                 return -EINVAL;
3972         }
3973         hw = I40E_PF_TO_HW(pf);
3974
3975         if (filter == NULL) {
3976                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3977                 return -EINVAL;
3978         }
3979
3980         new_mac = &filter->mac_addr;
3981
3982         if (is_zero_ether_addr(new_mac)) {
3983                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3984                 return -EINVAL;
3985         }
3986
3987         vf_id = filter->dst_id;
3988
3989         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3990                 PMD_DRV_LOG(ERR, "Invalid argument.");
3991                 return -EINVAL;
3992         }
3993         vf = &pf->vfs[vf_id];
3994
3995         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3996                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3997                 return -EINVAL;
3998         }
3999
4000         if (add) {
4001                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
4002                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4003                                 ETHER_ADDR_LEN);
4004                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4005                                  ETHER_ADDR_LEN);
4006
4007                 mac_filter.filter_type = filter->filter_type;
4008                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4009                 if (ret != I40E_SUCCESS) {
4010                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4011                         return -1;
4012                 }
4013                 ether_addr_copy(new_mac, &pf->dev_addr);
4014         } else {
4015                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4016                                 ETHER_ADDR_LEN);
4017                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4018                 if (ret != I40E_SUCCESS) {
4019                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4020                         return -1;
4021                 }
4022
4023                 /* Clear device address as it has been removed */
4024                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
4025                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
4026         }
4027
4028         return 0;
4029 }
4030
4031 /* MAC filter handle */
4032 static int
4033 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4034                 void *arg)
4035 {
4036         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4037         struct rte_eth_mac_filter *filter;
4038         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4039         int ret = I40E_NOT_SUPPORTED;
4040
4041         filter = (struct rte_eth_mac_filter *)(arg);
4042
4043         switch (filter_op) {
4044         case RTE_ETH_FILTER_NOP:
4045                 ret = I40E_SUCCESS;
4046                 break;
4047         case RTE_ETH_FILTER_ADD:
4048                 i40e_pf_disable_irq0(hw);
4049                 if (filter->is_vf)
4050                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4051                 i40e_pf_enable_irq0(hw);
4052                 break;
4053         case RTE_ETH_FILTER_DELETE:
4054                 i40e_pf_disable_irq0(hw);
4055                 if (filter->is_vf)
4056                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4057                 i40e_pf_enable_irq0(hw);
4058                 break;
4059         default:
4060                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4061                 ret = I40E_ERR_PARAM;
4062                 break;
4063         }
4064
4065         return ret;
4066 }
4067
4068 static int
4069 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4070 {
4071         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4072         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4073         uint32_t reg;
4074         int ret;
4075
4076         if (!lut)
4077                 return -EINVAL;
4078
4079         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4080                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4081                                           lut, lut_size);
4082                 if (ret) {
4083                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4084                         return ret;
4085                 }
4086         } else {
4087                 uint32_t *lut_dw = (uint32_t *)lut;
4088                 uint16_t i, lut_size_dw = lut_size / 4;
4089
4090                 if (vsi->type == I40E_VSI_SRIOV) {
4091                         for (i = 0; i <= lut_size_dw; i++) {
4092                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4093                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4094                         }
4095                 } else {
4096                         for (i = 0; i < lut_size_dw; i++)
4097                                 lut_dw[i] = I40E_READ_REG(hw,
4098                                                           I40E_PFQF_HLUT(i));
4099                 }
4100         }
4101
4102         return 0;
4103 }
4104
4105 int
4106 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4107 {
4108         struct i40e_pf *pf;
4109         struct i40e_hw *hw;
4110         int ret;
4111
4112         if (!vsi || !lut)
4113                 return -EINVAL;
4114
4115         pf = I40E_VSI_TO_PF(vsi);
4116         hw = I40E_VSI_TO_HW(vsi);
4117
4118         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4119                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4120                                           lut, lut_size);
4121                 if (ret) {
4122                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4123                         return ret;
4124                 }
4125         } else {
4126                 uint32_t *lut_dw = (uint32_t *)lut;
4127                 uint16_t i, lut_size_dw = lut_size / 4;
4128
4129                 if (vsi->type == I40E_VSI_SRIOV) {
4130                         for (i = 0; i < lut_size_dw; i++)
4131                                 I40E_WRITE_REG(
4132                                         hw,
4133                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4134                                         lut_dw[i]);
4135                 } else {
4136                         for (i = 0; i < lut_size_dw; i++)
4137                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4138                                                lut_dw[i]);
4139                 }
4140                 I40E_WRITE_FLUSH(hw);
4141         }
4142
4143         return 0;
4144 }
4145
4146 static int
4147 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4148                          struct rte_eth_rss_reta_entry64 *reta_conf,
4149                          uint16_t reta_size)
4150 {
4151         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4152         uint16_t i, lut_size = pf->hash_lut_size;
4153         uint16_t idx, shift;
4154         uint8_t *lut;
4155         int ret;
4156
4157         if (reta_size != lut_size ||
4158                 reta_size > ETH_RSS_RETA_SIZE_512) {
4159                 PMD_DRV_LOG(ERR,
4160                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4161                         reta_size, lut_size);
4162                 return -EINVAL;
4163         }
4164
4165         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4166         if (!lut) {
4167                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4168                 return -ENOMEM;
4169         }
4170         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4171         if (ret)
4172                 goto out;
4173         for (i = 0; i < reta_size; i++) {
4174                 idx = i / RTE_RETA_GROUP_SIZE;
4175                 shift = i % RTE_RETA_GROUP_SIZE;
4176                 if (reta_conf[idx].mask & (1ULL << shift))
4177                         lut[i] = reta_conf[idx].reta[shift];
4178         }
4179         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4180
4181 out:
4182         rte_free(lut);
4183
4184         return ret;
4185 }
4186
4187 static int
4188 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4189                         struct rte_eth_rss_reta_entry64 *reta_conf,
4190                         uint16_t reta_size)
4191 {
4192         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4193         uint16_t i, lut_size = pf->hash_lut_size;
4194         uint16_t idx, shift;
4195         uint8_t *lut;
4196         int ret;
4197
4198         if (reta_size != lut_size ||
4199                 reta_size > ETH_RSS_RETA_SIZE_512) {
4200                 PMD_DRV_LOG(ERR,
4201                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4202                         reta_size, lut_size);
4203                 return -EINVAL;
4204         }
4205
4206         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4207         if (!lut) {
4208                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4209                 return -ENOMEM;
4210         }
4211
4212         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4213         if (ret)
4214                 goto out;
4215         for (i = 0; i < reta_size; i++) {
4216                 idx = i / RTE_RETA_GROUP_SIZE;
4217                 shift = i % RTE_RETA_GROUP_SIZE;
4218                 if (reta_conf[idx].mask & (1ULL << shift))
4219                         reta_conf[idx].reta[shift] = lut[i];
4220         }
4221
4222 out:
4223         rte_free(lut);
4224
4225         return ret;
4226 }
4227
4228 /**
4229  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4230  * @hw:   pointer to the HW structure
4231  * @mem:  pointer to mem struct to fill out
4232  * @size: size of memory requested
4233  * @alignment: what to align the allocation to
4234  **/
4235 enum i40e_status_code
4236 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4237                         struct i40e_dma_mem *mem,
4238                         u64 size,
4239                         u32 alignment)
4240 {
4241         const struct rte_memzone *mz = NULL;
4242         char z_name[RTE_MEMZONE_NAMESIZE];
4243
4244         if (!mem)
4245                 return I40E_ERR_PARAM;
4246
4247         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4248         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4249                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4250         if (!mz)
4251                 return I40E_ERR_NO_MEMORY;
4252
4253         mem->size = size;
4254         mem->va = mz->addr;
4255         mem->pa = mz->iova;
4256         mem->zone = (const void *)mz;
4257         PMD_DRV_LOG(DEBUG,
4258                 "memzone %s allocated with physical address: %"PRIu64,
4259                 mz->name, mem->pa);
4260
4261         return I40E_SUCCESS;
4262 }
4263
4264 /**
4265  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4266  * @hw:   pointer to the HW structure
4267  * @mem:  ptr to mem struct to free
4268  **/
4269 enum i40e_status_code
4270 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4271                     struct i40e_dma_mem *mem)
4272 {
4273         if (!mem)
4274                 return I40E_ERR_PARAM;
4275
4276         PMD_DRV_LOG(DEBUG,
4277                 "memzone %s to be freed with physical address: %"PRIu64,
4278                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4279         rte_memzone_free((const struct rte_memzone *)mem->zone);
4280         mem->zone = NULL;
4281         mem->va = NULL;
4282         mem->pa = (u64)0;
4283
4284         return I40E_SUCCESS;
4285 }
4286
4287 /**
4288  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4289  * @hw:   pointer to the HW structure
4290  * @mem:  pointer to mem struct to fill out
4291  * @size: size of memory requested
4292  **/
4293 enum i40e_status_code
4294 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4295                          struct i40e_virt_mem *mem,
4296                          u32 size)
4297 {
4298         if (!mem)
4299                 return I40E_ERR_PARAM;
4300
4301         mem->size = size;
4302         mem->va = rte_zmalloc("i40e", size, 0);
4303
4304         if (mem->va)
4305                 return I40E_SUCCESS;
4306         else
4307                 return I40E_ERR_NO_MEMORY;
4308 }
4309
4310 /**
4311  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4312  * @hw:   pointer to the HW structure
4313  * @mem:  pointer to mem struct to free
4314  **/
4315 enum i40e_status_code
4316 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4317                      struct i40e_virt_mem *mem)
4318 {
4319         if (!mem)
4320                 return I40E_ERR_PARAM;
4321
4322         rte_free(mem->va);
4323         mem->va = NULL;
4324
4325         return I40E_SUCCESS;
4326 }
4327
4328 void
4329 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4330 {
4331         rte_spinlock_init(&sp->spinlock);
4332 }
4333
4334 void
4335 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4336 {
4337         rte_spinlock_lock(&sp->spinlock);
4338 }
4339
4340 void
4341 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4342 {
4343         rte_spinlock_unlock(&sp->spinlock);
4344 }
4345
4346 void
4347 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4348 {
4349         return;
4350 }
4351
4352 /**
4353  * Get the hardware capabilities, which will be parsed
4354  * and saved into struct i40e_hw.
4355  */
4356 static int
4357 i40e_get_cap(struct i40e_hw *hw)
4358 {
4359         struct i40e_aqc_list_capabilities_element_resp *buf;
4360         uint16_t len, size = 0;
4361         int ret;
4362
4363         /* Calculate a huge enough buff for saving response data temporarily */
4364         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4365                                                 I40E_MAX_CAP_ELE_NUM;
4366         buf = rte_zmalloc("i40e", len, 0);
4367         if (!buf) {
4368                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4369                 return I40E_ERR_NO_MEMORY;
4370         }
4371
4372         /* Get, parse the capabilities and save it to hw */
4373         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4374                         i40e_aqc_opc_list_func_capabilities, NULL);
4375         if (ret != I40E_SUCCESS)
4376                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4377
4378         /* Free the temporary buffer after being used */
4379         rte_free(buf);
4380
4381         return ret;
4382 }
4383
4384 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4385
4386 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4387                 const char *value,
4388                 void *opaque)
4389 {
4390         struct i40e_pf *pf;
4391         unsigned long num;
4392         char *end;
4393
4394         pf = (struct i40e_pf *)opaque;
4395         RTE_SET_USED(key);
4396
4397         errno = 0;
4398         num = strtoul(value, &end, 0);
4399         if (errno != 0 || end == value || *end != 0) {
4400                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4401                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4402                 return -(EINVAL);
4403         }
4404
4405         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4406                 pf->vf_nb_qp_max = (uint16_t)num;
4407         else
4408                 /* here return 0 to make next valid same argument work */
4409                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4410                             "power of 2 and equal or less than 16 !, Now it is "
4411                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4412
4413         return 0;
4414 }
4415
4416 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4417 {
4418         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4419         struct rte_kvargs *kvlist;
4420         int kvargs_count;
4421
4422         /* set default queue number per VF as 4 */
4423         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4424
4425         if (dev->device->devargs == NULL)
4426                 return 0;
4427
4428         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4429         if (kvlist == NULL)
4430                 return -(EINVAL);
4431
4432         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4433         if (!kvargs_count) {
4434                 rte_kvargs_free(kvlist);
4435                 return 0;
4436         }
4437
4438         if (kvargs_count > 1)
4439                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4440                             "the first invalid or last valid one is used !",
4441                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4442
4443         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4444                            i40e_pf_parse_vf_queue_number_handler, pf);
4445
4446         rte_kvargs_free(kvlist);
4447
4448         return 0;
4449 }
4450
4451 static int
4452 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4453 {
4454         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4455         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4456         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4457         uint16_t qp_count = 0, vsi_count = 0;
4458
4459         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4460                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4461                 return -EINVAL;
4462         }
4463
4464         i40e_pf_config_vf_rxq_number(dev);
4465
4466         /* Add the parameter init for LFC */
4467         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4468         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4469         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4470
4471         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4472         pf->max_num_vsi = hw->func_caps.num_vsis;
4473         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4474         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4475
4476         /* FDir queue/VSI allocation */
4477         pf->fdir_qp_offset = 0;
4478         if (hw->func_caps.fd) {
4479                 pf->flags |= I40E_FLAG_FDIR;
4480                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4481         } else {
4482                 pf->fdir_nb_qps = 0;
4483         }
4484         qp_count += pf->fdir_nb_qps;
4485         vsi_count += 1;
4486
4487         /* LAN queue/VSI allocation */
4488         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4489         if (!hw->func_caps.rss) {
4490                 pf->lan_nb_qps = 1;
4491         } else {
4492                 pf->flags |= I40E_FLAG_RSS;
4493                 if (hw->mac.type == I40E_MAC_X722)
4494                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4495                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4496         }
4497         qp_count += pf->lan_nb_qps;
4498         vsi_count += 1;
4499
4500         /* VF queue/VSI allocation */
4501         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4502         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4503                 pf->flags |= I40E_FLAG_SRIOV;
4504                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4505                 pf->vf_num = pci_dev->max_vfs;
4506                 PMD_DRV_LOG(DEBUG,
4507                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4508                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4509         } else {
4510                 pf->vf_nb_qps = 0;
4511                 pf->vf_num = 0;
4512         }
4513         qp_count += pf->vf_nb_qps * pf->vf_num;
4514         vsi_count += pf->vf_num;
4515
4516         /* VMDq queue/VSI allocation */
4517         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4518         pf->vmdq_nb_qps = 0;
4519         pf->max_nb_vmdq_vsi = 0;
4520         if (hw->func_caps.vmdq) {
4521                 if (qp_count < hw->func_caps.num_tx_qp &&
4522                         vsi_count < hw->func_caps.num_vsis) {
4523                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4524                                 qp_count) / pf->vmdq_nb_qp_max;
4525
4526                         /* Limit the maximum number of VMDq vsi to the maximum
4527                          * ethdev can support
4528                          */
4529                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4530                                 hw->func_caps.num_vsis - vsi_count);
4531                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4532                                 ETH_64_POOLS);
4533                         if (pf->max_nb_vmdq_vsi) {
4534                                 pf->flags |= I40E_FLAG_VMDQ;
4535                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4536                                 PMD_DRV_LOG(DEBUG,
4537                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4538                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4539                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4540                         } else {
4541                                 PMD_DRV_LOG(INFO,
4542                                         "No enough queues left for VMDq");
4543                         }
4544                 } else {
4545                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4546                 }
4547         }
4548         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4549         vsi_count += pf->max_nb_vmdq_vsi;
4550
4551         if (hw->func_caps.dcb)
4552                 pf->flags |= I40E_FLAG_DCB;
4553
4554         if (qp_count > hw->func_caps.num_tx_qp) {
4555                 PMD_DRV_LOG(ERR,
4556                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4557                         qp_count, hw->func_caps.num_tx_qp);
4558                 return -EINVAL;
4559         }
4560         if (vsi_count > hw->func_caps.num_vsis) {
4561                 PMD_DRV_LOG(ERR,
4562                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4563                         vsi_count, hw->func_caps.num_vsis);
4564                 return -EINVAL;
4565         }
4566
4567         return 0;
4568 }
4569
4570 static int
4571 i40e_pf_get_switch_config(struct i40e_pf *pf)
4572 {
4573         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4574         struct i40e_aqc_get_switch_config_resp *switch_config;
4575         struct i40e_aqc_switch_config_element_resp *element;
4576         uint16_t start_seid = 0, num_reported;
4577         int ret;
4578
4579         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4580                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4581         if (!switch_config) {
4582                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4583                 return -ENOMEM;
4584         }
4585
4586         /* Get the switch configurations */
4587         ret = i40e_aq_get_switch_config(hw, switch_config,
4588                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4589         if (ret != I40E_SUCCESS) {
4590                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4591                 goto fail;
4592         }
4593         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4594         if (num_reported != 1) { /* The number should be 1 */
4595                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4596                 goto fail;
4597         }
4598
4599         /* Parse the switch configuration elements */
4600         element = &(switch_config->element[0]);
4601         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4602                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4603                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4604         } else
4605                 PMD_DRV_LOG(INFO, "Unknown element type");
4606
4607 fail:
4608         rte_free(switch_config);
4609
4610         return ret;
4611 }
4612
4613 static int
4614 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4615                         uint32_t num)
4616 {
4617         struct pool_entry *entry;
4618
4619         if (pool == NULL || num == 0)
4620                 return -EINVAL;
4621
4622         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4623         if (entry == NULL) {
4624                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4625                 return -ENOMEM;
4626         }
4627
4628         /* queue heap initialize */
4629         pool->num_free = num;
4630         pool->num_alloc = 0;
4631         pool->base = base;
4632         LIST_INIT(&pool->alloc_list);
4633         LIST_INIT(&pool->free_list);
4634
4635         /* Initialize element  */
4636         entry->base = 0;
4637         entry->len = num;
4638
4639         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4640         return 0;
4641 }
4642
4643 static void
4644 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4645 {
4646         struct pool_entry *entry, *next_entry;
4647
4648         if (pool == NULL)
4649                 return;
4650
4651         for (entry = LIST_FIRST(&pool->alloc_list);
4652                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4653                         entry = next_entry) {
4654                 LIST_REMOVE(entry, next);
4655                 rte_free(entry);
4656         }
4657
4658         for (entry = LIST_FIRST(&pool->free_list);
4659                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4660                         entry = next_entry) {
4661                 LIST_REMOVE(entry, next);
4662                 rte_free(entry);
4663         }
4664
4665         pool->num_free = 0;
4666         pool->num_alloc = 0;
4667         pool->base = 0;
4668         LIST_INIT(&pool->alloc_list);
4669         LIST_INIT(&pool->free_list);
4670 }
4671
4672 static int
4673 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4674                        uint32_t base)
4675 {
4676         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4677         uint32_t pool_offset;
4678         int insert;
4679
4680         if (pool == NULL) {
4681                 PMD_DRV_LOG(ERR, "Invalid parameter");
4682                 return -EINVAL;
4683         }
4684
4685         pool_offset = base - pool->base;
4686         /* Lookup in alloc list */
4687         LIST_FOREACH(entry, &pool->alloc_list, next) {
4688                 if (entry->base == pool_offset) {
4689                         valid_entry = entry;
4690                         LIST_REMOVE(entry, next);
4691                         break;
4692                 }
4693         }
4694
4695         /* Not find, return */
4696         if (valid_entry == NULL) {
4697                 PMD_DRV_LOG(ERR, "Failed to find entry");
4698                 return -EINVAL;
4699         }
4700
4701         /**
4702          * Found it, move it to free list  and try to merge.
4703          * In order to make merge easier, always sort it by qbase.
4704          * Find adjacent prev and last entries.
4705          */
4706         prev = next = NULL;
4707         LIST_FOREACH(entry, &pool->free_list, next) {
4708                 if (entry->base > valid_entry->base) {
4709                         next = entry;
4710                         break;
4711                 }
4712                 prev = entry;
4713         }
4714
4715         insert = 0;
4716         /* Try to merge with next one*/
4717         if (next != NULL) {
4718                 /* Merge with next one */
4719                 if (valid_entry->base + valid_entry->len == next->base) {
4720                         next->base = valid_entry->base;
4721                         next->len += valid_entry->len;
4722                         rte_free(valid_entry);
4723                         valid_entry = next;
4724                         insert = 1;
4725                 }
4726         }
4727
4728         if (prev != NULL) {
4729                 /* Merge with previous one */
4730                 if (prev->base + prev->len == valid_entry->base) {
4731                         prev->len += valid_entry->len;
4732                         /* If it merge with next one, remove next node */
4733                         if (insert == 1) {
4734                                 LIST_REMOVE(valid_entry, next);
4735                                 rte_free(valid_entry);
4736                         } else {
4737                                 rte_free(valid_entry);
4738                                 insert = 1;
4739                         }
4740                 }
4741         }
4742
4743         /* Not find any entry to merge, insert */
4744         if (insert == 0) {
4745                 if (prev != NULL)
4746                         LIST_INSERT_AFTER(prev, valid_entry, next);
4747                 else if (next != NULL)
4748                         LIST_INSERT_BEFORE(next, valid_entry, next);
4749                 else /* It's empty list, insert to head */
4750                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4751         }
4752
4753         pool->num_free += valid_entry->len;
4754         pool->num_alloc -= valid_entry->len;
4755
4756         return 0;
4757 }
4758
4759 static int
4760 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4761                        uint16_t num)
4762 {
4763         struct pool_entry *entry, *valid_entry;
4764
4765         if (pool == NULL || num == 0) {
4766                 PMD_DRV_LOG(ERR, "Invalid parameter");
4767                 return -EINVAL;
4768         }
4769
4770         if (pool->num_free < num) {
4771                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4772                             num, pool->num_free);
4773                 return -ENOMEM;
4774         }
4775
4776         valid_entry = NULL;
4777         /* Lookup  in free list and find most fit one */
4778         LIST_FOREACH(entry, &pool->free_list, next) {
4779                 if (entry->len >= num) {
4780                         /* Find best one */
4781                         if (entry->len == num) {
4782                                 valid_entry = entry;
4783                                 break;
4784                         }
4785                         if (valid_entry == NULL || valid_entry->len > entry->len)
4786                                 valid_entry = entry;
4787                 }
4788         }
4789
4790         /* Not find one to satisfy the request, return */
4791         if (valid_entry == NULL) {
4792                 PMD_DRV_LOG(ERR, "No valid entry found");
4793                 return -ENOMEM;
4794         }
4795         /**
4796          * The entry have equal queue number as requested,
4797          * remove it from alloc_list.
4798          */
4799         if (valid_entry->len == num) {
4800                 LIST_REMOVE(valid_entry, next);
4801         } else {
4802                 /**
4803                  * The entry have more numbers than requested,
4804                  * create a new entry for alloc_list and minus its
4805                  * queue base and number in free_list.
4806                  */
4807                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4808                 if (entry == NULL) {
4809                         PMD_DRV_LOG(ERR,
4810                                 "Failed to allocate memory for resource pool");
4811                         return -ENOMEM;
4812                 }
4813                 entry->base = valid_entry->base;
4814                 entry->len = num;
4815                 valid_entry->base += num;
4816                 valid_entry->len -= num;
4817                 valid_entry = entry;
4818         }
4819
4820         /* Insert it into alloc list, not sorted */
4821         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4822
4823         pool->num_free -= valid_entry->len;
4824         pool->num_alloc += valid_entry->len;
4825
4826         return valid_entry->base + pool->base;
4827 }
4828
4829 /**
4830  * bitmap_is_subset - Check whether src2 is subset of src1
4831  **/
4832 static inline int
4833 bitmap_is_subset(uint8_t src1, uint8_t src2)
4834 {
4835         return !((src1 ^ src2) & src2);
4836 }
4837
4838 static enum i40e_status_code
4839 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4840 {
4841         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4842
4843         /* If DCB is not supported, only default TC is supported */
4844         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4845                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4846                 return I40E_NOT_SUPPORTED;
4847         }
4848
4849         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4850                 PMD_DRV_LOG(ERR,
4851                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4852                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4853                 return I40E_NOT_SUPPORTED;
4854         }
4855         return I40E_SUCCESS;
4856 }
4857
4858 int
4859 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4860                                 struct i40e_vsi_vlan_pvid_info *info)
4861 {
4862         struct i40e_hw *hw;
4863         struct i40e_vsi_context ctxt;
4864         uint8_t vlan_flags = 0;
4865         int ret;
4866
4867         if (vsi == NULL || info == NULL) {
4868                 PMD_DRV_LOG(ERR, "invalid parameters");
4869                 return I40E_ERR_PARAM;
4870         }
4871
4872         if (info->on) {
4873                 vsi->info.pvid = info->config.pvid;
4874                 /**
4875                  * If insert pvid is enabled, only tagged pkts are
4876                  * allowed to be sent out.
4877                  */
4878                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4879                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4880         } else {
4881                 vsi->info.pvid = 0;
4882                 if (info->config.reject.tagged == 0)
4883                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4884
4885                 if (info->config.reject.untagged == 0)
4886                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4887         }
4888         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4889                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4890         vsi->info.port_vlan_flags |= vlan_flags;
4891         vsi->info.valid_sections =
4892                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4893         memset(&ctxt, 0, sizeof(ctxt));
4894         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4895         ctxt.seid = vsi->seid;
4896
4897         hw = I40E_VSI_TO_HW(vsi);
4898         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4899         if (ret != I40E_SUCCESS)
4900                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4901
4902         return ret;
4903 }
4904
4905 static int
4906 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4907 {
4908         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4909         int i, ret;
4910         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4911
4912         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4913         if (ret != I40E_SUCCESS)
4914                 return ret;
4915
4916         if (!vsi->seid) {
4917                 PMD_DRV_LOG(ERR, "seid not valid");
4918                 return -EINVAL;
4919         }
4920
4921         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4922         tc_bw_data.tc_valid_bits = enabled_tcmap;
4923         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4924                 tc_bw_data.tc_bw_credits[i] =
4925                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4926
4927         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4928         if (ret != I40E_SUCCESS) {
4929                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4930                 return ret;
4931         }
4932
4933         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4934                                         sizeof(vsi->info.qs_handle));
4935         return I40E_SUCCESS;
4936 }
4937
4938 static enum i40e_status_code
4939 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4940                                  struct i40e_aqc_vsi_properties_data *info,
4941                                  uint8_t enabled_tcmap)
4942 {
4943         enum i40e_status_code ret;
4944         int i, total_tc = 0;
4945         uint16_t qpnum_per_tc, bsf, qp_idx;
4946
4947         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4948         if (ret != I40E_SUCCESS)
4949                 return ret;
4950
4951         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4952                 if (enabled_tcmap & (1 << i))
4953                         total_tc++;
4954         if (total_tc == 0)
4955                 total_tc = 1;
4956         vsi->enabled_tc = enabled_tcmap;
4957
4958         /* Number of queues per enabled TC */
4959         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4960         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4961         bsf = rte_bsf32(qpnum_per_tc);
4962
4963         /* Adjust the queue number to actual queues that can be applied */
4964         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4965                 vsi->nb_qps = qpnum_per_tc * total_tc;
4966
4967         /**
4968          * Configure TC and queue mapping parameters, for enabled TC,
4969          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4970          * default queue will serve it.
4971          */
4972         qp_idx = 0;
4973         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4974                 if (vsi->enabled_tc & (1 << i)) {
4975                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4976                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4977                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4978                         qp_idx += qpnum_per_tc;
4979                 } else
4980                         info->tc_mapping[i] = 0;
4981         }
4982
4983         /* Associate queue number with VSI */
4984         if (vsi->type == I40E_VSI_SRIOV) {
4985                 info->mapping_flags |=
4986                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4987                 for (i = 0; i < vsi->nb_qps; i++)
4988                         info->queue_mapping[i] =
4989                                 rte_cpu_to_le_16(vsi->base_queue + i);
4990         } else {
4991                 info->mapping_flags |=
4992                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4993                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4994         }
4995         info->valid_sections |=
4996                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4997
4998         return I40E_SUCCESS;
4999 }
5000
5001 static int
5002 i40e_veb_release(struct i40e_veb *veb)
5003 {
5004         struct i40e_vsi *vsi;
5005         struct i40e_hw *hw;
5006
5007         if (veb == NULL)
5008                 return -EINVAL;
5009
5010         if (!TAILQ_EMPTY(&veb->head)) {
5011                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5012                 return -EACCES;
5013         }
5014         /* associate_vsi field is NULL for floating VEB */
5015         if (veb->associate_vsi != NULL) {
5016                 vsi = veb->associate_vsi;
5017                 hw = I40E_VSI_TO_HW(vsi);
5018
5019                 vsi->uplink_seid = veb->uplink_seid;
5020                 vsi->veb = NULL;
5021         } else {
5022                 veb->associate_pf->main_vsi->floating_veb = NULL;
5023                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5024         }
5025
5026         i40e_aq_delete_element(hw, veb->seid, NULL);
5027         rte_free(veb);
5028         return I40E_SUCCESS;
5029 }
5030
5031 /* Setup a veb */
5032 static struct i40e_veb *
5033 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5034 {
5035         struct i40e_veb *veb;
5036         int ret;
5037         struct i40e_hw *hw;
5038
5039         if (pf == NULL) {
5040                 PMD_DRV_LOG(ERR,
5041                             "veb setup failed, associated PF shouldn't null");
5042                 return NULL;
5043         }
5044         hw = I40E_PF_TO_HW(pf);
5045
5046         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5047         if (!veb) {
5048                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5049                 goto fail;
5050         }
5051
5052         veb->associate_vsi = vsi;
5053         veb->associate_pf = pf;
5054         TAILQ_INIT(&veb->head);
5055         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5056
5057         /* create floating veb if vsi is NULL */
5058         if (vsi != NULL) {
5059                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5060                                       I40E_DEFAULT_TCMAP, false,
5061                                       &veb->seid, false, NULL);
5062         } else {
5063                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5064                                       true, &veb->seid, false, NULL);
5065         }
5066
5067         if (ret != I40E_SUCCESS) {
5068                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5069                             hw->aq.asq_last_status);
5070                 goto fail;
5071         }
5072         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5073
5074         /* get statistics index */
5075         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5076                                 &veb->stats_idx, NULL, NULL, NULL);
5077         if (ret != I40E_SUCCESS) {
5078                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5079                             hw->aq.asq_last_status);
5080                 goto fail;
5081         }
5082         /* Get VEB bandwidth, to be implemented */
5083         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5084         if (vsi)
5085                 vsi->uplink_seid = veb->seid;
5086
5087         return veb;
5088 fail:
5089         rte_free(veb);
5090         return NULL;
5091 }
5092
5093 int
5094 i40e_vsi_release(struct i40e_vsi *vsi)
5095 {
5096         struct i40e_pf *pf;
5097         struct i40e_hw *hw;
5098         struct i40e_vsi_list *vsi_list;
5099         void *temp;
5100         int ret;
5101         struct i40e_mac_filter *f;
5102         uint16_t user_param;
5103
5104         if (!vsi)
5105                 return I40E_SUCCESS;
5106
5107         if (!vsi->adapter)
5108                 return -EFAULT;
5109
5110         user_param = vsi->user_param;
5111
5112         pf = I40E_VSI_TO_PF(vsi);
5113         hw = I40E_VSI_TO_HW(vsi);
5114
5115         /* VSI has child to attach, release child first */
5116         if (vsi->veb) {
5117                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5118                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5119                                 return -1;
5120                 }
5121                 i40e_veb_release(vsi->veb);
5122         }
5123
5124         if (vsi->floating_veb) {
5125                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5126                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5127                                 return -1;
5128                 }
5129         }
5130
5131         /* Remove all macvlan filters of the VSI */
5132         i40e_vsi_remove_all_macvlan_filter(vsi);
5133         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5134                 rte_free(f);
5135
5136         if (vsi->type != I40E_VSI_MAIN &&
5137             ((vsi->type != I40E_VSI_SRIOV) ||
5138             !pf->floating_veb_list[user_param])) {
5139                 /* Remove vsi from parent's sibling list */
5140                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5141                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5142                         return I40E_ERR_PARAM;
5143                 }
5144                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5145                                 &vsi->sib_vsi_list, list);
5146
5147                 /* Remove all switch element of the VSI */
5148                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5149                 if (ret != I40E_SUCCESS)
5150                         PMD_DRV_LOG(ERR, "Failed to delete element");
5151         }
5152
5153         if ((vsi->type == I40E_VSI_SRIOV) &&
5154             pf->floating_veb_list[user_param]) {
5155                 /* Remove vsi from parent's sibling list */
5156                 if (vsi->parent_vsi == NULL ||
5157                     vsi->parent_vsi->floating_veb == NULL) {
5158                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5159                         return I40E_ERR_PARAM;
5160                 }
5161                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5162                              &vsi->sib_vsi_list, list);
5163
5164                 /* Remove all switch element of the VSI */
5165                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5166                 if (ret != I40E_SUCCESS)
5167                         PMD_DRV_LOG(ERR, "Failed to delete element");
5168         }
5169
5170         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5171
5172         if (vsi->type != I40E_VSI_SRIOV)
5173                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5174         rte_free(vsi);
5175
5176         return I40E_SUCCESS;
5177 }
5178
5179 static int
5180 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5181 {
5182         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5183         struct i40e_aqc_remove_macvlan_element_data def_filter;
5184         struct i40e_mac_filter_info filter;
5185         int ret;
5186
5187         if (vsi->type != I40E_VSI_MAIN)
5188                 return I40E_ERR_CONFIG;
5189         memset(&def_filter, 0, sizeof(def_filter));
5190         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5191                                         ETH_ADDR_LEN);
5192         def_filter.vlan_tag = 0;
5193         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5194                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5195         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5196         if (ret != I40E_SUCCESS) {
5197                 struct i40e_mac_filter *f;
5198                 struct ether_addr *mac;
5199
5200                 PMD_DRV_LOG(DEBUG,
5201                             "Cannot remove the default macvlan filter");
5202                 /* It needs to add the permanent mac into mac list */
5203                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5204                 if (f == NULL) {
5205                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5206                         return I40E_ERR_NO_MEMORY;
5207                 }
5208                 mac = &f->mac_info.mac_addr;
5209                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5210                                 ETH_ADDR_LEN);
5211                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5212                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5213                 vsi->mac_num++;
5214
5215                 return ret;
5216         }
5217         rte_memcpy(&filter.mac_addr,
5218                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5219         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5220         return i40e_vsi_add_mac(vsi, &filter);
5221 }
5222
5223 /*
5224  * i40e_vsi_get_bw_config - Query VSI BW Information
5225  * @vsi: the VSI to be queried
5226  *
5227  * Returns 0 on success, negative value on failure
5228  */
5229 static enum i40e_status_code
5230 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5231 {
5232         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5233         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5234         struct i40e_hw *hw = &vsi->adapter->hw;
5235         i40e_status ret;
5236         int i;
5237         uint32_t bw_max;
5238
5239         memset(&bw_config, 0, sizeof(bw_config));
5240         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5241         if (ret != I40E_SUCCESS) {
5242                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5243                             hw->aq.asq_last_status);
5244                 return ret;
5245         }
5246
5247         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5248         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5249                                         &ets_sla_config, NULL);
5250         if (ret != I40E_SUCCESS) {
5251                 PMD_DRV_LOG(ERR,
5252                         "VSI failed to get TC bandwdith configuration %u",
5253                         hw->aq.asq_last_status);
5254                 return ret;
5255         }
5256
5257         /* store and print out BW info */
5258         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5259         vsi->bw_info.bw_max = bw_config.max_bw;
5260         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5261         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5262         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5263                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5264                      I40E_16_BIT_WIDTH);
5265         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5266                 vsi->bw_info.bw_ets_share_credits[i] =
5267                                 ets_sla_config.share_credits[i];
5268                 vsi->bw_info.bw_ets_credits[i] =
5269                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5270                 /* 4 bits per TC, 4th bit is reserved */
5271                 vsi->bw_info.bw_ets_max[i] =
5272                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5273                                   RTE_LEN2MASK(3, uint8_t));
5274                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5275                             vsi->bw_info.bw_ets_share_credits[i]);
5276                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5277                             vsi->bw_info.bw_ets_credits[i]);
5278                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5279                             vsi->bw_info.bw_ets_max[i]);
5280         }
5281
5282         return I40E_SUCCESS;
5283 }
5284
5285 /* i40e_enable_pf_lb
5286  * @pf: pointer to the pf structure
5287  *
5288  * allow loopback on pf
5289  */
5290 static inline void
5291 i40e_enable_pf_lb(struct i40e_pf *pf)
5292 {
5293         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5294         struct i40e_vsi_context ctxt;
5295         int ret;
5296
5297         /* Use the FW API if FW >= v5.0 */
5298         if (hw->aq.fw_maj_ver < 5) {
5299                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5300                 return;
5301         }
5302
5303         memset(&ctxt, 0, sizeof(ctxt));
5304         ctxt.seid = pf->main_vsi_seid;
5305         ctxt.pf_num = hw->pf_id;
5306         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5307         if (ret) {
5308                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5309                             ret, hw->aq.asq_last_status);
5310                 return;
5311         }
5312         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5313         ctxt.info.valid_sections =
5314                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5315         ctxt.info.switch_id |=
5316                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5317
5318         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5319         if (ret)
5320                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5321                             hw->aq.asq_last_status);
5322 }
5323
5324 /* Setup a VSI */
5325 struct i40e_vsi *
5326 i40e_vsi_setup(struct i40e_pf *pf,
5327                enum i40e_vsi_type type,
5328                struct i40e_vsi *uplink_vsi,
5329                uint16_t user_param)
5330 {
5331         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5332         struct i40e_vsi *vsi;
5333         struct i40e_mac_filter_info filter;
5334         int ret;
5335         struct i40e_vsi_context ctxt;
5336         struct ether_addr broadcast =
5337                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5338
5339         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5340             uplink_vsi == NULL) {
5341                 PMD_DRV_LOG(ERR,
5342                         "VSI setup failed, VSI link shouldn't be NULL");
5343                 return NULL;
5344         }
5345
5346         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5347                 PMD_DRV_LOG(ERR,
5348                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5349                 return NULL;
5350         }
5351
5352         /* two situations
5353          * 1.type is not MAIN and uplink vsi is not NULL
5354          * If uplink vsi didn't setup VEB, create one first under veb field
5355          * 2.type is SRIOV and the uplink is NULL
5356          * If floating VEB is NULL, create one veb under floating veb field
5357          */
5358
5359         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5360             uplink_vsi->veb == NULL) {
5361                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5362
5363                 if (uplink_vsi->veb == NULL) {
5364                         PMD_DRV_LOG(ERR, "VEB setup failed");
5365                         return NULL;
5366                 }
5367                 /* set ALLOWLOOPBACk on pf, when veb is created */
5368                 i40e_enable_pf_lb(pf);
5369         }
5370
5371         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5372             pf->main_vsi->floating_veb == NULL) {
5373                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5374
5375                 if (pf->main_vsi->floating_veb == NULL) {
5376                         PMD_DRV_LOG(ERR, "VEB setup failed");
5377                         return NULL;
5378                 }
5379         }
5380
5381         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5382         if (!vsi) {
5383                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5384                 return NULL;
5385         }
5386         TAILQ_INIT(&vsi->mac_list);
5387         vsi->type = type;
5388         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5389         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5390         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5391         vsi->user_param = user_param;
5392         vsi->vlan_anti_spoof_on = 0;
5393         vsi->vlan_filter_on = 0;
5394         /* Allocate queues */
5395         switch (vsi->type) {
5396         case I40E_VSI_MAIN  :
5397                 vsi->nb_qps = pf->lan_nb_qps;
5398                 break;
5399         case I40E_VSI_SRIOV :
5400                 vsi->nb_qps = pf->vf_nb_qps;
5401                 break;
5402         case I40E_VSI_VMDQ2:
5403                 vsi->nb_qps = pf->vmdq_nb_qps;
5404                 break;
5405         case I40E_VSI_FDIR:
5406                 vsi->nb_qps = pf->fdir_nb_qps;
5407                 break;
5408         default:
5409                 goto fail_mem;
5410         }
5411         /*
5412          * The filter status descriptor is reported in rx queue 0,
5413          * while the tx queue for fdir filter programming has no
5414          * such constraints, can be non-zero queues.
5415          * To simplify it, choose FDIR vsi use queue 0 pair.
5416          * To make sure it will use queue 0 pair, queue allocation
5417          * need be done before this function is called
5418          */
5419         if (type != I40E_VSI_FDIR) {
5420                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5421                         if (ret < 0) {
5422                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5423                                                 vsi->seid, ret);
5424                                 goto fail_mem;
5425                         }
5426                         vsi->base_queue = ret;
5427         } else
5428                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5429
5430         /* VF has MSIX interrupt in VF range, don't allocate here */
5431         if (type == I40E_VSI_MAIN) {
5432                 if (pf->support_multi_driver) {
5433                         /* If support multi-driver, need to use INT0 instead of
5434                          * allocating from msix pool. The Msix pool is init from
5435                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5436                          * to 1 without calling i40e_res_pool_alloc.
5437                          */
5438                         vsi->msix_intr = 0;
5439                         vsi->nb_msix = 1;
5440                 } else {
5441                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5442                                                   RTE_MIN(vsi->nb_qps,
5443                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5444                         if (ret < 0) {
5445                                 PMD_DRV_LOG(ERR,
5446                                             "VSI MAIN %d get heap failed %d",
5447                                             vsi->seid, ret);
5448                                 goto fail_queue_alloc;
5449                         }
5450                         vsi->msix_intr = ret;
5451                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5452                                                RTE_MAX_RXTX_INTR_VEC_ID);
5453                 }
5454         } else if (type != I40E_VSI_SRIOV) {
5455                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5456                 if (ret < 0) {
5457                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5458                         goto fail_queue_alloc;
5459                 }
5460                 vsi->msix_intr = ret;
5461                 vsi->nb_msix = 1;
5462         } else {
5463                 vsi->msix_intr = 0;
5464                 vsi->nb_msix = 0;
5465         }
5466
5467         /* Add VSI */
5468         if (type == I40E_VSI_MAIN) {
5469                 /* For main VSI, no need to add since it's default one */
5470                 vsi->uplink_seid = pf->mac_seid;
5471                 vsi->seid = pf->main_vsi_seid;
5472                 /* Bind queues with specific MSIX interrupt */
5473                 /**
5474                  * Needs 2 interrupt at least, one for misc cause which will
5475                  * enabled from OS side, Another for queues binding the
5476                  * interrupt from device side only.
5477                  */
5478
5479                 /* Get default VSI parameters from hardware */
5480                 memset(&ctxt, 0, sizeof(ctxt));
5481                 ctxt.seid = vsi->seid;
5482                 ctxt.pf_num = hw->pf_id;
5483                 ctxt.uplink_seid = vsi->uplink_seid;
5484                 ctxt.vf_num = 0;
5485                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5486                 if (ret != I40E_SUCCESS) {
5487                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5488                         goto fail_msix_alloc;
5489                 }
5490                 rte_memcpy(&vsi->info, &ctxt.info,
5491                         sizeof(struct i40e_aqc_vsi_properties_data));
5492                 vsi->vsi_id = ctxt.vsi_number;
5493                 vsi->info.valid_sections = 0;
5494
5495                 /* Configure tc, enabled TC0 only */
5496                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5497                         I40E_SUCCESS) {
5498                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5499                         goto fail_msix_alloc;
5500                 }
5501
5502                 /* TC, queue mapping */
5503                 memset(&ctxt, 0, sizeof(ctxt));
5504                 vsi->info.valid_sections |=
5505                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5506                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5507                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5508                 rte_memcpy(&ctxt.info, &vsi->info,
5509                         sizeof(struct i40e_aqc_vsi_properties_data));
5510                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5511                                                 I40E_DEFAULT_TCMAP);
5512                 if (ret != I40E_SUCCESS) {
5513                         PMD_DRV_LOG(ERR,
5514                                 "Failed to configure TC queue mapping");
5515                         goto fail_msix_alloc;
5516                 }
5517                 ctxt.seid = vsi->seid;
5518                 ctxt.pf_num = hw->pf_id;
5519                 ctxt.uplink_seid = vsi->uplink_seid;
5520                 ctxt.vf_num = 0;
5521
5522                 /* Update VSI parameters */
5523                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5524                 if (ret != I40E_SUCCESS) {
5525                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5526                         goto fail_msix_alloc;
5527                 }
5528
5529                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5530                                                 sizeof(vsi->info.tc_mapping));
5531                 rte_memcpy(&vsi->info.queue_mapping,
5532                                 &ctxt.info.queue_mapping,
5533                         sizeof(vsi->info.queue_mapping));
5534                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5535                 vsi->info.valid_sections = 0;
5536
5537                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5538                                 ETH_ADDR_LEN);
5539
5540                 /**
5541                  * Updating default filter settings are necessary to prevent
5542                  * reception of tagged packets.
5543                  * Some old firmware configurations load a default macvlan
5544                  * filter which accepts both tagged and untagged packets.
5545                  * The updating is to use a normal filter instead if needed.
5546                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5547                  * The firmware with correct configurations load the default
5548                  * macvlan filter which is expected and cannot be removed.
5549                  */
5550                 i40e_update_default_filter_setting(vsi);
5551                 i40e_config_qinq(hw, vsi);
5552         } else if (type == I40E_VSI_SRIOV) {
5553                 memset(&ctxt, 0, sizeof(ctxt));
5554                 /**
5555                  * For other VSI, the uplink_seid equals to uplink VSI's
5556                  * uplink_seid since they share same VEB
5557                  */
5558                 if (uplink_vsi == NULL)
5559                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5560                 else
5561                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5562                 ctxt.pf_num = hw->pf_id;
5563                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5564                 ctxt.uplink_seid = vsi->uplink_seid;
5565                 ctxt.connection_type = 0x1;
5566                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5567
5568                 /* Use the VEB configuration if FW >= v5.0 */
5569                 if (hw->aq.fw_maj_ver >= 5) {
5570                         /* Configure switch ID */
5571                         ctxt.info.valid_sections |=
5572                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5573                         ctxt.info.switch_id =
5574                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5575                 }
5576
5577                 /* Configure port/vlan */
5578                 ctxt.info.valid_sections |=
5579                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5580                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5581                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5582                                                 hw->func_caps.enabled_tcmap);
5583                 if (ret != I40E_SUCCESS) {
5584                         PMD_DRV_LOG(ERR,
5585                                 "Failed to configure TC queue mapping");
5586                         goto fail_msix_alloc;
5587                 }
5588
5589                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5590                 ctxt.info.valid_sections |=
5591                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5592                 /**
5593                  * Since VSI is not created yet, only configure parameter,
5594                  * will add vsi below.
5595                  */
5596
5597                 i40e_config_qinq(hw, vsi);
5598         } else if (type == I40E_VSI_VMDQ2) {
5599                 memset(&ctxt, 0, sizeof(ctxt));
5600                 /*
5601                  * For other VSI, the uplink_seid equals to uplink VSI's
5602                  * uplink_seid since they share same VEB
5603                  */
5604                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5605                 ctxt.pf_num = hw->pf_id;
5606                 ctxt.vf_num = 0;
5607                 ctxt.uplink_seid = vsi->uplink_seid;
5608                 ctxt.connection_type = 0x1;
5609                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5610
5611                 ctxt.info.valid_sections |=
5612                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5613                 /* user_param carries flag to enable loop back */
5614                 if (user_param) {
5615                         ctxt.info.switch_id =
5616                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5617                         ctxt.info.switch_id |=
5618                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5619                 }
5620
5621                 /* Configure port/vlan */
5622                 ctxt.info.valid_sections |=
5623                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5624                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5625                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5626                                                 I40E_DEFAULT_TCMAP);
5627                 if (ret != I40E_SUCCESS) {
5628                         PMD_DRV_LOG(ERR,
5629                                 "Failed to configure TC queue mapping");
5630                         goto fail_msix_alloc;
5631                 }
5632                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5633                 ctxt.info.valid_sections |=
5634                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5635         } else if (type == I40E_VSI_FDIR) {
5636                 memset(&ctxt, 0, sizeof(ctxt));
5637                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5638                 ctxt.pf_num = hw->pf_id;
5639                 ctxt.vf_num = 0;
5640                 ctxt.uplink_seid = vsi->uplink_seid;
5641                 ctxt.connection_type = 0x1;     /* regular data port */
5642                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5643                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5644                                                 I40E_DEFAULT_TCMAP);
5645                 if (ret != I40E_SUCCESS) {
5646                         PMD_DRV_LOG(ERR,
5647                                 "Failed to configure TC queue mapping.");
5648                         goto fail_msix_alloc;
5649                 }
5650                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5651                 ctxt.info.valid_sections |=
5652                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5653         } else {
5654                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5655                 goto fail_msix_alloc;
5656         }
5657
5658         if (vsi->type != I40E_VSI_MAIN) {
5659                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5660                 if (ret != I40E_SUCCESS) {
5661                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5662                                     hw->aq.asq_last_status);
5663                         goto fail_msix_alloc;
5664                 }
5665                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5666                 vsi->info.valid_sections = 0;
5667                 vsi->seid = ctxt.seid;
5668                 vsi->vsi_id = ctxt.vsi_number;
5669                 vsi->sib_vsi_list.vsi = vsi;
5670                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5671                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5672                                           &vsi->sib_vsi_list, list);
5673                 } else {
5674                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5675                                           &vsi->sib_vsi_list, list);
5676                 }
5677         }
5678
5679         /* MAC/VLAN configuration */
5680         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5681         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5682
5683         ret = i40e_vsi_add_mac(vsi, &filter);
5684         if (ret != I40E_SUCCESS) {
5685                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5686                 goto fail_msix_alloc;
5687         }
5688
5689         /* Get VSI BW information */
5690         i40e_vsi_get_bw_config(vsi);
5691         return vsi;
5692 fail_msix_alloc:
5693         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5694 fail_queue_alloc:
5695         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5696 fail_mem:
5697         rte_free(vsi);
5698         return NULL;
5699 }
5700
5701 /* Configure vlan filter on or off */
5702 int
5703 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5704 {
5705         int i, num;
5706         struct i40e_mac_filter *f;
5707         void *temp;
5708         struct i40e_mac_filter_info *mac_filter;
5709         enum rte_mac_filter_type desired_filter;
5710         int ret = I40E_SUCCESS;
5711
5712         if (on) {
5713                 /* Filter to match MAC and VLAN */
5714                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5715         } else {
5716                 /* Filter to match only MAC */
5717                 desired_filter = RTE_MAC_PERFECT_MATCH;
5718         }
5719
5720         num = vsi->mac_num;
5721
5722         mac_filter = rte_zmalloc("mac_filter_info_data",
5723                                  num * sizeof(*mac_filter), 0);
5724         if (mac_filter == NULL) {
5725                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5726                 return I40E_ERR_NO_MEMORY;
5727         }
5728
5729         i = 0;
5730
5731         /* Remove all existing mac */
5732         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5733                 mac_filter[i] = f->mac_info;
5734                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5735                 if (ret) {
5736                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5737                                     on ? "enable" : "disable");
5738                         goto DONE;
5739                 }
5740                 i++;
5741         }
5742
5743         /* Override with new filter */
5744         for (i = 0; i < num; i++) {
5745                 mac_filter[i].filter_type = desired_filter;
5746                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5747                 if (ret) {
5748                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5749                                     on ? "enable" : "disable");
5750                         goto DONE;
5751                 }
5752         }
5753
5754 DONE:
5755         rte_free(mac_filter);
5756         return ret;
5757 }
5758
5759 /* Configure vlan stripping on or off */
5760 int
5761 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5762 {
5763         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5764         struct i40e_vsi_context ctxt;
5765         uint8_t vlan_flags;
5766         int ret = I40E_SUCCESS;
5767
5768         /* Check if it has been already on or off */
5769         if (vsi->info.valid_sections &
5770                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5771                 if (on) {
5772                         if ((vsi->info.port_vlan_flags &
5773                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5774                                 return 0; /* already on */
5775                 } else {
5776                         if ((vsi->info.port_vlan_flags &
5777                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5778                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5779                                 return 0; /* already off */
5780                 }
5781         }
5782
5783         if (on)
5784                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5785         else
5786                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5787         vsi->info.valid_sections =
5788                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5789         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5790         vsi->info.port_vlan_flags |= vlan_flags;
5791         ctxt.seid = vsi->seid;
5792         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5793         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5794         if (ret)
5795                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5796                             on ? "enable" : "disable");
5797
5798         return ret;
5799 }
5800
5801 static int
5802 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5803 {
5804         struct rte_eth_dev_data *data = dev->data;
5805         int ret;
5806         int mask = 0;
5807
5808         /* Apply vlan offload setting */
5809         mask = ETH_VLAN_STRIP_MASK |
5810                ETH_VLAN_FILTER_MASK |
5811                ETH_VLAN_EXTEND_MASK;
5812         ret = i40e_vlan_offload_set(dev, mask);
5813         if (ret) {
5814                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5815                 return ret;
5816         }
5817
5818         /* Apply pvid setting */
5819         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5820                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5821         if (ret)
5822                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5823
5824         return ret;
5825 }
5826
5827 static int
5828 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5829 {
5830         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5831
5832         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5833 }
5834
5835 static int
5836 i40e_update_flow_control(struct i40e_hw *hw)
5837 {
5838 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5839         struct i40e_link_status link_status;
5840         uint32_t rxfc = 0, txfc = 0, reg;
5841         uint8_t an_info;
5842         int ret;
5843
5844         memset(&link_status, 0, sizeof(link_status));
5845         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5846         if (ret != I40E_SUCCESS) {
5847                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5848                 goto write_reg; /* Disable flow control */
5849         }
5850
5851         an_info = hw->phy.link_info.an_info;
5852         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5853                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5854                 ret = I40E_ERR_NOT_READY;
5855                 goto write_reg; /* Disable flow control */
5856         }
5857         /**
5858          * If link auto negotiation is enabled, flow control needs to
5859          * be configured according to it
5860          */
5861         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5862         case I40E_LINK_PAUSE_RXTX:
5863                 rxfc = 1;
5864                 txfc = 1;
5865                 hw->fc.current_mode = I40E_FC_FULL;
5866                 break;
5867         case I40E_AQ_LINK_PAUSE_RX:
5868                 rxfc = 1;
5869                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5870                 break;
5871         case I40E_AQ_LINK_PAUSE_TX:
5872                 txfc = 1;
5873                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5874                 break;
5875         default:
5876                 hw->fc.current_mode = I40E_FC_NONE;
5877                 break;
5878         }
5879
5880 write_reg:
5881         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5882                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5883         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5884         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5885         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5886         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5887
5888         return ret;
5889 }
5890
5891 /* PF setup */
5892 static int
5893 i40e_pf_setup(struct i40e_pf *pf)
5894 {
5895         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5896         struct i40e_filter_control_settings settings;
5897         struct i40e_vsi *vsi;
5898         int ret;
5899
5900         /* Clear all stats counters */
5901         pf->offset_loaded = FALSE;
5902         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5903         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5904         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5905         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5906
5907         ret = i40e_pf_get_switch_config(pf);
5908         if (ret != I40E_SUCCESS) {
5909                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5910                 return ret;
5911         }
5912
5913         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
5914         if (ret)
5915                 PMD_INIT_LOG(WARNING,
5916                         "failed to allocate switch domain for device %d", ret);
5917
5918         if (pf->flags & I40E_FLAG_FDIR) {
5919                 /* make queue allocated first, let FDIR use queue pair 0*/
5920                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5921                 if (ret != I40E_FDIR_QUEUE_ID) {
5922                         PMD_DRV_LOG(ERR,
5923                                 "queue allocation fails for FDIR: ret =%d",
5924                                 ret);
5925                         pf->flags &= ~I40E_FLAG_FDIR;
5926                 }
5927         }
5928         /*  main VSI setup */
5929         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5930         if (!vsi) {
5931                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5932                 return I40E_ERR_NOT_READY;
5933         }
5934         pf->main_vsi = vsi;
5935
5936         /* Configure filter control */
5937         memset(&settings, 0, sizeof(settings));
5938         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5939                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5940         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5941                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5942         else {
5943                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5944                         hw->func_caps.rss_table_size);
5945                 return I40E_ERR_PARAM;
5946         }
5947         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5948                 hw->func_caps.rss_table_size);
5949         pf->hash_lut_size = hw->func_caps.rss_table_size;
5950
5951         /* Enable ethtype and macvlan filters */
5952         settings.enable_ethtype = TRUE;
5953         settings.enable_macvlan = TRUE;
5954         ret = i40e_set_filter_control(hw, &settings);
5955         if (ret)
5956                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5957                                                                 ret);
5958
5959         /* Update flow control according to the auto negotiation */
5960         i40e_update_flow_control(hw);
5961
5962         return I40E_SUCCESS;
5963 }
5964
5965 int
5966 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5967 {
5968         uint32_t reg;
5969         uint16_t j;
5970
5971         /**
5972          * Set or clear TX Queue Disable flags,
5973          * which is required by hardware.
5974          */
5975         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5976         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5977
5978         /* Wait until the request is finished */
5979         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5980                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5981                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5982                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5983                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5984                                                         & 0x1))) {
5985                         break;
5986                 }
5987         }
5988         if (on) {
5989                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5990                         return I40E_SUCCESS; /* already on, skip next steps */
5991
5992                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5993                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5994         } else {
5995                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5996                         return I40E_SUCCESS; /* already off, skip next steps */
5997                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5998         }
5999         /* Write the register */
6000         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6001         /* Check the result */
6002         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6003                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6004                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6005                 if (on) {
6006                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6007                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6008                                 break;
6009                 } else {
6010                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6011                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6012                                 break;
6013                 }
6014         }
6015         /* Check if it is timeout */
6016         if (j >= I40E_CHK_Q_ENA_COUNT) {
6017                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6018                             (on ? "enable" : "disable"), q_idx);
6019                 return I40E_ERR_TIMEOUT;
6020         }
6021
6022         return I40E_SUCCESS;
6023 }
6024
6025 /* Swith on or off the tx queues */
6026 static int
6027 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6028 {
6029         struct rte_eth_dev_data *dev_data = pf->dev_data;
6030         struct i40e_tx_queue *txq;
6031         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6032         uint16_t i;
6033         int ret;
6034
6035         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6036                 txq = dev_data->tx_queues[i];
6037                 /* Don't operate the queue if not configured or
6038                  * if starting only per queue */
6039                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6040                         continue;
6041                 if (on)
6042                         ret = i40e_dev_tx_queue_start(dev, i);
6043                 else
6044                         ret = i40e_dev_tx_queue_stop(dev, i);
6045                 if ( ret != I40E_SUCCESS)
6046                         return ret;
6047         }
6048
6049         return I40E_SUCCESS;
6050 }
6051
6052 int
6053 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6054 {
6055         uint32_t reg;
6056         uint16_t j;
6057
6058         /* Wait until the request is finished */
6059         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6060                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6061                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6062                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6063                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6064                         break;
6065         }
6066
6067         if (on) {
6068                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6069                         return I40E_SUCCESS; /* Already on, skip next steps */
6070                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6071         } else {
6072                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6073                         return I40E_SUCCESS; /* Already off, skip next steps */
6074                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6075         }
6076
6077         /* Write the register */
6078         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6079         /* Check the result */
6080         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6081                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6082                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6083                 if (on) {
6084                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6085                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6086                                 break;
6087                 } else {
6088                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6089                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6090                                 break;
6091                 }
6092         }
6093
6094         /* Check if it is timeout */
6095         if (j >= I40E_CHK_Q_ENA_COUNT) {
6096                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6097                             (on ? "enable" : "disable"), q_idx);
6098                 return I40E_ERR_TIMEOUT;
6099         }
6100
6101         return I40E_SUCCESS;
6102 }
6103 /* Switch on or off the rx queues */
6104 static int
6105 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6106 {
6107         struct rte_eth_dev_data *dev_data = pf->dev_data;
6108         struct i40e_rx_queue *rxq;
6109         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6110         uint16_t i;
6111         int ret;
6112
6113         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6114                 rxq = dev_data->rx_queues[i];
6115                 /* Don't operate the queue if not configured or
6116                  * if starting only per queue */
6117                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6118                         continue;
6119                 if (on)
6120                         ret = i40e_dev_rx_queue_start(dev, i);
6121                 else
6122                         ret = i40e_dev_rx_queue_stop(dev, i);
6123                 if (ret != I40E_SUCCESS)
6124                         return ret;
6125         }
6126
6127         return I40E_SUCCESS;
6128 }
6129
6130 /* Switch on or off all the rx/tx queues */
6131 int
6132 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6133 {
6134         int ret;
6135
6136         if (on) {
6137                 /* enable rx queues before enabling tx queues */
6138                 ret = i40e_dev_switch_rx_queues(pf, on);
6139                 if (ret) {
6140                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6141                         return ret;
6142                 }
6143                 ret = i40e_dev_switch_tx_queues(pf, on);
6144         } else {
6145                 /* Stop tx queues before stopping rx queues */
6146                 ret = i40e_dev_switch_tx_queues(pf, on);
6147                 if (ret) {
6148                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6149                         return ret;
6150                 }
6151                 ret = i40e_dev_switch_rx_queues(pf, on);
6152         }
6153
6154         return ret;
6155 }
6156
6157 /* Initialize VSI for TX */
6158 static int
6159 i40e_dev_tx_init(struct i40e_pf *pf)
6160 {
6161         struct rte_eth_dev_data *data = pf->dev_data;
6162         uint16_t i;
6163         uint32_t ret = I40E_SUCCESS;
6164         struct i40e_tx_queue *txq;
6165
6166         for (i = 0; i < data->nb_tx_queues; i++) {
6167                 txq = data->tx_queues[i];
6168                 if (!txq || !txq->q_set)
6169                         continue;
6170                 ret = i40e_tx_queue_init(txq);
6171                 if (ret != I40E_SUCCESS)
6172                         break;
6173         }
6174         if (ret == I40E_SUCCESS)
6175                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6176                                      ->eth_dev);
6177
6178         return ret;
6179 }
6180
6181 /* Initialize VSI for RX */
6182 static int
6183 i40e_dev_rx_init(struct i40e_pf *pf)
6184 {
6185         struct rte_eth_dev_data *data = pf->dev_data;
6186         int ret = I40E_SUCCESS;
6187         uint16_t i;
6188         struct i40e_rx_queue *rxq;
6189
6190         i40e_pf_config_mq_rx(pf);
6191         for (i = 0; i < data->nb_rx_queues; i++) {
6192                 rxq = data->rx_queues[i];
6193                 if (!rxq || !rxq->q_set)
6194                         continue;
6195
6196                 ret = i40e_rx_queue_init(rxq);
6197                 if (ret != I40E_SUCCESS) {
6198                         PMD_DRV_LOG(ERR,
6199                                 "Failed to do RX queue initialization");
6200                         break;
6201                 }
6202         }
6203         if (ret == I40E_SUCCESS)
6204                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6205                                      ->eth_dev);
6206
6207         return ret;
6208 }
6209
6210 static int
6211 i40e_dev_rxtx_init(struct i40e_pf *pf)
6212 {
6213         int err;
6214
6215         err = i40e_dev_tx_init(pf);
6216         if (err) {
6217                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6218                 return err;
6219         }
6220         err = i40e_dev_rx_init(pf);
6221         if (err) {
6222                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6223                 return err;
6224         }
6225
6226         return err;
6227 }
6228
6229 static int
6230 i40e_vmdq_setup(struct rte_eth_dev *dev)
6231 {
6232         struct rte_eth_conf *conf = &dev->data->dev_conf;
6233         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6234         int i, err, conf_vsis, j, loop;
6235         struct i40e_vsi *vsi;
6236         struct i40e_vmdq_info *vmdq_info;
6237         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6238         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6239
6240         /*
6241          * Disable interrupt to avoid message from VF. Furthermore, it will
6242          * avoid race condition in VSI creation/destroy.
6243          */
6244         i40e_pf_disable_irq0(hw);
6245
6246         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6247                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6248                 return -ENOTSUP;
6249         }
6250
6251         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6252         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6253                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6254                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6255                         pf->max_nb_vmdq_vsi);
6256                 return -ENOTSUP;
6257         }
6258
6259         if (pf->vmdq != NULL) {
6260                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6261                 return 0;
6262         }
6263
6264         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6265                                 sizeof(*vmdq_info) * conf_vsis, 0);
6266
6267         if (pf->vmdq == NULL) {
6268                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6269                 return -ENOMEM;
6270         }
6271
6272         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6273
6274         /* Create VMDQ VSI */
6275         for (i = 0; i < conf_vsis; i++) {
6276                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6277                                 vmdq_conf->enable_loop_back);
6278                 if (vsi == NULL) {
6279                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6280                         err = -1;
6281                         goto err_vsi_setup;
6282                 }
6283                 vmdq_info = &pf->vmdq[i];
6284                 vmdq_info->pf = pf;
6285                 vmdq_info->vsi = vsi;
6286         }
6287         pf->nb_cfg_vmdq_vsi = conf_vsis;
6288
6289         /* Configure Vlan */
6290         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6291         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6292                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6293                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6294                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6295                                         vmdq_conf->pool_map[i].vlan_id, j);
6296
6297                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6298                                                 vmdq_conf->pool_map[i].vlan_id);
6299                                 if (err) {
6300                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6301                                         err = -1;
6302                                         goto err_vsi_setup;
6303                                 }
6304                         }
6305                 }
6306         }
6307
6308         i40e_pf_enable_irq0(hw);
6309
6310         return 0;
6311
6312 err_vsi_setup:
6313         for (i = 0; i < conf_vsis; i++)
6314                 if (pf->vmdq[i].vsi == NULL)
6315                         break;
6316                 else
6317                         i40e_vsi_release(pf->vmdq[i].vsi);
6318
6319         rte_free(pf->vmdq);
6320         pf->vmdq = NULL;
6321         i40e_pf_enable_irq0(hw);
6322         return err;
6323 }
6324
6325 static void
6326 i40e_stat_update_32(struct i40e_hw *hw,
6327                    uint32_t reg,
6328                    bool offset_loaded,
6329                    uint64_t *offset,
6330                    uint64_t *stat)
6331 {
6332         uint64_t new_data;
6333
6334         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6335         if (!offset_loaded)
6336                 *offset = new_data;
6337
6338         if (new_data >= *offset)
6339                 *stat = (uint64_t)(new_data - *offset);
6340         else
6341                 *stat = (uint64_t)((new_data +
6342                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6343 }
6344
6345 static void
6346 i40e_stat_update_48(struct i40e_hw *hw,
6347                    uint32_t hireg,
6348                    uint32_t loreg,
6349                    bool offset_loaded,
6350                    uint64_t *offset,
6351                    uint64_t *stat)
6352 {
6353         uint64_t new_data;
6354
6355         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6356         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6357                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6358
6359         if (!offset_loaded)
6360                 *offset = new_data;
6361
6362         if (new_data >= *offset)
6363                 *stat = new_data - *offset;
6364         else
6365                 *stat = (uint64_t)((new_data +
6366                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6367
6368         *stat &= I40E_48_BIT_MASK;
6369 }
6370
6371 /* Disable IRQ0 */
6372 void
6373 i40e_pf_disable_irq0(struct i40e_hw *hw)
6374 {
6375         /* Disable all interrupt types */
6376         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6377                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6378         I40E_WRITE_FLUSH(hw);
6379 }
6380
6381 /* Enable IRQ0 */
6382 void
6383 i40e_pf_enable_irq0(struct i40e_hw *hw)
6384 {
6385         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6386                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6387                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6388                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6389         I40E_WRITE_FLUSH(hw);
6390 }
6391
6392 static void
6393 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6394 {
6395         /* read pending request and disable first */
6396         i40e_pf_disable_irq0(hw);
6397         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6398         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6399                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6400
6401         if (no_queue)
6402                 /* Link no queues with irq0 */
6403                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6404                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6405 }
6406
6407 static void
6408 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6409 {
6410         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6411         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6412         int i;
6413         uint16_t abs_vf_id;
6414         uint32_t index, offset, val;
6415
6416         if (!pf->vfs)
6417                 return;
6418         /**
6419          * Try to find which VF trigger a reset, use absolute VF id to access
6420          * since the reg is global register.
6421          */
6422         for (i = 0; i < pf->vf_num; i++) {
6423                 abs_vf_id = hw->func_caps.vf_base_id + i;
6424                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6425                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6426                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6427                 /* VFR event occurred */
6428                 if (val & (0x1 << offset)) {
6429                         int ret;
6430
6431                         /* Clear the event first */
6432                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6433                                                         (0x1 << offset));
6434                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6435                         /**
6436                          * Only notify a VF reset event occurred,
6437                          * don't trigger another SW reset
6438                          */
6439                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6440                         if (ret != I40E_SUCCESS)
6441                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6442                 }
6443         }
6444 }
6445
6446 static void
6447 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6448 {
6449         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6450         int i;
6451
6452         for (i = 0; i < pf->vf_num; i++)
6453                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6454 }
6455
6456 static void
6457 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6458 {
6459         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6460         struct i40e_arq_event_info info;
6461         uint16_t pending, opcode;
6462         int ret;
6463
6464         info.buf_len = I40E_AQ_BUF_SZ;
6465         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6466         if (!info.msg_buf) {
6467                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6468                 return;
6469         }
6470
6471         pending = 1;
6472         while (pending) {
6473                 ret = i40e_clean_arq_element(hw, &info, &pending);
6474
6475                 if (ret != I40E_SUCCESS) {
6476                         PMD_DRV_LOG(INFO,
6477                                 "Failed to read msg from AdminQ, aq_err: %u",
6478                                 hw->aq.asq_last_status);
6479                         break;
6480                 }
6481                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6482
6483                 switch (opcode) {
6484                 case i40e_aqc_opc_send_msg_to_pf:
6485                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6486                         i40e_pf_host_handle_vf_msg(dev,
6487                                         rte_le_to_cpu_16(info.desc.retval),
6488                                         rte_le_to_cpu_32(info.desc.cookie_high),
6489                                         rte_le_to_cpu_32(info.desc.cookie_low),
6490                                         info.msg_buf,
6491                                         info.msg_len);
6492                         break;
6493                 case i40e_aqc_opc_get_link_status:
6494                         ret = i40e_dev_link_update(dev, 0);
6495                         if (!ret)
6496                                 _rte_eth_dev_callback_process(dev,
6497                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6498                         break;
6499                 default:
6500                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6501                                     opcode);
6502                         break;
6503                 }
6504         }
6505         rte_free(info.msg_buf);
6506 }
6507
6508 /**
6509  * Interrupt handler triggered by NIC  for handling
6510  * specific interrupt.
6511  *
6512  * @param handle
6513  *  Pointer to interrupt handle.
6514  * @param param
6515  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6516  *
6517  * @return
6518  *  void
6519  */
6520 static void
6521 i40e_dev_interrupt_handler(void *param)
6522 {
6523         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6524         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6525         uint32_t icr0;
6526
6527         /* Disable interrupt */
6528         i40e_pf_disable_irq0(hw);
6529
6530         /* read out interrupt causes */
6531         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6532
6533         /* No interrupt event indicated */
6534         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6535                 PMD_DRV_LOG(INFO, "No interrupt event");
6536                 goto done;
6537         }
6538         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6539                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6540         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6541                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6542         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6543                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6544         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6545                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6546         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6547                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6548         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6549                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6550         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6551                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6552
6553         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6554                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6555                 i40e_dev_handle_vfr_event(dev);
6556         }
6557         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6558                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6559                 i40e_dev_handle_aq_msg(dev);
6560         }
6561
6562 done:
6563         /* Enable interrupt */
6564         i40e_pf_enable_irq0(hw);
6565         rte_intr_enable(dev->intr_handle);
6566 }
6567
6568 static void
6569 i40e_dev_alarm_handler(void *param)
6570 {
6571         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6572         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6573         uint32_t icr0;
6574
6575         /* Disable interrupt */
6576         i40e_pf_disable_irq0(hw);
6577
6578         /* read out interrupt causes */
6579         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6580
6581         /* No interrupt event indicated */
6582         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6583                 PMD_DRV_LOG(INFO, "No interrupt event");
6584                 goto done;
6585         }
6586         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6587                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6588         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6589                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6590         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6591                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6592         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6593                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6594         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6595                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6596         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6597                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6598         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6599                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6600
6601         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6602                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6603                 i40e_dev_handle_vfr_event(dev);
6604         }
6605         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6606                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6607                 i40e_dev_handle_aq_msg(dev);
6608         }
6609
6610 done:
6611         /* Enable interrupt */
6612         i40e_pf_enable_irq0(hw);
6613         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6614                           i40e_dev_alarm_handler, dev);
6615 }
6616
6617 int
6618 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6619                          struct i40e_macvlan_filter *filter,
6620                          int total)
6621 {
6622         int ele_num, ele_buff_size;
6623         int num, actual_num, i;
6624         uint16_t flags;
6625         int ret = I40E_SUCCESS;
6626         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6627         struct i40e_aqc_add_macvlan_element_data *req_list;
6628
6629         if (filter == NULL  || total == 0)
6630                 return I40E_ERR_PARAM;
6631         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6632         ele_buff_size = hw->aq.asq_buf_size;
6633
6634         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6635         if (req_list == NULL) {
6636                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6637                 return I40E_ERR_NO_MEMORY;
6638         }
6639
6640         num = 0;
6641         do {
6642                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6643                 memset(req_list, 0, ele_buff_size);
6644
6645                 for (i = 0; i < actual_num; i++) {
6646                         rte_memcpy(req_list[i].mac_addr,
6647                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6648                         req_list[i].vlan_tag =
6649                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6650
6651                         switch (filter[num + i].filter_type) {
6652                         case RTE_MAC_PERFECT_MATCH:
6653                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6654                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6655                                 break;
6656                         case RTE_MACVLAN_PERFECT_MATCH:
6657                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6658                                 break;
6659                         case RTE_MAC_HASH_MATCH:
6660                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6661                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6662                                 break;
6663                         case RTE_MACVLAN_HASH_MATCH:
6664                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6665                                 break;
6666                         default:
6667                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6668                                 ret = I40E_ERR_PARAM;
6669                                 goto DONE;
6670                         }
6671
6672                         req_list[i].queue_number = 0;
6673
6674                         req_list[i].flags = rte_cpu_to_le_16(flags);
6675                 }
6676
6677                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6678                                                 actual_num, NULL);
6679                 if (ret != I40E_SUCCESS) {
6680                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6681                         goto DONE;
6682                 }
6683                 num += actual_num;
6684         } while (num < total);
6685
6686 DONE:
6687         rte_free(req_list);
6688         return ret;
6689 }
6690
6691 int
6692 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6693                             struct i40e_macvlan_filter *filter,
6694                             int total)
6695 {
6696         int ele_num, ele_buff_size;
6697         int num, actual_num, i;
6698         uint16_t flags;
6699         int ret = I40E_SUCCESS;
6700         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6701         struct i40e_aqc_remove_macvlan_element_data *req_list;
6702
6703         if (filter == NULL  || total == 0)
6704                 return I40E_ERR_PARAM;
6705
6706         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6707         ele_buff_size = hw->aq.asq_buf_size;
6708
6709         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6710         if (req_list == NULL) {
6711                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6712                 return I40E_ERR_NO_MEMORY;
6713         }
6714
6715         num = 0;
6716         do {
6717                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6718                 memset(req_list, 0, ele_buff_size);
6719
6720                 for (i = 0; i < actual_num; i++) {
6721                         rte_memcpy(req_list[i].mac_addr,
6722                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6723                         req_list[i].vlan_tag =
6724                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6725
6726                         switch (filter[num + i].filter_type) {
6727                         case RTE_MAC_PERFECT_MATCH:
6728                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6729                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6730                                 break;
6731                         case RTE_MACVLAN_PERFECT_MATCH:
6732                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6733                                 break;
6734                         case RTE_MAC_HASH_MATCH:
6735                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6736                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6737                                 break;
6738                         case RTE_MACVLAN_HASH_MATCH:
6739                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6740                                 break;
6741                         default:
6742                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6743                                 ret = I40E_ERR_PARAM;
6744                                 goto DONE;
6745                         }
6746                         req_list[i].flags = rte_cpu_to_le_16(flags);
6747                 }
6748
6749                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6750                                                 actual_num, NULL);
6751                 if (ret != I40E_SUCCESS) {
6752                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6753                         goto DONE;
6754                 }
6755                 num += actual_num;
6756         } while (num < total);
6757
6758 DONE:
6759         rte_free(req_list);
6760         return ret;
6761 }
6762
6763 /* Find out specific MAC filter */
6764 static struct i40e_mac_filter *
6765 i40e_find_mac_filter(struct i40e_vsi *vsi,
6766                          struct ether_addr *macaddr)
6767 {
6768         struct i40e_mac_filter *f;
6769
6770         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6771                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6772                         return f;
6773         }
6774
6775         return NULL;
6776 }
6777
6778 static bool
6779 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6780                          uint16_t vlan_id)
6781 {
6782         uint32_t vid_idx, vid_bit;
6783
6784         if (vlan_id > ETH_VLAN_ID_MAX)
6785                 return 0;
6786
6787         vid_idx = I40E_VFTA_IDX(vlan_id);
6788         vid_bit = I40E_VFTA_BIT(vlan_id);
6789
6790         if (vsi->vfta[vid_idx] & vid_bit)
6791                 return 1;
6792         else
6793                 return 0;
6794 }
6795
6796 static void
6797 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6798                        uint16_t vlan_id, bool on)
6799 {
6800         uint32_t vid_idx, vid_bit;
6801
6802         vid_idx = I40E_VFTA_IDX(vlan_id);
6803         vid_bit = I40E_VFTA_BIT(vlan_id);
6804
6805         if (on)
6806                 vsi->vfta[vid_idx] |= vid_bit;
6807         else
6808                 vsi->vfta[vid_idx] &= ~vid_bit;
6809 }
6810
6811 void
6812 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6813                      uint16_t vlan_id, bool on)
6814 {
6815         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6816         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6817         int ret;
6818
6819         if (vlan_id > ETH_VLAN_ID_MAX)
6820                 return;
6821
6822         i40e_store_vlan_filter(vsi, vlan_id, on);
6823
6824         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6825                 return;
6826
6827         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6828
6829         if (on) {
6830                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6831                                        &vlan_data, 1, NULL);
6832                 if (ret != I40E_SUCCESS)
6833                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6834         } else {
6835                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6836                                           &vlan_data, 1, NULL);
6837                 if (ret != I40E_SUCCESS)
6838                         PMD_DRV_LOG(ERR,
6839                                     "Failed to remove vlan filter");
6840         }
6841 }
6842
6843 /**
6844  * Find all vlan options for specific mac addr,
6845  * return with actual vlan found.
6846  */
6847 int
6848 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6849                            struct i40e_macvlan_filter *mv_f,
6850                            int num, struct ether_addr *addr)
6851 {
6852         int i;
6853         uint32_t j, k;
6854
6855         /**
6856          * Not to use i40e_find_vlan_filter to decrease the loop time,
6857          * although the code looks complex.
6858           */
6859         if (num < vsi->vlan_num)
6860                 return I40E_ERR_PARAM;
6861
6862         i = 0;
6863         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6864                 if (vsi->vfta[j]) {
6865                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6866                                 if (vsi->vfta[j] & (1 << k)) {
6867                                         if (i > num - 1) {
6868                                                 PMD_DRV_LOG(ERR,
6869                                                         "vlan number doesn't match");
6870                                                 return I40E_ERR_PARAM;
6871                                         }
6872                                         rte_memcpy(&mv_f[i].macaddr,
6873                                                         addr, ETH_ADDR_LEN);
6874                                         mv_f[i].vlan_id =
6875                                                 j * I40E_UINT32_BIT_SIZE + k;
6876                                         i++;
6877                                 }
6878                         }
6879                 }
6880         }
6881         return I40E_SUCCESS;
6882 }
6883
6884 static inline int
6885 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6886                            struct i40e_macvlan_filter *mv_f,
6887                            int num,
6888                            uint16_t vlan)
6889 {
6890         int i = 0;
6891         struct i40e_mac_filter *f;
6892
6893         if (num < vsi->mac_num)
6894                 return I40E_ERR_PARAM;
6895
6896         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6897                 if (i > num - 1) {
6898                         PMD_DRV_LOG(ERR, "buffer number not match");
6899                         return I40E_ERR_PARAM;
6900                 }
6901                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6902                                 ETH_ADDR_LEN);
6903                 mv_f[i].vlan_id = vlan;
6904                 mv_f[i].filter_type = f->mac_info.filter_type;
6905                 i++;
6906         }
6907
6908         return I40E_SUCCESS;
6909 }
6910
6911 static int
6912 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6913 {
6914         int i, j, num;
6915         struct i40e_mac_filter *f;
6916         struct i40e_macvlan_filter *mv_f;
6917         int ret = I40E_SUCCESS;
6918
6919         if (vsi == NULL || vsi->mac_num == 0)
6920                 return I40E_ERR_PARAM;
6921
6922         /* Case that no vlan is set */
6923         if (vsi->vlan_num == 0)
6924                 num = vsi->mac_num;
6925         else
6926                 num = vsi->mac_num * vsi->vlan_num;
6927
6928         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6929         if (mv_f == NULL) {
6930                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6931                 return I40E_ERR_NO_MEMORY;
6932         }
6933
6934         i = 0;
6935         if (vsi->vlan_num == 0) {
6936                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6937                         rte_memcpy(&mv_f[i].macaddr,
6938                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6939                         mv_f[i].filter_type = f->mac_info.filter_type;
6940                         mv_f[i].vlan_id = 0;
6941                         i++;
6942                 }
6943         } else {
6944                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6945                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6946                                         vsi->vlan_num, &f->mac_info.mac_addr);
6947                         if (ret != I40E_SUCCESS)
6948                                 goto DONE;
6949                         for (j = i; j < i + vsi->vlan_num; j++)
6950                                 mv_f[j].filter_type = f->mac_info.filter_type;
6951                         i += vsi->vlan_num;
6952                 }
6953         }
6954
6955         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6956 DONE:
6957         rte_free(mv_f);
6958
6959         return ret;
6960 }
6961
6962 int
6963 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6964 {
6965         struct i40e_macvlan_filter *mv_f;
6966         int mac_num;
6967         int ret = I40E_SUCCESS;
6968
6969         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6970                 return I40E_ERR_PARAM;
6971
6972         /* If it's already set, just return */
6973         if (i40e_find_vlan_filter(vsi,vlan))
6974                 return I40E_SUCCESS;
6975
6976         mac_num = vsi->mac_num;
6977
6978         if (mac_num == 0) {
6979                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6980                 return I40E_ERR_PARAM;
6981         }
6982
6983         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6984
6985         if (mv_f == NULL) {
6986                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6987                 return I40E_ERR_NO_MEMORY;
6988         }
6989
6990         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6991
6992         if (ret != I40E_SUCCESS)
6993                 goto DONE;
6994
6995         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6996
6997         if (ret != I40E_SUCCESS)
6998                 goto DONE;
6999
7000         i40e_set_vlan_filter(vsi, vlan, 1);
7001
7002         vsi->vlan_num++;
7003         ret = I40E_SUCCESS;
7004 DONE:
7005         rte_free(mv_f);
7006         return ret;
7007 }
7008
7009 int
7010 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7011 {
7012         struct i40e_macvlan_filter *mv_f;
7013         int mac_num;
7014         int ret = I40E_SUCCESS;
7015
7016         /**
7017          * Vlan 0 is the generic filter for untagged packets
7018          * and can't be removed.
7019          */
7020         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
7021                 return I40E_ERR_PARAM;
7022
7023         /* If can't find it, just return */
7024         if (!i40e_find_vlan_filter(vsi, vlan))
7025                 return I40E_ERR_PARAM;
7026
7027         mac_num = vsi->mac_num;
7028
7029         if (mac_num == 0) {
7030                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7031                 return I40E_ERR_PARAM;
7032         }
7033
7034         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7035
7036         if (mv_f == NULL) {
7037                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7038                 return I40E_ERR_NO_MEMORY;
7039         }
7040
7041         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7042
7043         if (ret != I40E_SUCCESS)
7044                 goto DONE;
7045
7046         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7047
7048         if (ret != I40E_SUCCESS)
7049                 goto DONE;
7050
7051         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7052         if (vsi->vlan_num == 1) {
7053                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7054                 if (ret != I40E_SUCCESS)
7055                         goto DONE;
7056
7057                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7058                 if (ret != I40E_SUCCESS)
7059                         goto DONE;
7060         }
7061
7062         i40e_set_vlan_filter(vsi, vlan, 0);
7063
7064         vsi->vlan_num--;
7065         ret = I40E_SUCCESS;
7066 DONE:
7067         rte_free(mv_f);
7068         return ret;
7069 }
7070
7071 int
7072 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7073 {
7074         struct i40e_mac_filter *f;
7075         struct i40e_macvlan_filter *mv_f;
7076         int i, vlan_num = 0;
7077         int ret = I40E_SUCCESS;
7078
7079         /* If it's add and we've config it, return */
7080         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7081         if (f != NULL)
7082                 return I40E_SUCCESS;
7083         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7084                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7085
7086                 /**
7087                  * If vlan_num is 0, that's the first time to add mac,
7088                  * set mask for vlan_id 0.
7089                  */
7090                 if (vsi->vlan_num == 0) {
7091                         i40e_set_vlan_filter(vsi, 0, 1);
7092                         vsi->vlan_num = 1;
7093                 }
7094                 vlan_num = vsi->vlan_num;
7095         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7096                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7097                 vlan_num = 1;
7098
7099         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7100         if (mv_f == NULL) {
7101                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7102                 return I40E_ERR_NO_MEMORY;
7103         }
7104
7105         for (i = 0; i < vlan_num; i++) {
7106                 mv_f[i].filter_type = mac_filter->filter_type;
7107                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7108                                 ETH_ADDR_LEN);
7109         }
7110
7111         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7112                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7113                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7114                                         &mac_filter->mac_addr);
7115                 if (ret != I40E_SUCCESS)
7116                         goto DONE;
7117         }
7118
7119         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7120         if (ret != I40E_SUCCESS)
7121                 goto DONE;
7122
7123         /* Add the mac addr into mac list */
7124         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7125         if (f == NULL) {
7126                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7127                 ret = I40E_ERR_NO_MEMORY;
7128                 goto DONE;
7129         }
7130         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7131                         ETH_ADDR_LEN);
7132         f->mac_info.filter_type = mac_filter->filter_type;
7133         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7134         vsi->mac_num++;
7135
7136         ret = I40E_SUCCESS;
7137 DONE:
7138         rte_free(mv_f);
7139
7140         return ret;
7141 }
7142
7143 int
7144 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7145 {
7146         struct i40e_mac_filter *f;
7147         struct i40e_macvlan_filter *mv_f;
7148         int i, vlan_num;
7149         enum rte_mac_filter_type filter_type;
7150         int ret = I40E_SUCCESS;
7151
7152         /* Can't find it, return an error */
7153         f = i40e_find_mac_filter(vsi, addr);
7154         if (f == NULL)
7155                 return I40E_ERR_PARAM;
7156
7157         vlan_num = vsi->vlan_num;
7158         filter_type = f->mac_info.filter_type;
7159         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7160                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7161                 if (vlan_num == 0) {
7162                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7163                         return I40E_ERR_PARAM;
7164                 }
7165         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7166                         filter_type == RTE_MAC_HASH_MATCH)
7167                 vlan_num = 1;
7168
7169         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7170         if (mv_f == NULL) {
7171                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7172                 return I40E_ERR_NO_MEMORY;
7173         }
7174
7175         for (i = 0; i < vlan_num; i++) {
7176                 mv_f[i].filter_type = filter_type;
7177                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7178                                 ETH_ADDR_LEN);
7179         }
7180         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7181                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7182                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7183                 if (ret != I40E_SUCCESS)
7184                         goto DONE;
7185         }
7186
7187         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7188         if (ret != I40E_SUCCESS)
7189                 goto DONE;
7190
7191         /* Remove the mac addr into mac list */
7192         TAILQ_REMOVE(&vsi->mac_list, f, next);
7193         rte_free(f);
7194         vsi->mac_num--;
7195
7196         ret = I40E_SUCCESS;
7197 DONE:
7198         rte_free(mv_f);
7199         return ret;
7200 }
7201
7202 /* Configure hash enable flags for RSS */
7203 uint64_t
7204 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7205 {
7206         uint64_t hena = 0;
7207         int i;
7208
7209         if (!flags)
7210                 return hena;
7211
7212         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7213                 if (flags & (1ULL << i))
7214                         hena |= adapter->pctypes_tbl[i];
7215         }
7216
7217         return hena;
7218 }
7219
7220 /* Parse the hash enable flags */
7221 uint64_t
7222 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7223 {
7224         uint64_t rss_hf = 0;
7225
7226         if (!flags)
7227                 return rss_hf;
7228         int i;
7229
7230         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7231                 if (flags & adapter->pctypes_tbl[i])
7232                         rss_hf |= (1ULL << i);
7233         }
7234         return rss_hf;
7235 }
7236
7237 /* Disable RSS */
7238 static void
7239 i40e_pf_disable_rss(struct i40e_pf *pf)
7240 {
7241         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7242
7243         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7244         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7245         I40E_WRITE_FLUSH(hw);
7246 }
7247
7248 int
7249 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7250 {
7251         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7252         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7253         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7254                            I40E_VFQF_HKEY_MAX_INDEX :
7255                            I40E_PFQF_HKEY_MAX_INDEX;
7256         int ret = 0;
7257
7258         if (!key || key_len == 0) {
7259                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7260                 return 0;
7261         } else if (key_len != (key_idx + 1) *
7262                 sizeof(uint32_t)) {
7263                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7264                 return -EINVAL;
7265         }
7266
7267         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7268                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7269                         (struct i40e_aqc_get_set_rss_key_data *)key;
7270
7271                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7272                 if (ret)
7273                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7274         } else {
7275                 uint32_t *hash_key = (uint32_t *)key;
7276                 uint16_t i;
7277
7278                 if (vsi->type == I40E_VSI_SRIOV) {
7279                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7280                                 I40E_WRITE_REG(
7281                                         hw,
7282                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7283                                         hash_key[i]);
7284
7285                 } else {
7286                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7287                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7288                                                hash_key[i]);
7289                 }
7290                 I40E_WRITE_FLUSH(hw);
7291         }
7292
7293         return ret;
7294 }
7295
7296 static int
7297 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7298 {
7299         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7300         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7301         uint32_t reg;
7302         int ret;
7303
7304         if (!key || !key_len)
7305                 return -EINVAL;
7306
7307         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7308                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7309                         (struct i40e_aqc_get_set_rss_key_data *)key);
7310                 if (ret) {
7311                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7312                         return ret;
7313                 }
7314         } else {
7315                 uint32_t *key_dw = (uint32_t *)key;
7316                 uint16_t i;
7317
7318                 if (vsi->type == I40E_VSI_SRIOV) {
7319                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7320                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7321                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7322                         }
7323                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7324                                    sizeof(uint32_t);
7325                 } else {
7326                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7327                                 reg = I40E_PFQF_HKEY(i);
7328                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7329                         }
7330                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7331                                    sizeof(uint32_t);
7332                 }
7333         }
7334         return 0;
7335 }
7336
7337 static int
7338 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7339 {
7340         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7341         uint64_t hena;
7342         int ret;
7343
7344         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7345                                rss_conf->rss_key_len);
7346         if (ret)
7347                 return ret;
7348
7349         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7350         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7351         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7352         I40E_WRITE_FLUSH(hw);
7353
7354         return 0;
7355 }
7356
7357 static int
7358 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7359                          struct rte_eth_rss_conf *rss_conf)
7360 {
7361         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7362         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7363         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7364         uint64_t hena;
7365
7366         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7367         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7368
7369         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7370                 if (rss_hf != 0) /* Enable RSS */
7371                         return -EINVAL;
7372                 return 0; /* Nothing to do */
7373         }
7374         /* RSS enabled */
7375         if (rss_hf == 0) /* Disable RSS */
7376                 return -EINVAL;
7377
7378         return i40e_hw_rss_hash_set(pf, rss_conf);
7379 }
7380
7381 static int
7382 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7383                            struct rte_eth_rss_conf *rss_conf)
7384 {
7385         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7386         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7387         uint64_t hena;
7388
7389         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7390                          &rss_conf->rss_key_len);
7391
7392         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7393         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7394         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7395
7396         return 0;
7397 }
7398
7399 static int
7400 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7401 {
7402         switch (filter_type) {
7403         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7404                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7405                 break;
7406         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7407                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7408                 break;
7409         case RTE_TUNNEL_FILTER_IMAC_TENID:
7410                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7411                 break;
7412         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7413                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7414                 break;
7415         case ETH_TUNNEL_FILTER_IMAC:
7416                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7417                 break;
7418         case ETH_TUNNEL_FILTER_OIP:
7419                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7420                 break;
7421         case ETH_TUNNEL_FILTER_IIP:
7422                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7423                 break;
7424         default:
7425                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7426                 return -EINVAL;
7427         }
7428
7429         return 0;
7430 }
7431
7432 /* Convert tunnel filter structure */
7433 static int
7434 i40e_tunnel_filter_convert(
7435         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7436         struct i40e_tunnel_filter *tunnel_filter)
7437 {
7438         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7439                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7440         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7441                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7442         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7443         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7444              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7445             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7446                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7447         else
7448                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7449         tunnel_filter->input.flags = cld_filter->element.flags;
7450         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7451         tunnel_filter->queue = cld_filter->element.queue_number;
7452         rte_memcpy(tunnel_filter->input.general_fields,
7453                    cld_filter->general_fields,
7454                    sizeof(cld_filter->general_fields));
7455
7456         return 0;
7457 }
7458
7459 /* Check if there exists the tunnel filter */
7460 struct i40e_tunnel_filter *
7461 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7462                              const struct i40e_tunnel_filter_input *input)
7463 {
7464         int ret;
7465
7466         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7467         if (ret < 0)
7468                 return NULL;
7469
7470         return tunnel_rule->hash_map[ret];
7471 }
7472
7473 /* Add a tunnel filter into the SW list */
7474 static int
7475 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7476                              struct i40e_tunnel_filter *tunnel_filter)
7477 {
7478         struct i40e_tunnel_rule *rule = &pf->tunnel;
7479         int ret;
7480
7481         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7482         if (ret < 0) {
7483                 PMD_DRV_LOG(ERR,
7484                             "Failed to insert tunnel filter to hash table %d!",
7485                             ret);
7486                 return ret;
7487         }
7488         rule->hash_map[ret] = tunnel_filter;
7489
7490         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7491
7492         return 0;
7493 }
7494
7495 /* Delete a tunnel filter from the SW list */
7496 int
7497 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7498                           struct i40e_tunnel_filter_input *input)
7499 {
7500         struct i40e_tunnel_rule *rule = &pf->tunnel;
7501         struct i40e_tunnel_filter *tunnel_filter;
7502         int ret;
7503
7504         ret = rte_hash_del_key(rule->hash_table, input);
7505         if (ret < 0) {
7506                 PMD_DRV_LOG(ERR,
7507                             "Failed to delete tunnel filter to hash table %d!",
7508                             ret);
7509                 return ret;
7510         }
7511         tunnel_filter = rule->hash_map[ret];
7512         rule->hash_map[ret] = NULL;
7513
7514         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7515         rte_free(tunnel_filter);
7516
7517         return 0;
7518 }
7519
7520 int
7521 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7522                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7523                         uint8_t add)
7524 {
7525         uint16_t ip_type;
7526         uint32_t ipv4_addr, ipv4_addr_le;
7527         uint8_t i, tun_type = 0;
7528         /* internal varialbe to convert ipv6 byte order */
7529         uint32_t convert_ipv6[4];
7530         int val, ret = 0;
7531         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7532         struct i40e_vsi *vsi = pf->main_vsi;
7533         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7534         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7535         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7536         struct i40e_tunnel_filter *tunnel, *node;
7537         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7538
7539         cld_filter = rte_zmalloc("tunnel_filter",
7540                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7541         0);
7542
7543         if (NULL == cld_filter) {
7544                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7545                 return -ENOMEM;
7546         }
7547         pfilter = cld_filter;
7548
7549         ether_addr_copy(&tunnel_filter->outer_mac,
7550                         (struct ether_addr *)&pfilter->element.outer_mac);
7551         ether_addr_copy(&tunnel_filter->inner_mac,
7552                         (struct ether_addr *)&pfilter->element.inner_mac);
7553
7554         pfilter->element.inner_vlan =
7555                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7556         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7557                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7558                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7559                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7560                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7561                                 &ipv4_addr_le,
7562                                 sizeof(pfilter->element.ipaddr.v4.data));
7563         } else {
7564                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7565                 for (i = 0; i < 4; i++) {
7566                         convert_ipv6[i] =
7567                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7568                 }
7569                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7570                            &convert_ipv6,
7571                            sizeof(pfilter->element.ipaddr.v6.data));
7572         }
7573
7574         /* check tunneled type */
7575         switch (tunnel_filter->tunnel_type) {
7576         case RTE_TUNNEL_TYPE_VXLAN:
7577                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7578                 break;
7579         case RTE_TUNNEL_TYPE_NVGRE:
7580                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7581                 break;
7582         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7583                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7584                 break;
7585         default:
7586                 /* Other tunnel types is not supported. */
7587                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7588                 rte_free(cld_filter);
7589                 return -EINVAL;
7590         }
7591
7592         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7593                                        &pfilter->element.flags);
7594         if (val < 0) {
7595                 rte_free(cld_filter);
7596                 return -EINVAL;
7597         }
7598
7599         pfilter->element.flags |= rte_cpu_to_le_16(
7600                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7601                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7602         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7603         pfilter->element.queue_number =
7604                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7605
7606         /* Check if there is the filter in SW list */
7607         memset(&check_filter, 0, sizeof(check_filter));
7608         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7609         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7610         if (add && node) {
7611                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7612                 rte_free(cld_filter);
7613                 return -EINVAL;
7614         }
7615
7616         if (!add && !node) {
7617                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7618                 rte_free(cld_filter);
7619                 return -EINVAL;
7620         }
7621
7622         if (add) {
7623                 ret = i40e_aq_add_cloud_filters(hw,
7624                                         vsi->seid, &cld_filter->element, 1);
7625                 if (ret < 0) {
7626                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7627                         rte_free(cld_filter);
7628                         return -ENOTSUP;
7629                 }
7630                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7631                 if (tunnel == NULL) {
7632                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7633                         rte_free(cld_filter);
7634                         return -ENOMEM;
7635                 }
7636
7637                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7638                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7639                 if (ret < 0)
7640                         rte_free(tunnel);
7641         } else {
7642                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7643                                                    &cld_filter->element, 1);
7644                 if (ret < 0) {
7645                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7646                         rte_free(cld_filter);
7647                         return -ENOTSUP;
7648                 }
7649                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7650         }
7651
7652         rte_free(cld_filter);
7653         return ret;
7654 }
7655
7656 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7657 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7658 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7659 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7660 #define I40E_TR_GRE_KEY_MASK                    0x400
7661 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7662 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7663
7664 static enum
7665 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7666 {
7667         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7668         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7669         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7670         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7671         enum i40e_status_code status = I40E_SUCCESS;
7672
7673         if (pf->support_multi_driver) {
7674                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7675                 return I40E_NOT_SUPPORTED;
7676         }
7677
7678         memset(&filter_replace, 0,
7679                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7680         memset(&filter_replace_buf, 0,
7681                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7682
7683         /* create L1 filter */
7684         filter_replace.old_filter_type =
7685                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7686         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7687         filter_replace.tr_bit = 0;
7688
7689         /* Prepare the buffer, 3 entries */
7690         filter_replace_buf.data[0] =
7691                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7692         filter_replace_buf.data[0] |=
7693                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7694         filter_replace_buf.data[2] = 0xFF;
7695         filter_replace_buf.data[3] = 0xFF;
7696         filter_replace_buf.data[4] =
7697                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7698         filter_replace_buf.data[4] |=
7699                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7700         filter_replace_buf.data[7] = 0xF0;
7701         filter_replace_buf.data[8]
7702                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7703         filter_replace_buf.data[8] |=
7704                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7705         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7706                 I40E_TR_GENEVE_KEY_MASK |
7707                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7708         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7709                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7710                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7711
7712         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7713                                                &filter_replace_buf);
7714         if (!status && (filter_replace.old_filter_type !=
7715                         filter_replace.new_filter_type))
7716                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7717                             " original: 0x%x, new: 0x%x",
7718                             dev->device->name,
7719                             filter_replace.old_filter_type,
7720                             filter_replace.new_filter_type);
7721
7722         return status;
7723 }
7724
7725 static enum
7726 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7727 {
7728         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7729         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7730         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7731         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7732         enum i40e_status_code status = I40E_SUCCESS;
7733
7734         if (pf->support_multi_driver) {
7735                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7736                 return I40E_NOT_SUPPORTED;
7737         }
7738
7739         /* For MPLSoUDP */
7740         memset(&filter_replace, 0,
7741                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7742         memset(&filter_replace_buf, 0,
7743                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7744         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7745                 I40E_AQC_MIRROR_CLOUD_FILTER;
7746         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7747         filter_replace.new_filter_type =
7748                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7749         /* Prepare the buffer, 2 entries */
7750         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7751         filter_replace_buf.data[0] |=
7752                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7753         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7754         filter_replace_buf.data[4] |=
7755                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7756         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7757                                                &filter_replace_buf);
7758         if (status < 0)
7759                 return status;
7760         if (filter_replace.old_filter_type !=
7761             filter_replace.new_filter_type)
7762                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7763                             " original: 0x%x, new: 0x%x",
7764                             dev->device->name,
7765                             filter_replace.old_filter_type,
7766                             filter_replace.new_filter_type);
7767
7768         /* For MPLSoGRE */
7769         memset(&filter_replace, 0,
7770                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7771         memset(&filter_replace_buf, 0,
7772                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7773
7774         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7775                 I40E_AQC_MIRROR_CLOUD_FILTER;
7776         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7777         filter_replace.new_filter_type =
7778                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7779         /* Prepare the buffer, 2 entries */
7780         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7781         filter_replace_buf.data[0] |=
7782                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7783         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7784         filter_replace_buf.data[4] |=
7785                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7786
7787         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7788                                                &filter_replace_buf);
7789         if (!status && (filter_replace.old_filter_type !=
7790                         filter_replace.new_filter_type))
7791                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7792                             " original: 0x%x, new: 0x%x",
7793                             dev->device->name,
7794                             filter_replace.old_filter_type,
7795                             filter_replace.new_filter_type);
7796
7797         return status;
7798 }
7799
7800 static enum i40e_status_code
7801 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7802 {
7803         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7804         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7805         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7806         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7807         enum i40e_status_code status = I40E_SUCCESS;
7808
7809         if (pf->support_multi_driver) {
7810                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7811                 return I40E_NOT_SUPPORTED;
7812         }
7813
7814         /* For GTP-C */
7815         memset(&filter_replace, 0,
7816                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7817         memset(&filter_replace_buf, 0,
7818                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7819         /* create L1 filter */
7820         filter_replace.old_filter_type =
7821                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7822         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7823         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7824                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7825         /* Prepare the buffer, 2 entries */
7826         filter_replace_buf.data[0] =
7827                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7828         filter_replace_buf.data[0] |=
7829                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7830         filter_replace_buf.data[2] = 0xFF;
7831         filter_replace_buf.data[3] = 0xFF;
7832         filter_replace_buf.data[4] =
7833                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7834         filter_replace_buf.data[4] |=
7835                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7836         filter_replace_buf.data[6] = 0xFF;
7837         filter_replace_buf.data[7] = 0xFF;
7838         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7839                                                &filter_replace_buf);
7840         if (status < 0)
7841                 return status;
7842         if (filter_replace.old_filter_type !=
7843             filter_replace.new_filter_type)
7844                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7845                             " original: 0x%x, new: 0x%x",
7846                             dev->device->name,
7847                             filter_replace.old_filter_type,
7848                             filter_replace.new_filter_type);
7849
7850         /* for GTP-U */
7851         memset(&filter_replace, 0,
7852                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7853         memset(&filter_replace_buf, 0,
7854                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7855         /* create L1 filter */
7856         filter_replace.old_filter_type =
7857                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7858         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7859         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7860                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7861         /* Prepare the buffer, 2 entries */
7862         filter_replace_buf.data[0] =
7863                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7864         filter_replace_buf.data[0] |=
7865                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7866         filter_replace_buf.data[2] = 0xFF;
7867         filter_replace_buf.data[3] = 0xFF;
7868         filter_replace_buf.data[4] =
7869                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7870         filter_replace_buf.data[4] |=
7871                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7872         filter_replace_buf.data[6] = 0xFF;
7873         filter_replace_buf.data[7] = 0xFF;
7874
7875         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7876                                                &filter_replace_buf);
7877         if (!status && (filter_replace.old_filter_type !=
7878                         filter_replace.new_filter_type))
7879                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7880                             " original: 0x%x, new: 0x%x",
7881                             dev->device->name,
7882                             filter_replace.old_filter_type,
7883                             filter_replace.new_filter_type);
7884
7885         return status;
7886 }
7887
7888 static enum
7889 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7890 {
7891         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7892         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7893         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7894         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7895         enum i40e_status_code status = I40E_SUCCESS;
7896
7897         if (pf->support_multi_driver) {
7898                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7899                 return I40E_NOT_SUPPORTED;
7900         }
7901
7902         /* for GTP-C */
7903         memset(&filter_replace, 0,
7904                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7905         memset(&filter_replace_buf, 0,
7906                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7907         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7908         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7909         filter_replace.new_filter_type =
7910                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7911         /* Prepare the buffer, 2 entries */
7912         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7913         filter_replace_buf.data[0] |=
7914                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7915         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7916         filter_replace_buf.data[4] |=
7917                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7918         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7919                                                &filter_replace_buf);
7920         if (status < 0)
7921                 return status;
7922         if (filter_replace.old_filter_type !=
7923             filter_replace.new_filter_type)
7924                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7925                             " original: 0x%x, new: 0x%x",
7926                             dev->device->name,
7927                             filter_replace.old_filter_type,
7928                             filter_replace.new_filter_type);
7929
7930         /* for GTP-U */
7931         memset(&filter_replace, 0,
7932                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7933         memset(&filter_replace_buf, 0,
7934                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7935         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7936         filter_replace.old_filter_type =
7937                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7938         filter_replace.new_filter_type =
7939                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7940         /* Prepare the buffer, 2 entries */
7941         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7942         filter_replace_buf.data[0] |=
7943                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7944         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7945         filter_replace_buf.data[4] |=
7946                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7947
7948         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7949                                                &filter_replace_buf);
7950         if (!status && (filter_replace.old_filter_type !=
7951                         filter_replace.new_filter_type))
7952                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7953                             " original: 0x%x, new: 0x%x",
7954                             dev->device->name,
7955                             filter_replace.old_filter_type,
7956                             filter_replace.new_filter_type);
7957
7958         return status;
7959 }
7960
7961 int
7962 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7963                       struct i40e_tunnel_filter_conf *tunnel_filter,
7964                       uint8_t add)
7965 {
7966         uint16_t ip_type;
7967         uint32_t ipv4_addr, ipv4_addr_le;
7968         uint8_t i, tun_type = 0;
7969         /* internal variable to convert ipv6 byte order */
7970         uint32_t convert_ipv6[4];
7971         int val, ret = 0;
7972         struct i40e_pf_vf *vf = NULL;
7973         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7974         struct i40e_vsi *vsi;
7975         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7976         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7977         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7978         struct i40e_tunnel_filter *tunnel, *node;
7979         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7980         uint32_t teid_le;
7981         bool big_buffer = 0;
7982
7983         cld_filter = rte_zmalloc("tunnel_filter",
7984                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7985                          0);
7986
7987         if (cld_filter == NULL) {
7988                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7989                 return -ENOMEM;
7990         }
7991         pfilter = cld_filter;
7992
7993         ether_addr_copy(&tunnel_filter->outer_mac,
7994                         (struct ether_addr *)&pfilter->element.outer_mac);
7995         ether_addr_copy(&tunnel_filter->inner_mac,
7996                         (struct ether_addr *)&pfilter->element.inner_mac);
7997
7998         pfilter->element.inner_vlan =
7999                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8000         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8001                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8002                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8003                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8004                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8005                                 &ipv4_addr_le,
8006                                 sizeof(pfilter->element.ipaddr.v4.data));
8007         } else {
8008                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8009                 for (i = 0; i < 4; i++) {
8010                         convert_ipv6[i] =
8011                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8012                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8013                 }
8014                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8015                            &convert_ipv6,
8016                            sizeof(pfilter->element.ipaddr.v6.data));
8017         }
8018
8019         /* check tunneled type */
8020         switch (tunnel_filter->tunnel_type) {
8021         case I40E_TUNNEL_TYPE_VXLAN:
8022                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8023                 break;
8024         case I40E_TUNNEL_TYPE_NVGRE:
8025                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8026                 break;
8027         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8028                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8029                 break;
8030         case I40E_TUNNEL_TYPE_MPLSoUDP:
8031                 if (!pf->mpls_replace_flag) {
8032                         i40e_replace_mpls_l1_filter(pf);
8033                         i40e_replace_mpls_cloud_filter(pf);
8034                         pf->mpls_replace_flag = 1;
8035                 }
8036                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8037                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8038                         teid_le >> 4;
8039                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8040                         (teid_le & 0xF) << 12;
8041                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8042                         0x40;
8043                 big_buffer = 1;
8044                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8045                 break;
8046         case I40E_TUNNEL_TYPE_MPLSoGRE:
8047                 if (!pf->mpls_replace_flag) {
8048                         i40e_replace_mpls_l1_filter(pf);
8049                         i40e_replace_mpls_cloud_filter(pf);
8050                         pf->mpls_replace_flag = 1;
8051                 }
8052                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8053                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8054                         teid_le >> 4;
8055                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8056                         (teid_le & 0xF) << 12;
8057                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8058                         0x0;
8059                 big_buffer = 1;
8060                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8061                 break;
8062         case I40E_TUNNEL_TYPE_GTPC:
8063                 if (!pf->gtp_replace_flag) {
8064                         i40e_replace_gtp_l1_filter(pf);
8065                         i40e_replace_gtp_cloud_filter(pf);
8066                         pf->gtp_replace_flag = 1;
8067                 }
8068                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8069                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8070                         (teid_le >> 16) & 0xFFFF;
8071                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8072                         teid_le & 0xFFFF;
8073                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8074                         0x0;
8075                 big_buffer = 1;
8076                 break;
8077         case I40E_TUNNEL_TYPE_GTPU:
8078                 if (!pf->gtp_replace_flag) {
8079                         i40e_replace_gtp_l1_filter(pf);
8080                         i40e_replace_gtp_cloud_filter(pf);
8081                         pf->gtp_replace_flag = 1;
8082                 }
8083                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8084                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8085                         (teid_le >> 16) & 0xFFFF;
8086                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8087                         teid_le & 0xFFFF;
8088                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8089                         0x0;
8090                 big_buffer = 1;
8091                 break;
8092         case I40E_TUNNEL_TYPE_QINQ:
8093                 if (!pf->qinq_replace_flag) {
8094                         ret = i40e_cloud_filter_qinq_create(pf);
8095                         if (ret < 0)
8096                                 PMD_DRV_LOG(DEBUG,
8097                                             "QinQ tunnel filter already created.");
8098                         pf->qinq_replace_flag = 1;
8099                 }
8100                 /*      Add in the General fields the values of
8101                  *      the Outer and Inner VLAN
8102                  *      Big Buffer should be set, see changes in
8103                  *      i40e_aq_add_cloud_filters
8104                  */
8105                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8106                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8107                 big_buffer = 1;
8108                 break;
8109         default:
8110                 /* Other tunnel types is not supported. */
8111                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8112                 rte_free(cld_filter);
8113                 return -EINVAL;
8114         }
8115
8116         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8117                 pfilter->element.flags =
8118                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8119         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8120                 pfilter->element.flags =
8121                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8122         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8123                 pfilter->element.flags =
8124                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8125         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8126                 pfilter->element.flags =
8127                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8128         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8129                 pfilter->element.flags |=
8130                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8131         else {
8132                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8133                                                 &pfilter->element.flags);
8134                 if (val < 0) {
8135                         rte_free(cld_filter);
8136                         return -EINVAL;
8137                 }
8138         }
8139
8140         pfilter->element.flags |= rte_cpu_to_le_16(
8141                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8142                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8143         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8144         pfilter->element.queue_number =
8145                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8146
8147         if (!tunnel_filter->is_to_vf)
8148                 vsi = pf->main_vsi;
8149         else {
8150                 if (tunnel_filter->vf_id >= pf->vf_num) {
8151                         PMD_DRV_LOG(ERR, "Invalid argument.");
8152                         rte_free(cld_filter);
8153                         return -EINVAL;
8154                 }
8155                 vf = &pf->vfs[tunnel_filter->vf_id];
8156                 vsi = vf->vsi;
8157         }
8158
8159         /* Check if there is the filter in SW list */
8160         memset(&check_filter, 0, sizeof(check_filter));
8161         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8162         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8163         check_filter.vf_id = tunnel_filter->vf_id;
8164         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8165         if (add && node) {
8166                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8167                 rte_free(cld_filter);
8168                 return -EINVAL;
8169         }
8170
8171         if (!add && !node) {
8172                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8173                 rte_free(cld_filter);
8174                 return -EINVAL;
8175         }
8176
8177         if (add) {
8178                 if (big_buffer)
8179                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
8180                                                    vsi->seid, cld_filter, 1);
8181                 else
8182                         ret = i40e_aq_add_cloud_filters(hw,
8183                                         vsi->seid, &cld_filter->element, 1);
8184                 if (ret < 0) {
8185                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8186                         rte_free(cld_filter);
8187                         return -ENOTSUP;
8188                 }
8189                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8190                 if (tunnel == NULL) {
8191                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8192                         rte_free(cld_filter);
8193                         return -ENOMEM;
8194                 }
8195
8196                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8197                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8198                 if (ret < 0)
8199                         rte_free(tunnel);
8200         } else {
8201                 if (big_buffer)
8202                         ret = i40e_aq_remove_cloud_filters_big_buffer(
8203                                 hw, vsi->seid, cld_filter, 1);
8204                 else
8205                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
8206                                                    &cld_filter->element, 1);
8207                 if (ret < 0) {
8208                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8209                         rte_free(cld_filter);
8210                         return -ENOTSUP;
8211                 }
8212                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8213         }
8214
8215         rte_free(cld_filter);
8216         return ret;
8217 }
8218
8219 static int
8220 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8221 {
8222         uint8_t i;
8223
8224         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8225                 if (pf->vxlan_ports[i] == port)
8226                         return i;
8227         }
8228
8229         return -1;
8230 }
8231
8232 static int
8233 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8234 {
8235         int  idx, ret;
8236         uint8_t filter_idx;
8237         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8238
8239         idx = i40e_get_vxlan_port_idx(pf, port);
8240
8241         /* Check if port already exists */
8242         if (idx >= 0) {
8243                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8244                 return -EINVAL;
8245         }
8246
8247         /* Now check if there is space to add the new port */
8248         idx = i40e_get_vxlan_port_idx(pf, 0);
8249         if (idx < 0) {
8250                 PMD_DRV_LOG(ERR,
8251                         "Maximum number of UDP ports reached, not adding port %d",
8252                         port);
8253                 return -ENOSPC;
8254         }
8255
8256         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8257                                         &filter_idx, NULL);
8258         if (ret < 0) {
8259                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8260                 return -1;
8261         }
8262
8263         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8264                          port,  filter_idx);
8265
8266         /* New port: add it and mark its index in the bitmap */
8267         pf->vxlan_ports[idx] = port;
8268         pf->vxlan_bitmap |= (1 << idx);
8269
8270         if (!(pf->flags & I40E_FLAG_VXLAN))
8271                 pf->flags |= I40E_FLAG_VXLAN;
8272
8273         return 0;
8274 }
8275
8276 static int
8277 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8278 {
8279         int idx;
8280         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8281
8282         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8283                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8284                 return -EINVAL;
8285         }
8286
8287         idx = i40e_get_vxlan_port_idx(pf, port);
8288
8289         if (idx < 0) {
8290                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8291                 return -EINVAL;
8292         }
8293
8294         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8295                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8296                 return -1;
8297         }
8298
8299         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8300                         port, idx);
8301
8302         pf->vxlan_ports[idx] = 0;
8303         pf->vxlan_bitmap &= ~(1 << idx);
8304
8305         if (!pf->vxlan_bitmap)
8306                 pf->flags &= ~I40E_FLAG_VXLAN;
8307
8308         return 0;
8309 }
8310
8311 /* Add UDP tunneling port */
8312 static int
8313 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8314                              struct rte_eth_udp_tunnel *udp_tunnel)
8315 {
8316         int ret = 0;
8317         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8318
8319         if (udp_tunnel == NULL)
8320                 return -EINVAL;
8321
8322         switch (udp_tunnel->prot_type) {
8323         case RTE_TUNNEL_TYPE_VXLAN:
8324                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8325                 break;
8326
8327         case RTE_TUNNEL_TYPE_GENEVE:
8328         case RTE_TUNNEL_TYPE_TEREDO:
8329                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8330                 ret = -1;
8331                 break;
8332
8333         default:
8334                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8335                 ret = -1;
8336                 break;
8337         }
8338
8339         return ret;
8340 }
8341
8342 /* Remove UDP tunneling port */
8343 static int
8344 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8345                              struct rte_eth_udp_tunnel *udp_tunnel)
8346 {
8347         int ret = 0;
8348         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8349
8350         if (udp_tunnel == NULL)
8351                 return -EINVAL;
8352
8353         switch (udp_tunnel->prot_type) {
8354         case RTE_TUNNEL_TYPE_VXLAN:
8355                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8356                 break;
8357         case RTE_TUNNEL_TYPE_GENEVE:
8358         case RTE_TUNNEL_TYPE_TEREDO:
8359                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8360                 ret = -1;
8361                 break;
8362         default:
8363                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8364                 ret = -1;
8365                 break;
8366         }
8367
8368         return ret;
8369 }
8370
8371 /* Calculate the maximum number of contiguous PF queues that are configured */
8372 static int
8373 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8374 {
8375         struct rte_eth_dev_data *data = pf->dev_data;
8376         int i, num;
8377         struct i40e_rx_queue *rxq;
8378
8379         num = 0;
8380         for (i = 0; i < pf->lan_nb_qps; i++) {
8381                 rxq = data->rx_queues[i];
8382                 if (rxq && rxq->q_set)
8383                         num++;
8384                 else
8385                         break;
8386         }
8387
8388         return num;
8389 }
8390
8391 /* Configure RSS */
8392 static int
8393 i40e_pf_config_rss(struct i40e_pf *pf)
8394 {
8395         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8396         struct rte_eth_rss_conf rss_conf;
8397         uint32_t i, lut = 0;
8398         uint16_t j, num;
8399
8400         /*
8401          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8402          * It's necessary to calculate the actual PF queues that are configured.
8403          */
8404         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8405                 num = i40e_pf_calc_configured_queues_num(pf);
8406         else
8407                 num = pf->dev_data->nb_rx_queues;
8408
8409         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8410         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8411                         num);
8412
8413         if (num == 0) {
8414                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8415                 return -ENOTSUP;
8416         }
8417
8418         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8419                 if (j == num)
8420                         j = 0;
8421                 lut = (lut << 8) | (j & ((0x1 <<
8422                         hw->func_caps.rss_table_entry_width) - 1));
8423                 if ((i & 3) == 3)
8424                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8425         }
8426
8427         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8428         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8429                 i40e_pf_disable_rss(pf);
8430                 return 0;
8431         }
8432         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8433                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8434                 /* Random default keys */
8435                 static uint32_t rss_key_default[] = {0x6b793944,
8436                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8437                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8438                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8439
8440                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8441                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8442                                                         sizeof(uint32_t);
8443         }
8444
8445         return i40e_hw_rss_hash_set(pf, &rss_conf);
8446 }
8447
8448 static int
8449 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8450                                struct rte_eth_tunnel_filter_conf *filter)
8451 {
8452         if (pf == NULL || filter == NULL) {
8453                 PMD_DRV_LOG(ERR, "Invalid parameter");
8454                 return -EINVAL;
8455         }
8456
8457         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8458                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8459                 return -EINVAL;
8460         }
8461
8462         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8463                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8464                 return -EINVAL;
8465         }
8466
8467         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8468                 (is_zero_ether_addr(&filter->outer_mac))) {
8469                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8470                 return -EINVAL;
8471         }
8472
8473         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8474                 (is_zero_ether_addr(&filter->inner_mac))) {
8475                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8476                 return -EINVAL;
8477         }
8478
8479         return 0;
8480 }
8481
8482 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8483 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8484 static int
8485 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8486 {
8487         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8488         uint32_t val, reg;
8489         int ret = -EINVAL;
8490
8491         if (pf->support_multi_driver) {
8492                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8493                 return -ENOTSUP;
8494         }
8495
8496         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8497         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8498
8499         if (len == 3) {
8500                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8501         } else if (len == 4) {
8502                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8503         } else {
8504                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8505                 return ret;
8506         }
8507
8508         if (reg != val) {
8509                 ret = i40e_aq_debug_write_global_register(hw,
8510                                                    I40E_GL_PRS_FVBM(2),
8511                                                    reg, NULL);
8512                 if (ret != 0)
8513                         return ret;
8514                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8515                             "with value 0x%08x",
8516                             I40E_GL_PRS_FVBM(2), reg);
8517         } else {
8518                 ret = 0;
8519         }
8520         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8521                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8522
8523         return ret;
8524 }
8525
8526 static int
8527 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8528 {
8529         int ret = -EINVAL;
8530
8531         if (!hw || !cfg)
8532                 return -EINVAL;
8533
8534         switch (cfg->cfg_type) {
8535         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8536                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8537                 break;
8538         default:
8539                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8540                 break;
8541         }
8542
8543         return ret;
8544 }
8545
8546 static int
8547 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8548                                enum rte_filter_op filter_op,
8549                                void *arg)
8550 {
8551         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8552         int ret = I40E_ERR_PARAM;
8553
8554         switch (filter_op) {
8555         case RTE_ETH_FILTER_SET:
8556                 ret = i40e_dev_global_config_set(hw,
8557                         (struct rte_eth_global_cfg *)arg);
8558                 break;
8559         default:
8560                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8561                 break;
8562         }
8563
8564         return ret;
8565 }
8566
8567 static int
8568 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8569                           enum rte_filter_op filter_op,
8570                           void *arg)
8571 {
8572         struct rte_eth_tunnel_filter_conf *filter;
8573         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8574         int ret = I40E_SUCCESS;
8575
8576         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8577
8578         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8579                 return I40E_ERR_PARAM;
8580
8581         switch (filter_op) {
8582         case RTE_ETH_FILTER_NOP:
8583                 if (!(pf->flags & I40E_FLAG_VXLAN))
8584                         ret = I40E_NOT_SUPPORTED;
8585                 break;
8586         case RTE_ETH_FILTER_ADD:
8587                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8588                 break;
8589         case RTE_ETH_FILTER_DELETE:
8590                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8591                 break;
8592         default:
8593                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8594                 ret = I40E_ERR_PARAM;
8595                 break;
8596         }
8597
8598         return ret;
8599 }
8600
8601 static int
8602 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8603 {
8604         int ret = 0;
8605         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8606
8607         /* RSS setup */
8608         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8609                 ret = i40e_pf_config_rss(pf);
8610         else
8611                 i40e_pf_disable_rss(pf);
8612
8613         return ret;
8614 }
8615
8616 /* Get the symmetric hash enable configurations per port */
8617 static void
8618 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8619 {
8620         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8621
8622         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8623 }
8624
8625 /* Set the symmetric hash enable configurations per port */
8626 static void
8627 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8628 {
8629         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8630
8631         if (enable > 0) {
8632                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8633                         PMD_DRV_LOG(INFO,
8634                                 "Symmetric hash has already been enabled");
8635                         return;
8636                 }
8637                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8638         } else {
8639                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8640                         PMD_DRV_LOG(INFO,
8641                                 "Symmetric hash has already been disabled");
8642                         return;
8643                 }
8644                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8645         }
8646         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8647         I40E_WRITE_FLUSH(hw);
8648 }
8649
8650 /*
8651  * Get global configurations of hash function type and symmetric hash enable
8652  * per flow type (pctype). Note that global configuration means it affects all
8653  * the ports on the same NIC.
8654  */
8655 static int
8656 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8657                                    struct rte_eth_hash_global_conf *g_cfg)
8658 {
8659         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8660         uint32_t reg;
8661         uint16_t i, j;
8662
8663         memset(g_cfg, 0, sizeof(*g_cfg));
8664         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8665         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8666                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8667         else
8668                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8669         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8670                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8671
8672         /*
8673          * As i40e supports less than 64 flow types, only first 64 bits need to
8674          * be checked.
8675          */
8676         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8677                 g_cfg->valid_bit_mask[i] = 0ULL;
8678                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8679         }
8680
8681         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8682
8683         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8684                 if (!adapter->pctypes_tbl[i])
8685                         continue;
8686                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8687                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8688                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8689                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8690                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8691                                         g_cfg->sym_hash_enable_mask[0] |=
8692                                                                 (1ULL << i);
8693                                 }
8694                         }
8695                 }
8696         }
8697
8698         return 0;
8699 }
8700
8701 static int
8702 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8703                               const struct rte_eth_hash_global_conf *g_cfg)
8704 {
8705         uint32_t i;
8706         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8707
8708         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8709                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8710                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8711                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8712                                                 g_cfg->hash_func);
8713                 return -EINVAL;
8714         }
8715
8716         /*
8717          * As i40e supports less than 64 flow types, only first 64 bits need to
8718          * be checked.
8719          */
8720         mask0 = g_cfg->valid_bit_mask[0];
8721         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8722                 if (i == 0) {
8723                         /* Check if any unsupported flow type configured */
8724                         if ((mask0 | i40e_mask) ^ i40e_mask)
8725                                 goto mask_err;
8726                 } else {
8727                         if (g_cfg->valid_bit_mask[i])
8728                                 goto mask_err;
8729                 }
8730         }
8731
8732         return 0;
8733
8734 mask_err:
8735         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8736
8737         return -EINVAL;
8738 }
8739
8740 /*
8741  * Set global configurations of hash function type and symmetric hash enable
8742  * per flow type (pctype). Note any modifying global configuration will affect
8743  * all the ports on the same NIC.
8744  */
8745 static int
8746 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8747                                    struct rte_eth_hash_global_conf *g_cfg)
8748 {
8749         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8750         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8751         int ret;
8752         uint16_t i, j;
8753         uint32_t reg;
8754         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8755
8756         if (pf->support_multi_driver) {
8757                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8758                 return -ENOTSUP;
8759         }
8760
8761         /* Check the input parameters */
8762         ret = i40e_hash_global_config_check(adapter, g_cfg);
8763         if (ret < 0)
8764                 return ret;
8765
8766         /*
8767          * As i40e supports less than 64 flow types, only first 64 bits need to
8768          * be configured.
8769          */
8770         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8771                 if (mask0 & (1UL << i)) {
8772                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8773                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8774
8775                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8776                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8777                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8778                                         i40e_write_global_rx_ctl(hw,
8779                                                           I40E_GLQF_HSYM(j),
8780                                                           reg);
8781                         }
8782                 }
8783         }
8784
8785         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8786         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8787                 /* Toeplitz */
8788                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8789                         PMD_DRV_LOG(DEBUG,
8790                                 "Hash function already set to Toeplitz");
8791                         goto out;
8792                 }
8793                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8794         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8795                 /* Simple XOR */
8796                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8797                         PMD_DRV_LOG(DEBUG,
8798                                 "Hash function already set to Simple XOR");
8799                         goto out;
8800                 }
8801                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8802         } else
8803                 /* Use the default, and keep it as it is */
8804                 goto out;
8805
8806         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8807
8808 out:
8809         I40E_WRITE_FLUSH(hw);
8810
8811         return 0;
8812 }
8813
8814 /**
8815  * Valid input sets for hash and flow director filters per PCTYPE
8816  */
8817 static uint64_t
8818 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8819                 enum rte_filter_type filter)
8820 {
8821         uint64_t valid;
8822
8823         static const uint64_t valid_hash_inset_table[] = {
8824                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8825                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8826                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8827                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8828                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8829                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8830                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8831                         I40E_INSET_FLEX_PAYLOAD,
8832                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8833                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8834                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8835                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8836                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8837                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8838                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8839                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8840                         I40E_INSET_FLEX_PAYLOAD,
8841                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8842                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8843                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8844                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8845                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8846                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8847                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8848                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8849                         I40E_INSET_FLEX_PAYLOAD,
8850                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8851                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8852                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8853                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8854                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8855                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8856                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8857                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8858                         I40E_INSET_FLEX_PAYLOAD,
8859                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8860                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8861                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8862                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8863                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8864                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8865                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8866                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8867                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8868                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8869                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8870                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8871                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8872                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8873                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8874                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8875                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8876                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8877                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8878                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8879                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8880                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8881                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8882                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8883                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8884                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8885                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8886                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8887                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8888                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8889                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8890                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8891                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8892                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8893                         I40E_INSET_FLEX_PAYLOAD,
8894                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8895                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8896                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8897                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8898                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8899                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8900                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8901                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8902                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8903                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8904                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8905                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8906                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8907                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8908                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8909                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8910                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8911                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8912                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8913                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8914                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8915                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8916                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8917                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8918                         I40E_INSET_FLEX_PAYLOAD,
8919                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8920                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8921                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8922                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8923                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8924                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8925                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8926                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8927                         I40E_INSET_FLEX_PAYLOAD,
8928                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8929                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8930                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8931                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8932                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8933                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8934                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8935                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8936                         I40E_INSET_FLEX_PAYLOAD,
8937                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8938                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8939                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8940                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8941                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8942                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8943                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8944                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8945                         I40E_INSET_FLEX_PAYLOAD,
8946                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8947                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8948                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8949                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8950                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8951                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8952                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8953                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8954                         I40E_INSET_FLEX_PAYLOAD,
8955                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8956                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8957                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8958                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8959                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8960                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8961                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8962                         I40E_INSET_FLEX_PAYLOAD,
8963                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8964                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8965                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8966                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8967                         I40E_INSET_FLEX_PAYLOAD,
8968         };
8969
8970         /**
8971          * Flow director supports only fields defined in
8972          * union rte_eth_fdir_flow.
8973          */
8974         static const uint64_t valid_fdir_inset_table[] = {
8975                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8976                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8977                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8978                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8979                 I40E_INSET_IPV4_TTL,
8980                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8981                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8982                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8983                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8984                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8985                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8986                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8987                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8988                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8989                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8990                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8991                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8992                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8993                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8994                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8995                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8996                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8997                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8998                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8999                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9000                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9001                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9002                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9003                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9004                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9005                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9006                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9007                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9008                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9009                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9010                 I40E_INSET_SCTP_VT,
9011                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9012                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9013                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9014                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9015                 I40E_INSET_IPV4_TTL,
9016                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9017                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9018                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9019                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9020                 I40E_INSET_IPV6_HOP_LIMIT,
9021                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9022                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9023                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9024                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9025                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9026                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9027                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9028                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9029                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9030                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9031                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9032                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9033                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9034                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9035                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9036                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9037                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9038                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9039                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9040                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9041                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9042                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9043                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9044                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9045                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9046                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9047                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9048                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9049                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9050                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9051                 I40E_INSET_SCTP_VT,
9052                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9053                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9054                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9055                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9056                 I40E_INSET_IPV6_HOP_LIMIT,
9057                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9058                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9059                 I40E_INSET_LAST_ETHER_TYPE,
9060         };
9061
9062         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9063                 return 0;
9064         if (filter == RTE_ETH_FILTER_HASH)
9065                 valid = valid_hash_inset_table[pctype];
9066         else
9067                 valid = valid_fdir_inset_table[pctype];
9068
9069         return valid;
9070 }
9071
9072 /**
9073  * Validate if the input set is allowed for a specific PCTYPE
9074  */
9075 int
9076 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9077                 enum rte_filter_type filter, uint64_t inset)
9078 {
9079         uint64_t valid;
9080
9081         valid = i40e_get_valid_input_set(pctype, filter);
9082         if (inset & (~valid))
9083                 return -EINVAL;
9084
9085         return 0;
9086 }
9087
9088 /* default input set fields combination per pctype */
9089 uint64_t
9090 i40e_get_default_input_set(uint16_t pctype)
9091 {
9092         static const uint64_t default_inset_table[] = {
9093                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9094                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9095                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9096                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9097                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9098                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9099                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9100                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9101                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9102                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9103                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9104                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9105                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9106                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9107                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9108                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9109                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9110                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9111                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9112                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9113                         I40E_INSET_SCTP_VT,
9114                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9115                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9116                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9117                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9118                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9119                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9120                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9121                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9122                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9123                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9124                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9125                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9126                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9127                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9128                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9129                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9130                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9131                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9132                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9133                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9134                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9135                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9136                         I40E_INSET_SCTP_VT,
9137                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9138                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9139                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9140                         I40E_INSET_LAST_ETHER_TYPE,
9141         };
9142
9143         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9144                 return 0;
9145
9146         return default_inset_table[pctype];
9147 }
9148
9149 /**
9150  * Parse the input set from index to logical bit masks
9151  */
9152 static int
9153 i40e_parse_input_set(uint64_t *inset,
9154                      enum i40e_filter_pctype pctype,
9155                      enum rte_eth_input_set_field *field,
9156                      uint16_t size)
9157 {
9158         uint16_t i, j;
9159         int ret = -EINVAL;
9160
9161         static const struct {
9162                 enum rte_eth_input_set_field field;
9163                 uint64_t inset;
9164         } inset_convert_table[] = {
9165                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9166                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9167                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9168                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9169                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9170                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9171                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9172                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9173                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9174                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9175                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9176                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9177                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9178                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9179                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9180                         I40E_INSET_IPV6_NEXT_HDR},
9181                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9182                         I40E_INSET_IPV6_HOP_LIMIT},
9183                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9184                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9185                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9186                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9187                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9188                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9189                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9190                         I40E_INSET_SCTP_VT},
9191                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9192                         I40E_INSET_TUNNEL_DMAC},
9193                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9194                         I40E_INSET_VLAN_TUNNEL},
9195                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9196                         I40E_INSET_TUNNEL_ID},
9197                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9198                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9199                         I40E_INSET_FLEX_PAYLOAD_W1},
9200                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9201                         I40E_INSET_FLEX_PAYLOAD_W2},
9202                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9203                         I40E_INSET_FLEX_PAYLOAD_W3},
9204                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9205                         I40E_INSET_FLEX_PAYLOAD_W4},
9206                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9207                         I40E_INSET_FLEX_PAYLOAD_W5},
9208                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9209                         I40E_INSET_FLEX_PAYLOAD_W6},
9210                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9211                         I40E_INSET_FLEX_PAYLOAD_W7},
9212                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9213                         I40E_INSET_FLEX_PAYLOAD_W8},
9214         };
9215
9216         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9217                 return ret;
9218
9219         /* Only one item allowed for default or all */
9220         if (size == 1) {
9221                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9222                         *inset = i40e_get_default_input_set(pctype);
9223                         return 0;
9224                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9225                         *inset = I40E_INSET_NONE;
9226                         return 0;
9227                 }
9228         }
9229
9230         for (i = 0, *inset = 0; i < size; i++) {
9231                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9232                         if (field[i] == inset_convert_table[j].field) {
9233                                 *inset |= inset_convert_table[j].inset;
9234                                 break;
9235                         }
9236                 }
9237
9238                 /* It contains unsupported input set, return immediately */
9239                 if (j == RTE_DIM(inset_convert_table))
9240                         return ret;
9241         }
9242
9243         return 0;
9244 }
9245
9246 /**
9247  * Translate the input set from bit masks to register aware bit masks
9248  * and vice versa
9249  */
9250 uint64_t
9251 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9252 {
9253         uint64_t val = 0;
9254         uint16_t i;
9255
9256         struct inset_map {
9257                 uint64_t inset;
9258                 uint64_t inset_reg;
9259         };
9260
9261         static const struct inset_map inset_map_common[] = {
9262                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9263                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9264                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9265                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9266                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9267                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9268                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9269                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9270                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9271                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9272                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9273                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9274                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9275                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9276                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9277                 {I40E_INSET_TUNNEL_DMAC,
9278                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9279                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9280                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9281                 {I40E_INSET_TUNNEL_SRC_PORT,
9282                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9283                 {I40E_INSET_TUNNEL_DST_PORT,
9284                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9285                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9286                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9287                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9288                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9289                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9290                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9291                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9292                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9293                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9294         };
9295
9296     /* some different registers map in x722*/
9297         static const struct inset_map inset_map_diff_x722[] = {
9298                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9299                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9300                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9301                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9302         };
9303
9304         static const struct inset_map inset_map_diff_not_x722[] = {
9305                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9306                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9307                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9308                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9309         };
9310
9311         if (input == 0)
9312                 return val;
9313
9314         /* Translate input set to register aware inset */
9315         if (type == I40E_MAC_X722) {
9316                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9317                         if (input & inset_map_diff_x722[i].inset)
9318                                 val |= inset_map_diff_x722[i].inset_reg;
9319                 }
9320         } else {
9321                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9322                         if (input & inset_map_diff_not_x722[i].inset)
9323                                 val |= inset_map_diff_not_x722[i].inset_reg;
9324                 }
9325         }
9326
9327         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9328                 if (input & inset_map_common[i].inset)
9329                         val |= inset_map_common[i].inset_reg;
9330         }
9331
9332         return val;
9333 }
9334
9335 int
9336 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9337 {
9338         uint8_t i, idx = 0;
9339         uint64_t inset_need_mask = inset;
9340
9341         static const struct {
9342                 uint64_t inset;
9343                 uint32_t mask;
9344         } inset_mask_map[] = {
9345                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9346                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9347                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9348                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9349                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9350                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9351                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9352                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9353         };
9354
9355         if (!inset || !mask || !nb_elem)
9356                 return 0;
9357
9358         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9359                 /* Clear the inset bit, if no MASK is required,
9360                  * for example proto + ttl
9361                  */
9362                 if ((inset & inset_mask_map[i].inset) ==
9363                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9364                         inset_need_mask &= ~inset_mask_map[i].inset;
9365                 if (!inset_need_mask)
9366                         return 0;
9367         }
9368         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9369                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9370                     inset_mask_map[i].inset) {
9371                         if (idx >= nb_elem) {
9372                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9373                                 return -EINVAL;
9374                         }
9375                         mask[idx] = inset_mask_map[i].mask;
9376                         idx++;
9377                 }
9378         }
9379
9380         return idx;
9381 }
9382
9383 void
9384 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9385 {
9386         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9387
9388         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9389         if (reg != val)
9390                 i40e_write_rx_ctl(hw, addr, val);
9391         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9392                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9393 }
9394
9395 void
9396 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9397 {
9398         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9399         struct rte_eth_dev *dev;
9400
9401         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9402         if (reg != val) {
9403                 i40e_write_rx_ctl(hw, addr, val);
9404                 PMD_DRV_LOG(WARNING,
9405                             "i40e device %s changed global register [0x%08x]."
9406                             " original: 0x%08x, new: 0x%08x",
9407                             dev->device->name, addr, reg,
9408                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9409         }
9410 }
9411
9412 static void
9413 i40e_filter_input_set_init(struct i40e_pf *pf)
9414 {
9415         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9416         enum i40e_filter_pctype pctype;
9417         uint64_t input_set, inset_reg;
9418         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9419         int num, i;
9420         uint16_t flow_type;
9421
9422         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9423              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9424                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9425
9426                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9427                         continue;
9428
9429                 input_set = i40e_get_default_input_set(pctype);
9430
9431                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9432                                                    I40E_INSET_MASK_NUM_REG);
9433                 if (num < 0)
9434                         return;
9435                 if (pf->support_multi_driver && num > 0) {
9436                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9437                         return;
9438                 }
9439                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9440                                         input_set);
9441
9442                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9443                                       (uint32_t)(inset_reg & UINT32_MAX));
9444                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9445                                      (uint32_t)((inset_reg >>
9446                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9447                 if (!pf->support_multi_driver) {
9448                         i40e_check_write_global_reg(hw,
9449                                             I40E_GLQF_HASH_INSET(0, pctype),
9450                                             (uint32_t)(inset_reg & UINT32_MAX));
9451                         i40e_check_write_global_reg(hw,
9452                                              I40E_GLQF_HASH_INSET(1, pctype),
9453                                              (uint32_t)((inset_reg >>
9454                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9455
9456                         for (i = 0; i < num; i++) {
9457                                 i40e_check_write_global_reg(hw,
9458                                                     I40E_GLQF_FD_MSK(i, pctype),
9459                                                     mask_reg[i]);
9460                                 i40e_check_write_global_reg(hw,
9461                                                   I40E_GLQF_HASH_MSK(i, pctype),
9462                                                   mask_reg[i]);
9463                         }
9464                         /*clear unused mask registers of the pctype */
9465                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9466                                 i40e_check_write_global_reg(hw,
9467                                                     I40E_GLQF_FD_MSK(i, pctype),
9468                                                     0);
9469                                 i40e_check_write_global_reg(hw,
9470                                                   I40E_GLQF_HASH_MSK(i, pctype),
9471                                                   0);
9472                         }
9473                 } else {
9474                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9475                 }
9476                 I40E_WRITE_FLUSH(hw);
9477
9478                 /* store the default input set */
9479                 if (!pf->support_multi_driver)
9480                         pf->hash_input_set[pctype] = input_set;
9481                 pf->fdir.input_set[pctype] = input_set;
9482         }
9483 }
9484
9485 int
9486 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9487                          struct rte_eth_input_set_conf *conf)
9488 {
9489         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9490         enum i40e_filter_pctype pctype;
9491         uint64_t input_set, inset_reg = 0;
9492         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9493         int ret, i, num;
9494
9495         if (!conf) {
9496                 PMD_DRV_LOG(ERR, "Invalid pointer");
9497                 return -EFAULT;
9498         }
9499         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9500             conf->op != RTE_ETH_INPUT_SET_ADD) {
9501                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9502                 return -EINVAL;
9503         }
9504
9505         if (pf->support_multi_driver) {
9506                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9507                 return -ENOTSUP;
9508         }
9509
9510         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9511         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9512                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9513                 return -EINVAL;
9514         }
9515
9516         if (hw->mac.type == I40E_MAC_X722) {
9517                 /* get translated pctype value in fd pctype register */
9518                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9519                         I40E_GLQF_FD_PCTYPES((int)pctype));
9520         }
9521
9522         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9523                                    conf->inset_size);
9524         if (ret) {
9525                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9526                 return -EINVAL;
9527         }
9528
9529         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9530                 /* get inset value in register */
9531                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9532                 inset_reg <<= I40E_32_BIT_WIDTH;
9533                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9534                 input_set |= pf->hash_input_set[pctype];
9535         }
9536         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9537                                            I40E_INSET_MASK_NUM_REG);
9538         if (num < 0)
9539                 return -EINVAL;
9540
9541         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9542
9543         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9544                                     (uint32_t)(inset_reg & UINT32_MAX));
9545         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9546                                     (uint32_t)((inset_reg >>
9547                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9548
9549         for (i = 0; i < num; i++)
9550                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9551                                             mask_reg[i]);
9552         /*clear unused mask registers of the pctype */
9553         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9554                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9555                                             0);
9556         I40E_WRITE_FLUSH(hw);
9557
9558         pf->hash_input_set[pctype] = input_set;
9559         return 0;
9560 }
9561
9562 int
9563 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9564                          struct rte_eth_input_set_conf *conf)
9565 {
9566         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9567         enum i40e_filter_pctype pctype;
9568         uint64_t input_set, inset_reg = 0;
9569         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9570         int ret, i, num;
9571
9572         if (!hw || !conf) {
9573                 PMD_DRV_LOG(ERR, "Invalid pointer");
9574                 return -EFAULT;
9575         }
9576         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9577             conf->op != RTE_ETH_INPUT_SET_ADD) {
9578                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9579                 return -EINVAL;
9580         }
9581
9582         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9583
9584         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9585                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9586                 return -EINVAL;
9587         }
9588
9589         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9590                                    conf->inset_size);
9591         if (ret) {
9592                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9593                 return -EINVAL;
9594         }
9595
9596         /* get inset value in register */
9597         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9598         inset_reg <<= I40E_32_BIT_WIDTH;
9599         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9600
9601         /* Can not change the inset reg for flex payload for fdir,
9602          * it is done by writing I40E_PRTQF_FD_FLXINSET
9603          * in i40e_set_flex_mask_on_pctype.
9604          */
9605         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9606                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9607         else
9608                 input_set |= pf->fdir.input_set[pctype];
9609         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9610                                            I40E_INSET_MASK_NUM_REG);
9611         if (num < 0)
9612                 return -EINVAL;
9613         if (pf->support_multi_driver && num > 0) {
9614                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9615                 return -ENOTSUP;
9616         }
9617
9618         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9619
9620         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9621                               (uint32_t)(inset_reg & UINT32_MAX));
9622         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9623                              (uint32_t)((inset_reg >>
9624                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9625
9626         if (!pf->support_multi_driver) {
9627                 for (i = 0; i < num; i++)
9628                         i40e_check_write_global_reg(hw,
9629                                                     I40E_GLQF_FD_MSK(i, pctype),
9630                                                     mask_reg[i]);
9631                 /*clear unused mask registers of the pctype */
9632                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9633                         i40e_check_write_global_reg(hw,
9634                                                     I40E_GLQF_FD_MSK(i, pctype),
9635                                                     0);
9636         } else {
9637                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9638         }
9639         I40E_WRITE_FLUSH(hw);
9640
9641         pf->fdir.input_set[pctype] = input_set;
9642         return 0;
9643 }
9644
9645 static int
9646 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9647 {
9648         int ret = 0;
9649
9650         if (!hw || !info) {
9651                 PMD_DRV_LOG(ERR, "Invalid pointer");
9652                 return -EFAULT;
9653         }
9654
9655         switch (info->info_type) {
9656         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9657                 i40e_get_symmetric_hash_enable_per_port(hw,
9658                                         &(info->info.enable));
9659                 break;
9660         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9661                 ret = i40e_get_hash_filter_global_config(hw,
9662                                 &(info->info.global_conf));
9663                 break;
9664         default:
9665                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9666                                                         info->info_type);
9667                 ret = -EINVAL;
9668                 break;
9669         }
9670
9671         return ret;
9672 }
9673
9674 static int
9675 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9676 {
9677         int ret = 0;
9678
9679         if (!hw || !info) {
9680                 PMD_DRV_LOG(ERR, "Invalid pointer");
9681                 return -EFAULT;
9682         }
9683
9684         switch (info->info_type) {
9685         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9686                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9687                 break;
9688         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9689                 ret = i40e_set_hash_filter_global_config(hw,
9690                                 &(info->info.global_conf));
9691                 break;
9692         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9693                 ret = i40e_hash_filter_inset_select(hw,
9694                                                &(info->info.input_set_conf));
9695                 break;
9696
9697         default:
9698                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9699                                                         info->info_type);
9700                 ret = -EINVAL;
9701                 break;
9702         }
9703
9704         return ret;
9705 }
9706
9707 /* Operations for hash function */
9708 static int
9709 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9710                       enum rte_filter_op filter_op,
9711                       void *arg)
9712 {
9713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9714         int ret = 0;
9715
9716         switch (filter_op) {
9717         case RTE_ETH_FILTER_NOP:
9718                 break;
9719         case RTE_ETH_FILTER_GET:
9720                 ret = i40e_hash_filter_get(hw,
9721                         (struct rte_eth_hash_filter_info *)arg);
9722                 break;
9723         case RTE_ETH_FILTER_SET:
9724                 ret = i40e_hash_filter_set(hw,
9725                         (struct rte_eth_hash_filter_info *)arg);
9726                 break;
9727         default:
9728                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9729                                                                 filter_op);
9730                 ret = -ENOTSUP;
9731                 break;
9732         }
9733
9734         return ret;
9735 }
9736
9737 /* Convert ethertype filter structure */
9738 static int
9739 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9740                               struct i40e_ethertype_filter *filter)
9741 {
9742         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9743         filter->input.ether_type = input->ether_type;
9744         filter->flags = input->flags;
9745         filter->queue = input->queue;
9746
9747         return 0;
9748 }
9749
9750 /* Check if there exists the ehtertype filter */
9751 struct i40e_ethertype_filter *
9752 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9753                                 const struct i40e_ethertype_filter_input *input)
9754 {
9755         int ret;
9756
9757         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9758         if (ret < 0)
9759                 return NULL;
9760
9761         return ethertype_rule->hash_map[ret];
9762 }
9763
9764 /* Add ethertype filter in SW list */
9765 static int
9766 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9767                                 struct i40e_ethertype_filter *filter)
9768 {
9769         struct i40e_ethertype_rule *rule = &pf->ethertype;
9770         int ret;
9771
9772         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9773         if (ret < 0) {
9774                 PMD_DRV_LOG(ERR,
9775                             "Failed to insert ethertype filter"
9776                             " to hash table %d!",
9777                             ret);
9778                 return ret;
9779         }
9780         rule->hash_map[ret] = filter;
9781
9782         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9783
9784         return 0;
9785 }
9786
9787 /* Delete ethertype filter in SW list */
9788 int
9789 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9790                              struct i40e_ethertype_filter_input *input)
9791 {
9792         struct i40e_ethertype_rule *rule = &pf->ethertype;
9793         struct i40e_ethertype_filter *filter;
9794         int ret;
9795
9796         ret = rte_hash_del_key(rule->hash_table, input);
9797         if (ret < 0) {
9798                 PMD_DRV_LOG(ERR,
9799                             "Failed to delete ethertype filter"
9800                             " to hash table %d!",
9801                             ret);
9802                 return ret;
9803         }
9804         filter = rule->hash_map[ret];
9805         rule->hash_map[ret] = NULL;
9806
9807         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9808         rte_free(filter);
9809
9810         return 0;
9811 }
9812
9813 /*
9814  * Configure ethertype filter, which can director packet by filtering
9815  * with mac address and ether_type or only ether_type
9816  */
9817 int
9818 i40e_ethertype_filter_set(struct i40e_pf *pf,
9819                         struct rte_eth_ethertype_filter *filter,
9820                         bool add)
9821 {
9822         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9823         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9824         struct i40e_ethertype_filter *ethertype_filter, *node;
9825         struct i40e_ethertype_filter check_filter;
9826         struct i40e_control_filter_stats stats;
9827         uint16_t flags = 0;
9828         int ret;
9829
9830         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9831                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9832                 return -EINVAL;
9833         }
9834         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9835                 filter->ether_type == ETHER_TYPE_IPv6) {
9836                 PMD_DRV_LOG(ERR,
9837                         "unsupported ether_type(0x%04x) in control packet filter.",
9838                         filter->ether_type);
9839                 return -EINVAL;
9840         }
9841         if (filter->ether_type == ETHER_TYPE_VLAN)
9842                 PMD_DRV_LOG(WARNING,
9843                         "filter vlan ether_type in first tag is not supported.");
9844
9845         /* Check if there is the filter in SW list */
9846         memset(&check_filter, 0, sizeof(check_filter));
9847         i40e_ethertype_filter_convert(filter, &check_filter);
9848         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9849                                                &check_filter.input);
9850         if (add && node) {
9851                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9852                 return -EINVAL;
9853         }
9854
9855         if (!add && !node) {
9856                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9857                 return -EINVAL;
9858         }
9859
9860         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9861                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9862         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9863                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9864         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9865
9866         memset(&stats, 0, sizeof(stats));
9867         ret = i40e_aq_add_rem_control_packet_filter(hw,
9868                         filter->mac_addr.addr_bytes,
9869                         filter->ether_type, flags,
9870                         pf->main_vsi->seid,
9871                         filter->queue, add, &stats, NULL);
9872
9873         PMD_DRV_LOG(INFO,
9874                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9875                 ret, stats.mac_etype_used, stats.etype_used,
9876                 stats.mac_etype_free, stats.etype_free);
9877         if (ret < 0)
9878                 return -ENOSYS;
9879
9880         /* Add or delete a filter in SW list */
9881         if (add) {
9882                 ethertype_filter = rte_zmalloc("ethertype_filter",
9883                                        sizeof(*ethertype_filter), 0);
9884                 if (ethertype_filter == NULL) {
9885                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9886                         return -ENOMEM;
9887                 }
9888
9889                 rte_memcpy(ethertype_filter, &check_filter,
9890                            sizeof(check_filter));
9891                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9892                 if (ret < 0)
9893                         rte_free(ethertype_filter);
9894         } else {
9895                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9896         }
9897
9898         return ret;
9899 }
9900
9901 /*
9902  * Handle operations for ethertype filter.
9903  */
9904 static int
9905 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9906                                 enum rte_filter_op filter_op,
9907                                 void *arg)
9908 {
9909         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9910         int ret = 0;
9911
9912         if (filter_op == RTE_ETH_FILTER_NOP)
9913                 return ret;
9914
9915         if (arg == NULL) {
9916                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9917                             filter_op);
9918                 return -EINVAL;
9919         }
9920
9921         switch (filter_op) {
9922         case RTE_ETH_FILTER_ADD:
9923                 ret = i40e_ethertype_filter_set(pf,
9924                         (struct rte_eth_ethertype_filter *)arg,
9925                         TRUE);
9926                 break;
9927         case RTE_ETH_FILTER_DELETE:
9928                 ret = i40e_ethertype_filter_set(pf,
9929                         (struct rte_eth_ethertype_filter *)arg,
9930                         FALSE);
9931                 break;
9932         default:
9933                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9934                 ret = -ENOSYS;
9935                 break;
9936         }
9937         return ret;
9938 }
9939
9940 static int
9941 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9942                      enum rte_filter_type filter_type,
9943                      enum rte_filter_op filter_op,
9944                      void *arg)
9945 {
9946         int ret = 0;
9947
9948         if (dev == NULL)
9949                 return -EINVAL;
9950
9951         switch (filter_type) {
9952         case RTE_ETH_FILTER_NONE:
9953                 /* For global configuration */
9954                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9955                 break;
9956         case RTE_ETH_FILTER_HASH:
9957                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9958                 break;
9959         case RTE_ETH_FILTER_MACVLAN:
9960                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9961                 break;
9962         case RTE_ETH_FILTER_ETHERTYPE:
9963                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9964                 break;
9965         case RTE_ETH_FILTER_TUNNEL:
9966                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9967                 break;
9968         case RTE_ETH_FILTER_FDIR:
9969                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9970                 break;
9971         case RTE_ETH_FILTER_GENERIC:
9972                 if (filter_op != RTE_ETH_FILTER_GET)
9973                         return -EINVAL;
9974                 *(const void **)arg = &i40e_flow_ops;
9975                 break;
9976         default:
9977                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9978                                                         filter_type);
9979                 ret = -EINVAL;
9980                 break;
9981         }
9982
9983         return ret;
9984 }
9985
9986 /*
9987  * Check and enable Extended Tag.
9988  * Enabling Extended Tag is important for 40G performance.
9989  */
9990 static void
9991 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9992 {
9993         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9994         uint32_t buf = 0;
9995         int ret;
9996
9997         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9998                                       PCI_DEV_CAP_REG);
9999         if (ret < 0) {
10000                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10001                             PCI_DEV_CAP_REG);
10002                 return;
10003         }
10004         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10005                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10006                 return;
10007         }
10008
10009         buf = 0;
10010         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10011                                       PCI_DEV_CTRL_REG);
10012         if (ret < 0) {
10013                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10014                             PCI_DEV_CTRL_REG);
10015                 return;
10016         }
10017         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10018                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10019                 return;
10020         }
10021         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10022         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10023                                        PCI_DEV_CTRL_REG);
10024         if (ret < 0) {
10025                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10026                             PCI_DEV_CTRL_REG);
10027                 return;
10028         }
10029 }
10030
10031 /*
10032  * As some registers wouldn't be reset unless a global hardware reset,
10033  * hardware initialization is needed to put those registers into an
10034  * expected initial state.
10035  */
10036 static void
10037 i40e_hw_init(struct rte_eth_dev *dev)
10038 {
10039         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10040
10041         i40e_enable_extended_tag(dev);
10042
10043         /* clear the PF Queue Filter control register */
10044         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10045
10046         /* Disable symmetric hash per port */
10047         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10048 }
10049
10050 /*
10051  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10052  * however this function will return only one highest pctype index,
10053  * which is not quite correct. This is known problem of i40e driver
10054  * and needs to be fixed later.
10055  */
10056 enum i40e_filter_pctype
10057 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10058 {
10059         int i;
10060         uint64_t pctype_mask;
10061
10062         if (flow_type < I40E_FLOW_TYPE_MAX) {
10063                 pctype_mask = adapter->pctypes_tbl[flow_type];
10064                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10065                         if (pctype_mask & (1ULL << i))
10066                                 return (enum i40e_filter_pctype)i;
10067                 }
10068         }
10069         return I40E_FILTER_PCTYPE_INVALID;
10070 }
10071
10072 uint16_t
10073 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10074                         enum i40e_filter_pctype pctype)
10075 {
10076         uint16_t flowtype;
10077         uint64_t pctype_mask = 1ULL << pctype;
10078
10079         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10080              flowtype++) {
10081                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10082                         return flowtype;
10083         }
10084
10085         return RTE_ETH_FLOW_UNKNOWN;
10086 }
10087
10088 /*
10089  * On X710, performance number is far from the expectation on recent firmware
10090  * versions; on XL710, performance number is also far from the expectation on
10091  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10092  * mode is enabled and port MAC address is equal to the packet destination MAC
10093  * address. The fix for this issue may not be integrated in the following
10094  * firmware version. So the workaround in software driver is needed. It needs
10095  * to modify the initial values of 3 internal only registers for both X710 and
10096  * XL710. Note that the values for X710 or XL710 could be different, and the
10097  * workaround can be removed when it is fixed in firmware in the future.
10098  */
10099
10100 /* For both X710 and XL710 */
10101 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10102 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10103 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10104
10105 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10106 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10107
10108 /* For X722 */
10109 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10110 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10111
10112 /* For X710 */
10113 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10114 /* For XL710 */
10115 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10116 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10117
10118 /*
10119  * GL_SWR_PM_UP_THR:
10120  * The value is not impacted from the link speed, its value is set according
10121  * to the total number of ports for a better pipe-monitor configuration.
10122  */
10123 static bool
10124 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10125 {
10126 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10127                 .device_id = (dev),   \
10128                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10129
10130 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10131                 .device_id = (dev),   \
10132                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10133
10134         static const struct {
10135                 uint16_t device_id;
10136                 uint32_t val;
10137         } swr_pm_table[] = {
10138                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10139                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10140                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10141                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10142
10143                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10144                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10145                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10146                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10147                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10148                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10149                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10150         };
10151         uint32_t i;
10152
10153         if (value == NULL) {
10154                 PMD_DRV_LOG(ERR, "value is NULL");
10155                 return false;
10156         }
10157
10158         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10159                 if (hw->device_id == swr_pm_table[i].device_id) {
10160                         *value = swr_pm_table[i].val;
10161
10162                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10163                                     "value - 0x%08x",
10164                                     hw->device_id, *value);
10165                         return true;
10166                 }
10167         }
10168
10169         return false;
10170 }
10171
10172 static int
10173 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10174 {
10175         enum i40e_status_code status;
10176         struct i40e_aq_get_phy_abilities_resp phy_ab;
10177         int ret = -ENOTSUP;
10178         int retries = 0;
10179
10180         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10181                                               NULL);
10182
10183         while (status) {
10184                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10185                         status);
10186                 retries++;
10187                 rte_delay_us(100000);
10188                 if  (retries < 5)
10189                         status = i40e_aq_get_phy_capabilities(hw, false,
10190                                         true, &phy_ab, NULL);
10191                 else
10192                         return ret;
10193         }
10194         return 0;
10195 }
10196
10197 static void
10198 i40e_configure_registers(struct i40e_hw *hw)
10199 {
10200         static struct {
10201                 uint32_t addr;
10202                 uint64_t val;
10203         } reg_table[] = {
10204                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10205                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10206                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10207         };
10208         uint64_t reg;
10209         uint32_t i;
10210         int ret;
10211
10212         for (i = 0; i < RTE_DIM(reg_table); i++) {
10213                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10214                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10215                                 reg_table[i].val =
10216                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10217                         else /* For X710/XL710/XXV710 */
10218                                 if (hw->aq.fw_maj_ver < 6)
10219                                         reg_table[i].val =
10220                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10221                                 else
10222                                         reg_table[i].val =
10223                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10224                 }
10225
10226                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10227                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10228                                 reg_table[i].val =
10229                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10230                         else /* For X710/XL710/XXV710 */
10231                                 reg_table[i].val =
10232                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10233                 }
10234
10235                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10236                         uint32_t cfg_val;
10237
10238                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10239                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10240                                             "GL_SWR_PM_UP_THR value fixup",
10241                                             hw->device_id);
10242                                 continue;
10243                         }
10244
10245                         reg_table[i].val = cfg_val;
10246                 }
10247
10248                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10249                                                         &reg, NULL);
10250                 if (ret < 0) {
10251                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10252                                                         reg_table[i].addr);
10253                         break;
10254                 }
10255                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10256                                                 reg_table[i].addr, reg);
10257                 if (reg == reg_table[i].val)
10258                         continue;
10259
10260                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10261                                                 reg_table[i].val, NULL);
10262                 if (ret < 0) {
10263                         PMD_DRV_LOG(ERR,
10264                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10265                                 reg_table[i].val, reg_table[i].addr);
10266                         break;
10267                 }
10268                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10269                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10270         }
10271 }
10272
10273 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10274 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10275 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10276 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10277 static int
10278 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10279 {
10280         uint32_t reg;
10281         int ret;
10282
10283         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10284                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10285                 return -EINVAL;
10286         }
10287
10288         /* Configure for double VLAN RX stripping */
10289         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10290         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10291                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10292                 ret = i40e_aq_debug_write_register(hw,
10293                                                    I40E_VSI_TSR(vsi->vsi_id),
10294                                                    reg, NULL);
10295                 if (ret < 0) {
10296                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10297                                     vsi->vsi_id);
10298                         return I40E_ERR_CONFIG;
10299                 }
10300         }
10301
10302         /* Configure for double VLAN TX insertion */
10303         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10304         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10305                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10306                 ret = i40e_aq_debug_write_register(hw,
10307                                                    I40E_VSI_L2TAGSTXVALID(
10308                                                    vsi->vsi_id), reg, NULL);
10309                 if (ret < 0) {
10310                         PMD_DRV_LOG(ERR,
10311                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10312                                 vsi->vsi_id);
10313                         return I40E_ERR_CONFIG;
10314                 }
10315         }
10316
10317         return 0;
10318 }
10319
10320 /**
10321  * i40e_aq_add_mirror_rule
10322  * @hw: pointer to the hardware structure
10323  * @seid: VEB seid to add mirror rule to
10324  * @dst_id: destination vsi seid
10325  * @entries: Buffer which contains the entities to be mirrored
10326  * @count: number of entities contained in the buffer
10327  * @rule_id:the rule_id of the rule to be added
10328  *
10329  * Add a mirror rule for a given veb.
10330  *
10331  **/
10332 static enum i40e_status_code
10333 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10334                         uint16_t seid, uint16_t dst_id,
10335                         uint16_t rule_type, uint16_t *entries,
10336                         uint16_t count, uint16_t *rule_id)
10337 {
10338         struct i40e_aq_desc desc;
10339         struct i40e_aqc_add_delete_mirror_rule cmd;
10340         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10341                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10342                 &desc.params.raw;
10343         uint16_t buff_len;
10344         enum i40e_status_code status;
10345
10346         i40e_fill_default_direct_cmd_desc(&desc,
10347                                           i40e_aqc_opc_add_mirror_rule);
10348         memset(&cmd, 0, sizeof(cmd));
10349
10350         buff_len = sizeof(uint16_t) * count;
10351         desc.datalen = rte_cpu_to_le_16(buff_len);
10352         if (buff_len > 0)
10353                 desc.flags |= rte_cpu_to_le_16(
10354                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10355         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10356                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10357         cmd.num_entries = rte_cpu_to_le_16(count);
10358         cmd.seid = rte_cpu_to_le_16(seid);
10359         cmd.destination = rte_cpu_to_le_16(dst_id);
10360
10361         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10362         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10363         PMD_DRV_LOG(INFO,
10364                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10365                 hw->aq.asq_last_status, resp->rule_id,
10366                 resp->mirror_rules_used, resp->mirror_rules_free);
10367         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10368
10369         return status;
10370 }
10371
10372 /**
10373  * i40e_aq_del_mirror_rule
10374  * @hw: pointer to the hardware structure
10375  * @seid: VEB seid to add mirror rule to
10376  * @entries: Buffer which contains the entities to be mirrored
10377  * @count: number of entities contained in the buffer
10378  * @rule_id:the rule_id of the rule to be delete
10379  *
10380  * Delete a mirror rule for a given veb.
10381  *
10382  **/
10383 static enum i40e_status_code
10384 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10385                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10386                 uint16_t count, uint16_t rule_id)
10387 {
10388         struct i40e_aq_desc desc;
10389         struct i40e_aqc_add_delete_mirror_rule cmd;
10390         uint16_t buff_len = 0;
10391         enum i40e_status_code status;
10392         void *buff = NULL;
10393
10394         i40e_fill_default_direct_cmd_desc(&desc,
10395                                           i40e_aqc_opc_delete_mirror_rule);
10396         memset(&cmd, 0, sizeof(cmd));
10397         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10398                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10399                                                           I40E_AQ_FLAG_RD));
10400                 cmd.num_entries = count;
10401                 buff_len = sizeof(uint16_t) * count;
10402                 desc.datalen = rte_cpu_to_le_16(buff_len);
10403                 buff = (void *)entries;
10404         } else
10405                 /* rule id is filled in destination field for deleting mirror rule */
10406                 cmd.destination = rte_cpu_to_le_16(rule_id);
10407
10408         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10409                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10410         cmd.seid = rte_cpu_to_le_16(seid);
10411
10412         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10413         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10414
10415         return status;
10416 }
10417
10418 /**
10419  * i40e_mirror_rule_set
10420  * @dev: pointer to the hardware structure
10421  * @mirror_conf: mirror rule info
10422  * @sw_id: mirror rule's sw_id
10423  * @on: enable/disable
10424  *
10425  * set a mirror rule.
10426  *
10427  **/
10428 static int
10429 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10430                         struct rte_eth_mirror_conf *mirror_conf,
10431                         uint8_t sw_id, uint8_t on)
10432 {
10433         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10434         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10435         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10436         struct i40e_mirror_rule *parent = NULL;
10437         uint16_t seid, dst_seid, rule_id;
10438         uint16_t i, j = 0;
10439         int ret;
10440
10441         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10442
10443         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10444                 PMD_DRV_LOG(ERR,
10445                         "mirror rule can not be configured without veb or vfs.");
10446                 return -ENOSYS;
10447         }
10448         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10449                 PMD_DRV_LOG(ERR, "mirror table is full.");
10450                 return -ENOSPC;
10451         }
10452         if (mirror_conf->dst_pool > pf->vf_num) {
10453                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10454                                  mirror_conf->dst_pool);
10455                 return -EINVAL;
10456         }
10457
10458         seid = pf->main_vsi->veb->seid;
10459
10460         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10461                 if (sw_id <= it->index) {
10462                         mirr_rule = it;
10463                         break;
10464                 }
10465                 parent = it;
10466         }
10467         if (mirr_rule && sw_id == mirr_rule->index) {
10468                 if (on) {
10469                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10470                         return -EEXIST;
10471                 } else {
10472                         ret = i40e_aq_del_mirror_rule(hw, seid,
10473                                         mirr_rule->rule_type,
10474                                         mirr_rule->entries,
10475                                         mirr_rule->num_entries, mirr_rule->id);
10476                         if (ret < 0) {
10477                                 PMD_DRV_LOG(ERR,
10478                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10479                                         ret, hw->aq.asq_last_status);
10480                                 return -ENOSYS;
10481                         }
10482                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10483                         rte_free(mirr_rule);
10484                         pf->nb_mirror_rule--;
10485                         return 0;
10486                 }
10487         } else if (!on) {
10488                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10489                 return -ENOENT;
10490         }
10491
10492         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10493                                 sizeof(struct i40e_mirror_rule) , 0);
10494         if (!mirr_rule) {
10495                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10496                 return I40E_ERR_NO_MEMORY;
10497         }
10498         switch (mirror_conf->rule_type) {
10499         case ETH_MIRROR_VLAN:
10500                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10501                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10502                                 mirr_rule->entries[j] =
10503                                         mirror_conf->vlan.vlan_id[i];
10504                                 j++;
10505                         }
10506                 }
10507                 if (j == 0) {
10508                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10509                         rte_free(mirr_rule);
10510                         return -EINVAL;
10511                 }
10512                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10513                 break;
10514         case ETH_MIRROR_VIRTUAL_POOL_UP:
10515         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10516                 /* check if the specified pool bit is out of range */
10517                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10518                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10519                         rte_free(mirr_rule);
10520                         return -EINVAL;
10521                 }
10522                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10523                         if (mirror_conf->pool_mask & (1ULL << i)) {
10524                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10525                                 j++;
10526                         }
10527                 }
10528                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10529                         /* add pf vsi to entries */
10530                         mirr_rule->entries[j] = pf->main_vsi_seid;
10531                         j++;
10532                 }
10533                 if (j == 0) {
10534                         PMD_DRV_LOG(ERR, "pool is not specified.");
10535                         rte_free(mirr_rule);
10536                         return -EINVAL;
10537                 }
10538                 /* egress and ingress in aq commands means from switch but not port */
10539                 mirr_rule->rule_type =
10540                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10541                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10542                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10543                 break;
10544         case ETH_MIRROR_UPLINK_PORT:
10545                 /* egress and ingress in aq commands means from switch but not port*/
10546                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10547                 break;
10548         case ETH_MIRROR_DOWNLINK_PORT:
10549                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10550                 break;
10551         default:
10552                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10553                         mirror_conf->rule_type);
10554                 rte_free(mirr_rule);
10555                 return -EINVAL;
10556         }
10557
10558         /* If the dst_pool is equal to vf_num, consider it as PF */
10559         if (mirror_conf->dst_pool == pf->vf_num)
10560                 dst_seid = pf->main_vsi_seid;
10561         else
10562                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10563
10564         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10565                                       mirr_rule->rule_type, mirr_rule->entries,
10566                                       j, &rule_id);
10567         if (ret < 0) {
10568                 PMD_DRV_LOG(ERR,
10569                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10570                         ret, hw->aq.asq_last_status);
10571                 rte_free(mirr_rule);
10572                 return -ENOSYS;
10573         }
10574
10575         mirr_rule->index = sw_id;
10576         mirr_rule->num_entries = j;
10577         mirr_rule->id = rule_id;
10578         mirr_rule->dst_vsi_seid = dst_seid;
10579
10580         if (parent)
10581                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10582         else
10583                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10584
10585         pf->nb_mirror_rule++;
10586         return 0;
10587 }
10588
10589 /**
10590  * i40e_mirror_rule_reset
10591  * @dev: pointer to the device
10592  * @sw_id: mirror rule's sw_id
10593  *
10594  * reset a mirror rule.
10595  *
10596  **/
10597 static int
10598 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10599 {
10600         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10601         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10602         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10603         uint16_t seid;
10604         int ret;
10605
10606         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10607
10608         seid = pf->main_vsi->veb->seid;
10609
10610         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10611                 if (sw_id == it->index) {
10612                         mirr_rule = it;
10613                         break;
10614                 }
10615         }
10616         if (mirr_rule) {
10617                 ret = i40e_aq_del_mirror_rule(hw, seid,
10618                                 mirr_rule->rule_type,
10619                                 mirr_rule->entries,
10620                                 mirr_rule->num_entries, mirr_rule->id);
10621                 if (ret < 0) {
10622                         PMD_DRV_LOG(ERR,
10623                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10624                                 ret, hw->aq.asq_last_status);
10625                         return -ENOSYS;
10626                 }
10627                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10628                 rte_free(mirr_rule);
10629                 pf->nb_mirror_rule--;
10630         } else {
10631                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10632                 return -ENOENT;
10633         }
10634         return 0;
10635 }
10636
10637 static uint64_t
10638 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10639 {
10640         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10641         uint64_t systim_cycles;
10642
10643         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10644         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10645                         << 32;
10646
10647         return systim_cycles;
10648 }
10649
10650 static uint64_t
10651 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10652 {
10653         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10654         uint64_t rx_tstamp;
10655
10656         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10657         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10658                         << 32;
10659
10660         return rx_tstamp;
10661 }
10662
10663 static uint64_t
10664 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10665 {
10666         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10667         uint64_t tx_tstamp;
10668
10669         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10670         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10671                         << 32;
10672
10673         return tx_tstamp;
10674 }
10675
10676 static void
10677 i40e_start_timecounters(struct rte_eth_dev *dev)
10678 {
10679         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10680         struct i40e_adapter *adapter =
10681                         (struct i40e_adapter *)dev->data->dev_private;
10682         struct rte_eth_link link;
10683         uint32_t tsync_inc_l;
10684         uint32_t tsync_inc_h;
10685
10686         /* Get current link speed. */
10687         i40e_dev_link_update(dev, 1);
10688         rte_eth_linkstatus_get(dev, &link);
10689
10690         switch (link.link_speed) {
10691         case ETH_SPEED_NUM_40G:
10692                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10693                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10694                 break;
10695         case ETH_SPEED_NUM_10G:
10696                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10697                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10698                 break;
10699         case ETH_SPEED_NUM_1G:
10700                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10701                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10702                 break;
10703         default:
10704                 tsync_inc_l = 0x0;
10705                 tsync_inc_h = 0x0;
10706         }
10707
10708         /* Set the timesync increment value. */
10709         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10710         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10711
10712         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10713         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10714         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10715
10716         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10717         adapter->systime_tc.cc_shift = 0;
10718         adapter->systime_tc.nsec_mask = 0;
10719
10720         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10721         adapter->rx_tstamp_tc.cc_shift = 0;
10722         adapter->rx_tstamp_tc.nsec_mask = 0;
10723
10724         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10725         adapter->tx_tstamp_tc.cc_shift = 0;
10726         adapter->tx_tstamp_tc.nsec_mask = 0;
10727 }
10728
10729 static int
10730 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10731 {
10732         struct i40e_adapter *adapter =
10733                         (struct i40e_adapter *)dev->data->dev_private;
10734
10735         adapter->systime_tc.nsec += delta;
10736         adapter->rx_tstamp_tc.nsec += delta;
10737         adapter->tx_tstamp_tc.nsec += delta;
10738
10739         return 0;
10740 }
10741
10742 static int
10743 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10744 {
10745         uint64_t ns;
10746         struct i40e_adapter *adapter =
10747                         (struct i40e_adapter *)dev->data->dev_private;
10748
10749         ns = rte_timespec_to_ns(ts);
10750
10751         /* Set the timecounters to a new value. */
10752         adapter->systime_tc.nsec = ns;
10753         adapter->rx_tstamp_tc.nsec = ns;
10754         adapter->tx_tstamp_tc.nsec = ns;
10755
10756         return 0;
10757 }
10758
10759 static int
10760 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10761 {
10762         uint64_t ns, systime_cycles;
10763         struct i40e_adapter *adapter =
10764                         (struct i40e_adapter *)dev->data->dev_private;
10765
10766         systime_cycles = i40e_read_systime_cyclecounter(dev);
10767         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10768         *ts = rte_ns_to_timespec(ns);
10769
10770         return 0;
10771 }
10772
10773 static int
10774 i40e_timesync_enable(struct rte_eth_dev *dev)
10775 {
10776         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10777         uint32_t tsync_ctl_l;
10778         uint32_t tsync_ctl_h;
10779
10780         /* Stop the timesync system time. */
10781         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10782         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10783         /* Reset the timesync system time value. */
10784         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10785         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10786
10787         i40e_start_timecounters(dev);
10788
10789         /* Clear timesync registers. */
10790         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10791         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10792         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10793         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10794         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10795         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10796
10797         /* Enable timestamping of PTP packets. */
10798         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10799         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10800
10801         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10802         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10803         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10804
10805         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10806         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10807
10808         return 0;
10809 }
10810
10811 static int
10812 i40e_timesync_disable(struct rte_eth_dev *dev)
10813 {
10814         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10815         uint32_t tsync_ctl_l;
10816         uint32_t tsync_ctl_h;
10817
10818         /* Disable timestamping of transmitted PTP packets. */
10819         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10820         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10821
10822         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10823         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10824
10825         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10826         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10827
10828         /* Reset the timesync increment value. */
10829         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10830         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10831
10832         return 0;
10833 }
10834
10835 static int
10836 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10837                                 struct timespec *timestamp, uint32_t flags)
10838 {
10839         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10840         struct i40e_adapter *adapter =
10841                 (struct i40e_adapter *)dev->data->dev_private;
10842
10843         uint32_t sync_status;
10844         uint32_t index = flags & 0x03;
10845         uint64_t rx_tstamp_cycles;
10846         uint64_t ns;
10847
10848         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10849         if ((sync_status & (1 << index)) == 0)
10850                 return -EINVAL;
10851
10852         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10853         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10854         *timestamp = rte_ns_to_timespec(ns);
10855
10856         return 0;
10857 }
10858
10859 static int
10860 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10861                                 struct timespec *timestamp)
10862 {
10863         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10864         struct i40e_adapter *adapter =
10865                 (struct i40e_adapter *)dev->data->dev_private;
10866
10867         uint32_t sync_status;
10868         uint64_t tx_tstamp_cycles;
10869         uint64_t ns;
10870
10871         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10872         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10873                 return -EINVAL;
10874
10875         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10876         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10877         *timestamp = rte_ns_to_timespec(ns);
10878
10879         return 0;
10880 }
10881
10882 /*
10883  * i40e_parse_dcb_configure - parse dcb configure from user
10884  * @dev: the device being configured
10885  * @dcb_cfg: pointer of the result of parse
10886  * @*tc_map: bit map of enabled traffic classes
10887  *
10888  * Returns 0 on success, negative value on failure
10889  */
10890 static int
10891 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10892                          struct i40e_dcbx_config *dcb_cfg,
10893                          uint8_t *tc_map)
10894 {
10895         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10896         uint8_t i, tc_bw, bw_lf;
10897
10898         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10899
10900         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10901         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10902                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10903                 return -EINVAL;
10904         }
10905
10906         /* assume each tc has the same bw */
10907         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10908         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10909                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10910         /* to ensure the sum of tcbw is equal to 100 */
10911         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10912         for (i = 0; i < bw_lf; i++)
10913                 dcb_cfg->etscfg.tcbwtable[i]++;
10914
10915         /* assume each tc has the same Transmission Selection Algorithm */
10916         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10917                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10918
10919         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10920                 dcb_cfg->etscfg.prioritytable[i] =
10921                                 dcb_rx_conf->dcb_tc[i];
10922
10923         /* FW needs one App to configure HW */
10924         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10925         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10926         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10927         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10928
10929         if (dcb_rx_conf->nb_tcs == 0)
10930                 *tc_map = 1; /* tc0 only */
10931         else
10932                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10933
10934         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10935                 dcb_cfg->pfc.willing = 0;
10936                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10937                 dcb_cfg->pfc.pfcenable = *tc_map;
10938         }
10939         return 0;
10940 }
10941
10942
10943 static enum i40e_status_code
10944 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10945                               struct i40e_aqc_vsi_properties_data *info,
10946                               uint8_t enabled_tcmap)
10947 {
10948         enum i40e_status_code ret;
10949         int i, total_tc = 0;
10950         uint16_t qpnum_per_tc, bsf, qp_idx;
10951         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10952         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10953         uint16_t used_queues;
10954
10955         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10956         if (ret != I40E_SUCCESS)
10957                 return ret;
10958
10959         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10960                 if (enabled_tcmap & (1 << i))
10961                         total_tc++;
10962         }
10963         if (total_tc == 0)
10964                 total_tc = 1;
10965         vsi->enabled_tc = enabled_tcmap;
10966
10967         /* different VSI has different queues assigned */
10968         if (vsi->type == I40E_VSI_MAIN)
10969                 used_queues = dev_data->nb_rx_queues -
10970                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10971         else if (vsi->type == I40E_VSI_VMDQ2)
10972                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10973         else {
10974                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10975                 return I40E_ERR_NO_AVAILABLE_VSI;
10976         }
10977
10978         qpnum_per_tc = used_queues / total_tc;
10979         /* Number of queues per enabled TC */
10980         if (qpnum_per_tc == 0) {
10981                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10982                 return I40E_ERR_INVALID_QP_ID;
10983         }
10984         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10985                                 I40E_MAX_Q_PER_TC);
10986         bsf = rte_bsf32(qpnum_per_tc);
10987
10988         /**
10989          * Configure TC and queue mapping parameters, for enabled TC,
10990          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10991          * default queue will serve it.
10992          */
10993         qp_idx = 0;
10994         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10995                 if (vsi->enabled_tc & (1 << i)) {
10996                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10997                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10998                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10999                         qp_idx += qpnum_per_tc;
11000                 } else
11001                         info->tc_mapping[i] = 0;
11002         }
11003
11004         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11005         if (vsi->type == I40E_VSI_SRIOV) {
11006                 info->mapping_flags |=
11007                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11008                 for (i = 0; i < vsi->nb_qps; i++)
11009                         info->queue_mapping[i] =
11010                                 rte_cpu_to_le_16(vsi->base_queue + i);
11011         } else {
11012                 info->mapping_flags |=
11013                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11014                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11015         }
11016         info->valid_sections |=
11017                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11018
11019         return I40E_SUCCESS;
11020 }
11021
11022 /*
11023  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11024  * @veb: VEB to be configured
11025  * @tc_map: enabled TC bitmap
11026  *
11027  * Returns 0 on success, negative value on failure
11028  */
11029 static enum i40e_status_code
11030 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11031 {
11032         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11033         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11034         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11035         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11036         enum i40e_status_code ret = I40E_SUCCESS;
11037         int i;
11038         uint32_t bw_max;
11039
11040         /* Check if enabled_tc is same as existing or new TCs */
11041         if (veb->enabled_tc == tc_map)
11042                 return ret;
11043
11044         /* configure tc bandwidth */
11045         memset(&veb_bw, 0, sizeof(veb_bw));
11046         veb_bw.tc_valid_bits = tc_map;
11047         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11048         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11049                 if (tc_map & BIT_ULL(i))
11050                         veb_bw.tc_bw_share_credits[i] = 1;
11051         }
11052         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11053                                                    &veb_bw, NULL);
11054         if (ret) {
11055                 PMD_INIT_LOG(ERR,
11056                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11057                         hw->aq.asq_last_status);
11058                 return ret;
11059         }
11060
11061         memset(&ets_query, 0, sizeof(ets_query));
11062         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11063                                                    &ets_query, NULL);
11064         if (ret != I40E_SUCCESS) {
11065                 PMD_DRV_LOG(ERR,
11066                         "Failed to get switch_comp ETS configuration %u",
11067                         hw->aq.asq_last_status);
11068                 return ret;
11069         }
11070         memset(&bw_query, 0, sizeof(bw_query));
11071         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11072                                                   &bw_query, NULL);
11073         if (ret != I40E_SUCCESS) {
11074                 PMD_DRV_LOG(ERR,
11075                         "Failed to get switch_comp bandwidth configuration %u",
11076                         hw->aq.asq_last_status);
11077                 return ret;
11078         }
11079
11080         /* store and print out BW info */
11081         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11082         veb->bw_info.bw_max = ets_query.tc_bw_max;
11083         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11084         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11085         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11086                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11087                      I40E_16_BIT_WIDTH);
11088         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11089                 veb->bw_info.bw_ets_share_credits[i] =
11090                                 bw_query.tc_bw_share_credits[i];
11091                 veb->bw_info.bw_ets_credits[i] =
11092                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11093                 /* 4 bits per TC, 4th bit is reserved */
11094                 veb->bw_info.bw_ets_max[i] =
11095                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11096                                   RTE_LEN2MASK(3, uint8_t));
11097                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11098                             veb->bw_info.bw_ets_share_credits[i]);
11099                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11100                             veb->bw_info.bw_ets_credits[i]);
11101                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11102                             veb->bw_info.bw_ets_max[i]);
11103         }
11104
11105         veb->enabled_tc = tc_map;
11106
11107         return ret;
11108 }
11109
11110
11111 /*
11112  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11113  * @vsi: VSI to be configured
11114  * @tc_map: enabled TC bitmap
11115  *
11116  * Returns 0 on success, negative value on failure
11117  */
11118 static enum i40e_status_code
11119 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11120 {
11121         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11122         struct i40e_vsi_context ctxt;
11123         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11124         enum i40e_status_code ret = I40E_SUCCESS;
11125         int i;
11126
11127         /* Check if enabled_tc is same as existing or new TCs */
11128         if (vsi->enabled_tc == tc_map)
11129                 return ret;
11130
11131         /* configure tc bandwidth */
11132         memset(&bw_data, 0, sizeof(bw_data));
11133         bw_data.tc_valid_bits = tc_map;
11134         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11135         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11136                 if (tc_map & BIT_ULL(i))
11137                         bw_data.tc_bw_credits[i] = 1;
11138         }
11139         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11140         if (ret) {
11141                 PMD_INIT_LOG(ERR,
11142                         "AQ command Config VSI BW allocation per TC failed = %d",
11143                         hw->aq.asq_last_status);
11144                 goto out;
11145         }
11146         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11147                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11148
11149         /* Update Queue Pairs Mapping for currently enabled UPs */
11150         ctxt.seid = vsi->seid;
11151         ctxt.pf_num = hw->pf_id;
11152         ctxt.vf_num = 0;
11153         ctxt.uplink_seid = vsi->uplink_seid;
11154         ctxt.info = vsi->info;
11155         i40e_get_cap(hw);
11156         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11157         if (ret)
11158                 goto out;
11159
11160         /* Update the VSI after updating the VSI queue-mapping information */
11161         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11162         if (ret) {
11163                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11164                         hw->aq.asq_last_status);
11165                 goto out;
11166         }
11167         /* update the local VSI info with updated queue map */
11168         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11169                                         sizeof(vsi->info.tc_mapping));
11170         rte_memcpy(&vsi->info.queue_mapping,
11171                         &ctxt.info.queue_mapping,
11172                 sizeof(vsi->info.queue_mapping));
11173         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11174         vsi->info.valid_sections = 0;
11175
11176         /* query and update current VSI BW information */
11177         ret = i40e_vsi_get_bw_config(vsi);
11178         if (ret) {
11179                 PMD_INIT_LOG(ERR,
11180                          "Failed updating vsi bw info, err %s aq_err %s",
11181                          i40e_stat_str(hw, ret),
11182                          i40e_aq_str(hw, hw->aq.asq_last_status));
11183                 goto out;
11184         }
11185
11186         vsi->enabled_tc = tc_map;
11187
11188 out:
11189         return ret;
11190 }
11191
11192 /*
11193  * i40e_dcb_hw_configure - program the dcb setting to hw
11194  * @pf: pf the configuration is taken on
11195  * @new_cfg: new configuration
11196  * @tc_map: enabled TC bitmap
11197  *
11198  * Returns 0 on success, negative value on failure
11199  */
11200 static enum i40e_status_code
11201 i40e_dcb_hw_configure(struct i40e_pf *pf,
11202                       struct i40e_dcbx_config *new_cfg,
11203                       uint8_t tc_map)
11204 {
11205         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11206         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11207         struct i40e_vsi *main_vsi = pf->main_vsi;
11208         struct i40e_vsi_list *vsi_list;
11209         enum i40e_status_code ret;
11210         int i;
11211         uint32_t val;
11212
11213         /* Use the FW API if FW > v4.4*/
11214         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11215               (hw->aq.fw_maj_ver >= 5))) {
11216                 PMD_INIT_LOG(ERR,
11217                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11218                 return I40E_ERR_FIRMWARE_API_VERSION;
11219         }
11220
11221         /* Check if need reconfiguration */
11222         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11223                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11224                 return I40E_SUCCESS;
11225         }
11226
11227         /* Copy the new config to the current config */
11228         *old_cfg = *new_cfg;
11229         old_cfg->etsrec = old_cfg->etscfg;
11230         ret = i40e_set_dcb_config(hw);
11231         if (ret) {
11232                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11233                          i40e_stat_str(hw, ret),
11234                          i40e_aq_str(hw, hw->aq.asq_last_status));
11235                 return ret;
11236         }
11237         /* set receive Arbiter to RR mode and ETS scheme by default */
11238         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11239                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11240                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11241                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11242                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11243                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11244                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11245                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11246                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11247                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11248                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11249                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11250                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11251         }
11252         /* get local mib to check whether it is configured correctly */
11253         /* IEEE mode */
11254         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11255         /* Get Local DCB Config */
11256         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11257                                      &hw->local_dcbx_config);
11258
11259         /* if Veb is created, need to update TC of it at first */
11260         if (main_vsi->veb) {
11261                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11262                 if (ret)
11263                         PMD_INIT_LOG(WARNING,
11264                                  "Failed configuring TC for VEB seid=%d",
11265                                  main_vsi->veb->seid);
11266         }
11267         /* Update each VSI */
11268         i40e_vsi_config_tc(main_vsi, tc_map);
11269         if (main_vsi->veb) {
11270                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11271                         /* Beside main VSI and VMDQ VSIs, only enable default
11272                          * TC for other VSIs
11273                          */
11274                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11275                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11276                                                          tc_map);
11277                         else
11278                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11279                                                          I40E_DEFAULT_TCMAP);
11280                         if (ret)
11281                                 PMD_INIT_LOG(WARNING,
11282                                         "Failed configuring TC for VSI seid=%d",
11283                                         vsi_list->vsi->seid);
11284                         /* continue */
11285                 }
11286         }
11287         return I40E_SUCCESS;
11288 }
11289
11290 /*
11291  * i40e_dcb_init_configure - initial dcb config
11292  * @dev: device being configured
11293  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11294  *
11295  * Returns 0 on success, negative value on failure
11296  */
11297 int
11298 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11299 {
11300         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11301         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11302         int i, ret = 0;
11303
11304         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11305                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11306                 return -ENOTSUP;
11307         }
11308
11309         /* DCB initialization:
11310          * Update DCB configuration from the Firmware and configure
11311          * LLDP MIB change event.
11312          */
11313         if (sw_dcb == TRUE) {
11314                 /* When using NVM 6.01 or later, the RX data path does
11315                  * not hang if the FW LLDP is stopped.
11316                  */
11317                 if (((hw->nvm.version >> 12) & 0xf) >= 6 &&
11318                     ((hw->nvm.version >> 4) & 0xff) >= 1) {
11319                         ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11320                         if (ret != I40E_SUCCESS)
11321                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11322                 }
11323
11324                 ret = i40e_init_dcb(hw);
11325                 /* If lldp agent is stopped, the return value from
11326                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11327                  * adminq status. Otherwise, it should return success.
11328                  */
11329                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11330                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11331                         memset(&hw->local_dcbx_config, 0,
11332                                 sizeof(struct i40e_dcbx_config));
11333                         /* set dcb default configuration */
11334                         hw->local_dcbx_config.etscfg.willing = 0;
11335                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11336                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11337                         hw->local_dcbx_config.etscfg.tsatable[0] =
11338                                                 I40E_IEEE_TSA_ETS;
11339                         /* all UPs mapping to TC0 */
11340                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11341                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11342                         hw->local_dcbx_config.etsrec =
11343                                 hw->local_dcbx_config.etscfg;
11344                         hw->local_dcbx_config.pfc.willing = 0;
11345                         hw->local_dcbx_config.pfc.pfccap =
11346                                                 I40E_MAX_TRAFFIC_CLASS;
11347                         /* FW needs one App to configure HW */
11348                         hw->local_dcbx_config.numapps = 1;
11349                         hw->local_dcbx_config.app[0].selector =
11350                                                 I40E_APP_SEL_ETHTYPE;
11351                         hw->local_dcbx_config.app[0].priority = 3;
11352                         hw->local_dcbx_config.app[0].protocolid =
11353                                                 I40E_APP_PROTOID_FCOE;
11354                         ret = i40e_set_dcb_config(hw);
11355                         if (ret) {
11356                                 PMD_INIT_LOG(ERR,
11357                                         "default dcb config fails. err = %d, aq_err = %d.",
11358                                         ret, hw->aq.asq_last_status);
11359                                 return -ENOSYS;
11360                         }
11361                 } else {
11362                         PMD_INIT_LOG(ERR,
11363                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11364                                 ret, hw->aq.asq_last_status);
11365                         return -ENOTSUP;
11366                 }
11367         } else {
11368                 ret = i40e_aq_start_lldp(hw, NULL);
11369                 if (ret != I40E_SUCCESS)
11370                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11371
11372                 ret = i40e_init_dcb(hw);
11373                 if (!ret) {
11374                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11375                                 PMD_INIT_LOG(ERR,
11376                                         "HW doesn't support DCBX offload.");
11377                                 return -ENOTSUP;
11378                         }
11379                 } else {
11380                         PMD_INIT_LOG(ERR,
11381                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11382                                 ret, hw->aq.asq_last_status);
11383                         return -ENOTSUP;
11384                 }
11385         }
11386         return 0;
11387 }
11388
11389 /*
11390  * i40e_dcb_setup - setup dcb related config
11391  * @dev: device being configured
11392  *
11393  * Returns 0 on success, negative value on failure
11394  */
11395 static int
11396 i40e_dcb_setup(struct rte_eth_dev *dev)
11397 {
11398         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11399         struct i40e_dcbx_config dcb_cfg;
11400         uint8_t tc_map = 0;
11401         int ret = 0;
11402
11403         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11404                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11405                 return -ENOTSUP;
11406         }
11407
11408         if (pf->vf_num != 0)
11409                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11410
11411         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11412         if (ret) {
11413                 PMD_INIT_LOG(ERR, "invalid dcb config");
11414                 return -EINVAL;
11415         }
11416         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11417         if (ret) {
11418                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11419                 return -ENOSYS;
11420         }
11421
11422         return 0;
11423 }
11424
11425 static int
11426 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11427                       struct rte_eth_dcb_info *dcb_info)
11428 {
11429         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11430         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11431         struct i40e_vsi *vsi = pf->main_vsi;
11432         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11433         uint16_t bsf, tc_mapping;
11434         int i, j = 0;
11435
11436         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11437                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11438         else
11439                 dcb_info->nb_tcs = 1;
11440         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11441                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11442         for (i = 0; i < dcb_info->nb_tcs; i++)
11443                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11444
11445         /* get queue mapping if vmdq is disabled */
11446         if (!pf->nb_cfg_vmdq_vsi) {
11447                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11448                         if (!(vsi->enabled_tc & (1 << i)))
11449                                 continue;
11450                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11451                         dcb_info->tc_queue.tc_rxq[j][i].base =
11452                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11453                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11454                         dcb_info->tc_queue.tc_txq[j][i].base =
11455                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11456                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11457                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11458                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11459                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11460                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11461                 }
11462                 return 0;
11463         }
11464
11465         /* get queue mapping if vmdq is enabled */
11466         do {
11467                 vsi = pf->vmdq[j].vsi;
11468                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11469                         if (!(vsi->enabled_tc & (1 << i)))
11470                                 continue;
11471                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11472                         dcb_info->tc_queue.tc_rxq[j][i].base =
11473                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11474                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11475                         dcb_info->tc_queue.tc_txq[j][i].base =
11476                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11477                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11478                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11479                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11480                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11481                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11482                 }
11483                 j++;
11484         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11485         return 0;
11486 }
11487
11488 static int
11489 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11490 {
11491         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11492         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11493         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11494         uint16_t msix_intr;
11495
11496         msix_intr = intr_handle->intr_vec[queue_id];
11497         if (msix_intr == I40E_MISC_VEC_ID)
11498                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11499                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11500                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11501                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11502         else
11503                 I40E_WRITE_REG(hw,
11504                                I40E_PFINT_DYN_CTLN(msix_intr -
11505                                                    I40E_RX_VEC_START),
11506                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11507                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11508                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11509
11510         I40E_WRITE_FLUSH(hw);
11511         rte_intr_enable(&pci_dev->intr_handle);
11512
11513         return 0;
11514 }
11515
11516 static int
11517 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11518 {
11519         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11520         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11521         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11522         uint16_t msix_intr;
11523
11524         msix_intr = intr_handle->intr_vec[queue_id];
11525         if (msix_intr == I40E_MISC_VEC_ID)
11526                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11527                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11528         else
11529                 I40E_WRITE_REG(hw,
11530                                I40E_PFINT_DYN_CTLN(msix_intr -
11531                                                    I40E_RX_VEC_START),
11532                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11533         I40E_WRITE_FLUSH(hw);
11534
11535         return 0;
11536 }
11537
11538 static int i40e_get_regs(struct rte_eth_dev *dev,
11539                          struct rte_dev_reg_info *regs)
11540 {
11541         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11542         uint32_t *ptr_data = regs->data;
11543         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11544         const struct i40e_reg_info *reg_info;
11545
11546         if (ptr_data == NULL) {
11547                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11548                 regs->width = sizeof(uint32_t);
11549                 return 0;
11550         }
11551
11552         /* The first few registers have to be read using AQ operations */
11553         reg_idx = 0;
11554         while (i40e_regs_adminq[reg_idx].name) {
11555                 reg_info = &i40e_regs_adminq[reg_idx++];
11556                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11557                         for (arr_idx2 = 0;
11558                                         arr_idx2 <= reg_info->count2;
11559                                         arr_idx2++) {
11560                                 reg_offset = arr_idx * reg_info->stride1 +
11561                                         arr_idx2 * reg_info->stride2;
11562                                 reg_offset += reg_info->base_addr;
11563                                 ptr_data[reg_offset >> 2] =
11564                                         i40e_read_rx_ctl(hw, reg_offset);
11565                         }
11566         }
11567
11568         /* The remaining registers can be read using primitives */
11569         reg_idx = 0;
11570         while (i40e_regs_others[reg_idx].name) {
11571                 reg_info = &i40e_regs_others[reg_idx++];
11572                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11573                         for (arr_idx2 = 0;
11574                                         arr_idx2 <= reg_info->count2;
11575                                         arr_idx2++) {
11576                                 reg_offset = arr_idx * reg_info->stride1 +
11577                                         arr_idx2 * reg_info->stride2;
11578                                 reg_offset += reg_info->base_addr;
11579                                 ptr_data[reg_offset >> 2] =
11580                                         I40E_READ_REG(hw, reg_offset);
11581                         }
11582         }
11583
11584         return 0;
11585 }
11586
11587 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11588 {
11589         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11590
11591         /* Convert word count to byte count */
11592         return hw->nvm.sr_size << 1;
11593 }
11594
11595 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11596                            struct rte_dev_eeprom_info *eeprom)
11597 {
11598         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11599         uint16_t *data = eeprom->data;
11600         uint16_t offset, length, cnt_words;
11601         int ret_code;
11602
11603         offset = eeprom->offset >> 1;
11604         length = eeprom->length >> 1;
11605         cnt_words = length;
11606
11607         if (offset > hw->nvm.sr_size ||
11608                 offset + length > hw->nvm.sr_size) {
11609                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11610                 return -EINVAL;
11611         }
11612
11613         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11614
11615         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11616         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11617                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11618                 return -EIO;
11619         }
11620
11621         return 0;
11622 }
11623
11624 static int i40e_get_module_info(struct rte_eth_dev *dev,
11625                                 struct rte_eth_dev_module_info *modinfo)
11626 {
11627         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11628         uint32_t sff8472_comp = 0;
11629         uint32_t sff8472_swap = 0;
11630         uint32_t sff8636_rev = 0;
11631         i40e_status status;
11632         uint32_t type = 0;
11633
11634         /* Check if firmware supports reading module EEPROM. */
11635         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11636                 PMD_DRV_LOG(ERR,
11637                             "Module EEPROM memory read not supported. "
11638                             "Please update the NVM image.\n");
11639                 return -EINVAL;
11640         }
11641
11642         status = i40e_update_link_info(hw);
11643         if (status)
11644                 return -EIO;
11645
11646         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11647                 PMD_DRV_LOG(ERR,
11648                             "Cannot read module EEPROM memory. "
11649                             "No module connected.\n");
11650                 return -EINVAL;
11651         }
11652
11653         type = hw->phy.link_info.module_type[0];
11654
11655         switch (type) {
11656         case I40E_MODULE_TYPE_SFP:
11657                 status = i40e_aq_get_phy_register(hw,
11658                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11659                                 I40E_I2C_EEPROM_DEV_ADDR,
11660                                 I40E_MODULE_SFF_8472_COMP,
11661                                 &sff8472_comp, NULL);
11662                 if (status)
11663                         return -EIO;
11664
11665                 status = i40e_aq_get_phy_register(hw,
11666                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11667                                 I40E_I2C_EEPROM_DEV_ADDR,
11668                                 I40E_MODULE_SFF_8472_SWAP,
11669                                 &sff8472_swap, NULL);
11670                 if (status)
11671                         return -EIO;
11672
11673                 /* Check if the module requires address swap to access
11674                  * the other EEPROM memory page.
11675                  */
11676                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11677                         PMD_DRV_LOG(WARNING,
11678                                     "Module address swap to access "
11679                                     "page 0xA2 is not supported.\n");
11680                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11681                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11682                 } else if (sff8472_comp == 0x00) {
11683                         /* Module is not SFF-8472 compliant */
11684                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11685                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11686                 } else {
11687                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11688                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11689                 }
11690                 break;
11691         case I40E_MODULE_TYPE_QSFP_PLUS:
11692                 /* Read from memory page 0. */
11693                 status = i40e_aq_get_phy_register(hw,
11694                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11695                                 0,
11696                                 I40E_MODULE_REVISION_ADDR,
11697                                 &sff8636_rev, NULL);
11698                 if (status)
11699                         return -EIO;
11700                 /* Determine revision compliance byte */
11701                 if (sff8636_rev > 0x02) {
11702                         /* Module is SFF-8636 compliant */
11703                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11704                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11705                 } else {
11706                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11707                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11708                 }
11709                 break;
11710         case I40E_MODULE_TYPE_QSFP28:
11711                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11712                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11713                 break;
11714         default:
11715                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11716                 return -EINVAL;
11717         }
11718         return 0;
11719 }
11720
11721 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11722                                   struct rte_dev_eeprom_info *info)
11723 {
11724         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11725         bool is_sfp = false;
11726         i40e_status status;
11727         uint8_t *data = info->data;
11728         uint32_t value = 0;
11729         uint32_t i;
11730
11731         if (!info || !info->length || !data)
11732                 return -EINVAL;
11733
11734         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11735                 is_sfp = true;
11736
11737         for (i = 0; i < info->length; i++) {
11738                 u32 offset = i + info->offset;
11739                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11740
11741                 /* Check if we need to access the other memory page */
11742                 if (is_sfp) {
11743                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11744                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11745                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11746                         }
11747                 } else {
11748                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11749                                 /* Compute memory page number and offset. */
11750                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11751                                 addr++;
11752                         }
11753                 }
11754                 status = i40e_aq_get_phy_register(hw,
11755                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11756                                 addr, offset, &value, NULL);
11757                 if (status)
11758                         return -EIO;
11759                 data[i] = (uint8_t)value;
11760         }
11761         return 0;
11762 }
11763
11764 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11765                                      struct ether_addr *mac_addr)
11766 {
11767         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11768         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11769         struct i40e_vsi *vsi = pf->main_vsi;
11770         struct i40e_mac_filter_info mac_filter;
11771         struct i40e_mac_filter *f;
11772         int ret;
11773
11774         if (!is_valid_assigned_ether_addr(mac_addr)) {
11775                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11776                 return -EINVAL;
11777         }
11778
11779         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11780                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11781                         break;
11782         }
11783
11784         if (f == NULL) {
11785                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11786                 return -EIO;
11787         }
11788
11789         mac_filter = f->mac_info;
11790         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11791         if (ret != I40E_SUCCESS) {
11792                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11793                 return -EIO;
11794         }
11795         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11796         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11797         if (ret != I40E_SUCCESS) {
11798                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11799                 return -EIO;
11800         }
11801         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11802
11803         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11804                                         mac_addr->addr_bytes, NULL);
11805         if (ret != I40E_SUCCESS) {
11806                 PMD_DRV_LOG(ERR, "Failed to change mac");
11807                 return -EIO;
11808         }
11809
11810         return 0;
11811 }
11812
11813 static int
11814 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11815 {
11816         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11817         struct rte_eth_dev_data *dev_data = pf->dev_data;
11818         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11819         int ret = 0;
11820
11821         /* check if mtu is within the allowed range */
11822         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11823                 return -EINVAL;
11824
11825         /* mtu setting is forbidden if port is start */
11826         if (dev_data->dev_started) {
11827                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11828                             dev_data->port_id);
11829                 return -EBUSY;
11830         }
11831
11832         if (frame_size > ETHER_MAX_LEN)
11833                 dev_data->dev_conf.rxmode.offloads |=
11834                         DEV_RX_OFFLOAD_JUMBO_FRAME;
11835         else
11836                 dev_data->dev_conf.rxmode.offloads &=
11837                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11838
11839         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11840
11841         return ret;
11842 }
11843
11844 /* Restore ethertype filter */
11845 static void
11846 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11847 {
11848         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11849         struct i40e_ethertype_filter_list
11850                 *ethertype_list = &pf->ethertype.ethertype_list;
11851         struct i40e_ethertype_filter *f;
11852         struct i40e_control_filter_stats stats;
11853         uint16_t flags;
11854
11855         TAILQ_FOREACH(f, ethertype_list, rules) {
11856                 flags = 0;
11857                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11858                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11859                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11860                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11861                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11862
11863                 memset(&stats, 0, sizeof(stats));
11864                 i40e_aq_add_rem_control_packet_filter(hw,
11865                                             f->input.mac_addr.addr_bytes,
11866                                             f->input.ether_type,
11867                                             flags, pf->main_vsi->seid,
11868                                             f->queue, 1, &stats, NULL);
11869         }
11870         PMD_DRV_LOG(INFO, "Ethertype filter:"
11871                     " mac_etype_used = %u, etype_used = %u,"
11872                     " mac_etype_free = %u, etype_free = %u",
11873                     stats.mac_etype_used, stats.etype_used,
11874                     stats.mac_etype_free, stats.etype_free);
11875 }
11876
11877 /* Restore tunnel filter */
11878 static void
11879 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11880 {
11881         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11882         struct i40e_vsi *vsi;
11883         struct i40e_pf_vf *vf;
11884         struct i40e_tunnel_filter_list
11885                 *tunnel_list = &pf->tunnel.tunnel_list;
11886         struct i40e_tunnel_filter *f;
11887         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11888         bool big_buffer = 0;
11889
11890         TAILQ_FOREACH(f, tunnel_list, rules) {
11891                 if (!f->is_to_vf)
11892                         vsi = pf->main_vsi;
11893                 else {
11894                         vf = &pf->vfs[f->vf_id];
11895                         vsi = vf->vsi;
11896                 }
11897                 memset(&cld_filter, 0, sizeof(cld_filter));
11898                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11899                         (struct ether_addr *)&cld_filter.element.outer_mac);
11900                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11901                         (struct ether_addr *)&cld_filter.element.inner_mac);
11902                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11903                 cld_filter.element.flags = f->input.flags;
11904                 cld_filter.element.tenant_id = f->input.tenant_id;
11905                 cld_filter.element.queue_number = f->queue;
11906                 rte_memcpy(cld_filter.general_fields,
11907                            f->input.general_fields,
11908                            sizeof(f->input.general_fields));
11909
11910                 if (((f->input.flags &
11911                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11912                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11913                     ((f->input.flags &
11914                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11915                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11916                     ((f->input.flags &
11917                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11918                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11919                         big_buffer = 1;
11920
11921                 if (big_buffer)
11922                         i40e_aq_add_cloud_filters_big_buffer(hw,
11923                                              vsi->seid, &cld_filter, 1);
11924                 else
11925                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11926                                                   &cld_filter.element, 1);
11927         }
11928 }
11929
11930 /* Restore rss filter */
11931 static inline void
11932 i40e_rss_filter_restore(struct i40e_pf *pf)
11933 {
11934         struct i40e_rte_flow_rss_conf *conf =
11935                                         &pf->rss_info;
11936         if (conf->conf.queue_num)
11937                 i40e_config_rss_filter(pf, conf, TRUE);
11938 }
11939
11940 static void
11941 i40e_filter_restore(struct i40e_pf *pf)
11942 {
11943         i40e_ethertype_filter_restore(pf);
11944         i40e_tunnel_filter_restore(pf);
11945         i40e_fdir_filter_restore(pf);
11946         i40e_rss_filter_restore(pf);
11947 }
11948
11949 static bool
11950 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11951 {
11952         if (strcmp(dev->device->driver->name, drv->driver.name))
11953                 return false;
11954
11955         return true;
11956 }
11957
11958 bool
11959 is_i40e_supported(struct rte_eth_dev *dev)
11960 {
11961         return is_device_supported(dev, &rte_i40e_pmd);
11962 }
11963
11964 struct i40e_customized_pctype*
11965 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11966 {
11967         int i;
11968
11969         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11970                 if (pf->customized_pctype[i].index == index)
11971                         return &pf->customized_pctype[i];
11972         }
11973         return NULL;
11974 }
11975
11976 static int
11977 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11978                               uint32_t pkg_size, uint32_t proto_num,
11979                               struct rte_pmd_i40e_proto_info *proto,
11980                               enum rte_pmd_i40e_package_op op)
11981 {
11982         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11983         uint32_t pctype_num;
11984         struct rte_pmd_i40e_ptype_info *pctype;
11985         uint32_t buff_size;
11986         struct i40e_customized_pctype *new_pctype = NULL;
11987         uint8_t proto_id;
11988         uint8_t pctype_value;
11989         char name[64];
11990         uint32_t i, j, n;
11991         int ret;
11992
11993         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11994             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11995                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11996                 return -1;
11997         }
11998
11999         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12000                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12001                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12002         if (ret) {
12003                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12004                 return -1;
12005         }
12006         if (!pctype_num) {
12007                 PMD_DRV_LOG(INFO, "No new pctype added");
12008                 return -1;
12009         }
12010
12011         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12012         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12013         if (!pctype) {
12014                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12015                 return -1;
12016         }
12017         /* get information about new pctype list */
12018         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12019                                         (uint8_t *)pctype, buff_size,
12020                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12021         if (ret) {
12022                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12023                 rte_free(pctype);
12024                 return -1;
12025         }
12026
12027         /* Update customized pctype. */
12028         for (i = 0; i < pctype_num; i++) {
12029                 pctype_value = pctype[i].ptype_id;
12030                 memset(name, 0, sizeof(name));
12031                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12032                         proto_id = pctype[i].protocols[j];
12033                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12034                                 continue;
12035                         for (n = 0; n < proto_num; n++) {
12036                                 if (proto[n].proto_id != proto_id)
12037                                         continue;
12038                                 strcat(name, proto[n].name);
12039                                 strcat(name, "_");
12040                                 break;
12041                         }
12042                 }
12043                 name[strlen(name) - 1] = '\0';
12044                 if (!strcmp(name, "GTPC"))
12045                         new_pctype =
12046                                 i40e_find_customized_pctype(pf,
12047                                                       I40E_CUSTOMIZED_GTPC);
12048                 else if (!strcmp(name, "GTPU_IPV4"))
12049                         new_pctype =
12050                                 i40e_find_customized_pctype(pf,
12051                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12052                 else if (!strcmp(name, "GTPU_IPV6"))
12053                         new_pctype =
12054                                 i40e_find_customized_pctype(pf,
12055                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12056                 else if (!strcmp(name, "GTPU"))
12057                         new_pctype =
12058                                 i40e_find_customized_pctype(pf,
12059                                                       I40E_CUSTOMIZED_GTPU);
12060                 if (new_pctype) {
12061                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12062                                 new_pctype->pctype = pctype_value;
12063                                 new_pctype->valid = true;
12064                         } else {
12065                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12066                                 new_pctype->valid = false;
12067                         }
12068                 }
12069         }
12070
12071         rte_free(pctype);
12072         return 0;
12073 }
12074
12075 static int
12076 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12077                              uint32_t pkg_size, uint32_t proto_num,
12078                              struct rte_pmd_i40e_proto_info *proto,
12079                              enum rte_pmd_i40e_package_op op)
12080 {
12081         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12082         uint16_t port_id = dev->data->port_id;
12083         uint32_t ptype_num;
12084         struct rte_pmd_i40e_ptype_info *ptype;
12085         uint32_t buff_size;
12086         uint8_t proto_id;
12087         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12088         uint32_t i, j, n;
12089         bool in_tunnel;
12090         int ret;
12091
12092         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12093             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12094                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12095                 return -1;
12096         }
12097
12098         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12099                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12100                 return 0;
12101         }
12102
12103         /* get information about new ptype num */
12104         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12105                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12106                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12107         if (ret) {
12108                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12109                 return ret;
12110         }
12111         if (!ptype_num) {
12112                 PMD_DRV_LOG(INFO, "No new ptype added");
12113                 return -1;
12114         }
12115
12116         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12117         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12118         if (!ptype) {
12119                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12120                 return -1;
12121         }
12122
12123         /* get information about new ptype list */
12124         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12125                                         (uint8_t *)ptype, buff_size,
12126                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12127         if (ret) {
12128                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12129                 rte_free(ptype);
12130                 return ret;
12131         }
12132
12133         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12134         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12135         if (!ptype_mapping) {
12136                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12137                 rte_free(ptype);
12138                 return -1;
12139         }
12140
12141         /* Update ptype mapping table. */
12142         for (i = 0; i < ptype_num; i++) {
12143                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12144                 ptype_mapping[i].sw_ptype = 0;
12145                 in_tunnel = false;
12146                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12147                         proto_id = ptype[i].protocols[j];
12148                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12149                                 continue;
12150                         for (n = 0; n < proto_num; n++) {
12151                                 if (proto[n].proto_id != proto_id)
12152                                         continue;
12153                                 memset(name, 0, sizeof(name));
12154                                 strcpy(name, proto[n].name);
12155                                 if (!strncasecmp(name, "PPPOE", 5))
12156                                         ptype_mapping[i].sw_ptype |=
12157                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12158                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12159                                          !in_tunnel) {
12160                                         ptype_mapping[i].sw_ptype |=
12161                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12162                                         ptype_mapping[i].sw_ptype |=
12163                                                 RTE_PTYPE_L4_FRAG;
12164                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12165                                            in_tunnel) {
12166                                         ptype_mapping[i].sw_ptype |=
12167                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12168                                         ptype_mapping[i].sw_ptype |=
12169                                                 RTE_PTYPE_INNER_L4_FRAG;
12170                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12171                                         ptype_mapping[i].sw_ptype |=
12172                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12173                                         in_tunnel = true;
12174                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12175                                            !in_tunnel)
12176                                         ptype_mapping[i].sw_ptype |=
12177                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12178                                 else if (!strncasecmp(name, "IPV4", 4) &&
12179                                          in_tunnel)
12180                                         ptype_mapping[i].sw_ptype |=
12181                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12182                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12183                                          !in_tunnel) {
12184                                         ptype_mapping[i].sw_ptype |=
12185                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12186                                         ptype_mapping[i].sw_ptype |=
12187                                                 RTE_PTYPE_L4_FRAG;
12188                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12189                                            in_tunnel) {
12190                                         ptype_mapping[i].sw_ptype |=
12191                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12192                                         ptype_mapping[i].sw_ptype |=
12193                                                 RTE_PTYPE_INNER_L4_FRAG;
12194                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12195                                         ptype_mapping[i].sw_ptype |=
12196                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12197                                         in_tunnel = true;
12198                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12199                                            !in_tunnel)
12200                                         ptype_mapping[i].sw_ptype |=
12201                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12202                                 else if (!strncasecmp(name, "IPV6", 4) &&
12203                                          in_tunnel)
12204                                         ptype_mapping[i].sw_ptype |=
12205                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12206                                 else if (!strncasecmp(name, "UDP", 3) &&
12207                                          !in_tunnel)
12208                                         ptype_mapping[i].sw_ptype |=
12209                                                 RTE_PTYPE_L4_UDP;
12210                                 else if (!strncasecmp(name, "UDP", 3) &&
12211                                          in_tunnel)
12212                                         ptype_mapping[i].sw_ptype |=
12213                                                 RTE_PTYPE_INNER_L4_UDP;
12214                                 else if (!strncasecmp(name, "TCP", 3) &&
12215                                          !in_tunnel)
12216                                         ptype_mapping[i].sw_ptype |=
12217                                                 RTE_PTYPE_L4_TCP;
12218                                 else if (!strncasecmp(name, "TCP", 3) &&
12219                                          in_tunnel)
12220                                         ptype_mapping[i].sw_ptype |=
12221                                                 RTE_PTYPE_INNER_L4_TCP;
12222                                 else if (!strncasecmp(name, "SCTP", 4) &&
12223                                          !in_tunnel)
12224                                         ptype_mapping[i].sw_ptype |=
12225                                                 RTE_PTYPE_L4_SCTP;
12226                                 else if (!strncasecmp(name, "SCTP", 4) &&
12227                                          in_tunnel)
12228                                         ptype_mapping[i].sw_ptype |=
12229                                                 RTE_PTYPE_INNER_L4_SCTP;
12230                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12231                                           !strncasecmp(name, "ICMPV6", 6)) &&
12232                                          !in_tunnel)
12233                                         ptype_mapping[i].sw_ptype |=
12234                                                 RTE_PTYPE_L4_ICMP;
12235                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12236                                           !strncasecmp(name, "ICMPV6", 6)) &&
12237                                          in_tunnel)
12238                                         ptype_mapping[i].sw_ptype |=
12239                                                 RTE_PTYPE_INNER_L4_ICMP;
12240                                 else if (!strncasecmp(name, "GTPC", 4)) {
12241                                         ptype_mapping[i].sw_ptype |=
12242                                                 RTE_PTYPE_TUNNEL_GTPC;
12243                                         in_tunnel = true;
12244                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12245                                         ptype_mapping[i].sw_ptype |=
12246                                                 RTE_PTYPE_TUNNEL_GTPU;
12247                                         in_tunnel = true;
12248                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12249                                         ptype_mapping[i].sw_ptype |=
12250                                                 RTE_PTYPE_TUNNEL_GRENAT;
12251                                         in_tunnel = true;
12252                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12253                                            !strncasecmp(name, "L2TPV2", 6)) {
12254                                         ptype_mapping[i].sw_ptype |=
12255                                                 RTE_PTYPE_TUNNEL_L2TP;
12256                                         in_tunnel = true;
12257                                 }
12258
12259                                 break;
12260                         }
12261                 }
12262         }
12263
12264         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12265                                                 ptype_num, 0);
12266         if (ret)
12267                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12268
12269         rte_free(ptype_mapping);
12270         rte_free(ptype);
12271         return ret;
12272 }
12273
12274 void
12275 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12276                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12277 {
12278         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12279         uint32_t proto_num;
12280         struct rte_pmd_i40e_proto_info *proto;
12281         uint32_t buff_size;
12282         uint32_t i;
12283         int ret;
12284
12285         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12286             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12287                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12288                 return;
12289         }
12290
12291         /* get information about protocol number */
12292         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12293                                        (uint8_t *)&proto_num, sizeof(proto_num),
12294                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12295         if (ret) {
12296                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12297                 return;
12298         }
12299         if (!proto_num) {
12300                 PMD_DRV_LOG(INFO, "No new protocol added");
12301                 return;
12302         }
12303
12304         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12305         proto = rte_zmalloc("new_proto", buff_size, 0);
12306         if (!proto) {
12307                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12308                 return;
12309         }
12310
12311         /* get information about protocol list */
12312         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12313                                         (uint8_t *)proto, buff_size,
12314                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12315         if (ret) {
12316                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12317                 rte_free(proto);
12318                 return;
12319         }
12320
12321         /* Check if GTP is supported. */
12322         for (i = 0; i < proto_num; i++) {
12323                 if (!strncmp(proto[i].name, "GTP", 3)) {
12324                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12325                                 pf->gtp_support = true;
12326                         else
12327                                 pf->gtp_support = false;
12328                         break;
12329                 }
12330         }
12331
12332         /* Update customized pctype info */
12333         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12334                                             proto_num, proto, op);
12335         if (ret)
12336                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12337
12338         /* Update customized ptype info */
12339         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12340                                            proto_num, proto, op);
12341         if (ret)
12342                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12343
12344         rte_free(proto);
12345 }
12346
12347 /* Create a QinQ cloud filter
12348  *
12349  * The Fortville NIC has limited resources for tunnel filters,
12350  * so we can only reuse existing filters.
12351  *
12352  * In step 1 we define which Field Vector fields can be used for
12353  * filter types.
12354  * As we do not have the inner tag defined as a field,
12355  * we have to define it first, by reusing one of L1 entries.
12356  *
12357  * In step 2 we are replacing one of existing filter types with
12358  * a new one for QinQ.
12359  * As we reusing L1 and replacing L2, some of the default filter
12360  * types will disappear,which depends on L1 and L2 entries we reuse.
12361  *
12362  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12363  *
12364  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12365  *              later when we define the cloud filter.
12366  *      a.      Valid_flags.replace_cloud = 0
12367  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12368  *      c.      New_filter = 0x10
12369  *      d.      TR bit = 0xff (optional, not used here)
12370  *      e.      Buffer – 2 entries:
12371  *              i.      Byte 0 = 8 (outer vlan FV index).
12372  *                      Byte 1 = 0 (rsv)
12373  *                      Byte 2-3 = 0x0fff
12374  *              ii.     Byte 0 = 37 (inner vlan FV index).
12375  *                      Byte 1 =0 (rsv)
12376  *                      Byte 2-3 = 0x0fff
12377  *
12378  * Step 2:
12379  * 2.   Create cloud filter using two L1 filters entries: stag and
12380  *              new filter(outer vlan+ inner vlan)
12381  *      a.      Valid_flags.replace_cloud = 1
12382  *      b.      Old_filter = 1 (instead of outer IP)
12383  *      c.      New_filter = 0x10
12384  *      d.      Buffer – 2 entries:
12385  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12386  *                      Byte 1-3 = 0 (rsv)
12387  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12388  *                      Byte 9-11 = 0 (rsv)
12389  */
12390 static int
12391 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12392 {
12393         int ret = -ENOTSUP;
12394         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12395         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12396         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12397         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12398
12399         if (pf->support_multi_driver) {
12400                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12401                 return ret;
12402         }
12403
12404         /* Init */
12405         memset(&filter_replace, 0,
12406                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12407         memset(&filter_replace_buf, 0,
12408                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12409
12410         /* create L1 filter */
12411         filter_replace.old_filter_type =
12412                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12413         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12414         filter_replace.tr_bit = 0;
12415
12416         /* Prepare the buffer, 2 entries */
12417         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12418         filter_replace_buf.data[0] |=
12419                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12420         /* Field Vector 12b mask */
12421         filter_replace_buf.data[2] = 0xff;
12422         filter_replace_buf.data[3] = 0x0f;
12423         filter_replace_buf.data[4] =
12424                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12425         filter_replace_buf.data[4] |=
12426                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12427         /* Field Vector 12b mask */
12428         filter_replace_buf.data[6] = 0xff;
12429         filter_replace_buf.data[7] = 0x0f;
12430         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12431                         &filter_replace_buf);
12432         if (ret != I40E_SUCCESS)
12433                 return ret;
12434
12435         if (filter_replace.old_filter_type !=
12436             filter_replace.new_filter_type)
12437                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12438                             " original: 0x%x, new: 0x%x",
12439                             dev->device->name,
12440                             filter_replace.old_filter_type,
12441                             filter_replace.new_filter_type);
12442
12443         /* Apply the second L2 cloud filter */
12444         memset(&filter_replace, 0,
12445                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12446         memset(&filter_replace_buf, 0,
12447                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12448
12449         /* create L2 filter, input for L2 filter will be L1 filter  */
12450         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12451         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12452         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12453
12454         /* Prepare the buffer, 2 entries */
12455         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12456         filter_replace_buf.data[0] |=
12457                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12458         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12459         filter_replace_buf.data[4] |=
12460                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12461         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12462                         &filter_replace_buf);
12463         if (!ret && (filter_replace.old_filter_type !=
12464                      filter_replace.new_filter_type))
12465                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12466                             " original: 0x%x, new: 0x%x",
12467                             dev->device->name,
12468                             filter_replace.old_filter_type,
12469                             filter_replace.new_filter_type);
12470
12471         return ret;
12472 }
12473
12474 int
12475 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12476                    const struct rte_flow_action_rss *in)
12477 {
12478         if (in->key_len > RTE_DIM(out->key) ||
12479             in->queue_num > RTE_DIM(out->queue))
12480                 return -EINVAL;
12481         out->conf = (struct rte_flow_action_rss){
12482                 .func = in->func,
12483                 .level = in->level,
12484                 .types = in->types,
12485                 .key_len = in->key_len,
12486                 .queue_num = in->queue_num,
12487                 .key = memcpy(out->key, in->key, in->key_len),
12488                 .queue = memcpy(out->queue, in->queue,
12489                                 sizeof(*in->queue) * in->queue_num),
12490         };
12491         return 0;
12492 }
12493
12494 int
12495 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12496                      const struct rte_flow_action_rss *with)
12497 {
12498         return (comp->func == with->func &&
12499                 comp->level == with->level &&
12500                 comp->types == with->types &&
12501                 comp->key_len == with->key_len &&
12502                 comp->queue_num == with->queue_num &&
12503                 !memcmp(comp->key, with->key, with->key_len) &&
12504                 !memcmp(comp->queue, with->queue,
12505                         sizeof(*with->queue) * with->queue_num));
12506 }
12507
12508 int
12509 i40e_config_rss_filter(struct i40e_pf *pf,
12510                 struct i40e_rte_flow_rss_conf *conf, bool add)
12511 {
12512         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12513         uint32_t i, lut = 0;
12514         uint16_t j, num;
12515         struct rte_eth_rss_conf rss_conf = {
12516                 .rss_key = conf->conf.key_len ?
12517                         (void *)(uintptr_t)conf->conf.key : NULL,
12518                 .rss_key_len = conf->conf.key_len,
12519                 .rss_hf = conf->conf.types,
12520         };
12521         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12522
12523         if (!add) {
12524                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12525                         i40e_pf_disable_rss(pf);
12526                         memset(rss_info, 0,
12527                                 sizeof(struct i40e_rte_flow_rss_conf));
12528                         return 0;
12529                 }
12530                 return -EINVAL;
12531         }
12532
12533         if (rss_info->conf.queue_num)
12534                 return -EINVAL;
12535
12536         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12537          * It's necessary to calculate the actual PF queues that are configured.
12538          */
12539         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12540                 num = i40e_pf_calc_configured_queues_num(pf);
12541         else
12542                 num = pf->dev_data->nb_rx_queues;
12543
12544         num = RTE_MIN(num, conf->conf.queue_num);
12545         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12546                         num);
12547
12548         if (num == 0) {
12549                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12550                 return -ENOTSUP;
12551         }
12552
12553         /* Fill in redirection table */
12554         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12555                 if (j == num)
12556                         j = 0;
12557                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12558                         hw->func_caps.rss_table_entry_width) - 1));
12559                 if ((i & 3) == 3)
12560                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12561         }
12562
12563         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12564                 i40e_pf_disable_rss(pf);
12565                 return 0;
12566         }
12567         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12568                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12569                 /* Random default keys */
12570                 static uint32_t rss_key_default[] = {0x6b793944,
12571                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12572                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12573                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12574
12575                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12576                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12577                                                         sizeof(uint32_t);
12578         }
12579
12580         i40e_hw_rss_hash_set(pf, &rss_conf);
12581
12582         if (i40e_rss_conf_init(rss_info, &conf->conf))
12583                 return -EINVAL;
12584
12585         return 0;
12586 }
12587
12588 RTE_INIT(i40e_init_log)
12589 {
12590         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12591         if (i40e_logtype_init >= 0)
12592                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12593         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12594         if (i40e_logtype_driver >= 0)
12595                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12596 }
12597
12598 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12599                               ETH_I40E_FLOATING_VEB_ARG "=1"
12600                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12601                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12602                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");