drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  47 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  48
  49 #define I40E_CLEAR_PXE_WAIT_MS     200
  50
  51 /* Maximun number of capability elements */
  52 #define I40E_MAX_CAP_ELE_NUM       128
  53
  54 /* Wait count and interval */
  55 #define I40E_CHK_Q_ENA_COUNT       1000
  56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  57
  58 /* Maximun number of VSI */
  59 #define I40E_MAX_NUM_VSIS          (384UL)
  60
  61 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  62
  63 /* Flow control default timer */
  64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  65
  66 /* Flow control enable fwd bit */
  67 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  68
  69 /* Receive Packet Buffer size */
  70 #define I40E_RXPBSIZE (968 * 1024)
  71
  72 /* Kilobytes shift */
  73 #define I40E_KILOSHIFT 10
  74
  75 /* Flow control default high water */
  76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Flow control default low water */
  79 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  80
  81 /* Receive Average Packet Size in Byte*/
  82 #define I40E_PACKET_AVERAGE_SIZE 128
  83
  84 /* Mask of PF interrupt causes */
  85 #define I40E_PFINT_ICR0_ENA_MASK ( \
  86                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  87                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  90                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 /* Additional timesync values. */
 110 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 111 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 112 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 113 #define I40E_PRTTSYN_TSYNENA     0x80000000
 114 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 115 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 116
 117 /**
 118  * Below are values for writing un-exposed registers suggested
 119  * by silicon experts
 120  */
 121 /* Destination MAC address */
 122 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 123 /* Source MAC address */
 124 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 126 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 128 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 129 /* Single VLAN tag in the inner L2 header */
 130 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 131 /* Source IPv4 address */
 132 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 133 /* Destination IPv4 address */
 134 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 135 /* Source IPv4 address for X722 */
 136 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 137 /* Destination IPv4 address for X722 */
 138 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 139 /* IPv4 Protocol for X722 */
 140 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 141 /* IPv4 Time to Live for X722 */
 142 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 143 /* IPv4 Type of Service (TOS) */
 144 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 145 /* IPv4 Protocol */
 146 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 147 /* IPv4 Time to Live */
 148 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 149 /* Source IPv6 address */
 150 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 151 /* Destination IPv6 address */
 152 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 153 /* IPv6 Traffic Class (TC) */
 154 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 155 /* IPv6 Next Header */
 156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 157 /* IPv6 Hop Limit */
 158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 159 /* Source L4 port */
 160 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 161 /* Destination L4 port */
 162 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 163 /* SCTP verification tag */
 164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 167 /* Source port of tunneling UDP */
 168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 169 /* Destination port of tunneling UDP */
 170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 171 /* UDP Tunneling ID, NVGRE/GRE key */
 172 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 173 /* Last ether type */
 174 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 175 /* Tunneling outer destination IPv4 address */
 176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 177 /* Tunneling outer destination IPv6 address */
 178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 179 /* 1st word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 181 /* 2nd word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 183 /* 3rd word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 185 /* 4th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 187 /* 5th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 189 /* 6th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 191 /* 7th word of flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 193 /* 8th word of flex payload */
 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 195 /* all 8 words flex payload */
 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 197 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 198
 199 #define I40E_TRANSLATE_INSET 0
 200 #define I40E_TRANSLATE_REG   1
 201
 202 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 203 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 204 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 205 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 207 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 208
 209 /* PCI offset for querying capability */
 210 #define PCI_DEV_CAP_REG            0xA4
 211 /* PCI offset for enabling/disabling Extended Tag */
 212 #define PCI_DEV_CTRL_REG           0xA8
 213 /* Bit mask of Extended Tag capability */
 214 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 215 /* Bit shift of Extended Tag enable/disable */
 216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 217 /* Bit mask of Extended Tag enable/disable */
 218 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 219
 220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 222 static int i40e_dev_configure(struct rte_eth_dev *dev);
 223 static int i40e_dev_start(struct rte_eth_dev *dev);
 224 static void i40e_dev_stop(struct rte_eth_dev *dev);
 225 static void i40e_dev_close(struct rte_eth_dev *dev);
 226 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 227 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 228 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 229 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 230 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 234                                struct rte_eth_stats *stats);
 235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 236                                struct rte_eth_xstat *xstats, unsigned n);
 237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 238                                      struct rte_eth_xstat_name *xstats_names,
 239                                      unsigned limit);
 240 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 244                              struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct rte_ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static void i40e_dev_alarm_handler(void *param);
 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 294                                 uint32_t base, uint32_t num);
 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 297                         uint32_t base);
 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 299                         uint16_t num);
 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 301 static int i40e_veb_release(struct i40e_veb *veb);
 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 303                                                 struct i40e_vsi *vsi);
 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static int i40e_get_module_info(struct rte_eth_dev *dev,
 374                                 struct rte_eth_dev_module_info *modinfo);
 375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 376                                   struct rte_dev_eeprom_info *info);
 377
 378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 379                                       struct rte_ether_addr *mac_addr);
 380
 381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 382
 383 static int i40e_ethertype_filter_convert(
 384         const struct rte_eth_ethertype_filter *input,
 385         struct i40e_ethertype_filter *filter);
 386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 387                                    struct i40e_ethertype_filter *filter);
 388
 389 static int i40e_tunnel_filter_convert(
 390         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 391         struct i40e_tunnel_filter *tunnel_filter);
 392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 393                                 struct i40e_tunnel_filter *tunnel_filter);
 394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 395
 396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 398 static void i40e_filter_restore(struct i40e_pf *pf);
 399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 400
 401 int i40e_logtype_init;
 402 int i40e_logtype_driver;
 403
 404 static const char *const valid_keys[] = {
 405         ETH_I40E_FLOATING_VEB_ARG,
 406         ETH_I40E_FLOATING_VEB_LIST_ARG,
 407         ETH_I40E_SUPPORT_MULTI_DRIVER,
 408         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 409         ETH_I40E_USE_LATEST_VEC,
 410         ETH_I40E_VF_MSG_CFG,
 411         NULL};
 412
 413 static const struct rte_pci_id pci_id_i40e_map[] = {
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 437         { .vendor_id = 0, /* sentinel */ },
 438 };
 439
 440 static const struct eth_dev_ops i40e_eth_dev_ops = {
 441         .dev_configure                = i40e_dev_configure,
 442         .dev_start                    = i40e_dev_start,
 443         .dev_stop                     = i40e_dev_stop,
 444         .dev_close                    = i40e_dev_close,
 445         .dev_reset                    = i40e_dev_reset,
 446         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 447         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 448         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 449         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 450         .dev_set_link_up              = i40e_dev_set_link_up,
 451         .dev_set_link_down            = i40e_dev_set_link_down,
 452         .link_update                  = i40e_dev_link_update,
 453         .stats_get                    = i40e_dev_stats_get,
 454         .xstats_get                   = i40e_dev_xstats_get,
 455         .xstats_get_names             = i40e_dev_xstats_get_names,
 456         .stats_reset                  = i40e_dev_stats_reset,
 457         .xstats_reset                 = i40e_dev_stats_reset,
 458         .fw_version_get               = i40e_fw_version_get,
 459         .dev_infos_get                = i40e_dev_info_get,
 460         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 461         .vlan_filter_set              = i40e_vlan_filter_set,
 462         .vlan_tpid_set                = i40e_vlan_tpid_set,
 463         .vlan_offload_set             = i40e_vlan_offload_set,
 464         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 465         .vlan_pvid_set                = i40e_vlan_pvid_set,
 466         .rx_queue_start               = i40e_dev_rx_queue_start,
 467         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 468         .tx_queue_start               = i40e_dev_tx_queue_start,
 469         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 470         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 471         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 472         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 473         .rx_queue_release             = i40e_dev_rx_queue_release,
 474         .rx_queue_count               = i40e_dev_rx_queue_count,
 475         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 476         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 477         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 478         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 479         .tx_queue_release             = i40e_dev_tx_queue_release,
 480         .dev_led_on                   = i40e_dev_led_on,
 481         .dev_led_off                  = i40e_dev_led_off,
 482         .flow_ctrl_get                = i40e_flow_ctrl_get,
 483         .flow_ctrl_set                = i40e_flow_ctrl_set,
 484         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 485         .mac_addr_add                 = i40e_macaddr_add,
 486         .mac_addr_remove              = i40e_macaddr_remove,
 487         .reta_update                  = i40e_dev_rss_reta_update,
 488         .reta_query                   = i40e_dev_rss_reta_query,
 489         .rss_hash_update              = i40e_dev_rss_hash_update,
 490         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 491         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 492         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 493         .filter_ctrl                  = i40e_dev_filter_ctrl,
 494         .rxq_info_get                 = i40e_rxq_info_get,
 495         .txq_info_get                 = i40e_txq_info_get,
 496         .mirror_rule_set              = i40e_mirror_rule_set,
 497         .mirror_rule_reset            = i40e_mirror_rule_reset,
 498         .timesync_enable              = i40e_timesync_enable,
 499         .timesync_disable             = i40e_timesync_disable,
 500         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 501         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 502         .get_dcb_info                 = i40e_dev_get_dcb_info,
 503         .timesync_adjust_time         = i40e_timesync_adjust_time,
 504         .timesync_read_time           = i40e_timesync_read_time,
 505         .timesync_write_time          = i40e_timesync_write_time,
 506         .get_reg                      = i40e_get_regs,
 507         .get_eeprom_length            = i40e_get_eeprom_length,
 508         .get_eeprom                   = i40e_get_eeprom,
 509         .get_module_info              = i40e_get_module_info,
 510         .get_module_eeprom            = i40e_get_module_eeprom,
 511         .mac_addr_set                 = i40e_set_default_mac_addr,
 512         .mtu_set                      = i40e_dev_mtu_set,
 513         .tm_ops_get                   = i40e_tm_ops_get,
 514 };
 515
 516 /* store statistics names and its offset in stats structure */
 517 struct rte_i40e_xstats_name_off {
 518         char name[RTE_ETH_XSTATS_NAME_SIZE];
 519         unsigned offset;
 520 };
 521
 522 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 523         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 524         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 525         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 526         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 527         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 528                 rx_unknown_protocol)},
 529         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 530         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 531         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 532         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 533 };
 534
 535 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 536                 sizeof(rte_i40e_stats_strings[0]))
 537
 538 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 539         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 540                 tx_dropped_link_down)},
 541         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 542         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 543                 illegal_bytes)},
 544         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 545         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 546                 mac_local_faults)},
 547         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 548                 mac_remote_faults)},
 549         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 550                 rx_length_errors)},
 551         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 552         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 553         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 554         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 555         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 556         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 557                 rx_size_127)},
 558         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 559                 rx_size_255)},
 560         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 561                 rx_size_511)},
 562         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_1023)},
 564         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_1522)},
 566         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_big)},
 568         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 569                 rx_undersize)},
 570         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 571                 rx_oversize)},
 572         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 573                 mac_short_packet_dropped)},
 574         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 575                 rx_fragments)},
 576         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 577         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 578         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 579                 tx_size_127)},
 580         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 581                 tx_size_255)},
 582         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 583                 tx_size_511)},
 584         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_1023)},
 586         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_1522)},
 588         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_big)},
 590         {"rx_flow_director_atr_match_packets",
 591                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 592         {"rx_flow_director_sb_match_packets",
 593                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 594         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 595                 tx_lpi_status)},
 596         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 597                 rx_lpi_status)},
 598         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 599                 tx_lpi_count)},
 600         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 601                 rx_lpi_count)},
 602 };
 603
 604 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 605                 sizeof(rte_i40e_hw_port_strings[0]))
 606
 607 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 608         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 609                 priority_xon_rx)},
 610         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 611                 priority_xoff_rx)},
 612 };
 613
 614 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 615                 sizeof(rte_i40e_rxq_prio_strings[0]))
 616
 617 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 618         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 619                 priority_xon_tx)},
 620         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 621                 priority_xoff_tx)},
 622         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xon_2_xoff)},
 624 };
 625
 626 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 627                 sizeof(rte_i40e_txq_prio_strings[0]))
 628
 629 static int
 630 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 631         struct rte_pci_device *pci_dev)
 632 {
 633         char name[RTE_ETH_NAME_MAX_LEN];
 634         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 635         int i, retval;
 636
 637         if (pci_dev->device.devargs) {
 638                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 639                                 &eth_da);
 640                 if (retval)
 641                         return retval;
 642         }
 643
 644         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 645                 sizeof(struct i40e_adapter),
 646                 eth_dev_pci_specific_init, pci_dev,
 647                 eth_i40e_dev_init, NULL);
 648
 649         if (retval || eth_da.nb_representor_ports < 1)
 650                 return retval;
 651
 652         /* probe VF representor ports */
 653         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 654                 pci_dev->device.name);
 655
 656         if (pf_ethdev == NULL)
 657                 return -ENODEV;
 658
 659         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 660                 struct i40e_vf_representor representor = {
 661                         .vf_id = eth_da.representor_ports[i],
 662                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 663                                 pf_ethdev->data->dev_private)->switch_domain_id,
 664                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 665                                 pf_ethdev->data->dev_private)
 666                 };
 667
 668                 /* representor port net_bdf_port */
 669                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 670                         pci_dev->device.name, eth_da.representor_ports[i]);
 671
 672                 retval = rte_eth_dev_create(&pci_dev->device, name,
 673                         sizeof(struct i40e_vf_representor), NULL, NULL,
 674                         i40e_vf_representor_init, &representor);
 675
 676                 if (retval)
 677                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 678                                 "representor %s.", name);
 679         }
 680
 681         return 0;
 682 }
 683
 684 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 685 {
 686         struct rte_eth_dev *ethdev;
 687
 688         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 689         if (!ethdev)
 690                 return -ENODEV;
 691
 692
 693         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 694                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 695         else
 696                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 697 }
 698
 699 static struct rte_pci_driver rte_i40e_pmd = {
 700         .id_table = pci_id_i40e_map,
 701         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 702         .probe = eth_i40e_pci_probe,
 703         .remove = eth_i40e_pci_remove,
 704 };
 705
 706 static inline void
 707 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 708                          uint32_t reg_val)
 709 {
 710         uint32_t ori_reg_val;
 711         struct rte_eth_dev *dev;
 712
 713         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 714         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 715         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 716         if (ori_reg_val != reg_val)
 717                 PMD_DRV_LOG(WARNING,
 718                             "i40e device %s changed global register [0x%08x]."
 719                             " original: 0x%08x, new: 0x%08x",
 720                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 721 }
 722
 723 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 724 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 725 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 726
 727 #ifndef I40E_GLQF_ORT
 728 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 729 #endif
 730 #ifndef I40E_GLQF_PIT
 731 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 732 #endif
 733 #ifndef I40E_GLQF_L3_MAP
 734 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 735 #endif
 736
 737 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 738 {
 739         /*
 740          * Initialize registers for parsing packet type of QinQ
 741          * This should be removed from code once proper
 742          * configuration API is added to avoid configuration conflicts
 743          * between ports of the same device.
 744          */
 745         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 746         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 747 }
 748
 749 static inline void i40e_config_automask(struct i40e_pf *pf)
 750 {
 751         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 752         uint32_t val;
 753
 754         /* INTENA flag is not auto-cleared for interrupt */
 755         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 756         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 757                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 758
 759         /* If support multi-driver, PF will use INT0. */
 760         if (!pf->support_multi_driver)
 761                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 762
 763         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 764 }
 765
 766 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 767
 768 /*
 769  * Add a ethertype filter to drop all flow control frames transmitted
 770  * from VSIs.
 771 */
 772 static void
 773 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 774 {
 775         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 776         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 777                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 778                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 779         int ret;
 780
 781         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 782                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 783                                 pf->main_vsi_seid, 0,
 784                                 TRUE, NULL, NULL);
 785         if (ret)
 786                 PMD_INIT_LOG(ERR,
 787                         "Failed to add filter to drop flow control frames from VSIs.");
 788 }
 789
 790 static int
 791 floating_veb_list_handler(__rte_unused const char *key,
 792                           const char *floating_veb_value,
 793                           void *opaque)
 794 {
 795         int idx = 0;
 796         unsigned int count = 0;
 797         char *end = NULL;
 798         int min, max;
 799         bool *vf_floating_veb = opaque;
 800
 801         while (isblank(*floating_veb_value))
 802                 floating_veb_value++;
 803
 804         /* Reset floating VEB configuration for VFs */
 805         for (idx = 0; idx < I40E_MAX_VF; idx++)
 806                 vf_floating_veb[idx] = false;
 807
 808         min = I40E_MAX_VF;
 809         do {
 810                 while (isblank(*floating_veb_value))
 811                         floating_veb_value++;
 812                 if (*floating_veb_value == '\0')
 813                         return -1;
 814                 errno = 0;
 815                 idx = strtoul(floating_veb_value, &end, 10);
 816                 if (errno || end == NULL)
 817                         return -1;
 818                 while (isblank(*end))
 819                         end++;
 820                 if (*end == '-') {
 821                         min = idx;
 822                 } else if ((*end == ';') || (*end == '\0')) {
 823                         max = idx;
 824                         if (min == I40E_MAX_VF)
 825                                 min = idx;
 826                         if (max >= I40E_MAX_VF)
 827                                 max = I40E_MAX_VF - 1;
 828                         for (idx = min; idx <= max; idx++) {
 829                                 vf_floating_veb[idx] = true;
 830                                 count++;
 831                         }
 832                         min = I40E_MAX_VF;
 833                 } else {
 834                         return -1;
 835                 }
 836                 floating_veb_value = end + 1;
 837         } while (*end != '\0');
 838
 839         if (count == 0)
 840                 return -1;
 841
 842         return 0;
 843 }
 844
 845 static void
 846 config_vf_floating_veb(struct rte_devargs *devargs,
 847                        uint16_t floating_veb,
 848                        bool *vf_floating_veb)
 849 {
 850         struct rte_kvargs *kvlist;
 851         int i;
 852         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 853
 854         if (!floating_veb)
 855                 return;
 856         /* All the VFs attach to the floating VEB by default
 857          * when the floating VEB is enabled.
 858          */
 859         for (i = 0; i < I40E_MAX_VF; i++)
 860                 vf_floating_veb[i] = true;
 861
 862         if (devargs == NULL)
 863                 return;
 864
 865         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 866         if (kvlist == NULL)
 867                 return;
 868
 869         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 870                 rte_kvargs_free(kvlist);
 871                 return;
 872         }
 873         /* When the floating_veb_list parameter exists, all the VFs
 874          * will attach to the legacy VEB firstly, then configure VFs
 875          * to the floating VEB according to the floating_veb_list.
 876          */
 877         if (rte_kvargs_process(kvlist, floating_veb_list,
 878                                floating_veb_list_handler,
 879                                vf_floating_veb) < 0) {
 880                 rte_kvargs_free(kvlist);
 881                 return;
 882         }
 883         rte_kvargs_free(kvlist);
 884 }
 885
 886 static int
 887 i40e_check_floating_handler(__rte_unused const char *key,
 888                             const char *value,
 889                             __rte_unused void *opaque)
 890 {
 891         if (strcmp(value, "1"))
 892                 return -1;
 893
 894         return 0;
 895 }
 896
 897 static int
 898 is_floating_veb_supported(struct rte_devargs *devargs)
 899 {
 900         struct rte_kvargs *kvlist;
 901         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 902
 903         if (devargs == NULL)
 904                 return 0;
 905
 906         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 907         if (kvlist == NULL)
 908                 return 0;
 909
 910         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 911                 rte_kvargs_free(kvlist);
 912                 return 0;
 913         }
 914         /* Floating VEB is enabled when there's key-value:
 915          * enable_floating_veb=1
 916          */
 917         if (rte_kvargs_process(kvlist, floating_veb_key,
 918                                i40e_check_floating_handler, NULL) < 0) {
 919                 rte_kvargs_free(kvlist);
 920                 return 0;
 921         }
 922         rte_kvargs_free(kvlist);
 923
 924         return 1;
 925 }
 926
 927 static void
 928 config_floating_veb(struct rte_eth_dev *dev)
 929 {
 930         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 931         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 933
 934         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 935
 936         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 937                 pf->floating_veb =
 938                         is_floating_veb_supported(pci_dev->device.devargs);
 939                 config_vf_floating_veb(pci_dev->device.devargs,
 940                                        pf->floating_veb,
 941                                        pf->floating_veb_list);
 942         } else {
 943                 pf->floating_veb = false;
 944         }
 945 }
 946
 947 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 948 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 949
 950 static int
 951 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 952 {
 953         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 954         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 955         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 956         int ret;
 957
 958         struct rte_hash_parameters ethertype_hash_params = {
 959                 .name = ethertype_hash_name,
 960                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 961                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 962                 .hash_func = rte_hash_crc,
 963                 .hash_func_init_val = 0,
 964                 .socket_id = rte_socket_id(),
 965         };
 966
 967         /* Initialize ethertype filter rule list and hash */
 968         TAILQ_INIT(&ethertype_rule->ethertype_list);
 969         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 970                  "ethertype_%s", dev->device->name);
 971         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 972         if (!ethertype_rule->hash_table) {
 973                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 974                 return -EINVAL;
 975         }
 976         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 977                                        sizeof(struct i40e_ethertype_filter *) *
 978                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 979                                        0);
 980         if (!ethertype_rule->hash_map) {
 981                 PMD_INIT_LOG(ERR,
 982                              "Failed to allocate memory for ethertype hash map!");
 983                 ret = -ENOMEM;
 984                 goto err_ethertype_hash_map_alloc;
 985         }
 986
 987         return 0;
 988
 989 err_ethertype_hash_map_alloc:
 990         rte_hash_free(ethertype_rule->hash_table);
 991
 992         return ret;
 993 }
 994
 995 static int
 996 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 997 {
 998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 999         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1000         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1001         int ret;
1002
1003         struct rte_hash_parameters tunnel_hash_params = {
1004                 .name = tunnel_hash_name,
1005                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1006                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1007                 .hash_func = rte_hash_crc,
1008                 .hash_func_init_val = 0,
1009                 .socket_id = rte_socket_id(),
1010         };
1011
1012         /* Initialize tunnel filter rule list and hash */
1013         TAILQ_INIT(&tunnel_rule->tunnel_list);
1014         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1015                  "tunnel_%s", dev->device->name);
1016         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1017         if (!tunnel_rule->hash_table) {
1018                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1019                 return -EINVAL;
1020         }
1021         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1022                                     sizeof(struct i40e_tunnel_filter *) *
1023                                     I40E_MAX_TUNNEL_FILTER_NUM,
1024                                     0);
1025         if (!tunnel_rule->hash_map) {
1026                 PMD_INIT_LOG(ERR,
1027                              "Failed to allocate memory for tunnel hash map!");
1028                 ret = -ENOMEM;
1029                 goto err_tunnel_hash_map_alloc;
1030         }
1031
1032         return 0;
1033
1034 err_tunnel_hash_map_alloc:
1035         rte_hash_free(tunnel_rule->hash_table);
1036
1037         return ret;
1038 }
1039
1040 static int
1041 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1042 {
1043         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1044         struct i40e_fdir_info *fdir_info = &pf->fdir;
1045         char fdir_hash_name[RTE_HASH_NAMESIZE];
1046         int ret;
1047
1048         struct rte_hash_parameters fdir_hash_params = {
1049                 .name = fdir_hash_name,
1050                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1051                 .key_len = sizeof(struct i40e_fdir_input),
1052                 .hash_func = rte_hash_crc,
1053                 .hash_func_init_val = 0,
1054                 .socket_id = rte_socket_id(),
1055         };
1056
1057         /* Initialize flow director filter rule list and hash */
1058         TAILQ_INIT(&fdir_info->fdir_list);
1059         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1060                  "fdir_%s", dev->device->name);
1061         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1062         if (!fdir_info->hash_table) {
1063                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1064                 return -EINVAL;
1065         }
1066         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1067                                           sizeof(struct i40e_fdir_filter *) *
1068                                           I40E_MAX_FDIR_FILTER_NUM,
1069                                           0);
1070         if (!fdir_info->hash_map) {
1071                 PMD_INIT_LOG(ERR,
1072                              "Failed to allocate memory for fdir hash map!");
1073                 ret = -ENOMEM;
1074                 goto err_fdir_hash_map_alloc;
1075         }
1076         return 0;
1077
1078 err_fdir_hash_map_alloc:
1079         rte_hash_free(fdir_info->hash_table);
1080
1081         return ret;
1082 }
1083
1084 static void
1085 i40e_init_customized_info(struct i40e_pf *pf)
1086 {
1087         int i;
1088
1089         /* Initialize customized pctype */
1090         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1091                 pf->customized_pctype[i].index = i;
1092                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1093                 pf->customized_pctype[i].valid = false;
1094         }
1095
1096         pf->gtp_support = false;
1097 }
1098
1099 void
1100 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1101 {
1102         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1103         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1104         struct i40e_queue_regions *info = &pf->queue_region;
1105         uint16_t i;
1106
1107         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1108                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1109
1110         memset(info, 0, sizeof(struct i40e_queue_regions));
1111 }
1112
1113 static int
1114 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1115                                const char *value,
1116                                void *opaque)
1117 {
1118         struct i40e_pf *pf;
1119         unsigned long support_multi_driver;
1120         char *end;
1121
1122         pf = (struct i40e_pf *)opaque;
1123
1124         errno = 0;
1125         support_multi_driver = strtoul(value, &end, 10);
1126         if (errno != 0 || end == value || *end != 0) {
1127                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1128                 return -(EINVAL);
1129         }
1130
1131         if (support_multi_driver == 1 || support_multi_driver == 0)
1132                 pf->support_multi_driver = (bool)support_multi_driver;
1133         else
1134                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1135                             "enable global configuration by default."
1136                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1137         return 0;
1138 }
1139
1140 static int
1141 i40e_support_multi_driver(struct rte_eth_dev *dev)
1142 {
1143         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1144         struct rte_kvargs *kvlist;
1145         int kvargs_count;
1146
1147         /* Enable global configuration by default */
1148         pf->support_multi_driver = false;
1149
1150         if (!dev->device->devargs)
1151                 return 0;
1152
1153         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1154         if (!kvlist)
1155                 return -EINVAL;
1156
1157         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1158         if (!kvargs_count) {
1159                 rte_kvargs_free(kvlist);
1160                 return 0;
1161         }
1162
1163         if (kvargs_count > 1)
1164                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1165                             "the first invalid or last valid one is used !",
1166                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1167
1168         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1169                                i40e_parse_multi_drv_handler, pf) < 0) {
1170                 rte_kvargs_free(kvlist);
1171                 return -EINVAL;
1172         }
1173
1174         rte_kvargs_free(kvlist);
1175         return 0;
1176 }
1177
1178 static int
1179 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1180                                     uint32_t reg_addr, uint64_t reg_val,
1181                                     struct i40e_asq_cmd_details *cmd_details)
1182 {
1183         uint64_t ori_reg_val;
1184         struct rte_eth_dev *dev;
1185         int ret;
1186
1187         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1188         if (ret != I40E_SUCCESS) {
1189                 PMD_DRV_LOG(ERR,
1190                             "Fail to debug read from 0x%08x",
1191                             reg_addr);
1192                 return -EIO;
1193         }
1194         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1195
1196         if (ori_reg_val != reg_val)
1197                 PMD_DRV_LOG(WARNING,
1198                             "i40e device %s changed global register [0x%08x]."
1199                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1200                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1201
1202         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1203 }
1204
1205 static int
1206 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1207                                 const char *value,
1208                                 void *opaque)
1209 {
1210         struct i40e_adapter *ad = opaque;
1211         int use_latest_vec;
1212
1213         use_latest_vec = atoi(value);
1214
1215         if (use_latest_vec != 0 && use_latest_vec != 1)
1216                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1217
1218         ad->use_latest_vec = (uint8_t)use_latest_vec;
1219
1220         return 0;
1221 }
1222
1223 static int
1224 i40e_use_latest_vec(struct rte_eth_dev *dev)
1225 {
1226         struct i40e_adapter *ad =
1227                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1228         struct rte_kvargs *kvlist;
1229         int kvargs_count;
1230
1231         ad->use_latest_vec = false;
1232
1233         if (!dev->device->devargs)
1234                 return 0;
1235
1236         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1237         if (!kvlist)
1238                 return -EINVAL;
1239
1240         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1241         if (!kvargs_count) {
1242                 rte_kvargs_free(kvlist);
1243                 return 0;
1244         }
1245
1246         if (kvargs_count > 1)
1247                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1248                             "the first invalid or last valid one is used !",
1249                             ETH_I40E_USE_LATEST_VEC);
1250
1251         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1252                                 i40e_parse_latest_vec_handler, ad) < 0) {
1253                 rte_kvargs_free(kvlist);
1254                 return -EINVAL;
1255         }
1256
1257         rte_kvargs_free(kvlist);
1258         return 0;
1259 }
1260
1261 static int
1262 read_vf_msg_config(__rte_unused const char *key,
1263                                const char *value,
1264                                void *opaque)
1265 {
1266         struct i40e_vf_msg_cfg *cfg = opaque;
1267
1268         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1269                         &cfg->ignore_second) != 3) {
1270                 memset(cfg, 0, sizeof(*cfg));
1271                 PMD_DRV_LOG(ERR, "format error! example: "
1272                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1273                 return -EINVAL;
1274         }
1275
1276         /*
1277          * If the message validation function been enabled, the 'period'
1278          * and 'ignore_second' must greater than 0.
1279          */
1280         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1281                 memset(cfg, 0, sizeof(*cfg));
1282                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1283                                 " number must be greater than 0!",
1284                                 ETH_I40E_VF_MSG_CFG);
1285                 return -EINVAL;
1286         }
1287
1288         return 0;
1289 }
1290
1291 static int
1292 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1293                 struct i40e_vf_msg_cfg *msg_cfg)
1294 {
1295         struct rte_kvargs *kvlist;
1296         int kvargs_count;
1297         int ret = 0;
1298
1299         memset(msg_cfg, 0, sizeof(*msg_cfg));
1300
1301         if (!dev->device->devargs)
1302                 return ret;
1303
1304         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1305         if (!kvlist)
1306                 return -EINVAL;
1307
1308         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1309         if (!kvargs_count)
1310                 goto free_end;
1311
1312         if (kvargs_count > 1) {
1313                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1314                                 ETH_I40E_VF_MSG_CFG);
1315                 ret = -EINVAL;
1316                 goto free_end;
1317         }
1318
1319         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1320                         read_vf_msg_config, msg_cfg) < 0)
1321                 ret = -EINVAL;
1322
1323 free_end:
1324         rte_kvargs_free(kvlist);
1325         return ret;
1326 }
1327
1328 #define I40E_ALARM_INTERVAL 50000 /* us */
1329
1330 static int
1331 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1332 {
1333         struct rte_pci_device *pci_dev;
1334         struct rte_intr_handle *intr_handle;
1335         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1336         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1337         struct i40e_vsi *vsi;
1338         int ret;
1339         uint32_t len, val;
1340         uint8_t aq_fail = 0;
1341
1342         PMD_INIT_FUNC_TRACE();
1343
1344         dev->dev_ops = &i40e_eth_dev_ops;
1345         dev->rx_pkt_burst = i40e_recv_pkts;
1346         dev->tx_pkt_burst = i40e_xmit_pkts;
1347         dev->tx_pkt_prepare = i40e_prep_pkts;
1348
1349         /* for secondary processes, we don't initialise any further as primary
1350          * has already done this work. Only check we don't need a different
1351          * RX function */
1352         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1353                 i40e_set_rx_function(dev);
1354                 i40e_set_tx_function(dev);
1355                 return 0;
1356         }
1357         i40e_set_default_ptype_table(dev);
1358         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1359         intr_handle = &pci_dev->intr_handle;
1360
1361         rte_eth_copy_pci_info(dev, pci_dev);
1362
1363         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1364         pf->adapter->eth_dev = dev;
1365         pf->dev_data = dev->data;
1366
1367         hw->back = I40E_PF_TO_ADAPTER(pf);
1368         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1369         if (!hw->hw_addr) {
1370                 PMD_INIT_LOG(ERR,
1371                         "Hardware is not available, as address is NULL");
1372                 return -ENODEV;
1373         }
1374
1375         hw->vendor_id = pci_dev->id.vendor_id;
1376         hw->device_id = pci_dev->id.device_id;
1377         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1378         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1379         hw->bus.device = pci_dev->addr.devid;
1380         hw->bus.func = pci_dev->addr.function;
1381         hw->adapter_stopped = 0;
1382         hw->adapter_closed = 0;
1383
1384         /*
1385          * Switch Tag value should not be identical to either the First Tag
1386          * or Second Tag values. So set something other than common Ethertype
1387          * for internal switching.
1388          */
1389         hw->switch_tag = 0xffff;
1390
1391         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1392         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1393                 PMD_INIT_LOG(ERR, "\nERROR: "
1394                         "Firmware recovery mode detected. Limiting functionality.\n"
1395                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1396                         "User Guide for details on firmware recovery mode.");
1397                 return -EIO;
1398         }
1399
1400         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1401         /* Check if need to support multi-driver */
1402         i40e_support_multi_driver(dev);
1403         /* Check if users want the latest supported vec path */
1404         i40e_use_latest_vec(dev);
1405
1406         /* Make sure all is clean before doing PF reset */
1407         i40e_clear_hw(hw);
1408
1409         /* Reset here to make sure all is clean for each PF */
1410         ret = i40e_pf_reset(hw);
1411         if (ret) {
1412                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1413                 return ret;
1414         }
1415
1416         /* Initialize the shared code (base driver) */
1417         ret = i40e_init_shared_code(hw);
1418         if (ret) {
1419                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1420                 return ret;
1421         }
1422
1423         /* Initialize the parameters for adminq */
1424         i40e_init_adminq_parameter(hw);
1425         ret = i40e_init_adminq(hw);
1426         if (ret != I40E_SUCCESS) {
1427                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1428                 return -EIO;
1429         }
1430         /* Firmware of SFP x722 does not support adminq option */
1431         if (hw->device_id == I40E_DEV_ID_SFP_X722)
1432                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1433
1434         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1435                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1436                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1437                      ((hw->nvm.version >> 12) & 0xf),
1438                      ((hw->nvm.version >> 4) & 0xff),
1439                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1440
1441         /* Initialize the hardware */
1442         i40e_hw_init(dev);
1443
1444         i40e_config_automask(pf);
1445
1446         i40e_set_default_pctype_table(dev);
1447
1448         /*
1449          * To work around the NVM issue, initialize registers
1450          * for packet type of QinQ by software.
1451          * It should be removed once issues are fixed in NVM.
1452          */
1453         if (!pf->support_multi_driver)
1454                 i40e_GLQF_reg_init(hw);
1455
1456         /* Initialize the input set for filters (hash and fd) to default value */
1457         i40e_filter_input_set_init(pf);
1458
1459         /* initialise the L3_MAP register */
1460         if (!pf->support_multi_driver) {
1461                 ret = i40e_aq_debug_write_global_register(hw,
1462                                                    I40E_GLQF_L3_MAP(40),
1463                                                    0x00000028,  NULL);
1464                 if (ret)
1465                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1466                                      ret);
1467                 PMD_INIT_LOG(DEBUG,
1468                              "Global register 0x%08x is changed with 0x28",
1469                              I40E_GLQF_L3_MAP(40));
1470         }
1471
1472         /* Need the special FW version to support floating VEB */
1473         config_floating_veb(dev);
1474         /* Clear PXE mode */
1475         i40e_clear_pxe_mode(hw);
1476         i40e_dev_sync_phy_type(hw);
1477
1478         /*
1479          * On X710, performance number is far from the expectation on recent
1480          * firmware versions. The fix for this issue may not be integrated in
1481          * the following firmware version. So the workaround in software driver
1482          * is needed. It needs to modify the initial values of 3 internal only
1483          * registers. Note that the workaround can be removed when it is fixed
1484          * in firmware in the future.
1485          */
1486         i40e_configure_registers(hw);
1487
1488         /* Get hw capabilities */
1489         ret = i40e_get_cap(hw);
1490         if (ret != I40E_SUCCESS) {
1491                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1492                 goto err_get_capabilities;
1493         }
1494
1495         /* Initialize parameters for PF */
1496         ret = i40e_pf_parameter_init(dev);
1497         if (ret != 0) {
1498                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1499                 goto err_parameter_init;
1500         }
1501
1502         /* Initialize the queue management */
1503         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1504         if (ret < 0) {
1505                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1506                 goto err_qp_pool_init;
1507         }
1508         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1509                                 hw->func_caps.num_msix_vectors - 1);
1510         if (ret < 0) {
1511                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1512                 goto err_msix_pool_init;
1513         }
1514
1515         /* Initialize lan hmc */
1516         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1517                                 hw->func_caps.num_rx_qp, 0, 0);
1518         if (ret != I40E_SUCCESS) {
1519                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1520                 goto err_init_lan_hmc;
1521         }
1522
1523         /* Configure lan hmc */
1524         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1525         if (ret != I40E_SUCCESS) {
1526                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1527                 goto err_configure_lan_hmc;
1528         }
1529
1530         /* Get and check the mac address */
1531         i40e_get_mac_addr(hw, hw->mac.addr);
1532         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1533                 PMD_INIT_LOG(ERR, "mac address is not valid");
1534                 ret = -EIO;
1535                 goto err_get_mac_addr;
1536         }
1537         /* Copy the permanent MAC address */
1538         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1539                         (struct rte_ether_addr *)hw->mac.perm_addr);
1540
1541         /* Disable flow control */
1542         hw->fc.requested_mode = I40E_FC_NONE;
1543         i40e_set_fc(hw, &aq_fail, TRUE);
1544
1545         /* Set the global registers with default ether type value */
1546         if (!pf->support_multi_driver) {
1547                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1548                                          RTE_ETHER_TYPE_VLAN);
1549                 if (ret != I40E_SUCCESS) {
1550                         PMD_INIT_LOG(ERR,
1551                                      "Failed to set the default outer "
1552                                      "VLAN ether type");
1553                         goto err_setup_pf_switch;
1554                 }
1555         }
1556
1557         /* PF setup, which includes VSI setup */
1558         ret = i40e_pf_setup(pf);
1559         if (ret) {
1560                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1561                 goto err_setup_pf_switch;
1562         }
1563
1564         vsi = pf->main_vsi;
1565
1566         /* Disable double vlan by default */
1567         i40e_vsi_config_double_vlan(vsi, FALSE);
1568
1569         /* Disable S-TAG identification when floating_veb is disabled */
1570         if (!pf->floating_veb) {
1571                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1572                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1573                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1574                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1575                 }
1576         }
1577
1578         if (!vsi->max_macaddrs)
1579                 len = RTE_ETHER_ADDR_LEN;
1580         else
1581                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1582
1583         /* Should be after VSI initialized */
1584         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1585         if (!dev->data->mac_addrs) {
1586                 PMD_INIT_LOG(ERR,
1587                         "Failed to allocated memory for storing mac address");
1588                 goto err_mac_alloc;
1589         }
1590         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1591                                         &dev->data->mac_addrs[0]);
1592
1593         /* Pass the information to the rte_eth_dev_close() that it should also
1594          * release the private port resources.
1595          */
1596         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1597
1598         /* Init dcb to sw mode by default */
1599         ret = i40e_dcb_init_configure(dev, TRUE);
1600         if (ret != I40E_SUCCESS) {
1601                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1602                 pf->flags &= ~I40E_FLAG_DCB;
1603         }
1604         /* Update HW struct after DCB configuration */
1605         i40e_get_cap(hw);
1606
1607         /* initialize pf host driver to setup SRIOV resource if applicable */
1608         i40e_pf_host_init(dev);
1609
1610         /* register callback func to eal lib */
1611         rte_intr_callback_register(intr_handle,
1612                                    i40e_dev_interrupt_handler, dev);
1613
1614         /* configure and enable device interrupt */
1615         i40e_pf_config_irq0(hw, TRUE);
1616         i40e_pf_enable_irq0(hw);
1617
1618         /* enable uio intr after callback register */
1619         rte_intr_enable(intr_handle);
1620
1621         /* By default disable flexible payload in global configuration */
1622         if (!pf->support_multi_driver)
1623                 i40e_flex_payload_reg_set_default(hw);
1624
1625         /*
1626          * Add an ethertype filter to drop all flow control frames transmitted
1627          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1628          * frames to wire.
1629          */
1630         i40e_add_tx_flow_control_drop_filter(pf);
1631
1632         /* Set the max frame size to 0x2600 by default,
1633          * in case other drivers changed the default value.
1634          */
1635         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1636
1637         /* initialize mirror rule list */
1638         TAILQ_INIT(&pf->mirror_list);
1639
1640         /* initialize Traffic Manager configuration */
1641         i40e_tm_conf_init(dev);
1642
1643         /* Initialize customized information */
1644         i40e_init_customized_info(pf);
1645
1646         ret = i40e_init_ethtype_filter_list(dev);
1647         if (ret < 0)
1648                 goto err_init_ethtype_filter_list;
1649         ret = i40e_init_tunnel_filter_list(dev);
1650         if (ret < 0)
1651                 goto err_init_tunnel_filter_list;
1652         ret = i40e_init_fdir_filter_list(dev);
1653         if (ret < 0)
1654                 goto err_init_fdir_filter_list;
1655
1656         /* initialize queue region configuration */
1657         i40e_init_queue_region_conf(dev);
1658
1659         /* initialize rss configuration from rte_flow */
1660         memset(&pf->rss_info, 0,
1661                 sizeof(struct i40e_rte_flow_rss_conf));
1662
1663         /* reset all stats of the device, including pf and main vsi */
1664         i40e_dev_stats_reset(dev);
1665
1666         return 0;
1667
1668 err_init_fdir_filter_list:
1669         rte_free(pf->tunnel.hash_table);
1670         rte_free(pf->tunnel.hash_map);
1671 err_init_tunnel_filter_list:
1672         rte_free(pf->ethertype.hash_table);
1673         rte_free(pf->ethertype.hash_map);
1674 err_init_ethtype_filter_list:
1675         rte_free(dev->data->mac_addrs);
1676         dev->data->mac_addrs = NULL;
1677 err_mac_alloc:
1678         i40e_vsi_release(pf->main_vsi);
1679 err_setup_pf_switch:
1680 err_get_mac_addr:
1681 err_configure_lan_hmc:
1682         (void)i40e_shutdown_lan_hmc(hw);
1683 err_init_lan_hmc:
1684         i40e_res_pool_destroy(&pf->msix_pool);
1685 err_msix_pool_init:
1686         i40e_res_pool_destroy(&pf->qp_pool);
1687 err_qp_pool_init:
1688 err_parameter_init:
1689 err_get_capabilities:
1690         (void)i40e_shutdown_adminq(hw);
1691
1692         return ret;
1693 }
1694
1695 static void
1696 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1697 {
1698         struct i40e_ethertype_filter *p_ethertype;
1699         struct i40e_ethertype_rule *ethertype_rule;
1700
1701         ethertype_rule = &pf->ethertype;
1702         /* Remove all ethertype filter rules and hash */
1703         if (ethertype_rule->hash_map)
1704                 rte_free(ethertype_rule->hash_map);
1705         if (ethertype_rule->hash_table)
1706                 rte_hash_free(ethertype_rule->hash_table);
1707
1708         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1709                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1710                              p_ethertype, rules);
1711                 rte_free(p_ethertype);
1712         }
1713 }
1714
1715 static void
1716 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1717 {
1718         struct i40e_tunnel_filter *p_tunnel;
1719         struct i40e_tunnel_rule *tunnel_rule;
1720
1721         tunnel_rule = &pf->tunnel;
1722         /* Remove all tunnel director rules and hash */
1723         if (tunnel_rule->hash_map)
1724                 rte_free(tunnel_rule->hash_map);
1725         if (tunnel_rule->hash_table)
1726                 rte_hash_free(tunnel_rule->hash_table);
1727
1728         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1729                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1730                 rte_free(p_tunnel);
1731         }
1732 }
1733
1734 static void
1735 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1736 {
1737         struct i40e_fdir_filter *p_fdir;
1738         struct i40e_fdir_info *fdir_info;
1739
1740         fdir_info = &pf->fdir;
1741         /* Remove all flow director rules and hash */
1742         if (fdir_info->hash_map)
1743                 rte_free(fdir_info->hash_map);
1744         if (fdir_info->hash_table)
1745                 rte_hash_free(fdir_info->hash_table);
1746
1747         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1748                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1749                 rte_free(p_fdir);
1750         }
1751 }
1752
1753 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1754 {
1755         /*
1756          * Disable by default flexible payload
1757          * for corresponding L2/L3/L4 layers.
1758          */
1759         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1760         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1761         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1762 }
1763
1764 static int
1765 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1766 {
1767         struct i40e_hw *hw;
1768
1769         PMD_INIT_FUNC_TRACE();
1770
1771         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1772                 return 0;
1773
1774         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1775
1776         if (hw->adapter_closed == 0)
1777                 i40e_dev_close(dev);
1778
1779         return 0;
1780 }
1781
1782 static int
1783 i40e_dev_configure(struct rte_eth_dev *dev)
1784 {
1785         struct i40e_adapter *ad =
1786                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1787         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1788         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1789         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1790         int i, ret;
1791
1792         ret = i40e_dev_sync_phy_type(hw);
1793         if (ret)
1794                 return ret;
1795
1796         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1797          * bulk allocation or vector Rx preconditions we will reset it.
1798          */
1799         ad->rx_bulk_alloc_allowed = true;
1800         ad->rx_vec_allowed = true;
1801         ad->tx_simple_allowed = true;
1802         ad->tx_vec_allowed = true;
1803
1804         /* Only legacy filter API needs the following fdir config. So when the
1805          * legacy filter API is deprecated, the following codes should also be
1806          * removed.
1807          */
1808         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1809                 ret = i40e_fdir_setup(pf);
1810                 if (ret != I40E_SUCCESS) {
1811                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1812                         return -ENOTSUP;
1813                 }
1814                 ret = i40e_fdir_configure(dev);
1815                 if (ret < 0) {
1816                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1817                         goto err;
1818                 }
1819         } else
1820                 i40e_fdir_teardown(pf);
1821
1822         ret = i40e_dev_init_vlan(dev);
1823         if (ret < 0)
1824                 goto err;
1825
1826         /* VMDQ setup.
1827          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1828          *  RSS setting have different requirements.
1829          *  General PMD driver call sequence are NIC init, configure,
1830          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1831          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1832          *  applicable. So, VMDQ setting has to be done before
1833          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1834          *  For RSS setting, it will try to calculate actual configured RX queue
1835          *  number, which will be available after rx_queue_setup(). dev_start()
1836          *  function is good to place RSS setup.
1837          */
1838         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1839                 ret = i40e_vmdq_setup(dev);
1840                 if (ret)
1841                         goto err;
1842         }
1843
1844         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1845                 ret = i40e_dcb_setup(dev);
1846                 if (ret) {
1847                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1848                         goto err_dcb;
1849                 }
1850         }
1851
1852         TAILQ_INIT(&pf->flow_list);
1853
1854         return 0;
1855
1856 err_dcb:
1857         /* need to release vmdq resource if exists */
1858         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1859                 i40e_vsi_release(pf->vmdq[i].vsi);
1860                 pf->vmdq[i].vsi = NULL;
1861         }
1862         rte_free(pf->vmdq);
1863         pf->vmdq = NULL;
1864 err:
1865         /* Need to release fdir resource if exists.
1866          * Only legacy filter API needs the following fdir config. So when the
1867          * legacy filter API is deprecated, the following code should also be
1868          * removed.
1869          */
1870         i40e_fdir_teardown(pf);
1871         return ret;
1872 }
1873
1874 void
1875 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1876 {
1877         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1878         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1879         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1880         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1881         uint16_t msix_vect = vsi->msix_intr;
1882         uint16_t i;
1883
1884         for (i = 0; i < vsi->nb_qps; i++) {
1885                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1886                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1887                 rte_wmb();
1888         }
1889
1890         if (vsi->type != I40E_VSI_SRIOV) {
1891                 if (!rte_intr_allow_others(intr_handle)) {
1892                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1893                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1894                         I40E_WRITE_REG(hw,
1895                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1896                                        0);
1897                 } else {
1898                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1899                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1900                         I40E_WRITE_REG(hw,
1901                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1902                                                        msix_vect - 1), 0);
1903                 }
1904         } else {
1905                 uint32_t reg;
1906                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1907                         vsi->user_param + (msix_vect - 1);
1908
1909                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1910                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1911         }
1912         I40E_WRITE_FLUSH(hw);
1913 }
1914
1915 static void
1916 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1917                        int base_queue, int nb_queue,
1918                        uint16_t itr_idx)
1919 {
1920         int i;
1921         uint32_t val;
1922         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1923         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1924
1925         /* Bind all RX queues to allocated MSIX interrupt */
1926         for (i = 0; i < nb_queue; i++) {
1927                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1928                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1929                         ((base_queue + i + 1) <<
1930                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1931                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1932                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1933
1934                 if (i == nb_queue - 1)
1935                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1936                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1937         }
1938
1939         /* Write first RX queue to Link list register as the head element */
1940         if (vsi->type != I40E_VSI_SRIOV) {
1941                 uint16_t interval =
1942                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1943
1944                 if (msix_vect == I40E_MISC_VEC_ID) {
1945                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1946                                        (base_queue <<
1947                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1948                                        (0x0 <<
1949                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1950                         I40E_WRITE_REG(hw,
1951                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1952                                        interval);
1953                 } else {
1954                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1955                                        (base_queue <<
1956                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1957                                        (0x0 <<
1958                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1959                         I40E_WRITE_REG(hw,
1960                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1961                                                        msix_vect - 1),
1962                                        interval);
1963                 }
1964         } else {
1965                 uint32_t reg;
1966
1967                 if (msix_vect == I40E_MISC_VEC_ID) {
1968                         I40E_WRITE_REG(hw,
1969                                        I40E_VPINT_LNKLST0(vsi->user_param),
1970                                        (base_queue <<
1971                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1972                                        (0x0 <<
1973                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1974                 } else {
1975                         /* num_msix_vectors_vf needs to minus irq0 */
1976                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1977                                 vsi->user_param + (msix_vect - 1);
1978
1979                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1980                                        (base_queue <<
1981                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1982                                        (0x0 <<
1983                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1984                 }
1985         }
1986
1987         I40E_WRITE_FLUSH(hw);
1988 }
1989
1990 void
1991 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1992 {
1993         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1994         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1995         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1996         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1997         uint16_t msix_vect = vsi->msix_intr;
1998         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1999         uint16_t queue_idx = 0;
2000         int record = 0;
2001         int i;
2002
2003         for (i = 0; i < vsi->nb_qps; i++) {
2004                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2005                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2006         }
2007
2008         /* VF bind interrupt */
2009         if (vsi->type == I40E_VSI_SRIOV) {
2010                 __vsi_queues_bind_intr(vsi, msix_vect,
2011                                        vsi->base_queue, vsi->nb_qps,
2012                                        itr_idx);
2013                 return;
2014         }
2015
2016         /* PF & VMDq bind interrupt */
2017         if (rte_intr_dp_is_en(intr_handle)) {
2018                 if (vsi->type == I40E_VSI_MAIN) {
2019                         queue_idx = 0;
2020                         record = 1;
2021                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2022                         struct i40e_vsi *main_vsi =
2023                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2024                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2025                         record = 1;
2026                 }
2027         }
2028
2029         for (i = 0; i < vsi->nb_used_qps; i++) {
2030                 if (nb_msix <= 1) {
2031                         if (!rte_intr_allow_others(intr_handle))
2032                                 /* allow to share MISC_VEC_ID */
2033                                 msix_vect = I40E_MISC_VEC_ID;
2034
2035                         /* no enough msix_vect, map all to one */
2036                         __vsi_queues_bind_intr(vsi, msix_vect,
2037                                                vsi->base_queue + i,
2038                                                vsi->nb_used_qps - i,
2039                                                itr_idx);
2040                         for (; !!record && i < vsi->nb_used_qps; i++)
2041                                 intr_handle->intr_vec[queue_idx + i] =
2042                                         msix_vect;
2043                         break;
2044                 }
2045                 /* 1:1 queue/msix_vect mapping */
2046                 __vsi_queues_bind_intr(vsi, msix_vect,
2047                                        vsi->base_queue + i, 1,
2048                                        itr_idx);
2049                 if (!!record)
2050                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2051
2052                 msix_vect++;
2053                 nb_msix--;
2054         }
2055 }
2056
2057 static void
2058 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2059 {
2060         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2061         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2062         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2063         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2064         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2065         uint16_t msix_intr, i;
2066
2067         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2068                 for (i = 0; i < vsi->nb_msix; i++) {
2069                         msix_intr = vsi->msix_intr + i;
2070                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2071                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2072                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2073                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2074                 }
2075         else
2076                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2077                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2078                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2079                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2080
2081         I40E_WRITE_FLUSH(hw);
2082 }
2083
2084 static void
2085 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2086 {
2087         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2088         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2089         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2090         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2091         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2092         uint16_t msix_intr, i;
2093
2094         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2095                 for (i = 0; i < vsi->nb_msix; i++) {
2096                         msix_intr = vsi->msix_intr + i;
2097                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2098                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2099                 }
2100         else
2101                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2102                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2103
2104         I40E_WRITE_FLUSH(hw);
2105 }
2106
2107 static inline uint8_t
2108 i40e_parse_link_speeds(uint16_t link_speeds)
2109 {
2110         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2111
2112         if (link_speeds & ETH_LINK_SPEED_40G)
2113                 link_speed |= I40E_LINK_SPEED_40GB;
2114         if (link_speeds & ETH_LINK_SPEED_25G)
2115                 link_speed |= I40E_LINK_SPEED_25GB;
2116         if (link_speeds & ETH_LINK_SPEED_20G)
2117                 link_speed |= I40E_LINK_SPEED_20GB;
2118         if (link_speeds & ETH_LINK_SPEED_10G)
2119                 link_speed |= I40E_LINK_SPEED_10GB;
2120         if (link_speeds & ETH_LINK_SPEED_1G)
2121                 link_speed |= I40E_LINK_SPEED_1GB;
2122         if (link_speeds & ETH_LINK_SPEED_100M)
2123                 link_speed |= I40E_LINK_SPEED_100MB;
2124
2125         return link_speed;
2126 }
2127
2128 static int
2129 i40e_phy_conf_link(struct i40e_hw *hw,
2130                    uint8_t abilities,
2131                    uint8_t force_speed,
2132                    bool is_up)
2133 {
2134         enum i40e_status_code status;
2135         struct i40e_aq_get_phy_abilities_resp phy_ab;
2136         struct i40e_aq_set_phy_config phy_conf;
2137         enum i40e_aq_phy_type cnt;
2138         uint8_t avail_speed;
2139         uint32_t phy_type_mask = 0;
2140
2141         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2142                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2143                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2144                         I40E_AQ_PHY_FLAG_LOW_POWER;
2145         int ret = -ENOTSUP;
2146
2147         /* To get phy capabilities of available speeds. */
2148         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2149                                               NULL);
2150         if (status) {
2151                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2152                                 status);
2153                 return ret;
2154         }
2155         avail_speed = phy_ab.link_speed;
2156
2157         /* To get the current phy config. */
2158         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2159                                               NULL);
2160         if (status) {
2161                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2162                                 status);
2163                 return ret;
2164         }
2165
2166         /* If link needs to go up and it is in autoneg mode the speed is OK,
2167          * no need to set up again.
2168          */
2169         if (is_up && phy_ab.phy_type != 0 &&
2170                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2171                      phy_ab.link_speed != 0)
2172                 return I40E_SUCCESS;
2173
2174         memset(&phy_conf, 0, sizeof(phy_conf));
2175
2176         /* bits 0-2 use the values from get_phy_abilities_resp */
2177         abilities &= ~mask;
2178         abilities |= phy_ab.abilities & mask;
2179
2180         phy_conf.abilities = abilities;
2181
2182         /* If link needs to go up, but the force speed is not supported,
2183          * Warn users and config the default available speeds.
2184          */
2185         if (is_up && !(force_speed & avail_speed)) {
2186                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2187                 phy_conf.link_speed = avail_speed;
2188         } else {
2189                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2190         }
2191
2192         /* PHY type mask needs to include each type except PHY type extension */
2193         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2194                 phy_type_mask |= 1 << cnt;
2195
2196         /* use get_phy_abilities_resp value for the rest */
2197         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2198         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2199                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2200                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2201         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2202         phy_conf.eee_capability = phy_ab.eee_capability;
2203         phy_conf.eeer = phy_ab.eeer_val;
2204         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2205
2206         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2207                     phy_ab.abilities, phy_ab.link_speed);
2208         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2209                     phy_conf.abilities, phy_conf.link_speed);
2210
2211         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2212         if (status)
2213                 return ret;
2214
2215         return I40E_SUCCESS;
2216 }
2217
2218 static int
2219 i40e_apply_link_speed(struct rte_eth_dev *dev)
2220 {
2221         uint8_t speed;
2222         uint8_t abilities = 0;
2223         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2224         struct rte_eth_conf *conf = &dev->data->dev_conf;
2225
2226         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2227                 conf->link_speeds = ETH_LINK_SPEED_40G |
2228                                     ETH_LINK_SPEED_25G |
2229                                     ETH_LINK_SPEED_20G |
2230                                     ETH_LINK_SPEED_10G |
2231                                     ETH_LINK_SPEED_1G |
2232                                     ETH_LINK_SPEED_100M;
2233         }
2234         speed = i40e_parse_link_speeds(conf->link_speeds);
2235         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2236                      I40E_AQ_PHY_AN_ENABLED |
2237                      I40E_AQ_PHY_LINK_ENABLED;
2238
2239         return i40e_phy_conf_link(hw, abilities, speed, true);
2240 }
2241
2242 static int
2243 i40e_dev_start(struct rte_eth_dev *dev)
2244 {
2245         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2246         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2247         struct i40e_vsi *main_vsi = pf->main_vsi;
2248         int ret, i;
2249         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2250         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2251         uint32_t intr_vector = 0;
2252         struct i40e_vsi *vsi;
2253
2254         hw->adapter_stopped = 0;
2255
2256         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2257                 PMD_INIT_LOG(ERR,
2258                 "Invalid link_speeds for port %u, autonegotiation disabled",
2259                               dev->data->port_id);
2260                 return -EINVAL;
2261         }
2262
2263         rte_intr_disable(intr_handle);
2264
2265         if ((rte_intr_cap_multiple(intr_handle) ||
2266              !RTE_ETH_DEV_SRIOV(dev).active) &&
2267             dev->data->dev_conf.intr_conf.rxq != 0) {
2268                 intr_vector = dev->data->nb_rx_queues;
2269                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2270                 if (ret)
2271                         return ret;
2272         }
2273
2274         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2275                 intr_handle->intr_vec =
2276                         rte_zmalloc("intr_vec",
2277                                     dev->data->nb_rx_queues * sizeof(int),
2278                                     0);
2279                 if (!intr_handle->intr_vec) {
2280                         PMD_INIT_LOG(ERR,
2281                                 "Failed to allocate %d rx_queues intr_vec",
2282                                 dev->data->nb_rx_queues);
2283                         return -ENOMEM;
2284                 }
2285         }
2286
2287         /* Initialize VSI */
2288         ret = i40e_dev_rxtx_init(pf);
2289         if (ret != I40E_SUCCESS) {
2290                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2291                 goto err_up;
2292         }
2293
2294         /* Map queues with MSIX interrupt */
2295         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2296                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2297         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2298         i40e_vsi_enable_queues_intr(main_vsi);
2299
2300         /* Map VMDQ VSI queues with MSIX interrupt */
2301         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2302                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2303                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2304                                           I40E_ITR_INDEX_DEFAULT);
2305                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2306         }
2307
2308         /* enable FDIR MSIX interrupt */
2309         if (pf->fdir.fdir_vsi) {
2310                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2311                                           I40E_ITR_INDEX_NONE);
2312                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2313         }
2314
2315         /* Enable all queues which have been configured */
2316         ret = i40e_dev_switch_queues(pf, TRUE);
2317         if (ret != I40E_SUCCESS) {
2318                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2319                 goto err_up;
2320         }
2321
2322         /* Enable receiving broadcast packets */
2323         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2324         if (ret != I40E_SUCCESS)
2325                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2326
2327         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2328                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2329                                                 true, NULL);
2330                 if (ret != I40E_SUCCESS)
2331                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2332         }
2333
2334         /* Enable the VLAN promiscuous mode. */
2335         if (pf->vfs) {
2336                 for (i = 0; i < pf->vf_num; i++) {
2337                         vsi = pf->vfs[i].vsi;
2338                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2339                                                      true, NULL);
2340                 }
2341         }
2342
2343         /* Enable mac loopback mode */
2344         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2345             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2346                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2347                 if (ret != I40E_SUCCESS) {
2348                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2349                         goto err_up;
2350                 }
2351         }
2352
2353         /* Apply link configure */
2354         ret = i40e_apply_link_speed(dev);
2355         if (I40E_SUCCESS != ret) {
2356                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2357                 goto err_up;
2358         }
2359
2360         if (!rte_intr_allow_others(intr_handle)) {
2361                 rte_intr_callback_unregister(intr_handle,
2362                                              i40e_dev_interrupt_handler,
2363                                              (void *)dev);
2364                 /* configure and enable device interrupt */
2365                 i40e_pf_config_irq0(hw, FALSE);
2366                 i40e_pf_enable_irq0(hw);
2367
2368                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2369                         PMD_INIT_LOG(INFO,
2370                                 "lsc won't enable because of no intr multiplex");
2371         } else {
2372                 ret = i40e_aq_set_phy_int_mask(hw,
2373                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2374                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2375                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2376                 if (ret != I40E_SUCCESS)
2377                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2378
2379                 /* Call get_link_info aq commond to enable/disable LSE */
2380                 i40e_dev_link_update(dev, 0);
2381         }
2382
2383         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2384                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2385                                   i40e_dev_alarm_handler, dev);
2386         } else {
2387                 /* enable uio intr after callback register */
2388                 rte_intr_enable(intr_handle);
2389         }
2390
2391         i40e_filter_restore(pf);
2392
2393         if (pf->tm_conf.root && !pf->tm_conf.committed)
2394                 PMD_DRV_LOG(WARNING,
2395                             "please call hierarchy_commit() "
2396                             "before starting the port");
2397
2398         return I40E_SUCCESS;
2399
2400 err_up:
2401         i40e_dev_switch_queues(pf, FALSE);
2402         i40e_dev_clear_queues(dev);
2403
2404         return ret;
2405 }
2406
2407 static void
2408 i40e_dev_stop(struct rte_eth_dev *dev)
2409 {
2410         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2411         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2412         struct i40e_vsi *main_vsi = pf->main_vsi;
2413         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2414         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2415         int i;
2416
2417         if (hw->adapter_stopped == 1)
2418                 return;
2419
2420         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2421                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2422                 rte_intr_enable(intr_handle);
2423         }
2424
2425         /* Disable all queues */
2426         i40e_dev_switch_queues(pf, FALSE);
2427
2428         /* un-map queues with interrupt registers */
2429         i40e_vsi_disable_queues_intr(main_vsi);
2430         i40e_vsi_queues_unbind_intr(main_vsi);
2431
2432         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2433                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2434                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2435         }
2436
2437         if (pf->fdir.fdir_vsi) {
2438                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2439                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2440         }
2441         /* Clear all queues and release memory */
2442         i40e_dev_clear_queues(dev);
2443
2444         /* Set link down */
2445         i40e_dev_set_link_down(dev);
2446
2447         if (!rte_intr_allow_others(intr_handle))
2448                 /* resume to the default handler */
2449                 rte_intr_callback_register(intr_handle,
2450                                            i40e_dev_interrupt_handler,
2451                                            (void *)dev);
2452
2453         /* Clean datapath event and queue/vec mapping */
2454         rte_intr_efd_disable(intr_handle);
2455         if (intr_handle->intr_vec) {
2456                 rte_free(intr_handle->intr_vec);
2457                 intr_handle->intr_vec = NULL;
2458         }
2459
2460         /* reset hierarchy commit */
2461         pf->tm_conf.committed = false;
2462
2463         hw->adapter_stopped = 1;
2464
2465         pf->adapter->rss_reta_updated = 0;
2466 }
2467
2468 static void
2469 i40e_dev_close(struct rte_eth_dev *dev)
2470 {
2471         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2472         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2473         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2474         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2475         struct i40e_mirror_rule *p_mirror;
2476         struct i40e_filter_control_settings settings;
2477         struct rte_flow *p_flow;
2478         uint32_t reg;
2479         int i;
2480         int ret;
2481         uint8_t aq_fail = 0;
2482         int retries = 0;
2483
2484         PMD_INIT_FUNC_TRACE();
2485
2486         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2487         if (ret)
2488                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2489
2490
2491         i40e_dev_stop(dev);
2492
2493         /* Remove all mirror rules */
2494         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2495                 ret = i40e_aq_del_mirror_rule(hw,
2496                                               pf->main_vsi->veb->seid,
2497                                               p_mirror->rule_type,
2498                                               p_mirror->entries,
2499                                               p_mirror->num_entries,
2500                                               p_mirror->id);
2501                 if (ret < 0)
2502                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2503                                     "status = %d, aq_err = %d.", ret,
2504                                     hw->aq.asq_last_status);
2505
2506                 /* remove mirror software resource anyway */
2507                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2508                 rte_free(p_mirror);
2509                 pf->nb_mirror_rule--;
2510         }
2511
2512         i40e_dev_free_queues(dev);
2513
2514         /* Disable interrupt */
2515         i40e_pf_disable_irq0(hw);
2516         rte_intr_disable(intr_handle);
2517
2518         /*
2519          * Only legacy filter API needs the following fdir config. So when the
2520          * legacy filter API is deprecated, the following code should also be
2521          * removed.
2522          */
2523         i40e_fdir_teardown(pf);
2524
2525         /* shutdown and destroy the HMC */
2526         i40e_shutdown_lan_hmc(hw);
2527
2528         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2529                 i40e_vsi_release(pf->vmdq[i].vsi);
2530                 pf->vmdq[i].vsi = NULL;
2531         }
2532         rte_free(pf->vmdq);
2533         pf->vmdq = NULL;
2534
2535         /* release all the existing VSIs and VEBs */
2536         i40e_vsi_release(pf->main_vsi);
2537
2538         /* shutdown the adminq */
2539         i40e_aq_queue_shutdown(hw, true);
2540         i40e_shutdown_adminq(hw);
2541
2542         i40e_res_pool_destroy(&pf->qp_pool);
2543         i40e_res_pool_destroy(&pf->msix_pool);
2544
2545         /* Disable flexible payload in global configuration */
2546         if (!pf->support_multi_driver)
2547                 i40e_flex_payload_reg_set_default(hw);
2548
2549         /* force a PF reset to clean anything leftover */
2550         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2551         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2552                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2553         I40E_WRITE_FLUSH(hw);
2554
2555         dev->dev_ops = NULL;
2556         dev->rx_pkt_burst = NULL;
2557         dev->tx_pkt_burst = NULL;
2558
2559         /* Clear PXE mode */
2560         i40e_clear_pxe_mode(hw);
2561
2562         /* Unconfigure filter control */
2563         memset(&settings, 0, sizeof(settings));
2564         ret = i40e_set_filter_control(hw, &settings);
2565         if (ret)
2566                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2567                                         ret);
2568
2569         /* Disable flow control */
2570         hw->fc.requested_mode = I40E_FC_NONE;
2571         i40e_set_fc(hw, &aq_fail, TRUE);
2572
2573         /* uninitialize pf host driver */
2574         i40e_pf_host_uninit(dev);
2575
2576         do {
2577                 ret = rte_intr_callback_unregister(intr_handle,
2578                                 i40e_dev_interrupt_handler, dev);
2579                 if (ret >= 0) {
2580                         break;
2581                 } else if (ret != -EAGAIN) {
2582                         PMD_INIT_LOG(ERR,
2583                                  "intr callback unregister failed: %d",
2584                                  ret);
2585                 }
2586                 i40e_msec_delay(500);
2587         } while (retries++ < 5);
2588
2589         i40e_rm_ethtype_filter_list(pf);
2590         i40e_rm_tunnel_filter_list(pf);
2591         i40e_rm_fdir_filter_list(pf);
2592
2593         /* Remove all flows */
2594         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2595                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2596                 rte_free(p_flow);
2597         }
2598
2599         /* Remove all Traffic Manager configuration */
2600         i40e_tm_conf_uninit(dev);
2601
2602         hw->adapter_closed = 1;
2603 }
2604
2605 /*
2606  * Reset PF device only to re-initialize resources in PMD layer
2607  */
2608 static int
2609 i40e_dev_reset(struct rte_eth_dev *dev)
2610 {
2611         int ret;
2612
2613         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2614          * its VF to make them align with it. The detailed notification
2615          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2616          * To avoid unexpected behavior in VF, currently reset of PF with
2617          * SR-IOV activation is not supported. It might be supported later.
2618          */
2619         if (dev->data->sriov.active)
2620                 return -ENOTSUP;
2621
2622         ret = eth_i40e_dev_uninit(dev);
2623         if (ret)
2624                 return ret;
2625
2626         ret = eth_i40e_dev_init(dev, NULL);
2627
2628         return ret;
2629 }
2630
2631 static int
2632 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2633 {
2634         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2635         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2636         struct i40e_vsi *vsi = pf->main_vsi;
2637         int status;
2638
2639         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2640                                                      true, NULL, true);
2641         if (status != I40E_SUCCESS) {
2642                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2643                 return -EAGAIN;
2644         }
2645
2646         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2647                                                         TRUE, NULL);
2648         if (status != I40E_SUCCESS) {
2649                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2650                 /* Rollback unicast promiscuous mode */
2651                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2652                                                     false, NULL, true);
2653                 return -EAGAIN;
2654         }
2655
2656         return 0;
2657 }
2658
2659 static int
2660 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2661 {
2662         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2663         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2664         struct i40e_vsi *vsi = pf->main_vsi;
2665         int status;
2666
2667         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2668                                                      false, NULL, true);
2669         if (status != I40E_SUCCESS) {
2670                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2671                 return -EAGAIN;
2672         }
2673
2674         /* must remain in all_multicast mode */
2675         if (dev->data->all_multicast == 1)
2676                 return 0;
2677
2678         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2679                                                         false, NULL);
2680         if (status != I40E_SUCCESS) {
2681                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2682                 /* Rollback unicast promiscuous mode */
2683                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2684                                                     true, NULL, true);
2685                 return -EAGAIN;
2686         }
2687
2688         return 0;
2689 }
2690
2691 static int
2692 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2693 {
2694         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2695         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2696         struct i40e_vsi *vsi = pf->main_vsi;
2697         int ret;
2698
2699         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2700         if (ret != I40E_SUCCESS) {
2701                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2702                 return -EAGAIN;
2703         }
2704
2705         return 0;
2706 }
2707
2708 static int
2709 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2710 {
2711         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2712         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2713         struct i40e_vsi *vsi = pf->main_vsi;
2714         int ret;
2715
2716         if (dev->data->promiscuous == 1)
2717                 return 0; /* must remain in all_multicast mode */
2718
2719         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2720                                 vsi->seid, FALSE, NULL);
2721         if (ret != I40E_SUCCESS) {
2722                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2723                 return -EAGAIN;
2724         }
2725
2726         return 0;
2727 }
2728
2729 /*
2730  * Set device link up.
2731  */
2732 static int
2733 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2734 {
2735         /* re-apply link speed setting */
2736         return i40e_apply_link_speed(dev);
2737 }
2738
2739 /*
2740  * Set device link down.
2741  */
2742 static int
2743 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2744 {
2745         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2746         uint8_t abilities = 0;
2747         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2748
2749         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2750         return i40e_phy_conf_link(hw, abilities, speed, false);
2751 }
2752
2753 static __rte_always_inline void
2754 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2755 {
2756 /* Link status registers and values*/
2757 #define I40E_PRTMAC_LINKSTA             0x001E2420
2758 #define I40E_REG_LINK_UP                0x40000080
2759 #define I40E_PRTMAC_MACC                0x001E24E0
2760 #define I40E_REG_MACC_25GB              0x00020000
2761 #define I40E_REG_SPEED_MASK             0x38000000
2762 #define I40E_REG_SPEED_0                0x00000000
2763 #define I40E_REG_SPEED_1                0x08000000
2764 #define I40E_REG_SPEED_2                0x10000000
2765 #define I40E_REG_SPEED_3                0x18000000
2766 #define I40E_REG_SPEED_4                0x20000000
2767         uint32_t link_speed;
2768         uint32_t reg_val;
2769
2770         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2771         link_speed = reg_val & I40E_REG_SPEED_MASK;
2772         reg_val &= I40E_REG_LINK_UP;
2773         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2774
2775         if (unlikely(link->link_status == 0))
2776                 return;
2777
2778         /* Parse the link status */
2779         switch (link_speed) {
2780         case I40E_REG_SPEED_0:
2781                 link->link_speed = ETH_SPEED_NUM_100M;
2782                 break;
2783         case I40E_REG_SPEED_1:
2784                 link->link_speed = ETH_SPEED_NUM_1G;
2785                 break;
2786         case I40E_REG_SPEED_2:
2787                 if (hw->mac.type == I40E_MAC_X722)
2788                         link->link_speed = ETH_SPEED_NUM_2_5G;
2789                 else
2790                         link->link_speed = ETH_SPEED_NUM_10G;
2791                 break;
2792         case I40E_REG_SPEED_3:
2793                 if (hw->mac.type == I40E_MAC_X722) {
2794                         link->link_speed = ETH_SPEED_NUM_5G;
2795                 } else {
2796                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2797
2798                         if (reg_val & I40E_REG_MACC_25GB)
2799                                 link->link_speed = ETH_SPEED_NUM_25G;
2800                         else
2801                                 link->link_speed = ETH_SPEED_NUM_40G;
2802                 }
2803                 break;
2804         case I40E_REG_SPEED_4:
2805                 if (hw->mac.type == I40E_MAC_X722)
2806                         link->link_speed = ETH_SPEED_NUM_10G;
2807                 else
2808                         link->link_speed = ETH_SPEED_NUM_20G;
2809                 break;
2810         default:
2811                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2812                 break;
2813         }
2814 }
2815
2816 static __rte_always_inline void
2817 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2818         bool enable_lse, int wait_to_complete)
2819 {
2820 #define CHECK_INTERVAL             100  /* 100ms */
2821 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2822         uint32_t rep_cnt = MAX_REPEAT_TIME;
2823         struct i40e_link_status link_status;
2824         int status;
2825
2826         memset(&link_status, 0, sizeof(link_status));
2827
2828         do {
2829                 memset(&link_status, 0, sizeof(link_status));
2830
2831                 /* Get link status information from hardware */
2832                 status = i40e_aq_get_link_info(hw, enable_lse,
2833                                                 &link_status, NULL);
2834                 if (unlikely(status != I40E_SUCCESS)) {
2835                         link->link_speed = ETH_SPEED_NUM_NONE;
2836                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2837                         PMD_DRV_LOG(ERR, "Failed to get link info");
2838                         return;
2839                 }
2840
2841                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2842                 if (!wait_to_complete || link->link_status)
2843                         break;
2844
2845                 rte_delay_ms(CHECK_INTERVAL);
2846         } while (--rep_cnt);
2847
2848         /* Parse the link status */
2849         switch (link_status.link_speed) {
2850         case I40E_LINK_SPEED_100MB:
2851                 link->link_speed = ETH_SPEED_NUM_100M;
2852                 break;
2853         case I40E_LINK_SPEED_1GB:
2854                 link->link_speed = ETH_SPEED_NUM_1G;
2855                 break;
2856         case I40E_LINK_SPEED_10GB:
2857                 link->link_speed = ETH_SPEED_NUM_10G;
2858                 break;
2859         case I40E_LINK_SPEED_20GB:
2860                 link->link_speed = ETH_SPEED_NUM_20G;
2861                 break;
2862         case I40E_LINK_SPEED_25GB:
2863                 link->link_speed = ETH_SPEED_NUM_25G;
2864                 break;
2865         case I40E_LINK_SPEED_40GB:
2866                 link->link_speed = ETH_SPEED_NUM_40G;
2867                 break;
2868         default:
2869                 link->link_speed = ETH_SPEED_NUM_NONE;
2870                 break;
2871         }
2872 }
2873
2874 int
2875 i40e_dev_link_update(struct rte_eth_dev *dev,
2876                      int wait_to_complete)
2877 {
2878         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2879         struct rte_eth_link link;
2880         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2881         int ret;
2882
2883         memset(&link, 0, sizeof(link));
2884
2885         /* i40e uses full duplex only */
2886         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2887         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2888                         ETH_LINK_SPEED_FIXED);
2889
2890         if (!wait_to_complete && !enable_lse)
2891                 update_link_reg(hw, &link);
2892         else
2893                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2894
2895         ret = rte_eth_linkstatus_set(dev, &link);
2896         i40e_notify_all_vfs_link_status(dev);
2897
2898         return ret;
2899 }
2900
2901 /* Get all the statistics of a VSI */
2902 void
2903 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2904 {
2905         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2906         struct i40e_eth_stats *nes = &vsi->eth_stats;
2907         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2908         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2909
2910         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2911                             vsi->offset_loaded, &oes->rx_bytes,
2912                             &nes->rx_bytes);
2913         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2914                             vsi->offset_loaded, &oes->rx_unicast,
2915                             &nes->rx_unicast);
2916         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2917                             vsi->offset_loaded, &oes->rx_multicast,
2918                             &nes->rx_multicast);
2919         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2920                             vsi->offset_loaded, &oes->rx_broadcast,
2921                             &nes->rx_broadcast);
2922         /* exclude CRC bytes */
2923         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2924                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2925
2926         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2927                             &oes->rx_discards, &nes->rx_discards);
2928         /* GLV_REPC not supported */
2929         /* GLV_RMPC not supported */
2930         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2931                             &oes->rx_unknown_protocol,
2932                             &nes->rx_unknown_protocol);
2933         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2934                             vsi->offset_loaded, &oes->tx_bytes,
2935                             &nes->tx_bytes);
2936         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2937                             vsi->offset_loaded, &oes->tx_unicast,
2938                             &nes->tx_unicast);
2939         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2940                             vsi->offset_loaded, &oes->tx_multicast,
2941                             &nes->tx_multicast);
2942         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2943                             vsi->offset_loaded,  &oes->tx_broadcast,
2944                             &nes->tx_broadcast);
2945         /* GLV_TDPC not supported */
2946         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2947                             &oes->tx_errors, &nes->tx_errors);
2948         vsi->offset_loaded = true;
2949
2950         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2951                     vsi->vsi_id);
2952         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2953         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2954         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2955         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2956         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2957         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2958                     nes->rx_unknown_protocol);
2959         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2960         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2961         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2962         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2963         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2964         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2965         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2966                     vsi->vsi_id);
2967 }
2968
2969 static void
2970 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2971 {
2972         unsigned int i;
2973         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2974         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2975
2976         /* Get rx/tx bytes of internal transfer packets */
2977         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2978                         I40E_GLV_GORCL(hw->port),
2979                         pf->offset_loaded,
2980                         &pf->internal_stats_offset.rx_bytes,
2981                         &pf->internal_stats.rx_bytes);
2982
2983         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2984                         I40E_GLV_GOTCL(hw->port),
2985                         pf->offset_loaded,
2986                         &pf->internal_stats_offset.tx_bytes,
2987                         &pf->internal_stats.tx_bytes);
2988         /* Get total internal rx packet count */
2989         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2990                             I40E_GLV_UPRCL(hw->port),
2991                             pf->offset_loaded,
2992                             &pf->internal_stats_offset.rx_unicast,
2993                             &pf->internal_stats.rx_unicast);
2994         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2995                             I40E_GLV_MPRCL(hw->port),
2996                             pf->offset_loaded,
2997                             &pf->internal_stats_offset.rx_multicast,
2998                             &pf->internal_stats.rx_multicast);
2999         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3000                             I40E_GLV_BPRCL(hw->port),
3001                             pf->offset_loaded,
3002                             &pf->internal_stats_offset.rx_broadcast,
3003                             &pf->internal_stats.rx_broadcast);
3004         /* Get total internal tx packet count */
3005         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3006                             I40E_GLV_UPTCL(hw->port),
3007                             pf->offset_loaded,
3008                             &pf->internal_stats_offset.tx_unicast,
3009                             &pf->internal_stats.tx_unicast);
3010         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3011                             I40E_GLV_MPTCL(hw->port),
3012                             pf->offset_loaded,
3013                             &pf->internal_stats_offset.tx_multicast,
3014                             &pf->internal_stats.tx_multicast);
3015         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3016                             I40E_GLV_BPTCL(hw->port),
3017                             pf->offset_loaded,
3018                             &pf->internal_stats_offset.tx_broadcast,
3019                             &pf->internal_stats.tx_broadcast);
3020
3021         /* exclude CRC size */
3022         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3023                 pf->internal_stats.rx_multicast +
3024                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3025
3026         /* Get statistics of struct i40e_eth_stats */
3027         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3028                             I40E_GLPRT_GORCL(hw->port),
3029                             pf->offset_loaded, &os->eth.rx_bytes,
3030                             &ns->eth.rx_bytes);
3031         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3032                             I40E_GLPRT_UPRCL(hw->port),
3033                             pf->offset_loaded, &os->eth.rx_unicast,
3034                             &ns->eth.rx_unicast);
3035         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3036                             I40E_GLPRT_MPRCL(hw->port),
3037                             pf->offset_loaded, &os->eth.rx_multicast,
3038                             &ns->eth.rx_multicast);
3039         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3040                             I40E_GLPRT_BPRCL(hw->port),
3041                             pf->offset_loaded, &os->eth.rx_broadcast,
3042                             &ns->eth.rx_broadcast);
3043         /* Workaround: CRC size should not be included in byte statistics,
3044          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3045          * packet.
3046          */
3047         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3048                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3049
3050         /* exclude internal rx bytes
3051          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3052          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3053          * value.
3054          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3055          */
3056         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3057                 ns->eth.rx_bytes = 0;
3058         else
3059                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3060
3061         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3062                 ns->eth.rx_unicast = 0;
3063         else
3064                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3065
3066         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3067                 ns->eth.rx_multicast = 0;
3068         else
3069                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3070
3071         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3072                 ns->eth.rx_broadcast = 0;
3073         else
3074                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3075
3076         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3077                             pf->offset_loaded, &os->eth.rx_discards,
3078                             &ns->eth.rx_discards);
3079         /* GLPRT_REPC not supported */
3080         /* GLPRT_RMPC not supported */
3081         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3082                             pf->offset_loaded,
3083                             &os->eth.rx_unknown_protocol,
3084                             &ns->eth.rx_unknown_protocol);
3085         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3086                             I40E_GLPRT_GOTCL(hw->port),
3087                             pf->offset_loaded, &os->eth.tx_bytes,
3088                             &ns->eth.tx_bytes);
3089         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3090                             I40E_GLPRT_UPTCL(hw->port),
3091                             pf->offset_loaded, &os->eth.tx_unicast,
3092                             &ns->eth.tx_unicast);
3093         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3094                             I40E_GLPRT_MPTCL(hw->port),
3095                             pf->offset_loaded, &os->eth.tx_multicast,
3096                             &ns->eth.tx_multicast);
3097         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3098                             I40E_GLPRT_BPTCL(hw->port),
3099                             pf->offset_loaded, &os->eth.tx_broadcast,
3100                             &ns->eth.tx_broadcast);
3101         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3102                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3103
3104         /* exclude internal tx bytes
3105          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3106          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3107          * value.
3108          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3109          */
3110         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3111                 ns->eth.tx_bytes = 0;
3112         else
3113                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3114
3115         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3116                 ns->eth.tx_unicast = 0;
3117         else
3118                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3119
3120         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3121                 ns->eth.tx_multicast = 0;
3122         else
3123                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3124
3125         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3126                 ns->eth.tx_broadcast = 0;
3127         else
3128                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3129
3130         /* GLPRT_TEPC not supported */
3131
3132         /* additional port specific stats */
3133         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3134                             pf->offset_loaded, &os->tx_dropped_link_down,
3135                             &ns->tx_dropped_link_down);
3136         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3137                             pf->offset_loaded, &os->crc_errors,
3138                             &ns->crc_errors);
3139         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3140                             pf->offset_loaded, &os->illegal_bytes,
3141                             &ns->illegal_bytes);
3142         /* GLPRT_ERRBC not supported */
3143         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3144                             pf->offset_loaded, &os->mac_local_faults,
3145                             &ns->mac_local_faults);
3146         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3147                             pf->offset_loaded, &os->mac_remote_faults,
3148                             &ns->mac_remote_faults);
3149         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3150                             pf->offset_loaded, &os->rx_length_errors,
3151                             &ns->rx_length_errors);
3152         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3153                             pf->offset_loaded, &os->link_xon_rx,
3154                             &ns->link_xon_rx);
3155         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3156                             pf->offset_loaded, &os->link_xoff_rx,
3157                             &ns->link_xoff_rx);
3158         for (i = 0; i < 8; i++) {
3159                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3160                                     pf->offset_loaded,
3161                                     &os->priority_xon_rx[i],
3162                                     &ns->priority_xon_rx[i]);
3163                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3164                                     pf->offset_loaded,
3165                                     &os->priority_xoff_rx[i],
3166                                     &ns->priority_xoff_rx[i]);
3167         }
3168         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3169                             pf->offset_loaded, &os->link_xon_tx,
3170                             &ns->link_xon_tx);
3171         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3172                             pf->offset_loaded, &os->link_xoff_tx,
3173                             &ns->link_xoff_tx);
3174         for (i = 0; i < 8; i++) {
3175                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3176                                     pf->offset_loaded,
3177                                     &os->priority_xon_tx[i],
3178                                     &ns->priority_xon_tx[i]);
3179                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3180                                     pf->offset_loaded,
3181                                     &os->priority_xoff_tx[i],
3182                                     &ns->priority_xoff_tx[i]);
3183                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3184                                     pf->offset_loaded,
3185                                     &os->priority_xon_2_xoff[i],
3186                                     &ns->priority_xon_2_xoff[i]);
3187         }
3188         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3189                             I40E_GLPRT_PRC64L(hw->port),
3190                             pf->offset_loaded, &os->rx_size_64,
3191                             &ns->rx_size_64);
3192         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3193                             I40E_GLPRT_PRC127L(hw->port),
3194                             pf->offset_loaded, &os->rx_size_127,
3195                             &ns->rx_size_127);
3196         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3197                             I40E_GLPRT_PRC255L(hw->port),
3198                             pf->offset_loaded, &os->rx_size_255,
3199                             &ns->rx_size_255);
3200         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3201                             I40E_GLPRT_PRC511L(hw->port),
3202                             pf->offset_loaded, &os->rx_size_511,
3203                             &ns->rx_size_511);
3204         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3205                             I40E_GLPRT_PRC1023L(hw->port),
3206                             pf->offset_loaded, &os->rx_size_1023,
3207                             &ns->rx_size_1023);
3208         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3209                             I40E_GLPRT_PRC1522L(hw->port),
3210                             pf->offset_loaded, &os->rx_size_1522,
3211                             &ns->rx_size_1522);
3212         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3213                             I40E_GLPRT_PRC9522L(hw->port),
3214                             pf->offset_loaded, &os->rx_size_big,
3215                             &ns->rx_size_big);
3216         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3217                             pf->offset_loaded, &os->rx_undersize,
3218                             &ns->rx_undersize);
3219         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3220                             pf->offset_loaded, &os->rx_fragments,
3221                             &ns->rx_fragments);
3222         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3223                             pf->offset_loaded, &os->rx_oversize,
3224                             &ns->rx_oversize);
3225         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3226                             pf->offset_loaded, &os->rx_jabber,
3227                             &ns->rx_jabber);
3228         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3229                             I40E_GLPRT_PTC64L(hw->port),
3230                             pf->offset_loaded, &os->tx_size_64,
3231                             &ns->tx_size_64);
3232         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3233                             I40E_GLPRT_PTC127L(hw->port),
3234                             pf->offset_loaded, &os->tx_size_127,
3235                             &ns->tx_size_127);
3236         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3237                             I40E_GLPRT_PTC255L(hw->port),
3238                             pf->offset_loaded, &os->tx_size_255,
3239                             &ns->tx_size_255);
3240         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3241                             I40E_GLPRT_PTC511L(hw->port),
3242                             pf->offset_loaded, &os->tx_size_511,
3243                             &ns->tx_size_511);
3244         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3245                             I40E_GLPRT_PTC1023L(hw->port),
3246                             pf->offset_loaded, &os->tx_size_1023,
3247                             &ns->tx_size_1023);
3248         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3249                             I40E_GLPRT_PTC1522L(hw->port),
3250                             pf->offset_loaded, &os->tx_size_1522,
3251                             &ns->tx_size_1522);
3252         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3253                             I40E_GLPRT_PTC9522L(hw->port),
3254                             pf->offset_loaded, &os->tx_size_big,
3255                             &ns->tx_size_big);
3256         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3257                            pf->offset_loaded,
3258                            &os->fd_sb_match, &ns->fd_sb_match);
3259         /* GLPRT_MSPDC not supported */
3260         /* GLPRT_XEC not supported */
3261
3262         pf->offset_loaded = true;
3263
3264         if (pf->main_vsi)
3265                 i40e_update_vsi_stats(pf->main_vsi);
3266 }
3267
3268 /* Get all statistics of a port */
3269 static int
3270 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3271 {
3272         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3273         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3274         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3275         struct i40e_vsi *vsi;
3276         unsigned i;
3277
3278         /* call read registers - updates values, now write them to struct */
3279         i40e_read_stats_registers(pf, hw);
3280
3281         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3282                         pf->main_vsi->eth_stats.rx_multicast +
3283                         pf->main_vsi->eth_stats.rx_broadcast -
3284                         pf->main_vsi->eth_stats.rx_discards;
3285         stats->opackets = ns->eth.tx_unicast +
3286                         ns->eth.tx_multicast +
3287                         ns->eth.tx_broadcast;
3288         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3289         stats->obytes   = ns->eth.tx_bytes;
3290         stats->oerrors  = ns->eth.tx_errors +
3291                         pf->main_vsi->eth_stats.tx_errors;
3292
3293         /* Rx Errors */
3294         stats->imissed  = ns->eth.rx_discards +
3295                         pf->main_vsi->eth_stats.rx_discards;
3296         stats->ierrors  = ns->crc_errors +
3297                         ns->rx_length_errors + ns->rx_undersize +
3298                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3299
3300         if (pf->vfs) {
3301                 for (i = 0; i < pf->vf_num; i++) {
3302                         vsi = pf->vfs[i].vsi;
3303                         i40e_update_vsi_stats(vsi);
3304
3305                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3306                                         vsi->eth_stats.rx_multicast +
3307                                         vsi->eth_stats.rx_broadcast -
3308                                         vsi->eth_stats.rx_discards);
3309                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3310                         stats->oerrors  += vsi->eth_stats.tx_errors;
3311                         stats->imissed  += vsi->eth_stats.rx_discards;
3312                 }
3313         }
3314
3315         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3316         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3317         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3318         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3319         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3320         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3321         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3322                     ns->eth.rx_unknown_protocol);
3323         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3324         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3325         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3326         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3327         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3328         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3329
3330         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3331                     ns->tx_dropped_link_down);
3332         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3333         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3334                     ns->illegal_bytes);
3335         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3336         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3337                     ns->mac_local_faults);
3338         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3339                     ns->mac_remote_faults);
3340         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3341                     ns->rx_length_errors);
3342         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3343         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3344         for (i = 0; i < 8; i++) {
3345                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3346                                 i, ns->priority_xon_rx[i]);
3347                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3348                                 i, ns->priority_xoff_rx[i]);
3349         }
3350         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3351         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3352         for (i = 0; i < 8; i++) {
3353                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3354                                 i, ns->priority_xon_tx[i]);
3355                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3356                                 i, ns->priority_xoff_tx[i]);
3357                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3358                                 i, ns->priority_xon_2_xoff[i]);
3359         }
3360         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3361         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3362         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3363         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3364         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3365         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3366         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3367         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3368         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3369         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3370         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3371         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3372         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3373         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3374         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3375         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3376         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3377         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3378         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3379                         ns->mac_short_packet_dropped);
3380         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3381                     ns->checksum_error);
3382         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3383         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3384         return 0;
3385 }
3386
3387 /* Reset the statistics */
3388 static int
3389 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3390 {
3391         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3392         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3393
3394         /* Mark PF and VSI stats to update the offset, aka "reset" */
3395         pf->offset_loaded = false;
3396         if (pf->main_vsi)
3397                 pf->main_vsi->offset_loaded = false;
3398
3399         /* read the stats, reading current register values into offset */
3400         i40e_read_stats_registers(pf, hw);
3401
3402         return 0;
3403 }
3404
3405 static uint32_t
3406 i40e_xstats_calc_num(void)
3407 {
3408         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3409                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3410                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3411 }
3412
3413 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3414                                      struct rte_eth_xstat_name *xstats_names,
3415                                      __rte_unused unsigned limit)
3416 {
3417         unsigned count = 0;
3418         unsigned i, prio;
3419
3420         if (xstats_names == NULL)
3421                 return i40e_xstats_calc_num();
3422
3423         /* Note: limit checked in rte_eth_xstats_names() */
3424
3425         /* Get stats from i40e_eth_stats struct */
3426         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3427                 strlcpy(xstats_names[count].name,
3428                         rte_i40e_stats_strings[i].name,
3429                         sizeof(xstats_names[count].name));
3430                 count++;
3431         }
3432
3433         /* Get individiual stats from i40e_hw_port struct */
3434         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3435                 strlcpy(xstats_names[count].name,
3436                         rte_i40e_hw_port_strings[i].name,
3437                         sizeof(xstats_names[count].name));
3438                 count++;
3439         }
3440
3441         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3442                 for (prio = 0; prio < 8; prio++) {
3443                         snprintf(xstats_names[count].name,
3444                                  sizeof(xstats_names[count].name),
3445                                  "rx_priority%u_%s", prio,
3446                                  rte_i40e_rxq_prio_strings[i].name);
3447                         count++;
3448                 }
3449         }
3450
3451         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3452                 for (prio = 0; prio < 8; prio++) {
3453                         snprintf(xstats_names[count].name,
3454                                  sizeof(xstats_names[count].name),
3455                                  "tx_priority%u_%s", prio,
3456                                  rte_i40e_txq_prio_strings[i].name);
3457                         count++;
3458                 }
3459         }
3460         return count;
3461 }
3462
3463 static int
3464 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3465                     unsigned n)
3466 {
3467         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3468         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3469         unsigned i, count, prio;
3470         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3471
3472         count = i40e_xstats_calc_num();
3473         if (n < count)
3474                 return count;
3475
3476         i40e_read_stats_registers(pf, hw);
3477
3478         if (xstats == NULL)
3479                 return 0;
3480
3481         count = 0;
3482
3483         /* Get stats from i40e_eth_stats struct */
3484         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3485                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3486                         rte_i40e_stats_strings[i].offset);
3487                 xstats[count].id = count;
3488                 count++;
3489         }
3490
3491         /* Get individiual stats from i40e_hw_port struct */
3492         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3493                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3494                         rte_i40e_hw_port_strings[i].offset);
3495                 xstats[count].id = count;
3496                 count++;
3497         }
3498
3499         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3500                 for (prio = 0; prio < 8; prio++) {
3501                         xstats[count].value =
3502                                 *(uint64_t *)(((char *)hw_stats) +
3503                                 rte_i40e_rxq_prio_strings[i].offset +
3504                                 (sizeof(uint64_t) * prio));
3505                         xstats[count].id = count;
3506                         count++;
3507                 }
3508         }
3509
3510         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3511                 for (prio = 0; prio < 8; prio++) {
3512                         xstats[count].value =
3513                                 *(uint64_t *)(((char *)hw_stats) +
3514                                 rte_i40e_txq_prio_strings[i].offset +
3515                                 (sizeof(uint64_t) * prio));
3516                         xstats[count].id = count;
3517                         count++;
3518                 }
3519         }
3520
3521         return count;
3522 }
3523
3524 static int
3525 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3526 {
3527         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3528         u32 full_ver;
3529         u8 ver, patch;
3530         u16 build;
3531         int ret;
3532
3533         full_ver = hw->nvm.oem_ver;
3534         ver = (u8)(full_ver >> 24);
3535         build = (u16)((full_ver >> 8) & 0xffff);
3536         patch = (u8)(full_ver & 0xff);
3537
3538         ret = snprintf(fw_version, fw_size,
3539                  "%d.%d%d 0x%08x %d.%d.%d",
3540                  ((hw->nvm.version >> 12) & 0xf),
3541                  ((hw->nvm.version >> 4) & 0xff),
3542                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3543                  ver, build, patch);
3544
3545         ret += 1; /* add the size of '\0' */
3546         if (fw_size < (u32)ret)
3547                 return ret;
3548         else
3549                 return 0;
3550 }
3551
3552 /*
3553  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3554  * the Rx data path does not hang if the FW LLDP is stopped.
3555  * return true if lldp need to stop
3556  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3557  */
3558 static bool
3559 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3560 {
3561         double nvm_ver;
3562         char ver_str[64] = {0};
3563         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3564
3565         i40e_fw_version_get(dev, ver_str, 64);
3566         nvm_ver = atof(ver_str);
3567         if ((hw->mac.type == I40E_MAC_X722 ||
3568              hw->mac.type == I40E_MAC_X722_VF) &&
3569              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3570                 return true;
3571         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3572                 return true;
3573
3574         return false;
3575 }
3576
3577 static int
3578 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3579 {
3580         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3581         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3582         struct i40e_vsi *vsi = pf->main_vsi;
3583         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3584
3585         dev_info->max_rx_queues = vsi->nb_qps;
3586         dev_info->max_tx_queues = vsi->nb_qps;
3587         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3588         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3589         dev_info->max_mac_addrs = vsi->max_macaddrs;
3590         dev_info->max_vfs = pci_dev->max_vfs;
3591         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3592         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3593         dev_info->rx_queue_offload_capa = 0;
3594         dev_info->rx_offload_capa =
3595                 DEV_RX_OFFLOAD_VLAN_STRIP |
3596                 DEV_RX_OFFLOAD_QINQ_STRIP |
3597                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3598                 DEV_RX_OFFLOAD_UDP_CKSUM |
3599                 DEV_RX_OFFLOAD_TCP_CKSUM |
3600                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3601                 DEV_RX_OFFLOAD_KEEP_CRC |
3602                 DEV_RX_OFFLOAD_SCATTER |
3603                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3604                 DEV_RX_OFFLOAD_VLAN_FILTER |
3605                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3606
3607         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3608         dev_info->tx_offload_capa =
3609                 DEV_TX_OFFLOAD_VLAN_INSERT |
3610                 DEV_TX_OFFLOAD_QINQ_INSERT |
3611                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3612                 DEV_TX_OFFLOAD_UDP_CKSUM |
3613                 DEV_TX_OFFLOAD_TCP_CKSUM |
3614                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3615                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3616                 DEV_TX_OFFLOAD_TCP_TSO |
3617                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3618                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3619                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3620                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3621                 DEV_TX_OFFLOAD_MULTI_SEGS |
3622                 dev_info->tx_queue_offload_capa;
3623         dev_info->dev_capa =
3624                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3625                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3626
3627         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3628                                                 sizeof(uint32_t);
3629         dev_info->reta_size = pf->hash_lut_size;
3630         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3631
3632         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3633                 .rx_thresh = {
3634                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3635                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3636                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3637                 },
3638                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3639                 .rx_drop_en = 0,
3640                 .offloads = 0,
3641         };
3642
3643         dev_info->default_txconf = (struct rte_eth_txconf) {
3644                 .tx_thresh = {
3645                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3646                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3647                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3648                 },
3649                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3650                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3651                 .offloads = 0,
3652         };
3653
3654         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3655                 .nb_max = I40E_MAX_RING_DESC,
3656                 .nb_min = I40E_MIN_RING_DESC,
3657                 .nb_align = I40E_ALIGN_RING_DESC,
3658         };
3659
3660         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3661                 .nb_max = I40E_MAX_RING_DESC,
3662                 .nb_min = I40E_MIN_RING_DESC,
3663                 .nb_align = I40E_ALIGN_RING_DESC,
3664                 .nb_seg_max = I40E_TX_MAX_SEG,
3665                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3666         };
3667
3668         if (pf->flags & I40E_FLAG_VMDQ) {
3669                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3670                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3671                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3672                                                 pf->max_nb_vmdq_vsi;
3673                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3674                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3675                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3676         }
3677
3678         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3679                 /* For XL710 */
3680                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3681                 dev_info->default_rxportconf.nb_queues = 2;
3682                 dev_info->default_txportconf.nb_queues = 2;
3683                 if (dev->data->nb_rx_queues == 1)
3684                         dev_info->default_rxportconf.ring_size = 2048;
3685                 else
3686                         dev_info->default_rxportconf.ring_size = 1024;
3687                 if (dev->data->nb_tx_queues == 1)
3688                         dev_info->default_txportconf.ring_size = 1024;
3689                 else
3690                         dev_info->default_txportconf.ring_size = 512;
3691
3692         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3693                 /* For XXV710 */
3694                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3695                 dev_info->default_rxportconf.nb_queues = 1;
3696                 dev_info->default_txportconf.nb_queues = 1;
3697                 dev_info->default_rxportconf.ring_size = 256;
3698                 dev_info->default_txportconf.ring_size = 256;
3699         } else {
3700                 /* For X710 */
3701                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3702                 dev_info->default_rxportconf.nb_queues = 1;
3703                 dev_info->default_txportconf.nb_queues = 1;
3704                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3705                         dev_info->default_rxportconf.ring_size = 512;
3706                         dev_info->default_txportconf.ring_size = 256;
3707                 } else {
3708                         dev_info->default_rxportconf.ring_size = 256;
3709                         dev_info->default_txportconf.ring_size = 256;
3710                 }
3711         }
3712         dev_info->default_rxportconf.burst_size = 32;
3713         dev_info->default_txportconf.burst_size = 32;
3714
3715         return 0;
3716 }
3717
3718 static int
3719 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3720 {
3721         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3722         struct i40e_vsi *vsi = pf->main_vsi;
3723         PMD_INIT_FUNC_TRACE();
3724
3725         if (on)
3726                 return i40e_vsi_add_vlan(vsi, vlan_id);
3727         else
3728                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3729 }
3730
3731 static int
3732 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3733                                 enum rte_vlan_type vlan_type,
3734                                 uint16_t tpid, int qinq)
3735 {
3736         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3737         uint64_t reg_r = 0;
3738         uint64_t reg_w = 0;
3739         uint16_t reg_id = 3;
3740         int ret;
3741
3742         if (qinq) {
3743                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3744                         reg_id = 2;
3745         }
3746
3747         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3748                                           &reg_r, NULL);
3749         if (ret != I40E_SUCCESS) {
3750                 PMD_DRV_LOG(ERR,
3751                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3752                            reg_id);
3753                 return -EIO;
3754         }
3755         PMD_DRV_LOG(DEBUG,
3756                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3757                     reg_id, reg_r);
3758
3759         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3760         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3761         if (reg_r == reg_w) {
3762                 PMD_DRV_LOG(DEBUG, "No need to write");
3763                 return 0;
3764         }
3765
3766         ret = i40e_aq_debug_write_global_register(hw,
3767                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3768                                            reg_w, NULL);
3769         if (ret != I40E_SUCCESS) {
3770                 PMD_DRV_LOG(ERR,
3771                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3772                             reg_id);
3773                 return -EIO;
3774         }
3775         PMD_DRV_LOG(DEBUG,
3776                     "Global register 0x%08x is changed with value 0x%08x",
3777                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3778
3779         return 0;
3780 }
3781
3782 static int
3783 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3784                    enum rte_vlan_type vlan_type,
3785                    uint16_t tpid)
3786 {
3787         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3788         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3789         int qinq = dev->data->dev_conf.rxmode.offloads &
3790                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3791         int ret = 0;
3792
3793         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3794              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3795             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3796                 PMD_DRV_LOG(ERR,
3797                             "Unsupported vlan type.");
3798                 return -EINVAL;
3799         }
3800
3801         if (pf->support_multi_driver) {
3802                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3803                 return -ENOTSUP;
3804         }
3805
3806         /* 802.1ad frames ability is added in NVM API 1.7*/
3807         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3808                 if (qinq) {
3809                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3810                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3811                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3812                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3813                 } else {
3814                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3815                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3816                 }
3817                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3818                 if (ret != I40E_SUCCESS) {
3819                         PMD_DRV_LOG(ERR,
3820                                     "Set switch config failed aq_err: %d",
3821                                     hw->aq.asq_last_status);
3822                         ret = -EIO;
3823                 }
3824         } else
3825                 /* If NVM API < 1.7, keep the register setting */
3826                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3827                                                       tpid, qinq);
3828
3829         return ret;
3830 }
3831
3832 static int
3833 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3834 {
3835         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3836         struct i40e_vsi *vsi = pf->main_vsi;
3837         struct rte_eth_rxmode *rxmode;
3838
3839         rxmode = &dev->data->dev_conf.rxmode;
3840         if (mask & ETH_VLAN_FILTER_MASK) {
3841                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3842                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3843                 else
3844                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3845         }
3846
3847         if (mask & ETH_VLAN_STRIP_MASK) {
3848                 /* Enable or disable VLAN stripping */
3849                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3850                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3851                 else
3852                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3853         }
3854
3855         if (mask & ETH_VLAN_EXTEND_MASK) {
3856                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3857                         i40e_vsi_config_double_vlan(vsi, TRUE);
3858                         /* Set global registers with default ethertype. */
3859                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3860                                            RTE_ETHER_TYPE_VLAN);
3861                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3862                                            RTE_ETHER_TYPE_VLAN);
3863                 }
3864                 else
3865                         i40e_vsi_config_double_vlan(vsi, FALSE);
3866         }
3867
3868         return 0;
3869 }
3870
3871 static void
3872 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3873                           __rte_unused uint16_t queue,
3874                           __rte_unused int on)
3875 {
3876         PMD_INIT_FUNC_TRACE();
3877 }
3878
3879 static int
3880 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3881 {
3882         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3883         struct i40e_vsi *vsi = pf->main_vsi;
3884         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3885         struct i40e_vsi_vlan_pvid_info info;
3886
3887         memset(&info, 0, sizeof(info));
3888         info.on = on;
3889         if (info.on)
3890                 info.config.pvid = pvid;
3891         else {
3892                 info.config.reject.tagged =
3893                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3894                 info.config.reject.untagged =
3895                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3896         }
3897
3898         return i40e_vsi_vlan_pvid_set(vsi, &info);
3899 }
3900
3901 static int
3902 i40e_dev_led_on(struct rte_eth_dev *dev)
3903 {
3904         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3905         uint32_t mode = i40e_led_get(hw);
3906
3907         if (mode == 0)
3908                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3909
3910         return 0;
3911 }
3912
3913 static int
3914 i40e_dev_led_off(struct rte_eth_dev *dev)
3915 {
3916         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3917         uint32_t mode = i40e_led_get(hw);
3918
3919         if (mode != 0)
3920                 i40e_led_set(hw, 0, false);
3921
3922         return 0;
3923 }
3924
3925 static int
3926 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3927 {
3928         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3929         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3930
3931         fc_conf->pause_time = pf->fc_conf.pause_time;
3932
3933         /* read out from register, in case they are modified by other port */
3934         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3935                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3936         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3937                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3938
3939         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3940         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3941
3942          /* Return current mode according to actual setting*/
3943         switch (hw->fc.current_mode) {
3944         case I40E_FC_FULL:
3945                 fc_conf->mode = RTE_FC_FULL;
3946                 break;
3947         case I40E_FC_TX_PAUSE:
3948                 fc_conf->mode = RTE_FC_TX_PAUSE;
3949                 break;
3950         case I40E_FC_RX_PAUSE:
3951                 fc_conf->mode = RTE_FC_RX_PAUSE;
3952                 break;
3953         case I40E_FC_NONE:
3954         default:
3955                 fc_conf->mode = RTE_FC_NONE;
3956         };
3957
3958         return 0;
3959 }
3960
3961 static int
3962 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3963 {
3964         uint32_t mflcn_reg, fctrl_reg, reg;
3965         uint32_t max_high_water;
3966         uint8_t i, aq_failure;
3967         int err;
3968         struct i40e_hw *hw;
3969         struct i40e_pf *pf;
3970         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3971                 [RTE_FC_NONE] = I40E_FC_NONE,
3972                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3973                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3974                 [RTE_FC_FULL] = I40E_FC_FULL
3975         };
3976
3977         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3978
3979         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3980         if ((fc_conf->high_water > max_high_water) ||
3981                         (fc_conf->high_water < fc_conf->low_water)) {
3982                 PMD_INIT_LOG(ERR,
3983                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3984                         max_high_water);
3985                 return -EINVAL;
3986         }
3987
3988         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3989         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3990         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3991
3992         pf->fc_conf.pause_time = fc_conf->pause_time;
3993         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3994         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3995
3996         PMD_INIT_FUNC_TRACE();
3997
3998         /* All the link flow control related enable/disable register
3999          * configuration is handle by the F/W
4000          */
4001         err = i40e_set_fc(hw, &aq_failure, true);
4002         if (err < 0)
4003                 return -ENOSYS;
4004
4005         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4006                 /* Configure flow control refresh threshold,
4007                  * the value for stat_tx_pause_refresh_timer[8]
4008                  * is used for global pause operation.
4009                  */
4010
4011                 I40E_WRITE_REG(hw,
4012                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4013                                pf->fc_conf.pause_time);
4014
4015                 /* configure the timer value included in transmitted pause
4016                  * frame,
4017                  * the value for stat_tx_pause_quanta[8] is used for global
4018                  * pause operation
4019                  */
4020                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4021                                pf->fc_conf.pause_time);
4022
4023                 fctrl_reg = I40E_READ_REG(hw,
4024                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4025
4026                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4027                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4028                 else
4029                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4030
4031                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4032                                fctrl_reg);
4033         } else {
4034                 /* Configure pause time (2 TCs per register) */
4035                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4036                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4037                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4038
4039                 /* Configure flow control refresh threshold value */
4040                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4041                                pf->fc_conf.pause_time / 2);
4042
4043                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4044
4045                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4046                  *depending on configuration
4047                  */
4048                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4049                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4050                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4051                 } else {
4052                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4053                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4054                 }
4055
4056                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4057         }
4058
4059         if (!pf->support_multi_driver) {
4060                 /* config water marker both based on the packets and bytes */
4061                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4062                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4063                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4064                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4065                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4066                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4067                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4068                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4069                                   << I40E_KILOSHIFT);
4070                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4071                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4072                                    << I40E_KILOSHIFT);
4073         } else {
4074                 PMD_DRV_LOG(ERR,
4075                             "Water marker configuration is not supported.");
4076         }
4077
4078         I40E_WRITE_FLUSH(hw);
4079
4080         return 0;
4081 }
4082
4083 static int
4084 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4085                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4086 {
4087         PMD_INIT_FUNC_TRACE();
4088
4089         return -ENOSYS;
4090 }
4091
4092 /* Add a MAC address, and update filters */
4093 static int
4094 i40e_macaddr_add(struct rte_eth_dev *dev,
4095                  struct rte_ether_addr *mac_addr,
4096                  __rte_unused uint32_t index,
4097                  uint32_t pool)
4098 {
4099         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4100         struct i40e_mac_filter_info mac_filter;
4101         struct i40e_vsi *vsi;
4102         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4103         int ret;
4104
4105         /* If VMDQ not enabled or configured, return */
4106         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4107                           !pf->nb_cfg_vmdq_vsi)) {
4108                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4109                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4110                         pool);
4111                 return -ENOTSUP;
4112         }
4113
4114         if (pool > pf->nb_cfg_vmdq_vsi) {
4115                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4116                                 pool, pf->nb_cfg_vmdq_vsi);
4117                 return -EINVAL;
4118         }
4119
4120         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4121         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4122                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4123         else
4124                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4125
4126         if (pool == 0)
4127                 vsi = pf->main_vsi;
4128         else
4129                 vsi = pf->vmdq[pool - 1].vsi;
4130
4131         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4132         if (ret != I40E_SUCCESS) {
4133                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4134                 return -ENODEV;
4135         }
4136         return 0;
4137 }
4138
4139 /* Remove a MAC address, and update filters */
4140 static void
4141 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4142 {
4143         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4144         struct i40e_vsi *vsi;
4145         struct rte_eth_dev_data *data = dev->data;
4146         struct rte_ether_addr *macaddr;
4147         int ret;
4148         uint32_t i;
4149         uint64_t pool_sel;
4150
4151         macaddr = &(data->mac_addrs[index]);
4152
4153         pool_sel = dev->data->mac_pool_sel[index];
4154
4155         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4156                 if (pool_sel & (1ULL << i)) {
4157                         if (i == 0)
4158                                 vsi = pf->main_vsi;
4159                         else {
4160                                 /* No VMDQ pool enabled or configured */
4161                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4162                                         (i > pf->nb_cfg_vmdq_vsi)) {
4163                                         PMD_DRV_LOG(ERR,
4164                                                 "No VMDQ pool enabled/configured");
4165                                         return;
4166                                 }
4167                                 vsi = pf->vmdq[i - 1].vsi;
4168                         }
4169                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4170
4171                         if (ret) {
4172                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4173                                 return;
4174                         }
4175                 }
4176         }
4177 }
4178
4179 /* Set perfect match or hash match of MAC and VLAN for a VF */
4180 static int
4181 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4182                  struct rte_eth_mac_filter *filter,
4183                  bool add)
4184 {
4185         struct i40e_hw *hw;
4186         struct i40e_mac_filter_info mac_filter;
4187         struct rte_ether_addr old_mac;
4188         struct rte_ether_addr *new_mac;
4189         struct i40e_pf_vf *vf = NULL;
4190         uint16_t vf_id;
4191         int ret;
4192
4193         if (pf == NULL) {
4194                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4195                 return -EINVAL;
4196         }
4197         hw = I40E_PF_TO_HW(pf);
4198
4199         if (filter == NULL) {
4200                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4201                 return -EINVAL;
4202         }
4203
4204         new_mac = &filter->mac_addr;
4205
4206         if (rte_is_zero_ether_addr(new_mac)) {
4207                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4208                 return -EINVAL;
4209         }
4210
4211         vf_id = filter->dst_id;
4212
4213         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4214                 PMD_DRV_LOG(ERR, "Invalid argument.");
4215                 return -EINVAL;
4216         }
4217         vf = &pf->vfs[vf_id];
4218
4219         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4220                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4221                 return -EINVAL;
4222         }
4223
4224         if (add) {
4225                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4226                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4227                                 RTE_ETHER_ADDR_LEN);
4228                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4229                                  RTE_ETHER_ADDR_LEN);
4230
4231                 mac_filter.filter_type = filter->filter_type;
4232                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4233                 if (ret != I40E_SUCCESS) {
4234                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4235                         return -1;
4236                 }
4237                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4238         } else {
4239                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4240                                 RTE_ETHER_ADDR_LEN);
4241                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4242                 if (ret != I40E_SUCCESS) {
4243                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4244                         return -1;
4245                 }
4246
4247                 /* Clear device address as it has been removed */
4248                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4249                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4250         }
4251
4252         return 0;
4253 }
4254
4255 /* MAC filter handle */
4256 static int
4257 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4258                 void *arg)
4259 {
4260         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4261         struct rte_eth_mac_filter *filter;
4262         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4263         int ret = I40E_NOT_SUPPORTED;
4264
4265         filter = (struct rte_eth_mac_filter *)(arg);
4266
4267         switch (filter_op) {
4268         case RTE_ETH_FILTER_NOP:
4269                 ret = I40E_SUCCESS;
4270                 break;
4271         case RTE_ETH_FILTER_ADD:
4272                 i40e_pf_disable_irq0(hw);
4273                 if (filter->is_vf)
4274                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4275                 i40e_pf_enable_irq0(hw);
4276                 break;
4277         case RTE_ETH_FILTER_DELETE:
4278                 i40e_pf_disable_irq0(hw);
4279                 if (filter->is_vf)
4280                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4281                 i40e_pf_enable_irq0(hw);
4282                 break;
4283         default:
4284                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4285                 ret = I40E_ERR_PARAM;
4286                 break;
4287         }
4288
4289         return ret;
4290 }
4291
4292 static int
4293 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4294 {
4295         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4296         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4297         uint32_t reg;
4298         int ret;
4299
4300         if (!lut)
4301                 return -EINVAL;
4302
4303         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4304                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4305                                           vsi->type != I40E_VSI_SRIOV,
4306                                           lut, lut_size);
4307                 if (ret) {
4308                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4309                         return ret;
4310                 }
4311         } else {
4312                 uint32_t *lut_dw = (uint32_t *)lut;
4313                 uint16_t i, lut_size_dw = lut_size / 4;
4314
4315                 if (vsi->type == I40E_VSI_SRIOV) {
4316                         for (i = 0; i <= lut_size_dw; i++) {
4317                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4318                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4319                         }
4320                 } else {
4321                         for (i = 0; i < lut_size_dw; i++)
4322                                 lut_dw[i] = I40E_READ_REG(hw,
4323                                                           I40E_PFQF_HLUT(i));
4324                 }
4325         }
4326
4327         return 0;
4328 }
4329
4330 int
4331 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4332 {
4333         struct i40e_pf *pf;
4334         struct i40e_hw *hw;
4335         int ret;
4336
4337         if (!vsi || !lut)
4338                 return -EINVAL;
4339
4340         pf = I40E_VSI_TO_PF(vsi);
4341         hw = I40E_VSI_TO_HW(vsi);
4342
4343         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4344                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4345                                           vsi->type != I40E_VSI_SRIOV,
4346                                           lut, lut_size);
4347                 if (ret) {
4348                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4349                         return ret;
4350                 }
4351         } else {
4352                 uint32_t *lut_dw = (uint32_t *)lut;
4353                 uint16_t i, lut_size_dw = lut_size / 4;
4354
4355                 if (vsi->type == I40E_VSI_SRIOV) {
4356                         for (i = 0; i < lut_size_dw; i++)
4357                                 I40E_WRITE_REG(
4358                                         hw,
4359                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4360                                         lut_dw[i]);
4361                 } else {
4362                         for (i = 0; i < lut_size_dw; i++)
4363                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4364                                                lut_dw[i]);
4365                 }
4366                 I40E_WRITE_FLUSH(hw);
4367         }
4368
4369         return 0;
4370 }
4371
4372 static int
4373 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4374                          struct rte_eth_rss_reta_entry64 *reta_conf,
4375                          uint16_t reta_size)
4376 {
4377         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4378         uint16_t i, lut_size = pf->hash_lut_size;
4379         uint16_t idx, shift;
4380         uint8_t *lut;
4381         int ret;
4382
4383         if (reta_size != lut_size ||
4384                 reta_size > ETH_RSS_RETA_SIZE_512) {
4385                 PMD_DRV_LOG(ERR,
4386                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4387                         reta_size, lut_size);
4388                 return -EINVAL;
4389         }
4390
4391         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4392         if (!lut) {
4393                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4394                 return -ENOMEM;
4395         }
4396         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4397         if (ret)
4398                 goto out;
4399         for (i = 0; i < reta_size; i++) {
4400                 idx = i / RTE_RETA_GROUP_SIZE;
4401                 shift = i % RTE_RETA_GROUP_SIZE;
4402                 if (reta_conf[idx].mask & (1ULL << shift))
4403                         lut[i] = reta_conf[idx].reta[shift];
4404         }
4405         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4406
4407         pf->adapter->rss_reta_updated = 1;
4408
4409 out:
4410         rte_free(lut);
4411
4412         return ret;
4413 }
4414
4415 static int
4416 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4417                         struct rte_eth_rss_reta_entry64 *reta_conf,
4418                         uint16_t reta_size)
4419 {
4420         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4421         uint16_t i, lut_size = pf->hash_lut_size;
4422         uint16_t idx, shift;
4423         uint8_t *lut;
4424         int ret;
4425
4426         if (reta_size != lut_size ||
4427                 reta_size > ETH_RSS_RETA_SIZE_512) {
4428                 PMD_DRV_LOG(ERR,
4429                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4430                         reta_size, lut_size);
4431                 return -EINVAL;
4432         }
4433
4434         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4435         if (!lut) {
4436                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4437                 return -ENOMEM;
4438         }
4439
4440         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4441         if (ret)
4442                 goto out;
4443         for (i = 0; i < reta_size; i++) {
4444                 idx = i / RTE_RETA_GROUP_SIZE;
4445                 shift = i % RTE_RETA_GROUP_SIZE;
4446                 if (reta_conf[idx].mask & (1ULL << shift))
4447                         reta_conf[idx].reta[shift] = lut[i];
4448         }
4449
4450 out:
4451         rte_free(lut);
4452
4453         return ret;
4454 }
4455
4456 /**
4457  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4458  * @hw:   pointer to the HW structure
4459  * @mem:  pointer to mem struct to fill out
4460  * @size: size of memory requested
4461  * @alignment: what to align the allocation to
4462  **/
4463 enum i40e_status_code
4464 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4465                         struct i40e_dma_mem *mem,
4466                         u64 size,
4467                         u32 alignment)
4468 {
4469         const struct rte_memzone *mz = NULL;
4470         char z_name[RTE_MEMZONE_NAMESIZE];
4471
4472         if (!mem)
4473                 return I40E_ERR_PARAM;
4474
4475         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4476         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4477                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4478         if (!mz)
4479                 return I40E_ERR_NO_MEMORY;
4480
4481         mem->size = size;
4482         mem->va = mz->addr;
4483         mem->pa = mz->iova;
4484         mem->zone = (const void *)mz;
4485         PMD_DRV_LOG(DEBUG,
4486                 "memzone %s allocated with physical address: %"PRIu64,
4487                 mz->name, mem->pa);
4488
4489         return I40E_SUCCESS;
4490 }
4491
4492 /**
4493  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4494  * @hw:   pointer to the HW structure
4495  * @mem:  ptr to mem struct to free
4496  **/
4497 enum i40e_status_code
4498 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4499                     struct i40e_dma_mem *mem)
4500 {
4501         if (!mem)
4502                 return I40E_ERR_PARAM;
4503
4504         PMD_DRV_LOG(DEBUG,
4505                 "memzone %s to be freed with physical address: %"PRIu64,
4506                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4507         rte_memzone_free((const struct rte_memzone *)mem->zone);
4508         mem->zone = NULL;
4509         mem->va = NULL;
4510         mem->pa = (u64)0;
4511
4512         return I40E_SUCCESS;
4513 }
4514
4515 /**
4516  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4517  * @hw:   pointer to the HW structure
4518  * @mem:  pointer to mem struct to fill out
4519  * @size: size of memory requested
4520  **/
4521 enum i40e_status_code
4522 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4523                          struct i40e_virt_mem *mem,
4524                          u32 size)
4525 {
4526         if (!mem)
4527                 return I40E_ERR_PARAM;
4528
4529         mem->size = size;
4530         mem->va = rte_zmalloc("i40e", size, 0);
4531
4532         if (mem->va)
4533                 return I40E_SUCCESS;
4534         else
4535                 return I40E_ERR_NO_MEMORY;
4536 }
4537
4538 /**
4539  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4540  * @hw:   pointer to the HW structure
4541  * @mem:  pointer to mem struct to free
4542  **/
4543 enum i40e_status_code
4544 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4545                      struct i40e_virt_mem *mem)
4546 {
4547         if (!mem)
4548                 return I40E_ERR_PARAM;
4549
4550         rte_free(mem->va);
4551         mem->va = NULL;
4552
4553         return I40E_SUCCESS;
4554 }
4555
4556 void
4557 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4558 {
4559         rte_spinlock_init(&sp->spinlock);
4560 }
4561
4562 void
4563 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4564 {
4565         rte_spinlock_lock(&sp->spinlock);
4566 }
4567
4568 void
4569 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4570 {
4571         rte_spinlock_unlock(&sp->spinlock);
4572 }
4573
4574 void
4575 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4576 {
4577         return;
4578 }
4579
4580 /**
4581  * Get the hardware capabilities, which will be parsed
4582  * and saved into struct i40e_hw.
4583  */
4584 static int
4585 i40e_get_cap(struct i40e_hw *hw)
4586 {
4587         struct i40e_aqc_list_capabilities_element_resp *buf;
4588         uint16_t len, size = 0;
4589         int ret;
4590
4591         /* Calculate a huge enough buff for saving response data temporarily */
4592         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4593                                                 I40E_MAX_CAP_ELE_NUM;
4594         buf = rte_zmalloc("i40e", len, 0);
4595         if (!buf) {
4596                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4597                 return I40E_ERR_NO_MEMORY;
4598         }
4599
4600         /* Get, parse the capabilities and save it to hw */
4601         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4602                         i40e_aqc_opc_list_func_capabilities, NULL);
4603         if (ret != I40E_SUCCESS)
4604                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4605
4606         /* Free the temporary buffer after being used */
4607         rte_free(buf);
4608
4609         return ret;
4610 }
4611
4612 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4613
4614 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4615                 const char *value,
4616                 void *opaque)
4617 {
4618         struct i40e_pf *pf;
4619         unsigned long num;
4620         char *end;
4621
4622         pf = (struct i40e_pf *)opaque;
4623         RTE_SET_USED(key);
4624
4625         errno = 0;
4626         num = strtoul(value, &end, 0);
4627         if (errno != 0 || end == value || *end != 0) {
4628                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4629                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4630                 return -(EINVAL);
4631         }
4632
4633         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4634                 pf->vf_nb_qp_max = (uint16_t)num;
4635         else
4636                 /* here return 0 to make next valid same argument work */
4637                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4638                             "power of 2 and equal or less than 16 !, Now it is "
4639                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4640
4641         return 0;
4642 }
4643
4644 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4645 {
4646         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4647         struct rte_kvargs *kvlist;
4648         int kvargs_count;
4649
4650         /* set default queue number per VF as 4 */
4651         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4652
4653         if (dev->device->devargs == NULL)
4654                 return 0;
4655
4656         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4657         if (kvlist == NULL)
4658                 return -(EINVAL);
4659
4660         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4661         if (!kvargs_count) {
4662                 rte_kvargs_free(kvlist);
4663                 return 0;
4664         }
4665
4666         if (kvargs_count > 1)
4667                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4668                             "the first invalid or last valid one is used !",
4669                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4670
4671         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4672                            i40e_pf_parse_vf_queue_number_handler, pf);
4673
4674         rte_kvargs_free(kvlist);
4675
4676         return 0;
4677 }
4678
4679 static int
4680 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4681 {
4682         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4683         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4684         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4685         uint16_t qp_count = 0, vsi_count = 0;
4686
4687         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4688                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4689                 return -EINVAL;
4690         }
4691
4692         i40e_pf_config_vf_rxq_number(dev);
4693
4694         /* Add the parameter init for LFC */
4695         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4696         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4697         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4698
4699         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4700         pf->max_num_vsi = hw->func_caps.num_vsis;
4701         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4702         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4703
4704         /* FDir queue/VSI allocation */
4705         pf->fdir_qp_offset = 0;
4706         if (hw->func_caps.fd) {
4707                 pf->flags |= I40E_FLAG_FDIR;
4708                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4709         } else {
4710                 pf->fdir_nb_qps = 0;
4711         }
4712         qp_count += pf->fdir_nb_qps;
4713         vsi_count += 1;
4714
4715         /* LAN queue/VSI allocation */
4716         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4717         if (!hw->func_caps.rss) {
4718                 pf->lan_nb_qps = 1;
4719         } else {
4720                 pf->flags |= I40E_FLAG_RSS;
4721                 if (hw->mac.type == I40E_MAC_X722)
4722                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4723                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4724         }
4725         qp_count += pf->lan_nb_qps;
4726         vsi_count += 1;
4727
4728         /* VF queue/VSI allocation */
4729         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4730         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4731                 pf->flags |= I40E_FLAG_SRIOV;
4732                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4733                 pf->vf_num = pci_dev->max_vfs;
4734                 PMD_DRV_LOG(DEBUG,
4735                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4736                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4737         } else {
4738                 pf->vf_nb_qps = 0;
4739                 pf->vf_num = 0;
4740         }
4741         qp_count += pf->vf_nb_qps * pf->vf_num;
4742         vsi_count += pf->vf_num;
4743
4744         /* VMDq queue/VSI allocation */
4745         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4746         pf->vmdq_nb_qps = 0;
4747         pf->max_nb_vmdq_vsi = 0;
4748         if (hw->func_caps.vmdq) {
4749                 if (qp_count < hw->func_caps.num_tx_qp &&
4750                         vsi_count < hw->func_caps.num_vsis) {
4751                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4752                                 qp_count) / pf->vmdq_nb_qp_max;
4753
4754                         /* Limit the maximum number of VMDq vsi to the maximum
4755                          * ethdev can support
4756                          */
4757                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4758                                 hw->func_caps.num_vsis - vsi_count);
4759                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4760                                 ETH_64_POOLS);
4761                         if (pf->max_nb_vmdq_vsi) {
4762                                 pf->flags |= I40E_FLAG_VMDQ;
4763                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4764                                 PMD_DRV_LOG(DEBUG,
4765                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4766                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4767                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4768                         } else {
4769                                 PMD_DRV_LOG(INFO,
4770                                         "No enough queues left for VMDq");
4771                         }
4772                 } else {
4773                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4774                 }
4775         }
4776         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4777         vsi_count += pf->max_nb_vmdq_vsi;
4778
4779         if (hw->func_caps.dcb)
4780                 pf->flags |= I40E_FLAG_DCB;
4781
4782         if (qp_count > hw->func_caps.num_tx_qp) {
4783                 PMD_DRV_LOG(ERR,
4784                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4785                         qp_count, hw->func_caps.num_tx_qp);
4786                 return -EINVAL;
4787         }
4788         if (vsi_count > hw->func_caps.num_vsis) {
4789                 PMD_DRV_LOG(ERR,
4790                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4791                         vsi_count, hw->func_caps.num_vsis);
4792                 return -EINVAL;
4793         }
4794
4795         return 0;
4796 }
4797
4798 static int
4799 i40e_pf_get_switch_config(struct i40e_pf *pf)
4800 {
4801         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4802         struct i40e_aqc_get_switch_config_resp *switch_config;
4803         struct i40e_aqc_switch_config_element_resp *element;
4804         uint16_t start_seid = 0, num_reported;
4805         int ret;
4806
4807         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4808                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4809         if (!switch_config) {
4810                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4811                 return -ENOMEM;
4812         }
4813
4814         /* Get the switch configurations */
4815         ret = i40e_aq_get_switch_config(hw, switch_config,
4816                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4817         if (ret != I40E_SUCCESS) {
4818                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4819                 goto fail;
4820         }
4821         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4822         if (num_reported != 1) { /* The number should be 1 */
4823                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4824                 goto fail;
4825         }
4826
4827         /* Parse the switch configuration elements */
4828         element = &(switch_config->element[0]);
4829         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4830                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4831                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4832         } else
4833                 PMD_DRV_LOG(INFO, "Unknown element type");
4834
4835 fail:
4836         rte_free(switch_config);
4837
4838         return ret;
4839 }
4840
4841 static int
4842 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4843                         uint32_t num)
4844 {
4845         struct pool_entry *entry;
4846
4847         if (pool == NULL || num == 0)
4848                 return -EINVAL;
4849
4850         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4851         if (entry == NULL) {
4852                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4853                 return -ENOMEM;
4854         }
4855
4856         /* queue heap initialize */
4857         pool->num_free = num;
4858         pool->num_alloc = 0;
4859         pool->base = base;
4860         LIST_INIT(&pool->alloc_list);
4861         LIST_INIT(&pool->free_list);
4862
4863         /* Initialize element  */
4864         entry->base = 0;
4865         entry->len = num;
4866
4867         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4868         return 0;
4869 }
4870
4871 static void
4872 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4873 {
4874         struct pool_entry *entry, *next_entry;
4875
4876         if (pool == NULL)
4877                 return;
4878
4879         for (entry = LIST_FIRST(&pool->alloc_list);
4880                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4881                         entry = next_entry) {
4882                 LIST_REMOVE(entry, next);
4883                 rte_free(entry);
4884         }
4885
4886         for (entry = LIST_FIRST(&pool->free_list);
4887                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4888                         entry = next_entry) {
4889                 LIST_REMOVE(entry, next);
4890                 rte_free(entry);
4891         }
4892
4893         pool->num_free = 0;
4894         pool->num_alloc = 0;
4895         pool->base = 0;
4896         LIST_INIT(&pool->alloc_list);
4897         LIST_INIT(&pool->free_list);
4898 }
4899
4900 static int
4901 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4902                        uint32_t base)
4903 {
4904         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4905         uint32_t pool_offset;
4906         int insert;
4907
4908         if (pool == NULL) {
4909                 PMD_DRV_LOG(ERR, "Invalid parameter");
4910                 return -EINVAL;
4911         }
4912
4913         pool_offset = base - pool->base;
4914         /* Lookup in alloc list */
4915         LIST_FOREACH(entry, &pool->alloc_list, next) {
4916                 if (entry->base == pool_offset) {
4917                         valid_entry = entry;
4918                         LIST_REMOVE(entry, next);
4919                         break;
4920                 }
4921         }
4922
4923         /* Not find, return */
4924         if (valid_entry == NULL) {
4925                 PMD_DRV_LOG(ERR, "Failed to find entry");
4926                 return -EINVAL;
4927         }
4928
4929         /**
4930          * Found it, move it to free list  and try to merge.
4931          * In order to make merge easier, always sort it by qbase.
4932          * Find adjacent prev and last entries.
4933          */
4934         prev = next = NULL;
4935         LIST_FOREACH(entry, &pool->free_list, next) {
4936                 if (entry->base > valid_entry->base) {
4937                         next = entry;
4938                         break;
4939                 }
4940                 prev = entry;
4941         }
4942
4943         insert = 0;
4944         /* Try to merge with next one*/
4945         if (next != NULL) {
4946                 /* Merge with next one */
4947                 if (valid_entry->base + valid_entry->len == next->base) {
4948                         next->base = valid_entry->base;
4949                         next->len += valid_entry->len;
4950                         rte_free(valid_entry);
4951                         valid_entry = next;
4952                         insert = 1;
4953                 }
4954         }
4955
4956         if (prev != NULL) {
4957                 /* Merge with previous one */
4958                 if (prev->base + prev->len == valid_entry->base) {
4959                         prev->len += valid_entry->len;
4960                         /* If it merge with next one, remove next node */
4961                         if (insert == 1) {
4962                                 LIST_REMOVE(valid_entry, next);
4963                                 rte_free(valid_entry);
4964                         } else {
4965                                 rte_free(valid_entry);
4966                                 insert = 1;
4967                         }
4968                 }
4969         }
4970
4971         /* Not find any entry to merge, insert */
4972         if (insert == 0) {
4973                 if (prev != NULL)
4974                         LIST_INSERT_AFTER(prev, valid_entry, next);
4975                 else if (next != NULL)
4976                         LIST_INSERT_BEFORE(next, valid_entry, next);
4977                 else /* It's empty list, insert to head */
4978                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4979         }
4980
4981         pool->num_free += valid_entry->len;
4982         pool->num_alloc -= valid_entry->len;
4983
4984         return 0;
4985 }
4986
4987 static int
4988 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4989                        uint16_t num)
4990 {
4991         struct pool_entry *entry, *valid_entry;
4992
4993         if (pool == NULL || num == 0) {
4994                 PMD_DRV_LOG(ERR, "Invalid parameter");
4995                 return -EINVAL;
4996         }
4997
4998         if (pool->num_free < num) {
4999                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5000                             num, pool->num_free);
5001                 return -ENOMEM;
5002         }
5003
5004         valid_entry = NULL;
5005         /* Lookup  in free list and find most fit one */
5006         LIST_FOREACH(entry, &pool->free_list, next) {
5007                 if (entry->len >= num) {
5008                         /* Find best one */
5009                         if (entry->len == num) {
5010                                 valid_entry = entry;
5011                                 break;
5012                         }
5013                         if (valid_entry == NULL || valid_entry->len > entry->len)
5014                                 valid_entry = entry;
5015                 }
5016         }
5017
5018         /* Not find one to satisfy the request, return */
5019         if (valid_entry == NULL) {
5020                 PMD_DRV_LOG(ERR, "No valid entry found");
5021                 return -ENOMEM;
5022         }
5023         /**
5024          * The entry have equal queue number as requested,
5025          * remove it from alloc_list.
5026          */
5027         if (valid_entry->len == num) {
5028                 LIST_REMOVE(valid_entry, next);
5029         } else {
5030                 /**
5031                  * The entry have more numbers than requested,
5032                  * create a new entry for alloc_list and minus its
5033                  * queue base and number in free_list.
5034                  */
5035                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5036                 if (entry == NULL) {
5037                         PMD_DRV_LOG(ERR,
5038                                 "Failed to allocate memory for resource pool");
5039                         return -ENOMEM;
5040                 }
5041                 entry->base = valid_entry->base;
5042                 entry->len = num;
5043                 valid_entry->base += num;
5044                 valid_entry->len -= num;
5045                 valid_entry = entry;
5046         }
5047
5048         /* Insert it into alloc list, not sorted */
5049         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5050
5051         pool->num_free -= valid_entry->len;
5052         pool->num_alloc += valid_entry->len;
5053
5054         return valid_entry->base + pool->base;
5055 }
5056
5057 /**
5058  * bitmap_is_subset - Check whether src2 is subset of src1
5059  **/
5060 static inline int
5061 bitmap_is_subset(uint8_t src1, uint8_t src2)
5062 {
5063         return !((src1 ^ src2) & src2);
5064 }
5065
5066 static enum i40e_status_code
5067 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5068 {
5069         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5070
5071         /* If DCB is not supported, only default TC is supported */
5072         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5073                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5074                 return I40E_NOT_SUPPORTED;
5075         }
5076
5077         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5078                 PMD_DRV_LOG(ERR,
5079                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5080                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5081                 return I40E_NOT_SUPPORTED;
5082         }
5083         return I40E_SUCCESS;
5084 }
5085
5086 int
5087 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5088                                 struct i40e_vsi_vlan_pvid_info *info)
5089 {
5090         struct i40e_hw *hw;
5091         struct i40e_vsi_context ctxt;
5092         uint8_t vlan_flags = 0;
5093         int ret;
5094
5095         if (vsi == NULL || info == NULL) {
5096                 PMD_DRV_LOG(ERR, "invalid parameters");
5097                 return I40E_ERR_PARAM;
5098         }
5099
5100         if (info->on) {
5101                 vsi->info.pvid = info->config.pvid;
5102                 /**
5103                  * If insert pvid is enabled, only tagged pkts are
5104                  * allowed to be sent out.
5105                  */
5106                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5107                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5108         } else {
5109                 vsi->info.pvid = 0;
5110                 if (info->config.reject.tagged == 0)
5111                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5112
5113                 if (info->config.reject.untagged == 0)
5114                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5115         }
5116         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5117                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5118         vsi->info.port_vlan_flags |= vlan_flags;
5119         vsi->info.valid_sections =
5120                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5121         memset(&ctxt, 0, sizeof(ctxt));
5122         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5123         ctxt.seid = vsi->seid;
5124
5125         hw = I40E_VSI_TO_HW(vsi);
5126         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5127         if (ret != I40E_SUCCESS)
5128                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5129
5130         return ret;
5131 }
5132
5133 static int
5134 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5135 {
5136         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5137         int i, ret;
5138         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5139
5140         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5141         if (ret != I40E_SUCCESS)
5142                 return ret;
5143
5144         if (!vsi->seid) {
5145                 PMD_DRV_LOG(ERR, "seid not valid");
5146                 return -EINVAL;
5147         }
5148
5149         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5150         tc_bw_data.tc_valid_bits = enabled_tcmap;
5151         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5152                 tc_bw_data.tc_bw_credits[i] =
5153                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5154
5155         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5156         if (ret != I40E_SUCCESS) {
5157                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5158                 return ret;
5159         }
5160
5161         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5162                                         sizeof(vsi->info.qs_handle));
5163         return I40E_SUCCESS;
5164 }
5165
5166 static enum i40e_status_code
5167 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5168                                  struct i40e_aqc_vsi_properties_data *info,
5169                                  uint8_t enabled_tcmap)
5170 {
5171         enum i40e_status_code ret;
5172         int i, total_tc = 0;
5173         uint16_t qpnum_per_tc, bsf, qp_idx;
5174
5175         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5176         if (ret != I40E_SUCCESS)
5177                 return ret;
5178
5179         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5180                 if (enabled_tcmap & (1 << i))
5181                         total_tc++;
5182         if (total_tc == 0)
5183                 total_tc = 1;
5184         vsi->enabled_tc = enabled_tcmap;
5185
5186         /* Number of queues per enabled TC */
5187         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5188         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5189         bsf = rte_bsf32(qpnum_per_tc);
5190
5191         /* Adjust the queue number to actual queues that can be applied */
5192         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5193                 vsi->nb_qps = qpnum_per_tc * total_tc;
5194
5195         /**
5196          * Configure TC and queue mapping parameters, for enabled TC,
5197          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5198          * default queue will serve it.
5199          */
5200         qp_idx = 0;
5201         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5202                 if (vsi->enabled_tc & (1 << i)) {
5203                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5204                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5205                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5206                         qp_idx += qpnum_per_tc;
5207                 } else
5208                         info->tc_mapping[i] = 0;
5209         }
5210
5211         /* Associate queue number with VSI */
5212         if (vsi->type == I40E_VSI_SRIOV) {
5213                 info->mapping_flags |=
5214                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5215                 for (i = 0; i < vsi->nb_qps; i++)
5216                         info->queue_mapping[i] =
5217                                 rte_cpu_to_le_16(vsi->base_queue + i);
5218         } else {
5219                 info->mapping_flags |=
5220                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5221                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5222         }
5223         info->valid_sections |=
5224                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5225
5226         return I40E_SUCCESS;
5227 }
5228
5229 static int
5230 i40e_veb_release(struct i40e_veb *veb)
5231 {
5232         struct i40e_vsi *vsi;
5233         struct i40e_hw *hw;
5234
5235         if (veb == NULL)
5236                 return -EINVAL;
5237
5238         if (!TAILQ_EMPTY(&veb->head)) {
5239                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5240                 return -EACCES;
5241         }
5242         /* associate_vsi field is NULL for floating VEB */
5243         if (veb->associate_vsi != NULL) {
5244                 vsi = veb->associate_vsi;
5245                 hw = I40E_VSI_TO_HW(vsi);
5246
5247                 vsi->uplink_seid = veb->uplink_seid;
5248                 vsi->veb = NULL;
5249         } else {
5250                 veb->associate_pf->main_vsi->floating_veb = NULL;
5251                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5252         }
5253
5254         i40e_aq_delete_element(hw, veb->seid, NULL);
5255         rte_free(veb);
5256         return I40E_SUCCESS;
5257 }
5258
5259 /* Setup a veb */
5260 static struct i40e_veb *
5261 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5262 {
5263         struct i40e_veb *veb;
5264         int ret;
5265         struct i40e_hw *hw;
5266
5267         if (pf == NULL) {
5268                 PMD_DRV_LOG(ERR,
5269                             "veb setup failed, associated PF shouldn't null");
5270                 return NULL;
5271         }
5272         hw = I40E_PF_TO_HW(pf);
5273
5274         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5275         if (!veb) {
5276                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5277                 goto fail;
5278         }
5279
5280         veb->associate_vsi = vsi;
5281         veb->associate_pf = pf;
5282         TAILQ_INIT(&veb->head);
5283         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5284
5285         /* create floating veb if vsi is NULL */
5286         if (vsi != NULL) {
5287                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5288                                       I40E_DEFAULT_TCMAP, false,
5289                                       &veb->seid, false, NULL);
5290         } else {
5291                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5292                                       true, &veb->seid, false, NULL);
5293         }
5294
5295         if (ret != I40E_SUCCESS) {
5296                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5297                             hw->aq.asq_last_status);
5298                 goto fail;
5299         }
5300         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5301
5302         /* get statistics index */
5303         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5304                                 &veb->stats_idx, NULL, NULL, NULL);
5305         if (ret != I40E_SUCCESS) {
5306                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5307                             hw->aq.asq_last_status);
5308                 goto fail;
5309         }
5310         /* Get VEB bandwidth, to be implemented */
5311         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5312         if (vsi)
5313                 vsi->uplink_seid = veb->seid;
5314
5315         return veb;
5316 fail:
5317         rte_free(veb);
5318         return NULL;
5319 }
5320
5321 int
5322 i40e_vsi_release(struct i40e_vsi *vsi)
5323 {
5324         struct i40e_pf *pf;
5325         struct i40e_hw *hw;
5326         struct i40e_vsi_list *vsi_list;
5327         void *temp;
5328         int ret;
5329         struct i40e_mac_filter *f;
5330         uint16_t user_param;
5331
5332         if (!vsi)
5333                 return I40E_SUCCESS;
5334
5335         if (!vsi->adapter)
5336                 return -EFAULT;
5337
5338         user_param = vsi->user_param;
5339
5340         pf = I40E_VSI_TO_PF(vsi);
5341         hw = I40E_VSI_TO_HW(vsi);
5342
5343         /* VSI has child to attach, release child first */
5344         if (vsi->veb) {
5345                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5346                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5347                                 return -1;
5348                 }
5349                 i40e_veb_release(vsi->veb);
5350         }
5351
5352         if (vsi->floating_veb) {
5353                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5354                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5355                                 return -1;
5356                 }
5357         }
5358
5359         /* Remove all macvlan filters of the VSI */
5360         i40e_vsi_remove_all_macvlan_filter(vsi);
5361         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5362                 rte_free(f);
5363
5364         if (vsi->type != I40E_VSI_MAIN &&
5365             ((vsi->type != I40E_VSI_SRIOV) ||
5366             !pf->floating_veb_list[user_param])) {
5367                 /* Remove vsi from parent's sibling list */
5368                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5369                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5370                         return I40E_ERR_PARAM;
5371                 }
5372                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5373                                 &vsi->sib_vsi_list, list);
5374
5375                 /* Remove all switch element of the VSI */
5376                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5377                 if (ret != I40E_SUCCESS)
5378                         PMD_DRV_LOG(ERR, "Failed to delete element");
5379         }
5380
5381         if ((vsi->type == I40E_VSI_SRIOV) &&
5382             pf->floating_veb_list[user_param]) {
5383                 /* Remove vsi from parent's sibling list */
5384                 if (vsi->parent_vsi == NULL ||
5385                     vsi->parent_vsi->floating_veb == NULL) {
5386                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5387                         return I40E_ERR_PARAM;
5388                 }
5389                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5390                              &vsi->sib_vsi_list, list);
5391
5392                 /* Remove all switch element of the VSI */
5393                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5394                 if (ret != I40E_SUCCESS)
5395                         PMD_DRV_LOG(ERR, "Failed to delete element");
5396         }
5397
5398         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5399
5400         if (vsi->type != I40E_VSI_SRIOV)
5401                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5402         rte_free(vsi);
5403
5404         return I40E_SUCCESS;
5405 }
5406
5407 static int
5408 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5409 {
5410         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5411         struct i40e_aqc_remove_macvlan_element_data def_filter;
5412         struct i40e_mac_filter_info filter;
5413         int ret;
5414
5415         if (vsi->type != I40E_VSI_MAIN)
5416                 return I40E_ERR_CONFIG;
5417         memset(&def_filter, 0, sizeof(def_filter));
5418         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5419                                         ETH_ADDR_LEN);
5420         def_filter.vlan_tag = 0;
5421         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5422                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5423         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5424         if (ret != I40E_SUCCESS) {
5425                 struct i40e_mac_filter *f;
5426                 struct rte_ether_addr *mac;
5427
5428                 PMD_DRV_LOG(DEBUG,
5429                             "Cannot remove the default macvlan filter");
5430                 /* It needs to add the permanent mac into mac list */
5431                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5432                 if (f == NULL) {
5433                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5434                         return I40E_ERR_NO_MEMORY;
5435                 }
5436                 mac = &f->mac_info.mac_addr;
5437                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5438                                 ETH_ADDR_LEN);
5439                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5440                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5441                 vsi->mac_num++;
5442
5443                 return ret;
5444         }
5445         rte_memcpy(&filter.mac_addr,
5446                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5447         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5448         return i40e_vsi_add_mac(vsi, &filter);
5449 }
5450
5451 /*
5452  * i40e_vsi_get_bw_config - Query VSI BW Information
5453  * @vsi: the VSI to be queried
5454  *
5455  * Returns 0 on success, negative value on failure
5456  */
5457 static enum i40e_status_code
5458 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5459 {
5460         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5461         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5462         struct i40e_hw *hw = &vsi->adapter->hw;
5463         i40e_status ret;
5464         int i;
5465         uint32_t bw_max;
5466
5467         memset(&bw_config, 0, sizeof(bw_config));
5468         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5469         if (ret != I40E_SUCCESS) {
5470                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5471                             hw->aq.asq_last_status);
5472                 return ret;
5473         }
5474
5475         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5476         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5477                                         &ets_sla_config, NULL);
5478         if (ret != I40E_SUCCESS) {
5479                 PMD_DRV_LOG(ERR,
5480                         "VSI failed to get TC bandwdith configuration %u",
5481                         hw->aq.asq_last_status);
5482                 return ret;
5483         }
5484
5485         /* store and print out BW info */
5486         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5487         vsi->bw_info.bw_max = bw_config.max_bw;
5488         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5489         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5490         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5491                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5492                      I40E_16_BIT_WIDTH);
5493         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5494                 vsi->bw_info.bw_ets_share_credits[i] =
5495                                 ets_sla_config.share_credits[i];
5496                 vsi->bw_info.bw_ets_credits[i] =
5497                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5498                 /* 4 bits per TC, 4th bit is reserved */
5499                 vsi->bw_info.bw_ets_max[i] =
5500                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5501                                   RTE_LEN2MASK(3, uint8_t));
5502                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5503                             vsi->bw_info.bw_ets_share_credits[i]);
5504                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5505                             vsi->bw_info.bw_ets_credits[i]);
5506                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5507                             vsi->bw_info.bw_ets_max[i]);
5508         }
5509
5510         return I40E_SUCCESS;
5511 }
5512
5513 /* i40e_enable_pf_lb
5514  * @pf: pointer to the pf structure
5515  *
5516  * allow loopback on pf
5517  */
5518 static inline void
5519 i40e_enable_pf_lb(struct i40e_pf *pf)
5520 {
5521         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5522         struct i40e_vsi_context ctxt;
5523         int ret;
5524
5525         /* Use the FW API if FW >= v5.0 */
5526         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5527                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5528                 return;
5529         }
5530
5531         memset(&ctxt, 0, sizeof(ctxt));
5532         ctxt.seid = pf->main_vsi_seid;
5533         ctxt.pf_num = hw->pf_id;
5534         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5535         if (ret) {
5536                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5537                             ret, hw->aq.asq_last_status);
5538                 return;
5539         }
5540         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5541         ctxt.info.valid_sections =
5542                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5543         ctxt.info.switch_id |=
5544                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5545
5546         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5547         if (ret)
5548                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5549                             hw->aq.asq_last_status);
5550 }
5551
5552 /* Setup a VSI */
5553 struct i40e_vsi *
5554 i40e_vsi_setup(struct i40e_pf *pf,
5555                enum i40e_vsi_type type,
5556                struct i40e_vsi *uplink_vsi,
5557                uint16_t user_param)
5558 {
5559         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5560         struct i40e_vsi *vsi;
5561         struct i40e_mac_filter_info filter;
5562         int ret;
5563         struct i40e_vsi_context ctxt;
5564         struct rte_ether_addr broadcast =
5565                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5566
5567         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5568             uplink_vsi == NULL) {
5569                 PMD_DRV_LOG(ERR,
5570                         "VSI setup failed, VSI link shouldn't be NULL");
5571                 return NULL;
5572         }
5573
5574         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5575                 PMD_DRV_LOG(ERR,
5576                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5577                 return NULL;
5578         }
5579
5580         /* two situations
5581          * 1.type is not MAIN and uplink vsi is not NULL
5582          * If uplink vsi didn't setup VEB, create one first under veb field
5583          * 2.type is SRIOV and the uplink is NULL
5584          * If floating VEB is NULL, create one veb under floating veb field
5585          */
5586
5587         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5588             uplink_vsi->veb == NULL) {
5589                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5590
5591                 if (uplink_vsi->veb == NULL) {
5592                         PMD_DRV_LOG(ERR, "VEB setup failed");
5593                         return NULL;
5594                 }
5595                 /* set ALLOWLOOPBACk on pf, when veb is created */
5596                 i40e_enable_pf_lb(pf);
5597         }
5598
5599         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5600             pf->main_vsi->floating_veb == NULL) {
5601                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5602
5603                 if (pf->main_vsi->floating_veb == NULL) {
5604                         PMD_DRV_LOG(ERR, "VEB setup failed");
5605                         return NULL;
5606                 }
5607         }
5608
5609         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5610         if (!vsi) {
5611                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5612                 return NULL;
5613         }
5614         TAILQ_INIT(&vsi->mac_list);
5615         vsi->type = type;
5616         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5617         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5618         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5619         vsi->user_param = user_param;
5620         vsi->vlan_anti_spoof_on = 0;
5621         vsi->vlan_filter_on = 0;
5622         /* Allocate queues */
5623         switch (vsi->type) {
5624         case I40E_VSI_MAIN  :
5625                 vsi->nb_qps = pf->lan_nb_qps;
5626                 break;
5627         case I40E_VSI_SRIOV :
5628                 vsi->nb_qps = pf->vf_nb_qps;
5629                 break;
5630         case I40E_VSI_VMDQ2:
5631                 vsi->nb_qps = pf->vmdq_nb_qps;
5632                 break;
5633         case I40E_VSI_FDIR:
5634                 vsi->nb_qps = pf->fdir_nb_qps;
5635                 break;
5636         default:
5637                 goto fail_mem;
5638         }
5639         /*
5640          * The filter status descriptor is reported in rx queue 0,
5641          * while the tx queue for fdir filter programming has no
5642          * such constraints, can be non-zero queues.
5643          * To simplify it, choose FDIR vsi use queue 0 pair.
5644          * To make sure it will use queue 0 pair, queue allocation
5645          * need be done before this function is called
5646          */
5647         if (type != I40E_VSI_FDIR) {
5648                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5649                         if (ret < 0) {
5650                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5651                                                 vsi->seid, ret);
5652                                 goto fail_mem;
5653                         }
5654                         vsi->base_queue = ret;
5655         } else
5656                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5657
5658         /* VF has MSIX interrupt in VF range, don't allocate here */
5659         if (type == I40E_VSI_MAIN) {
5660                 if (pf->support_multi_driver) {
5661                         /* If support multi-driver, need to use INT0 instead of
5662                          * allocating from msix pool. The Msix pool is init from
5663                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5664                          * to 1 without calling i40e_res_pool_alloc.
5665                          */
5666                         vsi->msix_intr = 0;
5667                         vsi->nb_msix = 1;
5668                 } else {
5669                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5670                                                   RTE_MIN(vsi->nb_qps,
5671                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5672                         if (ret < 0) {
5673                                 PMD_DRV_LOG(ERR,
5674                                             "VSI MAIN %d get heap failed %d",
5675                                             vsi->seid, ret);
5676                                 goto fail_queue_alloc;
5677                         }
5678                         vsi->msix_intr = ret;
5679                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5680                                                RTE_MAX_RXTX_INTR_VEC_ID);
5681                 }
5682         } else if (type != I40E_VSI_SRIOV) {
5683                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5684                 if (ret < 0) {
5685                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5686                         goto fail_queue_alloc;
5687                 }
5688                 vsi->msix_intr = ret;
5689                 vsi->nb_msix = 1;
5690         } else {
5691                 vsi->msix_intr = 0;
5692                 vsi->nb_msix = 0;
5693         }
5694
5695         /* Add VSI */
5696         if (type == I40E_VSI_MAIN) {
5697                 /* For main VSI, no need to add since it's default one */
5698                 vsi->uplink_seid = pf->mac_seid;
5699                 vsi->seid = pf->main_vsi_seid;
5700                 /* Bind queues with specific MSIX interrupt */
5701                 /**
5702                  * Needs 2 interrupt at least, one for misc cause which will
5703                  * enabled from OS side, Another for queues binding the
5704                  * interrupt from device side only.
5705                  */
5706
5707                 /* Get default VSI parameters from hardware */
5708                 memset(&ctxt, 0, sizeof(ctxt));
5709                 ctxt.seid = vsi->seid;
5710                 ctxt.pf_num = hw->pf_id;
5711                 ctxt.uplink_seid = vsi->uplink_seid;
5712                 ctxt.vf_num = 0;
5713                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5714                 if (ret != I40E_SUCCESS) {
5715                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5716                         goto fail_msix_alloc;
5717                 }
5718                 rte_memcpy(&vsi->info, &ctxt.info,
5719                         sizeof(struct i40e_aqc_vsi_properties_data));
5720                 vsi->vsi_id = ctxt.vsi_number;
5721                 vsi->info.valid_sections = 0;
5722
5723                 /* Configure tc, enabled TC0 only */
5724                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5725                         I40E_SUCCESS) {
5726                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5727                         goto fail_msix_alloc;
5728                 }
5729
5730                 /* TC, queue mapping */
5731                 memset(&ctxt, 0, sizeof(ctxt));
5732                 vsi->info.valid_sections |=
5733                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5734                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5735                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5736                 rte_memcpy(&ctxt.info, &vsi->info,
5737                         sizeof(struct i40e_aqc_vsi_properties_data));
5738                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5739                                                 I40E_DEFAULT_TCMAP);
5740                 if (ret != I40E_SUCCESS) {
5741                         PMD_DRV_LOG(ERR,
5742                                 "Failed to configure TC queue mapping");
5743                         goto fail_msix_alloc;
5744                 }
5745                 ctxt.seid = vsi->seid;
5746                 ctxt.pf_num = hw->pf_id;
5747                 ctxt.uplink_seid = vsi->uplink_seid;
5748                 ctxt.vf_num = 0;
5749
5750                 /* Update VSI parameters */
5751                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5752                 if (ret != I40E_SUCCESS) {
5753                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5754                         goto fail_msix_alloc;
5755                 }
5756
5757                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5758                                                 sizeof(vsi->info.tc_mapping));
5759                 rte_memcpy(&vsi->info.queue_mapping,
5760                                 &ctxt.info.queue_mapping,
5761                         sizeof(vsi->info.queue_mapping));
5762                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5763                 vsi->info.valid_sections = 0;
5764
5765                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5766                                 ETH_ADDR_LEN);
5767
5768                 /**
5769                  * Updating default filter settings are necessary to prevent
5770                  * reception of tagged packets.
5771                  * Some old firmware configurations load a default macvlan
5772                  * filter which accepts both tagged and untagged packets.
5773                  * The updating is to use a normal filter instead if needed.
5774                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5775                  * The firmware with correct configurations load the default
5776                  * macvlan filter which is expected and cannot be removed.
5777                  */
5778                 i40e_update_default_filter_setting(vsi);
5779                 i40e_config_qinq(hw, vsi);
5780         } else if (type == I40E_VSI_SRIOV) {
5781                 memset(&ctxt, 0, sizeof(ctxt));
5782                 /**
5783                  * For other VSI, the uplink_seid equals to uplink VSI's
5784                  * uplink_seid since they share same VEB
5785                  */
5786                 if (uplink_vsi == NULL)
5787                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5788                 else
5789                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5790                 ctxt.pf_num = hw->pf_id;
5791                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5792                 ctxt.uplink_seid = vsi->uplink_seid;
5793                 ctxt.connection_type = 0x1;
5794                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5795
5796                 /* Use the VEB configuration if FW >= v5.0 */
5797                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5798                         /* Configure switch ID */
5799                         ctxt.info.valid_sections |=
5800                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5801                         ctxt.info.switch_id =
5802                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5803                 }
5804
5805                 /* Configure port/vlan */
5806                 ctxt.info.valid_sections |=
5807                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5808                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5809                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5810                                                 hw->func_caps.enabled_tcmap);
5811                 if (ret != I40E_SUCCESS) {
5812                         PMD_DRV_LOG(ERR,
5813                                 "Failed to configure TC queue mapping");
5814                         goto fail_msix_alloc;
5815                 }
5816
5817                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5818                 ctxt.info.valid_sections |=
5819                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5820                 /**
5821                  * Since VSI is not created yet, only configure parameter,
5822                  * will add vsi below.
5823                  */
5824
5825                 i40e_config_qinq(hw, vsi);
5826         } else if (type == I40E_VSI_VMDQ2) {
5827                 memset(&ctxt, 0, sizeof(ctxt));
5828                 /*
5829                  * For other VSI, the uplink_seid equals to uplink VSI's
5830                  * uplink_seid since they share same VEB
5831                  */
5832                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5833                 ctxt.pf_num = hw->pf_id;
5834                 ctxt.vf_num = 0;
5835                 ctxt.uplink_seid = vsi->uplink_seid;
5836                 ctxt.connection_type = 0x1;
5837                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5838
5839                 ctxt.info.valid_sections |=
5840                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5841                 /* user_param carries flag to enable loop back */
5842                 if (user_param) {
5843                         ctxt.info.switch_id =
5844                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5845                         ctxt.info.switch_id |=
5846                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5847                 }
5848
5849                 /* Configure port/vlan */
5850                 ctxt.info.valid_sections |=
5851                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5852                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5853                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5854                                                 I40E_DEFAULT_TCMAP);
5855                 if (ret != I40E_SUCCESS) {
5856                         PMD_DRV_LOG(ERR,
5857                                 "Failed to configure TC queue mapping");
5858                         goto fail_msix_alloc;
5859                 }
5860                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5861                 ctxt.info.valid_sections |=
5862                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5863         } else if (type == I40E_VSI_FDIR) {
5864                 memset(&ctxt, 0, sizeof(ctxt));
5865                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5866                 ctxt.pf_num = hw->pf_id;
5867                 ctxt.vf_num = 0;
5868                 ctxt.uplink_seid = vsi->uplink_seid;
5869                 ctxt.connection_type = 0x1;     /* regular data port */
5870                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5871                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5872                                                 I40E_DEFAULT_TCMAP);
5873                 if (ret != I40E_SUCCESS) {
5874                         PMD_DRV_LOG(ERR,
5875                                 "Failed to configure TC queue mapping.");
5876                         goto fail_msix_alloc;
5877                 }
5878                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5879                 ctxt.info.valid_sections |=
5880                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5881         } else {
5882                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5883                 goto fail_msix_alloc;
5884         }
5885
5886         if (vsi->type != I40E_VSI_MAIN) {
5887                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5888                 if (ret != I40E_SUCCESS) {
5889                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5890                                     hw->aq.asq_last_status);
5891                         goto fail_msix_alloc;
5892                 }
5893                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5894                 vsi->info.valid_sections = 0;
5895                 vsi->seid = ctxt.seid;
5896                 vsi->vsi_id = ctxt.vsi_number;
5897                 vsi->sib_vsi_list.vsi = vsi;
5898                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5899                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5900                                           &vsi->sib_vsi_list, list);
5901                 } else {
5902                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5903                                           &vsi->sib_vsi_list, list);
5904                 }
5905         }
5906
5907         /* MAC/VLAN configuration */
5908         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5909         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5910
5911         ret = i40e_vsi_add_mac(vsi, &filter);
5912         if (ret != I40E_SUCCESS) {
5913                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5914                 goto fail_msix_alloc;
5915         }
5916
5917         /* Get VSI BW information */
5918         i40e_vsi_get_bw_config(vsi);
5919         return vsi;
5920 fail_msix_alloc:
5921         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5922 fail_queue_alloc:
5923         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5924 fail_mem:
5925         rte_free(vsi);
5926         return NULL;
5927 }
5928
5929 /* Configure vlan filter on or off */
5930 int
5931 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5932 {
5933         int i, num;
5934         struct i40e_mac_filter *f;
5935         void *temp;
5936         struct i40e_mac_filter_info *mac_filter;
5937         enum rte_mac_filter_type desired_filter;
5938         int ret = I40E_SUCCESS;
5939
5940         if (on) {
5941                 /* Filter to match MAC and VLAN */
5942                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5943         } else {
5944                 /* Filter to match only MAC */
5945                 desired_filter = RTE_MAC_PERFECT_MATCH;
5946         }
5947
5948         num = vsi->mac_num;
5949
5950         mac_filter = rte_zmalloc("mac_filter_info_data",
5951                                  num * sizeof(*mac_filter), 0);
5952         if (mac_filter == NULL) {
5953                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5954                 return I40E_ERR_NO_MEMORY;
5955         }
5956
5957         i = 0;
5958
5959         /* Remove all existing mac */
5960         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5961                 mac_filter[i] = f->mac_info;
5962                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5963                 if (ret) {
5964                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5965                                     on ? "enable" : "disable");
5966                         goto DONE;
5967                 }
5968                 i++;
5969         }
5970
5971         /* Override with new filter */
5972         for (i = 0; i < num; i++) {
5973                 mac_filter[i].filter_type = desired_filter;
5974                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5975                 if (ret) {
5976                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5977                                     on ? "enable" : "disable");
5978                         goto DONE;
5979                 }
5980         }
5981
5982 DONE:
5983         rte_free(mac_filter);
5984         return ret;
5985 }
5986
5987 /* Configure vlan stripping on or off */
5988 int
5989 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5990 {
5991         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5992         struct i40e_vsi_context ctxt;
5993         uint8_t vlan_flags;
5994         int ret = I40E_SUCCESS;
5995
5996         /* Check if it has been already on or off */
5997         if (vsi->info.valid_sections &
5998                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5999                 if (on) {
6000                         if ((vsi->info.port_vlan_flags &
6001                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6002                                 return 0; /* already on */
6003                 } else {
6004                         if ((vsi->info.port_vlan_flags &
6005                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6006                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6007                                 return 0; /* already off */
6008                 }
6009         }
6010
6011         if (on)
6012                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6013         else
6014                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6015         vsi->info.valid_sections =
6016                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6017         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6018         vsi->info.port_vlan_flags |= vlan_flags;
6019         ctxt.seid = vsi->seid;
6020         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6021         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6022         if (ret)
6023                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6024                             on ? "enable" : "disable");
6025
6026         return ret;
6027 }
6028
6029 static int
6030 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6031 {
6032         struct rte_eth_dev_data *data = dev->data;
6033         int ret;
6034         int mask = 0;
6035
6036         /* Apply vlan offload setting */
6037         mask = ETH_VLAN_STRIP_MASK |
6038                ETH_VLAN_FILTER_MASK |
6039                ETH_VLAN_EXTEND_MASK;
6040         ret = i40e_vlan_offload_set(dev, mask);
6041         if (ret) {
6042                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6043                 return ret;
6044         }
6045
6046         /* Apply pvid setting */
6047         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6048                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6049         if (ret)
6050                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6051
6052         return ret;
6053 }
6054
6055 static int
6056 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6057 {
6058         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6059
6060         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6061 }
6062
6063 static int
6064 i40e_update_flow_control(struct i40e_hw *hw)
6065 {
6066 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6067         struct i40e_link_status link_status;
6068         uint32_t rxfc = 0, txfc = 0, reg;
6069         uint8_t an_info;
6070         int ret;
6071
6072         memset(&link_status, 0, sizeof(link_status));
6073         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6074         if (ret != I40E_SUCCESS) {
6075                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6076                 goto write_reg; /* Disable flow control */
6077         }
6078
6079         an_info = hw->phy.link_info.an_info;
6080         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6081                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6082                 ret = I40E_ERR_NOT_READY;
6083                 goto write_reg; /* Disable flow control */
6084         }
6085         /**
6086          * If link auto negotiation is enabled, flow control needs to
6087          * be configured according to it
6088          */
6089         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6090         case I40E_LINK_PAUSE_RXTX:
6091                 rxfc = 1;
6092                 txfc = 1;
6093                 hw->fc.current_mode = I40E_FC_FULL;
6094                 break;
6095         case I40E_AQ_LINK_PAUSE_RX:
6096                 rxfc = 1;
6097                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6098                 break;
6099         case I40E_AQ_LINK_PAUSE_TX:
6100                 txfc = 1;
6101                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6102                 break;
6103         default:
6104                 hw->fc.current_mode = I40E_FC_NONE;
6105                 break;
6106         }
6107
6108 write_reg:
6109         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6110                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6111         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6112         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6113         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6114         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6115
6116         return ret;
6117 }
6118
6119 /* PF setup */
6120 static int
6121 i40e_pf_setup(struct i40e_pf *pf)
6122 {
6123         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6124         struct i40e_filter_control_settings settings;
6125         struct i40e_vsi *vsi;
6126         int ret;
6127
6128         /* Clear all stats counters */
6129         pf->offset_loaded = FALSE;
6130         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6131         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6132         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6133         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6134
6135         ret = i40e_pf_get_switch_config(pf);
6136         if (ret != I40E_SUCCESS) {
6137                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6138                 return ret;
6139         }
6140
6141         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6142         if (ret)
6143                 PMD_INIT_LOG(WARNING,
6144                         "failed to allocate switch domain for device %d", ret);
6145
6146         if (pf->flags & I40E_FLAG_FDIR) {
6147                 /* make queue allocated first, let FDIR use queue pair 0*/
6148                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6149                 if (ret != I40E_FDIR_QUEUE_ID) {
6150                         PMD_DRV_LOG(ERR,
6151                                 "queue allocation fails for FDIR: ret =%d",
6152                                 ret);
6153                         pf->flags &= ~I40E_FLAG_FDIR;
6154                 }
6155         }
6156         /*  main VSI setup */
6157         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6158         if (!vsi) {
6159                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6160                 return I40E_ERR_NOT_READY;
6161         }
6162         pf->main_vsi = vsi;
6163
6164         /* Configure filter control */
6165         memset(&settings, 0, sizeof(settings));
6166         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6167                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6168         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6169                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6170         else {
6171                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6172                         hw->func_caps.rss_table_size);
6173                 return I40E_ERR_PARAM;
6174         }
6175         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6176                 hw->func_caps.rss_table_size);
6177         pf->hash_lut_size = hw->func_caps.rss_table_size;
6178
6179         /* Enable ethtype and macvlan filters */
6180         settings.enable_ethtype = TRUE;
6181         settings.enable_macvlan = TRUE;
6182         ret = i40e_set_filter_control(hw, &settings);
6183         if (ret)
6184                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6185                                                                 ret);
6186
6187         /* Update flow control according to the auto negotiation */
6188         i40e_update_flow_control(hw);
6189
6190         return I40E_SUCCESS;
6191 }
6192
6193 int
6194 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6195 {
6196         uint32_t reg;
6197         uint16_t j;
6198
6199         /**
6200          * Set or clear TX Queue Disable flags,
6201          * which is required by hardware.
6202          */
6203         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6204         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6205
6206         /* Wait until the request is finished */
6207         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6208                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6209                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6210                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6211                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6212                                                         & 0x1))) {
6213                         break;
6214                 }
6215         }
6216         if (on) {
6217                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6218                         return I40E_SUCCESS; /* already on, skip next steps */
6219
6220                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6221                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6222         } else {
6223                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6224                         return I40E_SUCCESS; /* already off, skip next steps */
6225                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6226         }
6227         /* Write the register */
6228         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6229         /* Check the result */
6230         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6231                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6232                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6233                 if (on) {
6234                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6235                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6236                                 break;
6237                 } else {
6238                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6239                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6240                                 break;
6241                 }
6242         }
6243         /* Check if it is timeout */
6244         if (j >= I40E_CHK_Q_ENA_COUNT) {
6245                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6246                             (on ? "enable" : "disable"), q_idx);
6247                 return I40E_ERR_TIMEOUT;
6248         }
6249
6250         return I40E_SUCCESS;
6251 }
6252
6253 /* Swith on or off the tx queues */
6254 static int
6255 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6256 {
6257         struct rte_eth_dev_data *dev_data = pf->dev_data;
6258         struct i40e_tx_queue *txq;
6259         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6260         uint16_t i;
6261         int ret;
6262
6263         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6264                 txq = dev_data->tx_queues[i];
6265                 /* Don't operate the queue if not configured or
6266                  * if starting only per queue */
6267                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6268                         continue;
6269                 if (on)
6270                         ret = i40e_dev_tx_queue_start(dev, i);
6271                 else
6272                         ret = i40e_dev_tx_queue_stop(dev, i);
6273                 if ( ret != I40E_SUCCESS)
6274                         return ret;
6275         }
6276
6277         return I40E_SUCCESS;
6278 }
6279
6280 int
6281 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6282 {
6283         uint32_t reg;
6284         uint16_t j;
6285
6286         /* Wait until the request is finished */
6287         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6288                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6289                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6290                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6291                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6292                         break;
6293         }
6294
6295         if (on) {
6296                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6297                         return I40E_SUCCESS; /* Already on, skip next steps */
6298                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6299         } else {
6300                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6301                         return I40E_SUCCESS; /* Already off, skip next steps */
6302                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6303         }
6304
6305         /* Write the register */
6306         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6307         /* Check the result */
6308         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6309                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6310                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6311                 if (on) {
6312                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6313                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6314                                 break;
6315                 } else {
6316                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6317                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6318                                 break;
6319                 }
6320         }
6321
6322         /* Check if it is timeout */
6323         if (j >= I40E_CHK_Q_ENA_COUNT) {
6324                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6325                             (on ? "enable" : "disable"), q_idx);
6326                 return I40E_ERR_TIMEOUT;
6327         }
6328
6329         return I40E_SUCCESS;
6330 }
6331 /* Switch on or off the rx queues */
6332 static int
6333 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6334 {
6335         struct rte_eth_dev_data *dev_data = pf->dev_data;
6336         struct i40e_rx_queue *rxq;
6337         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6338         uint16_t i;
6339         int ret;
6340
6341         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6342                 rxq = dev_data->rx_queues[i];
6343                 /* Don't operate the queue if not configured or
6344                  * if starting only per queue */
6345                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6346                         continue;
6347                 if (on)
6348                         ret = i40e_dev_rx_queue_start(dev, i);
6349                 else
6350                         ret = i40e_dev_rx_queue_stop(dev, i);
6351                 if (ret != I40E_SUCCESS)
6352                         return ret;
6353         }
6354
6355         return I40E_SUCCESS;
6356 }
6357
6358 /* Switch on or off all the rx/tx queues */
6359 int
6360 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6361 {
6362         int ret;
6363
6364         if (on) {
6365                 /* enable rx queues before enabling tx queues */
6366                 ret = i40e_dev_switch_rx_queues(pf, on);
6367                 if (ret) {
6368                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6369                         return ret;
6370                 }
6371                 ret = i40e_dev_switch_tx_queues(pf, on);
6372         } else {
6373                 /* Stop tx queues before stopping rx queues */
6374                 ret = i40e_dev_switch_tx_queues(pf, on);
6375                 if (ret) {
6376                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6377                         return ret;
6378                 }
6379                 ret = i40e_dev_switch_rx_queues(pf, on);
6380         }
6381
6382         return ret;
6383 }
6384
6385 /* Initialize VSI for TX */
6386 static int
6387 i40e_dev_tx_init(struct i40e_pf *pf)
6388 {
6389         struct rte_eth_dev_data *data = pf->dev_data;
6390         uint16_t i;
6391         uint32_t ret = I40E_SUCCESS;
6392         struct i40e_tx_queue *txq;
6393
6394         for (i = 0; i < data->nb_tx_queues; i++) {
6395                 txq = data->tx_queues[i];
6396                 if (!txq || !txq->q_set)
6397                         continue;
6398                 ret = i40e_tx_queue_init(txq);
6399                 if (ret != I40E_SUCCESS)
6400                         break;
6401         }
6402         if (ret == I40E_SUCCESS)
6403                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6404                                      ->eth_dev);
6405
6406         return ret;
6407 }
6408
6409 /* Initialize VSI for RX */
6410 static int
6411 i40e_dev_rx_init(struct i40e_pf *pf)
6412 {
6413         struct rte_eth_dev_data *data = pf->dev_data;
6414         int ret = I40E_SUCCESS;
6415         uint16_t i;
6416         struct i40e_rx_queue *rxq;
6417
6418         i40e_pf_config_mq_rx(pf);
6419         for (i = 0; i < data->nb_rx_queues; i++) {
6420                 rxq = data->rx_queues[i];
6421                 if (!rxq || !rxq->q_set)
6422                         continue;
6423
6424                 ret = i40e_rx_queue_init(rxq);
6425                 if (ret != I40E_SUCCESS) {
6426                         PMD_DRV_LOG(ERR,
6427                                 "Failed to do RX queue initialization");
6428                         break;
6429                 }
6430         }
6431         if (ret == I40E_SUCCESS)
6432                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6433                                      ->eth_dev);
6434
6435         return ret;
6436 }
6437
6438 static int
6439 i40e_dev_rxtx_init(struct i40e_pf *pf)
6440 {
6441         int err;
6442
6443         err = i40e_dev_tx_init(pf);
6444         if (err) {
6445                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6446                 return err;
6447         }
6448         err = i40e_dev_rx_init(pf);
6449         if (err) {
6450                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6451                 return err;
6452         }
6453
6454         return err;
6455 }
6456
6457 static int
6458 i40e_vmdq_setup(struct rte_eth_dev *dev)
6459 {
6460         struct rte_eth_conf *conf = &dev->data->dev_conf;
6461         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6462         int i, err, conf_vsis, j, loop;
6463         struct i40e_vsi *vsi;
6464         struct i40e_vmdq_info *vmdq_info;
6465         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6466         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6467
6468         /*
6469          * Disable interrupt to avoid message from VF. Furthermore, it will
6470          * avoid race condition in VSI creation/destroy.
6471          */
6472         i40e_pf_disable_irq0(hw);
6473
6474         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6475                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6476                 return -ENOTSUP;
6477         }
6478
6479         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6480         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6481                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6482                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6483                         pf->max_nb_vmdq_vsi);
6484                 return -ENOTSUP;
6485         }
6486
6487         if (pf->vmdq != NULL) {
6488                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6489                 return 0;
6490         }
6491
6492         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6493                                 sizeof(*vmdq_info) * conf_vsis, 0);
6494
6495         if (pf->vmdq == NULL) {
6496                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6497                 return -ENOMEM;
6498         }
6499
6500         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6501
6502         /* Create VMDQ VSI */
6503         for (i = 0; i < conf_vsis; i++) {
6504                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6505                                 vmdq_conf->enable_loop_back);
6506                 if (vsi == NULL) {
6507                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6508                         err = -1;
6509                         goto err_vsi_setup;
6510                 }
6511                 vmdq_info = &pf->vmdq[i];
6512                 vmdq_info->pf = pf;
6513                 vmdq_info->vsi = vsi;
6514         }
6515         pf->nb_cfg_vmdq_vsi = conf_vsis;
6516
6517         /* Configure Vlan */
6518         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6519         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6520                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6521                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6522                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6523                                         vmdq_conf->pool_map[i].vlan_id, j);
6524
6525                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6526                                                 vmdq_conf->pool_map[i].vlan_id);
6527                                 if (err) {
6528                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6529                                         err = -1;
6530                                         goto err_vsi_setup;
6531                                 }
6532                         }
6533                 }
6534         }
6535
6536         i40e_pf_enable_irq0(hw);
6537
6538         return 0;
6539
6540 err_vsi_setup:
6541         for (i = 0; i < conf_vsis; i++)
6542                 if (pf->vmdq[i].vsi == NULL)
6543                         break;
6544                 else
6545                         i40e_vsi_release(pf->vmdq[i].vsi);
6546
6547         rte_free(pf->vmdq);
6548         pf->vmdq = NULL;
6549         i40e_pf_enable_irq0(hw);
6550         return err;
6551 }
6552
6553 static void
6554 i40e_stat_update_32(struct i40e_hw *hw,
6555                    uint32_t reg,
6556                    bool offset_loaded,
6557                    uint64_t *offset,
6558                    uint64_t *stat)
6559 {
6560         uint64_t new_data;
6561
6562         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6563         if (!offset_loaded)
6564                 *offset = new_data;
6565
6566         if (new_data >= *offset)
6567                 *stat = (uint64_t)(new_data - *offset);
6568         else
6569                 *stat = (uint64_t)((new_data +
6570                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6571 }
6572
6573 static void
6574 i40e_stat_update_48(struct i40e_hw *hw,
6575                    uint32_t hireg,
6576                    uint32_t loreg,
6577                    bool offset_loaded,
6578                    uint64_t *offset,
6579                    uint64_t *stat)
6580 {
6581         uint64_t new_data;
6582
6583         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6584         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6585                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6586
6587         if (!offset_loaded)
6588                 *offset = new_data;
6589
6590         if (new_data >= *offset)
6591                 *stat = new_data - *offset;
6592         else
6593                 *stat = (uint64_t)((new_data +
6594                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6595
6596         *stat &= I40E_48_BIT_MASK;
6597 }
6598
6599 /* Disable IRQ0 */
6600 void
6601 i40e_pf_disable_irq0(struct i40e_hw *hw)
6602 {
6603         /* Disable all interrupt types */
6604         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6605                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6606         I40E_WRITE_FLUSH(hw);
6607 }
6608
6609 /* Enable IRQ0 */
6610 void
6611 i40e_pf_enable_irq0(struct i40e_hw *hw)
6612 {
6613         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6614                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6615                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6616                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6617         I40E_WRITE_FLUSH(hw);
6618 }
6619
6620 static void
6621 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6622 {
6623         /* read pending request and disable first */
6624         i40e_pf_disable_irq0(hw);
6625         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6626         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6627                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6628
6629         if (no_queue)
6630                 /* Link no queues with irq0 */
6631                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6632                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6633 }
6634
6635 static void
6636 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6637 {
6638         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6639         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6640         int i;
6641         uint16_t abs_vf_id;
6642         uint32_t index, offset, val;
6643
6644         if (!pf->vfs)
6645                 return;
6646         /**
6647          * Try to find which VF trigger a reset, use absolute VF id to access
6648          * since the reg is global register.
6649          */
6650         for (i = 0; i < pf->vf_num; i++) {
6651                 abs_vf_id = hw->func_caps.vf_base_id + i;
6652                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6653                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6654                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6655                 /* VFR event occurred */
6656                 if (val & (0x1 << offset)) {
6657                         int ret;
6658
6659                         /* Clear the event first */
6660                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6661                                                         (0x1 << offset));
6662                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6663                         /**
6664                          * Only notify a VF reset event occurred,
6665                          * don't trigger another SW reset
6666                          */
6667                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6668                         if (ret != I40E_SUCCESS)
6669                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6670                 }
6671         }
6672 }
6673
6674 static void
6675 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6676 {
6677         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6678         int i;
6679
6680         for (i = 0; i < pf->vf_num; i++)
6681                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6682 }
6683
6684 static void
6685 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6686 {
6687         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6688         struct i40e_arq_event_info info;
6689         uint16_t pending, opcode;
6690         int ret;
6691
6692         info.buf_len = I40E_AQ_BUF_SZ;
6693         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6694         if (!info.msg_buf) {
6695                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6696                 return;
6697         }
6698
6699         pending = 1;
6700         while (pending) {
6701                 ret = i40e_clean_arq_element(hw, &info, &pending);
6702
6703                 if (ret != I40E_SUCCESS) {
6704                         PMD_DRV_LOG(INFO,
6705                                 "Failed to read msg from AdminQ, aq_err: %u",
6706                                 hw->aq.asq_last_status);
6707                         break;
6708                 }
6709                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6710
6711                 switch (opcode) {
6712                 case i40e_aqc_opc_send_msg_to_pf:
6713                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6714                         i40e_pf_host_handle_vf_msg(dev,
6715                                         rte_le_to_cpu_16(info.desc.retval),
6716                                         rte_le_to_cpu_32(info.desc.cookie_high),
6717                                         rte_le_to_cpu_32(info.desc.cookie_low),
6718                                         info.msg_buf,
6719                                         info.msg_len);
6720                         break;
6721                 case i40e_aqc_opc_get_link_status:
6722                         ret = i40e_dev_link_update(dev, 0);
6723                         if (!ret)
6724                                 _rte_eth_dev_callback_process(dev,
6725                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6726                         break;
6727                 default:
6728                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6729                                     opcode);
6730                         break;
6731                 }
6732         }
6733         rte_free(info.msg_buf);
6734 }
6735
6736 /**
6737  * Interrupt handler triggered by NIC  for handling
6738  * specific interrupt.
6739  *
6740  * @param handle
6741  *  Pointer to interrupt handle.
6742  * @param param
6743  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6744  *
6745  * @return
6746  *  void
6747  */
6748 static void
6749 i40e_dev_interrupt_handler(void *param)
6750 {
6751         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6752         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6753         uint32_t icr0;
6754
6755         /* Disable interrupt */
6756         i40e_pf_disable_irq0(hw);
6757
6758         /* read out interrupt causes */
6759         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6760
6761         /* No interrupt event indicated */
6762         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6763                 PMD_DRV_LOG(INFO, "No interrupt event");
6764                 goto done;
6765         }
6766         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6767                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6768         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6769                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6770         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6771                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6772         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6773                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6774         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6775                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6776         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6777                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6778         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6779                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6780
6781         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6782                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6783                 i40e_dev_handle_vfr_event(dev);
6784         }
6785         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6786                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6787                 i40e_dev_handle_aq_msg(dev);
6788         }
6789
6790 done:
6791         /* Enable interrupt */
6792         i40e_pf_enable_irq0(hw);
6793 }
6794
6795 static void
6796 i40e_dev_alarm_handler(void *param)
6797 {
6798         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6799         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6800         uint32_t icr0;
6801
6802         /* Disable interrupt */
6803         i40e_pf_disable_irq0(hw);
6804
6805         /* read out interrupt causes */
6806         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6807
6808         /* No interrupt event indicated */
6809         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6810                 goto done;
6811         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6812                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6813         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6814                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6815         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6816                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6817         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6818                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6819         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6820                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6821         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6822                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6823         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6824                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6825
6826         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6827                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6828                 i40e_dev_handle_vfr_event(dev);
6829         }
6830         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6831                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6832                 i40e_dev_handle_aq_msg(dev);
6833         }
6834
6835 done:
6836         /* Enable interrupt */
6837         i40e_pf_enable_irq0(hw);
6838         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6839                           i40e_dev_alarm_handler, dev);
6840 }
6841
6842 int
6843 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6844                          struct i40e_macvlan_filter *filter,
6845                          int total)
6846 {
6847         int ele_num, ele_buff_size;
6848         int num, actual_num, i;
6849         uint16_t flags;
6850         int ret = I40E_SUCCESS;
6851         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6852         struct i40e_aqc_add_macvlan_element_data *req_list;
6853
6854         if (filter == NULL  || total == 0)
6855                 return I40E_ERR_PARAM;
6856         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6857         ele_buff_size = hw->aq.asq_buf_size;
6858
6859         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6860         if (req_list == NULL) {
6861                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6862                 return I40E_ERR_NO_MEMORY;
6863         }
6864
6865         num = 0;
6866         do {
6867                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6868                 memset(req_list, 0, ele_buff_size);
6869
6870                 for (i = 0; i < actual_num; i++) {
6871                         rte_memcpy(req_list[i].mac_addr,
6872                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6873                         req_list[i].vlan_tag =
6874                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6875
6876                         switch (filter[num + i].filter_type) {
6877                         case RTE_MAC_PERFECT_MATCH:
6878                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6879                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6880                                 break;
6881                         case RTE_MACVLAN_PERFECT_MATCH:
6882                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6883                                 break;
6884                         case RTE_MAC_HASH_MATCH:
6885                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6886                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6887                                 break;
6888                         case RTE_MACVLAN_HASH_MATCH:
6889                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6890                                 break;
6891                         default:
6892                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6893                                 ret = I40E_ERR_PARAM;
6894                                 goto DONE;
6895                         }
6896
6897                         req_list[i].queue_number = 0;
6898
6899                         req_list[i].flags = rte_cpu_to_le_16(flags);
6900                 }
6901
6902                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6903                                                 actual_num, NULL);
6904                 if (ret != I40E_SUCCESS) {
6905                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6906                         goto DONE;
6907                 }
6908                 num += actual_num;
6909         } while (num < total);
6910
6911 DONE:
6912         rte_free(req_list);
6913         return ret;
6914 }
6915
6916 int
6917 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6918                             struct i40e_macvlan_filter *filter,
6919                             int total)
6920 {
6921         int ele_num, ele_buff_size;
6922         int num, actual_num, i;
6923         uint16_t flags;
6924         int ret = I40E_SUCCESS;
6925         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6926         struct i40e_aqc_remove_macvlan_element_data *req_list;
6927
6928         if (filter == NULL  || total == 0)
6929                 return I40E_ERR_PARAM;
6930
6931         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6932         ele_buff_size = hw->aq.asq_buf_size;
6933
6934         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6935         if (req_list == NULL) {
6936                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6937                 return I40E_ERR_NO_MEMORY;
6938         }
6939
6940         num = 0;
6941         do {
6942                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6943                 memset(req_list, 0, ele_buff_size);
6944
6945                 for (i = 0; i < actual_num; i++) {
6946                         rte_memcpy(req_list[i].mac_addr,
6947                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6948                         req_list[i].vlan_tag =
6949                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6950
6951                         switch (filter[num + i].filter_type) {
6952                         case RTE_MAC_PERFECT_MATCH:
6953                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6954                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6955                                 break;
6956                         case RTE_MACVLAN_PERFECT_MATCH:
6957                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6958                                 break;
6959                         case RTE_MAC_HASH_MATCH:
6960                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6961                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6962                                 break;
6963                         case RTE_MACVLAN_HASH_MATCH:
6964                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6965                                 break;
6966                         default:
6967                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6968                                 ret = I40E_ERR_PARAM;
6969                                 goto DONE;
6970                         }
6971                         req_list[i].flags = rte_cpu_to_le_16(flags);
6972                 }
6973
6974                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6975                                                 actual_num, NULL);
6976                 if (ret != I40E_SUCCESS) {
6977                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6978                         goto DONE;
6979                 }
6980                 num += actual_num;
6981         } while (num < total);
6982
6983 DONE:
6984         rte_free(req_list);
6985         return ret;
6986 }
6987
6988 /* Find out specific MAC filter */
6989 static struct i40e_mac_filter *
6990 i40e_find_mac_filter(struct i40e_vsi *vsi,
6991                          struct rte_ether_addr *macaddr)
6992 {
6993         struct i40e_mac_filter *f;
6994
6995         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6996                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6997                         return f;
6998         }
6999
7000         return NULL;
7001 }
7002
7003 static bool
7004 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7005                          uint16_t vlan_id)
7006 {
7007         uint32_t vid_idx, vid_bit;
7008
7009         if (vlan_id > ETH_VLAN_ID_MAX)
7010                 return 0;
7011
7012         vid_idx = I40E_VFTA_IDX(vlan_id);
7013         vid_bit = I40E_VFTA_BIT(vlan_id);
7014
7015         if (vsi->vfta[vid_idx] & vid_bit)
7016                 return 1;
7017         else
7018                 return 0;
7019 }
7020
7021 static void
7022 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7023                        uint16_t vlan_id, bool on)
7024 {
7025         uint32_t vid_idx, vid_bit;
7026
7027         vid_idx = I40E_VFTA_IDX(vlan_id);
7028         vid_bit = I40E_VFTA_BIT(vlan_id);
7029
7030         if (on)
7031                 vsi->vfta[vid_idx] |= vid_bit;
7032         else
7033                 vsi->vfta[vid_idx] &= ~vid_bit;
7034 }
7035
7036 void
7037 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7038                      uint16_t vlan_id, bool on)
7039 {
7040         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7041         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7042         int ret;
7043
7044         if (vlan_id > ETH_VLAN_ID_MAX)
7045                 return;
7046
7047         i40e_store_vlan_filter(vsi, vlan_id, on);
7048
7049         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7050                 return;
7051
7052         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7053
7054         if (on) {
7055                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7056                                        &vlan_data, 1, NULL);
7057                 if (ret != I40E_SUCCESS)
7058                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7059         } else {
7060                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7061                                           &vlan_data, 1, NULL);
7062                 if (ret != I40E_SUCCESS)
7063                         PMD_DRV_LOG(ERR,
7064                                     "Failed to remove vlan filter");
7065         }
7066 }
7067
7068 /**
7069  * Find all vlan options for specific mac addr,
7070  * return with actual vlan found.
7071  */
7072 int
7073 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7074                            struct i40e_macvlan_filter *mv_f,
7075                            int num, struct rte_ether_addr *addr)
7076 {
7077         int i;
7078         uint32_t j, k;
7079
7080         /**
7081          * Not to use i40e_find_vlan_filter to decrease the loop time,
7082          * although the code looks complex.
7083           */
7084         if (num < vsi->vlan_num)
7085                 return I40E_ERR_PARAM;
7086
7087         i = 0;
7088         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7089                 if (vsi->vfta[j]) {
7090                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7091                                 if (vsi->vfta[j] & (1 << k)) {
7092                                         if (i > num - 1) {
7093                                                 PMD_DRV_LOG(ERR,
7094                                                         "vlan number doesn't match");
7095                                                 return I40E_ERR_PARAM;
7096                                         }
7097                                         rte_memcpy(&mv_f[i].macaddr,
7098                                                         addr, ETH_ADDR_LEN);
7099                                         mv_f[i].vlan_id =
7100                                                 j * I40E_UINT32_BIT_SIZE + k;
7101                                         i++;
7102                                 }
7103                         }
7104                 }
7105         }
7106         return I40E_SUCCESS;
7107 }
7108
7109 static inline int
7110 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7111                            struct i40e_macvlan_filter *mv_f,
7112                            int num,
7113                            uint16_t vlan)
7114 {
7115         int i = 0;
7116         struct i40e_mac_filter *f;
7117
7118         if (num < vsi->mac_num)
7119                 return I40E_ERR_PARAM;
7120
7121         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7122                 if (i > num - 1) {
7123                         PMD_DRV_LOG(ERR, "buffer number not match");
7124                         return I40E_ERR_PARAM;
7125                 }
7126                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7127                                 ETH_ADDR_LEN);
7128                 mv_f[i].vlan_id = vlan;
7129                 mv_f[i].filter_type = f->mac_info.filter_type;
7130                 i++;
7131         }
7132
7133         return I40E_SUCCESS;
7134 }
7135
7136 static int
7137 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7138 {
7139         int i, j, num;
7140         struct i40e_mac_filter *f;
7141         struct i40e_macvlan_filter *mv_f;
7142         int ret = I40E_SUCCESS;
7143
7144         if (vsi == NULL || vsi->mac_num == 0)
7145                 return I40E_ERR_PARAM;
7146
7147         /* Case that no vlan is set */
7148         if (vsi->vlan_num == 0)
7149                 num = vsi->mac_num;
7150         else
7151                 num = vsi->mac_num * vsi->vlan_num;
7152
7153         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7154         if (mv_f == NULL) {
7155                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7156                 return I40E_ERR_NO_MEMORY;
7157         }
7158
7159         i = 0;
7160         if (vsi->vlan_num == 0) {
7161                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7162                         rte_memcpy(&mv_f[i].macaddr,
7163                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7164                         mv_f[i].filter_type = f->mac_info.filter_type;
7165                         mv_f[i].vlan_id = 0;
7166                         i++;
7167                 }
7168         } else {
7169                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7170                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7171                                         vsi->vlan_num, &f->mac_info.mac_addr);
7172                         if (ret != I40E_SUCCESS)
7173                                 goto DONE;
7174                         for (j = i; j < i + vsi->vlan_num; j++)
7175                                 mv_f[j].filter_type = f->mac_info.filter_type;
7176                         i += vsi->vlan_num;
7177                 }
7178         }
7179
7180         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7181 DONE:
7182         rte_free(mv_f);
7183
7184         return ret;
7185 }
7186
7187 int
7188 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7189 {
7190         struct i40e_macvlan_filter *mv_f;
7191         int mac_num;
7192         int ret = I40E_SUCCESS;
7193
7194         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7195                 return I40E_ERR_PARAM;
7196
7197         /* If it's already set, just return */
7198         if (i40e_find_vlan_filter(vsi,vlan))
7199                 return I40E_SUCCESS;
7200
7201         mac_num = vsi->mac_num;
7202
7203         if (mac_num == 0) {
7204                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7205                 return I40E_ERR_PARAM;
7206         }
7207
7208         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7209
7210         if (mv_f == NULL) {
7211                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7212                 return I40E_ERR_NO_MEMORY;
7213         }
7214
7215         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7216
7217         if (ret != I40E_SUCCESS)
7218                 goto DONE;
7219
7220         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7221
7222         if (ret != I40E_SUCCESS)
7223                 goto DONE;
7224
7225         i40e_set_vlan_filter(vsi, vlan, 1);
7226
7227         vsi->vlan_num++;
7228         ret = I40E_SUCCESS;
7229 DONE:
7230         rte_free(mv_f);
7231         return ret;
7232 }
7233
7234 int
7235 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7236 {
7237         struct i40e_macvlan_filter *mv_f;
7238         int mac_num;
7239         int ret = I40E_SUCCESS;
7240
7241         /**
7242          * Vlan 0 is the generic filter for untagged packets
7243          * and can't be removed.
7244          */
7245         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7246                 return I40E_ERR_PARAM;
7247
7248         /* If can't find it, just return */
7249         if (!i40e_find_vlan_filter(vsi, vlan))
7250                 return I40E_ERR_PARAM;
7251
7252         mac_num = vsi->mac_num;
7253
7254         if (mac_num == 0) {
7255                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7256                 return I40E_ERR_PARAM;
7257         }
7258
7259         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7260
7261         if (mv_f == NULL) {
7262                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7263                 return I40E_ERR_NO_MEMORY;
7264         }
7265
7266         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7267
7268         if (ret != I40E_SUCCESS)
7269                 goto DONE;
7270
7271         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7272
7273         if (ret != I40E_SUCCESS)
7274                 goto DONE;
7275
7276         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7277         if (vsi->vlan_num == 1) {
7278                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7279                 if (ret != I40E_SUCCESS)
7280                         goto DONE;
7281
7282                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7283                 if (ret != I40E_SUCCESS)
7284                         goto DONE;
7285         }
7286
7287         i40e_set_vlan_filter(vsi, vlan, 0);
7288
7289         vsi->vlan_num--;
7290         ret = I40E_SUCCESS;
7291 DONE:
7292         rte_free(mv_f);
7293         return ret;
7294 }
7295
7296 int
7297 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7298 {
7299         struct i40e_mac_filter *f;
7300         struct i40e_macvlan_filter *mv_f;
7301         int i, vlan_num = 0;
7302         int ret = I40E_SUCCESS;
7303
7304         /* If it's add and we've config it, return */
7305         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7306         if (f != NULL)
7307                 return I40E_SUCCESS;
7308         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7309                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7310
7311                 /**
7312                  * If vlan_num is 0, that's the first time to add mac,
7313                  * set mask for vlan_id 0.
7314                  */
7315                 if (vsi->vlan_num == 0) {
7316                         i40e_set_vlan_filter(vsi, 0, 1);
7317                         vsi->vlan_num = 1;
7318                 }
7319                 vlan_num = vsi->vlan_num;
7320         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7321                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7322                 vlan_num = 1;
7323
7324         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7325         if (mv_f == NULL) {
7326                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7327                 return I40E_ERR_NO_MEMORY;
7328         }
7329
7330         for (i = 0; i < vlan_num; i++) {
7331                 mv_f[i].filter_type = mac_filter->filter_type;
7332                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7333                                 ETH_ADDR_LEN);
7334         }
7335
7336         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7337                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7338                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7339                                         &mac_filter->mac_addr);
7340                 if (ret != I40E_SUCCESS)
7341                         goto DONE;
7342         }
7343
7344         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7345         if (ret != I40E_SUCCESS)
7346                 goto DONE;
7347
7348         /* Add the mac addr into mac list */
7349         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7350         if (f == NULL) {
7351                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7352                 ret = I40E_ERR_NO_MEMORY;
7353                 goto DONE;
7354         }
7355         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7356                         ETH_ADDR_LEN);
7357         f->mac_info.filter_type = mac_filter->filter_type;
7358         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7359         vsi->mac_num++;
7360
7361         ret = I40E_SUCCESS;
7362 DONE:
7363         rte_free(mv_f);
7364
7365         return ret;
7366 }
7367
7368 int
7369 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7370 {
7371         struct i40e_mac_filter *f;
7372         struct i40e_macvlan_filter *mv_f;
7373         int i, vlan_num;
7374         enum rte_mac_filter_type filter_type;
7375         int ret = I40E_SUCCESS;
7376
7377         /* Can't find it, return an error */
7378         f = i40e_find_mac_filter(vsi, addr);
7379         if (f == NULL)
7380                 return I40E_ERR_PARAM;
7381
7382         vlan_num = vsi->vlan_num;
7383         filter_type = f->mac_info.filter_type;
7384         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7385                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7386                 if (vlan_num == 0) {
7387                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7388                         return I40E_ERR_PARAM;
7389                 }
7390         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7391                         filter_type == RTE_MAC_HASH_MATCH)
7392                 vlan_num = 1;
7393
7394         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7395         if (mv_f == NULL) {
7396                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7397                 return I40E_ERR_NO_MEMORY;
7398         }
7399
7400         for (i = 0; i < vlan_num; i++) {
7401                 mv_f[i].filter_type = filter_type;
7402                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7403                                 ETH_ADDR_LEN);
7404         }
7405         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7406                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7407                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7408                 if (ret != I40E_SUCCESS)
7409                         goto DONE;
7410         }
7411
7412         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7413         if (ret != I40E_SUCCESS)
7414                 goto DONE;
7415
7416         /* Remove the mac addr into mac list */
7417         TAILQ_REMOVE(&vsi->mac_list, f, next);
7418         rte_free(f);
7419         vsi->mac_num--;
7420
7421         ret = I40E_SUCCESS;
7422 DONE:
7423         rte_free(mv_f);
7424         return ret;
7425 }
7426
7427 /* Configure hash enable flags for RSS */
7428 uint64_t
7429 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7430 {
7431         uint64_t hena = 0;
7432         int i;
7433
7434         if (!flags)
7435                 return hena;
7436
7437         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7438                 if (flags & (1ULL << i))
7439                         hena |= adapter->pctypes_tbl[i];
7440         }
7441
7442         return hena;
7443 }
7444
7445 /* Parse the hash enable flags */
7446 uint64_t
7447 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7448 {
7449         uint64_t rss_hf = 0;
7450
7451         if (!flags)
7452                 return rss_hf;
7453         int i;
7454
7455         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7456                 if (flags & adapter->pctypes_tbl[i])
7457                         rss_hf |= (1ULL << i);
7458         }
7459         return rss_hf;
7460 }
7461
7462 /* Disable RSS */
7463 static void
7464 i40e_pf_disable_rss(struct i40e_pf *pf)
7465 {
7466         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7467
7468         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7469         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7470         I40E_WRITE_FLUSH(hw);
7471 }
7472
7473 int
7474 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7475 {
7476         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7477         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7478         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7479                            I40E_VFQF_HKEY_MAX_INDEX :
7480                            I40E_PFQF_HKEY_MAX_INDEX;
7481         int ret = 0;
7482
7483         if (!key || key_len == 0) {
7484                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7485                 return 0;
7486         } else if (key_len != (key_idx + 1) *
7487                 sizeof(uint32_t)) {
7488                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7489                 return -EINVAL;
7490         }
7491
7492         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7493                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7494                         (struct i40e_aqc_get_set_rss_key_data *)key;
7495
7496                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7497                 if (ret)
7498                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7499         } else {
7500                 uint32_t *hash_key = (uint32_t *)key;
7501                 uint16_t i;
7502
7503                 if (vsi->type == I40E_VSI_SRIOV) {
7504                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7505                                 I40E_WRITE_REG(
7506                                         hw,
7507                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7508                                         hash_key[i]);
7509
7510                 } else {
7511                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7512                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7513                                                hash_key[i]);
7514                 }
7515                 I40E_WRITE_FLUSH(hw);
7516         }
7517
7518         return ret;
7519 }
7520
7521 static int
7522 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7523 {
7524         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7525         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7526         uint32_t reg;
7527         int ret;
7528
7529         if (!key || !key_len)
7530                 return 0;
7531
7532         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7533                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7534                         (struct i40e_aqc_get_set_rss_key_data *)key);
7535                 if (ret) {
7536                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7537                         return ret;
7538                 }
7539         } else {
7540                 uint32_t *key_dw = (uint32_t *)key;
7541                 uint16_t i;
7542
7543                 if (vsi->type == I40E_VSI_SRIOV) {
7544                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7545                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7546                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7547                         }
7548                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7549                                    sizeof(uint32_t);
7550                 } else {
7551                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7552                                 reg = I40E_PFQF_HKEY(i);
7553                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7554                         }
7555                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7556                                    sizeof(uint32_t);
7557                 }
7558         }
7559         return 0;
7560 }
7561
7562 static int
7563 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7564 {
7565         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7566         uint64_t hena;
7567         int ret;
7568
7569         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7570                                rss_conf->rss_key_len);
7571         if (ret)
7572                 return ret;
7573
7574         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7575         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7576         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7577         I40E_WRITE_FLUSH(hw);
7578
7579         return 0;
7580 }
7581
7582 static int
7583 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7584                          struct rte_eth_rss_conf *rss_conf)
7585 {
7586         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7587         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7588         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7589         uint64_t hena;
7590
7591         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7592         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7593
7594         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7595                 if (rss_hf != 0) /* Enable RSS */
7596                         return -EINVAL;
7597                 return 0; /* Nothing to do */
7598         }
7599         /* RSS enabled */
7600         if (rss_hf == 0) /* Disable RSS */
7601                 return -EINVAL;
7602
7603         return i40e_hw_rss_hash_set(pf, rss_conf);
7604 }
7605
7606 static int
7607 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7608                            struct rte_eth_rss_conf *rss_conf)
7609 {
7610         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7611         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7612         uint64_t hena;
7613         int ret;
7614
7615         if (!rss_conf)
7616                 return -EINVAL;
7617
7618         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7619                          &rss_conf->rss_key_len);
7620         if (ret)
7621                 return ret;
7622
7623         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7624         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7625         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7626
7627         return 0;
7628 }
7629
7630 static int
7631 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7632 {
7633         switch (filter_type) {
7634         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7635                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7636                 break;
7637         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7638                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7639                 break;
7640         case RTE_TUNNEL_FILTER_IMAC_TENID:
7641                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7642                 break;
7643         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7644                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7645                 break;
7646         case ETH_TUNNEL_FILTER_IMAC:
7647                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7648                 break;
7649         case ETH_TUNNEL_FILTER_OIP:
7650                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7651                 break;
7652         case ETH_TUNNEL_FILTER_IIP:
7653                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7654                 break;
7655         default:
7656                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7657                 return -EINVAL;
7658         }
7659
7660         return 0;
7661 }
7662
7663 /* Convert tunnel filter structure */
7664 static int
7665 i40e_tunnel_filter_convert(
7666         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7667         struct i40e_tunnel_filter *tunnel_filter)
7668 {
7669         rte_ether_addr_copy((struct rte_ether_addr *)
7670                         &cld_filter->element.outer_mac,
7671                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7672         rte_ether_addr_copy((struct rte_ether_addr *)
7673                         &cld_filter->element.inner_mac,
7674                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7675         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7676         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7677              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7678             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7679                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7680         else
7681                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7682         tunnel_filter->input.flags = cld_filter->element.flags;
7683         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7684         tunnel_filter->queue = cld_filter->element.queue_number;
7685         rte_memcpy(tunnel_filter->input.general_fields,
7686                    cld_filter->general_fields,
7687                    sizeof(cld_filter->general_fields));
7688
7689         return 0;
7690 }
7691
7692 /* Check if there exists the tunnel filter */
7693 struct i40e_tunnel_filter *
7694 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7695                              const struct i40e_tunnel_filter_input *input)
7696 {
7697         int ret;
7698
7699         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7700         if (ret < 0)
7701                 return NULL;
7702
7703         return tunnel_rule->hash_map[ret];
7704 }
7705
7706 /* Add a tunnel filter into the SW list */
7707 static int
7708 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7709                              struct i40e_tunnel_filter *tunnel_filter)
7710 {
7711         struct i40e_tunnel_rule *rule = &pf->tunnel;
7712         int ret;
7713
7714         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7715         if (ret < 0) {
7716                 PMD_DRV_LOG(ERR,
7717                             "Failed to insert tunnel filter to hash table %d!",
7718                             ret);
7719                 return ret;
7720         }
7721         rule->hash_map[ret] = tunnel_filter;
7722
7723         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7724
7725         return 0;
7726 }
7727
7728 /* Delete a tunnel filter from the SW list */
7729 int
7730 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7731                           struct i40e_tunnel_filter_input *input)
7732 {
7733         struct i40e_tunnel_rule *rule = &pf->tunnel;
7734         struct i40e_tunnel_filter *tunnel_filter;
7735         int ret;
7736
7737         ret = rte_hash_del_key(rule->hash_table, input);
7738         if (ret < 0) {
7739                 PMD_DRV_LOG(ERR,
7740                             "Failed to delete tunnel filter to hash table %d!",
7741                             ret);
7742                 return ret;
7743         }
7744         tunnel_filter = rule->hash_map[ret];
7745         rule->hash_map[ret] = NULL;
7746
7747         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7748         rte_free(tunnel_filter);
7749
7750         return 0;
7751 }
7752
7753 int
7754 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7755                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7756                         uint8_t add)
7757 {
7758         uint16_t ip_type;
7759         uint32_t ipv4_addr, ipv4_addr_le;
7760         uint8_t i, tun_type = 0;
7761         /* internal varialbe to convert ipv6 byte order */
7762         uint32_t convert_ipv6[4];
7763         int val, ret = 0;
7764         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7765         struct i40e_vsi *vsi = pf->main_vsi;
7766         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7767         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7768         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7769         struct i40e_tunnel_filter *tunnel, *node;
7770         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7771
7772         cld_filter = rte_zmalloc("tunnel_filter",
7773                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7774         0);
7775
7776         if (NULL == cld_filter) {
7777                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7778                 return -ENOMEM;
7779         }
7780         pfilter = cld_filter;
7781
7782         rte_ether_addr_copy(&tunnel_filter->outer_mac,
7783                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7784         rte_ether_addr_copy(&tunnel_filter->inner_mac,
7785                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
7786
7787         pfilter->element.inner_vlan =
7788                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7789         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7790                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7791                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7792                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7793                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7794                                 &ipv4_addr_le,
7795                                 sizeof(pfilter->element.ipaddr.v4.data));
7796         } else {
7797                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7798                 for (i = 0; i < 4; i++) {
7799                         convert_ipv6[i] =
7800                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7801                 }
7802                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7803                            &convert_ipv6,
7804                            sizeof(pfilter->element.ipaddr.v6.data));
7805         }
7806
7807         /* check tunneled type */
7808         switch (tunnel_filter->tunnel_type) {
7809         case RTE_TUNNEL_TYPE_VXLAN:
7810                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7811                 break;
7812         case RTE_TUNNEL_TYPE_NVGRE:
7813                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7814                 break;
7815         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7816                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7817                 break;
7818         case RTE_TUNNEL_TYPE_VXLAN_GPE:
7819                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7820                 break;
7821         default:
7822                 /* Other tunnel types is not supported. */
7823                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7824                 rte_free(cld_filter);
7825                 return -EINVAL;
7826         }
7827
7828         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7829                                        &pfilter->element.flags);
7830         if (val < 0) {
7831                 rte_free(cld_filter);
7832                 return -EINVAL;
7833         }
7834
7835         pfilter->element.flags |= rte_cpu_to_le_16(
7836                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7837                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7838         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7839         pfilter->element.queue_number =
7840                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7841
7842         /* Check if there is the filter in SW list */
7843         memset(&check_filter, 0, sizeof(check_filter));
7844         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7845         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7846         if (add && node) {
7847                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7848                 rte_free(cld_filter);
7849                 return -EINVAL;
7850         }
7851
7852         if (!add && !node) {
7853                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7854                 rte_free(cld_filter);
7855                 return -EINVAL;
7856         }
7857
7858         if (add) {
7859                 ret = i40e_aq_add_cloud_filters(hw,
7860                                         vsi->seid, &cld_filter->element, 1);
7861                 if (ret < 0) {
7862                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7863                         rte_free(cld_filter);
7864                         return -ENOTSUP;
7865                 }
7866                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7867                 if (tunnel == NULL) {
7868                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7869                         rte_free(cld_filter);
7870                         return -ENOMEM;
7871                 }
7872
7873                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7874                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7875                 if (ret < 0)
7876                         rte_free(tunnel);
7877         } else {
7878                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7879                                                    &cld_filter->element, 1);
7880                 if (ret < 0) {
7881                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7882                         rte_free(cld_filter);
7883                         return -ENOTSUP;
7884                 }
7885                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7886         }
7887
7888         rte_free(cld_filter);
7889         return ret;
7890 }
7891
7892 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7893 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7894 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7895 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7896 #define I40E_TR_GRE_KEY_MASK                    0x400
7897 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7898 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7899
7900 static enum
7901 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7902 {
7903         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7904         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7905         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7906         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7907         enum i40e_status_code status = I40E_SUCCESS;
7908
7909         if (pf->support_multi_driver) {
7910                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7911                 return I40E_NOT_SUPPORTED;
7912         }
7913
7914         memset(&filter_replace, 0,
7915                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7916         memset(&filter_replace_buf, 0,
7917                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7918
7919         /* create L1 filter */
7920         filter_replace.old_filter_type =
7921                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7922         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7923         filter_replace.tr_bit = 0;
7924
7925         /* Prepare the buffer, 3 entries */
7926         filter_replace_buf.data[0] =
7927                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7928         filter_replace_buf.data[0] |=
7929                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7930         filter_replace_buf.data[2] = 0xFF;
7931         filter_replace_buf.data[3] = 0xFF;
7932         filter_replace_buf.data[4] =
7933                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7934         filter_replace_buf.data[4] |=
7935                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7936         filter_replace_buf.data[7] = 0xF0;
7937         filter_replace_buf.data[8]
7938                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7939         filter_replace_buf.data[8] |=
7940                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7941         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7942                 I40E_TR_GENEVE_KEY_MASK |
7943                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7944         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7945                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7946                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7947
7948         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7949                                                &filter_replace_buf);
7950         if (!status && (filter_replace.old_filter_type !=
7951                         filter_replace.new_filter_type))
7952                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7953                             " original: 0x%x, new: 0x%x",
7954                             dev->device->name,
7955                             filter_replace.old_filter_type,
7956                             filter_replace.new_filter_type);
7957
7958         return status;
7959 }
7960
7961 static enum
7962 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7963 {
7964         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7965         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7966         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7967         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7968         enum i40e_status_code status = I40E_SUCCESS;
7969
7970         if (pf->support_multi_driver) {
7971                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7972                 return I40E_NOT_SUPPORTED;
7973         }
7974
7975         /* For MPLSoUDP */
7976         memset(&filter_replace, 0,
7977                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7978         memset(&filter_replace_buf, 0,
7979                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7980         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7981                 I40E_AQC_MIRROR_CLOUD_FILTER;
7982         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7983         filter_replace.new_filter_type =
7984                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7985         /* Prepare the buffer, 2 entries */
7986         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7987         filter_replace_buf.data[0] |=
7988                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7989         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7990         filter_replace_buf.data[4] |=
7991                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7992         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7993                                                &filter_replace_buf);
7994         if (status < 0)
7995                 return status;
7996         if (filter_replace.old_filter_type !=
7997             filter_replace.new_filter_type)
7998                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7999                             " original: 0x%x, new: 0x%x",
8000                             dev->device->name,
8001                             filter_replace.old_filter_type,
8002                             filter_replace.new_filter_type);
8003
8004         /* For MPLSoGRE */
8005         memset(&filter_replace, 0,
8006                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8007         memset(&filter_replace_buf, 0,
8008                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8009
8010         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8011                 I40E_AQC_MIRROR_CLOUD_FILTER;
8012         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8013         filter_replace.new_filter_type =
8014                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8015         /* Prepare the buffer, 2 entries */
8016         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8017         filter_replace_buf.data[0] |=
8018                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8019         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8020         filter_replace_buf.data[4] |=
8021                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8022
8023         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8024                                                &filter_replace_buf);
8025         if (!status && (filter_replace.old_filter_type !=
8026                         filter_replace.new_filter_type))
8027                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8028                             " original: 0x%x, new: 0x%x",
8029                             dev->device->name,
8030                             filter_replace.old_filter_type,
8031                             filter_replace.new_filter_type);
8032
8033         return status;
8034 }
8035
8036 static enum i40e_status_code
8037 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8038 {
8039         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8040         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8041         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8042         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8043         enum i40e_status_code status = I40E_SUCCESS;
8044
8045         if (pf->support_multi_driver) {
8046                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8047                 return I40E_NOT_SUPPORTED;
8048         }
8049
8050         /* For GTP-C */
8051         memset(&filter_replace, 0,
8052                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8053         memset(&filter_replace_buf, 0,
8054                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8055         /* create L1 filter */
8056         filter_replace.old_filter_type =
8057                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8058         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8059         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8060                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8061         /* Prepare the buffer, 2 entries */
8062         filter_replace_buf.data[0] =
8063                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8064         filter_replace_buf.data[0] |=
8065                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8066         filter_replace_buf.data[2] = 0xFF;
8067         filter_replace_buf.data[3] = 0xFF;
8068         filter_replace_buf.data[4] =
8069                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8070         filter_replace_buf.data[4] |=
8071                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8072         filter_replace_buf.data[6] = 0xFF;
8073         filter_replace_buf.data[7] = 0xFF;
8074         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8075                                                &filter_replace_buf);
8076         if (status < 0)
8077                 return status;
8078         if (filter_replace.old_filter_type !=
8079             filter_replace.new_filter_type)
8080                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8081                             " original: 0x%x, new: 0x%x",
8082                             dev->device->name,
8083                             filter_replace.old_filter_type,
8084                             filter_replace.new_filter_type);
8085
8086         /* for GTP-U */
8087         memset(&filter_replace, 0,
8088                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8089         memset(&filter_replace_buf, 0,
8090                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8091         /* create L1 filter */
8092         filter_replace.old_filter_type =
8093                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8094         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8095         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8096                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8097         /* Prepare the buffer, 2 entries */
8098         filter_replace_buf.data[0] =
8099                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8100         filter_replace_buf.data[0] |=
8101                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8102         filter_replace_buf.data[2] = 0xFF;
8103         filter_replace_buf.data[3] = 0xFF;
8104         filter_replace_buf.data[4] =
8105                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8106         filter_replace_buf.data[4] |=
8107                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8108         filter_replace_buf.data[6] = 0xFF;
8109         filter_replace_buf.data[7] = 0xFF;
8110
8111         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8112                                                &filter_replace_buf);
8113         if (!status && (filter_replace.old_filter_type !=
8114                         filter_replace.new_filter_type))
8115                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8116                             " original: 0x%x, new: 0x%x",
8117                             dev->device->name,
8118                             filter_replace.old_filter_type,
8119                             filter_replace.new_filter_type);
8120
8121         return status;
8122 }
8123
8124 static enum
8125 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8126 {
8127         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8128         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8129         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8130         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8131         enum i40e_status_code status = I40E_SUCCESS;
8132
8133         if (pf->support_multi_driver) {
8134                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8135                 return I40E_NOT_SUPPORTED;
8136         }
8137
8138         /* for GTP-C */
8139         memset(&filter_replace, 0,
8140                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8141         memset(&filter_replace_buf, 0,
8142                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8143         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8144         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8145         filter_replace.new_filter_type =
8146                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8147         /* Prepare the buffer, 2 entries */
8148         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8149         filter_replace_buf.data[0] |=
8150                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8151         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8152         filter_replace_buf.data[4] |=
8153                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8154         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8155                                                &filter_replace_buf);
8156         if (status < 0)
8157                 return status;
8158         if (filter_replace.old_filter_type !=
8159             filter_replace.new_filter_type)
8160                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8161                             " original: 0x%x, new: 0x%x",
8162                             dev->device->name,
8163                             filter_replace.old_filter_type,
8164                             filter_replace.new_filter_type);
8165
8166         /* for GTP-U */
8167         memset(&filter_replace, 0,
8168                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8169         memset(&filter_replace_buf, 0,
8170                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8171         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8172         filter_replace.old_filter_type =
8173                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8174         filter_replace.new_filter_type =
8175                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8176         /* Prepare the buffer, 2 entries */
8177         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8178         filter_replace_buf.data[0] |=
8179                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8180         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8181         filter_replace_buf.data[4] |=
8182                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8183
8184         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8185                                                &filter_replace_buf);
8186         if (!status && (filter_replace.old_filter_type !=
8187                         filter_replace.new_filter_type))
8188                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8189                             " original: 0x%x, new: 0x%x",
8190                             dev->device->name,
8191                             filter_replace.old_filter_type,
8192                             filter_replace.new_filter_type);
8193
8194         return status;
8195 }
8196
8197 int
8198 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8199                       struct i40e_tunnel_filter_conf *tunnel_filter,
8200                       uint8_t add)
8201 {
8202         uint16_t ip_type;
8203         uint32_t ipv4_addr, ipv4_addr_le;
8204         uint8_t i, tun_type = 0;
8205         /* internal variable to convert ipv6 byte order */
8206         uint32_t convert_ipv6[4];
8207         int val, ret = 0;
8208         struct i40e_pf_vf *vf = NULL;
8209         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8210         struct i40e_vsi *vsi;
8211         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8212         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8213         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8214         struct i40e_tunnel_filter *tunnel, *node;
8215         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8216         uint32_t teid_le;
8217         bool big_buffer = 0;
8218
8219         cld_filter = rte_zmalloc("tunnel_filter",
8220                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8221                          0);
8222
8223         if (cld_filter == NULL) {
8224                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8225                 return -ENOMEM;
8226         }
8227         pfilter = cld_filter;
8228
8229         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8230                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8231         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8232                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8233
8234         pfilter->element.inner_vlan =
8235                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8236         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8237                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8238                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8239                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8240                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8241                                 &ipv4_addr_le,
8242                                 sizeof(pfilter->element.ipaddr.v4.data));
8243         } else {
8244                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8245                 for (i = 0; i < 4; i++) {
8246                         convert_ipv6[i] =
8247                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8248                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8249                 }
8250                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8251                            &convert_ipv6,
8252                            sizeof(pfilter->element.ipaddr.v6.data));
8253         }
8254
8255         /* check tunneled type */
8256         switch (tunnel_filter->tunnel_type) {
8257         case I40E_TUNNEL_TYPE_VXLAN:
8258                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8259                 break;
8260         case I40E_TUNNEL_TYPE_NVGRE:
8261                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8262                 break;
8263         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8264                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8265                 break;
8266         case I40E_TUNNEL_TYPE_MPLSoUDP:
8267                 if (!pf->mpls_replace_flag) {
8268                         i40e_replace_mpls_l1_filter(pf);
8269                         i40e_replace_mpls_cloud_filter(pf);
8270                         pf->mpls_replace_flag = 1;
8271                 }
8272                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8273                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8274                         teid_le >> 4;
8275                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8276                         (teid_le & 0xF) << 12;
8277                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8278                         0x40;
8279                 big_buffer = 1;
8280                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8281                 break;
8282         case I40E_TUNNEL_TYPE_MPLSoGRE:
8283                 if (!pf->mpls_replace_flag) {
8284                         i40e_replace_mpls_l1_filter(pf);
8285                         i40e_replace_mpls_cloud_filter(pf);
8286                         pf->mpls_replace_flag = 1;
8287                 }
8288                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8289                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8290                         teid_le >> 4;
8291                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8292                         (teid_le & 0xF) << 12;
8293                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8294                         0x0;
8295                 big_buffer = 1;
8296                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8297                 break;
8298         case I40E_TUNNEL_TYPE_GTPC:
8299                 if (!pf->gtp_replace_flag) {
8300                         i40e_replace_gtp_l1_filter(pf);
8301                         i40e_replace_gtp_cloud_filter(pf);
8302                         pf->gtp_replace_flag = 1;
8303                 }
8304                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8305                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8306                         (teid_le >> 16) & 0xFFFF;
8307                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8308                         teid_le & 0xFFFF;
8309                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8310                         0x0;
8311                 big_buffer = 1;
8312                 break;
8313         case I40E_TUNNEL_TYPE_GTPU:
8314                 if (!pf->gtp_replace_flag) {
8315                         i40e_replace_gtp_l1_filter(pf);
8316                         i40e_replace_gtp_cloud_filter(pf);
8317                         pf->gtp_replace_flag = 1;
8318                 }
8319                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8320                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8321                         (teid_le >> 16) & 0xFFFF;
8322                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8323                         teid_le & 0xFFFF;
8324                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8325                         0x0;
8326                 big_buffer = 1;
8327                 break;
8328         case I40E_TUNNEL_TYPE_QINQ:
8329                 if (!pf->qinq_replace_flag) {
8330                         ret = i40e_cloud_filter_qinq_create(pf);
8331                         if (ret < 0)
8332                                 PMD_DRV_LOG(DEBUG,
8333                                             "QinQ tunnel filter already created.");
8334                         pf->qinq_replace_flag = 1;
8335                 }
8336                 /*      Add in the General fields the values of
8337                  *      the Outer and Inner VLAN
8338                  *      Big Buffer should be set, see changes in
8339                  *      i40e_aq_add_cloud_filters
8340                  */
8341                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8342                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8343                 big_buffer = 1;
8344                 break;
8345         default:
8346                 /* Other tunnel types is not supported. */
8347                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8348                 rte_free(cld_filter);
8349                 return -EINVAL;
8350         }
8351
8352         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8353                 pfilter->element.flags =
8354                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8355         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8356                 pfilter->element.flags =
8357                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8358         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8359                 pfilter->element.flags =
8360                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8361         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8362                 pfilter->element.flags =
8363                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8364         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8365                 pfilter->element.flags |=
8366                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8367         else {
8368                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8369                                                 &pfilter->element.flags);
8370                 if (val < 0) {
8371                         rte_free(cld_filter);
8372                         return -EINVAL;
8373                 }
8374         }
8375
8376         pfilter->element.flags |= rte_cpu_to_le_16(
8377                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8378                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8379         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8380         pfilter->element.queue_number =
8381                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8382
8383         if (!tunnel_filter->is_to_vf)
8384                 vsi = pf->main_vsi;
8385         else {
8386                 if (tunnel_filter->vf_id >= pf->vf_num) {
8387                         PMD_DRV_LOG(ERR, "Invalid argument.");
8388                         rte_free(cld_filter);
8389                         return -EINVAL;
8390                 }
8391                 vf = &pf->vfs[tunnel_filter->vf_id];
8392                 vsi = vf->vsi;
8393         }
8394
8395         /* Check if there is the filter in SW list */
8396         memset(&check_filter, 0, sizeof(check_filter));
8397         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8398         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8399         check_filter.vf_id = tunnel_filter->vf_id;
8400         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8401         if (add && node) {
8402                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8403                 rte_free(cld_filter);
8404                 return -EINVAL;
8405         }
8406
8407         if (!add && !node) {
8408                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8409                 rte_free(cld_filter);
8410                 return -EINVAL;
8411         }
8412
8413         if (add) {
8414                 if (big_buffer)
8415                         ret = i40e_aq_add_cloud_filters_bb(hw,
8416                                                    vsi->seid, cld_filter, 1);
8417                 else
8418                         ret = i40e_aq_add_cloud_filters(hw,
8419                                         vsi->seid, &cld_filter->element, 1);
8420                 if (ret < 0) {
8421                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8422                         rte_free(cld_filter);
8423                         return -ENOTSUP;
8424                 }
8425                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8426                 if (tunnel == NULL) {
8427                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8428                         rte_free(cld_filter);
8429                         return -ENOMEM;
8430                 }
8431
8432                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8433                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8434                 if (ret < 0)
8435                         rte_free(tunnel);
8436         } else {
8437                 if (big_buffer)
8438                         ret = i40e_aq_rem_cloud_filters_bb(
8439                                 hw, vsi->seid, cld_filter, 1);
8440                 else
8441                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8442                                                 &cld_filter->element, 1);
8443                 if (ret < 0) {
8444                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8445                         rte_free(cld_filter);
8446                         return -ENOTSUP;
8447                 }
8448                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8449         }
8450
8451         rte_free(cld_filter);
8452         return ret;
8453 }
8454
8455 static int
8456 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8457 {
8458         uint8_t i;
8459
8460         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8461                 if (pf->vxlan_ports[i] == port)
8462                         return i;
8463         }
8464
8465         return -1;
8466 }
8467
8468 static int
8469 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8470 {
8471         int  idx, ret;
8472         uint8_t filter_idx;
8473         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8474
8475         idx = i40e_get_vxlan_port_idx(pf, port);
8476
8477         /* Check if port already exists */
8478         if (idx >= 0) {
8479                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8480                 return -EINVAL;
8481         }
8482
8483         /* Now check if there is space to add the new port */
8484         idx = i40e_get_vxlan_port_idx(pf, 0);
8485         if (idx < 0) {
8486                 PMD_DRV_LOG(ERR,
8487                         "Maximum number of UDP ports reached, not adding port %d",
8488                         port);
8489                 return -ENOSPC;
8490         }
8491
8492         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8493                                         &filter_idx, NULL);
8494         if (ret < 0) {
8495                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8496                 return -1;
8497         }
8498
8499         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8500                          port,  filter_idx);
8501
8502         /* New port: add it and mark its index in the bitmap */
8503         pf->vxlan_ports[idx] = port;
8504         pf->vxlan_bitmap |= (1 << idx);
8505
8506         if (!(pf->flags & I40E_FLAG_VXLAN))
8507                 pf->flags |= I40E_FLAG_VXLAN;
8508
8509         return 0;
8510 }
8511
8512 static int
8513 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8514 {
8515         int idx;
8516         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8517
8518         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8519                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8520                 return -EINVAL;
8521         }
8522
8523         idx = i40e_get_vxlan_port_idx(pf, port);
8524
8525         if (idx < 0) {
8526                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8527                 return -EINVAL;
8528         }
8529
8530         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8531                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8532                 return -1;
8533         }
8534
8535         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8536                         port, idx);
8537
8538         pf->vxlan_ports[idx] = 0;
8539         pf->vxlan_bitmap &= ~(1 << idx);
8540
8541         if (!pf->vxlan_bitmap)
8542                 pf->flags &= ~I40E_FLAG_VXLAN;
8543
8544         return 0;
8545 }
8546
8547 /* Add UDP tunneling port */
8548 static int
8549 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8550                              struct rte_eth_udp_tunnel *udp_tunnel)
8551 {
8552         int ret = 0;
8553         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8554
8555         if (udp_tunnel == NULL)
8556                 return -EINVAL;
8557
8558         switch (udp_tunnel->prot_type) {
8559         case RTE_TUNNEL_TYPE_VXLAN:
8560                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8561                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8562                 break;
8563         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8564                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8565                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8566                 break;
8567         case RTE_TUNNEL_TYPE_GENEVE:
8568         case RTE_TUNNEL_TYPE_TEREDO:
8569                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8570                 ret = -1;
8571                 break;
8572
8573         default:
8574                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8575                 ret = -1;
8576                 break;
8577         }
8578
8579         return ret;
8580 }
8581
8582 /* Remove UDP tunneling port */
8583 static int
8584 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8585                              struct rte_eth_udp_tunnel *udp_tunnel)
8586 {
8587         int ret = 0;
8588         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8589
8590         if (udp_tunnel == NULL)
8591                 return -EINVAL;
8592
8593         switch (udp_tunnel->prot_type) {
8594         case RTE_TUNNEL_TYPE_VXLAN:
8595         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8596                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8597                 break;
8598         case RTE_TUNNEL_TYPE_GENEVE:
8599         case RTE_TUNNEL_TYPE_TEREDO:
8600                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8601                 ret = -1;
8602                 break;
8603         default:
8604                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8605                 ret = -1;
8606                 break;
8607         }
8608
8609         return ret;
8610 }
8611
8612 /* Calculate the maximum number of contiguous PF queues that are configured */
8613 static int
8614 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8615 {
8616         struct rte_eth_dev_data *data = pf->dev_data;
8617         int i, num;
8618         struct i40e_rx_queue *rxq;
8619
8620         num = 0;
8621         for (i = 0; i < pf->lan_nb_qps; i++) {
8622                 rxq = data->rx_queues[i];
8623                 if (rxq && rxq->q_set)
8624                         num++;
8625                 else
8626                         break;
8627         }
8628
8629         return num;
8630 }
8631
8632 /* Configure RSS */
8633 static int
8634 i40e_pf_config_rss(struct i40e_pf *pf)
8635 {
8636         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8637         struct rte_eth_rss_conf rss_conf;
8638         uint32_t i, lut = 0;
8639         uint16_t j, num;
8640
8641         /*
8642          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8643          * It's necessary to calculate the actual PF queues that are configured.
8644          */
8645         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8646                 num = i40e_pf_calc_configured_queues_num(pf);
8647         else
8648                 num = pf->dev_data->nb_rx_queues;
8649
8650         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8651         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8652                         num);
8653
8654         if (num == 0) {
8655                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8656                 return -ENOTSUP;
8657         }
8658
8659         if (pf->adapter->rss_reta_updated == 0) {
8660                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8661                         if (j == num)
8662                                 j = 0;
8663                         lut = (lut << 8) | (j & ((0x1 <<
8664                                 hw->func_caps.rss_table_entry_width) - 1));
8665                         if ((i & 3) == 3)
8666                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8667                                                rte_bswap32(lut));
8668                 }
8669         }
8670
8671         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8672         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8673                 i40e_pf_disable_rss(pf);
8674                 return 0;
8675         }
8676         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8677                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8678                 /* Random default keys */
8679                 static uint32_t rss_key_default[] = {0x6b793944,
8680                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8681                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8682                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8683
8684                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8685                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8686                                                         sizeof(uint32_t);
8687         }
8688
8689         return i40e_hw_rss_hash_set(pf, &rss_conf);
8690 }
8691
8692 static int
8693 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8694                                struct rte_eth_tunnel_filter_conf *filter)
8695 {
8696         if (pf == NULL || filter == NULL) {
8697                 PMD_DRV_LOG(ERR, "Invalid parameter");
8698                 return -EINVAL;
8699         }
8700
8701         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8702                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8703                 return -EINVAL;
8704         }
8705
8706         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8707                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8708                 return -EINVAL;
8709         }
8710
8711         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8712                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8713                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8714                 return -EINVAL;
8715         }
8716
8717         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8718                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8719                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8720                 return -EINVAL;
8721         }
8722
8723         return 0;
8724 }
8725
8726 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8727 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8728 static int
8729 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8730 {
8731         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8732         uint32_t val, reg;
8733         int ret = -EINVAL;
8734
8735         if (pf->support_multi_driver) {
8736                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8737                 return -ENOTSUP;
8738         }
8739
8740         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8741         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8742
8743         if (len == 3) {
8744                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8745         } else if (len == 4) {
8746                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8747         } else {
8748                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8749                 return ret;
8750         }
8751
8752         if (reg != val) {
8753                 ret = i40e_aq_debug_write_global_register(hw,
8754                                                    I40E_GL_PRS_FVBM(2),
8755                                                    reg, NULL);
8756                 if (ret != 0)
8757                         return ret;
8758                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8759                             "with value 0x%08x",
8760                             I40E_GL_PRS_FVBM(2), reg);
8761         } else {
8762                 ret = 0;
8763         }
8764         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8765                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8766
8767         return ret;
8768 }
8769
8770 static int
8771 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8772 {
8773         int ret = -EINVAL;
8774
8775         if (!hw || !cfg)
8776                 return -EINVAL;
8777
8778         switch (cfg->cfg_type) {
8779         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8780                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8781                 break;
8782         default:
8783                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8784                 break;
8785         }
8786
8787         return ret;
8788 }
8789
8790 static int
8791 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8792                                enum rte_filter_op filter_op,
8793                                void *arg)
8794 {
8795         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8796         int ret = I40E_ERR_PARAM;
8797
8798         switch (filter_op) {
8799         case RTE_ETH_FILTER_SET:
8800                 ret = i40e_dev_global_config_set(hw,
8801                         (struct rte_eth_global_cfg *)arg);
8802                 break;
8803         default:
8804                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8805                 break;
8806         }
8807
8808         return ret;
8809 }
8810
8811 static int
8812 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8813                           enum rte_filter_op filter_op,
8814                           void *arg)
8815 {
8816         struct rte_eth_tunnel_filter_conf *filter;
8817         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8818         int ret = I40E_SUCCESS;
8819
8820         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8821
8822         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8823                 return I40E_ERR_PARAM;
8824
8825         switch (filter_op) {
8826         case RTE_ETH_FILTER_NOP:
8827                 if (!(pf->flags & I40E_FLAG_VXLAN))
8828                         ret = I40E_NOT_SUPPORTED;
8829                 break;
8830         case RTE_ETH_FILTER_ADD:
8831                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8832                 break;
8833         case RTE_ETH_FILTER_DELETE:
8834                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8835                 break;
8836         default:
8837                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8838                 ret = I40E_ERR_PARAM;
8839                 break;
8840         }
8841
8842         return ret;
8843 }
8844
8845 static int
8846 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8847 {
8848         int ret = 0;
8849         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8850
8851         /* RSS setup */
8852         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8853                 ret = i40e_pf_config_rss(pf);
8854         else
8855                 i40e_pf_disable_rss(pf);
8856
8857         return ret;
8858 }
8859
8860 /* Get the symmetric hash enable configurations per port */
8861 static void
8862 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8863 {
8864         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8865
8866         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8867 }
8868
8869 /* Set the symmetric hash enable configurations per port */
8870 static void
8871 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8872 {
8873         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8874
8875         if (enable > 0) {
8876                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8877                         PMD_DRV_LOG(INFO,
8878                                 "Symmetric hash has already been enabled");
8879                         return;
8880                 }
8881                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8882         } else {
8883                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8884                         PMD_DRV_LOG(INFO,
8885                                 "Symmetric hash has already been disabled");
8886                         return;
8887                 }
8888                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8889         }
8890         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8891         I40E_WRITE_FLUSH(hw);
8892 }
8893
8894 /*
8895  * Get global configurations of hash function type and symmetric hash enable
8896  * per flow type (pctype). Note that global configuration means it affects all
8897  * the ports on the same NIC.
8898  */
8899 static int
8900 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8901                                    struct rte_eth_hash_global_conf *g_cfg)
8902 {
8903         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8904         uint32_t reg;
8905         uint16_t i, j;
8906
8907         memset(g_cfg, 0, sizeof(*g_cfg));
8908         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8909         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8910                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8911         else
8912                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8913         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8914                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8915
8916         /*
8917          * As i40e supports less than 64 flow types, only first 64 bits need to
8918          * be checked.
8919          */
8920         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8921                 g_cfg->valid_bit_mask[i] = 0ULL;
8922                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8923         }
8924
8925         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8926
8927         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8928                 if (!adapter->pctypes_tbl[i])
8929                         continue;
8930                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8931                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8932                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8933                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8934                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8935                                         g_cfg->sym_hash_enable_mask[0] |=
8936                                                                 (1ULL << i);
8937                                 }
8938                         }
8939                 }
8940         }
8941
8942         return 0;
8943 }
8944
8945 static int
8946 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8947                               const struct rte_eth_hash_global_conf *g_cfg)
8948 {
8949         uint32_t i;
8950         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8951
8952         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8953                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8954                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8955                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8956                                                 g_cfg->hash_func);
8957                 return -EINVAL;
8958         }
8959
8960         /*
8961          * As i40e supports less than 64 flow types, only first 64 bits need to
8962          * be checked.
8963          */
8964         mask0 = g_cfg->valid_bit_mask[0];
8965         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8966                 if (i == 0) {
8967                         /* Check if any unsupported flow type configured */
8968                         if ((mask0 | i40e_mask) ^ i40e_mask)
8969                                 goto mask_err;
8970                 } else {
8971                         if (g_cfg->valid_bit_mask[i])
8972                                 goto mask_err;
8973                 }
8974         }
8975
8976         return 0;
8977
8978 mask_err:
8979         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8980
8981         return -EINVAL;
8982 }
8983
8984 /*
8985  * Set global configurations of hash function type and symmetric hash enable
8986  * per flow type (pctype). Note any modifying global configuration will affect
8987  * all the ports on the same NIC.
8988  */
8989 static int
8990 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8991                                    struct rte_eth_hash_global_conf *g_cfg)
8992 {
8993         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8994         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8995         int ret;
8996         uint16_t i, j;
8997         uint32_t reg;
8998         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8999
9000         if (pf->support_multi_driver) {
9001                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9002                 return -ENOTSUP;
9003         }
9004
9005         /* Check the input parameters */
9006         ret = i40e_hash_global_config_check(adapter, g_cfg);
9007         if (ret < 0)
9008                 return ret;
9009
9010         /*
9011          * As i40e supports less than 64 flow types, only first 64 bits need to
9012          * be configured.
9013          */
9014         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9015                 if (mask0 & (1UL << i)) {
9016                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9017                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9018
9019                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9020                              j < I40E_FILTER_PCTYPE_MAX; j++) {
9021                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
9022                                         i40e_write_global_rx_ctl(hw,
9023                                                           I40E_GLQF_HSYM(j),
9024                                                           reg);
9025                         }
9026                 }
9027         }
9028
9029         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9030         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9031                 /* Toeplitz */
9032                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9033                         PMD_DRV_LOG(DEBUG,
9034                                 "Hash function already set to Toeplitz");
9035                         goto out;
9036                 }
9037                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9038         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9039                 /* Simple XOR */
9040                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9041                         PMD_DRV_LOG(DEBUG,
9042                                 "Hash function already set to Simple XOR");
9043                         goto out;
9044                 }
9045                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9046         } else
9047                 /* Use the default, and keep it as it is */
9048                 goto out;
9049
9050         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9051
9052 out:
9053         I40E_WRITE_FLUSH(hw);
9054
9055         return 0;
9056 }
9057
9058 /**
9059  * Valid input sets for hash and flow director filters per PCTYPE
9060  */
9061 static uint64_t
9062 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9063                 enum rte_filter_type filter)
9064 {
9065         uint64_t valid;
9066
9067         static const uint64_t valid_hash_inset_table[] = {
9068                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9069                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9070                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9071                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9072                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9073                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9074                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9075                         I40E_INSET_FLEX_PAYLOAD,
9076                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9077                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9078                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9079                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9080                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9081                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9082                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9083                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9084                         I40E_INSET_FLEX_PAYLOAD,
9085                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9086                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9087                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9088                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9089                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9090                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9091                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9092                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9093                         I40E_INSET_FLEX_PAYLOAD,
9094                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9095                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9096                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9097                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9098                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9099                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9100                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9101                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9102                         I40E_INSET_FLEX_PAYLOAD,
9103                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9104                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9105                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9106                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9107                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9108                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9109                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9110                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9111                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9112                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9113                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9114                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9115                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9116                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9117                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9118                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9119                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9120                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9121                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9122                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9123                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9124                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9125                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9126                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9127                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9128                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9129                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9130                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9131                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9132                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9133                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9134                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9135                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9136                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9137                         I40E_INSET_FLEX_PAYLOAD,
9138                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9139                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9140                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9141                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9142                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9143                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9144                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9145                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9146                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9147                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9148                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9149                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9150                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9151                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9152                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9153                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9154                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9155                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9156                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9157                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9158                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9159                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9160                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9161                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9162                         I40E_INSET_FLEX_PAYLOAD,
9163                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9164                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9165                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9166                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9167                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9168                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9169                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9170                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9171                         I40E_INSET_FLEX_PAYLOAD,
9172                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9173                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9174                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9175                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9176                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9177                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9178                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9179                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9180                         I40E_INSET_FLEX_PAYLOAD,
9181                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9182                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9183                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9184                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9185                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9186                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9187                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9188                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9189                         I40E_INSET_FLEX_PAYLOAD,
9190                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9191                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9192                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9193                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9194                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9195                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9196                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9197                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9198                         I40E_INSET_FLEX_PAYLOAD,
9199                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9200                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9201                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9202                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9203                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9204                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9205                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9206                         I40E_INSET_FLEX_PAYLOAD,
9207                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9208                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9209                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9210                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9211                         I40E_INSET_FLEX_PAYLOAD,
9212         };
9213
9214         /**
9215          * Flow director supports only fields defined in
9216          * union rte_eth_fdir_flow.
9217          */
9218         static const uint64_t valid_fdir_inset_table[] = {
9219                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9220                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9221                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9222                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9223                 I40E_INSET_IPV4_TTL,
9224                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9225                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9226                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9227                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9228                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9229                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9230                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9231                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9232                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9233                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9234                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9235                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9236                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9237                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9238                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9239                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9240                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9241                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9242                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9243                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9244                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9245                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9246                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9247                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9248                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9249                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9250                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9251                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9252                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9253                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9254                 I40E_INSET_SCTP_VT,
9255                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9256                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9257                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9258                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9259                 I40E_INSET_IPV4_TTL,
9260                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9261                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9262                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9263                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9264                 I40E_INSET_IPV6_HOP_LIMIT,
9265                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9266                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9267                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9268                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9269                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9270                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9271                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9272                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9273                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9274                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9275                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9276                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9277                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9278                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9279                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9280                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9281                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9282                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9283                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9284                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9285                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9286                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9287                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9288                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9289                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9290                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9291                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9292                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9293                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9294                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9295                 I40E_INSET_SCTP_VT,
9296                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9297                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9298                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9299                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9300                 I40E_INSET_IPV6_HOP_LIMIT,
9301                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9302                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9303                 I40E_INSET_LAST_ETHER_TYPE,
9304         };
9305
9306         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9307                 return 0;
9308         if (filter == RTE_ETH_FILTER_HASH)
9309                 valid = valid_hash_inset_table[pctype];
9310         else
9311                 valid = valid_fdir_inset_table[pctype];
9312
9313         return valid;
9314 }
9315
9316 /**
9317  * Validate if the input set is allowed for a specific PCTYPE
9318  */
9319 int
9320 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9321                 enum rte_filter_type filter, uint64_t inset)
9322 {
9323         uint64_t valid;
9324
9325         valid = i40e_get_valid_input_set(pctype, filter);
9326         if (inset & (~valid))
9327                 return -EINVAL;
9328
9329         return 0;
9330 }
9331
9332 /* default input set fields combination per pctype */
9333 uint64_t
9334 i40e_get_default_input_set(uint16_t pctype)
9335 {
9336         static const uint64_t default_inset_table[] = {
9337                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9338                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9339                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9340                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9341                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9342                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9343                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9344                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9345                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9346                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9347                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9348                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9349                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9350                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9351                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9352                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9353                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9354                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9355                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9356                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9357                         I40E_INSET_SCTP_VT,
9358                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9359                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9360                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9361                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9362                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9363                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9364                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9365                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9366                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9367                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9368                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9369                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9370                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9371                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9372                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9373                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9374                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9375                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9376                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9377                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9378                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9379                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9380                         I40E_INSET_SCTP_VT,
9381                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9382                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9383                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9384                         I40E_INSET_LAST_ETHER_TYPE,
9385         };
9386
9387         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9388                 return 0;
9389
9390         return default_inset_table[pctype];
9391 }
9392
9393 /**
9394  * Parse the input set from index to logical bit masks
9395  */
9396 static int
9397 i40e_parse_input_set(uint64_t *inset,
9398                      enum i40e_filter_pctype pctype,
9399                      enum rte_eth_input_set_field *field,
9400                      uint16_t size)
9401 {
9402         uint16_t i, j;
9403         int ret = -EINVAL;
9404
9405         static const struct {
9406                 enum rte_eth_input_set_field field;
9407                 uint64_t inset;
9408         } inset_convert_table[] = {
9409                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9410                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9411                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9412                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9413                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9414                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9415                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9416                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9417                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9418                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9419                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9420                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9421                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9422                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9423                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9424                         I40E_INSET_IPV6_NEXT_HDR},
9425                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9426                         I40E_INSET_IPV6_HOP_LIMIT},
9427                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9428                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9429                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9430                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9431                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9432                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9433                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9434                         I40E_INSET_SCTP_VT},
9435                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9436                         I40E_INSET_TUNNEL_DMAC},
9437                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9438                         I40E_INSET_VLAN_TUNNEL},
9439                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9440                         I40E_INSET_TUNNEL_ID},
9441                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9442                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9443                         I40E_INSET_FLEX_PAYLOAD_W1},
9444                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9445                         I40E_INSET_FLEX_PAYLOAD_W2},
9446                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9447                         I40E_INSET_FLEX_PAYLOAD_W3},
9448                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9449                         I40E_INSET_FLEX_PAYLOAD_W4},
9450                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9451                         I40E_INSET_FLEX_PAYLOAD_W5},
9452                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9453                         I40E_INSET_FLEX_PAYLOAD_W6},
9454                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9455                         I40E_INSET_FLEX_PAYLOAD_W7},
9456                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9457                         I40E_INSET_FLEX_PAYLOAD_W8},
9458         };
9459
9460         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9461                 return ret;
9462
9463         /* Only one item allowed for default or all */
9464         if (size == 1) {
9465                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9466                         *inset = i40e_get_default_input_set(pctype);
9467                         return 0;
9468                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9469                         *inset = I40E_INSET_NONE;
9470                         return 0;
9471                 }
9472         }
9473
9474         for (i = 0, *inset = 0; i < size; i++) {
9475                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9476                         if (field[i] == inset_convert_table[j].field) {
9477                                 *inset |= inset_convert_table[j].inset;
9478                                 break;
9479                         }
9480                 }
9481
9482                 /* It contains unsupported input set, return immediately */
9483                 if (j == RTE_DIM(inset_convert_table))
9484                         return ret;
9485         }
9486
9487         return 0;
9488 }
9489
9490 /**
9491  * Translate the input set from bit masks to register aware bit masks
9492  * and vice versa
9493  */
9494 uint64_t
9495 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9496 {
9497         uint64_t val = 0;
9498         uint16_t i;
9499
9500         struct inset_map {
9501                 uint64_t inset;
9502                 uint64_t inset_reg;
9503         };
9504
9505         static const struct inset_map inset_map_common[] = {
9506                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9507                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9508                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9509                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9510                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9511                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9512                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9513                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9514                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9515                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9516                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9517                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9518                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9519                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9520                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9521                 {I40E_INSET_TUNNEL_DMAC,
9522                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9523                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9524                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9525                 {I40E_INSET_TUNNEL_SRC_PORT,
9526                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9527                 {I40E_INSET_TUNNEL_DST_PORT,
9528                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9529                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9530                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9531                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9532                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9533                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9534                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9535                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9536                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9537                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9538         };
9539
9540     /* some different registers map in x722*/
9541         static const struct inset_map inset_map_diff_x722[] = {
9542                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9543                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9544                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9545                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9546         };
9547
9548         static const struct inset_map inset_map_diff_not_x722[] = {
9549                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9550                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9551                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9552                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9553         };
9554
9555         if (input == 0)
9556                 return val;
9557
9558         /* Translate input set to register aware inset */
9559         if (type == I40E_MAC_X722) {
9560                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9561                         if (input & inset_map_diff_x722[i].inset)
9562                                 val |= inset_map_diff_x722[i].inset_reg;
9563                 }
9564         } else {
9565                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9566                         if (input & inset_map_diff_not_x722[i].inset)
9567                                 val |= inset_map_diff_not_x722[i].inset_reg;
9568                 }
9569         }
9570
9571         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9572                 if (input & inset_map_common[i].inset)
9573                         val |= inset_map_common[i].inset_reg;
9574         }
9575
9576         return val;
9577 }
9578
9579 int
9580 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9581 {
9582         uint8_t i, idx = 0;
9583         uint64_t inset_need_mask = inset;
9584
9585         static const struct {
9586                 uint64_t inset;
9587                 uint32_t mask;
9588         } inset_mask_map[] = {
9589                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9590                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9591                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9592                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9593                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9594                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9595                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9596                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9597         };
9598
9599         if (!inset || !mask || !nb_elem)
9600                 return 0;
9601
9602         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9603                 /* Clear the inset bit, if no MASK is required,
9604                  * for example proto + ttl
9605                  */
9606                 if ((inset & inset_mask_map[i].inset) ==
9607                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9608                         inset_need_mask &= ~inset_mask_map[i].inset;
9609                 if (!inset_need_mask)
9610                         return 0;
9611         }
9612         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9613                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9614                     inset_mask_map[i].inset) {
9615                         if (idx >= nb_elem) {
9616                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9617                                 return -EINVAL;
9618                         }
9619                         mask[idx] = inset_mask_map[i].mask;
9620                         idx++;
9621                 }
9622         }
9623
9624         return idx;
9625 }
9626
9627 void
9628 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9629 {
9630         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9631
9632         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9633         if (reg != val)
9634                 i40e_write_rx_ctl(hw, addr, val);
9635         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9636                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9637 }
9638
9639 void
9640 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9641 {
9642         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9643         struct rte_eth_dev *dev;
9644
9645         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9646         if (reg != val) {
9647                 i40e_write_rx_ctl(hw, addr, val);
9648                 PMD_DRV_LOG(WARNING,
9649                             "i40e device %s changed global register [0x%08x]."
9650                             " original: 0x%08x, new: 0x%08x",
9651                             dev->device->name, addr, reg,
9652                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9653         }
9654 }
9655
9656 static void
9657 i40e_filter_input_set_init(struct i40e_pf *pf)
9658 {
9659         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9660         enum i40e_filter_pctype pctype;
9661         uint64_t input_set, inset_reg;
9662         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9663         int num, i;
9664         uint16_t flow_type;
9665
9666         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9667              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9668                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9669
9670                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9671                         continue;
9672
9673                 input_set = i40e_get_default_input_set(pctype);
9674
9675                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9676                                                    I40E_INSET_MASK_NUM_REG);
9677                 if (num < 0)
9678                         return;
9679                 if (pf->support_multi_driver && num > 0) {
9680                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9681                         return;
9682                 }
9683                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9684                                         input_set);
9685
9686                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9687                                       (uint32_t)(inset_reg & UINT32_MAX));
9688                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9689                                      (uint32_t)((inset_reg >>
9690                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9691                 if (!pf->support_multi_driver) {
9692                         i40e_check_write_global_reg(hw,
9693                                             I40E_GLQF_HASH_INSET(0, pctype),
9694                                             (uint32_t)(inset_reg & UINT32_MAX));
9695                         i40e_check_write_global_reg(hw,
9696                                              I40E_GLQF_HASH_INSET(1, pctype),
9697                                              (uint32_t)((inset_reg >>
9698                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9699
9700                         for (i = 0; i < num; i++) {
9701                                 i40e_check_write_global_reg(hw,
9702                                                     I40E_GLQF_FD_MSK(i, pctype),
9703                                                     mask_reg[i]);
9704                                 i40e_check_write_global_reg(hw,
9705                                                   I40E_GLQF_HASH_MSK(i, pctype),
9706                                                   mask_reg[i]);
9707                         }
9708                         /*clear unused mask registers of the pctype */
9709                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9710                                 i40e_check_write_global_reg(hw,
9711                                                     I40E_GLQF_FD_MSK(i, pctype),
9712                                                     0);
9713                                 i40e_check_write_global_reg(hw,
9714                                                   I40E_GLQF_HASH_MSK(i, pctype),
9715                                                   0);
9716                         }
9717                 } else {
9718                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9719                 }
9720                 I40E_WRITE_FLUSH(hw);
9721
9722                 /* store the default input set */
9723                 if (!pf->support_multi_driver)
9724                         pf->hash_input_set[pctype] = input_set;
9725                 pf->fdir.input_set[pctype] = input_set;
9726         }
9727 }
9728
9729 int
9730 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9731                          struct rte_eth_input_set_conf *conf)
9732 {
9733         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9734         enum i40e_filter_pctype pctype;
9735         uint64_t input_set, inset_reg = 0;
9736         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9737         int ret, i, num;
9738
9739         if (!conf) {
9740                 PMD_DRV_LOG(ERR, "Invalid pointer");
9741                 return -EFAULT;
9742         }
9743         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9744             conf->op != RTE_ETH_INPUT_SET_ADD) {
9745                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9746                 return -EINVAL;
9747         }
9748
9749         if (pf->support_multi_driver) {
9750                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9751                 return -ENOTSUP;
9752         }
9753
9754         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9755         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9756                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9757                 return -EINVAL;
9758         }
9759
9760         if (hw->mac.type == I40E_MAC_X722) {
9761                 /* get translated pctype value in fd pctype register */
9762                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9763                         I40E_GLQF_FD_PCTYPES((int)pctype));
9764         }
9765
9766         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9767                                    conf->inset_size);
9768         if (ret) {
9769                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9770                 return -EINVAL;
9771         }
9772
9773         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9774                 /* get inset value in register */
9775                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9776                 inset_reg <<= I40E_32_BIT_WIDTH;
9777                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9778                 input_set |= pf->hash_input_set[pctype];
9779         }
9780         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9781                                            I40E_INSET_MASK_NUM_REG);
9782         if (num < 0)
9783                 return -EINVAL;
9784
9785         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9786
9787         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9788                                     (uint32_t)(inset_reg & UINT32_MAX));
9789         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9790                                     (uint32_t)((inset_reg >>
9791                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9792
9793         for (i = 0; i < num; i++)
9794                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9795                                             mask_reg[i]);
9796         /*clear unused mask registers of the pctype */
9797         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9798                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9799                                             0);
9800         I40E_WRITE_FLUSH(hw);
9801
9802         pf->hash_input_set[pctype] = input_set;
9803         return 0;
9804 }
9805
9806 int
9807 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9808                          struct rte_eth_input_set_conf *conf)
9809 {
9810         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9811         enum i40e_filter_pctype pctype;
9812         uint64_t input_set, inset_reg = 0;
9813         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9814         int ret, i, num;
9815
9816         if (!hw || !conf) {
9817                 PMD_DRV_LOG(ERR, "Invalid pointer");
9818                 return -EFAULT;
9819         }
9820         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9821             conf->op != RTE_ETH_INPUT_SET_ADD) {
9822                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9823                 return -EINVAL;
9824         }
9825
9826         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9827
9828         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9829                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9830                 return -EINVAL;
9831         }
9832
9833         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9834                                    conf->inset_size);
9835         if (ret) {
9836                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9837                 return -EINVAL;
9838         }
9839
9840         /* get inset value in register */
9841         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9842         inset_reg <<= I40E_32_BIT_WIDTH;
9843         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9844
9845         /* Can not change the inset reg for flex payload for fdir,
9846          * it is done by writing I40E_PRTQF_FD_FLXINSET
9847          * in i40e_set_flex_mask_on_pctype.
9848          */
9849         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9850                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9851         else
9852                 input_set |= pf->fdir.input_set[pctype];
9853         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9854                                            I40E_INSET_MASK_NUM_REG);
9855         if (num < 0)
9856                 return -EINVAL;
9857         if (pf->support_multi_driver && num > 0) {
9858                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9859                 return -ENOTSUP;
9860         }
9861
9862         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9863
9864         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9865                               (uint32_t)(inset_reg & UINT32_MAX));
9866         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9867                              (uint32_t)((inset_reg >>
9868                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9869
9870         if (!pf->support_multi_driver) {
9871                 for (i = 0; i < num; i++)
9872                         i40e_check_write_global_reg(hw,
9873                                                     I40E_GLQF_FD_MSK(i, pctype),
9874                                                     mask_reg[i]);
9875                 /*clear unused mask registers of the pctype */
9876                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9877                         i40e_check_write_global_reg(hw,
9878                                                     I40E_GLQF_FD_MSK(i, pctype),
9879                                                     0);
9880         } else {
9881                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9882         }
9883         I40E_WRITE_FLUSH(hw);
9884
9885         pf->fdir.input_set[pctype] = input_set;
9886         return 0;
9887 }
9888
9889 static int
9890 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9891 {
9892         int ret = 0;
9893
9894         if (!hw || !info) {
9895                 PMD_DRV_LOG(ERR, "Invalid pointer");
9896                 return -EFAULT;
9897         }
9898
9899         switch (info->info_type) {
9900         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9901                 i40e_get_symmetric_hash_enable_per_port(hw,
9902                                         &(info->info.enable));
9903                 break;
9904         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9905                 ret = i40e_get_hash_filter_global_config(hw,
9906                                 &(info->info.global_conf));
9907                 break;
9908         default:
9909                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9910                                                         info->info_type);
9911                 ret = -EINVAL;
9912                 break;
9913         }
9914
9915         return ret;
9916 }
9917
9918 static int
9919 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9920 {
9921         int ret = 0;
9922
9923         if (!hw || !info) {
9924                 PMD_DRV_LOG(ERR, "Invalid pointer");
9925                 return -EFAULT;
9926         }
9927
9928         switch (info->info_type) {
9929         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9930                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9931                 break;
9932         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9933                 ret = i40e_set_hash_filter_global_config(hw,
9934                                 &(info->info.global_conf));
9935                 break;
9936         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9937                 ret = i40e_hash_filter_inset_select(hw,
9938                                                &(info->info.input_set_conf));
9939                 break;
9940
9941         default:
9942                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9943                                                         info->info_type);
9944                 ret = -EINVAL;
9945                 break;
9946         }
9947
9948         return ret;
9949 }
9950
9951 /* Operations for hash function */
9952 static int
9953 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9954                       enum rte_filter_op filter_op,
9955                       void *arg)
9956 {
9957         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9958         int ret = 0;
9959
9960         switch (filter_op) {
9961         case RTE_ETH_FILTER_NOP:
9962                 break;
9963         case RTE_ETH_FILTER_GET:
9964                 ret = i40e_hash_filter_get(hw,
9965                         (struct rte_eth_hash_filter_info *)arg);
9966                 break;
9967         case RTE_ETH_FILTER_SET:
9968                 ret = i40e_hash_filter_set(hw,
9969                         (struct rte_eth_hash_filter_info *)arg);
9970                 break;
9971         default:
9972                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9973                                                                 filter_op);
9974                 ret = -ENOTSUP;
9975                 break;
9976         }
9977
9978         return ret;
9979 }
9980
9981 /* Convert ethertype filter structure */
9982 static int
9983 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9984                               struct i40e_ethertype_filter *filter)
9985 {
9986         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9987                 RTE_ETHER_ADDR_LEN);
9988         filter->input.ether_type = input->ether_type;
9989         filter->flags = input->flags;
9990         filter->queue = input->queue;
9991
9992         return 0;
9993 }
9994
9995 /* Check if there exists the ehtertype filter */
9996 struct i40e_ethertype_filter *
9997 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9998                                 const struct i40e_ethertype_filter_input *input)
9999 {
10000         int ret;
10001
10002         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10003         if (ret < 0)
10004                 return NULL;
10005
10006         return ethertype_rule->hash_map[ret];
10007 }
10008
10009 /* Add ethertype filter in SW list */
10010 static int
10011 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10012                                 struct i40e_ethertype_filter *filter)
10013 {
10014         struct i40e_ethertype_rule *rule = &pf->ethertype;
10015         int ret;
10016
10017         ret = rte_hash_add_key(rule->hash_table, &filter->input);
10018         if (ret < 0) {
10019                 PMD_DRV_LOG(ERR,
10020                             "Failed to insert ethertype filter"
10021                             " to hash table %d!",
10022                             ret);
10023                 return ret;
10024         }
10025         rule->hash_map[ret] = filter;
10026
10027         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10028
10029         return 0;
10030 }
10031
10032 /* Delete ethertype filter in SW list */
10033 int
10034 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10035                              struct i40e_ethertype_filter_input *input)
10036 {
10037         struct i40e_ethertype_rule *rule = &pf->ethertype;
10038         struct i40e_ethertype_filter *filter;
10039         int ret;
10040
10041         ret = rte_hash_del_key(rule->hash_table, input);
10042         if (ret < 0) {
10043                 PMD_DRV_LOG(ERR,
10044                             "Failed to delete ethertype filter"
10045                             " to hash table %d!",
10046                             ret);
10047                 return ret;
10048         }
10049         filter = rule->hash_map[ret];
10050         rule->hash_map[ret] = NULL;
10051
10052         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10053         rte_free(filter);
10054
10055         return 0;
10056 }
10057
10058 /*
10059  * Configure ethertype filter, which can director packet by filtering
10060  * with mac address and ether_type or only ether_type
10061  */
10062 int
10063 i40e_ethertype_filter_set(struct i40e_pf *pf,
10064                         struct rte_eth_ethertype_filter *filter,
10065                         bool add)
10066 {
10067         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10068         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10069         struct i40e_ethertype_filter *ethertype_filter, *node;
10070         struct i40e_ethertype_filter check_filter;
10071         struct i40e_control_filter_stats stats;
10072         uint16_t flags = 0;
10073         int ret;
10074
10075         if (filter->queue >= pf->dev_data->nb_rx_queues) {
10076                 PMD_DRV_LOG(ERR, "Invalid queue ID");
10077                 return -EINVAL;
10078         }
10079         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10080                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10081                 PMD_DRV_LOG(ERR,
10082                         "unsupported ether_type(0x%04x) in control packet filter.",
10083                         filter->ether_type);
10084                 return -EINVAL;
10085         }
10086         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10087                 PMD_DRV_LOG(WARNING,
10088                         "filter vlan ether_type in first tag is not supported.");
10089
10090         /* Check if there is the filter in SW list */
10091         memset(&check_filter, 0, sizeof(check_filter));
10092         i40e_ethertype_filter_convert(filter, &check_filter);
10093         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10094                                                &check_filter.input);
10095         if (add && node) {
10096                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10097                 return -EINVAL;
10098         }
10099
10100         if (!add && !node) {
10101                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10102                 return -EINVAL;
10103         }
10104
10105         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10106                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10107         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10108                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10109         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10110
10111         memset(&stats, 0, sizeof(stats));
10112         ret = i40e_aq_add_rem_control_packet_filter(hw,
10113                         filter->mac_addr.addr_bytes,
10114                         filter->ether_type, flags,
10115                         pf->main_vsi->seid,
10116                         filter->queue, add, &stats, NULL);
10117
10118         PMD_DRV_LOG(INFO,
10119                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10120                 ret, stats.mac_etype_used, stats.etype_used,
10121                 stats.mac_etype_free, stats.etype_free);
10122         if (ret < 0)
10123                 return -ENOSYS;
10124
10125         /* Add or delete a filter in SW list */
10126         if (add) {
10127                 ethertype_filter = rte_zmalloc("ethertype_filter",
10128                                        sizeof(*ethertype_filter), 0);
10129                 if (ethertype_filter == NULL) {
10130                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10131                         return -ENOMEM;
10132                 }
10133
10134                 rte_memcpy(ethertype_filter, &check_filter,
10135                            sizeof(check_filter));
10136                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10137                 if (ret < 0)
10138                         rte_free(ethertype_filter);
10139         } else {
10140                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10141         }
10142
10143         return ret;
10144 }
10145
10146 /*
10147  * Handle operations for ethertype filter.
10148  */
10149 static int
10150 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10151                                 enum rte_filter_op filter_op,
10152                                 void *arg)
10153 {
10154         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10155         int ret = 0;
10156
10157         if (filter_op == RTE_ETH_FILTER_NOP)
10158                 return ret;
10159
10160         if (arg == NULL) {
10161                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10162                             filter_op);
10163                 return -EINVAL;
10164         }
10165
10166         switch (filter_op) {
10167         case RTE_ETH_FILTER_ADD:
10168                 ret = i40e_ethertype_filter_set(pf,
10169                         (struct rte_eth_ethertype_filter *)arg,
10170                         TRUE);
10171                 break;
10172         case RTE_ETH_FILTER_DELETE:
10173                 ret = i40e_ethertype_filter_set(pf,
10174                         (struct rte_eth_ethertype_filter *)arg,
10175                         FALSE);
10176                 break;
10177         default:
10178                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10179                 ret = -ENOSYS;
10180                 break;
10181         }
10182         return ret;
10183 }
10184
10185 static int
10186 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10187                      enum rte_filter_type filter_type,
10188                      enum rte_filter_op filter_op,
10189                      void *arg)
10190 {
10191         int ret = 0;
10192
10193         if (dev == NULL)
10194                 return -EINVAL;
10195
10196         switch (filter_type) {
10197         case RTE_ETH_FILTER_NONE:
10198                 /* For global configuration */
10199                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10200                 break;
10201         case RTE_ETH_FILTER_HASH:
10202                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10203                 break;
10204         case RTE_ETH_FILTER_MACVLAN:
10205                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10206                 break;
10207         case RTE_ETH_FILTER_ETHERTYPE:
10208                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10209                 break;
10210         case RTE_ETH_FILTER_TUNNEL:
10211                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10212                 break;
10213         case RTE_ETH_FILTER_FDIR:
10214                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10215                 break;
10216         case RTE_ETH_FILTER_GENERIC:
10217                 if (filter_op != RTE_ETH_FILTER_GET)
10218                         return -EINVAL;
10219                 *(const void **)arg = &i40e_flow_ops;
10220                 break;
10221         default:
10222                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10223                                                         filter_type);
10224                 ret = -EINVAL;
10225                 break;
10226         }
10227
10228         return ret;
10229 }
10230
10231 /*
10232  * Check and enable Extended Tag.
10233  * Enabling Extended Tag is important for 40G performance.
10234  */
10235 static void
10236 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10237 {
10238         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10239         uint32_t buf = 0;
10240         int ret;
10241
10242         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10243                                       PCI_DEV_CAP_REG);
10244         if (ret < 0) {
10245                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10246                             PCI_DEV_CAP_REG);
10247                 return;
10248         }
10249         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10250                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10251                 return;
10252         }
10253
10254         buf = 0;
10255         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10256                                       PCI_DEV_CTRL_REG);
10257         if (ret < 0) {
10258                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10259                             PCI_DEV_CTRL_REG);
10260                 return;
10261         }
10262         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10263                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10264                 return;
10265         }
10266         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10267         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10268                                        PCI_DEV_CTRL_REG);
10269         if (ret < 0) {
10270                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10271                             PCI_DEV_CTRL_REG);
10272                 return;
10273         }
10274 }
10275
10276 /*
10277  * As some registers wouldn't be reset unless a global hardware reset,
10278  * hardware initialization is needed to put those registers into an
10279  * expected initial state.
10280  */
10281 static void
10282 i40e_hw_init(struct rte_eth_dev *dev)
10283 {
10284         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10285
10286         i40e_enable_extended_tag(dev);
10287
10288         /* clear the PF Queue Filter control register */
10289         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10290
10291         /* Disable symmetric hash per port */
10292         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10293 }
10294
10295 /*
10296  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10297  * however this function will return only one highest pctype index,
10298  * which is not quite correct. This is known problem of i40e driver
10299  * and needs to be fixed later.
10300  */
10301 enum i40e_filter_pctype
10302 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10303 {
10304         int i;
10305         uint64_t pctype_mask;
10306
10307         if (flow_type < I40E_FLOW_TYPE_MAX) {
10308                 pctype_mask = adapter->pctypes_tbl[flow_type];
10309                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10310                         if (pctype_mask & (1ULL << i))
10311                                 return (enum i40e_filter_pctype)i;
10312                 }
10313         }
10314         return I40E_FILTER_PCTYPE_INVALID;
10315 }
10316
10317 uint16_t
10318 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10319                         enum i40e_filter_pctype pctype)
10320 {
10321         uint16_t flowtype;
10322         uint64_t pctype_mask = 1ULL << pctype;
10323
10324         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10325              flowtype++) {
10326                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10327                         return flowtype;
10328         }
10329
10330         return RTE_ETH_FLOW_UNKNOWN;
10331 }
10332
10333 /*
10334  * On X710, performance number is far from the expectation on recent firmware
10335  * versions; on XL710, performance number is also far from the expectation on
10336  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10337  * mode is enabled and port MAC address is equal to the packet destination MAC
10338  * address. The fix for this issue may not be integrated in the following
10339  * firmware version. So the workaround in software driver is needed. It needs
10340  * to modify the initial values of 3 internal only registers for both X710 and
10341  * XL710. Note that the values for X710 or XL710 could be different, and the
10342  * workaround can be removed when it is fixed in firmware in the future.
10343  */
10344
10345 /* For both X710 and XL710 */
10346 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10347 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10348 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10349
10350 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10351 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10352
10353 /* For X722 */
10354 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10355 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10356
10357 /* For X710 */
10358 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10359 /* For XL710 */
10360 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10361 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10362
10363 /*
10364  * GL_SWR_PM_UP_THR:
10365  * The value is not impacted from the link speed, its value is set according
10366  * to the total number of ports for a better pipe-monitor configuration.
10367  */
10368 static bool
10369 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10370 {
10371 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10372                 .device_id = (dev),   \
10373                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10374
10375 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10376                 .device_id = (dev),   \
10377                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10378
10379         static const struct {
10380                 uint16_t device_id;
10381                 uint32_t val;
10382         } swr_pm_table[] = {
10383                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10384                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10385                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10386                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10387
10388                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10389                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10390                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10391                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10392                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10393                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10394                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10395         };
10396         uint32_t i;
10397
10398         if (value == NULL) {
10399                 PMD_DRV_LOG(ERR, "value is NULL");
10400                 return false;
10401         }
10402
10403         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10404                 if (hw->device_id == swr_pm_table[i].device_id) {
10405                         *value = swr_pm_table[i].val;
10406
10407                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10408                                     "value - 0x%08x",
10409                                     hw->device_id, *value);
10410                         return true;
10411                 }
10412         }
10413
10414         return false;
10415 }
10416
10417 static int
10418 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10419 {
10420         enum i40e_status_code status;
10421         struct i40e_aq_get_phy_abilities_resp phy_ab;
10422         int ret = -ENOTSUP;
10423         int retries = 0;
10424
10425         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10426                                               NULL);
10427
10428         while (status) {
10429                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10430                         status);
10431                 retries++;
10432                 rte_delay_us(100000);
10433                 if  (retries < 5)
10434                         status = i40e_aq_get_phy_capabilities(hw, false,
10435                                         true, &phy_ab, NULL);
10436                 else
10437                         return ret;
10438         }
10439         return 0;
10440 }
10441
10442 static void
10443 i40e_configure_registers(struct i40e_hw *hw)
10444 {
10445         static struct {
10446                 uint32_t addr;
10447                 uint64_t val;
10448         } reg_table[] = {
10449                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10450                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10451                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10452         };
10453         uint64_t reg;
10454         uint32_t i;
10455         int ret;
10456
10457         for (i = 0; i < RTE_DIM(reg_table); i++) {
10458                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10459                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10460                                 reg_table[i].val =
10461                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10462                         else /* For X710/XL710/XXV710 */
10463                                 if (hw->aq.fw_maj_ver < 6)
10464                                         reg_table[i].val =
10465                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10466                                 else
10467                                         reg_table[i].val =
10468                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10469                 }
10470
10471                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10472                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10473                                 reg_table[i].val =
10474                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10475                         else /* For X710/XL710/XXV710 */
10476                                 reg_table[i].val =
10477                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10478                 }
10479
10480                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10481                         uint32_t cfg_val;
10482
10483                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10484                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10485                                             "GL_SWR_PM_UP_THR value fixup",
10486                                             hw->device_id);
10487                                 continue;
10488                         }
10489
10490                         reg_table[i].val = cfg_val;
10491                 }
10492
10493                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10494                                                         &reg, NULL);
10495                 if (ret < 0) {
10496                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10497                                                         reg_table[i].addr);
10498                         break;
10499                 }
10500                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10501                                                 reg_table[i].addr, reg);
10502                 if (reg == reg_table[i].val)
10503                         continue;
10504
10505                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10506                                                 reg_table[i].val, NULL);
10507                 if (ret < 0) {
10508                         PMD_DRV_LOG(ERR,
10509                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10510                                 reg_table[i].val, reg_table[i].addr);
10511                         break;
10512                 }
10513                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10514                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10515         }
10516 }
10517
10518 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10519 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10520 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10521 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10522 static int
10523 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10524 {
10525         uint32_t reg;
10526         int ret;
10527
10528         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10529                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10530                 return -EINVAL;
10531         }
10532
10533         /* Configure for double VLAN RX stripping */
10534         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10535         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10536                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10537                 ret = i40e_aq_debug_write_register(hw,
10538                                                    I40E_VSI_TSR(vsi->vsi_id),
10539                                                    reg, NULL);
10540                 if (ret < 0) {
10541                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10542                                     vsi->vsi_id);
10543                         return I40E_ERR_CONFIG;
10544                 }
10545         }
10546
10547         /* Configure for double VLAN TX insertion */
10548         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10549         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10550                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10551                 ret = i40e_aq_debug_write_register(hw,
10552                                                    I40E_VSI_L2TAGSTXVALID(
10553                                                    vsi->vsi_id), reg, NULL);
10554                 if (ret < 0) {
10555                         PMD_DRV_LOG(ERR,
10556                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10557                                 vsi->vsi_id);
10558                         return I40E_ERR_CONFIG;
10559                 }
10560         }
10561
10562         return 0;
10563 }
10564
10565 /**
10566  * i40e_aq_add_mirror_rule
10567  * @hw: pointer to the hardware structure
10568  * @seid: VEB seid to add mirror rule to
10569  * @dst_id: destination vsi seid
10570  * @entries: Buffer which contains the entities to be mirrored
10571  * @count: number of entities contained in the buffer
10572  * @rule_id:the rule_id of the rule to be added
10573  *
10574  * Add a mirror rule for a given veb.
10575  *
10576  **/
10577 static enum i40e_status_code
10578 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10579                         uint16_t seid, uint16_t dst_id,
10580                         uint16_t rule_type, uint16_t *entries,
10581                         uint16_t count, uint16_t *rule_id)
10582 {
10583         struct i40e_aq_desc desc;
10584         struct i40e_aqc_add_delete_mirror_rule cmd;
10585         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10586                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10587                 &desc.params.raw;
10588         uint16_t buff_len;
10589         enum i40e_status_code status;
10590
10591         i40e_fill_default_direct_cmd_desc(&desc,
10592                                           i40e_aqc_opc_add_mirror_rule);
10593         memset(&cmd, 0, sizeof(cmd));
10594
10595         buff_len = sizeof(uint16_t) * count;
10596         desc.datalen = rte_cpu_to_le_16(buff_len);
10597         if (buff_len > 0)
10598                 desc.flags |= rte_cpu_to_le_16(
10599                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10600         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10601                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10602         cmd.num_entries = rte_cpu_to_le_16(count);
10603         cmd.seid = rte_cpu_to_le_16(seid);
10604         cmd.destination = rte_cpu_to_le_16(dst_id);
10605
10606         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10607         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10608         PMD_DRV_LOG(INFO,
10609                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10610                 hw->aq.asq_last_status, resp->rule_id,
10611                 resp->mirror_rules_used, resp->mirror_rules_free);
10612         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10613
10614         return status;
10615 }
10616
10617 /**
10618  * i40e_aq_del_mirror_rule
10619  * @hw: pointer to the hardware structure
10620  * @seid: VEB seid to add mirror rule to
10621  * @entries: Buffer which contains the entities to be mirrored
10622  * @count: number of entities contained in the buffer
10623  * @rule_id:the rule_id of the rule to be delete
10624  *
10625  * Delete a mirror rule for a given veb.
10626  *
10627  **/
10628 static enum i40e_status_code
10629 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10630                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10631                 uint16_t count, uint16_t rule_id)
10632 {
10633         struct i40e_aq_desc desc;
10634         struct i40e_aqc_add_delete_mirror_rule cmd;
10635         uint16_t buff_len = 0;
10636         enum i40e_status_code status;
10637         void *buff = NULL;
10638
10639         i40e_fill_default_direct_cmd_desc(&desc,
10640                                           i40e_aqc_opc_delete_mirror_rule);
10641         memset(&cmd, 0, sizeof(cmd));
10642         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10643                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10644                                                           I40E_AQ_FLAG_RD));
10645                 cmd.num_entries = count;
10646                 buff_len = sizeof(uint16_t) * count;
10647                 desc.datalen = rte_cpu_to_le_16(buff_len);
10648                 buff = (void *)entries;
10649         } else
10650                 /* rule id is filled in destination field for deleting mirror rule */
10651                 cmd.destination = rte_cpu_to_le_16(rule_id);
10652
10653         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10654                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10655         cmd.seid = rte_cpu_to_le_16(seid);
10656
10657         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10658         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10659
10660         return status;
10661 }
10662
10663 /**
10664  * i40e_mirror_rule_set
10665  * @dev: pointer to the hardware structure
10666  * @mirror_conf: mirror rule info
10667  * @sw_id: mirror rule's sw_id
10668  * @on: enable/disable
10669  *
10670  * set a mirror rule.
10671  *
10672  **/
10673 static int
10674 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10675                         struct rte_eth_mirror_conf *mirror_conf,
10676                         uint8_t sw_id, uint8_t on)
10677 {
10678         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10679         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10680         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10681         struct i40e_mirror_rule *parent = NULL;
10682         uint16_t seid, dst_seid, rule_id;
10683         uint16_t i, j = 0;
10684         int ret;
10685
10686         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10687
10688         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10689                 PMD_DRV_LOG(ERR,
10690                         "mirror rule can not be configured without veb or vfs.");
10691                 return -ENOSYS;
10692         }
10693         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10694                 PMD_DRV_LOG(ERR, "mirror table is full.");
10695                 return -ENOSPC;
10696         }
10697         if (mirror_conf->dst_pool > pf->vf_num) {
10698                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10699                                  mirror_conf->dst_pool);
10700                 return -EINVAL;
10701         }
10702
10703         seid = pf->main_vsi->veb->seid;
10704
10705         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10706                 if (sw_id <= it->index) {
10707                         mirr_rule = it;
10708                         break;
10709                 }
10710                 parent = it;
10711         }
10712         if (mirr_rule && sw_id == mirr_rule->index) {
10713                 if (on) {
10714                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10715                         return -EEXIST;
10716                 } else {
10717                         ret = i40e_aq_del_mirror_rule(hw, seid,
10718                                         mirr_rule->rule_type,
10719                                         mirr_rule->entries,
10720                                         mirr_rule->num_entries, mirr_rule->id);
10721                         if (ret < 0) {
10722                                 PMD_DRV_LOG(ERR,
10723                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10724                                         ret, hw->aq.asq_last_status);
10725                                 return -ENOSYS;
10726                         }
10727                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10728                         rte_free(mirr_rule);
10729                         pf->nb_mirror_rule--;
10730                         return 0;
10731                 }
10732         } else if (!on) {
10733                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10734                 return -ENOENT;
10735         }
10736
10737         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10738                                 sizeof(struct i40e_mirror_rule) , 0);
10739         if (!mirr_rule) {
10740                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10741                 return I40E_ERR_NO_MEMORY;
10742         }
10743         switch (mirror_conf->rule_type) {
10744         case ETH_MIRROR_VLAN:
10745                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10746                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10747                                 mirr_rule->entries[j] =
10748                                         mirror_conf->vlan.vlan_id[i];
10749                                 j++;
10750                         }
10751                 }
10752                 if (j == 0) {
10753                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10754                         rte_free(mirr_rule);
10755                         return -EINVAL;
10756                 }
10757                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10758                 break;
10759         case ETH_MIRROR_VIRTUAL_POOL_UP:
10760         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10761                 /* check if the specified pool bit is out of range */
10762                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10763                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10764                         rte_free(mirr_rule);
10765                         return -EINVAL;
10766                 }
10767                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10768                         if (mirror_conf->pool_mask & (1ULL << i)) {
10769                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10770                                 j++;
10771                         }
10772                 }
10773                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10774                         /* add pf vsi to entries */
10775                         mirr_rule->entries[j] = pf->main_vsi_seid;
10776                         j++;
10777                 }
10778                 if (j == 0) {
10779                         PMD_DRV_LOG(ERR, "pool is not specified.");
10780                         rte_free(mirr_rule);
10781                         return -EINVAL;
10782                 }
10783                 /* egress and ingress in aq commands means from switch but not port */
10784                 mirr_rule->rule_type =
10785                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10786                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10787                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10788                 break;
10789         case ETH_MIRROR_UPLINK_PORT:
10790                 /* egress and ingress in aq commands means from switch but not port*/
10791                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10792                 break;
10793         case ETH_MIRROR_DOWNLINK_PORT:
10794                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10795                 break;
10796         default:
10797                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10798                         mirror_conf->rule_type);
10799                 rte_free(mirr_rule);
10800                 return -EINVAL;
10801         }
10802
10803         /* If the dst_pool is equal to vf_num, consider it as PF */
10804         if (mirror_conf->dst_pool == pf->vf_num)
10805                 dst_seid = pf->main_vsi_seid;
10806         else
10807                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10808
10809         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10810                                       mirr_rule->rule_type, mirr_rule->entries,
10811                                       j, &rule_id);
10812         if (ret < 0) {
10813                 PMD_DRV_LOG(ERR,
10814                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10815                         ret, hw->aq.asq_last_status);
10816                 rte_free(mirr_rule);
10817                 return -ENOSYS;
10818         }
10819
10820         mirr_rule->index = sw_id;
10821         mirr_rule->num_entries = j;
10822         mirr_rule->id = rule_id;
10823         mirr_rule->dst_vsi_seid = dst_seid;
10824
10825         if (parent)
10826                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10827         else
10828                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10829
10830         pf->nb_mirror_rule++;
10831         return 0;
10832 }
10833
10834 /**
10835  * i40e_mirror_rule_reset
10836  * @dev: pointer to the device
10837  * @sw_id: mirror rule's sw_id
10838  *
10839  * reset a mirror rule.
10840  *
10841  **/
10842 static int
10843 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10844 {
10845         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10846         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10847         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10848         uint16_t seid;
10849         int ret;
10850
10851         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10852
10853         seid = pf->main_vsi->veb->seid;
10854
10855         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10856                 if (sw_id == it->index) {
10857                         mirr_rule = it;
10858                         break;
10859                 }
10860         }
10861         if (mirr_rule) {
10862                 ret = i40e_aq_del_mirror_rule(hw, seid,
10863                                 mirr_rule->rule_type,
10864                                 mirr_rule->entries,
10865                                 mirr_rule->num_entries, mirr_rule->id);
10866                 if (ret < 0) {
10867                         PMD_DRV_LOG(ERR,
10868                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10869                                 ret, hw->aq.asq_last_status);
10870                         return -ENOSYS;
10871                 }
10872                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10873                 rte_free(mirr_rule);
10874                 pf->nb_mirror_rule--;
10875         } else {
10876                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10877                 return -ENOENT;
10878         }
10879         return 0;
10880 }
10881
10882 static uint64_t
10883 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10884 {
10885         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10886         uint64_t systim_cycles;
10887
10888         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10889         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10890                         << 32;
10891
10892         return systim_cycles;
10893 }
10894
10895 static uint64_t
10896 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10897 {
10898         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10899         uint64_t rx_tstamp;
10900
10901         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10902         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10903                         << 32;
10904
10905         return rx_tstamp;
10906 }
10907
10908 static uint64_t
10909 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10910 {
10911         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10912         uint64_t tx_tstamp;
10913
10914         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10915         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10916                         << 32;
10917
10918         return tx_tstamp;
10919 }
10920
10921 static void
10922 i40e_start_timecounters(struct rte_eth_dev *dev)
10923 {
10924         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10925         struct i40e_adapter *adapter = dev->data->dev_private;
10926         struct rte_eth_link link;
10927         uint32_t tsync_inc_l;
10928         uint32_t tsync_inc_h;
10929
10930         /* Get current link speed. */
10931         i40e_dev_link_update(dev, 1);
10932         rte_eth_linkstatus_get(dev, &link);
10933
10934         switch (link.link_speed) {
10935         case ETH_SPEED_NUM_40G:
10936         case ETH_SPEED_NUM_25G:
10937                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10938                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10939                 break;
10940         case ETH_SPEED_NUM_10G:
10941                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10942                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10943                 break;
10944         case ETH_SPEED_NUM_1G:
10945                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10946                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10947                 break;
10948         default:
10949                 tsync_inc_l = 0x0;
10950                 tsync_inc_h = 0x0;
10951         }
10952
10953         /* Set the timesync increment value. */
10954         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10955         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10956
10957         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10958         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10959         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10960
10961         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10962         adapter->systime_tc.cc_shift = 0;
10963         adapter->systime_tc.nsec_mask = 0;
10964
10965         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10966         adapter->rx_tstamp_tc.cc_shift = 0;
10967         adapter->rx_tstamp_tc.nsec_mask = 0;
10968
10969         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10970         adapter->tx_tstamp_tc.cc_shift = 0;
10971         adapter->tx_tstamp_tc.nsec_mask = 0;
10972 }
10973
10974 static int
10975 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10976 {
10977         struct i40e_adapter *adapter = dev->data->dev_private;
10978
10979         adapter->systime_tc.nsec += delta;
10980         adapter->rx_tstamp_tc.nsec += delta;
10981         adapter->tx_tstamp_tc.nsec += delta;
10982
10983         return 0;
10984 }
10985
10986 static int
10987 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10988 {
10989         uint64_t ns;
10990         struct i40e_adapter *adapter = dev->data->dev_private;
10991
10992         ns = rte_timespec_to_ns(ts);
10993
10994         /* Set the timecounters to a new value. */
10995         adapter->systime_tc.nsec = ns;
10996         adapter->rx_tstamp_tc.nsec = ns;
10997         adapter->tx_tstamp_tc.nsec = ns;
10998
10999         return 0;
11000 }
11001
11002 static int
11003 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11004 {
11005         uint64_t ns, systime_cycles;
11006         struct i40e_adapter *adapter = dev->data->dev_private;
11007
11008         systime_cycles = i40e_read_systime_cyclecounter(dev);
11009         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11010         *ts = rte_ns_to_timespec(ns);
11011
11012         return 0;
11013 }
11014
11015 static int
11016 i40e_timesync_enable(struct rte_eth_dev *dev)
11017 {
11018         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11019         uint32_t tsync_ctl_l;
11020         uint32_t tsync_ctl_h;
11021
11022         /* Stop the timesync system time. */
11023         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11024         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11025         /* Reset the timesync system time value. */
11026         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11027         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11028
11029         i40e_start_timecounters(dev);
11030
11031         /* Clear timesync registers. */
11032         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11033         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11034         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11035         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11036         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11037         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11038
11039         /* Enable timestamping of PTP packets. */
11040         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11041         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11042
11043         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11044         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11045         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11046
11047         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11048         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11049
11050         return 0;
11051 }
11052
11053 static int
11054 i40e_timesync_disable(struct rte_eth_dev *dev)
11055 {
11056         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11057         uint32_t tsync_ctl_l;
11058         uint32_t tsync_ctl_h;
11059
11060         /* Disable timestamping of transmitted PTP packets. */
11061         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11062         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11063
11064         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11065         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11066
11067         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11068         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11069
11070         /* Reset the timesync increment value. */
11071         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11072         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11073
11074         return 0;
11075 }
11076
11077 static int
11078 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11079                                 struct timespec *timestamp, uint32_t flags)
11080 {
11081         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11082         struct i40e_adapter *adapter = dev->data->dev_private;
11083         uint32_t sync_status;
11084         uint32_t index = flags & 0x03;
11085         uint64_t rx_tstamp_cycles;
11086         uint64_t ns;
11087
11088         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11089         if ((sync_status & (1 << index)) == 0)
11090                 return -EINVAL;
11091
11092         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11093         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11094         *timestamp = rte_ns_to_timespec(ns);
11095
11096         return 0;
11097 }
11098
11099 static int
11100 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11101                                 struct timespec *timestamp)
11102 {
11103         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11104         struct i40e_adapter *adapter = dev->data->dev_private;
11105         uint32_t sync_status;
11106         uint64_t tx_tstamp_cycles;
11107         uint64_t ns;
11108
11109         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11110         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11111                 return -EINVAL;
11112
11113         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11114         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11115         *timestamp = rte_ns_to_timespec(ns);
11116
11117         return 0;
11118 }
11119
11120 /*
11121  * i40e_parse_dcb_configure - parse dcb configure from user
11122  * @dev: the device being configured
11123  * @dcb_cfg: pointer of the result of parse
11124  * @*tc_map: bit map of enabled traffic classes
11125  *
11126  * Returns 0 on success, negative value on failure
11127  */
11128 static int
11129 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11130                          struct i40e_dcbx_config *dcb_cfg,
11131                          uint8_t *tc_map)
11132 {
11133         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11134         uint8_t i, tc_bw, bw_lf;
11135
11136         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11137
11138         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11139         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11140                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11141                 return -EINVAL;
11142         }
11143
11144         /* assume each tc has the same bw */
11145         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11146         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11147                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11148         /* to ensure the sum of tcbw is equal to 100 */
11149         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11150         for (i = 0; i < bw_lf; i++)
11151                 dcb_cfg->etscfg.tcbwtable[i]++;
11152
11153         /* assume each tc has the same Transmission Selection Algorithm */
11154         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11155                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11156
11157         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11158                 dcb_cfg->etscfg.prioritytable[i] =
11159                                 dcb_rx_conf->dcb_tc[i];
11160
11161         /* FW needs one App to configure HW */
11162         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11163         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11164         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11165         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11166
11167         if (dcb_rx_conf->nb_tcs == 0)
11168                 *tc_map = 1; /* tc0 only */
11169         else
11170                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11171
11172         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11173                 dcb_cfg->pfc.willing = 0;
11174                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11175                 dcb_cfg->pfc.pfcenable = *tc_map;
11176         }
11177         return 0;
11178 }
11179
11180
11181 static enum i40e_status_code
11182 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11183                               struct i40e_aqc_vsi_properties_data *info,
11184                               uint8_t enabled_tcmap)
11185 {
11186         enum i40e_status_code ret;
11187         int i, total_tc = 0;
11188         uint16_t qpnum_per_tc, bsf, qp_idx;
11189         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11190         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11191         uint16_t used_queues;
11192
11193         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11194         if (ret != I40E_SUCCESS)
11195                 return ret;
11196
11197         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11198                 if (enabled_tcmap & (1 << i))
11199                         total_tc++;
11200         }
11201         if (total_tc == 0)
11202                 total_tc = 1;
11203         vsi->enabled_tc = enabled_tcmap;
11204
11205         /* different VSI has different queues assigned */
11206         if (vsi->type == I40E_VSI_MAIN)
11207                 used_queues = dev_data->nb_rx_queues -
11208                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11209         else if (vsi->type == I40E_VSI_VMDQ2)
11210                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11211         else {
11212                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11213                 return I40E_ERR_NO_AVAILABLE_VSI;
11214         }
11215
11216         qpnum_per_tc = used_queues / total_tc;
11217         /* Number of queues per enabled TC */
11218         if (qpnum_per_tc == 0) {
11219                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11220                 return I40E_ERR_INVALID_QP_ID;
11221         }
11222         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11223                                 I40E_MAX_Q_PER_TC);
11224         bsf = rte_bsf32(qpnum_per_tc);
11225
11226         /**
11227          * Configure TC and queue mapping parameters, for enabled TC,
11228          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11229          * default queue will serve it.
11230          */
11231         qp_idx = 0;
11232         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11233                 if (vsi->enabled_tc & (1 << i)) {
11234                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11235                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11236                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11237                         qp_idx += qpnum_per_tc;
11238                 } else
11239                         info->tc_mapping[i] = 0;
11240         }
11241
11242         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11243         if (vsi->type == I40E_VSI_SRIOV) {
11244                 info->mapping_flags |=
11245                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11246                 for (i = 0; i < vsi->nb_qps; i++)
11247                         info->queue_mapping[i] =
11248                                 rte_cpu_to_le_16(vsi->base_queue + i);
11249         } else {
11250                 info->mapping_flags |=
11251                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11252                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11253         }
11254         info->valid_sections |=
11255                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11256
11257         return I40E_SUCCESS;
11258 }
11259
11260 /*
11261  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11262  * @veb: VEB to be configured
11263  * @tc_map: enabled TC bitmap
11264  *
11265  * Returns 0 on success, negative value on failure
11266  */
11267 static enum i40e_status_code
11268 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11269 {
11270         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11271         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11272         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11273         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11274         enum i40e_status_code ret = I40E_SUCCESS;
11275         int i;
11276         uint32_t bw_max;
11277
11278         /* Check if enabled_tc is same as existing or new TCs */
11279         if (veb->enabled_tc == tc_map)
11280                 return ret;
11281
11282         /* configure tc bandwidth */
11283         memset(&veb_bw, 0, sizeof(veb_bw));
11284         veb_bw.tc_valid_bits = tc_map;
11285         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11286         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11287                 if (tc_map & BIT_ULL(i))
11288                         veb_bw.tc_bw_share_credits[i] = 1;
11289         }
11290         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11291                                                    &veb_bw, NULL);
11292         if (ret) {
11293                 PMD_INIT_LOG(ERR,
11294                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11295                         hw->aq.asq_last_status);
11296                 return ret;
11297         }
11298
11299         memset(&ets_query, 0, sizeof(ets_query));
11300         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11301                                                    &ets_query, NULL);
11302         if (ret != I40E_SUCCESS) {
11303                 PMD_DRV_LOG(ERR,
11304                         "Failed to get switch_comp ETS configuration %u",
11305                         hw->aq.asq_last_status);
11306                 return ret;
11307         }
11308         memset(&bw_query, 0, sizeof(bw_query));
11309         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11310                                                   &bw_query, NULL);
11311         if (ret != I40E_SUCCESS) {
11312                 PMD_DRV_LOG(ERR,
11313                         "Failed to get switch_comp bandwidth configuration %u",
11314                         hw->aq.asq_last_status);
11315                 return ret;
11316         }
11317
11318         /* store and print out BW info */
11319         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11320         veb->bw_info.bw_max = ets_query.tc_bw_max;
11321         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11322         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11323         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11324                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11325                      I40E_16_BIT_WIDTH);
11326         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11327                 veb->bw_info.bw_ets_share_credits[i] =
11328                                 bw_query.tc_bw_share_credits[i];
11329                 veb->bw_info.bw_ets_credits[i] =
11330                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11331                 /* 4 bits per TC, 4th bit is reserved */
11332                 veb->bw_info.bw_ets_max[i] =
11333                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11334                                   RTE_LEN2MASK(3, uint8_t));
11335                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11336                             veb->bw_info.bw_ets_share_credits[i]);
11337                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11338                             veb->bw_info.bw_ets_credits[i]);
11339                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11340                             veb->bw_info.bw_ets_max[i]);
11341         }
11342
11343         veb->enabled_tc = tc_map;
11344
11345         return ret;
11346 }
11347
11348
11349 /*
11350  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11351  * @vsi: VSI to be configured
11352  * @tc_map: enabled TC bitmap
11353  *
11354  * Returns 0 on success, negative value on failure
11355  */
11356 static enum i40e_status_code
11357 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11358 {
11359         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11360         struct i40e_vsi_context ctxt;
11361         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11362         enum i40e_status_code ret = I40E_SUCCESS;
11363         int i;
11364
11365         /* Check if enabled_tc is same as existing or new TCs */
11366         if (vsi->enabled_tc == tc_map)
11367                 return ret;
11368
11369         /* configure tc bandwidth */
11370         memset(&bw_data, 0, sizeof(bw_data));
11371         bw_data.tc_valid_bits = tc_map;
11372         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11373         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11374                 if (tc_map & BIT_ULL(i))
11375                         bw_data.tc_bw_credits[i] = 1;
11376         }
11377         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11378         if (ret) {
11379                 PMD_INIT_LOG(ERR,
11380                         "AQ command Config VSI BW allocation per TC failed = %d",
11381                         hw->aq.asq_last_status);
11382                 goto out;
11383         }
11384         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11385                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11386
11387         /* Update Queue Pairs Mapping for currently enabled UPs */
11388         ctxt.seid = vsi->seid;
11389         ctxt.pf_num = hw->pf_id;
11390         ctxt.vf_num = 0;
11391         ctxt.uplink_seid = vsi->uplink_seid;
11392         ctxt.info = vsi->info;
11393         i40e_get_cap(hw);
11394         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11395         if (ret)
11396                 goto out;
11397
11398         /* Update the VSI after updating the VSI queue-mapping information */
11399         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11400         if (ret) {
11401                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11402                         hw->aq.asq_last_status);
11403                 goto out;
11404         }
11405         /* update the local VSI info with updated queue map */
11406         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11407                                         sizeof(vsi->info.tc_mapping));
11408         rte_memcpy(&vsi->info.queue_mapping,
11409                         &ctxt.info.queue_mapping,
11410                 sizeof(vsi->info.queue_mapping));
11411         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11412         vsi->info.valid_sections = 0;
11413
11414         /* query and update current VSI BW information */
11415         ret = i40e_vsi_get_bw_config(vsi);
11416         if (ret) {
11417                 PMD_INIT_LOG(ERR,
11418                          "Failed updating vsi bw info, err %s aq_err %s",
11419                          i40e_stat_str(hw, ret),
11420                          i40e_aq_str(hw, hw->aq.asq_last_status));
11421                 goto out;
11422         }
11423
11424         vsi->enabled_tc = tc_map;
11425
11426 out:
11427         return ret;
11428 }
11429
11430 /*
11431  * i40e_dcb_hw_configure - program the dcb setting to hw
11432  * @pf: pf the configuration is taken on
11433  * @new_cfg: new configuration
11434  * @tc_map: enabled TC bitmap
11435  *
11436  * Returns 0 on success, negative value on failure
11437  */
11438 static enum i40e_status_code
11439 i40e_dcb_hw_configure(struct i40e_pf *pf,
11440                       struct i40e_dcbx_config *new_cfg,
11441                       uint8_t tc_map)
11442 {
11443         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11444         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11445         struct i40e_vsi *main_vsi = pf->main_vsi;
11446         struct i40e_vsi_list *vsi_list;
11447         enum i40e_status_code ret;
11448         int i;
11449         uint32_t val;
11450
11451         /* Use the FW API if FW > v4.4*/
11452         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11453               (hw->aq.fw_maj_ver >= 5))) {
11454                 PMD_INIT_LOG(ERR,
11455                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11456                 return I40E_ERR_FIRMWARE_API_VERSION;
11457         }
11458
11459         /* Check if need reconfiguration */
11460         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11461                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11462                 return I40E_SUCCESS;
11463         }
11464
11465         /* Copy the new config to the current config */
11466         *old_cfg = *new_cfg;
11467         old_cfg->etsrec = old_cfg->etscfg;
11468         ret = i40e_set_dcb_config(hw);
11469         if (ret) {
11470                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11471                          i40e_stat_str(hw, ret),
11472                          i40e_aq_str(hw, hw->aq.asq_last_status));
11473                 return ret;
11474         }
11475         /* set receive Arbiter to RR mode and ETS scheme by default */
11476         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11477                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11478                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11479                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11480                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11481                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11482                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11483                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11484                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11485                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11486                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11487                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11488                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11489         }
11490         /* get local mib to check whether it is configured correctly */
11491         /* IEEE mode */
11492         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11493         /* Get Local DCB Config */
11494         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11495                                      &hw->local_dcbx_config);
11496
11497         /* if Veb is created, need to update TC of it at first */
11498         if (main_vsi->veb) {
11499                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11500                 if (ret)
11501                         PMD_INIT_LOG(WARNING,
11502                                  "Failed configuring TC for VEB seid=%d",
11503                                  main_vsi->veb->seid);
11504         }
11505         /* Update each VSI */
11506         i40e_vsi_config_tc(main_vsi, tc_map);
11507         if (main_vsi->veb) {
11508                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11509                         /* Beside main VSI and VMDQ VSIs, only enable default
11510                          * TC for other VSIs
11511                          */
11512                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11513                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11514                                                          tc_map);
11515                         else
11516                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11517                                                          I40E_DEFAULT_TCMAP);
11518                         if (ret)
11519                                 PMD_INIT_LOG(WARNING,
11520                                         "Failed configuring TC for VSI seid=%d",
11521                                         vsi_list->vsi->seid);
11522                         /* continue */
11523                 }
11524         }
11525         return I40E_SUCCESS;
11526 }
11527
11528 /*
11529  * i40e_dcb_init_configure - initial dcb config
11530  * @dev: device being configured
11531  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11532  *
11533  * Returns 0 on success, negative value on failure
11534  */
11535 int
11536 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11537 {
11538         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11539         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11540         int i, ret = 0;
11541
11542         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11543                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11544                 return -ENOTSUP;
11545         }
11546
11547         /* DCB initialization:
11548          * Update DCB configuration from the Firmware and configure
11549          * LLDP MIB change event.
11550          */
11551         if (sw_dcb == TRUE) {
11552                 if (i40e_need_stop_lldp(dev)) {
11553                         ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11554                         if (ret != I40E_SUCCESS)
11555                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11556                 }
11557
11558                 ret = i40e_init_dcb(hw);
11559                 /* If lldp agent is stopped, the return value from
11560                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11561                  * adminq status. Otherwise, it should return success.
11562                  */
11563                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11564                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11565                         memset(&hw->local_dcbx_config, 0,
11566                                 sizeof(struct i40e_dcbx_config));
11567                         /* set dcb default configuration */
11568                         hw->local_dcbx_config.etscfg.willing = 0;
11569                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11570                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11571                         hw->local_dcbx_config.etscfg.tsatable[0] =
11572                                                 I40E_IEEE_TSA_ETS;
11573                         /* all UPs mapping to TC0 */
11574                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11575                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11576                         hw->local_dcbx_config.etsrec =
11577                                 hw->local_dcbx_config.etscfg;
11578                         hw->local_dcbx_config.pfc.willing = 0;
11579                         hw->local_dcbx_config.pfc.pfccap =
11580                                                 I40E_MAX_TRAFFIC_CLASS;
11581                         /* FW needs one App to configure HW */
11582                         hw->local_dcbx_config.numapps = 1;
11583                         hw->local_dcbx_config.app[0].selector =
11584                                                 I40E_APP_SEL_ETHTYPE;
11585                         hw->local_dcbx_config.app[0].priority = 3;
11586                         hw->local_dcbx_config.app[0].protocolid =
11587                                                 I40E_APP_PROTOID_FCOE;
11588                         ret = i40e_set_dcb_config(hw);
11589                         if (ret) {
11590                                 PMD_INIT_LOG(ERR,
11591                                         "default dcb config fails. err = %d, aq_err = %d.",
11592                                         ret, hw->aq.asq_last_status);
11593                                 return -ENOSYS;
11594                         }
11595                 } else {
11596                         PMD_INIT_LOG(ERR,
11597                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11598                                 ret, hw->aq.asq_last_status);
11599                         return -ENOTSUP;
11600                 }
11601         } else {
11602                 ret = i40e_aq_start_lldp(hw, NULL);
11603                 if (ret != I40E_SUCCESS)
11604                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11605
11606                 ret = i40e_init_dcb(hw);
11607                 if (!ret) {
11608                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11609                                 PMD_INIT_LOG(ERR,
11610                                         "HW doesn't support DCBX offload.");
11611                                 return -ENOTSUP;
11612                         }
11613                 } else {
11614                         PMD_INIT_LOG(ERR,
11615                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11616                                 ret, hw->aq.asq_last_status);
11617                         return -ENOTSUP;
11618                 }
11619         }
11620         return 0;
11621 }
11622
11623 /*
11624  * i40e_dcb_setup - setup dcb related config
11625  * @dev: device being configured
11626  *
11627  * Returns 0 on success, negative value on failure
11628  */
11629 static int
11630 i40e_dcb_setup(struct rte_eth_dev *dev)
11631 {
11632         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11633         struct i40e_dcbx_config dcb_cfg;
11634         uint8_t tc_map = 0;
11635         int ret = 0;
11636
11637         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11638                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11639                 return -ENOTSUP;
11640         }
11641
11642         if (pf->vf_num != 0)
11643                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11644
11645         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11646         if (ret) {
11647                 PMD_INIT_LOG(ERR, "invalid dcb config");
11648                 return -EINVAL;
11649         }
11650         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11651         if (ret) {
11652                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11653                 return -ENOSYS;
11654         }
11655
11656         return 0;
11657 }
11658
11659 static int
11660 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11661                       struct rte_eth_dcb_info *dcb_info)
11662 {
11663         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11664         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11665         struct i40e_vsi *vsi = pf->main_vsi;
11666         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11667         uint16_t bsf, tc_mapping;
11668         int i, j = 0;
11669
11670         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11671                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11672         else
11673                 dcb_info->nb_tcs = 1;
11674         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11675                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11676         for (i = 0; i < dcb_info->nb_tcs; i++)
11677                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11678
11679         /* get queue mapping if vmdq is disabled */
11680         if (!pf->nb_cfg_vmdq_vsi) {
11681                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11682                         if (!(vsi->enabled_tc & (1 << i)))
11683                                 continue;
11684                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11685                         dcb_info->tc_queue.tc_rxq[j][i].base =
11686                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11687                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11688                         dcb_info->tc_queue.tc_txq[j][i].base =
11689                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11690                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11691                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11692                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11693                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11694                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11695                 }
11696                 return 0;
11697         }
11698
11699         /* get queue mapping if vmdq is enabled */
11700         do {
11701                 vsi = pf->vmdq[j].vsi;
11702                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11703                         if (!(vsi->enabled_tc & (1 << i)))
11704                                 continue;
11705                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11706                         dcb_info->tc_queue.tc_rxq[j][i].base =
11707                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11708                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11709                         dcb_info->tc_queue.tc_txq[j][i].base =
11710                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11711                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11712                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11713                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11714                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11715                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11716                 }
11717                 j++;
11718         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11719         return 0;
11720 }
11721
11722 static int
11723 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11724 {
11725         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11726         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11727         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11728         uint16_t msix_intr;
11729
11730         msix_intr = intr_handle->intr_vec[queue_id];
11731         if (msix_intr == I40E_MISC_VEC_ID)
11732                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11733                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11734                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11735                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11736         else
11737                 I40E_WRITE_REG(hw,
11738                                I40E_PFINT_DYN_CTLN(msix_intr -
11739                                                    I40E_RX_VEC_START),
11740                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11741                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11742                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11743
11744         I40E_WRITE_FLUSH(hw);
11745         rte_intr_ack(&pci_dev->intr_handle);
11746
11747         return 0;
11748 }
11749
11750 static int
11751 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11752 {
11753         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11754         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11755         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11756         uint16_t msix_intr;
11757
11758         msix_intr = intr_handle->intr_vec[queue_id];
11759         if (msix_intr == I40E_MISC_VEC_ID)
11760                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11761                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11762         else
11763                 I40E_WRITE_REG(hw,
11764                                I40E_PFINT_DYN_CTLN(msix_intr -
11765                                                    I40E_RX_VEC_START),
11766                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11767         I40E_WRITE_FLUSH(hw);
11768
11769         return 0;
11770 }
11771
11772 /**
11773  * This function is used to check if the register is valid.
11774  * Below is the valid registers list for X722 only:
11775  * 0x2b800--0x2bb00
11776  * 0x38700--0x38a00
11777  * 0x3d800--0x3db00
11778  * 0x208e00--0x209000
11779  * 0x20be00--0x20c000
11780  * 0x263c00--0x264000
11781  * 0x265c00--0x266000
11782  */
11783 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11784 {
11785         if ((type != I40E_MAC_X722) &&
11786             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11787              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11788              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11789              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11790              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11791              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11792              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11793                 return 0;
11794         else
11795                 return 1;
11796 }
11797
11798 static int i40e_get_regs(struct rte_eth_dev *dev,
11799                          struct rte_dev_reg_info *regs)
11800 {
11801         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11802         uint32_t *ptr_data = regs->data;
11803         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11804         const struct i40e_reg_info *reg_info;
11805
11806         if (ptr_data == NULL) {
11807                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11808                 regs->width = sizeof(uint32_t);
11809                 return 0;
11810         }
11811
11812         /* The first few registers have to be read using AQ operations */
11813         reg_idx = 0;
11814         while (i40e_regs_adminq[reg_idx].name) {
11815                 reg_info = &i40e_regs_adminq[reg_idx++];
11816                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11817                         for (arr_idx2 = 0;
11818                                         arr_idx2 <= reg_info->count2;
11819                                         arr_idx2++) {
11820                                 reg_offset = arr_idx * reg_info->stride1 +
11821                                         arr_idx2 * reg_info->stride2;
11822                                 reg_offset += reg_info->base_addr;
11823                                 ptr_data[reg_offset >> 2] =
11824                                         i40e_read_rx_ctl(hw, reg_offset);
11825                         }
11826         }
11827
11828         /* The remaining registers can be read using primitives */
11829         reg_idx = 0;
11830         while (i40e_regs_others[reg_idx].name) {
11831                 reg_info = &i40e_regs_others[reg_idx++];
11832                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11833                         for (arr_idx2 = 0;
11834                                         arr_idx2 <= reg_info->count2;
11835                                         arr_idx2++) {
11836                                 reg_offset = arr_idx * reg_info->stride1 +
11837                                         arr_idx2 * reg_info->stride2;
11838                                 reg_offset += reg_info->base_addr;
11839                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11840                                         ptr_data[reg_offset >> 2] = 0;
11841                                 else
11842                                         ptr_data[reg_offset >> 2] =
11843                                                 I40E_READ_REG(hw, reg_offset);
11844                         }
11845         }
11846
11847         return 0;
11848 }
11849
11850 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11851 {
11852         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11853
11854         /* Convert word count to byte count */
11855         return hw->nvm.sr_size << 1;
11856 }
11857
11858 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11859                            struct rte_dev_eeprom_info *eeprom)
11860 {
11861         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11862         uint16_t *data = eeprom->data;
11863         uint16_t offset, length, cnt_words;
11864         int ret_code;
11865
11866         offset = eeprom->offset >> 1;
11867         length = eeprom->length >> 1;
11868         cnt_words = length;
11869
11870         if (offset > hw->nvm.sr_size ||
11871                 offset + length > hw->nvm.sr_size) {
11872                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11873                 return -EINVAL;
11874         }
11875
11876         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11877
11878         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11879         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11880                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11881                 return -EIO;
11882         }
11883
11884         return 0;
11885 }
11886
11887 static int i40e_get_module_info(struct rte_eth_dev *dev,
11888                                 struct rte_eth_dev_module_info *modinfo)
11889 {
11890         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11891         uint32_t sff8472_comp = 0;
11892         uint32_t sff8472_swap = 0;
11893         uint32_t sff8636_rev = 0;
11894         i40e_status status;
11895         uint32_t type = 0;
11896
11897         /* Check if firmware supports reading module EEPROM. */
11898         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11899                 PMD_DRV_LOG(ERR,
11900                             "Module EEPROM memory read not supported. "
11901                             "Please update the NVM image.\n");
11902                 return -EINVAL;
11903         }
11904
11905         status = i40e_update_link_info(hw);
11906         if (status)
11907                 return -EIO;
11908
11909         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11910                 PMD_DRV_LOG(ERR,
11911                             "Cannot read module EEPROM memory. "
11912                             "No module connected.\n");
11913                 return -EINVAL;
11914         }
11915
11916         type = hw->phy.link_info.module_type[0];
11917
11918         switch (type) {
11919         case I40E_MODULE_TYPE_SFP:
11920                 status = i40e_aq_get_phy_register(hw,
11921                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11922                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11923                                 I40E_MODULE_SFF_8472_COMP,
11924                                 &sff8472_comp, NULL);
11925                 if (status)
11926                         return -EIO;
11927
11928                 status = i40e_aq_get_phy_register(hw,
11929                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11930                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11931                                 I40E_MODULE_SFF_8472_SWAP,
11932                                 &sff8472_swap, NULL);
11933                 if (status)
11934                         return -EIO;
11935
11936                 /* Check if the module requires address swap to access
11937                  * the other EEPROM memory page.
11938                  */
11939                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11940                         PMD_DRV_LOG(WARNING,
11941                                     "Module address swap to access "
11942                                     "page 0xA2 is not supported.\n");
11943                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11944                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11945                 } else if (sff8472_comp == 0x00) {
11946                         /* Module is not SFF-8472 compliant */
11947                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11948                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11949                 } else {
11950                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11951                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11952                 }
11953                 break;
11954         case I40E_MODULE_TYPE_QSFP_PLUS:
11955                 /* Read from memory page 0. */
11956                 status = i40e_aq_get_phy_register(hw,
11957                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11958                                 0, 1,
11959                                 I40E_MODULE_REVISION_ADDR,
11960                                 &sff8636_rev, NULL);
11961                 if (status)
11962                         return -EIO;
11963                 /* Determine revision compliance byte */
11964                 if (sff8636_rev > 0x02) {
11965                         /* Module is SFF-8636 compliant */
11966                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11967                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11968                 } else {
11969                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11970                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11971                 }
11972                 break;
11973         case I40E_MODULE_TYPE_QSFP28:
11974                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11975                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11976                 break;
11977         default:
11978                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11979                 return -EINVAL;
11980         }
11981         return 0;
11982 }
11983
11984 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11985                                   struct rte_dev_eeprom_info *info)
11986 {
11987         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11988         bool is_sfp = false;
11989         i40e_status status;
11990         uint8_t *data;
11991         uint32_t value = 0;
11992         uint32_t i;
11993
11994         if (!info || !info->length || !info->data)
11995                 return -EINVAL;
11996
11997         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11998                 is_sfp = true;
11999
12000         data = info->data;
12001         for (i = 0; i < info->length; i++) {
12002                 u32 offset = i + info->offset;
12003                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12004
12005                 /* Check if we need to access the other memory page */
12006                 if (is_sfp) {
12007                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12008                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12009                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12010                         }
12011                 } else {
12012                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12013                                 /* Compute memory page number and offset. */
12014                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12015                                 addr++;
12016                         }
12017                 }
12018                 status = i40e_aq_get_phy_register(hw,
12019                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12020                                 addr, offset, 1, &value, NULL);
12021                 if (status)
12022                         return -EIO;
12023                 data[i] = (uint8_t)value;
12024         }
12025         return 0;
12026 }
12027
12028 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12029                                      struct rte_ether_addr *mac_addr)
12030 {
12031         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12032         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12033         struct i40e_vsi *vsi = pf->main_vsi;
12034         struct i40e_mac_filter_info mac_filter;
12035         struct i40e_mac_filter *f;
12036         int ret;
12037
12038         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12039                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12040                 return -EINVAL;
12041         }
12042
12043         TAILQ_FOREACH(f, &vsi->mac_list, next) {
12044                 if (rte_is_same_ether_addr(&pf->dev_addr,
12045                                                 &f->mac_info.mac_addr))
12046                         break;
12047         }
12048
12049         if (f == NULL) {
12050                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12051                 return -EIO;
12052         }
12053
12054         mac_filter = f->mac_info;
12055         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12056         if (ret != I40E_SUCCESS) {
12057                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12058                 return -EIO;
12059         }
12060         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12061         ret = i40e_vsi_add_mac(vsi, &mac_filter);
12062         if (ret != I40E_SUCCESS) {
12063                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12064                 return -EIO;
12065         }
12066         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12067
12068         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12069                                         mac_addr->addr_bytes, NULL);
12070         if (ret != I40E_SUCCESS) {
12071                 PMD_DRV_LOG(ERR, "Failed to change mac");
12072                 return -EIO;
12073         }
12074
12075         return 0;
12076 }
12077
12078 static int
12079 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12080 {
12081         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12082         struct rte_eth_dev_data *dev_data = pf->dev_data;
12083         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12084         int ret = 0;
12085
12086         /* check if mtu is within the allowed range */
12087         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12088                 return -EINVAL;
12089
12090         /* mtu setting is forbidden if port is start */
12091         if (dev_data->dev_started) {
12092                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12093                             dev_data->port_id);
12094                 return -EBUSY;
12095         }
12096
12097         if (frame_size > RTE_ETHER_MAX_LEN)
12098                 dev_data->dev_conf.rxmode.offloads |=
12099                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12100         else
12101                 dev_data->dev_conf.rxmode.offloads &=
12102                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12103
12104         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12105
12106         return ret;
12107 }
12108
12109 /* Restore ethertype filter */
12110 static void
12111 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12112 {
12113         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12114         struct i40e_ethertype_filter_list
12115                 *ethertype_list = &pf->ethertype.ethertype_list;
12116         struct i40e_ethertype_filter *f;
12117         struct i40e_control_filter_stats stats;
12118         uint16_t flags;
12119
12120         TAILQ_FOREACH(f, ethertype_list, rules) {
12121                 flags = 0;
12122                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12123                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12124                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12125                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12126                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12127
12128                 memset(&stats, 0, sizeof(stats));
12129                 i40e_aq_add_rem_control_packet_filter(hw,
12130                                             f->input.mac_addr.addr_bytes,
12131                                             f->input.ether_type,
12132                                             flags, pf->main_vsi->seid,
12133                                             f->queue, 1, &stats, NULL);
12134         }
12135         PMD_DRV_LOG(INFO, "Ethertype filter:"
12136                     " mac_etype_used = %u, etype_used = %u,"
12137                     " mac_etype_free = %u, etype_free = %u",
12138                     stats.mac_etype_used, stats.etype_used,
12139                     stats.mac_etype_free, stats.etype_free);
12140 }
12141
12142 /* Restore tunnel filter */
12143 static void
12144 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12145 {
12146         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12147         struct i40e_vsi *vsi;
12148         struct i40e_pf_vf *vf;
12149         struct i40e_tunnel_filter_list
12150                 *tunnel_list = &pf->tunnel.tunnel_list;
12151         struct i40e_tunnel_filter *f;
12152         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12153         bool big_buffer = 0;
12154
12155         TAILQ_FOREACH(f, tunnel_list, rules) {
12156                 if (!f->is_to_vf)
12157                         vsi = pf->main_vsi;
12158                 else {
12159                         vf = &pf->vfs[f->vf_id];
12160                         vsi = vf->vsi;
12161                 }
12162                 memset(&cld_filter, 0, sizeof(cld_filter));
12163                 rte_ether_addr_copy((struct rte_ether_addr *)
12164                                 &f->input.outer_mac,
12165                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12166                 rte_ether_addr_copy((struct rte_ether_addr *)
12167                                 &f->input.inner_mac,
12168                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12169                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12170                 cld_filter.element.flags = f->input.flags;
12171                 cld_filter.element.tenant_id = f->input.tenant_id;
12172                 cld_filter.element.queue_number = f->queue;
12173                 rte_memcpy(cld_filter.general_fields,
12174                            f->input.general_fields,
12175                            sizeof(f->input.general_fields));
12176
12177                 if (((f->input.flags &
12178                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12179                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12180                     ((f->input.flags &
12181                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12182                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12183                     ((f->input.flags &
12184                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12185                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12186                         big_buffer = 1;
12187
12188                 if (big_buffer)
12189                         i40e_aq_add_cloud_filters_bb(hw,
12190                                         vsi->seid, &cld_filter, 1);
12191                 else
12192                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12193                                                   &cld_filter.element, 1);
12194         }
12195 }
12196
12197 /* Restore rss filter */
12198 static inline void
12199 i40e_rss_filter_restore(struct i40e_pf *pf)
12200 {
12201         struct i40e_rte_flow_rss_conf *conf =
12202                                         &pf->rss_info;
12203         if (conf->conf.queue_num)
12204                 i40e_config_rss_filter(pf, conf, TRUE);
12205 }
12206
12207 static void
12208 i40e_filter_restore(struct i40e_pf *pf)
12209 {
12210         i40e_ethertype_filter_restore(pf);
12211         i40e_tunnel_filter_restore(pf);
12212         i40e_fdir_filter_restore(pf);
12213         i40e_rss_filter_restore(pf);
12214 }
12215
12216 bool
12217 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12218 {
12219         if (strcmp(dev->device->driver->name, drv->driver.name))
12220                 return false;
12221
12222         return true;
12223 }
12224
12225 bool
12226 is_i40e_supported(struct rte_eth_dev *dev)
12227 {
12228         return is_device_supported(dev, &rte_i40e_pmd);
12229 }
12230
12231 struct i40e_customized_pctype*
12232 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12233 {
12234         int i;
12235
12236         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12237                 if (pf->customized_pctype[i].index == index)
12238                         return &pf->customized_pctype[i];
12239         }
12240         return NULL;
12241 }
12242
12243 static int
12244 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12245                               uint32_t pkg_size, uint32_t proto_num,
12246                               struct rte_pmd_i40e_proto_info *proto,
12247                               enum rte_pmd_i40e_package_op op)
12248 {
12249         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12250         uint32_t pctype_num;
12251         struct rte_pmd_i40e_ptype_info *pctype;
12252         uint32_t buff_size;
12253         struct i40e_customized_pctype *new_pctype = NULL;
12254         uint8_t proto_id;
12255         uint8_t pctype_value;
12256         char name[64];
12257         uint32_t i, j, n;
12258         int ret;
12259
12260         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12261             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12262                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12263                 return -1;
12264         }
12265
12266         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12267                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12268                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12269         if (ret) {
12270                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12271                 return -1;
12272         }
12273         if (!pctype_num) {
12274                 PMD_DRV_LOG(INFO, "No new pctype added");
12275                 return -1;
12276         }
12277
12278         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12279         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12280         if (!pctype) {
12281                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12282                 return -1;
12283         }
12284         /* get information about new pctype list */
12285         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12286                                         (uint8_t *)pctype, buff_size,
12287                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12288         if (ret) {
12289                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12290                 rte_free(pctype);
12291                 return -1;
12292         }
12293
12294         /* Update customized pctype. */
12295         for (i = 0; i < pctype_num; i++) {
12296                 pctype_value = pctype[i].ptype_id;
12297                 memset(name, 0, sizeof(name));
12298                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12299                         proto_id = pctype[i].protocols[j];
12300                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12301                                 continue;
12302                         for (n = 0; n < proto_num; n++) {
12303                                 if (proto[n].proto_id != proto_id)
12304                                         continue;
12305                                 strlcat(name, proto[n].name, sizeof(name));
12306                                 strlcat(name, "_", sizeof(name));
12307                                 break;
12308                         }
12309                 }
12310                 name[strlen(name) - 1] = '\0';
12311                 if (!strcmp(name, "GTPC"))
12312                         new_pctype =
12313                                 i40e_find_customized_pctype(pf,
12314                                                       I40E_CUSTOMIZED_GTPC);
12315                 else if (!strcmp(name, "GTPU_IPV4"))
12316                         new_pctype =
12317                                 i40e_find_customized_pctype(pf,
12318                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12319                 else if (!strcmp(name, "GTPU_IPV6"))
12320                         new_pctype =
12321                                 i40e_find_customized_pctype(pf,
12322                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12323                 else if (!strcmp(name, "GTPU"))
12324                         new_pctype =
12325                                 i40e_find_customized_pctype(pf,
12326                                                       I40E_CUSTOMIZED_GTPU);
12327                 if (new_pctype) {
12328                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12329                                 new_pctype->pctype = pctype_value;
12330                                 new_pctype->valid = true;
12331                         } else {
12332                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12333                                 new_pctype->valid = false;
12334                         }
12335                 }
12336         }
12337
12338         rte_free(pctype);
12339         return 0;
12340 }
12341
12342 static int
12343 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12344                              uint32_t pkg_size, uint32_t proto_num,
12345                              struct rte_pmd_i40e_proto_info *proto,
12346                              enum rte_pmd_i40e_package_op op)
12347 {
12348         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12349         uint16_t port_id = dev->data->port_id;
12350         uint32_t ptype_num;
12351         struct rte_pmd_i40e_ptype_info *ptype;
12352         uint32_t buff_size;
12353         uint8_t proto_id;
12354         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12355         uint32_t i, j, n;
12356         bool in_tunnel;
12357         int ret;
12358
12359         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12360             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12361                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12362                 return -1;
12363         }
12364
12365         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12366                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12367                 return 0;
12368         }
12369
12370         /* get information about new ptype num */
12371         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12372                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12373                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12374         if (ret) {
12375                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12376                 return ret;
12377         }
12378         if (!ptype_num) {
12379                 PMD_DRV_LOG(INFO, "No new ptype added");
12380                 return -1;
12381         }
12382
12383         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12384         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12385         if (!ptype) {
12386                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12387                 return -1;
12388         }
12389
12390         /* get information about new ptype list */
12391         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12392                                         (uint8_t *)ptype, buff_size,
12393                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12394         if (ret) {
12395                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12396                 rte_free(ptype);
12397                 return ret;
12398         }
12399
12400         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12401         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12402         if (!ptype_mapping) {
12403                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12404                 rte_free(ptype);
12405                 return -1;
12406         }
12407
12408         /* Update ptype mapping table. */
12409         for (i = 0; i < ptype_num; i++) {
12410                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12411                 ptype_mapping[i].sw_ptype = 0;
12412                 in_tunnel = false;
12413                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12414                         proto_id = ptype[i].protocols[j];
12415                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12416                                 continue;
12417                         for (n = 0; n < proto_num; n++) {
12418                                 if (proto[n].proto_id != proto_id)
12419                                         continue;
12420                                 memset(name, 0, sizeof(name));
12421                                 strcpy(name, proto[n].name);
12422                                 if (!strncasecmp(name, "PPPOE", 5))
12423                                         ptype_mapping[i].sw_ptype |=
12424                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12425                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12426                                          !in_tunnel) {
12427                                         ptype_mapping[i].sw_ptype |=
12428                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12429                                         ptype_mapping[i].sw_ptype |=
12430                                                 RTE_PTYPE_L4_FRAG;
12431                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12432                                            in_tunnel) {
12433                                         ptype_mapping[i].sw_ptype |=
12434                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12435                                         ptype_mapping[i].sw_ptype |=
12436                                                 RTE_PTYPE_INNER_L4_FRAG;
12437                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12438                                         ptype_mapping[i].sw_ptype |=
12439                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12440                                         in_tunnel = true;
12441                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12442                                            !in_tunnel)
12443                                         ptype_mapping[i].sw_ptype |=
12444                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12445                                 else if (!strncasecmp(name, "IPV4", 4) &&
12446                                          in_tunnel)
12447                                         ptype_mapping[i].sw_ptype |=
12448                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12449                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12450                                          !in_tunnel) {
12451                                         ptype_mapping[i].sw_ptype |=
12452                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12453                                         ptype_mapping[i].sw_ptype |=
12454                                                 RTE_PTYPE_L4_FRAG;
12455                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12456                                            in_tunnel) {
12457                                         ptype_mapping[i].sw_ptype |=
12458                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12459                                         ptype_mapping[i].sw_ptype |=
12460                                                 RTE_PTYPE_INNER_L4_FRAG;
12461                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12462                                         ptype_mapping[i].sw_ptype |=
12463                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12464                                         in_tunnel = true;
12465                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12466                                            !in_tunnel)
12467                                         ptype_mapping[i].sw_ptype |=
12468                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12469                                 else if (!strncasecmp(name, "IPV6", 4) &&
12470                                          in_tunnel)
12471                                         ptype_mapping[i].sw_ptype |=
12472                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12473                                 else if (!strncasecmp(name, "UDP", 3) &&
12474                                          !in_tunnel)
12475                                         ptype_mapping[i].sw_ptype |=
12476                                                 RTE_PTYPE_L4_UDP;
12477                                 else if (!strncasecmp(name, "UDP", 3) &&
12478                                          in_tunnel)
12479                                         ptype_mapping[i].sw_ptype |=
12480                                                 RTE_PTYPE_INNER_L4_UDP;
12481                                 else if (!strncasecmp(name, "TCP", 3) &&
12482                                          !in_tunnel)
12483                                         ptype_mapping[i].sw_ptype |=
12484                                                 RTE_PTYPE_L4_TCP;
12485                                 else if (!strncasecmp(name, "TCP", 3) &&
12486                                          in_tunnel)
12487                                         ptype_mapping[i].sw_ptype |=
12488                                                 RTE_PTYPE_INNER_L4_TCP;
12489                                 else if (!strncasecmp(name, "SCTP", 4) &&
12490                                          !in_tunnel)
12491                                         ptype_mapping[i].sw_ptype |=
12492                                                 RTE_PTYPE_L4_SCTP;
12493                                 else if (!strncasecmp(name, "SCTP", 4) &&
12494                                          in_tunnel)
12495                                         ptype_mapping[i].sw_ptype |=
12496                                                 RTE_PTYPE_INNER_L4_SCTP;
12497                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12498                                           !strncasecmp(name, "ICMPV6", 6)) &&
12499                                          !in_tunnel)
12500                                         ptype_mapping[i].sw_ptype |=
12501                                                 RTE_PTYPE_L4_ICMP;
12502                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12503                                           !strncasecmp(name, "ICMPV6", 6)) &&
12504                                          in_tunnel)
12505                                         ptype_mapping[i].sw_ptype |=
12506                                                 RTE_PTYPE_INNER_L4_ICMP;
12507                                 else if (!strncasecmp(name, "GTPC", 4)) {
12508                                         ptype_mapping[i].sw_ptype |=
12509                                                 RTE_PTYPE_TUNNEL_GTPC;
12510                                         in_tunnel = true;
12511                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12512                                         ptype_mapping[i].sw_ptype |=
12513                                                 RTE_PTYPE_TUNNEL_GTPU;
12514                                         in_tunnel = true;
12515                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12516                                         ptype_mapping[i].sw_ptype |=
12517                                                 RTE_PTYPE_TUNNEL_GRENAT;
12518                                         in_tunnel = true;
12519                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12520                                            !strncasecmp(name, "L2TPV2", 6)) {
12521                                         ptype_mapping[i].sw_ptype |=
12522                                                 RTE_PTYPE_TUNNEL_L2TP;
12523                                         in_tunnel = true;
12524                                 }
12525
12526                                 break;
12527                         }
12528                 }
12529         }
12530
12531         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12532                                                 ptype_num, 0);
12533         if (ret)
12534                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12535
12536         rte_free(ptype_mapping);
12537         rte_free(ptype);
12538         return ret;
12539 }
12540
12541 void
12542 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12543                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12544 {
12545         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12546         uint32_t proto_num;
12547         struct rte_pmd_i40e_proto_info *proto;
12548         uint32_t buff_size;
12549         uint32_t i;
12550         int ret;
12551
12552         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12553             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12554                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12555                 return;
12556         }
12557
12558         /* get information about protocol number */
12559         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12560                                        (uint8_t *)&proto_num, sizeof(proto_num),
12561                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12562         if (ret) {
12563                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12564                 return;
12565         }
12566         if (!proto_num) {
12567                 PMD_DRV_LOG(INFO, "No new protocol added");
12568                 return;
12569         }
12570
12571         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12572         proto = rte_zmalloc("new_proto", buff_size, 0);
12573         if (!proto) {
12574                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12575                 return;
12576         }
12577
12578         /* get information about protocol list */
12579         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12580                                         (uint8_t *)proto, buff_size,
12581                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12582         if (ret) {
12583                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12584                 rte_free(proto);
12585                 return;
12586         }
12587
12588         /* Check if GTP is supported. */
12589         for (i = 0; i < proto_num; i++) {
12590                 if (!strncmp(proto[i].name, "GTP", 3)) {
12591                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12592                                 pf->gtp_support = true;
12593                         else
12594                                 pf->gtp_support = false;
12595                         break;
12596                 }
12597         }
12598
12599         /* Update customized pctype info */
12600         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12601                                             proto_num, proto, op);
12602         if (ret)
12603                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12604
12605         /* Update customized ptype info */
12606         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12607                                            proto_num, proto, op);
12608         if (ret)
12609                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12610
12611         rte_free(proto);
12612 }
12613
12614 /* Create a QinQ cloud filter
12615  *
12616  * The Fortville NIC has limited resources for tunnel filters,
12617  * so we can only reuse existing filters.
12618  *
12619  * In step 1 we define which Field Vector fields can be used for
12620  * filter types.
12621  * As we do not have the inner tag defined as a field,
12622  * we have to define it first, by reusing one of L1 entries.
12623  *
12624  * In step 2 we are replacing one of existing filter types with
12625  * a new one for QinQ.
12626  * As we reusing L1 and replacing L2, some of the default filter
12627  * types will disappear,which depends on L1 and L2 entries we reuse.
12628  *
12629  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12630  *
12631  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12632  *              later when we define the cloud filter.
12633  *      a.      Valid_flags.replace_cloud = 0
12634  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12635  *      c.      New_filter = 0x10
12636  *      d.      TR bit = 0xff (optional, not used here)
12637  *      e.      Buffer – 2 entries:
12638  *              i.      Byte 0 = 8 (outer vlan FV index).
12639  *                      Byte 1 = 0 (rsv)
12640  *                      Byte 2-3 = 0x0fff
12641  *              ii.     Byte 0 = 37 (inner vlan FV index).
12642  *                      Byte 1 =0 (rsv)
12643  *                      Byte 2-3 = 0x0fff
12644  *
12645  * Step 2:
12646  * 2.   Create cloud filter using two L1 filters entries: stag and
12647  *              new filter(outer vlan+ inner vlan)
12648  *      a.      Valid_flags.replace_cloud = 1
12649  *      b.      Old_filter = 1 (instead of outer IP)
12650  *      c.      New_filter = 0x10
12651  *      d.      Buffer – 2 entries:
12652  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12653  *                      Byte 1-3 = 0 (rsv)
12654  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12655  *                      Byte 9-11 = 0 (rsv)
12656  */
12657 static int
12658 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12659 {
12660         int ret = -ENOTSUP;
12661         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12662         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12663         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12664         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12665
12666         if (pf->support_multi_driver) {
12667                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12668                 return ret;
12669         }
12670
12671         /* Init */
12672         memset(&filter_replace, 0,
12673                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12674         memset(&filter_replace_buf, 0,
12675                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12676
12677         /* create L1 filter */
12678         filter_replace.old_filter_type =
12679                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12680         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12681         filter_replace.tr_bit = 0;
12682
12683         /* Prepare the buffer, 2 entries */
12684         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12685         filter_replace_buf.data[0] |=
12686                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12687         /* Field Vector 12b mask */
12688         filter_replace_buf.data[2] = 0xff;
12689         filter_replace_buf.data[3] = 0x0f;
12690         filter_replace_buf.data[4] =
12691                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12692         filter_replace_buf.data[4] |=
12693                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12694         /* Field Vector 12b mask */
12695         filter_replace_buf.data[6] = 0xff;
12696         filter_replace_buf.data[7] = 0x0f;
12697         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12698                         &filter_replace_buf);
12699         if (ret != I40E_SUCCESS)
12700                 return ret;
12701
12702         if (filter_replace.old_filter_type !=
12703             filter_replace.new_filter_type)
12704                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12705                             " original: 0x%x, new: 0x%x",
12706                             dev->device->name,
12707                             filter_replace.old_filter_type,
12708                             filter_replace.new_filter_type);
12709
12710         /* Apply the second L2 cloud filter */
12711         memset(&filter_replace, 0,
12712                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12713         memset(&filter_replace_buf, 0,
12714                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12715
12716         /* create L2 filter, input for L2 filter will be L1 filter  */
12717         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12718         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12719         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12720
12721         /* Prepare the buffer, 2 entries */
12722         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12723         filter_replace_buf.data[0] |=
12724                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12725         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12726         filter_replace_buf.data[4] |=
12727                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12728         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12729                         &filter_replace_buf);
12730         if (!ret && (filter_replace.old_filter_type !=
12731                      filter_replace.new_filter_type))
12732                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12733                             " original: 0x%x, new: 0x%x",
12734                             dev->device->name,
12735                             filter_replace.old_filter_type,
12736                             filter_replace.new_filter_type);
12737
12738         return ret;
12739 }
12740
12741 int
12742 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12743                    const struct rte_flow_action_rss *in)
12744 {
12745         if (in->key_len > RTE_DIM(out->key) ||
12746             in->queue_num > RTE_DIM(out->queue))
12747                 return -EINVAL;
12748         if (!in->key && in->key_len)
12749                 return -EINVAL;
12750         out->conf = (struct rte_flow_action_rss){
12751                 .func = in->func,
12752                 .level = in->level,
12753                 .types = in->types,
12754                 .key_len = in->key_len,
12755                 .queue_num = in->queue_num,
12756                 .queue = memcpy(out->queue, in->queue,
12757                                 sizeof(*in->queue) * in->queue_num),
12758         };
12759         if (in->key)
12760                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12761         return 0;
12762 }
12763
12764 int
12765 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12766                      const struct rte_flow_action_rss *with)
12767 {
12768         return (comp->func == with->func &&
12769                 comp->level == with->level &&
12770                 comp->types == with->types &&
12771                 comp->key_len == with->key_len &&
12772                 comp->queue_num == with->queue_num &&
12773                 !memcmp(comp->key, with->key, with->key_len) &&
12774                 !memcmp(comp->queue, with->queue,
12775                         sizeof(*with->queue) * with->queue_num));
12776 }
12777
12778 int
12779 i40e_config_rss_filter(struct i40e_pf *pf,
12780                 struct i40e_rte_flow_rss_conf *conf, bool add)
12781 {
12782         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12783         uint32_t i, lut = 0;
12784         uint16_t j, num;
12785         struct rte_eth_rss_conf rss_conf = {
12786                 .rss_key = conf->conf.key_len ?
12787                         (void *)(uintptr_t)conf->conf.key : NULL,
12788                 .rss_key_len = conf->conf.key_len,
12789                 .rss_hf = conf->conf.types,
12790         };
12791         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12792
12793         if (!add) {
12794                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12795                         i40e_pf_disable_rss(pf);
12796                         memset(rss_info, 0,
12797                                 sizeof(struct i40e_rte_flow_rss_conf));
12798                         return 0;
12799                 }
12800                 return -EINVAL;
12801         }
12802
12803         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12804          * It's necessary to calculate the actual PF queues that are configured.
12805          */
12806         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12807                 num = i40e_pf_calc_configured_queues_num(pf);
12808         else
12809                 num = pf->dev_data->nb_rx_queues;
12810
12811         num = RTE_MIN(num, conf->conf.queue_num);
12812         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12813                         num);
12814
12815         if (num == 0) {
12816                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12817                 return -ENOTSUP;
12818         }
12819
12820         /* Fill in redirection table */
12821         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12822                 if (j == num)
12823                         j = 0;
12824                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12825                         hw->func_caps.rss_table_entry_width) - 1));
12826                 if ((i & 3) == 3)
12827                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12828         }
12829
12830         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12831                 i40e_pf_disable_rss(pf);
12832                 return 0;
12833         }
12834         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12835                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12836                 /* Random default keys */
12837                 static uint32_t rss_key_default[] = {0x6b793944,
12838                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12839                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12840                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12841
12842                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12843                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12844                                                         sizeof(uint32_t);
12845                 PMD_DRV_LOG(INFO,
12846                         "No valid RSS key config for i40e, using default\n");
12847         }
12848
12849         i40e_hw_rss_hash_set(pf, &rss_conf);
12850
12851         if (i40e_rss_conf_init(rss_info, &conf->conf))
12852                 return -EINVAL;
12853
12854         return 0;
12855 }
12856
12857 RTE_INIT(i40e_init_log)
12858 {
12859         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12860         if (i40e_logtype_init >= 0)
12861                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12862         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12863         if (i40e_logtype_driver >= 0)
12864                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12865 }
12866
12867 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12868                               ETH_I40E_FLOATING_VEB_ARG "=1"
12869                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12870                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12871                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12872                               ETH_I40E_USE_LATEST_VEC "=0|1");