drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_adminq_cmd.h"
  57 #include "base/i40e_type.h"
  58 #include "base/i40e_register.h"
  59 #include "i40e_ethdev.h"
  60 #include "i40e_rxtx.h"
  61 #include "i40e_pf.h"
  62
  63 /* Maximun number of MAC addresses */
  64 #define I40E_NUM_MACADDR_MAX       64
  65 #define I40E_CLEAR_PXE_WAIT_MS     200
  66
  67 /* Maximun number of capability elements */
  68 #define I40E_MAX_CAP_ELE_NUM       128
  69
  70 /* Wait count and inteval */
  71 #define I40E_CHK_Q_ENA_COUNT       1000
  72 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  73
  74 /* Maximun number of VSI */
  75 #define I40E_MAX_NUM_VSIS          (384UL)
  76
  77 /* Default queue interrupt throttling time in microseconds */
  78 #define I40E_ITR_INDEX_DEFAULT          0
  79 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  80 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  81
  82 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  83
  84 /* Mask of PF interrupt causes */
  85 #define I40E_PFINT_ICR0_ENA_MASK ( \
  86                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  87                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  90                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
  92                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  95                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  96
  97 #define I40E_FLOW_TYPES ( \
  98         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 103         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 107         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 108         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 109
 110 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 111 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 112 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 113 #define I40E_PRTTSYN_TSYNENA  0x80000000
 114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 115
 116 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 117 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 118 static int i40e_dev_configure(struct rte_eth_dev *dev);
 119 static int i40e_dev_start(struct rte_eth_dev *dev);
 120 static void i40e_dev_stop(struct rte_eth_dev *dev);
 121 static void i40e_dev_close(struct rte_eth_dev *dev);
 122 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 123 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 124 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 125 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 126 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 127 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 128 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 129                                struct rte_eth_stats *stats);
 130 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 131 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 132                                             uint16_t queue_id,
 133                                             uint8_t stat_idx,
 134                                             uint8_t is_rx);
 135 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 136                               struct rte_eth_dev_info *dev_info);
 137 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 138                                 uint16_t vlan_id,
 139                                 int on);
 140 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 141 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 142 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 143                                       uint16_t queue,
 144                                       int on);
 145 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 146 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 147 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 148 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 149                               struct rte_eth_fc_conf *fc_conf);
 150 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 151                                        struct rte_eth_pfc_conf *pfc_conf);
 152 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 153                           struct ether_addr *mac_addr,
 154                           uint32_t index,
 155                           uint32_t pool);
 156 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 157 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 158                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 159                                     uint16_t reta_size);
 160 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 161                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 162                                    uint16_t reta_size);
 163
 164 static int i40e_get_cap(struct i40e_hw *hw);
 165 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 166 static int i40e_pf_setup(struct i40e_pf *pf);
 167 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 168 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 169 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 170                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 171 static void i40e_stat_update_48(struct i40e_hw *hw,
 172                                uint32_t hireg,
 173                                uint32_t loreg,
 174                                bool offset_loaded,
 175                                uint64_t *offset,
 176                                uint64_t *stat);
 177 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 178 static void i40e_dev_interrupt_handler(
 179                 __rte_unused struct rte_intr_handle *handle, void *param);
 180 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 181                                 uint32_t base, uint32_t num);
 182 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 183 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 184                         uint32_t base);
 185 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 186                         uint16_t num);
 187 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 188 static int i40e_veb_release(struct i40e_veb *veb);
 189 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 190                                                 struct i40e_vsi *vsi);
 191 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 192 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 193 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 194                                              struct i40e_macvlan_filter *mv_f,
 195                                              int num,
 196                                              struct ether_addr *addr);
 197 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 198                                              struct i40e_macvlan_filter *mv_f,
 199                                              int num,
 200                                              uint16_t vlan);
 201 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 202 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 203                                     struct rte_eth_rss_conf *rss_conf);
 204 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 205                                       struct rte_eth_rss_conf *rss_conf);
 206 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 207                                 struct rte_eth_udp_tunnel *udp_tunnel);
 208 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 209                                 struct rte_eth_udp_tunnel *udp_tunnel);
 210 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 211                         struct rte_eth_ethertype_filter *filter,
 212                         bool add);
 213 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 214                                 enum rte_filter_op filter_op,
 215                                 void *arg);
 216 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 217                                 enum rte_filter_type filter_type,
 218                                 enum rte_filter_op filter_op,
 219                                 void *arg);
 220 static void i40e_configure_registers(struct i40e_hw *hw);
 221 static void i40e_hw_init(struct i40e_hw *hw);
 222 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 223 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 224                         struct rte_eth_mirror_conf *mirror_conf,
 225                         uint8_t sw_id, uint8_t on);
 226 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 227
 228 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 229 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 230 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 231                                            struct timespec *timestamp,
 232                                            uint32_t flags);
 233 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 234                                            struct timespec *timestamp);
 235
 236 static const struct rte_pci_id pci_id_i40e_map[] = {
 237 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 238 #include "rte_pci_dev_ids.h"
 239 { .vendor_id = 0, /* sentinel */ },
 240 };
 241
 242 static const struct eth_dev_ops i40e_eth_dev_ops = {
 243         .dev_configure                = i40e_dev_configure,
 244         .dev_start                    = i40e_dev_start,
 245         .dev_stop                     = i40e_dev_stop,
 246         .dev_close                    = i40e_dev_close,
 247         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 248         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 249         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 250         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 251         .dev_set_link_up              = i40e_dev_set_link_up,
 252         .dev_set_link_down            = i40e_dev_set_link_down,
 253         .link_update                  = i40e_dev_link_update,
 254         .stats_get                    = i40e_dev_stats_get,
 255         .stats_reset                  = i40e_dev_stats_reset,
 256         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 257         .dev_infos_get                = i40e_dev_info_get,
 258         .vlan_filter_set              = i40e_vlan_filter_set,
 259         .vlan_tpid_set                = i40e_vlan_tpid_set,
 260         .vlan_offload_set             = i40e_vlan_offload_set,
 261         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 262         .vlan_pvid_set                = i40e_vlan_pvid_set,
 263         .rx_queue_start               = i40e_dev_rx_queue_start,
 264         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 265         .tx_queue_start               = i40e_dev_tx_queue_start,
 266         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 267         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 268         .rx_queue_release             = i40e_dev_rx_queue_release,
 269         .rx_queue_count               = i40e_dev_rx_queue_count,
 270         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 271         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 272         .tx_queue_release             = i40e_dev_tx_queue_release,
 273         .dev_led_on                   = i40e_dev_led_on,
 274         .dev_led_off                  = i40e_dev_led_off,
 275         .flow_ctrl_set                = i40e_flow_ctrl_set,
 276         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 277         .mac_addr_add                 = i40e_macaddr_add,
 278         .mac_addr_remove              = i40e_macaddr_remove,
 279         .reta_update                  = i40e_dev_rss_reta_update,
 280         .reta_query                   = i40e_dev_rss_reta_query,
 281         .rss_hash_update              = i40e_dev_rss_hash_update,
 282         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 283         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 284         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 285         .filter_ctrl                  = i40e_dev_filter_ctrl,
 286         .mirror_rule_set              = i40e_mirror_rule_set,
 287         .mirror_rule_reset            = i40e_mirror_rule_reset,
 288         .timesync_enable              = i40e_timesync_enable,
 289         .timesync_disable             = i40e_timesync_disable,
 290         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 291         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 292 };
 293
 294 static struct eth_driver rte_i40e_pmd = {
 295         .pci_drv = {
 296                 .name = "rte_i40e_pmd",
 297                 .id_table = pci_id_i40e_map,
 298                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 299                         RTE_PCI_DRV_DETACHABLE,
 300         },
 301         .eth_dev_init = eth_i40e_dev_init,
 302         .eth_dev_uninit = eth_i40e_dev_uninit,
 303         .dev_private_size = sizeof(struct i40e_adapter),
 304 };
 305
 306 static inline int
 307 i40e_align_floor(int n)
 308 {
 309         if (n == 0)
 310                 return 0;
 311         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 312 }
 313
 314 static inline int
 315 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 316                                      struct rte_eth_link *link)
 317 {
 318         struct rte_eth_link *dst = link;
 319         struct rte_eth_link *src = &(dev->data->dev_link);
 320
 321         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 322                                         *(uint64_t *)src) == 0)
 323                 return -1;
 324
 325         return 0;
 326 }
 327
 328 static inline int
 329 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 330                                       struct rte_eth_link *link)
 331 {
 332         struct rte_eth_link *dst = &(dev->data->dev_link);
 333         struct rte_eth_link *src = link;
 334
 335         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 336                                         *(uint64_t *)src) == 0)
 337                 return -1;
 338
 339         return 0;
 340 }
 341
 342 /*
 343  * Driver initialization routine.
 344  * Invoked once at EAL init time.
 345  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 346  */
 347 static int
 348 rte_i40e_pmd_init(const char *name __rte_unused,
 349                   const char *params __rte_unused)
 350 {
 351         PMD_INIT_FUNC_TRACE();
 352         rte_eth_driver_register(&rte_i40e_pmd);
 353
 354         return 0;
 355 }
 356
 357 static struct rte_driver rte_i40e_driver = {
 358         .type = PMD_PDEV,
 359         .init = rte_i40e_pmd_init,
 360 };
 361
 362 PMD_REGISTER_DRIVER(rte_i40e_driver);
 363
 364 /*
 365  * Initialize registers for flexible payload, which should be set by NVM.
 366  * This should be removed from code once it is fixed in NVM.
 367  */
 368 #ifndef I40E_GLQF_ORT
 369 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 370 #endif
 371 #ifndef I40E_GLQF_PIT
 372 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 373 #endif
 374
 375 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 376 {
 377         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 378         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 379         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 380         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 381         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 382         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 383         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 384         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 385         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 386         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 387
 388         /* GLQF_PIT Registers */
 389         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 390         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 391 }
 392
 393 static int
 394 eth_i40e_dev_init(struct rte_eth_dev *dev)
 395 {
 396         struct rte_pci_device *pci_dev;
 397         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 398         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 399         struct i40e_vsi *vsi;
 400         int ret;
 401         uint32_t len;
 402         uint8_t aq_fail = 0;
 403
 404         PMD_INIT_FUNC_TRACE();
 405
 406         dev->dev_ops = &i40e_eth_dev_ops;
 407         dev->rx_pkt_burst = i40e_recv_pkts;
 408         dev->tx_pkt_burst = i40e_xmit_pkts;
 409
 410         /* for secondary processes, we don't initialise any further as primary
 411          * has already done this work. Only check we don't need a different
 412          * RX function */
 413         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 414                 if (dev->data->scattered_rx)
 415                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 416                 return 0;
 417         }
 418         pci_dev = dev->pci_dev;
 419         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 420         pf->adapter->eth_dev = dev;
 421         pf->dev_data = dev->data;
 422
 423         hw->back = I40E_PF_TO_ADAPTER(pf);
 424         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 425         if (!hw->hw_addr) {
 426                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 427                              "as address is NULL");
 428                 return -ENODEV;
 429         }
 430
 431         hw->vendor_id = pci_dev->id.vendor_id;
 432         hw->device_id = pci_dev->id.device_id;
 433         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 434         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 435         hw->bus.device = pci_dev->addr.devid;
 436         hw->bus.func = pci_dev->addr.function;
 437         hw->adapter_stopped = 0;
 438
 439         /* Make sure all is clean before doing PF reset */
 440         i40e_clear_hw(hw);
 441
 442         /* Initialize the hardware */
 443         i40e_hw_init(hw);
 444
 445         /* Reset here to make sure all is clean for each PF */
 446         ret = i40e_pf_reset(hw);
 447         if (ret) {
 448                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 449                 return ret;
 450         }
 451
 452         /* Initialize the shared code (base driver) */
 453         ret = i40e_init_shared_code(hw);
 454         if (ret) {
 455                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 456                 return ret;
 457         }
 458
 459         /*
 460          * To work around the NVM issue,initialize registers
 461          * for flexible payload by software.
 462          * It should be removed once issues are fixed in NVM.
 463          */
 464         i40e_flex_payload_reg_init(hw);
 465
 466         /* Initialize the parameters for adminq */
 467         i40e_init_adminq_parameter(hw);
 468         ret = i40e_init_adminq(hw);
 469         if (ret != I40E_SUCCESS) {
 470                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 471                 return -EIO;
 472         }
 473         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 474                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 475                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 476                      ((hw->nvm.version >> 12) & 0xf),
 477                      ((hw->nvm.version >> 4) & 0xff),
 478                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 479
 480         /* Disable LLDP */
 481         ret = i40e_aq_stop_lldp(hw, true, NULL);
 482         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 483                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 484
 485         /* Clear PXE mode */
 486         i40e_clear_pxe_mode(hw);
 487
 488         /*
 489          * On X710, performance number is far from the expectation on recent
 490          * firmware versions. The fix for this issue may not be integrated in
 491          * the following firmware version. So the workaround in software driver
 492          * is needed. It needs to modify the initial values of 3 internal only
 493          * registers. Note that the workaround can be removed when it is fixed
 494          * in firmware in the future.
 495          */
 496         i40e_configure_registers(hw);
 497
 498         /* Get hw capabilities */
 499         ret = i40e_get_cap(hw);
 500         if (ret != I40E_SUCCESS) {
 501                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 502                 goto err_get_capabilities;
 503         }
 504
 505         /* Initialize parameters for PF */
 506         ret = i40e_pf_parameter_init(dev);
 507         if (ret != 0) {
 508                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 509                 goto err_parameter_init;
 510         }
 511
 512         /* Initialize the queue management */
 513         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 514         if (ret < 0) {
 515                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 516                 goto err_qp_pool_init;
 517         }
 518         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 519                                 hw->func_caps.num_msix_vectors - 1);
 520         if (ret < 0) {
 521                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 522                 goto err_msix_pool_init;
 523         }
 524
 525         /* Initialize lan hmc */
 526         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 527                                 hw->func_caps.num_rx_qp, 0, 0);
 528         if (ret != I40E_SUCCESS) {
 529                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 530                 goto err_init_lan_hmc;
 531         }
 532
 533         /* Configure lan hmc */
 534         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 535         if (ret != I40E_SUCCESS) {
 536                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 537                 goto err_configure_lan_hmc;
 538         }
 539
 540         /* Get and check the mac address */
 541         i40e_get_mac_addr(hw, hw->mac.addr);
 542         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 543                 PMD_INIT_LOG(ERR, "mac address is not valid");
 544                 ret = -EIO;
 545                 goto err_get_mac_addr;
 546         }
 547         /* Copy the permanent MAC address */
 548         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 549                         (struct ether_addr *) hw->mac.perm_addr);
 550
 551         /* Disable flow control */
 552         hw->fc.requested_mode = I40E_FC_NONE;
 553         i40e_set_fc(hw, &aq_fail, TRUE);
 554
 555         /* PF setup, which includes VSI setup */
 556         ret = i40e_pf_setup(pf);
 557         if (ret) {
 558                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 559                 goto err_setup_pf_switch;
 560         }
 561
 562         vsi = pf->main_vsi;
 563
 564         /* Disable double vlan by default */
 565         i40e_vsi_config_double_vlan(vsi, FALSE);
 566
 567         if (!vsi->max_macaddrs)
 568                 len = ETHER_ADDR_LEN;
 569         else
 570                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 571
 572         /* Should be after VSI initialized */
 573         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 574         if (!dev->data->mac_addrs) {
 575                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 576                                         "for storing mac address");
 577                 goto err_mac_alloc;
 578         }
 579         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 580                                         &dev->data->mac_addrs[0]);
 581
 582         /* initialize pf host driver to setup SRIOV resource if applicable */
 583         i40e_pf_host_init(dev);
 584
 585         /* register callback func to eal lib */
 586         rte_intr_callback_register(&(pci_dev->intr_handle),
 587                 i40e_dev_interrupt_handler, (void *)dev);
 588
 589         /* configure and enable device interrupt */
 590         i40e_pf_config_irq0(hw);
 591         i40e_pf_enable_irq0(hw);
 592
 593         /* enable uio intr after callback register */
 594         rte_intr_enable(&(pci_dev->intr_handle));
 595
 596         /* initialize mirror rule list */
 597         TAILQ_INIT(&pf->mirror_list);
 598
 599         return 0;
 600
 601 err_mac_alloc:
 602         i40e_vsi_release(pf->main_vsi);
 603 err_setup_pf_switch:
 604 err_get_mac_addr:
 605 err_configure_lan_hmc:
 606         (void)i40e_shutdown_lan_hmc(hw);
 607 err_init_lan_hmc:
 608         i40e_res_pool_destroy(&pf->msix_pool);
 609 err_msix_pool_init:
 610         i40e_res_pool_destroy(&pf->qp_pool);
 611 err_qp_pool_init:
 612 err_parameter_init:
 613 err_get_capabilities:
 614         (void)i40e_shutdown_adminq(hw);
 615
 616         return ret;
 617 }
 618
 619 static int
 620 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 621 {
 622         struct rte_pci_device *pci_dev;
 623         struct i40e_hw *hw;
 624         struct i40e_filter_control_settings settings;
 625         int ret;
 626         uint8_t aq_fail = 0;
 627
 628         PMD_INIT_FUNC_TRACE();
 629
 630         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 631                 return 0;
 632
 633         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 634         pci_dev = dev->pci_dev;
 635
 636         if (hw->adapter_stopped == 0)
 637                 i40e_dev_close(dev);
 638
 639         dev->dev_ops = NULL;
 640         dev->rx_pkt_burst = NULL;
 641         dev->tx_pkt_burst = NULL;
 642
 643         /* Disable LLDP */
 644         ret = i40e_aq_stop_lldp(hw, true, NULL);
 645         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 646                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 647
 648         /* Clear PXE mode */
 649         i40e_clear_pxe_mode(hw);
 650
 651         /* Unconfigure filter control */
 652         memset(&settings, 0, sizeof(settings));
 653         ret = i40e_set_filter_control(hw, &settings);
 654         if (ret)
 655                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 656                                         ret);
 657
 658         /* Disable flow control */
 659         hw->fc.requested_mode = I40E_FC_NONE;
 660         i40e_set_fc(hw, &aq_fail, TRUE);
 661
 662         /* uninitialize pf host driver */
 663         i40e_pf_host_uninit(dev);
 664
 665         rte_free(dev->data->mac_addrs);
 666         dev->data->mac_addrs = NULL;
 667
 668         /* disable uio intr before callback unregister */
 669         rte_intr_disable(&(pci_dev->intr_handle));
 670
 671         /* register callback func to eal lib */
 672         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 673                 i40e_dev_interrupt_handler, (void *)dev);
 674
 675         return 0;
 676 }
 677
 678 static int
 679 i40e_dev_configure(struct rte_eth_dev *dev)
 680 {
 681         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 682         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 683         int ret;
 684
 685         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 686                 ret = i40e_fdir_setup(pf);
 687                 if (ret != I40E_SUCCESS) {
 688                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 689                         return -ENOTSUP;
 690                 }
 691                 ret = i40e_fdir_configure(dev);
 692                 if (ret < 0) {
 693                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 694                         goto err;
 695                 }
 696         } else
 697                 i40e_fdir_teardown(pf);
 698
 699         ret = i40e_dev_init_vlan(dev);
 700         if (ret < 0)
 701                 goto err;
 702
 703         /* VMDQ setup.
 704          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 705          *  RSS setting have different requirements.
 706          *  General PMD driver call sequence are NIC init, configure,
 707          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 708          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 709          *  applicable. So, VMDQ setting has to be done before
 710          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 711          *  For RSS setting, it will try to calculate actual configured RX queue
 712          *  number, which will be available after rx_queue_setup(). dev_start()
 713          *  function is good to place RSS setup.
 714          */
 715         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 716                 ret = i40e_vmdq_setup(dev);
 717                 if (ret)
 718                         goto err;
 719         }
 720         return 0;
 721 err:
 722         i40e_fdir_teardown(pf);
 723         return ret;
 724 }
 725
 726 void
 727 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 728 {
 729         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 730         uint16_t msix_vect = vsi->msix_intr;
 731         uint16_t i;
 732
 733         for (i = 0; i < vsi->nb_qps; i++) {
 734                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 735                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 736                 rte_wmb();
 737         }
 738
 739         if (vsi->type != I40E_VSI_SRIOV) {
 740                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 741                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 742                                 msix_vect - 1), 0);
 743         } else {
 744                 uint32_t reg;
 745                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 746                         vsi->user_param + (msix_vect - 1);
 747
 748                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 749         }
 750         I40E_WRITE_FLUSH(hw);
 751 }
 752
 753 static inline uint16_t
 754 i40e_calc_itr_interval(int16_t interval)
 755 {
 756         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 757                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 758
 759         /* Convert to hardware count, as writing each 1 represents 2 us */
 760         return (interval/2);
 761 }
 762
 763 void
 764 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 765 {
 766         uint32_t val;
 767         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 768         uint16_t msix_vect = vsi->msix_intr;
 769         int i;
 770
 771         for (i = 0; i < vsi->nb_qps; i++)
 772                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 773
 774         /* Bind all RX queues to allocated MSIX interrupt */
 775         for (i = 0; i < vsi->nb_qps; i++) {
 776                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 777                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 778                         ((vsi->base_queue + i + 1) <<
 779                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 780                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 781                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 782
 783                 if (i == vsi->nb_qps - 1)
 784                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 785                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 786         }
 787
 788         /* Write first RX queue to Link list register as the head element */
 789         if (vsi->type != I40E_VSI_SRIOV) {
 790                 uint16_t interval =
 791                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 792
 793                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 794                                                 (vsi->base_queue <<
 795                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 796                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 797
 798                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 799                                                 msix_vect - 1), interval);
 800
 801 #ifndef I40E_GLINT_CTL
 802 #define I40E_GLINT_CTL                     0x0003F800
 803 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 804 #endif
 805                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 806                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 807                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 808         } else {
 809                 uint32_t reg;
 810
 811                 /* num_msix_vectors_vf needs to minus irq0 */
 812                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 813                         vsi->user_param + (msix_vect - 1);
 814
 815                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 816                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 817                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 818         }
 819
 820         I40E_WRITE_FLUSH(hw);
 821 }
 822
 823 static void
 824 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 825 {
 826         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 827         uint16_t interval = i40e_calc_itr_interval(\
 828                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 829
 830         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 831                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 832                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 833                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 834                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 835 }
 836
 837 static void
 838 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 839 {
 840         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 841
 842         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 843 }
 844
 845 static inline uint8_t
 846 i40e_parse_link_speed(uint16_t eth_link_speed)
 847 {
 848         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 849
 850         switch (eth_link_speed) {
 851         case ETH_LINK_SPEED_40G:
 852                 link_speed = I40E_LINK_SPEED_40GB;
 853                 break;
 854         case ETH_LINK_SPEED_20G:
 855                 link_speed = I40E_LINK_SPEED_20GB;
 856                 break;
 857         case ETH_LINK_SPEED_10G:
 858                 link_speed = I40E_LINK_SPEED_10GB;
 859                 break;
 860         case ETH_LINK_SPEED_1000:
 861                 link_speed = I40E_LINK_SPEED_1GB;
 862                 break;
 863         case ETH_LINK_SPEED_100:
 864                 link_speed = I40E_LINK_SPEED_100MB;
 865                 break;
 866         }
 867
 868         return link_speed;
 869 }
 870
 871 static int
 872 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 873 {
 874         enum i40e_status_code status;
 875         struct i40e_aq_get_phy_abilities_resp phy_ab;
 876         struct i40e_aq_set_phy_config phy_conf;
 877         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 878                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 879                         I40E_AQ_PHY_FLAG_LOW_POWER;
 880         const uint8_t advt = I40E_LINK_SPEED_40GB |
 881                         I40E_LINK_SPEED_10GB |
 882                         I40E_LINK_SPEED_1GB |
 883                         I40E_LINK_SPEED_100MB;
 884         int ret = -ENOTSUP;
 885
 886         /* Skip it on 40G interfaces, as a workaround for the link issue */
 887         if (i40e_is_40G_device(hw->device_id))
 888                 return I40E_SUCCESS;
 889
 890         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 891                                               NULL);
 892         if (status)
 893                 return ret;
 894
 895         memset(&phy_conf, 0, sizeof(phy_conf));
 896
 897         /* bits 0-2 use the values from get_phy_abilities_resp */
 898         abilities &= ~mask;
 899         abilities |= phy_ab.abilities & mask;
 900
 901         /* update ablities and speed */
 902         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 903                 phy_conf.link_speed = advt;
 904         else
 905                 phy_conf.link_speed = force_speed;
 906
 907         phy_conf.abilities = abilities;
 908
 909         /* use get_phy_abilities_resp value for the rest */
 910         phy_conf.phy_type = phy_ab.phy_type;
 911         phy_conf.eee_capability = phy_ab.eee_capability;
 912         phy_conf.eeer = phy_ab.eeer_val;
 913         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 914
 915         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 916                     phy_ab.abilities, phy_ab.link_speed);
 917         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 918                     phy_conf.abilities, phy_conf.link_speed);
 919
 920         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 921         if (status)
 922                 return ret;
 923
 924         return I40E_SUCCESS;
 925 }
 926
 927 static int
 928 i40e_apply_link_speed(struct rte_eth_dev *dev)
 929 {
 930         uint8_t speed;
 931         uint8_t abilities = 0;
 932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 933         struct rte_eth_conf *conf = &dev->data->dev_conf;
 934
 935         speed = i40e_parse_link_speed(conf->link_speed);
 936         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 937         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 938                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 939         else
 940                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 941
 942         return i40e_phy_conf_link(hw, abilities, speed);
 943 }
 944
 945 static int
 946 i40e_dev_start(struct rte_eth_dev *dev)
 947 {
 948         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 949         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 950         struct i40e_vsi *main_vsi = pf->main_vsi;
 951         int ret, i;
 952
 953         hw->adapter_stopped = 0;
 954
 955         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 956                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 957                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 958                              dev->data->dev_conf.link_duplex,
 959                              dev->data->port_id);
 960                 return -EINVAL;
 961         }
 962
 963         /* Initialize VSI */
 964         ret = i40e_dev_rxtx_init(pf);
 965         if (ret != I40E_SUCCESS) {
 966                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 967                 goto err_up;
 968         }
 969
 970         /* Map queues with MSIX interrupt */
 971         i40e_vsi_queues_bind_intr(main_vsi);
 972         i40e_vsi_enable_queues_intr(main_vsi);
 973
 974         /* Map VMDQ VSI queues with MSIX interrupt */
 975         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 976                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 977                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 978         }
 979
 980         /* enable FDIR MSIX interrupt */
 981         if (pf->fdir.fdir_vsi) {
 982                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 983                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 984         }
 985
 986         /* Enable all queues which have been configured */
 987         ret = i40e_dev_switch_queues(pf, TRUE);
 988         if (ret != I40E_SUCCESS) {
 989                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 990                 goto err_up;
 991         }
 992
 993         /* Enable receiving broadcast packets */
 994         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 995         if (ret != I40E_SUCCESS)
 996                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 997
 998         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 999                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1000                                                 true, NULL);
1001                 if (ret != I40E_SUCCESS)
1002                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1003         }
1004
1005         /* Apply link configure */
1006         ret = i40e_apply_link_speed(dev);
1007         if (I40E_SUCCESS != ret) {
1008                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1009                 goto err_up;
1010         }
1011
1012         return I40E_SUCCESS;
1013
1014 err_up:
1015         i40e_dev_switch_queues(pf, FALSE);
1016         i40e_dev_clear_queues(dev);
1017
1018         return ret;
1019 }
1020
1021 static void
1022 i40e_dev_stop(struct rte_eth_dev *dev)
1023 {
1024         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1025         struct i40e_vsi *main_vsi = pf->main_vsi;
1026         struct i40e_mirror_rule *p_mirror;
1027         int i;
1028
1029         /* Disable all queues */
1030         i40e_dev_switch_queues(pf, FALSE);
1031
1032         /* un-map queues with interrupt registers */
1033         i40e_vsi_disable_queues_intr(main_vsi);
1034         i40e_vsi_queues_unbind_intr(main_vsi);
1035
1036         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1037                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1038                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1039         }
1040
1041         if (pf->fdir.fdir_vsi) {
1042                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1043                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1044         }
1045         /* Clear all queues and release memory */
1046         i40e_dev_clear_queues(dev);
1047
1048         /* Set link down */
1049         i40e_dev_set_link_down(dev);
1050
1051         /* Remove all mirror rules */
1052         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1053                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1054                 rte_free(p_mirror);
1055         }
1056         pf->nb_mirror_rule = 0;
1057
1058 }
1059
1060 static void
1061 i40e_dev_close(struct rte_eth_dev *dev)
1062 {
1063         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1064         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1065         uint32_t reg;
1066         int i;
1067
1068         PMD_INIT_FUNC_TRACE();
1069
1070         i40e_dev_stop(dev);
1071         hw->adapter_stopped = 1;
1072
1073         /* Disable interrupt */
1074         i40e_pf_disable_irq0(hw);
1075         rte_intr_disable(&(dev->pci_dev->intr_handle));
1076
1077         /* shutdown and destroy the HMC */
1078         i40e_shutdown_lan_hmc(hw);
1079
1080         /* release all the existing VSIs and VEBs */
1081         i40e_fdir_teardown(pf);
1082         i40e_vsi_release(pf->main_vsi);
1083
1084         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1085                 i40e_vsi_release(pf->vmdq[i].vsi);
1086                 pf->vmdq[i].vsi = NULL;
1087         }
1088
1089         rte_free(pf->vmdq);
1090         pf->vmdq = NULL;
1091
1092         /* shutdown the adminq */
1093         i40e_aq_queue_shutdown(hw, true);
1094         i40e_shutdown_adminq(hw);
1095
1096         i40e_res_pool_destroy(&pf->qp_pool);
1097         i40e_res_pool_destroy(&pf->msix_pool);
1098
1099         /* force a PF reset to clean anything leftover */
1100         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1101         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1102                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1103         I40E_WRITE_FLUSH(hw);
1104 }
1105
1106 static void
1107 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1108 {
1109         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1110         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1111         struct i40e_vsi *vsi = pf->main_vsi;
1112         int status;
1113
1114         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1115                                                         true, NULL);
1116         if (status != I40E_SUCCESS)
1117                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1118
1119         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1120                                                         TRUE, NULL);
1121         if (status != I40E_SUCCESS)
1122                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1123
1124 }
1125
1126 static void
1127 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1128 {
1129         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1130         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1131         struct i40e_vsi *vsi = pf->main_vsi;
1132         int status;
1133
1134         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1135                                                         false, NULL);
1136         if (status != I40E_SUCCESS)
1137                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1138
1139         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1140                                                         false, NULL);
1141         if (status != I40E_SUCCESS)
1142                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1143 }
1144
1145 static void
1146 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1147 {
1148         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1149         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1150         struct i40e_vsi *vsi = pf->main_vsi;
1151         int ret;
1152
1153         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1154         if (ret != I40E_SUCCESS)
1155                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1156 }
1157
1158 static void
1159 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1160 {
1161         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1162         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1163         struct i40e_vsi *vsi = pf->main_vsi;
1164         int ret;
1165
1166         if (dev->data->promiscuous == 1)
1167                 return; /* must remain in all_multicast mode */
1168
1169         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1170                                 vsi->seid, FALSE, NULL);
1171         if (ret != I40E_SUCCESS)
1172                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1173 }
1174
1175 /*
1176  * Set device link up.
1177  */
1178 static int
1179 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1180 {
1181         /* re-apply link speed setting */
1182         return i40e_apply_link_speed(dev);
1183 }
1184
1185 /*
1186  * Set device link down.
1187  */
1188 static int
1189 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1190 {
1191         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1192         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1193         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1194
1195         return i40e_phy_conf_link(hw, abilities, speed);
1196 }
1197
1198 int
1199 i40e_dev_link_update(struct rte_eth_dev *dev,
1200                      int wait_to_complete)
1201 {
1202 #define CHECK_INTERVAL 100  /* 100ms */
1203 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1204         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205         struct i40e_link_status link_status;
1206         struct rte_eth_link link, old;
1207         int status;
1208         unsigned rep_cnt = MAX_REPEAT_TIME;
1209
1210         memset(&link, 0, sizeof(link));
1211         memset(&old, 0, sizeof(old));
1212         memset(&link_status, 0, sizeof(link_status));
1213         rte_i40e_dev_atomic_read_link_status(dev, &old);
1214
1215         do {
1216                 /* Get link status information from hardware */
1217                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1218                 if (status != I40E_SUCCESS) {
1219                         link.link_speed = ETH_LINK_SPEED_100;
1220                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1221                         PMD_DRV_LOG(ERR, "Failed to get link info");
1222                         goto out;
1223                 }
1224
1225                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1226                 if (!wait_to_complete)
1227                         break;
1228
1229                 rte_delay_ms(CHECK_INTERVAL);
1230         } while (!link.link_status && rep_cnt--);
1231
1232         if (!link.link_status)
1233                 goto out;
1234
1235         /* i40e uses full duplex only */
1236         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1237
1238         /* Parse the link status */
1239         switch (link_status.link_speed) {
1240         case I40E_LINK_SPEED_100MB:
1241                 link.link_speed = ETH_LINK_SPEED_100;
1242                 break;
1243         case I40E_LINK_SPEED_1GB:
1244                 link.link_speed = ETH_LINK_SPEED_1000;
1245                 break;
1246         case I40E_LINK_SPEED_10GB:
1247                 link.link_speed = ETH_LINK_SPEED_10G;
1248                 break;
1249         case I40E_LINK_SPEED_20GB:
1250                 link.link_speed = ETH_LINK_SPEED_20G;
1251                 break;
1252         case I40E_LINK_SPEED_40GB:
1253                 link.link_speed = ETH_LINK_SPEED_40G;
1254                 break;
1255         default:
1256                 link.link_speed = ETH_LINK_SPEED_100;
1257                 break;
1258         }
1259
1260 out:
1261         rte_i40e_dev_atomic_write_link_status(dev, &link);
1262         if (link.link_status == old.link_status)
1263                 return -1;
1264
1265         return 0;
1266 }
1267
1268 /* Get all the statistics of a VSI */
1269 void
1270 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1271 {
1272         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1273         struct i40e_eth_stats *nes = &vsi->eth_stats;
1274         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1275         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1276
1277         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1278                             vsi->offset_loaded, &oes->rx_bytes,
1279                             &nes->rx_bytes);
1280         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1281                             vsi->offset_loaded, &oes->rx_unicast,
1282                             &nes->rx_unicast);
1283         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1284                             vsi->offset_loaded, &oes->rx_multicast,
1285                             &nes->rx_multicast);
1286         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1287                             vsi->offset_loaded, &oes->rx_broadcast,
1288                             &nes->rx_broadcast);
1289         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1290                             &oes->rx_discards, &nes->rx_discards);
1291         /* GLV_REPC not supported */
1292         /* GLV_RMPC not supported */
1293         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1294                             &oes->rx_unknown_protocol,
1295                             &nes->rx_unknown_protocol);
1296         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1297                             vsi->offset_loaded, &oes->tx_bytes,
1298                             &nes->tx_bytes);
1299         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1300                             vsi->offset_loaded, &oes->tx_unicast,
1301                             &nes->tx_unicast);
1302         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1303                             vsi->offset_loaded, &oes->tx_multicast,
1304                             &nes->tx_multicast);
1305         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1306                             vsi->offset_loaded,  &oes->tx_broadcast,
1307                             &nes->tx_broadcast);
1308         /* GLV_TDPC not supported */
1309         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1310                             &oes->tx_errors, &nes->tx_errors);
1311         vsi->offset_loaded = true;
1312
1313         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1314                     vsi->vsi_id);
1315         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1316         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1317         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1318         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1319         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1320         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1321                     nes->rx_unknown_protocol);
1322         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1323         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1324         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1325         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1326         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1327         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1328         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1329                     vsi->vsi_id);
1330 }
1331
1332 /* Get all statistics of a port */
1333 static void
1334 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1335 {
1336         uint32_t i;
1337         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1338         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1339         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1340         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1341
1342         /* Get statistics of struct i40e_eth_stats */
1343         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1344                             I40E_GLPRT_GORCL(hw->port),
1345                             pf->offset_loaded, &os->eth.rx_bytes,
1346                             &ns->eth.rx_bytes);
1347         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1348                             I40E_GLPRT_UPRCL(hw->port),
1349                             pf->offset_loaded, &os->eth.rx_unicast,
1350                             &ns->eth.rx_unicast);
1351         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1352                             I40E_GLPRT_MPRCL(hw->port),
1353                             pf->offset_loaded, &os->eth.rx_multicast,
1354                             &ns->eth.rx_multicast);
1355         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1356                             I40E_GLPRT_BPRCL(hw->port),
1357                             pf->offset_loaded, &os->eth.rx_broadcast,
1358                             &ns->eth.rx_broadcast);
1359         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1360                             pf->offset_loaded, &os->eth.rx_discards,
1361                             &ns->eth.rx_discards);
1362         /* GLPRT_REPC not supported */
1363         /* GLPRT_RMPC not supported */
1364         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1365                             pf->offset_loaded,
1366                             &os->eth.rx_unknown_protocol,
1367                             &ns->eth.rx_unknown_protocol);
1368         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1369                             I40E_GLPRT_GOTCL(hw->port),
1370                             pf->offset_loaded, &os->eth.tx_bytes,
1371                             &ns->eth.tx_bytes);
1372         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1373                             I40E_GLPRT_UPTCL(hw->port),
1374                             pf->offset_loaded, &os->eth.tx_unicast,
1375                             &ns->eth.tx_unicast);
1376         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1377                             I40E_GLPRT_MPTCL(hw->port),
1378                             pf->offset_loaded, &os->eth.tx_multicast,
1379                             &ns->eth.tx_multicast);
1380         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1381                             I40E_GLPRT_BPTCL(hw->port),
1382                             pf->offset_loaded, &os->eth.tx_broadcast,
1383                             &ns->eth.tx_broadcast);
1384         /* GLPRT_TEPC not supported */
1385
1386         /* additional port specific stats */
1387         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1388                             pf->offset_loaded, &os->tx_dropped_link_down,
1389                             &ns->tx_dropped_link_down);
1390         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1391                             pf->offset_loaded, &os->crc_errors,
1392                             &ns->crc_errors);
1393         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1394                             pf->offset_loaded, &os->illegal_bytes,
1395                             &ns->illegal_bytes);
1396         /* GLPRT_ERRBC not supported */
1397         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1398                             pf->offset_loaded, &os->mac_local_faults,
1399                             &ns->mac_local_faults);
1400         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1401                             pf->offset_loaded, &os->mac_remote_faults,
1402                             &ns->mac_remote_faults);
1403         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1404                             pf->offset_loaded, &os->rx_length_errors,
1405                             &ns->rx_length_errors);
1406         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1407                             pf->offset_loaded, &os->link_xon_rx,
1408                             &ns->link_xon_rx);
1409         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1410                             pf->offset_loaded, &os->link_xoff_rx,
1411                             &ns->link_xoff_rx);
1412         for (i = 0; i < 8; i++) {
1413                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1414                                     pf->offset_loaded,
1415                                     &os->priority_xon_rx[i],
1416                                     &ns->priority_xon_rx[i]);
1417                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1418                                     pf->offset_loaded,
1419                                     &os->priority_xoff_rx[i],
1420                                     &ns->priority_xoff_rx[i]);
1421         }
1422         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1423                             pf->offset_loaded, &os->link_xon_tx,
1424                             &ns->link_xon_tx);
1425         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1426                             pf->offset_loaded, &os->link_xoff_tx,
1427                             &ns->link_xoff_tx);
1428         for (i = 0; i < 8; i++) {
1429                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1430                                     pf->offset_loaded,
1431                                     &os->priority_xon_tx[i],
1432                                     &ns->priority_xon_tx[i]);
1433                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1434                                     pf->offset_loaded,
1435                                     &os->priority_xoff_tx[i],
1436                                     &ns->priority_xoff_tx[i]);
1437                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1438                                     pf->offset_loaded,
1439                                     &os->priority_xon_2_xoff[i],
1440                                     &ns->priority_xon_2_xoff[i]);
1441         }
1442         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1443                             I40E_GLPRT_PRC64L(hw->port),
1444                             pf->offset_loaded, &os->rx_size_64,
1445                             &ns->rx_size_64);
1446         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1447                             I40E_GLPRT_PRC127L(hw->port),
1448                             pf->offset_loaded, &os->rx_size_127,
1449                             &ns->rx_size_127);
1450         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1451                             I40E_GLPRT_PRC255L(hw->port),
1452                             pf->offset_loaded, &os->rx_size_255,
1453                             &ns->rx_size_255);
1454         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1455                             I40E_GLPRT_PRC511L(hw->port),
1456                             pf->offset_loaded, &os->rx_size_511,
1457                             &ns->rx_size_511);
1458         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1459                             I40E_GLPRT_PRC1023L(hw->port),
1460                             pf->offset_loaded, &os->rx_size_1023,
1461                             &ns->rx_size_1023);
1462         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1463                             I40E_GLPRT_PRC1522L(hw->port),
1464                             pf->offset_loaded, &os->rx_size_1522,
1465                             &ns->rx_size_1522);
1466         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1467                             I40E_GLPRT_PRC9522L(hw->port),
1468                             pf->offset_loaded, &os->rx_size_big,
1469                             &ns->rx_size_big);
1470         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1471                             pf->offset_loaded, &os->rx_undersize,
1472                             &ns->rx_undersize);
1473         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1474                             pf->offset_loaded, &os->rx_fragments,
1475                             &ns->rx_fragments);
1476         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1477                             pf->offset_loaded, &os->rx_oversize,
1478                             &ns->rx_oversize);
1479         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1480                             pf->offset_loaded, &os->rx_jabber,
1481                             &ns->rx_jabber);
1482         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1483                             I40E_GLPRT_PTC64L(hw->port),
1484                             pf->offset_loaded, &os->tx_size_64,
1485                             &ns->tx_size_64);
1486         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1487                             I40E_GLPRT_PTC127L(hw->port),
1488                             pf->offset_loaded, &os->tx_size_127,
1489                             &ns->tx_size_127);
1490         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1491                             I40E_GLPRT_PTC255L(hw->port),
1492                             pf->offset_loaded, &os->tx_size_255,
1493                             &ns->tx_size_255);
1494         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1495                             I40E_GLPRT_PTC511L(hw->port),
1496                             pf->offset_loaded, &os->tx_size_511,
1497                             &ns->tx_size_511);
1498         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1499                             I40E_GLPRT_PTC1023L(hw->port),
1500                             pf->offset_loaded, &os->tx_size_1023,
1501                             &ns->tx_size_1023);
1502         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1503                             I40E_GLPRT_PTC1522L(hw->port),
1504                             pf->offset_loaded, &os->tx_size_1522,
1505                             &ns->tx_size_1522);
1506         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1507                             I40E_GLPRT_PTC9522L(hw->port),
1508                             pf->offset_loaded, &os->tx_size_big,
1509                             &ns->tx_size_big);
1510         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1511                            pf->offset_loaded,
1512                            &os->fd_sb_match, &ns->fd_sb_match);
1513         /* GLPRT_MSPDC not supported */
1514         /* GLPRT_XEC not supported */
1515
1516         pf->offset_loaded = true;
1517
1518         if (pf->main_vsi)
1519                 i40e_update_vsi_stats(pf->main_vsi);
1520
1521         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1522                                                 ns->eth.rx_broadcast;
1523         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1524                                                 ns->eth.tx_broadcast;
1525         stats->ibytes   = ns->eth.rx_bytes;
1526         stats->obytes   = ns->eth.tx_bytes;
1527         stats->oerrors  = ns->eth.tx_errors;
1528         stats->imcasts  = ns->eth.rx_multicast;
1529         stats->fdirmatch = ns->fd_sb_match;
1530
1531         /* Rx Errors */
1532         stats->ibadcrc  = ns->crc_errors;
1533         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1534                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1535         stats->imissed  = ns->eth.rx_discards;
1536         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1537
1538         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1539         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
1540         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
1541         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
1542         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
1543         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
1544         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1545                     ns->eth.rx_unknown_protocol);
1546         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
1547         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
1548         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
1549         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
1550         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
1551         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
1552
1553         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
1554                     ns->tx_dropped_link_down);
1555         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
1556         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
1557                     ns->illegal_bytes);
1558         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
1559         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
1560                     ns->mac_local_faults);
1561         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
1562                     ns->mac_remote_faults);
1563         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
1564                     ns->rx_length_errors);
1565         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
1566         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
1567         for (i = 0; i < 8; i++) {
1568                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
1569                                 i, ns->priority_xon_rx[i]);
1570                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
1571                                 i, ns->priority_xoff_rx[i]);
1572         }
1573         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
1574         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
1575         for (i = 0; i < 8; i++) {
1576                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
1577                                 i, ns->priority_xon_tx[i]);
1578                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
1579                                 i, ns->priority_xoff_tx[i]);
1580                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
1581                                 i, ns->priority_xon_2_xoff[i]);
1582         }
1583         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
1584         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
1585         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
1586         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
1587         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
1588         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
1589         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
1590         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
1591         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
1592         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
1593         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
1594         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
1595         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
1596         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
1597         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
1598         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
1599         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
1600         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
1601         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1602                         ns->mac_short_packet_dropped);
1603         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
1604                     ns->checksum_error);
1605         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
1606         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1607 }
1608
1609 /* Reset the statistics */
1610 static void
1611 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1612 {
1613         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1614
1615         /* It results in reloading the start point of each counter */
1616         pf->offset_loaded = false;
1617 }
1618
1619 static int
1620 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1621                                  __rte_unused uint16_t queue_id,
1622                                  __rte_unused uint8_t stat_idx,
1623                                  __rte_unused uint8_t is_rx)
1624 {
1625         PMD_INIT_FUNC_TRACE();
1626
1627         return -ENOSYS;
1628 }
1629
1630 static void
1631 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1632 {
1633         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1634         struct i40e_vsi *vsi = pf->main_vsi;
1635
1636         dev_info->max_rx_queues = vsi->nb_qps;
1637         dev_info->max_tx_queues = vsi->nb_qps;
1638         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1639         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1640         dev_info->max_mac_addrs = vsi->max_macaddrs;
1641         dev_info->max_vfs = dev->pci_dev->max_vfs;
1642         dev_info->rx_offload_capa =
1643                 DEV_RX_OFFLOAD_VLAN_STRIP |
1644                 DEV_RX_OFFLOAD_QINQ_STRIP |
1645                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1646                 DEV_RX_OFFLOAD_UDP_CKSUM |
1647                 DEV_RX_OFFLOAD_TCP_CKSUM;
1648         dev_info->tx_offload_capa =
1649                 DEV_TX_OFFLOAD_VLAN_INSERT |
1650                 DEV_TX_OFFLOAD_QINQ_INSERT |
1651                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1652                 DEV_TX_OFFLOAD_UDP_CKSUM |
1653                 DEV_TX_OFFLOAD_TCP_CKSUM |
1654                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1655                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1656                 DEV_TX_OFFLOAD_TCP_TSO;
1657         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
1658                                                 sizeof(uint32_t);
1659         dev_info->reta_size = pf->hash_lut_size;
1660         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1661
1662         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1663                 .rx_thresh = {
1664                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1665                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1666                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1667                 },
1668                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1669                 .rx_drop_en = 0,
1670         };
1671
1672         dev_info->default_txconf = (struct rte_eth_txconf) {
1673                 .tx_thresh = {
1674                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1675                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1676                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1677                 },
1678                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1679                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1680                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1681                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1682         };
1683
1684         if (pf->flags & I40E_FLAG_VMDQ) {
1685                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1686                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1687                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1688                                                 pf->max_nb_vmdq_vsi;
1689                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1690                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1691                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1692         }
1693 }
1694
1695 static int
1696 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1697 {
1698         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1699         struct i40e_vsi *vsi = pf->main_vsi;
1700         PMD_INIT_FUNC_TRACE();
1701
1702         if (on)
1703                 return i40e_vsi_add_vlan(vsi, vlan_id);
1704         else
1705                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1706 }
1707
1708 static void
1709 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1710                    __rte_unused uint16_t tpid)
1711 {
1712         PMD_INIT_FUNC_TRACE();
1713 }
1714
1715 static void
1716 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1717 {
1718         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1719         struct i40e_vsi *vsi = pf->main_vsi;
1720
1721         if (mask & ETH_VLAN_STRIP_MASK) {
1722                 /* Enable or disable VLAN stripping */
1723                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1724                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1725                 else
1726                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1727         }
1728
1729         if (mask & ETH_VLAN_EXTEND_MASK) {
1730                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1731                         i40e_vsi_config_double_vlan(vsi, TRUE);
1732                 else
1733                         i40e_vsi_config_double_vlan(vsi, FALSE);
1734         }
1735 }
1736
1737 static void
1738 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1739                           __rte_unused uint16_t queue,
1740                           __rte_unused int on)
1741 {
1742         PMD_INIT_FUNC_TRACE();
1743 }
1744
1745 static int
1746 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1747 {
1748         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1749         struct i40e_vsi *vsi = pf->main_vsi;
1750         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1751         struct i40e_vsi_vlan_pvid_info info;
1752
1753         memset(&info, 0, sizeof(info));
1754         info.on = on;
1755         if (info.on)
1756                 info.config.pvid = pvid;
1757         else {
1758                 info.config.reject.tagged =
1759                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1760                 info.config.reject.untagged =
1761                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1762         }
1763
1764         return i40e_vsi_vlan_pvid_set(vsi, &info);
1765 }
1766
1767 static int
1768 i40e_dev_led_on(struct rte_eth_dev *dev)
1769 {
1770         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1771         uint32_t mode = i40e_led_get(hw);
1772
1773         if (mode == 0)
1774                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1775
1776         return 0;
1777 }
1778
1779 static int
1780 i40e_dev_led_off(struct rte_eth_dev *dev)
1781 {
1782         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1783         uint32_t mode = i40e_led_get(hw);
1784
1785         if (mode != 0)
1786                 i40e_led_set(hw, 0, false);
1787
1788         return 0;
1789 }
1790
1791 static int
1792 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1793                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1794 {
1795         PMD_INIT_FUNC_TRACE();
1796
1797         return -ENOSYS;
1798 }
1799
1800 static int
1801 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1802                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1803 {
1804         PMD_INIT_FUNC_TRACE();
1805
1806         return -ENOSYS;
1807 }
1808
1809 /* Add a MAC address, and update filters */
1810 static void
1811 i40e_macaddr_add(struct rte_eth_dev *dev,
1812                  struct ether_addr *mac_addr,
1813                  __rte_unused uint32_t index,
1814                  uint32_t pool)
1815 {
1816         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1817         struct i40e_mac_filter_info mac_filter;
1818         struct i40e_vsi *vsi;
1819         int ret;
1820
1821         /* If VMDQ not enabled or configured, return */
1822         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1823                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1824                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1825                         pool);
1826                 return;
1827         }
1828
1829         if (pool > pf->nb_cfg_vmdq_vsi) {
1830                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1831                                 pool, pf->nb_cfg_vmdq_vsi);
1832                 return;
1833         }
1834
1835         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1836         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1837
1838         if (pool == 0)
1839                 vsi = pf->main_vsi;
1840         else
1841                 vsi = pf->vmdq[pool - 1].vsi;
1842
1843         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1844         if (ret != I40E_SUCCESS) {
1845                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1846                 return;
1847         }
1848 }
1849
1850 /* Remove a MAC address, and update filters */
1851 static void
1852 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1853 {
1854         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1855         struct i40e_vsi *vsi;
1856         struct rte_eth_dev_data *data = dev->data;
1857         struct ether_addr *macaddr;
1858         int ret;
1859         uint32_t i;
1860         uint64_t pool_sel;
1861
1862         macaddr = &(data->mac_addrs[index]);
1863
1864         pool_sel = dev->data->mac_pool_sel[index];
1865
1866         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1867                 if (pool_sel & (1ULL << i)) {
1868                         if (i == 0)
1869                                 vsi = pf->main_vsi;
1870                         else {
1871                                 /* No VMDQ pool enabled or configured */
1872                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1873                                         (i > pf->nb_cfg_vmdq_vsi)) {
1874                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1875                                                         "/configured");
1876                                         return;
1877                                 }
1878                                 vsi = pf->vmdq[i - 1].vsi;
1879                         }
1880                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1881
1882                         if (ret) {
1883                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1884                                 return;
1885                         }
1886                 }
1887         }
1888 }
1889
1890 /* Set perfect match or hash match of MAC and VLAN for a VF */
1891 static int
1892 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1893                  struct rte_eth_mac_filter *filter,
1894                  bool add)
1895 {
1896         struct i40e_hw *hw;
1897         struct i40e_mac_filter_info mac_filter;
1898         struct ether_addr old_mac;
1899         struct ether_addr *new_mac;
1900         struct i40e_pf_vf *vf = NULL;
1901         uint16_t vf_id;
1902         int ret;
1903
1904         if (pf == NULL) {
1905                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1906                 return -EINVAL;
1907         }
1908         hw = I40E_PF_TO_HW(pf);
1909
1910         if (filter == NULL) {
1911                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1912                 return -EINVAL;
1913         }
1914
1915         new_mac = &filter->mac_addr;
1916
1917         if (is_zero_ether_addr(new_mac)) {
1918                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1919                 return -EINVAL;
1920         }
1921
1922         vf_id = filter->dst_id;
1923
1924         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1925                 PMD_DRV_LOG(ERR, "Invalid argument.");
1926                 return -EINVAL;
1927         }
1928         vf = &pf->vfs[vf_id];
1929
1930         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1931                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1932                 return -EINVAL;
1933         }
1934
1935         if (add) {
1936                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1937                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1938                                 ETHER_ADDR_LEN);
1939                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1940                                  ETHER_ADDR_LEN);
1941
1942                 mac_filter.filter_type = filter->filter_type;
1943                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1944                 if (ret != I40E_SUCCESS) {
1945                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1946                         return -1;
1947                 }
1948                 ether_addr_copy(new_mac, &pf->dev_addr);
1949         } else {
1950                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1951                                 ETHER_ADDR_LEN);
1952                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1953                 if (ret != I40E_SUCCESS) {
1954                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1955                         return -1;
1956                 }
1957
1958                 /* Clear device address as it has been removed */
1959                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1960                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1961         }
1962
1963         return 0;
1964 }
1965
1966 /* MAC filter handle */
1967 static int
1968 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1969                 void *arg)
1970 {
1971         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1972         struct rte_eth_mac_filter *filter;
1973         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1974         int ret = I40E_NOT_SUPPORTED;
1975
1976         filter = (struct rte_eth_mac_filter *)(arg);
1977
1978         switch (filter_op) {
1979         case RTE_ETH_FILTER_NOP:
1980                 ret = I40E_SUCCESS;
1981                 break;
1982         case RTE_ETH_FILTER_ADD:
1983                 i40e_pf_disable_irq0(hw);
1984                 if (filter->is_vf)
1985                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1986                 i40e_pf_enable_irq0(hw);
1987                 break;
1988         case RTE_ETH_FILTER_DELETE:
1989                 i40e_pf_disable_irq0(hw);
1990                 if (filter->is_vf)
1991                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1992                 i40e_pf_enable_irq0(hw);
1993                 break;
1994         default:
1995                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1996                 ret = I40E_ERR_PARAM;
1997                 break;
1998         }
1999
2000         return ret;
2001 }
2002
2003 static int
2004 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2005                          struct rte_eth_rss_reta_entry64 *reta_conf,
2006                          uint16_t reta_size)
2007 {
2008         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2009         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2010         uint32_t lut, l;
2011         uint16_t i, j, lut_size = pf->hash_lut_size;
2012         uint16_t idx, shift;
2013         uint8_t mask;
2014
2015         if (reta_size != lut_size ||
2016                 reta_size > ETH_RSS_RETA_SIZE_512) {
2017                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2018                         "(%d) doesn't match the number hardware can supported "
2019                                         "(%d)\n", reta_size, lut_size);
2020                 return -EINVAL;
2021         }
2022
2023         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2024                 idx = i / RTE_RETA_GROUP_SIZE;
2025                 shift = i % RTE_RETA_GROUP_SIZE;
2026                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2027                                                 I40E_4_BIT_MASK);
2028                 if (!mask)
2029                         continue;
2030                 if (mask == I40E_4_BIT_MASK)
2031                         l = 0;
2032                 else
2033                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2034                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
2035                         if (mask & (0x1 << j))
2036                                 lut |= reta_conf[idx].reta[shift + j] <<
2037                                                         (CHAR_BIT * j);
2038                         else
2039                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
2040                 }
2041                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
2042         }
2043
2044         return 0;
2045 }
2046
2047 static int
2048 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2049                         struct rte_eth_rss_reta_entry64 *reta_conf,
2050                         uint16_t reta_size)
2051 {
2052         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2053         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2054         uint32_t lut;
2055         uint16_t i, j, lut_size = pf->hash_lut_size;
2056         uint16_t idx, shift;
2057         uint8_t mask;
2058
2059         if (reta_size != lut_size ||
2060                 reta_size > ETH_RSS_RETA_SIZE_512) {
2061                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2062                         "(%d) doesn't match the number hardware can supported "
2063                                         "(%d)\n", reta_size, lut_size);
2064                 return -EINVAL;
2065         }
2066
2067         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2068                 idx = i / RTE_RETA_GROUP_SIZE;
2069                 shift = i % RTE_RETA_GROUP_SIZE;
2070                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2071                                                 I40E_4_BIT_MASK);
2072                 if (!mask)
2073                         continue;
2074
2075                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2076                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
2077                         if (mask & (0x1 << j))
2078                                 reta_conf[idx].reta[shift + j] = ((lut >>
2079                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
2080                 }
2081         }
2082
2083         return 0;
2084 }
2085
2086 /**
2087  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2088  * @hw:   pointer to the HW structure
2089  * @mem:  pointer to mem struct to fill out
2090  * @size: size of memory requested
2091  * @alignment: what to align the allocation to
2092  **/
2093 enum i40e_status_code
2094 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2095                         struct i40e_dma_mem *mem,
2096                         u64 size,
2097                         u32 alignment)
2098 {
2099         static uint64_t id = 0;
2100         const struct rte_memzone *mz = NULL;
2101         char z_name[RTE_MEMZONE_NAMESIZE];
2102
2103         if (!mem)
2104                 return I40E_ERR_PARAM;
2105
2106         id++;
2107         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2108 #ifdef RTE_LIBRTE_XEN_DOM0
2109         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
2110                                                         RTE_PGSIZE_2M);
2111 #else
2112         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
2113 #endif
2114         if (!mz)
2115                 return I40E_ERR_NO_MEMORY;
2116
2117         mem->id = id;
2118         mem->size = size;
2119         mem->va = mz->addr;
2120 #ifdef RTE_LIBRTE_XEN_DOM0
2121         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2122 #else
2123         mem->pa = mz->phys_addr;
2124 #endif
2125
2126         return I40E_SUCCESS;
2127 }
2128
2129 /**
2130  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2131  * @hw:   pointer to the HW structure
2132  * @mem:  ptr to mem struct to free
2133  **/
2134 enum i40e_status_code
2135 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2136                     struct i40e_dma_mem *mem)
2137 {
2138         if (!mem || !mem->va)
2139                 return I40E_ERR_PARAM;
2140
2141         mem->va = NULL;
2142         mem->pa = (u64)0;
2143
2144         return I40E_SUCCESS;
2145 }
2146
2147 /**
2148  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2149  * @hw:   pointer to the HW structure
2150  * @mem:  pointer to mem struct to fill out
2151  * @size: size of memory requested
2152  **/
2153 enum i40e_status_code
2154 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2155                          struct i40e_virt_mem *mem,
2156                          u32 size)
2157 {
2158         if (!mem)
2159                 return I40E_ERR_PARAM;
2160
2161         mem->size = size;
2162         mem->va = rte_zmalloc("i40e", size, 0);
2163
2164         if (mem->va)
2165                 return I40E_SUCCESS;
2166         else
2167                 return I40E_ERR_NO_MEMORY;
2168 }
2169
2170 /**
2171  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2172  * @hw:   pointer to the HW structure
2173  * @mem:  pointer to mem struct to free
2174  **/
2175 enum i40e_status_code
2176 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2177                      struct i40e_virt_mem *mem)
2178 {
2179         if (!mem)
2180                 return I40E_ERR_PARAM;
2181
2182         rte_free(mem->va);
2183         mem->va = NULL;
2184
2185         return I40E_SUCCESS;
2186 }
2187
2188 void
2189 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2190 {
2191         rte_spinlock_init(&sp->spinlock);
2192 }
2193
2194 void
2195 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2196 {
2197         rte_spinlock_lock(&sp->spinlock);
2198 }
2199
2200 void
2201 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2202 {
2203         rte_spinlock_unlock(&sp->spinlock);
2204 }
2205
2206 void
2207 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2208 {
2209         return;
2210 }
2211
2212 /**
2213  * Get the hardware capabilities, which will be parsed
2214  * and saved into struct i40e_hw.
2215  */
2216 static int
2217 i40e_get_cap(struct i40e_hw *hw)
2218 {
2219         struct i40e_aqc_list_capabilities_element_resp *buf;
2220         uint16_t len, size = 0;
2221         int ret;
2222
2223         /* Calculate a huge enough buff for saving response data temporarily */
2224         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2225                                                 I40E_MAX_CAP_ELE_NUM;
2226         buf = rte_zmalloc("i40e", len, 0);
2227         if (!buf) {
2228                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2229                 return I40E_ERR_NO_MEMORY;
2230         }
2231
2232         /* Get, parse the capabilities and save it to hw */
2233         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2234                         i40e_aqc_opc_list_func_capabilities, NULL);
2235         if (ret != I40E_SUCCESS)
2236                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2237
2238         /* Free the temporary buffer after being used */
2239         rte_free(buf);
2240
2241         return ret;
2242 }
2243
2244 static int
2245 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2246 {
2247         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2248         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2249         uint16_t sum_queues = 0, sum_vsis, left_queues;
2250
2251         /* First check if FW support SRIOV */
2252         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2253                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2254                 return -EINVAL;
2255         }
2256
2257         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2258         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2259         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2260         /* Allocate queues for pf */
2261         if (hw->func_caps.rss) {
2262                 pf->flags |= I40E_FLAG_RSS;
2263                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2264                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2265                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2266         } else
2267                 pf->lan_nb_qps = 1;
2268         sum_queues = pf->lan_nb_qps;
2269         /* Default VSI is not counted in */
2270         sum_vsis = 0;
2271         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2272
2273         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2274                 pf->flags |= I40E_FLAG_SRIOV;
2275                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2276                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2277                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2278                                      "max supported %u.",
2279                                      dev->pci_dev->max_vfs,
2280                                      hw->func_caps.num_vfs);
2281                         return -EINVAL;
2282                 }
2283                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2284                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2285                                      "max support %u queues.",
2286                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2287                         return -EINVAL;
2288                 }
2289                 pf->vf_num = dev->pci_dev->max_vfs;
2290                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2291                 sum_vsis   += pf->vf_num;
2292                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2293                              pf->vf_num, pf->vf_nb_qps);
2294         } else
2295                 pf->vf_num = 0;
2296
2297         if (hw->func_caps.vmdq) {
2298                 pf->flags |= I40E_FLAG_VMDQ;
2299                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2300                 pf->max_nb_vmdq_vsi = 1;
2301                 /*
2302                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2303                  * later.
2304                  */
2305                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2306                 sum_vsis += pf->max_nb_vmdq_vsi;
2307         } else {
2308                 pf->vmdq_nb_qps = 0;
2309                 pf->max_nb_vmdq_vsi = 0;
2310         }
2311         pf->nb_cfg_vmdq_vsi = 0;
2312
2313         if (hw->func_caps.fd) {
2314                 pf->flags |= I40E_FLAG_FDIR;
2315                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2316                 /**
2317                  * Each flow director consumes one VSI and one queue,
2318                  * but can't calculate out predictably here.
2319                  */
2320         }
2321
2322         if (sum_vsis > pf->max_num_vsi ||
2323                 sum_queues > hw->func_caps.num_rx_qp) {
2324                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2325                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2326                              pf->max_num_vsi, sum_vsis);
2327                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2328                              hw->func_caps.num_rx_qp, sum_queues);
2329                 return -EINVAL;
2330         }
2331
2332         /* Adjust VMDQ setting to support as many VMs as possible */
2333         if (pf->flags & I40E_FLAG_VMDQ) {
2334                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2335
2336                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2337                                         pf->max_num_vsi - sum_vsis);
2338
2339                 /* Limit the max VMDQ number that rte_ether that can support  */
2340                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2341                                         ETH_64_POOLS - 1);
2342
2343                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2344                                 pf->max_nb_vmdq_vsi);
2345                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2346         }
2347
2348         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2349          * cause */
2350         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2351                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2352                              sum_vsis, hw->func_caps.num_msix_vectors);
2353                 return -EINVAL;
2354         }
2355         return I40E_SUCCESS;
2356 }
2357
2358 static int
2359 i40e_pf_get_switch_config(struct i40e_pf *pf)
2360 {
2361         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2362         struct i40e_aqc_get_switch_config_resp *switch_config;
2363         struct i40e_aqc_switch_config_element_resp *element;
2364         uint16_t start_seid = 0, num_reported;
2365         int ret;
2366
2367         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2368                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2369         if (!switch_config) {
2370                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2371                 return -ENOMEM;
2372         }
2373
2374         /* Get the switch configurations */
2375         ret = i40e_aq_get_switch_config(hw, switch_config,
2376                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2377         if (ret != I40E_SUCCESS) {
2378                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2379                 goto fail;
2380         }
2381         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2382         if (num_reported != 1) { /* The number should be 1 */
2383                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2384                 goto fail;
2385         }
2386
2387         /* Parse the switch configuration elements */
2388         element = &(switch_config->element[0]);
2389         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2390                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2391                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2392         } else
2393                 PMD_DRV_LOG(INFO, "Unknown element type");
2394
2395 fail:
2396         rte_free(switch_config);
2397
2398         return ret;
2399 }
2400
2401 static int
2402 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2403                         uint32_t num)
2404 {
2405         struct pool_entry *entry;
2406
2407         if (pool == NULL || num == 0)
2408                 return -EINVAL;
2409
2410         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2411         if (entry == NULL) {
2412                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2413                 return -ENOMEM;
2414         }
2415
2416         /* queue heap initialize */
2417         pool->num_free = num;
2418         pool->num_alloc = 0;
2419         pool->base = base;
2420         LIST_INIT(&pool->alloc_list);
2421         LIST_INIT(&pool->free_list);
2422
2423         /* Initialize element  */
2424         entry->base = 0;
2425         entry->len = num;
2426
2427         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2428         return 0;
2429 }
2430
2431 static void
2432 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2433 {
2434         struct pool_entry *entry;
2435
2436         if (pool == NULL)
2437                 return;
2438
2439         LIST_FOREACH(entry, &pool->alloc_list, next) {
2440                 LIST_REMOVE(entry, next);
2441                 rte_free(entry);
2442         }
2443
2444         LIST_FOREACH(entry, &pool->free_list, next) {
2445                 LIST_REMOVE(entry, next);
2446                 rte_free(entry);
2447         }
2448
2449         pool->num_free = 0;
2450         pool->num_alloc = 0;
2451         pool->base = 0;
2452         LIST_INIT(&pool->alloc_list);
2453         LIST_INIT(&pool->free_list);
2454 }
2455
2456 static int
2457 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2458                        uint32_t base)
2459 {
2460         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2461         uint32_t pool_offset;
2462         int insert;
2463
2464         if (pool == NULL) {
2465                 PMD_DRV_LOG(ERR, "Invalid parameter");
2466                 return -EINVAL;
2467         }
2468
2469         pool_offset = base - pool->base;
2470         /* Lookup in alloc list */
2471         LIST_FOREACH(entry, &pool->alloc_list, next) {
2472                 if (entry->base == pool_offset) {
2473                         valid_entry = entry;
2474                         LIST_REMOVE(entry, next);
2475                         break;
2476                 }
2477         }
2478
2479         /* Not find, return */
2480         if (valid_entry == NULL) {
2481                 PMD_DRV_LOG(ERR, "Failed to find entry");
2482                 return -EINVAL;
2483         }
2484
2485         /**
2486          * Found it, move it to free list  and try to merge.
2487          * In order to make merge easier, always sort it by qbase.
2488          * Find adjacent prev and last entries.
2489          */
2490         prev = next = NULL;
2491         LIST_FOREACH(entry, &pool->free_list, next) {
2492                 if (entry->base > valid_entry->base) {
2493                         next = entry;
2494                         break;
2495                 }
2496                 prev = entry;
2497         }
2498
2499         insert = 0;
2500         /* Try to merge with next one*/
2501         if (next != NULL) {
2502                 /* Merge with next one */
2503                 if (valid_entry->base + valid_entry->len == next->base) {
2504                         next->base = valid_entry->base;
2505                         next->len += valid_entry->len;
2506                         rte_free(valid_entry);
2507                         valid_entry = next;
2508                         insert = 1;
2509                 }
2510         }
2511
2512         if (prev != NULL) {
2513                 /* Merge with previous one */
2514                 if (prev->base + prev->len == valid_entry->base) {
2515                         prev->len += valid_entry->len;
2516                         /* If it merge with next one, remove next node */
2517                         if (insert == 1) {
2518                                 LIST_REMOVE(valid_entry, next);
2519                                 rte_free(valid_entry);
2520                         } else {
2521                                 rte_free(valid_entry);
2522                                 insert = 1;
2523                         }
2524                 }
2525         }
2526
2527         /* Not find any entry to merge, insert */
2528         if (insert == 0) {
2529                 if (prev != NULL)
2530                         LIST_INSERT_AFTER(prev, valid_entry, next);
2531                 else if (next != NULL)
2532                         LIST_INSERT_BEFORE(next, valid_entry, next);
2533                 else /* It's empty list, insert to head */
2534                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2535         }
2536
2537         pool->num_free += valid_entry->len;
2538         pool->num_alloc -= valid_entry->len;
2539
2540         return 0;
2541 }
2542
2543 static int
2544 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2545                        uint16_t num)
2546 {
2547         struct pool_entry *entry, *valid_entry;
2548
2549         if (pool == NULL || num == 0) {
2550                 PMD_DRV_LOG(ERR, "Invalid parameter");
2551                 return -EINVAL;
2552         }
2553
2554         if (pool->num_free < num) {
2555                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2556                             num, pool->num_free);
2557                 return -ENOMEM;
2558         }
2559
2560         valid_entry = NULL;
2561         /* Lookup  in free list and find most fit one */
2562         LIST_FOREACH(entry, &pool->free_list, next) {
2563                 if (entry->len >= num) {
2564                         /* Find best one */
2565                         if (entry->len == num) {
2566                                 valid_entry = entry;
2567                                 break;
2568                         }
2569                         if (valid_entry == NULL || valid_entry->len > entry->len)
2570                                 valid_entry = entry;
2571                 }
2572         }
2573
2574         /* Not find one to satisfy the request, return */
2575         if (valid_entry == NULL) {
2576                 PMD_DRV_LOG(ERR, "No valid entry found");
2577                 return -ENOMEM;
2578         }
2579         /**
2580          * The entry have equal queue number as requested,
2581          * remove it from alloc_list.
2582          */
2583         if (valid_entry->len == num) {
2584                 LIST_REMOVE(valid_entry, next);
2585         } else {
2586                 /**
2587                  * The entry have more numbers than requested,
2588                  * create a new entry for alloc_list and minus its
2589                  * queue base and number in free_list.
2590                  */
2591                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2592                 if (entry == NULL) {
2593                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2594                                     "resource pool");
2595                         return -ENOMEM;
2596                 }
2597                 entry->base = valid_entry->base;
2598                 entry->len = num;
2599                 valid_entry->base += num;
2600                 valid_entry->len -= num;
2601                 valid_entry = entry;
2602         }
2603
2604         /* Insert it into alloc list, not sorted */
2605         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2606
2607         pool->num_free -= valid_entry->len;
2608         pool->num_alloc += valid_entry->len;
2609
2610         return (valid_entry->base + pool->base);
2611 }
2612
2613 /**
2614  * bitmap_is_subset - Check whether src2 is subset of src1
2615  **/
2616 static inline int
2617 bitmap_is_subset(uint8_t src1, uint8_t src2)
2618 {
2619         return !((src1 ^ src2) & src2);
2620 }
2621
2622 static int
2623 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2624 {
2625         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2626
2627         /* If DCB is not supported, only default TC is supported */
2628         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2629                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2630                 return -EINVAL;
2631         }
2632
2633         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2634                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2635                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2636                             enabled_tcmap);
2637                 return -EINVAL;
2638         }
2639         return I40E_SUCCESS;
2640 }
2641
2642 int
2643 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2644                                 struct i40e_vsi_vlan_pvid_info *info)
2645 {
2646         struct i40e_hw *hw;
2647         struct i40e_vsi_context ctxt;
2648         uint8_t vlan_flags = 0;
2649         int ret;
2650
2651         if (vsi == NULL || info == NULL) {
2652                 PMD_DRV_LOG(ERR, "invalid parameters");
2653                 return I40E_ERR_PARAM;
2654         }
2655
2656         if (info->on) {
2657                 vsi->info.pvid = info->config.pvid;
2658                 /**
2659                  * If insert pvid is enabled, only tagged pkts are
2660                  * allowed to be sent out.
2661                  */
2662                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2663                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2664         } else {
2665                 vsi->info.pvid = 0;
2666                 if (info->config.reject.tagged == 0)
2667                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2668
2669                 if (info->config.reject.untagged == 0)
2670                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2671         }
2672         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2673                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2674         vsi->info.port_vlan_flags |= vlan_flags;
2675         vsi->info.valid_sections =
2676                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2677         memset(&ctxt, 0, sizeof(ctxt));
2678         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2679         ctxt.seid = vsi->seid;
2680
2681         hw = I40E_VSI_TO_HW(vsi);
2682         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2683         if (ret != I40E_SUCCESS)
2684                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2685
2686         return ret;
2687 }
2688
2689 static int
2690 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2691 {
2692         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2693         int i, ret;
2694         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2695
2696         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2697         if (ret != I40E_SUCCESS)
2698                 return ret;
2699
2700         if (!vsi->seid) {
2701                 PMD_DRV_LOG(ERR, "seid not valid");
2702                 return -EINVAL;
2703         }
2704
2705         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2706         tc_bw_data.tc_valid_bits = enabled_tcmap;
2707         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2708                 tc_bw_data.tc_bw_credits[i] =
2709                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2710
2711         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2712         if (ret != I40E_SUCCESS) {
2713                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2714                 return ret;
2715         }
2716
2717         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2718                                         sizeof(vsi->info.qs_handle));
2719         return I40E_SUCCESS;
2720 }
2721
2722 static int
2723 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2724                                  struct i40e_aqc_vsi_properties_data *info,
2725                                  uint8_t enabled_tcmap)
2726 {
2727         int ret, total_tc = 0, i;
2728         uint16_t qpnum_per_tc, bsf, qp_idx;
2729
2730         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2731         if (ret != I40E_SUCCESS)
2732                 return ret;
2733
2734         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2735                 if (enabled_tcmap & (1 << i))
2736                         total_tc++;
2737         vsi->enabled_tc = enabled_tcmap;
2738
2739         /* Number of queues per enabled TC */
2740         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2741         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2742         bsf = rte_bsf32(qpnum_per_tc);
2743
2744         /* Adjust the queue number to actual queues that can be applied */
2745         vsi->nb_qps = qpnum_per_tc * total_tc;
2746
2747         /**
2748          * Configure TC and queue mapping parameters, for enabled TC,
2749          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2750          * default queue will serve it.
2751          */
2752         qp_idx = 0;
2753         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2754                 if (vsi->enabled_tc & (1 << i)) {
2755                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2756                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2757                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2758                         qp_idx += qpnum_per_tc;
2759                 } else
2760                         info->tc_mapping[i] = 0;
2761         }
2762
2763         /* Associate queue number with VSI */
2764         if (vsi->type == I40E_VSI_SRIOV) {
2765                 info->mapping_flags |=
2766                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2767                 for (i = 0; i < vsi->nb_qps; i++)
2768                         info->queue_mapping[i] =
2769                                 rte_cpu_to_le_16(vsi->base_queue + i);
2770         } else {
2771                 info->mapping_flags |=
2772                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2773                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2774         }
2775         info->valid_sections |=
2776                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2777
2778         return I40E_SUCCESS;
2779 }
2780
2781 static int
2782 i40e_veb_release(struct i40e_veb *veb)
2783 {
2784         struct i40e_vsi *vsi;
2785         struct i40e_hw *hw;
2786
2787         if (veb == NULL || veb->associate_vsi == NULL)
2788                 return -EINVAL;
2789
2790         if (!TAILQ_EMPTY(&veb->head)) {
2791                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2792                 return -EACCES;
2793         }
2794
2795         vsi = veb->associate_vsi;
2796         hw = I40E_VSI_TO_HW(vsi);
2797
2798         vsi->uplink_seid = veb->uplink_seid;
2799         i40e_aq_delete_element(hw, veb->seid, NULL);
2800         rte_free(veb);
2801         vsi->veb = NULL;
2802         return I40E_SUCCESS;
2803 }
2804
2805 /* Setup a veb */
2806 static struct i40e_veb *
2807 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2808 {
2809         struct i40e_veb *veb;
2810         int ret;
2811         struct i40e_hw *hw;
2812
2813         if (NULL == pf || vsi == NULL) {
2814                 PMD_DRV_LOG(ERR, "veb setup failed, "
2815                             "associated VSI shouldn't null");
2816                 return NULL;
2817         }
2818         hw = I40E_PF_TO_HW(pf);
2819
2820         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2821         if (!veb) {
2822                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2823                 goto fail;
2824         }
2825
2826         veb->associate_vsi = vsi;
2827         TAILQ_INIT(&veb->head);
2828         veb->uplink_seid = vsi->uplink_seid;
2829
2830         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2831                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2832
2833         if (ret != I40E_SUCCESS) {
2834                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2835                             hw->aq.asq_last_status);
2836                 goto fail;
2837         }
2838
2839         /* get statistics index */
2840         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2841                                 &veb->stats_idx, NULL, NULL, NULL);
2842         if (ret != I40E_SUCCESS) {
2843                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2844                             hw->aq.asq_last_status);
2845                 goto fail;
2846         }
2847
2848         /* Get VEB bandwidth, to be implemented */
2849         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2850         vsi->uplink_seid = veb->seid;
2851
2852         return veb;
2853 fail:
2854         rte_free(veb);
2855         return NULL;
2856 }
2857
2858 int
2859 i40e_vsi_release(struct i40e_vsi *vsi)
2860 {
2861         struct i40e_pf *pf;
2862         struct i40e_hw *hw;
2863         struct i40e_vsi_list *vsi_list;
2864         int ret;
2865         struct i40e_mac_filter *f;
2866
2867         if (!vsi)
2868                 return I40E_SUCCESS;
2869
2870         pf = I40E_VSI_TO_PF(vsi);
2871         hw = I40E_VSI_TO_HW(vsi);
2872
2873         /* VSI has child to attach, release child first */
2874         if (vsi->veb) {
2875                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2876                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2877                                 return -1;
2878                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2879                 }
2880                 i40e_veb_release(vsi->veb);
2881         }
2882
2883         /* Remove all macvlan filters of the VSI */
2884         i40e_vsi_remove_all_macvlan_filter(vsi);
2885         TAILQ_FOREACH(f, &vsi->mac_list, next)
2886                 rte_free(f);
2887
2888         if (vsi->type != I40E_VSI_MAIN) {
2889                 /* Remove vsi from parent's sibling list */
2890                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2891                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2892                         return I40E_ERR_PARAM;
2893                 }
2894                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2895                                 &vsi->sib_vsi_list, list);
2896
2897                 /* Remove all switch element of the VSI */
2898                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2899                 if (ret != I40E_SUCCESS)
2900                         PMD_DRV_LOG(ERR, "Failed to delete element");
2901         }
2902         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2903
2904         if (vsi->type != I40E_VSI_SRIOV)
2905                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2906         rte_free(vsi);
2907
2908         return I40E_SUCCESS;
2909 }
2910
2911 static int
2912 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2913 {
2914         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2915         struct i40e_aqc_remove_macvlan_element_data def_filter;
2916         struct i40e_mac_filter_info filter;
2917         int ret;
2918
2919         if (vsi->type != I40E_VSI_MAIN)
2920                 return I40E_ERR_CONFIG;
2921         memset(&def_filter, 0, sizeof(def_filter));
2922         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2923                                         ETH_ADDR_LEN);
2924         def_filter.vlan_tag = 0;
2925         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2926                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2927         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2928         if (ret != I40E_SUCCESS) {
2929                 struct i40e_mac_filter *f;
2930                 struct ether_addr *mac;
2931
2932                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2933                             "macvlan filter");
2934                 /* It needs to add the permanent mac into mac list */
2935                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2936                 if (f == NULL) {
2937                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2938                         return I40E_ERR_NO_MEMORY;
2939                 }
2940                 mac = &f->mac_info.mac_addr;
2941                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2942                                 ETH_ADDR_LEN);
2943                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2944                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2945                 vsi->mac_num++;
2946
2947                 return ret;
2948         }
2949         (void)rte_memcpy(&filter.mac_addr,
2950                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2951         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2952         return i40e_vsi_add_mac(vsi, &filter);
2953 }
2954
2955 static int
2956 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2957 {
2958         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2959         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2960         struct i40e_hw *hw = &vsi->adapter->hw;
2961         i40e_status ret;
2962         int i;
2963
2964         memset(&bw_config, 0, sizeof(bw_config));
2965         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2966         if (ret != I40E_SUCCESS) {
2967                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2968                             hw->aq.asq_last_status);
2969                 return ret;
2970         }
2971
2972         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2973         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2974                                         &ets_sla_config, NULL);
2975         if (ret != I40E_SUCCESS) {
2976                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2977                             "configuration %u", hw->aq.asq_last_status);
2978                 return ret;
2979         }
2980
2981         /* Not store the info yet, just print out */
2982         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2983         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2984         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2985                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2986                             ets_sla_config.share_credits[i]);
2987                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2988                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2989                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2990                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2991                             (i * 4));
2992         }
2993
2994         return 0;
2995 }
2996
2997 /* Setup a VSI */
2998 struct i40e_vsi *
2999 i40e_vsi_setup(struct i40e_pf *pf,
3000                enum i40e_vsi_type type,
3001                struct i40e_vsi *uplink_vsi,
3002                uint16_t user_param)
3003 {
3004         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3005         struct i40e_vsi *vsi;
3006         struct i40e_mac_filter_info filter;
3007         int ret;
3008         struct i40e_vsi_context ctxt;
3009         struct ether_addr broadcast =
3010                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3011
3012         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3013                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3014                             "VSI link shouldn't be NULL");
3015                 return NULL;
3016         }
3017
3018         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3019                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3020                             "uplink VSI should be NULL");
3021                 return NULL;
3022         }
3023
3024         /* If uplink vsi didn't setup VEB, create one first */
3025         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3026                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3027
3028                 if (NULL == uplink_vsi->veb) {
3029                         PMD_DRV_LOG(ERR, "VEB setup failed");
3030                         return NULL;
3031                 }
3032         }
3033
3034         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3035         if (!vsi) {
3036                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3037                 return NULL;
3038         }
3039         TAILQ_INIT(&vsi->mac_list);
3040         vsi->type = type;
3041         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3042         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3043         vsi->parent_vsi = uplink_vsi;
3044         vsi->user_param = user_param;
3045         /* Allocate queues */
3046         switch (vsi->type) {
3047         case I40E_VSI_MAIN  :
3048                 vsi->nb_qps = pf->lan_nb_qps;
3049                 break;
3050         case I40E_VSI_SRIOV :
3051                 vsi->nb_qps = pf->vf_nb_qps;
3052                 break;
3053         case I40E_VSI_VMDQ2:
3054                 vsi->nb_qps = pf->vmdq_nb_qps;
3055                 break;
3056         case I40E_VSI_FDIR:
3057                 vsi->nb_qps = pf->fdir_nb_qps;
3058                 break;
3059         default:
3060                 goto fail_mem;
3061         }
3062         /*
3063          * The filter status descriptor is reported in rx queue 0,
3064          * while the tx queue for fdir filter programming has no
3065          * such constraints, can be non-zero queues.
3066          * To simplify it, choose FDIR vsi use queue 0 pair.
3067          * To make sure it will use queue 0 pair, queue allocation
3068          * need be done before this function is called
3069          */
3070         if (type != I40E_VSI_FDIR) {
3071                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3072                         if (ret < 0) {
3073                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3074                                                 vsi->seid, ret);
3075                                 goto fail_mem;
3076                         }
3077                         vsi->base_queue = ret;
3078         } else
3079                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3080
3081         /* VF has MSIX interrupt in VF range, don't allocate here */
3082         if (type != I40E_VSI_SRIOV) {
3083                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3084                 if (ret < 0) {
3085                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3086                         goto fail_queue_alloc;
3087                 }
3088                 vsi->msix_intr = ret;
3089         } else
3090                 vsi->msix_intr = 0;
3091         /* Add VSI */
3092         if (type == I40E_VSI_MAIN) {
3093                 /* For main VSI, no need to add since it's default one */
3094                 vsi->uplink_seid = pf->mac_seid;
3095                 vsi->seid = pf->main_vsi_seid;
3096                 /* Bind queues with specific MSIX interrupt */
3097                 /**
3098                  * Needs 2 interrupt at least, one for misc cause which will
3099                  * enabled from OS side, Another for queues binding the
3100                  * interrupt from device side only.
3101                  */
3102
3103                 /* Get default VSI parameters from hardware */
3104                 memset(&ctxt, 0, sizeof(ctxt));
3105                 ctxt.seid = vsi->seid;
3106                 ctxt.pf_num = hw->pf_id;
3107                 ctxt.uplink_seid = vsi->uplink_seid;
3108                 ctxt.vf_num = 0;
3109                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3110                 if (ret != I40E_SUCCESS) {
3111                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3112                         goto fail_msix_alloc;
3113                 }
3114                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3115                         sizeof(struct i40e_aqc_vsi_properties_data));
3116                 vsi->vsi_id = ctxt.vsi_number;
3117                 vsi->info.valid_sections = 0;
3118
3119                 /* Configure tc, enabled TC0 only */
3120                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3121                         I40E_SUCCESS) {
3122                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3123                         goto fail_msix_alloc;
3124                 }
3125
3126                 /* TC, queue mapping */
3127                 memset(&ctxt, 0, sizeof(ctxt));
3128                 vsi->info.valid_sections |=
3129                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3130                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3131                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3132                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3133                         sizeof(struct i40e_aqc_vsi_properties_data));
3134                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3135                                                 I40E_DEFAULT_TCMAP);
3136                 if (ret != I40E_SUCCESS) {
3137                         PMD_DRV_LOG(ERR, "Failed to configure "
3138                                     "TC queue mapping");
3139                         goto fail_msix_alloc;
3140                 }
3141                 ctxt.seid = vsi->seid;
3142                 ctxt.pf_num = hw->pf_id;
3143                 ctxt.uplink_seid = vsi->uplink_seid;
3144                 ctxt.vf_num = 0;
3145
3146                 /* Update VSI parameters */
3147                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3148                 if (ret != I40E_SUCCESS) {
3149                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3150                         goto fail_msix_alloc;
3151                 }
3152
3153                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3154                                                 sizeof(vsi->info.tc_mapping));
3155                 (void)rte_memcpy(&vsi->info.queue_mapping,
3156                                 &ctxt.info.queue_mapping,
3157                         sizeof(vsi->info.queue_mapping));
3158                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3159                 vsi->info.valid_sections = 0;
3160
3161                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3162                                 ETH_ADDR_LEN);
3163
3164                 /**
3165                  * Updating default filter settings are necessary to prevent
3166                  * reception of tagged packets.
3167                  * Some old firmware configurations load a default macvlan
3168                  * filter which accepts both tagged and untagged packets.
3169                  * The updating is to use a normal filter instead if needed.
3170                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3171                  * The firmware with correct configurations load the default
3172                  * macvlan filter which is expected and cannot be removed.
3173                  */
3174                 i40e_update_default_filter_setting(vsi);
3175                 i40e_config_qinq(hw, vsi);
3176         } else if (type == I40E_VSI_SRIOV) {
3177                 memset(&ctxt, 0, sizeof(ctxt));
3178                 /**
3179                  * For other VSI, the uplink_seid equals to uplink VSI's
3180                  * uplink_seid since they share same VEB
3181                  */
3182                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3183                 ctxt.pf_num = hw->pf_id;
3184                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3185                 ctxt.uplink_seid = vsi->uplink_seid;
3186                 ctxt.connection_type = 0x1;
3187                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3188
3189                 /**
3190                  * Do not configure switch ID to enable VEB switch by
3191                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3192                  * if the source mac address of packet sent from VF is not
3193                  * listed in the VEB's mac table, the VEB will switch the
3194                  * packet back to the VF. Need to enable it when HW issue
3195                  * is fixed.
3196                  */
3197
3198                 /* Configure port/vlan */
3199                 ctxt.info.valid_sections |=
3200                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3201                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3202                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3203                                                 I40E_DEFAULT_TCMAP);
3204                 if (ret != I40E_SUCCESS) {
3205                         PMD_DRV_LOG(ERR, "Failed to configure "
3206                                     "TC queue mapping");
3207                         goto fail_msix_alloc;
3208                 }
3209                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3210                 ctxt.info.valid_sections |=
3211                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3212                 /**
3213                  * Since VSI is not created yet, only configure parameter,
3214                  * will add vsi below.
3215                  */
3216
3217                 i40e_config_qinq(hw, vsi);
3218         } else if (type == I40E_VSI_VMDQ2) {
3219                 memset(&ctxt, 0, sizeof(ctxt));
3220                 /*
3221                  * For other VSI, the uplink_seid equals to uplink VSI's
3222                  * uplink_seid since they share same VEB
3223                  */
3224                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3225                 ctxt.pf_num = hw->pf_id;
3226                 ctxt.vf_num = 0;
3227                 ctxt.uplink_seid = vsi->uplink_seid;
3228                 ctxt.connection_type = 0x1;
3229                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3230
3231                 ctxt.info.valid_sections |=
3232                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3233                 /* user_param carries flag to enable loop back */
3234                 if (user_param) {
3235                         ctxt.info.switch_id =
3236                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3237                         ctxt.info.switch_id |=
3238                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3239                 }
3240
3241                 /* Configure port/vlan */
3242                 ctxt.info.valid_sections |=
3243                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3244                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3245                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3246                                                 I40E_DEFAULT_TCMAP);
3247                 if (ret != I40E_SUCCESS) {
3248                         PMD_DRV_LOG(ERR, "Failed to configure "
3249                                         "TC queue mapping");
3250                         goto fail_msix_alloc;
3251                 }
3252                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3253                 ctxt.info.valid_sections |=
3254                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3255         } else if (type == I40E_VSI_FDIR) {
3256                 memset(&ctxt, 0, sizeof(ctxt));
3257                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3258                 ctxt.pf_num = hw->pf_id;
3259                 ctxt.vf_num = 0;
3260                 ctxt.uplink_seid = vsi->uplink_seid;
3261                 ctxt.connection_type = 0x1;     /* regular data port */
3262                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3263                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3264                                                 I40E_DEFAULT_TCMAP);
3265                 if (ret != I40E_SUCCESS) {
3266                         PMD_DRV_LOG(ERR, "Failed to configure "
3267                                         "TC queue mapping.");
3268                         goto fail_msix_alloc;
3269                 }
3270                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3271                 ctxt.info.valid_sections |=
3272                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3273         } else {
3274                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3275                 goto fail_msix_alloc;
3276         }
3277
3278         if (vsi->type != I40E_VSI_MAIN) {
3279                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3280                 if (ret != I40E_SUCCESS) {
3281                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3282                                     hw->aq.asq_last_status);
3283                         goto fail_msix_alloc;
3284                 }
3285                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3286                 vsi->info.valid_sections = 0;
3287                 vsi->seid = ctxt.seid;
3288                 vsi->vsi_id = ctxt.vsi_number;
3289                 vsi->sib_vsi_list.vsi = vsi;
3290                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3291                                 &vsi->sib_vsi_list, list);
3292         }
3293
3294         /* MAC/VLAN configuration */
3295         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3296         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3297
3298         ret = i40e_vsi_add_mac(vsi, &filter);
3299         if (ret != I40E_SUCCESS) {
3300                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3301                 goto fail_msix_alloc;
3302         }
3303
3304         /* Get VSI BW information */
3305         i40e_vsi_dump_bw_config(vsi);
3306         return vsi;
3307 fail_msix_alloc:
3308         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3309 fail_queue_alloc:
3310         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3311 fail_mem:
3312         rte_free(vsi);
3313         return NULL;
3314 }
3315
3316 /* Configure vlan stripping on or off */
3317 int
3318 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3319 {
3320         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3321         struct i40e_vsi_context ctxt;
3322         uint8_t vlan_flags;
3323         int ret = I40E_SUCCESS;
3324
3325         /* Check if it has been already on or off */
3326         if (vsi->info.valid_sections &
3327                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3328                 if (on) {
3329                         if ((vsi->info.port_vlan_flags &
3330                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3331                                 return 0; /* already on */
3332                 } else {
3333                         if ((vsi->info.port_vlan_flags &
3334                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3335                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3336                                 return 0; /* already off */
3337                 }
3338         }
3339
3340         if (on)
3341                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3342         else
3343                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3344         vsi->info.valid_sections =
3345                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3346         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3347         vsi->info.port_vlan_flags |= vlan_flags;
3348         ctxt.seid = vsi->seid;
3349         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3350         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3351         if (ret)
3352                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3353                             on ? "enable" : "disable");
3354
3355         return ret;
3356 }
3357
3358 static int
3359 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3360 {
3361         struct rte_eth_dev_data *data = dev->data;
3362         int ret;
3363
3364         /* Apply vlan offload setting */
3365         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3366
3367         /* Apply double-vlan setting, not implemented yet */
3368
3369         /* Apply pvid setting */
3370         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3371                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3372         if (ret)
3373                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3374
3375         return ret;
3376 }
3377
3378 static int
3379 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3380 {
3381         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3382
3383         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3384 }
3385
3386 static int
3387 i40e_update_flow_control(struct i40e_hw *hw)
3388 {
3389 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3390         struct i40e_link_status link_status;
3391         uint32_t rxfc = 0, txfc = 0, reg;
3392         uint8_t an_info;
3393         int ret;
3394
3395         memset(&link_status, 0, sizeof(link_status));
3396         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3397         if (ret != I40E_SUCCESS) {
3398                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3399                 goto write_reg; /* Disable flow control */
3400         }
3401
3402         an_info = hw->phy.link_info.an_info;
3403         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3404                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3405                 ret = I40E_ERR_NOT_READY;
3406                 goto write_reg; /* Disable flow control */
3407         }
3408         /**
3409          * If link auto negotiation is enabled, flow control needs to
3410          * be configured according to it
3411          */
3412         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3413         case I40E_LINK_PAUSE_RXTX:
3414                 rxfc = 1;
3415                 txfc = 1;
3416                 hw->fc.current_mode = I40E_FC_FULL;
3417                 break;
3418         case I40E_AQ_LINK_PAUSE_RX:
3419                 rxfc = 1;
3420                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3421                 break;
3422         case I40E_AQ_LINK_PAUSE_TX:
3423                 txfc = 1;
3424                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3425                 break;
3426         default:
3427                 hw->fc.current_mode = I40E_FC_NONE;
3428                 break;
3429         }
3430
3431 write_reg:
3432         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3433                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3434         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3435         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3436         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3437         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3438
3439         return ret;
3440 }
3441
3442 /* PF setup */
3443 static int
3444 i40e_pf_setup(struct i40e_pf *pf)
3445 {
3446         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3447         struct i40e_filter_control_settings settings;
3448         struct i40e_vsi *vsi;
3449         int ret;
3450
3451         /* Clear all stats counters */
3452         pf->offset_loaded = FALSE;
3453         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3454         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3455
3456         ret = i40e_pf_get_switch_config(pf);
3457         if (ret != I40E_SUCCESS) {
3458                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3459                 return ret;
3460         }
3461         if (pf->flags & I40E_FLAG_FDIR) {
3462                 /* make queue allocated first, let FDIR use queue pair 0*/
3463                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3464                 if (ret != I40E_FDIR_QUEUE_ID) {
3465                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3466                                     " ret =%d", ret);
3467                         pf->flags &= ~I40E_FLAG_FDIR;
3468                 }
3469         }
3470         /*  main VSI setup */
3471         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3472         if (!vsi) {
3473                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3474                 return I40E_ERR_NOT_READY;
3475         }
3476         pf->main_vsi = vsi;
3477
3478         /* Configure filter control */
3479         memset(&settings, 0, sizeof(settings));
3480         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3481                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3482         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3483                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3484         else {
3485                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3486                                                 hw->func_caps.rss_table_size);
3487                 return I40E_ERR_PARAM;
3488         }
3489         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3490                         "size: %u\n", hw->func_caps.rss_table_size);
3491         pf->hash_lut_size = hw->func_caps.rss_table_size;
3492
3493         /* Enable ethtype and macvlan filters */
3494         settings.enable_ethtype = TRUE;
3495         settings.enable_macvlan = TRUE;
3496         ret = i40e_set_filter_control(hw, &settings);
3497         if (ret)
3498                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3499                                                                 ret);
3500
3501         /* Update flow control according to the auto negotiation */
3502         i40e_update_flow_control(hw);
3503
3504         return I40E_SUCCESS;
3505 }
3506
3507 int
3508 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3509 {
3510         uint32_t reg;
3511         uint16_t j;
3512
3513         /**
3514          * Set or clear TX Queue Disable flags,
3515          * which is required by hardware.
3516          */
3517         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3518         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3519
3520         /* Wait until the request is finished */
3521         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3522                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3523                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3524                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3525                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3526                                                         & 0x1))) {
3527                         break;
3528                 }
3529         }
3530         if (on) {
3531                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3532                         return I40E_SUCCESS; /* already on, skip next steps */
3533
3534                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3535                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3536         } else {
3537                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3538                         return I40E_SUCCESS; /* already off, skip next steps */
3539                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3540         }
3541         /* Write the register */
3542         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3543         /* Check the result */
3544         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3545                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3546                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3547                 if (on) {
3548                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3549                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3550                                 break;
3551                 } else {
3552                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3553                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3554                                 break;
3555                 }
3556         }
3557         /* Check if it is timeout */
3558         if (j >= I40E_CHK_Q_ENA_COUNT) {
3559                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3560                             (on ? "enable" : "disable"), q_idx);
3561                 return I40E_ERR_TIMEOUT;
3562         }
3563
3564         return I40E_SUCCESS;
3565 }
3566
3567 /* Swith on or off the tx queues */
3568 static int
3569 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3570 {
3571         struct rte_eth_dev_data *dev_data = pf->dev_data;
3572         struct i40e_tx_queue *txq;
3573         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3574         uint16_t i;
3575         int ret;
3576
3577         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3578                 txq = dev_data->tx_queues[i];
3579                 /* Don't operate the queue if not configured or
3580                  * if starting only per queue */
3581                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3582                         continue;
3583                 if (on)
3584                         ret = i40e_dev_tx_queue_start(dev, i);
3585                 else
3586                         ret = i40e_dev_tx_queue_stop(dev, i);
3587                 if ( ret != I40E_SUCCESS)
3588                         return ret;
3589         }
3590
3591         return I40E_SUCCESS;
3592 }
3593
3594 int
3595 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3596 {
3597         uint32_t reg;
3598         uint16_t j;
3599
3600         /* Wait until the request is finished */
3601         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3602                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3603                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3604                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3605                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3606                         break;
3607         }
3608
3609         if (on) {
3610                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3611                         return I40E_SUCCESS; /* Already on, skip next steps */
3612                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3613         } else {
3614                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3615                         return I40E_SUCCESS; /* Already off, skip next steps */
3616                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3617         }
3618
3619         /* Write the register */
3620         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3621         /* Check the result */
3622         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3623                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3624                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3625                 if (on) {
3626                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3627                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3628                                 break;
3629                 } else {
3630                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3631                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3632                                 break;
3633                 }
3634         }
3635
3636         /* Check if it is timeout */
3637         if (j >= I40E_CHK_Q_ENA_COUNT) {
3638                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3639                             (on ? "enable" : "disable"), q_idx);
3640                 return I40E_ERR_TIMEOUT;
3641         }
3642
3643         return I40E_SUCCESS;
3644 }
3645 /* Switch on or off the rx queues */
3646 static int
3647 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3648 {
3649         struct rte_eth_dev_data *dev_data = pf->dev_data;
3650         struct i40e_rx_queue *rxq;
3651         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3652         uint16_t i;
3653         int ret;
3654
3655         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3656                 rxq = dev_data->rx_queues[i];
3657                 /* Don't operate the queue if not configured or
3658                  * if starting only per queue */
3659                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3660                         continue;
3661                 if (on)
3662                         ret = i40e_dev_rx_queue_start(dev, i);
3663                 else
3664                         ret = i40e_dev_rx_queue_stop(dev, i);
3665                 if (ret != I40E_SUCCESS)
3666                         return ret;
3667         }
3668
3669         return I40E_SUCCESS;
3670 }
3671
3672 /* Switch on or off all the rx/tx queues */
3673 int
3674 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3675 {
3676         int ret;
3677
3678         if (on) {
3679                 /* enable rx queues before enabling tx queues */
3680                 ret = i40e_dev_switch_rx_queues(pf, on);
3681                 if (ret) {
3682                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3683                         return ret;
3684                 }
3685                 ret = i40e_dev_switch_tx_queues(pf, on);
3686         } else {
3687                 /* Stop tx queues before stopping rx queues */
3688                 ret = i40e_dev_switch_tx_queues(pf, on);
3689                 if (ret) {
3690                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3691                         return ret;
3692                 }
3693                 ret = i40e_dev_switch_rx_queues(pf, on);
3694         }
3695
3696         return ret;
3697 }
3698
3699 /* Initialize VSI for TX */
3700 static int
3701 i40e_dev_tx_init(struct i40e_pf *pf)
3702 {
3703         struct rte_eth_dev_data *data = pf->dev_data;
3704         uint16_t i;
3705         uint32_t ret = I40E_SUCCESS;
3706         struct i40e_tx_queue *txq;
3707
3708         for (i = 0; i < data->nb_tx_queues; i++) {
3709                 txq = data->tx_queues[i];
3710                 if (!txq || !txq->q_set)
3711                         continue;
3712                 ret = i40e_tx_queue_init(txq);
3713                 if (ret != I40E_SUCCESS)
3714                         break;
3715         }
3716
3717         return ret;
3718 }
3719
3720 /* Initialize VSI for RX */
3721 static int
3722 i40e_dev_rx_init(struct i40e_pf *pf)
3723 {
3724         struct rte_eth_dev_data *data = pf->dev_data;
3725         int ret = I40E_SUCCESS;
3726         uint16_t i;
3727         struct i40e_rx_queue *rxq;
3728
3729         i40e_pf_config_mq_rx(pf);
3730         for (i = 0; i < data->nb_rx_queues; i++) {
3731                 rxq = data->rx_queues[i];
3732                 if (!rxq || !rxq->q_set)
3733                         continue;
3734
3735                 ret = i40e_rx_queue_init(rxq);
3736                 if (ret != I40E_SUCCESS) {
3737                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3738                                     "initialization");
3739                         break;
3740                 }
3741         }
3742
3743         return ret;
3744 }
3745
3746 static int
3747 i40e_dev_rxtx_init(struct i40e_pf *pf)
3748 {
3749         int err;
3750
3751         err = i40e_dev_tx_init(pf);
3752         if (err) {
3753                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3754                 return err;
3755         }
3756         err = i40e_dev_rx_init(pf);
3757         if (err) {
3758                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3759                 return err;
3760         }
3761
3762         return err;
3763 }
3764
3765 static int
3766 i40e_vmdq_setup(struct rte_eth_dev *dev)
3767 {
3768         struct rte_eth_conf *conf = &dev->data->dev_conf;
3769         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3770         int i, err, conf_vsis, j, loop;
3771         struct i40e_vsi *vsi;
3772         struct i40e_vmdq_info *vmdq_info;
3773         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3774         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3775
3776         /*
3777          * Disable interrupt to avoid message from VF. Furthermore, it will
3778          * avoid race condition in VSI creation/destroy.
3779          */
3780         i40e_pf_disable_irq0(hw);
3781
3782         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3783                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3784                 return -ENOTSUP;
3785         }
3786
3787         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3788         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3789                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3790                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3791                         pf->max_nb_vmdq_vsi);
3792                 return -ENOTSUP;
3793         }
3794
3795         if (pf->vmdq != NULL) {
3796                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3797                 return 0;
3798         }
3799
3800         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3801                                 sizeof(*vmdq_info) * conf_vsis, 0);
3802
3803         if (pf->vmdq == NULL) {
3804                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3805                 return -ENOMEM;
3806         }
3807
3808         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3809
3810         /* Create VMDQ VSI */
3811         for (i = 0; i < conf_vsis; i++) {
3812                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3813                                 vmdq_conf->enable_loop_back);
3814                 if (vsi == NULL) {
3815                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3816                         err = -1;
3817                         goto err_vsi_setup;
3818                 }
3819                 vmdq_info = &pf->vmdq[i];
3820                 vmdq_info->pf = pf;
3821                 vmdq_info->vsi = vsi;
3822         }
3823         pf->nb_cfg_vmdq_vsi = conf_vsis;
3824
3825         /* Configure Vlan */
3826         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3827         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3828                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3829                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3830                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3831                                         vmdq_conf->pool_map[i].vlan_id, j);
3832
3833                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3834                                                 vmdq_conf->pool_map[i].vlan_id);
3835                                 if (err) {
3836                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3837                                         err = -1;
3838                                         goto err_vsi_setup;
3839                                 }
3840                         }
3841                 }
3842         }
3843
3844         i40e_pf_enable_irq0(hw);
3845
3846         return 0;
3847
3848 err_vsi_setup:
3849         for (i = 0; i < conf_vsis; i++)
3850                 if (pf->vmdq[i].vsi == NULL)
3851                         break;
3852                 else
3853                         i40e_vsi_release(pf->vmdq[i].vsi);
3854
3855         rte_free(pf->vmdq);
3856         pf->vmdq = NULL;
3857         i40e_pf_enable_irq0(hw);
3858         return err;
3859 }
3860
3861 static void
3862 i40e_stat_update_32(struct i40e_hw *hw,
3863                    uint32_t reg,
3864                    bool offset_loaded,
3865                    uint64_t *offset,
3866                    uint64_t *stat)
3867 {
3868         uint64_t new_data;
3869
3870         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3871         if (!offset_loaded)
3872                 *offset = new_data;
3873
3874         if (new_data >= *offset)
3875                 *stat = (uint64_t)(new_data - *offset);
3876         else
3877                 *stat = (uint64_t)((new_data +
3878                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3879 }
3880
3881 static void
3882 i40e_stat_update_48(struct i40e_hw *hw,
3883                    uint32_t hireg,
3884                    uint32_t loreg,
3885                    bool offset_loaded,
3886                    uint64_t *offset,
3887                    uint64_t *stat)
3888 {
3889         uint64_t new_data;
3890
3891         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3892         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3893                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3894
3895         if (!offset_loaded)
3896                 *offset = new_data;
3897
3898         if (new_data >= *offset)
3899                 *stat = new_data - *offset;
3900         else
3901                 *stat = (uint64_t)((new_data +
3902                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3903
3904         *stat &= I40E_48_BIT_MASK;
3905 }
3906
3907 /* Disable IRQ0 */
3908 void
3909 i40e_pf_disable_irq0(struct i40e_hw *hw)
3910 {
3911         /* Disable all interrupt types */
3912         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3913         I40E_WRITE_FLUSH(hw);
3914 }
3915
3916 /* Enable IRQ0 */
3917 void
3918 i40e_pf_enable_irq0(struct i40e_hw *hw)
3919 {
3920         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3921                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3922                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3923                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3924         I40E_WRITE_FLUSH(hw);
3925 }
3926
3927 static void
3928 i40e_pf_config_irq0(struct i40e_hw *hw)
3929 {
3930         /* read pending request and disable first */
3931         i40e_pf_disable_irq0(hw);
3932         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3933         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3934                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3935
3936         /* Link no queues with irq0 */
3937         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3938                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3939 }
3940
3941 static void
3942 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3943 {
3944         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3945         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3946         int i;
3947         uint16_t abs_vf_id;
3948         uint32_t index, offset, val;
3949
3950         if (!pf->vfs)
3951                 return;
3952         /**
3953          * Try to find which VF trigger a reset, use absolute VF id to access
3954          * since the reg is global register.
3955          */
3956         for (i = 0; i < pf->vf_num; i++) {
3957                 abs_vf_id = hw->func_caps.vf_base_id + i;
3958                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3959                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3960                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3961                 /* VFR event occured */
3962                 if (val & (0x1 << offset)) {
3963                         int ret;
3964
3965                         /* Clear the event first */
3966                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3967                                                         (0x1 << offset));
3968                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3969                         /**
3970                          * Only notify a VF reset event occured,
3971                          * don't trigger another SW reset
3972                          */
3973                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3974                         if (ret != I40E_SUCCESS)
3975                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3976                 }
3977         }
3978 }
3979
3980 static void
3981 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3982 {
3983         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3984         struct i40e_arq_event_info info;
3985         uint16_t pending, opcode;
3986         int ret;
3987
3988         info.buf_len = I40E_AQ_BUF_SZ;
3989         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3990         if (!info.msg_buf) {
3991                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3992                 return;
3993         }
3994
3995         pending = 1;
3996         while (pending) {
3997                 ret = i40e_clean_arq_element(hw, &info, &pending);
3998
3999                 if (ret != I40E_SUCCESS) {
4000                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4001                                     "aq_err: %u", hw->aq.asq_last_status);
4002                         break;
4003                 }
4004                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4005
4006                 switch (opcode) {
4007                 case i40e_aqc_opc_send_msg_to_pf:
4008                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4009                         i40e_pf_host_handle_vf_msg(dev,
4010                                         rte_le_to_cpu_16(info.desc.retval),
4011                                         rte_le_to_cpu_32(info.desc.cookie_high),
4012                                         rte_le_to_cpu_32(info.desc.cookie_low),
4013                                         info.msg_buf,
4014                                         info.msg_len);
4015                         break;
4016                 default:
4017                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4018                                     opcode);
4019                         break;
4020                 }
4021         }
4022         rte_free(info.msg_buf);
4023 }
4024
4025 /*
4026  * Interrupt handler is registered as the alarm callback for handling LSC
4027  * interrupt in a definite of time, in order to wait the NIC into a stable
4028  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4029  * no need for link down interrupt.
4030  */
4031 static void
4032 i40e_dev_interrupt_delayed_handler(void *param)
4033 {
4034         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4035         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4036         uint32_t icr0;
4037
4038         /* read interrupt causes again */
4039         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4040
4041 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4042         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4043                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4044         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4045                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4046         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4047                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4048         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4049                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4050         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4051                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4052                                                                 "state\n");
4053         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4054                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4055         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4056                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4057 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4058
4059         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4060                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4061                 i40e_dev_handle_vfr_event(dev);
4062         }
4063         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4064                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4065                 i40e_dev_handle_aq_msg(dev);
4066         }
4067
4068         /* handle the link up interrupt in an alarm callback */
4069         i40e_dev_link_update(dev, 0);
4070         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4071
4072         i40e_pf_enable_irq0(hw);
4073         rte_intr_enable(&(dev->pci_dev->intr_handle));
4074 }
4075
4076 /**
4077  * Interrupt handler triggered by NIC  for handling
4078  * specific interrupt.
4079  *
4080  * @param handle
4081  *  Pointer to interrupt handle.
4082  * @param param
4083  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4084  *
4085  * @return
4086  *  void
4087  */
4088 static void
4089 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4090                            void *param)
4091 {
4092         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4093         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4094         uint32_t icr0;
4095
4096         /* Disable interrupt */
4097         i40e_pf_disable_irq0(hw);
4098
4099         /* read out interrupt causes */
4100         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4101
4102         /* No interrupt event indicated */
4103         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4104                 PMD_DRV_LOG(INFO, "No interrupt event");
4105                 goto done;
4106         }
4107 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4108         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4109                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4110         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4111                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4112         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4113                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4114         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4115                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4116         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4117                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4118         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4119                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4120         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4121                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4122 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4123
4124         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4125                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4126                 i40e_dev_handle_vfr_event(dev);
4127         }
4128         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4129                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4130                 i40e_dev_handle_aq_msg(dev);
4131         }
4132
4133         /* Link Status Change interrupt */
4134         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4135 #define I40E_US_PER_SECOND 1000000
4136                 struct rte_eth_link link;
4137
4138                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4139                 memset(&link, 0, sizeof(link));
4140                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4141                 i40e_dev_link_update(dev, 0);
4142
4143                 /*
4144                  * For link up interrupt, it needs to wait 1 second to let the
4145                  * hardware be a stable state. Otherwise several consecutive
4146                  * interrupts can be observed.
4147                  * For link down interrupt, no need to wait.
4148                  */
4149                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4150                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4151                         return;
4152                 else
4153                         _rte_eth_dev_callback_process(dev,
4154                                 RTE_ETH_EVENT_INTR_LSC);
4155         }
4156
4157 done:
4158         /* Enable interrupt */
4159         i40e_pf_enable_irq0(hw);
4160         rte_intr_enable(&(dev->pci_dev->intr_handle));
4161 }
4162
4163 static int
4164 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4165                          struct i40e_macvlan_filter *filter,
4166                          int total)
4167 {
4168         int ele_num, ele_buff_size;
4169         int num, actual_num, i;
4170         uint16_t flags;
4171         int ret = I40E_SUCCESS;
4172         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4173         struct i40e_aqc_add_macvlan_element_data *req_list;
4174
4175         if (filter == NULL  || total == 0)
4176                 return I40E_ERR_PARAM;
4177         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4178         ele_buff_size = hw->aq.asq_buf_size;
4179
4180         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4181         if (req_list == NULL) {
4182                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4183                 return I40E_ERR_NO_MEMORY;
4184         }
4185
4186         num = 0;
4187         do {
4188                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4189                 memset(req_list, 0, ele_buff_size);
4190
4191                 for (i = 0; i < actual_num; i++) {
4192                         (void)rte_memcpy(req_list[i].mac_addr,
4193                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4194                         req_list[i].vlan_tag =
4195                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4196
4197                         switch (filter[num + i].filter_type) {
4198                         case RTE_MAC_PERFECT_MATCH:
4199                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4200                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4201                                 break;
4202                         case RTE_MACVLAN_PERFECT_MATCH:
4203                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4204                                 break;
4205                         case RTE_MAC_HASH_MATCH:
4206                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4207                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4208                                 break;
4209                         case RTE_MACVLAN_HASH_MATCH:
4210                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4211                                 break;
4212                         default:
4213                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4214                                 ret = I40E_ERR_PARAM;
4215                                 goto DONE;
4216                         }
4217
4218                         req_list[i].queue_number = 0;
4219
4220                         req_list[i].flags = rte_cpu_to_le_16(flags);
4221                 }
4222
4223                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4224                                                 actual_num, NULL);
4225                 if (ret != I40E_SUCCESS) {
4226                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4227                         goto DONE;
4228                 }
4229                 num += actual_num;
4230         } while (num < total);
4231
4232 DONE:
4233         rte_free(req_list);
4234         return ret;
4235 }
4236
4237 static int
4238 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4239                             struct i40e_macvlan_filter *filter,
4240                             int total)
4241 {
4242         int ele_num, ele_buff_size;
4243         int num, actual_num, i;
4244         uint16_t flags;
4245         int ret = I40E_SUCCESS;
4246         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4247         struct i40e_aqc_remove_macvlan_element_data *req_list;
4248
4249         if (filter == NULL  || total == 0)
4250                 return I40E_ERR_PARAM;
4251
4252         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4253         ele_buff_size = hw->aq.asq_buf_size;
4254
4255         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4256         if (req_list == NULL) {
4257                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4258                 return I40E_ERR_NO_MEMORY;
4259         }
4260
4261         num = 0;
4262         do {
4263                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4264                 memset(req_list, 0, ele_buff_size);
4265
4266                 for (i = 0; i < actual_num; i++) {
4267                         (void)rte_memcpy(req_list[i].mac_addr,
4268                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4269                         req_list[i].vlan_tag =
4270                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4271
4272                         switch (filter[num + i].filter_type) {
4273                         case RTE_MAC_PERFECT_MATCH:
4274                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4275                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4276                                 break;
4277                         case RTE_MACVLAN_PERFECT_MATCH:
4278                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4279                                 break;
4280                         case RTE_MAC_HASH_MATCH:
4281                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4282                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4283                                 break;
4284                         case RTE_MACVLAN_HASH_MATCH:
4285                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4286                                 break;
4287                         default:
4288                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4289                                 ret = I40E_ERR_PARAM;
4290                                 goto DONE;
4291                         }
4292                         req_list[i].flags = rte_cpu_to_le_16(flags);
4293                 }
4294
4295                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4296                                                 actual_num, NULL);
4297                 if (ret != I40E_SUCCESS) {
4298                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4299                         goto DONE;
4300                 }
4301                 num += actual_num;
4302         } while (num < total);
4303
4304 DONE:
4305         rte_free(req_list);
4306         return ret;
4307 }
4308
4309 /* Find out specific MAC filter */
4310 static struct i40e_mac_filter *
4311 i40e_find_mac_filter(struct i40e_vsi *vsi,
4312                          struct ether_addr *macaddr)
4313 {
4314         struct i40e_mac_filter *f;
4315
4316         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4317                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4318                         return f;
4319         }
4320
4321         return NULL;
4322 }
4323
4324 static bool
4325 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4326                          uint16_t vlan_id)
4327 {
4328         uint32_t vid_idx, vid_bit;
4329
4330         if (vlan_id > ETH_VLAN_ID_MAX)
4331                 return 0;
4332
4333         vid_idx = I40E_VFTA_IDX(vlan_id);
4334         vid_bit = I40E_VFTA_BIT(vlan_id);
4335
4336         if (vsi->vfta[vid_idx] & vid_bit)
4337                 return 1;
4338         else
4339                 return 0;
4340 }
4341
4342 static void
4343 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4344                          uint16_t vlan_id, bool on)
4345 {
4346         uint32_t vid_idx, vid_bit;
4347
4348         if (vlan_id > ETH_VLAN_ID_MAX)
4349                 return;
4350
4351         vid_idx = I40E_VFTA_IDX(vlan_id);
4352         vid_bit = I40E_VFTA_BIT(vlan_id);
4353
4354         if (on)
4355                 vsi->vfta[vid_idx] |= vid_bit;
4356         else
4357                 vsi->vfta[vid_idx] &= ~vid_bit;
4358 }
4359
4360 /**
4361  * Find all vlan options for specific mac addr,
4362  * return with actual vlan found.
4363  */
4364 static inline int
4365 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4366                            struct i40e_macvlan_filter *mv_f,
4367                            int num, struct ether_addr *addr)
4368 {
4369         int i;
4370         uint32_t j, k;
4371
4372         /**
4373          * Not to use i40e_find_vlan_filter to decrease the loop time,
4374          * although the code looks complex.
4375           */
4376         if (num < vsi->vlan_num)
4377                 return I40E_ERR_PARAM;
4378
4379         i = 0;
4380         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4381                 if (vsi->vfta[j]) {
4382                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4383                                 if (vsi->vfta[j] & (1 << k)) {
4384                                         if (i > num - 1) {
4385                                                 PMD_DRV_LOG(ERR, "vlan number "
4386                                                             "not match");
4387                                                 return I40E_ERR_PARAM;
4388                                         }
4389                                         (void)rte_memcpy(&mv_f[i].macaddr,
4390                                                         addr, ETH_ADDR_LEN);
4391                                         mv_f[i].vlan_id =
4392                                                 j * I40E_UINT32_BIT_SIZE + k;
4393                                         i++;
4394                                 }
4395                         }
4396                 }
4397         }
4398         return I40E_SUCCESS;
4399 }
4400
4401 static inline int
4402 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4403                            struct i40e_macvlan_filter *mv_f,
4404                            int num,
4405                            uint16_t vlan)
4406 {
4407         int i = 0;
4408         struct i40e_mac_filter *f;
4409
4410         if (num < vsi->mac_num)
4411                 return I40E_ERR_PARAM;
4412
4413         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4414                 if (i > num - 1) {
4415                         PMD_DRV_LOG(ERR, "buffer number not match");
4416                         return I40E_ERR_PARAM;
4417                 }
4418                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4419                                 ETH_ADDR_LEN);
4420                 mv_f[i].vlan_id = vlan;
4421                 mv_f[i].filter_type = f->mac_info.filter_type;
4422                 i++;
4423         }
4424
4425         return I40E_SUCCESS;
4426 }
4427
4428 static int
4429 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4430 {
4431         int i, num;
4432         struct i40e_mac_filter *f;
4433         struct i40e_macvlan_filter *mv_f;
4434         int ret = I40E_SUCCESS;
4435
4436         if (vsi == NULL || vsi->mac_num == 0)
4437                 return I40E_ERR_PARAM;
4438
4439         /* Case that no vlan is set */
4440         if (vsi->vlan_num == 0)
4441                 num = vsi->mac_num;
4442         else
4443                 num = vsi->mac_num * vsi->vlan_num;
4444
4445         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4446         if (mv_f == NULL) {
4447                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4448                 return I40E_ERR_NO_MEMORY;
4449         }
4450
4451         i = 0;
4452         if (vsi->vlan_num == 0) {
4453                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4454                         (void)rte_memcpy(&mv_f[i].macaddr,
4455                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4456                         mv_f[i].vlan_id = 0;
4457                         i++;
4458                 }
4459         } else {
4460                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4461                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4462                                         vsi->vlan_num, &f->mac_info.mac_addr);
4463                         if (ret != I40E_SUCCESS)
4464                                 goto DONE;
4465                         i += vsi->vlan_num;
4466                 }
4467         }
4468
4469         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4470 DONE:
4471         rte_free(mv_f);
4472
4473         return ret;
4474 }
4475
4476 int
4477 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4478 {
4479         struct i40e_macvlan_filter *mv_f;
4480         int mac_num;
4481         int ret = I40E_SUCCESS;
4482
4483         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4484                 return I40E_ERR_PARAM;
4485
4486         /* If it's already set, just return */
4487         if (i40e_find_vlan_filter(vsi,vlan))
4488                 return I40E_SUCCESS;
4489
4490         mac_num = vsi->mac_num;
4491
4492         if (mac_num == 0) {
4493                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4494                 return I40E_ERR_PARAM;
4495         }
4496
4497         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4498
4499         if (mv_f == NULL) {
4500                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4501                 return I40E_ERR_NO_MEMORY;
4502         }
4503
4504         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4505
4506         if (ret != I40E_SUCCESS)
4507                 goto DONE;
4508
4509         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4510
4511         if (ret != I40E_SUCCESS)
4512                 goto DONE;
4513
4514         i40e_set_vlan_filter(vsi, vlan, 1);
4515
4516         vsi->vlan_num++;
4517         ret = I40E_SUCCESS;
4518 DONE:
4519         rte_free(mv_f);
4520         return ret;
4521 }
4522
4523 int
4524 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4525 {
4526         struct i40e_macvlan_filter *mv_f;
4527         int mac_num;
4528         int ret = I40E_SUCCESS;
4529
4530         /**
4531          * Vlan 0 is the generic filter for untagged packets
4532          * and can't be removed.
4533          */
4534         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4535                 return I40E_ERR_PARAM;
4536
4537         /* If can't find it, just return */
4538         if (!i40e_find_vlan_filter(vsi, vlan))
4539                 return I40E_ERR_PARAM;
4540
4541         mac_num = vsi->mac_num;
4542
4543         if (mac_num == 0) {
4544                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4545                 return I40E_ERR_PARAM;
4546         }
4547
4548         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4549
4550         if (mv_f == NULL) {
4551                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4552                 return I40E_ERR_NO_MEMORY;
4553         }
4554
4555         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4556
4557         if (ret != I40E_SUCCESS)
4558                 goto DONE;
4559
4560         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4561
4562         if (ret != I40E_SUCCESS)
4563                 goto DONE;
4564
4565         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4566         if (vsi->vlan_num == 1) {
4567                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4568                 if (ret != I40E_SUCCESS)
4569                         goto DONE;
4570
4571                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4572                 if (ret != I40E_SUCCESS)
4573                         goto DONE;
4574         }
4575
4576         i40e_set_vlan_filter(vsi, vlan, 0);
4577
4578         vsi->vlan_num--;
4579         ret = I40E_SUCCESS;
4580 DONE:
4581         rte_free(mv_f);
4582         return ret;
4583 }
4584
4585 int
4586 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4587 {
4588         struct i40e_mac_filter *f;
4589         struct i40e_macvlan_filter *mv_f;
4590         int i, vlan_num = 0;
4591         int ret = I40E_SUCCESS;
4592
4593         /* If it's add and we've config it, return */
4594         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4595         if (f != NULL)
4596                 return I40E_SUCCESS;
4597         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4598                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4599
4600                 /**
4601                  * If vlan_num is 0, that's the first time to add mac,
4602                  * set mask for vlan_id 0.
4603                  */
4604                 if (vsi->vlan_num == 0) {
4605                         i40e_set_vlan_filter(vsi, 0, 1);
4606                         vsi->vlan_num = 1;
4607                 }
4608                 vlan_num = vsi->vlan_num;
4609         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4610                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4611                 vlan_num = 1;
4612
4613         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4614         if (mv_f == NULL) {
4615                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4616                 return I40E_ERR_NO_MEMORY;
4617         }
4618
4619         for (i = 0; i < vlan_num; i++) {
4620                 mv_f[i].filter_type = mac_filter->filter_type;
4621                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4622                                 ETH_ADDR_LEN);
4623         }
4624
4625         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4626                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4627                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4628                                         &mac_filter->mac_addr);
4629                 if (ret != I40E_SUCCESS)
4630                         goto DONE;
4631         }
4632
4633         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4634         if (ret != I40E_SUCCESS)
4635                 goto DONE;
4636
4637         /* Add the mac addr into mac list */
4638         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4639         if (f == NULL) {
4640                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4641                 ret = I40E_ERR_NO_MEMORY;
4642                 goto DONE;
4643         }
4644         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4645                         ETH_ADDR_LEN);
4646         f->mac_info.filter_type = mac_filter->filter_type;
4647         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4648         vsi->mac_num++;
4649
4650         ret = I40E_SUCCESS;
4651 DONE:
4652         rte_free(mv_f);
4653
4654         return ret;
4655 }
4656
4657 int
4658 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4659 {
4660         struct i40e_mac_filter *f;
4661         struct i40e_macvlan_filter *mv_f;
4662         int i, vlan_num;
4663         enum rte_mac_filter_type filter_type;
4664         int ret = I40E_SUCCESS;
4665
4666         /* Can't find it, return an error */
4667         f = i40e_find_mac_filter(vsi, addr);
4668         if (f == NULL)
4669                 return I40E_ERR_PARAM;
4670
4671         vlan_num = vsi->vlan_num;
4672         filter_type = f->mac_info.filter_type;
4673         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4674                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4675                 if (vlan_num == 0) {
4676                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4677                         return I40E_ERR_PARAM;
4678                 }
4679         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4680                         filter_type == RTE_MAC_HASH_MATCH)
4681                 vlan_num = 1;
4682
4683         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4684         if (mv_f == NULL) {
4685                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4686                 return I40E_ERR_NO_MEMORY;
4687         }
4688
4689         for (i = 0; i < vlan_num; i++) {
4690                 mv_f[i].filter_type = filter_type;
4691                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4692                                 ETH_ADDR_LEN);
4693         }
4694         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4695                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4696                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4697                 if (ret != I40E_SUCCESS)
4698                         goto DONE;
4699         }
4700
4701         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4702         if (ret != I40E_SUCCESS)
4703                 goto DONE;
4704
4705         /* Remove the mac addr into mac list */
4706         TAILQ_REMOVE(&vsi->mac_list, f, next);
4707         rte_free(f);
4708         vsi->mac_num--;
4709
4710         ret = I40E_SUCCESS;
4711 DONE:
4712         rte_free(mv_f);
4713         return ret;
4714 }
4715
4716 /* Configure hash enable flags for RSS */
4717 uint64_t
4718 i40e_config_hena(uint64_t flags)
4719 {
4720         uint64_t hena = 0;
4721
4722         if (!flags)
4723                 return hena;
4724
4725         if (flags & ETH_RSS_FRAG_IPV4)
4726                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4727         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4728                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4729         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4730                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4731         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4732                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4733         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4734                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4735         if (flags & ETH_RSS_FRAG_IPV6)
4736                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4737         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4738                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4739         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4740                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4741         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4742                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4743         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4744                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4745         if (flags & ETH_RSS_L2_PAYLOAD)
4746                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4747
4748         return hena;
4749 }
4750
4751 /* Parse the hash enable flags */
4752 uint64_t
4753 i40e_parse_hena(uint64_t flags)
4754 {
4755         uint64_t rss_hf = 0;
4756
4757         if (!flags)
4758                 return rss_hf;
4759         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4760                 rss_hf |= ETH_RSS_FRAG_IPV4;
4761         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4762                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4763         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4764                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4765         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4766                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4767         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4768                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4769         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4770                 rss_hf |= ETH_RSS_FRAG_IPV6;
4771         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4772                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4773         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4774                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4775         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4776                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4777         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4778                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4779         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4780                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4781
4782         return rss_hf;
4783 }
4784
4785 /* Disable RSS */
4786 static void
4787 i40e_pf_disable_rss(struct i40e_pf *pf)
4788 {
4789         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4790         uint64_t hena;
4791
4792         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4793         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4794         hena &= ~I40E_RSS_HENA_ALL;
4795         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4796         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4797         I40E_WRITE_FLUSH(hw);
4798 }
4799
4800 static int
4801 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4802 {
4803         uint32_t *hash_key;
4804         uint8_t hash_key_len;
4805         uint64_t rss_hf;
4806         uint16_t i;
4807         uint64_t hena;
4808
4809         hash_key = (uint32_t *)(rss_conf->rss_key);
4810         hash_key_len = rss_conf->rss_key_len;
4811         if (hash_key != NULL && hash_key_len >=
4812                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4813                 /* Fill in RSS hash key */
4814                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4815                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4816         }
4817
4818         rss_hf = rss_conf->rss_hf;
4819         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4820         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4821         hena &= ~I40E_RSS_HENA_ALL;
4822         hena |= i40e_config_hena(rss_hf);
4823         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4824         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4825         I40E_WRITE_FLUSH(hw);
4826
4827         return 0;
4828 }
4829
4830 static int
4831 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4832                          struct rte_eth_rss_conf *rss_conf)
4833 {
4834         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4835         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4836         uint64_t hena;
4837
4838         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4839         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4840         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4841                 if (rss_hf != 0) /* Enable RSS */
4842                         return -EINVAL;
4843                 return 0; /* Nothing to do */
4844         }
4845         /* RSS enabled */
4846         if (rss_hf == 0) /* Disable RSS */
4847                 return -EINVAL;
4848
4849         return i40e_hw_rss_hash_set(hw, rss_conf);
4850 }
4851
4852 static int
4853 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4854                            struct rte_eth_rss_conf *rss_conf)
4855 {
4856         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4857         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4858         uint64_t hena;
4859         uint16_t i;
4860
4861         if (hash_key != NULL) {
4862                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4863                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4864                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4865         }
4866         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4867         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4868         rss_conf->rss_hf = i40e_parse_hena(hena);
4869
4870         return 0;
4871 }
4872
4873 static int
4874 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4875 {
4876         switch (filter_type) {
4877         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4878                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4879                 break;
4880         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4881                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4882                 break;
4883         case RTE_TUNNEL_FILTER_IMAC_TENID:
4884                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4885                 break;
4886         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4887                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4888                 break;
4889         case ETH_TUNNEL_FILTER_IMAC:
4890                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4891                 break;
4892         default:
4893                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4894                 return -EINVAL;
4895         }
4896
4897         return 0;
4898 }
4899
4900 static int
4901 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4902                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4903                         uint8_t add)
4904 {
4905         uint16_t ip_type;
4906         uint8_t tun_type = 0;
4907         int val, ret = 0;
4908         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4909         struct i40e_vsi *vsi = pf->main_vsi;
4910         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4911         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4912
4913         cld_filter = rte_zmalloc("tunnel_filter",
4914                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4915                 0);
4916
4917         if (NULL == cld_filter) {
4918                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4919                 return -EINVAL;
4920         }
4921         pfilter = cld_filter;
4922
4923         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4924                         sizeof(struct ether_addr));
4925         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4926                         sizeof(struct ether_addr));
4927
4928         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4929         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4930                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4931                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4932                                 &tunnel_filter->ip_addr,
4933                                 sizeof(pfilter->ipaddr.v4.data));
4934         } else {
4935                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4936                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4937                                 &tunnel_filter->ip_addr,
4938                                 sizeof(pfilter->ipaddr.v6.data));
4939         }
4940
4941         /* check tunneled type */
4942         switch (tunnel_filter->tunnel_type) {
4943         case RTE_TUNNEL_TYPE_VXLAN:
4944                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4945                 break;
4946         case RTE_TUNNEL_TYPE_NVGRE:
4947                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
4948                 break;
4949         default:
4950                 /* Other tunnel types is not supported. */
4951                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4952                 rte_free(cld_filter);
4953                 return -EINVAL;
4954         }
4955
4956         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4957                                                 &pfilter->flags);
4958         if (val < 0) {
4959                 rte_free(cld_filter);
4960                 return -EINVAL;
4961         }
4962
4963         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4964                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4965         pfilter->tenant_id = tunnel_filter->tenant_id;
4966         pfilter->queue_number = tunnel_filter->queue_id;
4967
4968         if (add)
4969                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4970         else
4971                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4972                                                 cld_filter, 1);
4973
4974         rte_free(cld_filter);
4975         return ret;
4976 }
4977
4978 static int
4979 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4980 {
4981         uint8_t i;
4982
4983         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4984                 if (pf->vxlan_ports[i] == port)
4985                         return i;
4986         }
4987
4988         return -1;
4989 }
4990
4991 static int
4992 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4993 {
4994         int  idx, ret;
4995         uint8_t filter_idx;
4996         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4997
4998         idx = i40e_get_vxlan_port_idx(pf, port);
4999
5000         /* Check if port already exists */
5001         if (idx >= 0) {
5002                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5003                 return -EINVAL;
5004         }
5005
5006         /* Now check if there is space to add the new port */
5007         idx = i40e_get_vxlan_port_idx(pf, 0);
5008         if (idx < 0) {
5009                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5010                         "not adding port %d", port);
5011                 return -ENOSPC;
5012         }
5013
5014         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5015                                         &filter_idx, NULL);
5016         if (ret < 0) {
5017                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5018                 return -1;
5019         }
5020
5021         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5022                          port,  filter_idx);
5023
5024         /* New port: add it and mark its index in the bitmap */
5025         pf->vxlan_ports[idx] = port;
5026         pf->vxlan_bitmap |= (1 << idx);
5027
5028         if (!(pf->flags & I40E_FLAG_VXLAN))
5029                 pf->flags |= I40E_FLAG_VXLAN;
5030
5031         return 0;
5032 }
5033
5034 static int
5035 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5036 {
5037         int idx;
5038         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5039
5040         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5041                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5042                 return -EINVAL;
5043         }
5044
5045         idx = i40e_get_vxlan_port_idx(pf, port);
5046
5047         if (idx < 0) {
5048                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5049                 return -EINVAL;
5050         }
5051
5052         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5053                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5054                 return -1;
5055         }
5056
5057         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5058                         port, idx);
5059
5060         pf->vxlan_ports[idx] = 0;
5061         pf->vxlan_bitmap &= ~(1 << idx);
5062
5063         if (!pf->vxlan_bitmap)
5064                 pf->flags &= ~I40E_FLAG_VXLAN;
5065
5066         return 0;
5067 }
5068
5069 /* Add UDP tunneling port */
5070 static int
5071 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5072                         struct rte_eth_udp_tunnel *udp_tunnel)
5073 {
5074         int ret = 0;
5075         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5076
5077         if (udp_tunnel == NULL)
5078                 return -EINVAL;
5079
5080         switch (udp_tunnel->prot_type) {
5081         case RTE_TUNNEL_TYPE_VXLAN:
5082                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5083                 break;
5084
5085         case RTE_TUNNEL_TYPE_GENEVE:
5086         case RTE_TUNNEL_TYPE_TEREDO:
5087                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5088                 ret = -1;
5089                 break;
5090
5091         default:
5092                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5093                 ret = -1;
5094                 break;
5095         }
5096
5097         return ret;
5098 }
5099
5100 /* Remove UDP tunneling port */
5101 static int
5102 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5103                         struct rte_eth_udp_tunnel *udp_tunnel)
5104 {
5105         int ret = 0;
5106         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5107
5108         if (udp_tunnel == NULL)
5109                 return -EINVAL;
5110
5111         switch (udp_tunnel->prot_type) {
5112         case RTE_TUNNEL_TYPE_VXLAN:
5113                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5114                 break;
5115         case RTE_TUNNEL_TYPE_GENEVE:
5116         case RTE_TUNNEL_TYPE_TEREDO:
5117                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5118                 ret = -1;
5119                 break;
5120         default:
5121                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5122                 ret = -1;
5123                 break;
5124         }
5125
5126         return ret;
5127 }
5128
5129 /* Calculate the maximum number of contiguous PF queues that are configured */
5130 static int
5131 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5132 {
5133         struct rte_eth_dev_data *data = pf->dev_data;
5134         int i, num;
5135         struct i40e_rx_queue *rxq;
5136
5137         num = 0;
5138         for (i = 0; i < pf->lan_nb_qps; i++) {
5139                 rxq = data->rx_queues[i];
5140                 if (rxq && rxq->q_set)
5141                         num++;
5142                 else
5143                         break;
5144         }
5145
5146         return num;
5147 }
5148
5149 /* Configure RSS */
5150 static int
5151 i40e_pf_config_rss(struct i40e_pf *pf)
5152 {
5153         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5154         struct rte_eth_rss_conf rss_conf;
5155         uint32_t i, lut = 0;
5156         uint16_t j, num;
5157
5158         /*
5159          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5160          * It's necessary to calulate the actual PF queues that are configured.
5161          */
5162         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5163                 num = i40e_pf_calc_configured_queues_num(pf);
5164                 num = i40e_align_floor(num);
5165         } else
5166                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5167
5168         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5169                         num);
5170
5171         if (num == 0) {
5172                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5173                 return -ENOTSUP;
5174         }
5175
5176         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5177                 if (j == num)
5178                         j = 0;
5179                 lut = (lut << 8) | (j & ((0x1 <<
5180                         hw->func_caps.rss_table_entry_width) - 1));
5181                 if ((i & 3) == 3)
5182                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5183         }
5184
5185         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5186         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5187                 i40e_pf_disable_rss(pf);
5188                 return 0;
5189         }
5190         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5191                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5192                 /* Random default keys */
5193                 static uint32_t rss_key_default[] = {0x6b793944,
5194                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5195                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5196                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5197
5198                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5199                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5200                                                         sizeof(uint32_t);
5201         }
5202
5203         return i40e_hw_rss_hash_set(hw, &rss_conf);
5204 }
5205
5206 static int
5207 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5208                         struct rte_eth_tunnel_filter_conf *filter)
5209 {
5210         if (pf == NULL || filter == NULL) {
5211                 PMD_DRV_LOG(ERR, "Invalid parameter");
5212                 return -EINVAL;
5213         }
5214
5215         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5216                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5217                 return -EINVAL;
5218         }
5219
5220         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5221                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5222                 return -EINVAL;
5223         }
5224
5225         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5226                 (is_zero_ether_addr(filter->outer_mac))) {
5227                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5228                 return -EINVAL;
5229         }
5230
5231         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5232                 (is_zero_ether_addr(filter->inner_mac))) {
5233                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5234                 return -EINVAL;
5235         }
5236
5237         return 0;
5238 }
5239
5240 static int
5241 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5242                         void *arg)
5243 {
5244         struct rte_eth_tunnel_filter_conf *filter;
5245         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5246         int ret = I40E_SUCCESS;
5247
5248         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5249
5250         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5251                 return I40E_ERR_PARAM;
5252
5253         switch (filter_op) {
5254         case RTE_ETH_FILTER_NOP:
5255                 if (!(pf->flags & I40E_FLAG_VXLAN))
5256                         ret = I40E_NOT_SUPPORTED;
5257         case RTE_ETH_FILTER_ADD:
5258                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5259                 break;
5260         case RTE_ETH_FILTER_DELETE:
5261                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5262                 break;
5263         default:
5264                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5265                 ret = I40E_ERR_PARAM;
5266                 break;
5267         }
5268
5269         return ret;
5270 }
5271
5272 static int
5273 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5274 {
5275         int ret = 0;
5276         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5277
5278         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5279                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5280                 return -ENOTSUP;
5281         }
5282
5283         /* RSS setup */
5284         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5285                 ret = i40e_pf_config_rss(pf);
5286         else
5287                 i40e_pf_disable_rss(pf);
5288
5289         return ret;
5290 }
5291
5292 /* Get the symmetric hash enable configurations per port */
5293 static void
5294 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5295 {
5296         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5297
5298         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5299 }
5300
5301 /* Set the symmetric hash enable configurations per port */
5302 static void
5303 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5304 {
5305         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5306
5307         if (enable > 0) {
5308                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5309                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5310                                                         "been enabled");
5311                         return;
5312                 }
5313                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5314         } else {
5315                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5316                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5317                                                         "been disabled");
5318                         return;
5319                 }
5320                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5321         }
5322         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5323         I40E_WRITE_FLUSH(hw);
5324 }
5325
5326 /*
5327  * Get global configurations of hash function type and symmetric hash enable
5328  * per flow type (pctype). Note that global configuration means it affects all
5329  * the ports on the same NIC.
5330  */
5331 static int
5332 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5333                                    struct rte_eth_hash_global_conf *g_cfg)
5334 {
5335         uint32_t reg, mask = I40E_FLOW_TYPES;
5336         uint16_t i;
5337         enum i40e_filter_pctype pctype;
5338
5339         memset(g_cfg, 0, sizeof(*g_cfg));
5340         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5341         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5342                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5343         else
5344                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5345         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5346                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5347
5348         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5349                 if (!(mask & (1UL << i)))
5350                         continue;
5351                 mask &= ~(1UL << i);
5352                 /* Bit set indicats the coresponding flow type is supported */
5353                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5354                 pctype = i40e_flowtype_to_pctype(i);
5355                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5356                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5357                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5358         }
5359
5360         return 0;
5361 }
5362
5363 static int
5364 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5365 {
5366         uint32_t i;
5367         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5368
5369         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5370                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5371                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5372                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5373                                                 g_cfg->hash_func);
5374                 return -EINVAL;
5375         }
5376
5377         /*
5378          * As i40e supports less than 32 flow types, only first 32 bits need to
5379          * be checked.
5380          */
5381         mask0 = g_cfg->valid_bit_mask[0];
5382         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5383                 if (i == 0) {
5384                         /* Check if any unsupported flow type configured */
5385                         if ((mask0 | i40e_mask) ^ i40e_mask)
5386                                 goto mask_err;
5387                 } else {
5388                         if (g_cfg->valid_bit_mask[i])
5389                                 goto mask_err;
5390                 }
5391         }
5392
5393         return 0;
5394
5395 mask_err:
5396         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5397
5398         return -EINVAL;
5399 }
5400
5401 /*
5402  * Set global configurations of hash function type and symmetric hash enable
5403  * per flow type (pctype). Note any modifying global configuration will affect
5404  * all the ports on the same NIC.
5405  */
5406 static int
5407 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5408                                    struct rte_eth_hash_global_conf *g_cfg)
5409 {
5410         int ret;
5411         uint16_t i;
5412         uint32_t reg;
5413         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5414         enum i40e_filter_pctype pctype;
5415
5416         /* Check the input parameters */
5417         ret = i40e_hash_global_config_check(g_cfg);
5418         if (ret < 0)
5419                 return ret;
5420
5421         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5422                 if (!(mask0 & (1UL << i)))
5423                         continue;
5424                 mask0 &= ~(1UL << i);
5425                 pctype = i40e_flowtype_to_pctype(i);
5426                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5427                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5428                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5429         }
5430
5431         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5432         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5433                 /* Toeplitz */
5434                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5435                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5436                                                                 "Toeplitz");
5437                         goto out;
5438                 }
5439                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5440         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5441                 /* Simple XOR */
5442                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5443                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5444                                                         "Simple XOR");
5445                         goto out;
5446                 }
5447                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5448         } else
5449                 /* Use the default, and keep it as it is */
5450                 goto out;
5451
5452         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5453
5454 out:
5455         I40E_WRITE_FLUSH(hw);
5456
5457         return 0;
5458 }
5459
5460 static int
5461 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5462 {
5463         int ret = 0;
5464
5465         if (!hw || !info) {
5466                 PMD_DRV_LOG(ERR, "Invalid pointer");
5467                 return -EFAULT;
5468         }
5469
5470         switch (info->info_type) {
5471         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5472                 i40e_get_symmetric_hash_enable_per_port(hw,
5473                                         &(info->info.enable));
5474                 break;
5475         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5476                 ret = i40e_get_hash_filter_global_config(hw,
5477                                 &(info->info.global_conf));
5478                 break;
5479         default:
5480                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5481                                                         info->info_type);
5482                 ret = -EINVAL;
5483                 break;
5484         }
5485
5486         return ret;
5487 }
5488
5489 static int
5490 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5491 {
5492         int ret = 0;
5493
5494         if (!hw || !info) {
5495                 PMD_DRV_LOG(ERR, "Invalid pointer");
5496                 return -EFAULT;
5497         }
5498
5499         switch (info->info_type) {
5500         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5501                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5502                 break;
5503         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5504                 ret = i40e_set_hash_filter_global_config(hw,
5505                                 &(info->info.global_conf));
5506                 break;
5507         default:
5508                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5509                                                         info->info_type);
5510                 ret = -EINVAL;
5511                 break;
5512         }
5513
5514         return ret;
5515 }
5516
5517 /* Operations for hash function */
5518 static int
5519 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5520                       enum rte_filter_op filter_op,
5521                       void *arg)
5522 {
5523         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5524         int ret = 0;
5525
5526         switch (filter_op) {
5527         case RTE_ETH_FILTER_NOP:
5528                 break;
5529         case RTE_ETH_FILTER_GET:
5530                 ret = i40e_hash_filter_get(hw,
5531                         (struct rte_eth_hash_filter_info *)arg);
5532                 break;
5533         case RTE_ETH_FILTER_SET:
5534                 ret = i40e_hash_filter_set(hw,
5535                         (struct rte_eth_hash_filter_info *)arg);
5536                 break;
5537         default:
5538                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5539                                                                 filter_op);
5540                 ret = -ENOTSUP;
5541                 break;
5542         }
5543
5544         return ret;
5545 }
5546
5547 /*
5548  * Configure ethertype filter, which can director packet by filtering
5549  * with mac address and ether_type or only ether_type
5550  */
5551 static int
5552 i40e_ethertype_filter_set(struct i40e_pf *pf,
5553                         struct rte_eth_ethertype_filter *filter,
5554                         bool add)
5555 {
5556         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5557         struct i40e_control_filter_stats stats;
5558         uint16_t flags = 0;
5559         int ret;
5560
5561         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5562                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5563                 return -EINVAL;
5564         }
5565         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5566                 filter->ether_type == ETHER_TYPE_IPv6) {
5567                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5568                         " control packet filter.", filter->ether_type);
5569                 return -EINVAL;
5570         }
5571         if (filter->ether_type == ETHER_TYPE_VLAN)
5572                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5573                         " not supported.");
5574
5575         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5576                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5577         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5578                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5579         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5580
5581         memset(&stats, 0, sizeof(stats));
5582         ret = i40e_aq_add_rem_control_packet_filter(hw,
5583                         filter->mac_addr.addr_bytes,
5584                         filter->ether_type, flags,
5585                         pf->main_vsi->seid,
5586                         filter->queue, add, &stats, NULL);
5587
5588         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5589                          " mac_etype_used = %u, etype_used = %u,"
5590                          " mac_etype_free = %u, etype_free = %u\n",
5591                          ret, stats.mac_etype_used, stats.etype_used,
5592                          stats.mac_etype_free, stats.etype_free);
5593         if (ret < 0)
5594                 return -ENOSYS;
5595         return 0;
5596 }
5597
5598 /*
5599  * Handle operations for ethertype filter.
5600  */
5601 static int
5602 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5603                                 enum rte_filter_op filter_op,
5604                                 void *arg)
5605 {
5606         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5607         int ret = 0;
5608
5609         if (filter_op == RTE_ETH_FILTER_NOP)
5610                 return ret;
5611
5612         if (arg == NULL) {
5613                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5614                             filter_op);
5615                 return -EINVAL;
5616         }
5617
5618         switch (filter_op) {
5619         case RTE_ETH_FILTER_ADD:
5620                 ret = i40e_ethertype_filter_set(pf,
5621                         (struct rte_eth_ethertype_filter *)arg,
5622                         TRUE);
5623                 break;
5624         case RTE_ETH_FILTER_DELETE:
5625                 ret = i40e_ethertype_filter_set(pf,
5626                         (struct rte_eth_ethertype_filter *)arg,
5627                         FALSE);
5628                 break;
5629         default:
5630                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5631                 ret = -ENOSYS;
5632                 break;
5633         }
5634         return ret;
5635 }
5636
5637 static int
5638 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5639                      enum rte_filter_type filter_type,
5640                      enum rte_filter_op filter_op,
5641                      void *arg)
5642 {
5643         int ret = 0;
5644
5645         if (dev == NULL)
5646                 return -EINVAL;
5647
5648         switch (filter_type) {
5649         case RTE_ETH_FILTER_HASH:
5650                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5651                 break;
5652         case RTE_ETH_FILTER_MACVLAN:
5653                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5654                 break;
5655         case RTE_ETH_FILTER_ETHERTYPE:
5656                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5657                 break;
5658         case RTE_ETH_FILTER_TUNNEL:
5659                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5660                 break;
5661         case RTE_ETH_FILTER_FDIR:
5662                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5663                 break;
5664         default:
5665                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5666                                                         filter_type);
5667                 ret = -EINVAL;
5668                 break;
5669         }
5670
5671         return ret;
5672 }
5673
5674 /*
5675  * As some registers wouldn't be reset unless a global hardware reset,
5676  * hardware initialization is needed to put those registers into an
5677  * expected initial state.
5678  */
5679 static void
5680 i40e_hw_init(struct i40e_hw *hw)
5681 {
5682         /* clear the PF Queue Filter control register */
5683         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5684
5685         /* Disable symmetric hash per port */
5686         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5687 }
5688
5689 enum i40e_filter_pctype
5690 i40e_flowtype_to_pctype(uint16_t flow_type)
5691 {
5692         static const enum i40e_filter_pctype pctype_table[] = {
5693                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5694                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5695                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5696                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5697                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5698                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5699                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5700                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5701                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5702                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5703                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5704                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5705                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5706                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5707                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5708                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5709                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5710                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5711                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5712         };
5713
5714         return pctype_table[flow_type];
5715 }
5716
5717 uint16_t
5718 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5719 {
5720         static const uint16_t flowtype_table[] = {
5721                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5722                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5723                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5724                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5725                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5726                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5727                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5728                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5729                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5730                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5731                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5732                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5733                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5734                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5735                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5736                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5737                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5738                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5739                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5740         };
5741
5742         return flowtype_table[pctype];
5743 }
5744
5745 /*
5746  * On X710, performance number is far from the expectation on recent firmware
5747  * versions; on XL710, performance number is also far from the expectation on
5748  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5749  * mode is enabled and port MAC address is equal to the packet destination MAC
5750  * address. The fix for this issue may not be integrated in the following
5751  * firmware version. So the workaround in software driver is needed. It needs
5752  * to modify the initial values of 3 internal only registers for both X710 and
5753  * XL710. Note that the values for X710 or XL710 could be different, and the
5754  * workaround can be removed when it is fixed in firmware in the future.
5755  */
5756
5757 /* For both X710 and XL710 */
5758 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5759 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5760
5761 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5762 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5763
5764 /* For X710 */
5765 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
5766 /* For XL710 */
5767 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
5768 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5769
5770 static void
5771 i40e_configure_registers(struct i40e_hw *hw)
5772 {
5773         static struct {
5774                 uint32_t addr;
5775                 uint64_t val;
5776         } reg_table[] = {
5777                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5778                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5779                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
5780         };
5781         uint64_t reg;
5782         uint32_t i;
5783         int ret;
5784
5785         for (i = 0; i < RTE_DIM(reg_table); i++) {
5786                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
5787                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
5788                                 reg_table[i].val =
5789                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
5790                         else /* For X710 */
5791                                 reg_table[i].val =
5792                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
5793                 }
5794
5795                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
5796                                                         &reg, NULL);
5797                 if (ret < 0) {
5798                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5799                                                         reg_table[i].addr);
5800                         break;
5801                 }
5802                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5803                                                 reg_table[i].addr, reg);
5804                 if (reg == reg_table[i].val)
5805                         continue;
5806
5807                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5808                                                 reg_table[i].val, NULL);
5809                 if (ret < 0) {
5810                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5811                                 "address of 0x%"PRIx32, reg_table[i].val,
5812                                                         reg_table[i].addr);
5813                         break;
5814                 }
5815                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5816                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5817         }
5818 }
5819
5820 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
5821 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
5822 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
5823 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
5824 static int
5825 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
5826 {
5827         uint32_t reg;
5828         int ret;
5829
5830         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
5831                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
5832                 return -EINVAL;
5833         }
5834
5835         /* Configure for double VLAN RX stripping */
5836         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
5837         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
5838                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
5839                 ret = i40e_aq_debug_write_register(hw,
5840                                                    I40E_VSI_TSR(vsi->vsi_id),
5841                                                    reg, NULL);
5842                 if (ret < 0) {
5843                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
5844                                     vsi->vsi_id);
5845                         return I40E_ERR_CONFIG;
5846                 }
5847         }
5848
5849         /* Configure for double VLAN TX insertion */
5850         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
5851         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
5852                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
5853                 ret = i40e_aq_debug_write_register(hw,
5854                                                    I40E_VSI_L2TAGSTXVALID(
5855                                                    vsi->vsi_id), reg, NULL);
5856                 if (ret < 0) {
5857                         PMD_DRV_LOG(ERR, "Failed to update "
5858                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
5859                         return I40E_ERR_CONFIG;
5860                 }
5861         }
5862
5863         return 0;
5864 }
5865
5866 /**
5867  * i40e_aq_add_mirror_rule
5868  * @hw: pointer to the hardware structure
5869  * @seid: VEB seid to add mirror rule to
5870  * @dst_id: destination vsi seid
5871  * @entries: Buffer which contains the entities to be mirrored
5872  * @count: number of entities contained in the buffer
5873  * @rule_id:the rule_id of the rule to be added
5874  *
5875  * Add a mirror rule for a given veb.
5876  *
5877  **/
5878 static enum i40e_status_code
5879 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
5880                         uint16_t seid, uint16_t dst_id,
5881                         uint16_t rule_type, uint16_t *entries,
5882                         uint16_t count, uint16_t *rule_id)
5883 {
5884         struct i40e_aq_desc desc;
5885         struct i40e_aqc_add_delete_mirror_rule cmd;
5886         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
5887                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
5888                 &desc.params.raw;
5889         uint16_t buff_len;
5890         enum i40e_status_code status;
5891
5892         i40e_fill_default_direct_cmd_desc(&desc,
5893                                           i40e_aqc_opc_add_mirror_rule);
5894         memset(&cmd, 0, sizeof(cmd));
5895
5896         buff_len = sizeof(uint16_t) * count;
5897         desc.datalen = rte_cpu_to_le_16(buff_len);
5898         if (buff_len > 0)
5899                 desc.flags |= rte_cpu_to_le_16(
5900                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5901         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
5902                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
5903         cmd.num_entries = rte_cpu_to_le_16(count);
5904         cmd.seid = rte_cpu_to_le_16(seid);
5905         cmd.destination = rte_cpu_to_le_16(dst_id);
5906
5907         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
5908         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
5909         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
5910                          "rule_id = %u"
5911                          " mirror_rules_used = %u, mirror_rules_free = %u,",
5912                          hw->aq.asq_last_status, resp->rule_id,
5913                          resp->mirror_rules_used, resp->mirror_rules_free);
5914         *rule_id = rte_le_to_cpu_16(resp->rule_id);
5915
5916         return status;
5917 }
5918
5919 /**
5920  * i40e_aq_del_mirror_rule
5921  * @hw: pointer to the hardware structure
5922  * @seid: VEB seid to add mirror rule to
5923  * @entries: Buffer which contains the entities to be mirrored
5924  * @count: number of entities contained in the buffer
5925  * @rule_id:the rule_id of the rule to be delete
5926  *
5927  * Delete a mirror rule for a given veb.
5928  *
5929  **/
5930 static enum i40e_status_code
5931 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
5932                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
5933                 uint16_t count, uint16_t rule_id)
5934 {
5935         struct i40e_aq_desc desc;
5936         struct i40e_aqc_add_delete_mirror_rule cmd;
5937         uint16_t buff_len = 0;
5938         enum i40e_status_code status;
5939         void *buff = NULL;
5940
5941         i40e_fill_default_direct_cmd_desc(&desc,
5942                                           i40e_aqc_opc_delete_mirror_rule);
5943         memset(&cmd, 0, sizeof(cmd));
5944         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
5945                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
5946                                                           I40E_AQ_FLAG_RD));
5947                 cmd.num_entries = count;
5948                 buff_len = sizeof(uint16_t) * count;
5949                 desc.datalen = rte_cpu_to_le_16(buff_len);
5950                 buff = (void *)entries;
5951         } else
5952                 /* rule id is filled in destination field for deleting mirror rule */
5953                 cmd.destination = rte_cpu_to_le_16(rule_id);
5954
5955         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
5956                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
5957         cmd.seid = rte_cpu_to_le_16(seid);
5958
5959         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
5960         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
5961
5962         return status;
5963 }
5964
5965 /**
5966  * i40e_mirror_rule_set
5967  * @dev: pointer to the hardware structure
5968  * @mirror_conf: mirror rule info
5969  * @sw_id: mirror rule's sw_id
5970  * @on: enable/disable
5971  *
5972  * set a mirror rule.
5973  *
5974  **/
5975 static int
5976 i40e_mirror_rule_set(struct rte_eth_dev *dev,
5977                         struct rte_eth_mirror_conf *mirror_conf,
5978                         uint8_t sw_id, uint8_t on)
5979 {
5980         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5981         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5982         struct i40e_mirror_rule *it, *mirr_rule = NULL;
5983         struct i40e_mirror_rule *parent = NULL;
5984         uint16_t seid, dst_seid, rule_id;
5985         uint16_t i, j = 0;
5986         int ret;
5987
5988         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
5989
5990         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
5991                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
5992                         " without veb or vfs.");
5993                 return -ENOSYS;
5994         }
5995         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
5996                 PMD_DRV_LOG(ERR, "mirror table is full.");
5997                 return -ENOSPC;
5998         }
5999         if (mirror_conf->dst_pool > pf->vf_num) {
6000                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
6001                                  mirror_conf->dst_pool);
6002                 return -EINVAL;
6003         }
6004
6005         seid = pf->main_vsi->veb->seid;
6006
6007         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6008                 if (sw_id <= it->index) {
6009                         mirr_rule = it;
6010                         break;
6011                 }
6012                 parent = it;
6013         }
6014         if (mirr_rule && sw_id == mirr_rule->index) {
6015                 if (on) {
6016                         PMD_DRV_LOG(ERR, "mirror rule exists.");
6017                         return -EEXIST;
6018                 } else {
6019                         ret = i40e_aq_del_mirror_rule(hw, seid,
6020                                         mirr_rule->rule_type,
6021                                         mirr_rule->entries,
6022                                         mirr_rule->num_entries, mirr_rule->id);
6023                         if (ret < 0) {
6024                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6025                                                    " ret = %d, aq_err = %d.",
6026                                                    ret, hw->aq.asq_last_status);
6027                                 return -ENOSYS;
6028                         }
6029                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6030                         rte_free(mirr_rule);
6031                         pf->nb_mirror_rule--;
6032                         return 0;
6033                 }
6034         } else if (!on) {
6035                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6036                 return -ENOENT;
6037         }
6038
6039         mirr_rule = rte_zmalloc("i40e_mirror_rule",
6040                                 sizeof(struct i40e_mirror_rule) , 0);
6041         if (!mirr_rule) {
6042                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6043                 return I40E_ERR_NO_MEMORY;
6044         }
6045         switch (mirror_conf->rule_type) {
6046         case ETH_MIRROR_VLAN:
6047                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
6048                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
6049                                 mirr_rule->entries[j] =
6050                                         mirror_conf->vlan.vlan_id[i];
6051                                 j++;
6052                         }
6053                 }
6054                 if (j == 0) {
6055                         PMD_DRV_LOG(ERR, "vlan is not specified.");
6056                         rte_free(mirr_rule);
6057                         return -EINVAL;
6058                 }
6059                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
6060                 break;
6061         case ETH_MIRROR_VIRTUAL_POOL_UP:
6062         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
6063                 /* check if the specified pool bit is out of range */
6064                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
6065                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
6066                         rte_free(mirr_rule);
6067                         return -EINVAL;
6068                 }
6069                 for (i = 0, j = 0; i < pf->vf_num; i++) {
6070                         if (mirror_conf->pool_mask & (1ULL << i)) {
6071                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
6072                                 j++;
6073                         }
6074                 }
6075                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
6076                         /* add pf vsi to entries */
6077                         mirr_rule->entries[j] = pf->main_vsi_seid;
6078                         j++;
6079                 }
6080                 if (j == 0) {
6081                         PMD_DRV_LOG(ERR, "pool is not specified.");
6082                         rte_free(mirr_rule);
6083                         return -EINVAL;
6084                 }
6085                 /* egress and ingress in aq commands means from switch but not port */
6086                 mirr_rule->rule_type =
6087                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
6088                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
6089                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
6090                 break;
6091         case ETH_MIRROR_UPLINK_PORT:
6092                 /* egress and ingress in aq commands means from switch but not port*/
6093                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
6094                 break;
6095         case ETH_MIRROR_DOWNLINK_PORT:
6096                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6097                 break;
6098         default:
6099                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6100                         mirror_conf->rule_type);
6101                 rte_free(mirr_rule);
6102                 return -EINVAL;
6103         }
6104
6105         /* If the dst_pool is equal to vf_num, consider it as PF */
6106         if (mirror_conf->dst_pool == pf->vf_num)
6107                 dst_seid = pf->main_vsi_seid;
6108         else
6109                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6110
6111         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6112                                       mirr_rule->rule_type, mirr_rule->entries,
6113                                       j, &rule_id);
6114         if (ret < 0) {
6115                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6116                                    " ret = %d, aq_err = %d.",
6117                                    ret, hw->aq.asq_last_status);
6118                 rte_free(mirr_rule);
6119                 return -ENOSYS;
6120         }
6121
6122         mirr_rule->index = sw_id;
6123         mirr_rule->num_entries = j;
6124         mirr_rule->id = rule_id;
6125         mirr_rule->dst_vsi_seid = dst_seid;
6126
6127         if (parent)
6128                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6129         else
6130                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6131
6132         pf->nb_mirror_rule++;
6133         return 0;
6134 }
6135
6136 /**
6137  * i40e_mirror_rule_reset
6138  * @dev: pointer to the device
6139  * @sw_id: mirror rule's sw_id
6140  *
6141  * reset a mirror rule.
6142  *
6143  **/
6144 static int
6145 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6146 {
6147         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6148         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6149         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6150         uint16_t seid;
6151         int ret;
6152
6153         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6154
6155         seid = pf->main_vsi->veb->seid;
6156
6157         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6158                 if (sw_id == it->index) {
6159                         mirr_rule = it;
6160                         break;
6161                 }
6162         }
6163         if (mirr_rule) {
6164                 ret = i40e_aq_del_mirror_rule(hw, seid,
6165                                 mirr_rule->rule_type,
6166                                 mirr_rule->entries,
6167                                 mirr_rule->num_entries, mirr_rule->id);
6168                 if (ret < 0) {
6169                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6170                                            " status = %d, aq_err = %d.",
6171                                            ret, hw->aq.asq_last_status);
6172                         return -ENOSYS;
6173                 }
6174                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6175                 rte_free(mirr_rule);
6176                 pf->nb_mirror_rule--;
6177         } else {
6178                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6179                 return -ENOENT;
6180         }
6181         return 0;
6182 }
6183
6184 static int
6185 i40e_timesync_enable(struct rte_eth_dev *dev)
6186 {
6187         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6188         struct rte_eth_link *link = &dev->data->dev_link;
6189         uint32_t tsync_ctl_l;
6190         uint32_t tsync_ctl_h;
6191         uint32_t tsync_inc_l;
6192         uint32_t tsync_inc_h;
6193
6194         switch (link->link_speed) {
6195         case ETH_LINK_SPEED_40G:
6196                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
6197                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
6198                 break;
6199         case ETH_LINK_SPEED_10G:
6200                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
6201                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
6202                 break;
6203         case ETH_LINK_SPEED_1000:
6204                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
6205                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
6206                 break;
6207         default:
6208                 tsync_inc_l = 0x0;
6209                 tsync_inc_h = 0x0;
6210         }
6211
6212         /* Clear timesync registers. */
6213         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6214         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6215         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
6216         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
6217         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
6218         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
6219         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6220
6221         /* Set the timesync increment value. */
6222         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
6223         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
6224
6225         /* Enable timestamping of PTP packets. */
6226         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6227         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
6228
6229         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6230         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
6231         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
6232
6233         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6234         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6235
6236         return 0;
6237 }
6238
6239 static int
6240 i40e_timesync_disable(struct rte_eth_dev *dev)
6241 {
6242         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6243         uint32_t tsync_ctl_l;
6244         uint32_t tsync_ctl_h;
6245
6246         /* Disable timestamping of transmitted PTP packets. */
6247         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6248         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
6249
6250         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6251         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
6252
6253         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6254         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6255
6256         /* Set the timesync increment value. */
6257         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
6258         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
6259
6260         return 0;
6261 }
6262
6263 static int
6264 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6265                                 struct timespec *timestamp, uint32_t flags)
6266 {
6267         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6268         uint32_t sync_status;
6269         uint32_t rx_stmpl;
6270         uint32_t rx_stmph;
6271         uint32_t index = flags & 0x03;
6272
6273         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
6274         if ((sync_status & (1 << index)) == 0)
6275                 return -EINVAL;
6276
6277         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
6278         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
6279
6280         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
6281         timestamp->tv_nsec = 0;
6282
6283         return  0;
6284 }
6285
6286 static int
6287 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6288                                 struct timespec *timestamp)
6289 {
6290         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6291         uint32_t sync_status;
6292         uint32_t tx_stmpl;
6293         uint32_t tx_stmph;
6294
6295         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6296         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
6297                 return -EINVAL;
6298
6299         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
6300         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6301
6302         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
6303         timestamp->tv_nsec = 0;
6304
6305         return  0;
6306 }