drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_eth_ctrl.h>
  28 #include <rte_tailq.h>
  29 #include <rte_hash_crc.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45
  46 #define I40E_CLEAR_PXE_WAIT_MS     200
  47
  48 /* Maximun number of capability elements */
  49 #define I40E_MAX_CAP_ELE_NUM       128
  50
  51 /* Wait count and interval */
  52 #define I40E_CHK_Q_ENA_COUNT       1000
  53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  54
  55 /* Maximun number of VSI */
  56 #define I40E_MAX_NUM_VSIS          (384UL)
  57
  58 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  59
  60 /* Flow control default timer */
  61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  62
  63 /* Flow control enable fwd bit */
  64 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  65
  66 /* Receive Packet Buffer size */
  67 #define I40E_RXPBSIZE (968 * 1024)
  68
  69 /* Kilobytes shift */
  70 #define I40E_KILOSHIFT 10
  71
  72 /* Flow control default high water */
  73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  74
  75 /* Flow control default low water */
  76 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Receive Average Packet Size in Byte*/
  79 #define I40E_PACKET_AVERAGE_SIZE 128
  80
  81 /* Mask of PF interrupt causes */
  82 #define I40E_PFINT_ICR0_ENA_MASK ( \
  83                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  84                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  85                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  86                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  87                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  92
  93 #define I40E_FLOW_TYPES ( \
  94         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  99         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 104         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 105
 106 /* Additional timesync values. */
 107 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 108 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 109 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 110 #define I40E_PRTTSYN_TSYNENA     0x80000000
 111 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 112 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 113
 114 /**
 115  * Below are values for writing un-exposed registers suggested
 116  * by silicon experts
 117  */
 118 /* Destination MAC address */
 119 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 120 /* Source MAC address */
 121 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 123 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 125 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 126 /* Single VLAN tag in the inner L2 header */
 127 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 128 /* Source IPv4 address */
 129 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 130 /* Destination IPv4 address */
 131 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 132 /* Source IPv4 address for X722 */
 133 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 134 /* Destination IPv4 address for X722 */
 135 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 136 /* IPv4 Protocol for X722 */
 137 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 138 /* IPv4 Time to Live for X722 */
 139 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 140 /* IPv4 Type of Service (TOS) */
 141 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 142 /* IPv4 Protocol */
 143 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 144 /* IPv4 Time to Live */
 145 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 146 /* Source IPv6 address */
 147 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 148 /* Destination IPv6 address */
 149 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 150 /* IPv6 Traffic Class (TC) */
 151 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 152 /* IPv6 Next Header */
 153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 154 /* IPv6 Hop Limit */
 155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 156 /* Source L4 port */
 157 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 158 /* Destination L4 port */
 159 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 160 /* SCTP verification tag */
 161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 164 /* Source port of tunneling UDP */
 165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 166 /* Destination port of tunneling UDP */
 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 168 /* UDP Tunneling ID, NVGRE/GRE key */
 169 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 170 /* Last ether type */
 171 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 172 /* Tunneling outer destination IPv4 address */
 173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 174 /* Tunneling outer destination IPv6 address */
 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 176 /* 1st word of flex payload */
 177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 178 /* 2nd word of flex payload */
 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 180 /* 3rd word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 182 /* 4th word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 184 /* 5th word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 186 /* 6th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 188 /* 7th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 190 /* 8th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 192 /* all 8 words flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 194 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 195
 196 #define I40E_TRANSLATE_INSET 0
 197 #define I40E_TRANSLATE_REG   1
 198
 199 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 200 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 201 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 202 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 204 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 205
 206 /* PCI offset for querying capability */
 207 #define PCI_DEV_CAP_REG            0xA4
 208 /* PCI offset for enabling/disabling Extended Tag */
 209 #define PCI_DEV_CTRL_REG           0xA8
 210 /* Bit mask of Extended Tag capability */
 211 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 212 /* Bit shift of Extended Tag enable/disable */
 213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 214 /* Bit mask of Extended Tag enable/disable */
 215 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 216
 217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 219 static int i40e_dev_configure(struct rte_eth_dev *dev);
 220 static int i40e_dev_start(struct rte_eth_dev *dev);
 221 static void i40e_dev_stop(struct rte_eth_dev *dev);
 222 static void i40e_dev_close(struct rte_eth_dev *dev);
 223 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_stats *stats);
 232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 233                                struct rte_eth_xstat *xstats, unsigned n);
 234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 235                                      struct rte_eth_xstat_name *xstats_names,
 236                                      unsigned limit);
 237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 239                                             uint16_t queue_id,
 240                                             uint8_t stat_idx,
 241                                             uint8_t is_rx);
 242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 243                                 char *fw_version, size_t fw_size);
 244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 245                               struct rte_eth_dev_info *dev_info);
 246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 247                                 uint16_t vlan_id,
 248                                 int on);
 249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 250                               enum rte_vlan_type vlan_type,
 251                               uint16_t tpid);
 252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                                       uint16_t queue,
 255                                       int on);
 256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 260                               struct rte_eth_fc_conf *fc_conf);
 261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 264                                        struct rte_eth_pfc_conf *pfc_conf);
 265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 266                             struct ether_addr *mac_addr,
 267                             uint32_t index,
 268                             uint32_t pool);
 269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 271                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 272                                     uint16_t reta_size);
 273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 274                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 275                                    uint16_t reta_size);
 276
 277 static int i40e_get_cap(struct i40e_hw *hw);
 278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 279 static int i40e_pf_setup(struct i40e_pf *pf);
 280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 284                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 285 static void i40e_stat_update_48(struct i40e_hw *hw,
 286                                uint32_t hireg,
 287                                uint32_t loreg,
 288                                bool offset_loaded,
 289                                uint64_t *offset,
 290                                uint64_t *stat);
 291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 292 static void i40e_dev_interrupt_handler(void *param);
 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 294                                 uint32_t base, uint32_t num);
 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 297                         uint32_t base);
 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 299                         uint16_t num);
 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 301 static int i40e_veb_release(struct i40e_veb *veb);
 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 303                                                 struct i40e_vsi *vsi);
 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static int i40e_get_module_info(struct rte_eth_dev *dev,
 374                                 struct rte_eth_dev_module_info *modinfo);
 375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 376                                   struct rte_dev_eeprom_info *info);
 377
 378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 379                                       struct ether_addr *mac_addr);
 380
 381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 382
 383 static int i40e_ethertype_filter_convert(
 384         const struct rte_eth_ethertype_filter *input,
 385         struct i40e_ethertype_filter *filter);
 386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 387                                    struct i40e_ethertype_filter *filter);
 388
 389 static int i40e_tunnel_filter_convert(
 390         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 391         struct i40e_tunnel_filter *tunnel_filter);
 392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 393                                 struct i40e_tunnel_filter *tunnel_filter);
 394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 395
 396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 398 static void i40e_filter_restore(struct i40e_pf *pf);
 399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 400
 401 int i40e_logtype_init;
 402 int i40e_logtype_driver;
 403
 404 static const struct rte_pci_id pci_id_i40e_map[] = {
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 425         { .vendor_id = 0, /* sentinel */ },
 426 };
 427
 428 static const struct eth_dev_ops i40e_eth_dev_ops = {
 429         .dev_configure                = i40e_dev_configure,
 430         .dev_start                    = i40e_dev_start,
 431         .dev_stop                     = i40e_dev_stop,
 432         .dev_close                    = i40e_dev_close,
 433         .dev_reset                    = i40e_dev_reset,
 434         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 435         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 436         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 437         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 438         .dev_set_link_up              = i40e_dev_set_link_up,
 439         .dev_set_link_down            = i40e_dev_set_link_down,
 440         .link_update                  = i40e_dev_link_update,
 441         .stats_get                    = i40e_dev_stats_get,
 442         .xstats_get                   = i40e_dev_xstats_get,
 443         .xstats_get_names             = i40e_dev_xstats_get_names,
 444         .stats_reset                  = i40e_dev_stats_reset,
 445         .xstats_reset                 = i40e_dev_stats_reset,
 446         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 447         .fw_version_get               = i40e_fw_version_get,
 448         .dev_infos_get                = i40e_dev_info_get,
 449         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 450         .vlan_filter_set              = i40e_vlan_filter_set,
 451         .vlan_tpid_set                = i40e_vlan_tpid_set,
 452         .vlan_offload_set             = i40e_vlan_offload_set,
 453         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 454         .vlan_pvid_set                = i40e_vlan_pvid_set,
 455         .rx_queue_start               = i40e_dev_rx_queue_start,
 456         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 457         .tx_queue_start               = i40e_dev_tx_queue_start,
 458         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 459         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 460         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 461         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 462         .rx_queue_release             = i40e_dev_rx_queue_release,
 463         .rx_queue_count               = i40e_dev_rx_queue_count,
 464         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 465         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 466         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 467         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 468         .tx_queue_release             = i40e_dev_tx_queue_release,
 469         .dev_led_on                   = i40e_dev_led_on,
 470         .dev_led_off                  = i40e_dev_led_off,
 471         .flow_ctrl_get                = i40e_flow_ctrl_get,
 472         .flow_ctrl_set                = i40e_flow_ctrl_set,
 473         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 474         .mac_addr_add                 = i40e_macaddr_add,
 475         .mac_addr_remove              = i40e_macaddr_remove,
 476         .reta_update                  = i40e_dev_rss_reta_update,
 477         .reta_query                   = i40e_dev_rss_reta_query,
 478         .rss_hash_update              = i40e_dev_rss_hash_update,
 479         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 480         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 481         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 482         .filter_ctrl                  = i40e_dev_filter_ctrl,
 483         .rxq_info_get                 = i40e_rxq_info_get,
 484         .txq_info_get                 = i40e_txq_info_get,
 485         .mirror_rule_set              = i40e_mirror_rule_set,
 486         .mirror_rule_reset            = i40e_mirror_rule_reset,
 487         .timesync_enable              = i40e_timesync_enable,
 488         .timesync_disable             = i40e_timesync_disable,
 489         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 490         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 491         .get_dcb_info                 = i40e_dev_get_dcb_info,
 492         .timesync_adjust_time         = i40e_timesync_adjust_time,
 493         .timesync_read_time           = i40e_timesync_read_time,
 494         .timesync_write_time          = i40e_timesync_write_time,
 495         .get_reg                      = i40e_get_regs,
 496         .get_eeprom_length            = i40e_get_eeprom_length,
 497         .get_eeprom                   = i40e_get_eeprom,
 498         .get_module_info              = i40e_get_module_info,
 499         .get_module_eeprom            = i40e_get_module_eeprom,
 500         .mac_addr_set                 = i40e_set_default_mac_addr,
 501         .mtu_set                      = i40e_dev_mtu_set,
 502         .tm_ops_get                   = i40e_tm_ops_get,
 503 };
 504
 505 /* store statistics names and its offset in stats structure */
 506 struct rte_i40e_xstats_name_off {
 507         char name[RTE_ETH_XSTATS_NAME_SIZE];
 508         unsigned offset;
 509 };
 510
 511 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 512         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 513         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 514         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 515         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 516         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 517                 rx_unknown_protocol)},
 518         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 519         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 520         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 521         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 522 };
 523
 524 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 525                 sizeof(rte_i40e_stats_strings[0]))
 526
 527 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 528         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 529                 tx_dropped_link_down)},
 530         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 531         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 532                 illegal_bytes)},
 533         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 534         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 535                 mac_local_faults)},
 536         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 537                 mac_remote_faults)},
 538         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 539                 rx_length_errors)},
 540         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 541         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 542         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 543         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 544         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 545         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 546                 rx_size_127)},
 547         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 548                 rx_size_255)},
 549         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 550                 rx_size_511)},
 551         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 552                 rx_size_1023)},
 553         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 554                 rx_size_1522)},
 555         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 556                 rx_size_big)},
 557         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 558                 rx_undersize)},
 559         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 560                 rx_oversize)},
 561         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 562                 mac_short_packet_dropped)},
 563         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 564                 rx_fragments)},
 565         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 566         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 567         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 568                 tx_size_127)},
 569         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 570                 tx_size_255)},
 571         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 572                 tx_size_511)},
 573         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 574                 tx_size_1023)},
 575         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 576                 tx_size_1522)},
 577         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 578                 tx_size_big)},
 579         {"rx_flow_director_atr_match_packets",
 580                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 581         {"rx_flow_director_sb_match_packets",
 582                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 583         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 584                 tx_lpi_status)},
 585         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 586                 rx_lpi_status)},
 587         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 588                 tx_lpi_count)},
 589         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 590                 rx_lpi_count)},
 591 };
 592
 593 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 594                 sizeof(rte_i40e_hw_port_strings[0]))
 595
 596 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 597         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 598                 priority_xon_rx)},
 599         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 600                 priority_xoff_rx)},
 601 };
 602
 603 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 604                 sizeof(rte_i40e_rxq_prio_strings[0]))
 605
 606 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 607         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 608                 priority_xon_tx)},
 609         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xoff_tx)},
 611         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xon_2_xoff)},
 613 };
 614
 615 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 616                 sizeof(rte_i40e_txq_prio_strings[0]))
 617
 618 static int
 619 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 620         struct rte_pci_device *pci_dev)
 621 {
 622         char name[RTE_ETH_NAME_MAX_LEN];
 623         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 624         int i, retval;
 625
 626         if (pci_dev->device.devargs) {
 627                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 628                                 &eth_da);
 629                 if (retval)
 630                         return retval;
 631         }
 632
 633         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 634                 sizeof(struct i40e_adapter),
 635                 eth_dev_pci_specific_init, pci_dev,
 636                 eth_i40e_dev_init, NULL);
 637
 638         if (retval || eth_da.nb_representor_ports < 1)
 639                 return retval;
 640
 641         /* probe VF representor ports */
 642         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 643                 pci_dev->device.name);
 644
 645         if (pf_ethdev == NULL)
 646                 return -ENODEV;
 647
 648         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 649                 struct i40e_vf_representor representor = {
 650                         .vf_id = eth_da.representor_ports[i],
 651                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 652                                 pf_ethdev->data->dev_private)->switch_domain_id,
 653                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 654                                 pf_ethdev->data->dev_private)
 655                 };
 656
 657                 /* representor port net_bdf_port */
 658                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 659                         pci_dev->device.name, eth_da.representor_ports[i]);
 660
 661                 retval = rte_eth_dev_create(&pci_dev->device, name,
 662                         sizeof(struct i40e_vf_representor), NULL, NULL,
 663                         i40e_vf_representor_init, &representor);
 664
 665                 if (retval)
 666                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 667                                 "representor %s.", name);
 668         }
 669
 670         return 0;
 671 }
 672
 673 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 674 {
 675         struct rte_eth_dev *ethdev;
 676
 677         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 678         if (!ethdev)
 679                 return -ENODEV;
 680
 681
 682         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 683                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 684         else
 685                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 686 }
 687
 688 static struct rte_pci_driver rte_i40e_pmd = {
 689         .id_table = pci_id_i40e_map,
 690         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 691                      RTE_PCI_DRV_IOVA_AS_VA,
 692         .probe = eth_i40e_pci_probe,
 693         .remove = eth_i40e_pci_remove,
 694 };
 695
 696 static inline void
 697 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 698                          uint32_t reg_val)
 699 {
 700         uint32_t ori_reg_val;
 701
 702         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 703         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 704         PMD_DRV_LOG(DEBUG,
 705                     "Global register [0x%08x] original: 0x%08x, after: 0x%08x",
 706                     reg_addr, ori_reg_val, reg_val);
 707 }
 708
 709 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 710 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 711 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 712
 713 #ifndef I40E_GLQF_ORT
 714 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 715 #endif
 716 #ifndef I40E_GLQF_PIT
 717 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 718 #endif
 719 #ifndef I40E_GLQF_L3_MAP
 720 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 721 #endif
 722
 723 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 724 {
 725         /*
 726          * Initialize registers for parsing packet type of QinQ
 727          * This should be removed from code once proper
 728          * configuration API is added to avoid configuration conflicts
 729          * between ports of the same device.
 730          */
 731         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 732         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 733         i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
 734 }
 735
 736 static inline void i40e_config_automask(struct i40e_pf *pf)
 737 {
 738         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 739         uint32_t val;
 740
 741         /* INTENA flag is not auto-cleared for interrupt */
 742         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 743         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 744                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 745
 746         /* If support multi-driver, PF will use INT0. */
 747         if (!pf->support_multi_driver)
 748                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 749
 750         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 751 }
 752
 753 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 754
 755 /*
 756  * Add a ethertype filter to drop all flow control frames transmitted
 757  * from VSIs.
 758 */
 759 static void
 760 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 761 {
 762         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 763         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 764                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 765                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 766         int ret;
 767
 768         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 769                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 770                                 pf->main_vsi_seid, 0,
 771                                 TRUE, NULL, NULL);
 772         if (ret)
 773                 PMD_INIT_LOG(ERR,
 774                         "Failed to add filter to drop flow control frames from VSIs.");
 775 }
 776
 777 static int
 778 floating_veb_list_handler(__rte_unused const char *key,
 779                           const char *floating_veb_value,
 780                           void *opaque)
 781 {
 782         int idx = 0;
 783         unsigned int count = 0;
 784         char *end = NULL;
 785         int min, max;
 786         bool *vf_floating_veb = opaque;
 787
 788         while (isblank(*floating_veb_value))
 789                 floating_veb_value++;
 790
 791         /* Reset floating VEB configuration for VFs */
 792         for (idx = 0; idx < I40E_MAX_VF; idx++)
 793                 vf_floating_veb[idx] = false;
 794
 795         min = I40E_MAX_VF;
 796         do {
 797                 while (isblank(*floating_veb_value))
 798                         floating_veb_value++;
 799                 if (*floating_veb_value == '\0')
 800                         return -1;
 801                 errno = 0;
 802                 idx = strtoul(floating_veb_value, &end, 10);
 803                 if (errno || end == NULL)
 804                         return -1;
 805                 while (isblank(*end))
 806                         end++;
 807                 if (*end == '-') {
 808                         min = idx;
 809                 } else if ((*end == ';') || (*end == '\0')) {
 810                         max = idx;
 811                         if (min == I40E_MAX_VF)
 812                                 min = idx;
 813                         if (max >= I40E_MAX_VF)
 814                                 max = I40E_MAX_VF - 1;
 815                         for (idx = min; idx <= max; idx++) {
 816                                 vf_floating_veb[idx] = true;
 817                                 count++;
 818                         }
 819                         min = I40E_MAX_VF;
 820                 } else {
 821                         return -1;
 822                 }
 823                 floating_veb_value = end + 1;
 824         } while (*end != '\0');
 825
 826         if (count == 0)
 827                 return -1;
 828
 829         return 0;
 830 }
 831
 832 static void
 833 config_vf_floating_veb(struct rte_devargs *devargs,
 834                        uint16_t floating_veb,
 835                        bool *vf_floating_veb)
 836 {
 837         struct rte_kvargs *kvlist;
 838         int i;
 839         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 840
 841         if (!floating_veb)
 842                 return;
 843         /* All the VFs attach to the floating VEB by default
 844          * when the floating VEB is enabled.
 845          */
 846         for (i = 0; i < I40E_MAX_VF; i++)
 847                 vf_floating_veb[i] = true;
 848
 849         if (devargs == NULL)
 850                 return;
 851
 852         kvlist = rte_kvargs_parse(devargs->args, NULL);
 853         if (kvlist == NULL)
 854                 return;
 855
 856         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 857                 rte_kvargs_free(kvlist);
 858                 return;
 859         }
 860         /* When the floating_veb_list parameter exists, all the VFs
 861          * will attach to the legacy VEB firstly, then configure VFs
 862          * to the floating VEB according to the floating_veb_list.
 863          */
 864         if (rte_kvargs_process(kvlist, floating_veb_list,
 865                                floating_veb_list_handler,
 866                                vf_floating_veb) < 0) {
 867                 rte_kvargs_free(kvlist);
 868                 return;
 869         }
 870         rte_kvargs_free(kvlist);
 871 }
 872
 873 static int
 874 i40e_check_floating_handler(__rte_unused const char *key,
 875                             const char *value,
 876                             __rte_unused void *opaque)
 877 {
 878         if (strcmp(value, "1"))
 879                 return -1;
 880
 881         return 0;
 882 }
 883
 884 static int
 885 is_floating_veb_supported(struct rte_devargs *devargs)
 886 {
 887         struct rte_kvargs *kvlist;
 888         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 889
 890         if (devargs == NULL)
 891                 return 0;
 892
 893         kvlist = rte_kvargs_parse(devargs->args, NULL);
 894         if (kvlist == NULL)
 895                 return 0;
 896
 897         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 898                 rte_kvargs_free(kvlist);
 899                 return 0;
 900         }
 901         /* Floating VEB is enabled when there's key-value:
 902          * enable_floating_veb=1
 903          */
 904         if (rte_kvargs_process(kvlist, floating_veb_key,
 905                                i40e_check_floating_handler, NULL) < 0) {
 906                 rte_kvargs_free(kvlist);
 907                 return 0;
 908         }
 909         rte_kvargs_free(kvlist);
 910
 911         return 1;
 912 }
 913
 914 static void
 915 config_floating_veb(struct rte_eth_dev *dev)
 916 {
 917         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 918         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 919         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 920
 921         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 922
 923         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 924                 pf->floating_veb =
 925                         is_floating_veb_supported(pci_dev->device.devargs);
 926                 config_vf_floating_veb(pci_dev->device.devargs,
 927                                        pf->floating_veb,
 928                                        pf->floating_veb_list);
 929         } else {
 930                 pf->floating_veb = false;
 931         }
 932 }
 933
 934 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 935 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 936
 937 static int
 938 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 939 {
 940         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 941         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 942         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 943         int ret;
 944
 945         struct rte_hash_parameters ethertype_hash_params = {
 946                 .name = ethertype_hash_name,
 947                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 948                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 949                 .hash_func = rte_hash_crc,
 950                 .hash_func_init_val = 0,
 951                 .socket_id = rte_socket_id(),
 952         };
 953
 954         /* Initialize ethertype filter rule list and hash */
 955         TAILQ_INIT(&ethertype_rule->ethertype_list);
 956         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 957                  "ethertype_%s", dev->device->name);
 958         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 959         if (!ethertype_rule->hash_table) {
 960                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 961                 return -EINVAL;
 962         }
 963         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 964                                        sizeof(struct i40e_ethertype_filter *) *
 965                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 966                                        0);
 967         if (!ethertype_rule->hash_map) {
 968                 PMD_INIT_LOG(ERR,
 969                              "Failed to allocate memory for ethertype hash map!");
 970                 ret = -ENOMEM;
 971                 goto err_ethertype_hash_map_alloc;
 972         }
 973
 974         return 0;
 975
 976 err_ethertype_hash_map_alloc:
 977         rte_hash_free(ethertype_rule->hash_table);
 978
 979         return ret;
 980 }
 981
 982 static int
 983 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 984 {
 985         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 986         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 987         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 988         int ret;
 989
 990         struct rte_hash_parameters tunnel_hash_params = {
 991                 .name = tunnel_hash_name,
 992                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 993                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 994                 .hash_func = rte_hash_crc,
 995                 .hash_func_init_val = 0,
 996                 .socket_id = rte_socket_id(),
 997         };
 998
 999         /* Initialize tunnel filter rule list and hash */
1000         TAILQ_INIT(&tunnel_rule->tunnel_list);
1001         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1002                  "tunnel_%s", dev->device->name);
1003         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1004         if (!tunnel_rule->hash_table) {
1005                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1006                 return -EINVAL;
1007         }
1008         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1009                                     sizeof(struct i40e_tunnel_filter *) *
1010                                     I40E_MAX_TUNNEL_FILTER_NUM,
1011                                     0);
1012         if (!tunnel_rule->hash_map) {
1013                 PMD_INIT_LOG(ERR,
1014                              "Failed to allocate memory for tunnel hash map!");
1015                 ret = -ENOMEM;
1016                 goto err_tunnel_hash_map_alloc;
1017         }
1018
1019         return 0;
1020
1021 err_tunnel_hash_map_alloc:
1022         rte_hash_free(tunnel_rule->hash_table);
1023
1024         return ret;
1025 }
1026
1027 static int
1028 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1029 {
1030         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1031         struct i40e_fdir_info *fdir_info = &pf->fdir;
1032         char fdir_hash_name[RTE_HASH_NAMESIZE];
1033         int ret;
1034
1035         struct rte_hash_parameters fdir_hash_params = {
1036                 .name = fdir_hash_name,
1037                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1038                 .key_len = sizeof(struct i40e_fdir_input),
1039                 .hash_func = rte_hash_crc,
1040                 .hash_func_init_val = 0,
1041                 .socket_id = rte_socket_id(),
1042         };
1043
1044         /* Initialize flow director filter rule list and hash */
1045         TAILQ_INIT(&fdir_info->fdir_list);
1046         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1047                  "fdir_%s", dev->device->name);
1048         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1049         if (!fdir_info->hash_table) {
1050                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1051                 return -EINVAL;
1052         }
1053         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1054                                           sizeof(struct i40e_fdir_filter *) *
1055                                           I40E_MAX_FDIR_FILTER_NUM,
1056                                           0);
1057         if (!fdir_info->hash_map) {
1058                 PMD_INIT_LOG(ERR,
1059                              "Failed to allocate memory for fdir hash map!");
1060                 ret = -ENOMEM;
1061                 goto err_fdir_hash_map_alloc;
1062         }
1063         return 0;
1064
1065 err_fdir_hash_map_alloc:
1066         rte_hash_free(fdir_info->hash_table);
1067
1068         return ret;
1069 }
1070
1071 static void
1072 i40e_init_customized_info(struct i40e_pf *pf)
1073 {
1074         int i;
1075
1076         /* Initialize customized pctype */
1077         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1078                 pf->customized_pctype[i].index = i;
1079                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1080                 pf->customized_pctype[i].valid = false;
1081         }
1082
1083         pf->gtp_support = false;
1084 }
1085
1086 void
1087 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1088 {
1089         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1090         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1091         struct i40e_queue_regions *info = &pf->queue_region;
1092         uint16_t i;
1093
1094         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1095                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1096
1097         memset(info, 0, sizeof(struct i40e_queue_regions));
1098 }
1099
1100 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
1101
1102 static int
1103 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1104                                const char *value,
1105                                void *opaque)
1106 {
1107         struct i40e_pf *pf;
1108         unsigned long support_multi_driver;
1109         char *end;
1110
1111         pf = (struct i40e_pf *)opaque;
1112
1113         errno = 0;
1114         support_multi_driver = strtoul(value, &end, 10);
1115         if (errno != 0 || end == value || *end != 0) {
1116                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1117                 return -(EINVAL);
1118         }
1119
1120         if (support_multi_driver == 1 || support_multi_driver == 0)
1121                 pf->support_multi_driver = (bool)support_multi_driver;
1122         else
1123                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1124                             "enable global configuration by default."
1125                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1126         return 0;
1127 }
1128
1129 static int
1130 i40e_support_multi_driver(struct rte_eth_dev *dev)
1131 {
1132         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1133         static const char *const valid_keys[] = {
1134                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1135         struct rte_kvargs *kvlist;
1136
1137         /* Enable global configuration by default */
1138         pf->support_multi_driver = false;
1139
1140         if (!dev->device->devargs)
1141                 return 0;
1142
1143         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1144         if (!kvlist)
1145                 return -EINVAL;
1146
1147         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1148                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1149                             "the first invalid or last valid one is used !",
1150                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1151
1152         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1153                                i40e_parse_multi_drv_handler, pf) < 0) {
1154                 rte_kvargs_free(kvlist);
1155                 return -EINVAL;
1156         }
1157
1158         rte_kvargs_free(kvlist);
1159         return 0;
1160 }
1161
1162 static int
1163 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1164                                     uint32_t reg_addr, uint64_t reg_val,
1165                                     struct i40e_asq_cmd_details *cmd_details)
1166 {
1167         uint64_t ori_reg_val;
1168         int ret;
1169
1170         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1171         if (ret != I40E_SUCCESS) {
1172                 PMD_DRV_LOG(ERR,
1173                             "Fail to debug read from 0x%08x",
1174                             reg_addr);
1175                 return -EIO;
1176         }
1177
1178         PMD_DRV_LOG(DEBUG,
1179                     "Global register [0x%08x] original: 0x%"PRIx64
1180                     ", after: 0x%"PRIx64,
1181                     reg_addr, ori_reg_val, reg_val);
1182
1183         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1184 }
1185
1186 static int
1187 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1188 {
1189         struct rte_pci_device *pci_dev;
1190         struct rte_intr_handle *intr_handle;
1191         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1192         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1193         struct i40e_vsi *vsi;
1194         int ret;
1195         uint32_t len;
1196         uint8_t aq_fail = 0;
1197
1198         PMD_INIT_FUNC_TRACE();
1199
1200         dev->dev_ops = &i40e_eth_dev_ops;
1201         dev->rx_pkt_burst = i40e_recv_pkts;
1202         dev->tx_pkt_burst = i40e_xmit_pkts;
1203         dev->tx_pkt_prepare = i40e_prep_pkts;
1204
1205         /* for secondary processes, we don't initialise any further as primary
1206          * has already done this work. Only check we don't need a different
1207          * RX function */
1208         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1209                 i40e_set_rx_function(dev);
1210                 i40e_set_tx_function(dev);
1211                 return 0;
1212         }
1213         i40e_set_default_ptype_table(dev);
1214         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1215         intr_handle = &pci_dev->intr_handle;
1216
1217         rte_eth_copy_pci_info(dev, pci_dev);
1218
1219         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1220         pf->adapter->eth_dev = dev;
1221         pf->dev_data = dev->data;
1222
1223         hw->back = I40E_PF_TO_ADAPTER(pf);
1224         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1225         if (!hw->hw_addr) {
1226                 PMD_INIT_LOG(ERR,
1227                         "Hardware is not available, as address is NULL");
1228                 return -ENODEV;
1229         }
1230
1231         hw->vendor_id = pci_dev->id.vendor_id;
1232         hw->device_id = pci_dev->id.device_id;
1233         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1234         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1235         hw->bus.device = pci_dev->addr.devid;
1236         hw->bus.func = pci_dev->addr.function;
1237         hw->adapter_stopped = 0;
1238
1239         /* Check if need to support multi-driver */
1240         i40e_support_multi_driver(dev);
1241
1242         /* Make sure all is clean before doing PF reset */
1243         i40e_clear_hw(hw);
1244
1245         /* Initialize the hardware */
1246         i40e_hw_init(dev);
1247
1248         /* Reset here to make sure all is clean for each PF */
1249         ret = i40e_pf_reset(hw);
1250         if (ret) {
1251                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1252                 return ret;
1253         }
1254
1255         /* Initialize the shared code (base driver) */
1256         ret = i40e_init_shared_code(hw);
1257         if (ret) {
1258                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1259                 return ret;
1260         }
1261
1262         i40e_config_automask(pf);
1263
1264         i40e_set_default_pctype_table(dev);
1265
1266         /*
1267          * To work around the NVM issue, initialize registers
1268          * for packet type of QinQ by software.
1269          * It should be removed once issues are fixed in NVM.
1270          */
1271         if (!pf->support_multi_driver)
1272                 i40e_GLQF_reg_init(hw);
1273
1274         /* Initialize the input set for filters (hash and fd) to default value */
1275         i40e_filter_input_set_init(pf);
1276
1277         /* Initialize the parameters for adminq */
1278         i40e_init_adminq_parameter(hw);
1279         ret = i40e_init_adminq(hw);
1280         if (ret != I40E_SUCCESS) {
1281                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1282                 return -EIO;
1283         }
1284         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1285                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1286                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1287                      ((hw->nvm.version >> 12) & 0xf),
1288                      ((hw->nvm.version >> 4) & 0xff),
1289                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1290
1291         /* initialise the L3_MAP register */
1292         if (!pf->support_multi_driver) {
1293                 ret = i40e_aq_debug_write_global_register(hw,
1294                                                    I40E_GLQF_L3_MAP(40),
1295                                                    0x00000028,  NULL);
1296                 if (ret)
1297                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1298                                      ret);
1299                 PMD_INIT_LOG(DEBUG,
1300                              "Global register 0x%08x is changed with 0x28",
1301                              I40E_GLQF_L3_MAP(40));
1302                 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1303         }
1304
1305         /* Need the special FW version to support floating VEB */
1306         config_floating_veb(dev);
1307         /* Clear PXE mode */
1308         i40e_clear_pxe_mode(hw);
1309         i40e_dev_sync_phy_type(hw);
1310
1311         /*
1312          * On X710, performance number is far from the expectation on recent
1313          * firmware versions. The fix for this issue may not be integrated in
1314          * the following firmware version. So the workaround in software driver
1315          * is needed. It needs to modify the initial values of 3 internal only
1316          * registers. Note that the workaround can be removed when it is fixed
1317          * in firmware in the future.
1318          */
1319         i40e_configure_registers(hw);
1320
1321         /* Get hw capabilities */
1322         ret = i40e_get_cap(hw);
1323         if (ret != I40E_SUCCESS) {
1324                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1325                 goto err_get_capabilities;
1326         }
1327
1328         /* Initialize parameters for PF */
1329         ret = i40e_pf_parameter_init(dev);
1330         if (ret != 0) {
1331                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1332                 goto err_parameter_init;
1333         }
1334
1335         /* Initialize the queue management */
1336         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1337         if (ret < 0) {
1338                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1339                 goto err_qp_pool_init;
1340         }
1341         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1342                                 hw->func_caps.num_msix_vectors - 1);
1343         if (ret < 0) {
1344                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1345                 goto err_msix_pool_init;
1346         }
1347
1348         /* Initialize lan hmc */
1349         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1350                                 hw->func_caps.num_rx_qp, 0, 0);
1351         if (ret != I40E_SUCCESS) {
1352                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1353                 goto err_init_lan_hmc;
1354         }
1355
1356         /* Configure lan hmc */
1357         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1358         if (ret != I40E_SUCCESS) {
1359                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1360                 goto err_configure_lan_hmc;
1361         }
1362
1363         /* Get and check the mac address */
1364         i40e_get_mac_addr(hw, hw->mac.addr);
1365         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1366                 PMD_INIT_LOG(ERR, "mac address is not valid");
1367                 ret = -EIO;
1368                 goto err_get_mac_addr;
1369         }
1370         /* Copy the permanent MAC address */
1371         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1372                         (struct ether_addr *) hw->mac.perm_addr);
1373
1374         /* Disable flow control */
1375         hw->fc.requested_mode = I40E_FC_NONE;
1376         i40e_set_fc(hw, &aq_fail, TRUE);
1377
1378         /* Set the global registers with default ether type value */
1379         if (!pf->support_multi_driver) {
1380                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1381                                          ETHER_TYPE_VLAN);
1382                 if (ret != I40E_SUCCESS) {
1383                         PMD_INIT_LOG(ERR,
1384                                      "Failed to set the default outer "
1385                                      "VLAN ether type");
1386                         goto err_setup_pf_switch;
1387                 }
1388         }
1389
1390         /* PF setup, which includes VSI setup */
1391         ret = i40e_pf_setup(pf);
1392         if (ret) {
1393                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1394                 goto err_setup_pf_switch;
1395         }
1396
1397         /* reset all stats of the device, including pf and main vsi */
1398         i40e_dev_stats_reset(dev);
1399
1400         vsi = pf->main_vsi;
1401
1402         /* Disable double vlan by default */
1403         i40e_vsi_config_double_vlan(vsi, FALSE);
1404
1405         /* Disable S-TAG identification when floating_veb is disabled */
1406         if (!pf->floating_veb) {
1407                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1408                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1409                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1410                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1411                 }
1412         }
1413
1414         if (!vsi->max_macaddrs)
1415                 len = ETHER_ADDR_LEN;
1416         else
1417                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1418
1419         /* Should be after VSI initialized */
1420         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1421         if (!dev->data->mac_addrs) {
1422                 PMD_INIT_LOG(ERR,
1423                         "Failed to allocated memory for storing mac address");
1424                 goto err_mac_alloc;
1425         }
1426         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1427                                         &dev->data->mac_addrs[0]);
1428
1429         /* Init dcb to sw mode by default */
1430         ret = i40e_dcb_init_configure(dev, TRUE);
1431         if (ret != I40E_SUCCESS) {
1432                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1433                 pf->flags &= ~I40E_FLAG_DCB;
1434         }
1435         /* Update HW struct after DCB configuration */
1436         i40e_get_cap(hw);
1437
1438         /* initialize pf host driver to setup SRIOV resource if applicable */
1439         i40e_pf_host_init(dev);
1440
1441         /* register callback func to eal lib */
1442         rte_intr_callback_register(intr_handle,
1443                                    i40e_dev_interrupt_handler, dev);
1444
1445         /* configure and enable device interrupt */
1446         i40e_pf_config_irq0(hw, TRUE);
1447         i40e_pf_enable_irq0(hw);
1448
1449         /* enable uio intr after callback register */
1450         rte_intr_enable(intr_handle);
1451
1452         /* By default disable flexible payload in global configuration */
1453         if (!pf->support_multi_driver)
1454                 i40e_flex_payload_reg_set_default(hw);
1455
1456         /*
1457          * Add an ethertype filter to drop all flow control frames transmitted
1458          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1459          * frames to wire.
1460          */
1461         i40e_add_tx_flow_control_drop_filter(pf);
1462
1463         /* Set the max frame size to 0x2600 by default,
1464          * in case other drivers changed the default value.
1465          */
1466         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1467
1468         /* initialize mirror rule list */
1469         TAILQ_INIT(&pf->mirror_list);
1470
1471         /* initialize Traffic Manager configuration */
1472         i40e_tm_conf_init(dev);
1473
1474         /* Initialize customized information */
1475         i40e_init_customized_info(pf);
1476
1477         ret = i40e_init_ethtype_filter_list(dev);
1478         if (ret < 0)
1479                 goto err_init_ethtype_filter_list;
1480         ret = i40e_init_tunnel_filter_list(dev);
1481         if (ret < 0)
1482                 goto err_init_tunnel_filter_list;
1483         ret = i40e_init_fdir_filter_list(dev);
1484         if (ret < 0)
1485                 goto err_init_fdir_filter_list;
1486
1487         /* initialize queue region configuration */
1488         i40e_init_queue_region_conf(dev);
1489
1490         /* initialize rss configuration from rte_flow */
1491         memset(&pf->rss_info, 0,
1492                 sizeof(struct i40e_rte_flow_rss_conf));
1493
1494         return 0;
1495
1496 err_init_fdir_filter_list:
1497         rte_free(pf->tunnel.hash_table);
1498         rte_free(pf->tunnel.hash_map);
1499 err_init_tunnel_filter_list:
1500         rte_free(pf->ethertype.hash_table);
1501         rte_free(pf->ethertype.hash_map);
1502 err_init_ethtype_filter_list:
1503         rte_free(dev->data->mac_addrs);
1504 err_mac_alloc:
1505         i40e_vsi_release(pf->main_vsi);
1506 err_setup_pf_switch:
1507 err_get_mac_addr:
1508 err_configure_lan_hmc:
1509         (void)i40e_shutdown_lan_hmc(hw);
1510 err_init_lan_hmc:
1511         i40e_res_pool_destroy(&pf->msix_pool);
1512 err_msix_pool_init:
1513         i40e_res_pool_destroy(&pf->qp_pool);
1514 err_qp_pool_init:
1515 err_parameter_init:
1516 err_get_capabilities:
1517         (void)i40e_shutdown_adminq(hw);
1518
1519         return ret;
1520 }
1521
1522 static void
1523 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1524 {
1525         struct i40e_ethertype_filter *p_ethertype;
1526         struct i40e_ethertype_rule *ethertype_rule;
1527
1528         ethertype_rule = &pf->ethertype;
1529         /* Remove all ethertype filter rules and hash */
1530         if (ethertype_rule->hash_map)
1531                 rte_free(ethertype_rule->hash_map);
1532         if (ethertype_rule->hash_table)
1533                 rte_hash_free(ethertype_rule->hash_table);
1534
1535         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1536                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1537                              p_ethertype, rules);
1538                 rte_free(p_ethertype);
1539         }
1540 }
1541
1542 static void
1543 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1544 {
1545         struct i40e_tunnel_filter *p_tunnel;
1546         struct i40e_tunnel_rule *tunnel_rule;
1547
1548         tunnel_rule = &pf->tunnel;
1549         /* Remove all tunnel director rules and hash */
1550         if (tunnel_rule->hash_map)
1551                 rte_free(tunnel_rule->hash_map);
1552         if (tunnel_rule->hash_table)
1553                 rte_hash_free(tunnel_rule->hash_table);
1554
1555         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1556                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1557                 rte_free(p_tunnel);
1558         }
1559 }
1560
1561 static void
1562 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1563 {
1564         struct i40e_fdir_filter *p_fdir;
1565         struct i40e_fdir_info *fdir_info;
1566
1567         fdir_info = &pf->fdir;
1568         /* Remove all flow director rules and hash */
1569         if (fdir_info->hash_map)
1570                 rte_free(fdir_info->hash_map);
1571         if (fdir_info->hash_table)
1572                 rte_hash_free(fdir_info->hash_table);
1573
1574         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1575                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1576                 rte_free(p_fdir);
1577         }
1578 }
1579
1580 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1581 {
1582         /*
1583          * Disable by default flexible payload
1584          * for corresponding L2/L3/L4 layers.
1585          */
1586         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1587         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1588         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1589         i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
1590 }
1591
1592 static int
1593 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1594 {
1595         struct i40e_pf *pf;
1596         struct rte_pci_device *pci_dev;
1597         struct rte_intr_handle *intr_handle;
1598         struct i40e_hw *hw;
1599         struct i40e_filter_control_settings settings;
1600         struct rte_flow *p_flow;
1601         int ret;
1602         uint8_t aq_fail = 0;
1603         int retries = 0;
1604
1605         PMD_INIT_FUNC_TRACE();
1606
1607         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1608                 return 0;
1609
1610         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1611         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1612         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1613         intr_handle = &pci_dev->intr_handle;
1614
1615         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1616         if (ret)
1617                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1618
1619         if (hw->adapter_stopped == 0)
1620                 i40e_dev_close(dev);
1621
1622         dev->dev_ops = NULL;
1623         dev->rx_pkt_burst = NULL;
1624         dev->tx_pkt_burst = NULL;
1625
1626         /* Clear PXE mode */
1627         i40e_clear_pxe_mode(hw);
1628
1629         /* Unconfigure filter control */
1630         memset(&settings, 0, sizeof(settings));
1631         ret = i40e_set_filter_control(hw, &settings);
1632         if (ret)
1633                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1634                                         ret);
1635
1636         /* Disable flow control */
1637         hw->fc.requested_mode = I40E_FC_NONE;
1638         i40e_set_fc(hw, &aq_fail, TRUE);
1639
1640         /* uninitialize pf host driver */
1641         i40e_pf_host_uninit(dev);
1642
1643         rte_free(dev->data->mac_addrs);
1644         dev->data->mac_addrs = NULL;
1645
1646         /* disable uio intr before callback unregister */
1647         rte_intr_disable(intr_handle);
1648
1649         /* unregister callback func to eal lib */
1650         do {
1651                 ret = rte_intr_callback_unregister(intr_handle,
1652                                 i40e_dev_interrupt_handler, dev);
1653                 if (ret >= 0) {
1654                         break;
1655                 } else if (ret != -EAGAIN) {
1656                         PMD_INIT_LOG(ERR,
1657                                  "intr callback unregister failed: %d",
1658                                  ret);
1659                         return ret;
1660                 }
1661                 i40e_msec_delay(500);
1662         } while (retries++ < 5);
1663
1664         i40e_rm_ethtype_filter_list(pf);
1665         i40e_rm_tunnel_filter_list(pf);
1666         i40e_rm_fdir_filter_list(pf);
1667
1668         /* Remove all flows */
1669         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1670                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1671                 rte_free(p_flow);
1672         }
1673
1674         /* Remove all Traffic Manager configuration */
1675         i40e_tm_conf_uninit(dev);
1676
1677         return 0;
1678 }
1679
1680 static int
1681 i40e_dev_configure(struct rte_eth_dev *dev)
1682 {
1683         struct i40e_adapter *ad =
1684                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1685         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1686         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1688         int i, ret;
1689
1690         ret = i40e_dev_sync_phy_type(hw);
1691         if (ret)
1692                 return ret;
1693
1694         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1695          * bulk allocation or vector Rx preconditions we will reset it.
1696          */
1697         ad->rx_bulk_alloc_allowed = true;
1698         ad->rx_vec_allowed = true;
1699         ad->tx_simple_allowed = true;
1700         ad->tx_vec_allowed = true;
1701
1702         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1703                 ret = i40e_fdir_setup(pf);
1704                 if (ret != I40E_SUCCESS) {
1705                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1706                         return -ENOTSUP;
1707                 }
1708                 ret = i40e_fdir_configure(dev);
1709                 if (ret < 0) {
1710                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1711                         goto err;
1712                 }
1713         } else
1714                 i40e_fdir_teardown(pf);
1715
1716         ret = i40e_dev_init_vlan(dev);
1717         if (ret < 0)
1718                 goto err;
1719
1720         /* VMDQ setup.
1721          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1722          *  RSS setting have different requirements.
1723          *  General PMD driver call sequence are NIC init, configure,
1724          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1725          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1726          *  applicable. So, VMDQ setting has to be done before
1727          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1728          *  For RSS setting, it will try to calculate actual configured RX queue
1729          *  number, which will be available after rx_queue_setup(). dev_start()
1730          *  function is good to place RSS setup.
1731          */
1732         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1733                 ret = i40e_vmdq_setup(dev);
1734                 if (ret)
1735                         goto err;
1736         }
1737
1738         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1739                 ret = i40e_dcb_setup(dev);
1740                 if (ret) {
1741                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1742                         goto err_dcb;
1743                 }
1744         }
1745
1746         TAILQ_INIT(&pf->flow_list);
1747
1748         return 0;
1749
1750 err_dcb:
1751         /* need to release vmdq resource if exists */
1752         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1753                 i40e_vsi_release(pf->vmdq[i].vsi);
1754                 pf->vmdq[i].vsi = NULL;
1755         }
1756         rte_free(pf->vmdq);
1757         pf->vmdq = NULL;
1758 err:
1759         /* need to release fdir resource if exists */
1760         i40e_fdir_teardown(pf);
1761         return ret;
1762 }
1763
1764 void
1765 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1766 {
1767         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1768         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1769         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1770         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1771         uint16_t msix_vect = vsi->msix_intr;
1772         uint16_t i;
1773
1774         for (i = 0; i < vsi->nb_qps; i++) {
1775                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1776                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1777                 rte_wmb();
1778         }
1779
1780         if (vsi->type != I40E_VSI_SRIOV) {
1781                 if (!rte_intr_allow_others(intr_handle)) {
1782                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1783                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1784                         I40E_WRITE_REG(hw,
1785                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1786                                        0);
1787                 } else {
1788                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1789                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1790                         I40E_WRITE_REG(hw,
1791                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1792                                                        msix_vect - 1), 0);
1793                 }
1794         } else {
1795                 uint32_t reg;
1796                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1797                         vsi->user_param + (msix_vect - 1);
1798
1799                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1800                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1801         }
1802         I40E_WRITE_FLUSH(hw);
1803 }
1804
1805 static void
1806 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1807                        int base_queue, int nb_queue,
1808                        uint16_t itr_idx)
1809 {
1810         int i;
1811         uint32_t val;
1812         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1813         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1814
1815         /* Bind all RX queues to allocated MSIX interrupt */
1816         for (i = 0; i < nb_queue; i++) {
1817                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1818                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1819                         ((base_queue + i + 1) <<
1820                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1821                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1822                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1823
1824                 if (i == nb_queue - 1)
1825                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1826                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1827         }
1828
1829         /* Write first RX queue to Link list register as the head element */
1830         if (vsi->type != I40E_VSI_SRIOV) {
1831                 uint16_t interval =
1832                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,
1833                                                pf->support_multi_driver);
1834
1835                 if (msix_vect == I40E_MISC_VEC_ID) {
1836                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1837                                        (base_queue <<
1838                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1839                                        (0x0 <<
1840                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1841                         I40E_WRITE_REG(hw,
1842                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1843                                        interval);
1844                 } else {
1845                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1846                                        (base_queue <<
1847                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1848                                        (0x0 <<
1849                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1850                         I40E_WRITE_REG(hw,
1851                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1852                                                        msix_vect - 1),
1853                                        interval);
1854                 }
1855         } else {
1856                 uint32_t reg;
1857
1858                 if (msix_vect == I40E_MISC_VEC_ID) {
1859                         I40E_WRITE_REG(hw,
1860                                        I40E_VPINT_LNKLST0(vsi->user_param),
1861                                        (base_queue <<
1862                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1863                                        (0x0 <<
1864                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1865                 } else {
1866                         /* num_msix_vectors_vf needs to minus irq0 */
1867                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1868                                 vsi->user_param + (msix_vect - 1);
1869
1870                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1871                                        (base_queue <<
1872                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1873                                        (0x0 <<
1874                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1875                 }
1876         }
1877
1878         I40E_WRITE_FLUSH(hw);
1879 }
1880
1881 void
1882 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1883 {
1884         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1885         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1886         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1887         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1888         uint16_t msix_vect = vsi->msix_intr;
1889         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1890         uint16_t queue_idx = 0;
1891         int record = 0;
1892         int i;
1893
1894         for (i = 0; i < vsi->nb_qps; i++) {
1895                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1896                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1897         }
1898
1899         /* VF bind interrupt */
1900         if (vsi->type == I40E_VSI_SRIOV) {
1901                 __vsi_queues_bind_intr(vsi, msix_vect,
1902                                        vsi->base_queue, vsi->nb_qps,
1903                                        itr_idx);
1904                 return;
1905         }
1906
1907         /* PF & VMDq bind interrupt */
1908         if (rte_intr_dp_is_en(intr_handle)) {
1909                 if (vsi->type == I40E_VSI_MAIN) {
1910                         queue_idx = 0;
1911                         record = 1;
1912                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1913                         struct i40e_vsi *main_vsi =
1914                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1915                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1916                         record = 1;
1917                 }
1918         }
1919
1920         for (i = 0; i < vsi->nb_used_qps; i++) {
1921                 if (nb_msix <= 1) {
1922                         if (!rte_intr_allow_others(intr_handle))
1923                                 /* allow to share MISC_VEC_ID */
1924                                 msix_vect = I40E_MISC_VEC_ID;
1925
1926                         /* no enough msix_vect, map all to one */
1927                         __vsi_queues_bind_intr(vsi, msix_vect,
1928                                                vsi->base_queue + i,
1929                                                vsi->nb_used_qps - i,
1930                                                itr_idx);
1931                         for (; !!record && i < vsi->nb_used_qps; i++)
1932                                 intr_handle->intr_vec[queue_idx + i] =
1933                                         msix_vect;
1934                         break;
1935                 }
1936                 /* 1:1 queue/msix_vect mapping */
1937                 __vsi_queues_bind_intr(vsi, msix_vect,
1938                                        vsi->base_queue + i, 1,
1939                                        itr_idx);
1940                 if (!!record)
1941                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1942
1943                 msix_vect++;
1944                 nb_msix--;
1945         }
1946 }
1947
1948 static void
1949 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1950 {
1951         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1952         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1953         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1954         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1955         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1956         uint16_t msix_intr, i;
1957
1958         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1959                 for (i = 0; i < vsi->nb_msix; i++) {
1960                         msix_intr = vsi->msix_intr + i;
1961                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1962                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1963                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1964                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1965                 }
1966         else
1967                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1968                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1969                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1970                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1971
1972         I40E_WRITE_FLUSH(hw);
1973 }
1974
1975 static void
1976 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1977 {
1978         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1979         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1980         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1981         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1982         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1983         uint16_t msix_intr, i;
1984
1985         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1986                 for (i = 0; i < vsi->nb_msix; i++) {
1987                         msix_intr = vsi->msix_intr + i;
1988                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1989                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1990                 }
1991         else
1992                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1993                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1994
1995         I40E_WRITE_FLUSH(hw);
1996 }
1997
1998 static inline uint8_t
1999 i40e_parse_link_speeds(uint16_t link_speeds)
2000 {
2001         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2002
2003         if (link_speeds & ETH_LINK_SPEED_40G)
2004                 link_speed |= I40E_LINK_SPEED_40GB;
2005         if (link_speeds & ETH_LINK_SPEED_25G)
2006                 link_speed |= I40E_LINK_SPEED_25GB;
2007         if (link_speeds & ETH_LINK_SPEED_20G)
2008                 link_speed |= I40E_LINK_SPEED_20GB;
2009         if (link_speeds & ETH_LINK_SPEED_10G)
2010                 link_speed |= I40E_LINK_SPEED_10GB;
2011         if (link_speeds & ETH_LINK_SPEED_1G)
2012                 link_speed |= I40E_LINK_SPEED_1GB;
2013         if (link_speeds & ETH_LINK_SPEED_100M)
2014                 link_speed |= I40E_LINK_SPEED_100MB;
2015
2016         return link_speed;
2017 }
2018
2019 static int
2020 i40e_phy_conf_link(struct i40e_hw *hw,
2021                    uint8_t abilities,
2022                    uint8_t force_speed,
2023                    bool is_up)
2024 {
2025         enum i40e_status_code status;
2026         struct i40e_aq_get_phy_abilities_resp phy_ab;
2027         struct i40e_aq_set_phy_config phy_conf;
2028         enum i40e_aq_phy_type cnt;
2029         uint32_t phy_type_mask = 0;
2030
2031         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2032                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2033                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2034                         I40E_AQ_PHY_FLAG_LOW_POWER;
2035         const uint8_t advt = I40E_LINK_SPEED_40GB |
2036                         I40E_LINK_SPEED_25GB |
2037                         I40E_LINK_SPEED_10GB |
2038                         I40E_LINK_SPEED_1GB |
2039                         I40E_LINK_SPEED_100MB;
2040         int ret = -ENOTSUP;
2041
2042
2043         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2044                                               NULL);
2045         if (status)
2046                 return ret;
2047
2048         /* If link already up, no need to set up again */
2049         if (is_up && phy_ab.phy_type != 0)
2050                 return I40E_SUCCESS;
2051
2052         memset(&phy_conf, 0, sizeof(phy_conf));
2053
2054         /* bits 0-2 use the values from get_phy_abilities_resp */
2055         abilities &= ~mask;
2056         abilities |= phy_ab.abilities & mask;
2057
2058         /* update ablities and speed */
2059         if (abilities & I40E_AQ_PHY_AN_ENABLED)
2060                 phy_conf.link_speed = advt;
2061         else
2062                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
2063
2064         phy_conf.abilities = abilities;
2065
2066
2067
2068         /* To enable link, phy_type mask needs to include each type */
2069         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
2070                 phy_type_mask |= 1 << cnt;
2071
2072         /* use get_phy_abilities_resp value for the rest */
2073         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2074         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2075                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2076                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2077         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2078         phy_conf.eee_capability = phy_ab.eee_capability;
2079         phy_conf.eeer = phy_ab.eeer_val;
2080         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2081
2082         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2083                     phy_ab.abilities, phy_ab.link_speed);
2084         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2085                     phy_conf.abilities, phy_conf.link_speed);
2086
2087         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2088         if (status)
2089                 return ret;
2090
2091         return I40E_SUCCESS;
2092 }
2093
2094 static int
2095 i40e_apply_link_speed(struct rte_eth_dev *dev)
2096 {
2097         uint8_t speed;
2098         uint8_t abilities = 0;
2099         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100         struct rte_eth_conf *conf = &dev->data->dev_conf;
2101
2102         speed = i40e_parse_link_speeds(conf->link_speeds);
2103         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2104         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2105                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2106         abilities |= I40E_AQ_PHY_LINK_ENABLED;
2107
2108         return i40e_phy_conf_link(hw, abilities, speed, true);
2109 }
2110
2111 static int
2112 i40e_dev_start(struct rte_eth_dev *dev)
2113 {
2114         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2115         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2116         struct i40e_vsi *main_vsi = pf->main_vsi;
2117         int ret, i;
2118         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2119         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2120         uint32_t intr_vector = 0;
2121         struct i40e_vsi *vsi;
2122
2123         hw->adapter_stopped = 0;
2124
2125         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2126                 PMD_INIT_LOG(ERR,
2127                 "Invalid link_speeds for port %u, autonegotiation disabled",
2128                               dev->data->port_id);
2129                 return -EINVAL;
2130         }
2131
2132         rte_intr_disable(intr_handle);
2133
2134         if ((rte_intr_cap_multiple(intr_handle) ||
2135              !RTE_ETH_DEV_SRIOV(dev).active) &&
2136             dev->data->dev_conf.intr_conf.rxq != 0) {
2137                 intr_vector = dev->data->nb_rx_queues;
2138                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2139                 if (ret)
2140                         return ret;
2141         }
2142
2143         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2144                 intr_handle->intr_vec =
2145                         rte_zmalloc("intr_vec",
2146                                     dev->data->nb_rx_queues * sizeof(int),
2147                                     0);
2148                 if (!intr_handle->intr_vec) {
2149                         PMD_INIT_LOG(ERR,
2150                                 "Failed to allocate %d rx_queues intr_vec",
2151                                 dev->data->nb_rx_queues);
2152                         return -ENOMEM;
2153                 }
2154         }
2155
2156         /* Initialize VSI */
2157         ret = i40e_dev_rxtx_init(pf);
2158         if (ret != I40E_SUCCESS) {
2159                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2160                 goto err_up;
2161         }
2162
2163         /* Map queues with MSIX interrupt */
2164         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2165                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2166         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2167         i40e_vsi_enable_queues_intr(main_vsi);
2168
2169         /* Map VMDQ VSI queues with MSIX interrupt */
2170         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2171                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2172                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2173                                           I40E_ITR_INDEX_DEFAULT);
2174                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2175         }
2176
2177         /* enable FDIR MSIX interrupt */
2178         if (pf->fdir.fdir_vsi) {
2179                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2180                                           I40E_ITR_INDEX_NONE);
2181                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2182         }
2183
2184         /* Enable all queues which have been configured */
2185         ret = i40e_dev_switch_queues(pf, TRUE);
2186         if (ret != I40E_SUCCESS) {
2187                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2188                 goto err_up;
2189         }
2190
2191         /* Enable receiving broadcast packets */
2192         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2193         if (ret != I40E_SUCCESS)
2194                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2195
2196         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2197                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2198                                                 true, NULL);
2199                 if (ret != I40E_SUCCESS)
2200                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2201         }
2202
2203         /* Enable the VLAN promiscuous mode. */
2204         if (pf->vfs) {
2205                 for (i = 0; i < pf->vf_num; i++) {
2206                         vsi = pf->vfs[i].vsi;
2207                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2208                                                      true, NULL);
2209                 }
2210         }
2211
2212         /* Enable mac loopback mode */
2213         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2214             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2215                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2216                 if (ret != I40E_SUCCESS) {
2217                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2218                         goto err_up;
2219                 }
2220         }
2221
2222         /* Apply link configure */
2223         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2224                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2225                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2226                                 ETH_LINK_SPEED_40G)) {
2227                 PMD_DRV_LOG(ERR, "Invalid link setting");
2228                 goto err_up;
2229         }
2230         ret = i40e_apply_link_speed(dev);
2231         if (I40E_SUCCESS != ret) {
2232                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2233                 goto err_up;
2234         }
2235
2236         if (!rte_intr_allow_others(intr_handle)) {
2237                 rte_intr_callback_unregister(intr_handle,
2238                                              i40e_dev_interrupt_handler,
2239                                              (void *)dev);
2240                 /* configure and enable device interrupt */
2241                 i40e_pf_config_irq0(hw, FALSE);
2242                 i40e_pf_enable_irq0(hw);
2243
2244                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2245                         PMD_INIT_LOG(INFO,
2246                                 "lsc won't enable because of no intr multiplex");
2247         } else {
2248                 ret = i40e_aq_set_phy_int_mask(hw,
2249                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2250                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2251                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2252                 if (ret != I40E_SUCCESS)
2253                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2254
2255                 /* Call get_link_info aq commond to enable/disable LSE */
2256                 i40e_dev_link_update(dev, 0);
2257         }
2258
2259         /* enable uio intr after callback register */
2260         rte_intr_enable(intr_handle);
2261
2262         i40e_filter_restore(pf);
2263
2264         if (pf->tm_conf.root && !pf->tm_conf.committed)
2265                 PMD_DRV_LOG(WARNING,
2266                             "please call hierarchy_commit() "
2267                             "before starting the port");
2268
2269         return I40E_SUCCESS;
2270
2271 err_up:
2272         i40e_dev_switch_queues(pf, FALSE);
2273         i40e_dev_clear_queues(dev);
2274
2275         return ret;
2276 }
2277
2278 static void
2279 i40e_dev_stop(struct rte_eth_dev *dev)
2280 {
2281         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2282         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2283         struct i40e_vsi *main_vsi = pf->main_vsi;
2284         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2285         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2286         int i;
2287
2288         if (hw->adapter_stopped == 1)
2289                 return;
2290         /* Disable all queues */
2291         i40e_dev_switch_queues(pf, FALSE);
2292
2293         /* un-map queues with interrupt registers */
2294         i40e_vsi_disable_queues_intr(main_vsi);
2295         i40e_vsi_queues_unbind_intr(main_vsi);
2296
2297         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2298                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2299                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2300         }
2301
2302         if (pf->fdir.fdir_vsi) {
2303                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2304                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2305         }
2306         /* Clear all queues and release memory */
2307         i40e_dev_clear_queues(dev);
2308
2309         /* Set link down */
2310         i40e_dev_set_link_down(dev);
2311
2312         if (!rte_intr_allow_others(intr_handle))
2313                 /* resume to the default handler */
2314                 rte_intr_callback_register(intr_handle,
2315                                            i40e_dev_interrupt_handler,
2316                                            (void *)dev);
2317
2318         /* Clean datapath event and queue/vec mapping */
2319         rte_intr_efd_disable(intr_handle);
2320         if (intr_handle->intr_vec) {
2321                 rte_free(intr_handle->intr_vec);
2322                 intr_handle->intr_vec = NULL;
2323         }
2324
2325         /* reset hierarchy commit */
2326         pf->tm_conf.committed = false;
2327
2328         hw->adapter_stopped = 1;
2329 }
2330
2331 static void
2332 i40e_dev_close(struct rte_eth_dev *dev)
2333 {
2334         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2335         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2336         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2337         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2338         struct i40e_mirror_rule *p_mirror;
2339         uint32_t reg;
2340         int i;
2341         int ret;
2342
2343         PMD_INIT_FUNC_TRACE();
2344
2345         i40e_dev_stop(dev);
2346
2347         /* Remove all mirror rules */
2348         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2349                 ret = i40e_aq_del_mirror_rule(hw,
2350                                               pf->main_vsi->veb->seid,
2351                                               p_mirror->rule_type,
2352                                               p_mirror->entries,
2353                                               p_mirror->num_entries,
2354                                               p_mirror->id);
2355                 if (ret < 0)
2356                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2357                                     "status = %d, aq_err = %d.", ret,
2358                                     hw->aq.asq_last_status);
2359
2360                 /* remove mirror software resource anyway */
2361                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2362                 rte_free(p_mirror);
2363                 pf->nb_mirror_rule--;
2364         }
2365
2366         i40e_dev_free_queues(dev);
2367
2368         /* Disable interrupt */
2369         i40e_pf_disable_irq0(hw);
2370         rte_intr_disable(intr_handle);
2371
2372         /* shutdown and destroy the HMC */
2373         i40e_shutdown_lan_hmc(hw);
2374
2375         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2376                 i40e_vsi_release(pf->vmdq[i].vsi);
2377                 pf->vmdq[i].vsi = NULL;
2378         }
2379         rte_free(pf->vmdq);
2380         pf->vmdq = NULL;
2381
2382         /* release all the existing VSIs and VEBs */
2383         i40e_fdir_teardown(pf);
2384         i40e_vsi_release(pf->main_vsi);
2385
2386         /* shutdown the adminq */
2387         i40e_aq_queue_shutdown(hw, true);
2388         i40e_shutdown_adminq(hw);
2389
2390         i40e_res_pool_destroy(&pf->qp_pool);
2391         i40e_res_pool_destroy(&pf->msix_pool);
2392
2393         /* Disable flexible payload in global configuration */
2394         if (!pf->support_multi_driver)
2395                 i40e_flex_payload_reg_set_default(hw);
2396
2397         /* force a PF reset to clean anything leftover */
2398         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2399         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2400                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2401         I40E_WRITE_FLUSH(hw);
2402 }
2403
2404 /*
2405  * Reset PF device only to re-initialize resources in PMD layer
2406  */
2407 static int
2408 i40e_dev_reset(struct rte_eth_dev *dev)
2409 {
2410         int ret;
2411
2412         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2413          * its VF to make them align with it. The detailed notification
2414          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2415          * To avoid unexpected behavior in VF, currently reset of PF with
2416          * SR-IOV activation is not supported. It might be supported later.
2417          */
2418         if (dev->data->sriov.active)
2419                 return -ENOTSUP;
2420
2421         ret = eth_i40e_dev_uninit(dev);
2422         if (ret)
2423                 return ret;
2424
2425         ret = eth_i40e_dev_init(dev, NULL);
2426
2427         return ret;
2428 }
2429
2430 static void
2431 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2432 {
2433         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2434         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435         struct i40e_vsi *vsi = pf->main_vsi;
2436         int status;
2437
2438         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2439                                                      true, NULL, true);
2440         if (status != I40E_SUCCESS)
2441                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2442
2443         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2444                                                         TRUE, NULL);
2445         if (status != I40E_SUCCESS)
2446                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2447
2448 }
2449
2450 static void
2451 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2452 {
2453         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2454         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2455         struct i40e_vsi *vsi = pf->main_vsi;
2456         int status;
2457
2458         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2459                                                      false, NULL, true);
2460         if (status != I40E_SUCCESS)
2461                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2462
2463         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2464                                                         false, NULL);
2465         if (status != I40E_SUCCESS)
2466                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2467 }
2468
2469 static void
2470 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2471 {
2472         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2473         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2474         struct i40e_vsi *vsi = pf->main_vsi;
2475         int ret;
2476
2477         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2478         if (ret != I40E_SUCCESS)
2479                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2480 }
2481
2482 static void
2483 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2484 {
2485         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2486         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2487         struct i40e_vsi *vsi = pf->main_vsi;
2488         int ret;
2489
2490         if (dev->data->promiscuous == 1)
2491                 return; /* must remain in all_multicast mode */
2492
2493         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2494                                 vsi->seid, FALSE, NULL);
2495         if (ret != I40E_SUCCESS)
2496                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2497 }
2498
2499 /*
2500  * Set device link up.
2501  */
2502 static int
2503 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2504 {
2505         /* re-apply link speed setting */
2506         return i40e_apply_link_speed(dev);
2507 }
2508
2509 /*
2510  * Set device link down.
2511  */
2512 static int
2513 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2514 {
2515         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2516         uint8_t abilities = 0;
2517         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2518
2519         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2520         return i40e_phy_conf_link(hw, abilities, speed, false);
2521 }
2522
2523 static __rte_always_inline void
2524 update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link)
2525 {
2526 /* Link status registers and values*/
2527 #define I40E_PRTMAC_LINKSTA             0x001E2420
2528 #define I40E_REG_LINK_UP                0x40000080
2529 #define I40E_PRTMAC_MACC                0x001E24E0
2530 #define I40E_REG_MACC_25GB              0x00020000
2531 #define I40E_REG_SPEED_MASK             0x38000000
2532 #define I40E_REG_SPEED_100MB            0x00000000
2533 #define I40E_REG_SPEED_1GB              0x08000000
2534 #define I40E_REG_SPEED_10GB             0x10000000
2535 #define I40E_REG_SPEED_20GB             0x20000000
2536 #define I40E_REG_SPEED_25_40GB          0x18000000
2537         uint32_t link_speed;
2538         uint32_t reg_val;
2539
2540         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2541         link_speed = reg_val & I40E_REG_SPEED_MASK;
2542         reg_val &= I40E_REG_LINK_UP;
2543         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2544
2545         if (unlikely(link->link_status == 0))
2546                 return;
2547
2548         /* Parse the link status */
2549         switch (link_speed) {
2550         case I40E_REG_SPEED_100MB:
2551                 link->link_speed = ETH_SPEED_NUM_100M;
2552                 break;
2553         case I40E_REG_SPEED_1GB:
2554                 link->link_speed = ETH_SPEED_NUM_1G;
2555                 break;
2556         case I40E_REG_SPEED_10GB:
2557                 link->link_speed = ETH_SPEED_NUM_10G;
2558                 break;
2559         case I40E_REG_SPEED_20GB:
2560                 link->link_speed = ETH_SPEED_NUM_20G;
2561                 break;
2562         case I40E_REG_SPEED_25_40GB:
2563                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2564
2565                 if (reg_val & I40E_REG_MACC_25GB)
2566                         link->link_speed = ETH_SPEED_NUM_25G;
2567                 else
2568                         link->link_speed = ETH_SPEED_NUM_40G;
2569
2570                 break;
2571         default:
2572                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2573                 break;
2574         }
2575 }
2576
2577 static __rte_always_inline void
2578 update_link_wait(struct i40e_hw *hw, struct rte_eth_link *link,
2579         bool enable_lse)
2580 {
2581 #define CHECK_INTERVAL             100  /* 100ms */
2582 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2583         uint32_t rep_cnt = MAX_REPEAT_TIME;
2584         struct i40e_link_status link_status;
2585         int status;
2586
2587         memset(&link_status, 0, sizeof(link_status));
2588
2589         do {
2590                 memset(&link_status, 0, sizeof(link_status));
2591
2592                 /* Get link status information from hardware */
2593                 status = i40e_aq_get_link_info(hw, enable_lse,
2594                                                 &link_status, NULL);
2595                 if (unlikely(status != I40E_SUCCESS)) {
2596                         link->link_speed = ETH_SPEED_NUM_100M;
2597                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2598                         PMD_DRV_LOG(ERR, "Failed to get link info");
2599                         return;
2600                 }
2601
2602                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2603                 if (unlikely(link->link_status != 0))
2604                         break;
2605
2606                 rte_delay_ms(CHECK_INTERVAL);
2607         } while (--rep_cnt);
2608
2609         /* Parse the link status */
2610         switch (link_status.link_speed) {
2611         case I40E_LINK_SPEED_100MB:
2612                 link->link_speed = ETH_SPEED_NUM_100M;
2613                 break;
2614         case I40E_LINK_SPEED_1GB:
2615                 link->link_speed = ETH_SPEED_NUM_1G;
2616                 break;
2617         case I40E_LINK_SPEED_10GB:
2618                 link->link_speed = ETH_SPEED_NUM_10G;
2619                 break;
2620         case I40E_LINK_SPEED_20GB:
2621                 link->link_speed = ETH_SPEED_NUM_20G;
2622                 break;
2623         case I40E_LINK_SPEED_25GB:
2624                 link->link_speed = ETH_SPEED_NUM_25G;
2625                 break;
2626         case I40E_LINK_SPEED_40GB:
2627                 link->link_speed = ETH_SPEED_NUM_40G;
2628                 break;
2629         default:
2630                 link->link_speed = ETH_SPEED_NUM_100M;
2631                 break;
2632         }
2633 }
2634
2635 int
2636 i40e_dev_link_update(struct rte_eth_dev *dev,
2637                      int wait_to_complete)
2638 {
2639         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640         struct rte_eth_link link;
2641         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2642         int ret;
2643
2644         memset(&link, 0, sizeof(link));
2645
2646         /* i40e uses full duplex only */
2647         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2648         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2649                         ETH_LINK_SPEED_FIXED);
2650
2651         if (!wait_to_complete)
2652                 update_link_no_wait(hw, &link);
2653         else
2654                 update_link_wait(hw, &link, enable_lse);
2655
2656         ret = rte_eth_linkstatus_set(dev, &link);
2657         i40e_notify_all_vfs_link_status(dev);
2658
2659         return ret;
2660 }
2661
2662 /* Get all the statistics of a VSI */
2663 void
2664 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2665 {
2666         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2667         struct i40e_eth_stats *nes = &vsi->eth_stats;
2668         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2669         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2670
2671         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2672                             vsi->offset_loaded, &oes->rx_bytes,
2673                             &nes->rx_bytes);
2674         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2675                             vsi->offset_loaded, &oes->rx_unicast,
2676                             &nes->rx_unicast);
2677         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2678                             vsi->offset_loaded, &oes->rx_multicast,
2679                             &nes->rx_multicast);
2680         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2681                             vsi->offset_loaded, &oes->rx_broadcast,
2682                             &nes->rx_broadcast);
2683         /* exclude CRC bytes */
2684         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2685                 nes->rx_broadcast) * ETHER_CRC_LEN;
2686
2687         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2688                             &oes->rx_discards, &nes->rx_discards);
2689         /* GLV_REPC not supported */
2690         /* GLV_RMPC not supported */
2691         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2692                             &oes->rx_unknown_protocol,
2693                             &nes->rx_unknown_protocol);
2694         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2695                             vsi->offset_loaded, &oes->tx_bytes,
2696                             &nes->tx_bytes);
2697         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2698                             vsi->offset_loaded, &oes->tx_unicast,
2699                             &nes->tx_unicast);
2700         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2701                             vsi->offset_loaded, &oes->tx_multicast,
2702                             &nes->tx_multicast);
2703         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2704                             vsi->offset_loaded,  &oes->tx_broadcast,
2705                             &nes->tx_broadcast);
2706         /* GLV_TDPC not supported */
2707         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2708                             &oes->tx_errors, &nes->tx_errors);
2709         vsi->offset_loaded = true;
2710
2711         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2712                     vsi->vsi_id);
2713         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2714         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2715         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2716         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2717         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2718         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2719                     nes->rx_unknown_protocol);
2720         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2721         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2722         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2723         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2724         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2725         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2726         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2727                     vsi->vsi_id);
2728 }
2729
2730 static void
2731 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2732 {
2733         unsigned int i;
2734         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2735         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2736
2737         /* Get rx/tx bytes of internal transfer packets */
2738         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2739                         I40E_GLV_GORCL(hw->port),
2740                         pf->offset_loaded,
2741                         &pf->internal_stats_offset.rx_bytes,
2742                         &pf->internal_stats.rx_bytes);
2743
2744         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2745                         I40E_GLV_GOTCL(hw->port),
2746                         pf->offset_loaded,
2747                         &pf->internal_stats_offset.tx_bytes,
2748                         &pf->internal_stats.tx_bytes);
2749         /* Get total internal rx packet count */
2750         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2751                             I40E_GLV_UPRCL(hw->port),
2752                             pf->offset_loaded,
2753                             &pf->internal_stats_offset.rx_unicast,
2754                             &pf->internal_stats.rx_unicast);
2755         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2756                             I40E_GLV_MPRCL(hw->port),
2757                             pf->offset_loaded,
2758                             &pf->internal_stats_offset.rx_multicast,
2759                             &pf->internal_stats.rx_multicast);
2760         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2761                             I40E_GLV_BPRCL(hw->port),
2762                             pf->offset_loaded,
2763                             &pf->internal_stats_offset.rx_broadcast,
2764                             &pf->internal_stats.rx_broadcast);
2765         /* Get total internal tx packet count */
2766         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2767                             I40E_GLV_UPTCL(hw->port),
2768                             pf->offset_loaded,
2769                             &pf->internal_stats_offset.tx_unicast,
2770                             &pf->internal_stats.tx_unicast);
2771         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2772                             I40E_GLV_MPTCL(hw->port),
2773                             pf->offset_loaded,
2774                             &pf->internal_stats_offset.tx_multicast,
2775                             &pf->internal_stats.tx_multicast);
2776         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2777                             I40E_GLV_BPTCL(hw->port),
2778                             pf->offset_loaded,
2779                             &pf->internal_stats_offset.tx_broadcast,
2780                             &pf->internal_stats.tx_broadcast);
2781
2782         /* exclude CRC size */
2783         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2784                 pf->internal_stats.rx_multicast +
2785                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2786
2787         /* Get statistics of struct i40e_eth_stats */
2788         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2789                             I40E_GLPRT_GORCL(hw->port),
2790                             pf->offset_loaded, &os->eth.rx_bytes,
2791                             &ns->eth.rx_bytes);
2792         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2793                             I40E_GLPRT_UPRCL(hw->port),
2794                             pf->offset_loaded, &os->eth.rx_unicast,
2795                             &ns->eth.rx_unicast);
2796         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2797                             I40E_GLPRT_MPRCL(hw->port),
2798                             pf->offset_loaded, &os->eth.rx_multicast,
2799                             &ns->eth.rx_multicast);
2800         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2801                             I40E_GLPRT_BPRCL(hw->port),
2802                             pf->offset_loaded, &os->eth.rx_broadcast,
2803                             &ns->eth.rx_broadcast);
2804         /* Workaround: CRC size should not be included in byte statistics,
2805          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2806          */
2807         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2808                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2809
2810         /* exclude internal rx bytes
2811          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2812          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2813          * value.
2814          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2815          */
2816         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2817                 ns->eth.rx_bytes = 0;
2818         else
2819                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2820
2821         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2822                 ns->eth.rx_unicast = 0;
2823         else
2824                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2825
2826         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2827                 ns->eth.rx_multicast = 0;
2828         else
2829                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2830
2831         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2832                 ns->eth.rx_broadcast = 0;
2833         else
2834                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2835
2836         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2837                             pf->offset_loaded, &os->eth.rx_discards,
2838                             &ns->eth.rx_discards);
2839         /* GLPRT_REPC not supported */
2840         /* GLPRT_RMPC not supported */
2841         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2842                             pf->offset_loaded,
2843                             &os->eth.rx_unknown_protocol,
2844                             &ns->eth.rx_unknown_protocol);
2845         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2846                             I40E_GLPRT_GOTCL(hw->port),
2847                             pf->offset_loaded, &os->eth.tx_bytes,
2848                             &ns->eth.tx_bytes);
2849         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2850                             I40E_GLPRT_UPTCL(hw->port),
2851                             pf->offset_loaded, &os->eth.tx_unicast,
2852                             &ns->eth.tx_unicast);
2853         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2854                             I40E_GLPRT_MPTCL(hw->port),
2855                             pf->offset_loaded, &os->eth.tx_multicast,
2856                             &ns->eth.tx_multicast);
2857         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2858                             I40E_GLPRT_BPTCL(hw->port),
2859                             pf->offset_loaded, &os->eth.tx_broadcast,
2860                             &ns->eth.tx_broadcast);
2861         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2862                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2863
2864         /* exclude internal tx bytes
2865          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2866          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2867          * value.
2868          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2869          */
2870         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2871                 ns->eth.tx_bytes = 0;
2872         else
2873                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2874
2875         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2876                 ns->eth.tx_unicast = 0;
2877         else
2878                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2879
2880         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2881                 ns->eth.tx_multicast = 0;
2882         else
2883                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2884
2885         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2886                 ns->eth.tx_broadcast = 0;
2887         else
2888                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2889
2890         /* GLPRT_TEPC not supported */
2891
2892         /* additional port specific stats */
2893         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2894                             pf->offset_loaded, &os->tx_dropped_link_down,
2895                             &ns->tx_dropped_link_down);
2896         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2897                             pf->offset_loaded, &os->crc_errors,
2898                             &ns->crc_errors);
2899         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2900                             pf->offset_loaded, &os->illegal_bytes,
2901                             &ns->illegal_bytes);
2902         /* GLPRT_ERRBC not supported */
2903         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2904                             pf->offset_loaded, &os->mac_local_faults,
2905                             &ns->mac_local_faults);
2906         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2907                             pf->offset_loaded, &os->mac_remote_faults,
2908                             &ns->mac_remote_faults);
2909         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2910                             pf->offset_loaded, &os->rx_length_errors,
2911                             &ns->rx_length_errors);
2912         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2913                             pf->offset_loaded, &os->link_xon_rx,
2914                             &ns->link_xon_rx);
2915         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2916                             pf->offset_loaded, &os->link_xoff_rx,
2917                             &ns->link_xoff_rx);
2918         for (i = 0; i < 8; i++) {
2919                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2920                                     pf->offset_loaded,
2921                                     &os->priority_xon_rx[i],
2922                                     &ns->priority_xon_rx[i]);
2923                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2924                                     pf->offset_loaded,
2925                                     &os->priority_xoff_rx[i],
2926                                     &ns->priority_xoff_rx[i]);
2927         }
2928         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2929                             pf->offset_loaded, &os->link_xon_tx,
2930                             &ns->link_xon_tx);
2931         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2932                             pf->offset_loaded, &os->link_xoff_tx,
2933                             &ns->link_xoff_tx);
2934         for (i = 0; i < 8; i++) {
2935                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2936                                     pf->offset_loaded,
2937                                     &os->priority_xon_tx[i],
2938                                     &ns->priority_xon_tx[i]);
2939                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2940                                     pf->offset_loaded,
2941                                     &os->priority_xoff_tx[i],
2942                                     &ns->priority_xoff_tx[i]);
2943                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2944                                     pf->offset_loaded,
2945                                     &os->priority_xon_2_xoff[i],
2946                                     &ns->priority_xon_2_xoff[i]);
2947         }
2948         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2949                             I40E_GLPRT_PRC64L(hw->port),
2950                             pf->offset_loaded, &os->rx_size_64,
2951                             &ns->rx_size_64);
2952         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2953                             I40E_GLPRT_PRC127L(hw->port),
2954                             pf->offset_loaded, &os->rx_size_127,
2955                             &ns->rx_size_127);
2956         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2957                             I40E_GLPRT_PRC255L(hw->port),
2958                             pf->offset_loaded, &os->rx_size_255,
2959                             &ns->rx_size_255);
2960         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2961                             I40E_GLPRT_PRC511L(hw->port),
2962                             pf->offset_loaded, &os->rx_size_511,
2963                             &ns->rx_size_511);
2964         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2965                             I40E_GLPRT_PRC1023L(hw->port),
2966                             pf->offset_loaded, &os->rx_size_1023,
2967                             &ns->rx_size_1023);
2968         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2969                             I40E_GLPRT_PRC1522L(hw->port),
2970                             pf->offset_loaded, &os->rx_size_1522,
2971                             &ns->rx_size_1522);
2972         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2973                             I40E_GLPRT_PRC9522L(hw->port),
2974                             pf->offset_loaded, &os->rx_size_big,
2975                             &ns->rx_size_big);
2976         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2977                             pf->offset_loaded, &os->rx_undersize,
2978                             &ns->rx_undersize);
2979         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2980                             pf->offset_loaded, &os->rx_fragments,
2981                             &ns->rx_fragments);
2982         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2983                             pf->offset_loaded, &os->rx_oversize,
2984                             &ns->rx_oversize);
2985         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2986                             pf->offset_loaded, &os->rx_jabber,
2987                             &ns->rx_jabber);
2988         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2989                             I40E_GLPRT_PTC64L(hw->port),
2990                             pf->offset_loaded, &os->tx_size_64,
2991                             &ns->tx_size_64);
2992         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2993                             I40E_GLPRT_PTC127L(hw->port),
2994                             pf->offset_loaded, &os->tx_size_127,
2995                             &ns->tx_size_127);
2996         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2997                             I40E_GLPRT_PTC255L(hw->port),
2998                             pf->offset_loaded, &os->tx_size_255,
2999                             &ns->tx_size_255);
3000         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3001                             I40E_GLPRT_PTC511L(hw->port),
3002                             pf->offset_loaded, &os->tx_size_511,
3003                             &ns->tx_size_511);
3004         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3005                             I40E_GLPRT_PTC1023L(hw->port),
3006                             pf->offset_loaded, &os->tx_size_1023,
3007                             &ns->tx_size_1023);
3008         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3009                             I40E_GLPRT_PTC1522L(hw->port),
3010                             pf->offset_loaded, &os->tx_size_1522,
3011                             &ns->tx_size_1522);
3012         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3013                             I40E_GLPRT_PTC9522L(hw->port),
3014                             pf->offset_loaded, &os->tx_size_big,
3015                             &ns->tx_size_big);
3016         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3017                            pf->offset_loaded,
3018                            &os->fd_sb_match, &ns->fd_sb_match);
3019         /* GLPRT_MSPDC not supported */
3020         /* GLPRT_XEC not supported */
3021
3022         pf->offset_loaded = true;
3023
3024         if (pf->main_vsi)
3025                 i40e_update_vsi_stats(pf->main_vsi);
3026 }
3027
3028 /* Get all statistics of a port */
3029 static int
3030 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3031 {
3032         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3033         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3034         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3035         unsigned i;
3036
3037         /* call read registers - updates values, now write them to struct */
3038         i40e_read_stats_registers(pf, hw);
3039
3040         stats->ipackets = ns->eth.rx_unicast +
3041                         ns->eth.rx_multicast +
3042                         ns->eth.rx_broadcast -
3043                         ns->eth.rx_discards -
3044                         pf->main_vsi->eth_stats.rx_discards;
3045         stats->opackets = ns->eth.tx_unicast +
3046                         ns->eth.tx_multicast +
3047                         ns->eth.tx_broadcast;
3048         stats->ibytes   = ns->eth.rx_bytes;
3049         stats->obytes   = ns->eth.tx_bytes;
3050         stats->oerrors  = ns->eth.tx_errors +
3051                         pf->main_vsi->eth_stats.tx_errors;
3052
3053         /* Rx Errors */
3054         stats->imissed  = ns->eth.rx_discards +
3055                         pf->main_vsi->eth_stats.rx_discards;
3056         stats->ierrors  = ns->crc_errors +
3057                         ns->rx_length_errors + ns->rx_undersize +
3058                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3059
3060         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3061         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3062         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3063         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3064         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3065         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3066         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3067                     ns->eth.rx_unknown_protocol);
3068         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3069         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3070         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3071         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3072         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3073         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3074
3075         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3076                     ns->tx_dropped_link_down);
3077         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3078         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3079                     ns->illegal_bytes);
3080         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3081         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3082                     ns->mac_local_faults);
3083         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3084                     ns->mac_remote_faults);
3085         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3086                     ns->rx_length_errors);
3087         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3088         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3089         for (i = 0; i < 8; i++) {
3090                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3091                                 i, ns->priority_xon_rx[i]);
3092                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3093                                 i, ns->priority_xoff_rx[i]);
3094         }
3095         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3096         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3097         for (i = 0; i < 8; i++) {
3098                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3099                                 i, ns->priority_xon_tx[i]);
3100                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3101                                 i, ns->priority_xoff_tx[i]);
3102                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3103                                 i, ns->priority_xon_2_xoff[i]);
3104         }
3105         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3106         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3107         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3108         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3109         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3110         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3111         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3112         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3113         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3114         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3115         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3116         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3117         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3118         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3119         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3120         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3121         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3122         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3123         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3124                         ns->mac_short_packet_dropped);
3125         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3126                     ns->checksum_error);
3127         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3128         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3129         return 0;
3130 }
3131
3132 /* Reset the statistics */
3133 static void
3134 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3135 {
3136         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3137         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3138
3139         /* Mark PF and VSI stats to update the offset, aka "reset" */
3140         pf->offset_loaded = false;
3141         if (pf->main_vsi)
3142                 pf->main_vsi->offset_loaded = false;
3143
3144         /* read the stats, reading current register values into offset */
3145         i40e_read_stats_registers(pf, hw);
3146 }
3147
3148 static uint32_t
3149 i40e_xstats_calc_num(void)
3150 {
3151         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3152                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3153                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3154 }
3155
3156 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3157                                      struct rte_eth_xstat_name *xstats_names,
3158                                      __rte_unused unsigned limit)
3159 {
3160         unsigned count = 0;
3161         unsigned i, prio;
3162
3163         if (xstats_names == NULL)
3164                 return i40e_xstats_calc_num();
3165
3166         /* Note: limit checked in rte_eth_xstats_names() */
3167
3168         /* Get stats from i40e_eth_stats struct */
3169         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3170                 snprintf(xstats_names[count].name,
3171                          sizeof(xstats_names[count].name),
3172                          "%s", rte_i40e_stats_strings[i].name);
3173                 count++;
3174         }
3175
3176         /* Get individiual stats from i40e_hw_port struct */
3177         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3178                 snprintf(xstats_names[count].name,
3179                         sizeof(xstats_names[count].name),
3180                          "%s", rte_i40e_hw_port_strings[i].name);
3181                 count++;
3182         }
3183
3184         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3185                 for (prio = 0; prio < 8; prio++) {
3186                         snprintf(xstats_names[count].name,
3187                                  sizeof(xstats_names[count].name),
3188                                  "rx_priority%u_%s", prio,
3189                                  rte_i40e_rxq_prio_strings[i].name);
3190                         count++;
3191                 }
3192         }
3193
3194         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3195                 for (prio = 0; prio < 8; prio++) {
3196                         snprintf(xstats_names[count].name,
3197                                  sizeof(xstats_names[count].name),
3198                                  "tx_priority%u_%s", prio,
3199                                  rte_i40e_txq_prio_strings[i].name);
3200                         count++;
3201                 }
3202         }
3203         return count;
3204 }
3205
3206 static int
3207 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3208                     unsigned n)
3209 {
3210         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3211         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3212         unsigned i, count, prio;
3213         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3214
3215         count = i40e_xstats_calc_num();
3216         if (n < count)
3217                 return count;
3218
3219         i40e_read_stats_registers(pf, hw);
3220
3221         if (xstats == NULL)
3222                 return 0;
3223
3224         count = 0;
3225
3226         /* Get stats from i40e_eth_stats struct */
3227         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3228                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3229                         rte_i40e_stats_strings[i].offset);
3230                 xstats[count].id = count;
3231                 count++;
3232         }
3233
3234         /* Get individiual stats from i40e_hw_port struct */
3235         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3236                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3237                         rte_i40e_hw_port_strings[i].offset);
3238                 xstats[count].id = count;
3239                 count++;
3240         }
3241
3242         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3243                 for (prio = 0; prio < 8; prio++) {
3244                         xstats[count].value =
3245                                 *(uint64_t *)(((char *)hw_stats) +
3246                                 rte_i40e_rxq_prio_strings[i].offset +
3247                                 (sizeof(uint64_t) * prio));
3248                         xstats[count].id = count;
3249                         count++;
3250                 }
3251         }
3252
3253         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3254                 for (prio = 0; prio < 8; prio++) {
3255                         xstats[count].value =
3256                                 *(uint64_t *)(((char *)hw_stats) +
3257                                 rte_i40e_txq_prio_strings[i].offset +
3258                                 (sizeof(uint64_t) * prio));
3259                         xstats[count].id = count;
3260                         count++;
3261                 }
3262         }
3263
3264         return count;
3265 }
3266
3267 static int
3268 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3269                                  __rte_unused uint16_t queue_id,
3270                                  __rte_unused uint8_t stat_idx,
3271                                  __rte_unused uint8_t is_rx)
3272 {
3273         PMD_INIT_FUNC_TRACE();
3274
3275         return -ENOSYS;
3276 }
3277
3278 static int
3279 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3280 {
3281         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3282         u32 full_ver;
3283         u8 ver, patch;
3284         u16 build;
3285         int ret;
3286
3287         full_ver = hw->nvm.oem_ver;
3288         ver = (u8)(full_ver >> 24);
3289         build = (u16)((full_ver >> 8) & 0xffff);
3290         patch = (u8)(full_ver & 0xff);
3291
3292         ret = snprintf(fw_version, fw_size,
3293                  "%d.%d%d 0x%08x %d.%d.%d",
3294                  ((hw->nvm.version >> 12) & 0xf),
3295                  ((hw->nvm.version >> 4) & 0xff),
3296                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3297                  ver, build, patch);
3298
3299         ret += 1; /* add the size of '\0' */
3300         if (fw_size < (u32)ret)
3301                 return ret;
3302         else
3303                 return 0;
3304 }
3305
3306 static void
3307 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3308 {
3309         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3310         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3311         struct i40e_vsi *vsi = pf->main_vsi;
3312         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3313
3314         dev_info->max_rx_queues = vsi->nb_qps;
3315         dev_info->max_tx_queues = vsi->nb_qps;
3316         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3317         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3318         dev_info->max_mac_addrs = vsi->max_macaddrs;
3319         dev_info->max_vfs = pci_dev->max_vfs;
3320         dev_info->rx_queue_offload_capa = 0;
3321         dev_info->rx_offload_capa =
3322                 DEV_RX_OFFLOAD_VLAN_STRIP |
3323                 DEV_RX_OFFLOAD_QINQ_STRIP |
3324                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3325                 DEV_RX_OFFLOAD_UDP_CKSUM |
3326                 DEV_RX_OFFLOAD_TCP_CKSUM |
3327                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3328                 DEV_RX_OFFLOAD_CRC_STRIP |
3329                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3330                 DEV_RX_OFFLOAD_VLAN_FILTER |
3331                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3332
3333         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3334         dev_info->tx_offload_capa =
3335                 DEV_TX_OFFLOAD_VLAN_INSERT |
3336                 DEV_TX_OFFLOAD_QINQ_INSERT |
3337                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3338                 DEV_TX_OFFLOAD_UDP_CKSUM |
3339                 DEV_TX_OFFLOAD_TCP_CKSUM |
3340                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3341                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3342                 DEV_TX_OFFLOAD_TCP_TSO |
3343                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3344                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3345                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3346                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3347                 DEV_TX_OFFLOAD_MULTI_SEGS |
3348                 dev_info->tx_queue_offload_capa;
3349         dev_info->dev_capa =
3350                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3351                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3352
3353         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3354                                                 sizeof(uint32_t);
3355         dev_info->reta_size = pf->hash_lut_size;
3356         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3357
3358         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3359                 .rx_thresh = {
3360                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3361                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3362                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3363                 },
3364                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3365                 .rx_drop_en = 0,
3366                 .offloads = 0,
3367         };
3368
3369         dev_info->default_txconf = (struct rte_eth_txconf) {
3370                 .tx_thresh = {
3371                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3372                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3373                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3374                 },
3375                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3376                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3377                 .offloads = 0,
3378         };
3379
3380         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3381                 .nb_max = I40E_MAX_RING_DESC,
3382                 .nb_min = I40E_MIN_RING_DESC,
3383                 .nb_align = I40E_ALIGN_RING_DESC,
3384         };
3385
3386         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3387                 .nb_max = I40E_MAX_RING_DESC,
3388                 .nb_min = I40E_MIN_RING_DESC,
3389                 .nb_align = I40E_ALIGN_RING_DESC,
3390                 .nb_seg_max = I40E_TX_MAX_SEG,
3391                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3392         };
3393
3394         if (pf->flags & I40E_FLAG_VMDQ) {
3395                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3396                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3397                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3398                                                 pf->max_nb_vmdq_vsi;
3399                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3400                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3401                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3402         }
3403
3404         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3405                 /* For XL710 */
3406                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3407                 dev_info->default_rxportconf.nb_queues = 2;
3408                 dev_info->default_txportconf.nb_queues = 2;
3409                 if (dev->data->nb_rx_queues == 1)
3410                         dev_info->default_rxportconf.ring_size = 2048;
3411                 else
3412                         dev_info->default_rxportconf.ring_size = 1024;
3413                 if (dev->data->nb_tx_queues == 1)
3414                         dev_info->default_txportconf.ring_size = 1024;
3415                 else
3416                         dev_info->default_txportconf.ring_size = 512;
3417
3418         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3419                 /* For XXV710 */
3420                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3421                 dev_info->default_rxportconf.nb_queues = 1;
3422                 dev_info->default_txportconf.nb_queues = 1;
3423                 dev_info->default_rxportconf.ring_size = 256;
3424                 dev_info->default_txportconf.ring_size = 256;
3425         } else {
3426                 /* For X710 */
3427                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3428                 dev_info->default_rxportconf.nb_queues = 1;
3429                 dev_info->default_txportconf.nb_queues = 1;
3430                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3431                         dev_info->default_rxportconf.ring_size = 512;
3432                         dev_info->default_txportconf.ring_size = 256;
3433                 } else {
3434                         dev_info->default_rxportconf.ring_size = 256;
3435                         dev_info->default_txportconf.ring_size = 256;
3436                 }
3437         }
3438         dev_info->default_rxportconf.burst_size = 32;
3439         dev_info->default_txportconf.burst_size = 32;
3440 }
3441
3442 static int
3443 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3444 {
3445         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3446         struct i40e_vsi *vsi = pf->main_vsi;
3447         PMD_INIT_FUNC_TRACE();
3448
3449         if (on)
3450                 return i40e_vsi_add_vlan(vsi, vlan_id);
3451         else
3452                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3453 }
3454
3455 static int
3456 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3457                                 enum rte_vlan_type vlan_type,
3458                                 uint16_t tpid, int qinq)
3459 {
3460         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3461         uint64_t reg_r = 0;
3462         uint64_t reg_w = 0;
3463         uint16_t reg_id = 3;
3464         int ret;
3465
3466         if (qinq) {
3467                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3468                         reg_id = 2;
3469         }
3470
3471         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3472                                           &reg_r, NULL);
3473         if (ret != I40E_SUCCESS) {
3474                 PMD_DRV_LOG(ERR,
3475                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3476                            reg_id);
3477                 return -EIO;
3478         }
3479         PMD_DRV_LOG(DEBUG,
3480                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3481                     reg_id, reg_r);
3482
3483         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3484         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3485         if (reg_r == reg_w) {
3486                 PMD_DRV_LOG(DEBUG, "No need to write");
3487                 return 0;
3488         }
3489
3490         ret = i40e_aq_debug_write_global_register(hw,
3491                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3492                                            reg_w, NULL);
3493         if (ret != I40E_SUCCESS) {
3494                 PMD_DRV_LOG(ERR,
3495                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3496                             reg_id);
3497                 return -EIO;
3498         }
3499         PMD_DRV_LOG(DEBUG,
3500                     "Global register 0x%08x is changed with value 0x%08x",
3501                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3502
3503         i40e_global_cfg_warning(I40E_WARNING_TPID);
3504
3505         return 0;
3506 }
3507
3508 static int
3509 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3510                    enum rte_vlan_type vlan_type,
3511                    uint16_t tpid)
3512 {
3513         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3515         int qinq = dev->data->dev_conf.rxmode.offloads &
3516                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3517         int ret = 0;
3518
3519         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3520              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3521             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3522                 PMD_DRV_LOG(ERR,
3523                             "Unsupported vlan type.");
3524                 return -EINVAL;
3525         }
3526
3527         if (pf->support_multi_driver) {
3528                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3529                 return -ENOTSUP;
3530         }
3531
3532         /* 802.1ad frames ability is added in NVM API 1.7*/
3533         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3534                 if (qinq) {
3535                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3536                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3537                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3538                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3539                 } else {
3540                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3541                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3542                 }
3543                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3544                 if (ret != I40E_SUCCESS) {
3545                         PMD_DRV_LOG(ERR,
3546                                     "Set switch config failed aq_err: %d",
3547                                     hw->aq.asq_last_status);
3548                         ret = -EIO;
3549                 }
3550         } else
3551                 /* If NVM API < 1.7, keep the register setting */
3552                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3553                                                       tpid, qinq);
3554
3555         return ret;
3556 }
3557
3558 static int
3559 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3560 {
3561         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3562         struct i40e_vsi *vsi = pf->main_vsi;
3563         struct rte_eth_rxmode *rxmode;
3564
3565         rxmode = &dev->data->dev_conf.rxmode;
3566         if (mask & ETH_VLAN_FILTER_MASK) {
3567                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3568                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3569                 else
3570                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3571         }
3572
3573         if (mask & ETH_VLAN_STRIP_MASK) {
3574                 /* Enable or disable VLAN stripping */
3575                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3576                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3577                 else
3578                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3579         }
3580
3581         if (mask & ETH_VLAN_EXTEND_MASK) {
3582                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3583                         i40e_vsi_config_double_vlan(vsi, TRUE);
3584                         /* Set global registers with default ethertype. */
3585                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3586                                            ETHER_TYPE_VLAN);
3587                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3588                                            ETHER_TYPE_VLAN);
3589                 }
3590                 else
3591                         i40e_vsi_config_double_vlan(vsi, FALSE);
3592         }
3593
3594         return 0;
3595 }
3596
3597 static void
3598 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3599                           __rte_unused uint16_t queue,
3600                           __rte_unused int on)
3601 {
3602         PMD_INIT_FUNC_TRACE();
3603 }
3604
3605 static int
3606 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3607 {
3608         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3609         struct i40e_vsi *vsi = pf->main_vsi;
3610         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3611         struct i40e_vsi_vlan_pvid_info info;
3612
3613         memset(&info, 0, sizeof(info));
3614         info.on = on;
3615         if (info.on)
3616                 info.config.pvid = pvid;
3617         else {
3618                 info.config.reject.tagged =
3619                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3620                 info.config.reject.untagged =
3621                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3622         }
3623
3624         return i40e_vsi_vlan_pvid_set(vsi, &info);
3625 }
3626
3627 static int
3628 i40e_dev_led_on(struct rte_eth_dev *dev)
3629 {
3630         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3631         uint32_t mode = i40e_led_get(hw);
3632
3633         if (mode == 0)
3634                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3635
3636         return 0;
3637 }
3638
3639 static int
3640 i40e_dev_led_off(struct rte_eth_dev *dev)
3641 {
3642         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3643         uint32_t mode = i40e_led_get(hw);
3644
3645         if (mode != 0)
3646                 i40e_led_set(hw, 0, false);
3647
3648         return 0;
3649 }
3650
3651 static int
3652 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3653 {
3654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3655         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3656
3657         fc_conf->pause_time = pf->fc_conf.pause_time;
3658
3659         /* read out from register, in case they are modified by other port */
3660         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3661                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3662         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3663                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3664
3665         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3666         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3667
3668          /* Return current mode according to actual setting*/
3669         switch (hw->fc.current_mode) {
3670         case I40E_FC_FULL:
3671                 fc_conf->mode = RTE_FC_FULL;
3672                 break;
3673         case I40E_FC_TX_PAUSE:
3674                 fc_conf->mode = RTE_FC_TX_PAUSE;
3675                 break;
3676         case I40E_FC_RX_PAUSE:
3677                 fc_conf->mode = RTE_FC_RX_PAUSE;
3678                 break;
3679         case I40E_FC_NONE:
3680         default:
3681                 fc_conf->mode = RTE_FC_NONE;
3682         };
3683
3684         return 0;
3685 }
3686
3687 static int
3688 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3689 {
3690         uint32_t mflcn_reg, fctrl_reg, reg;
3691         uint32_t max_high_water;
3692         uint8_t i, aq_failure;
3693         int err;
3694         struct i40e_hw *hw;
3695         struct i40e_pf *pf;
3696         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3697                 [RTE_FC_NONE] = I40E_FC_NONE,
3698                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3699                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3700                 [RTE_FC_FULL] = I40E_FC_FULL
3701         };
3702
3703         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3704
3705         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3706         if ((fc_conf->high_water > max_high_water) ||
3707                         (fc_conf->high_water < fc_conf->low_water)) {
3708                 PMD_INIT_LOG(ERR,
3709                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3710                         max_high_water);
3711                 return -EINVAL;
3712         }
3713
3714         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3715         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3716         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3717
3718         pf->fc_conf.pause_time = fc_conf->pause_time;
3719         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3720         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3721
3722         PMD_INIT_FUNC_TRACE();
3723
3724         /* All the link flow control related enable/disable register
3725          * configuration is handle by the F/W
3726          */
3727         err = i40e_set_fc(hw, &aq_failure, true);
3728         if (err < 0)
3729                 return -ENOSYS;
3730
3731         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3732                 /* Configure flow control refresh threshold,
3733                  * the value for stat_tx_pause_refresh_timer[8]
3734                  * is used for global pause operation.
3735                  */
3736
3737                 I40E_WRITE_REG(hw,
3738                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3739                                pf->fc_conf.pause_time);
3740
3741                 /* configure the timer value included in transmitted pause
3742                  * frame,
3743                  * the value for stat_tx_pause_quanta[8] is used for global
3744                  * pause operation
3745                  */
3746                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3747                                pf->fc_conf.pause_time);
3748
3749                 fctrl_reg = I40E_READ_REG(hw,
3750                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3751
3752                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3753                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3754                 else
3755                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3756
3757                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3758                                fctrl_reg);
3759         } else {
3760                 /* Configure pause time (2 TCs per register) */
3761                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3762                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3763                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3764
3765                 /* Configure flow control refresh threshold value */
3766                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3767                                pf->fc_conf.pause_time / 2);
3768
3769                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3770
3771                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3772                  *depending on configuration
3773                  */
3774                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3775                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3776                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3777                 } else {
3778                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3779                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3780                 }
3781
3782                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3783         }
3784
3785         if (!pf->support_multi_driver) {
3786                 /* config water marker both based on the packets and bytes */
3787                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3788                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3789                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3790                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3791                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3792                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3793                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3794                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3795                                   << I40E_KILOSHIFT);
3796                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3797                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3798                                    << I40E_KILOSHIFT);
3799                 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3800         } else {
3801                 PMD_DRV_LOG(ERR,
3802                             "Water marker configuration is not supported.");
3803         }
3804
3805         I40E_WRITE_FLUSH(hw);
3806
3807         return 0;
3808 }
3809
3810 static int
3811 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3812                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3813 {
3814         PMD_INIT_FUNC_TRACE();
3815
3816         return -ENOSYS;
3817 }
3818
3819 /* Add a MAC address, and update filters */
3820 static int
3821 i40e_macaddr_add(struct rte_eth_dev *dev,
3822                  struct ether_addr *mac_addr,
3823                  __rte_unused uint32_t index,
3824                  uint32_t pool)
3825 {
3826         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3827         struct i40e_mac_filter_info mac_filter;
3828         struct i40e_vsi *vsi;
3829         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3830         int ret;
3831
3832         /* If VMDQ not enabled or configured, return */
3833         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3834                           !pf->nb_cfg_vmdq_vsi)) {
3835                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3836                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3837                         pool);
3838                 return -ENOTSUP;
3839         }
3840
3841         if (pool > pf->nb_cfg_vmdq_vsi) {
3842                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3843                                 pool, pf->nb_cfg_vmdq_vsi);
3844                 return -EINVAL;
3845         }
3846
3847         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3848         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3849                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3850         else
3851                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3852
3853         if (pool == 0)
3854                 vsi = pf->main_vsi;
3855         else
3856                 vsi = pf->vmdq[pool - 1].vsi;
3857
3858         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3859         if (ret != I40E_SUCCESS) {
3860                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3861                 return -ENODEV;
3862         }
3863         return 0;
3864 }
3865
3866 /* Remove a MAC address, and update filters */
3867 static void
3868 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3869 {
3870         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3871         struct i40e_vsi *vsi;
3872         struct rte_eth_dev_data *data = dev->data;
3873         struct ether_addr *macaddr;
3874         int ret;
3875         uint32_t i;
3876         uint64_t pool_sel;
3877
3878         macaddr = &(data->mac_addrs[index]);
3879
3880         pool_sel = dev->data->mac_pool_sel[index];
3881
3882         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3883                 if (pool_sel & (1ULL << i)) {
3884                         if (i == 0)
3885                                 vsi = pf->main_vsi;
3886                         else {
3887                                 /* No VMDQ pool enabled or configured */
3888                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3889                                         (i > pf->nb_cfg_vmdq_vsi)) {
3890                                         PMD_DRV_LOG(ERR,
3891                                                 "No VMDQ pool enabled/configured");
3892                                         return;
3893                                 }
3894                                 vsi = pf->vmdq[i - 1].vsi;
3895                         }
3896                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3897
3898                         if (ret) {
3899                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3900                                 return;
3901                         }
3902                 }
3903         }
3904 }
3905
3906 /* Set perfect match or hash match of MAC and VLAN for a VF */
3907 static int
3908 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3909                  struct rte_eth_mac_filter *filter,
3910                  bool add)
3911 {
3912         struct i40e_hw *hw;
3913         struct i40e_mac_filter_info mac_filter;
3914         struct ether_addr old_mac;
3915         struct ether_addr *new_mac;
3916         struct i40e_pf_vf *vf = NULL;
3917         uint16_t vf_id;
3918         int ret;
3919
3920         if (pf == NULL) {
3921                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3922                 return -EINVAL;
3923         }
3924         hw = I40E_PF_TO_HW(pf);
3925
3926         if (filter == NULL) {
3927                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3928                 return -EINVAL;
3929         }
3930
3931         new_mac = &filter->mac_addr;
3932
3933         if (is_zero_ether_addr(new_mac)) {
3934                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3935                 return -EINVAL;
3936         }
3937
3938         vf_id = filter->dst_id;
3939
3940         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3941                 PMD_DRV_LOG(ERR, "Invalid argument.");
3942                 return -EINVAL;
3943         }
3944         vf = &pf->vfs[vf_id];
3945
3946         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3947                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3948                 return -EINVAL;
3949         }
3950
3951         if (add) {
3952                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3953                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3954                                 ETHER_ADDR_LEN);
3955                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3956                                  ETHER_ADDR_LEN);
3957
3958                 mac_filter.filter_type = filter->filter_type;
3959                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3960                 if (ret != I40E_SUCCESS) {
3961                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3962                         return -1;
3963                 }
3964                 ether_addr_copy(new_mac, &pf->dev_addr);
3965         } else {
3966                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3967                                 ETHER_ADDR_LEN);
3968                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3969                 if (ret != I40E_SUCCESS) {
3970                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3971                         return -1;
3972                 }
3973
3974                 /* Clear device address as it has been removed */
3975                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3976                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3977         }
3978
3979         return 0;
3980 }
3981
3982 /* MAC filter handle */
3983 static int
3984 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3985                 void *arg)
3986 {
3987         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3988         struct rte_eth_mac_filter *filter;
3989         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3990         int ret = I40E_NOT_SUPPORTED;
3991
3992         filter = (struct rte_eth_mac_filter *)(arg);
3993
3994         switch (filter_op) {
3995         case RTE_ETH_FILTER_NOP:
3996                 ret = I40E_SUCCESS;
3997                 break;
3998         case RTE_ETH_FILTER_ADD:
3999                 i40e_pf_disable_irq0(hw);
4000                 if (filter->is_vf)
4001                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4002                 i40e_pf_enable_irq0(hw);
4003                 break;
4004         case RTE_ETH_FILTER_DELETE:
4005                 i40e_pf_disable_irq0(hw);
4006                 if (filter->is_vf)
4007                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4008                 i40e_pf_enable_irq0(hw);
4009                 break;
4010         default:
4011                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4012                 ret = I40E_ERR_PARAM;
4013                 break;
4014         }
4015
4016         return ret;
4017 }
4018
4019 static int
4020 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4021 {
4022         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4023         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4024         uint32_t reg;
4025         int ret;
4026
4027         if (!lut)
4028                 return -EINVAL;
4029
4030         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4031                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4032                                           lut, lut_size);
4033                 if (ret) {
4034                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4035                         return ret;
4036                 }
4037         } else {
4038                 uint32_t *lut_dw = (uint32_t *)lut;
4039                 uint16_t i, lut_size_dw = lut_size / 4;
4040
4041                 if (vsi->type == I40E_VSI_SRIOV) {
4042                         for (i = 0; i <= lut_size_dw; i++) {
4043                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4044                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4045                         }
4046                 } else {
4047                         for (i = 0; i < lut_size_dw; i++)
4048                                 lut_dw[i] = I40E_READ_REG(hw,
4049                                                           I40E_PFQF_HLUT(i));
4050                 }
4051         }
4052
4053         return 0;
4054 }
4055
4056 int
4057 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4058 {
4059         struct i40e_pf *pf;
4060         struct i40e_hw *hw;
4061         int ret;
4062
4063         if (!vsi || !lut)
4064                 return -EINVAL;
4065
4066         pf = I40E_VSI_TO_PF(vsi);
4067         hw = I40E_VSI_TO_HW(vsi);
4068
4069         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4070                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4071                                           lut, lut_size);
4072                 if (ret) {
4073                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4074                         return ret;
4075                 }
4076         } else {
4077                 uint32_t *lut_dw = (uint32_t *)lut;
4078                 uint16_t i, lut_size_dw = lut_size / 4;
4079
4080                 if (vsi->type == I40E_VSI_SRIOV) {
4081                         for (i = 0; i < lut_size_dw; i++)
4082                                 I40E_WRITE_REG(
4083                                         hw,
4084                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4085                                         lut_dw[i]);
4086                 } else {
4087                         for (i = 0; i < lut_size_dw; i++)
4088                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4089                                                lut_dw[i]);
4090                 }
4091                 I40E_WRITE_FLUSH(hw);
4092         }
4093
4094         return 0;
4095 }
4096
4097 static int
4098 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4099                          struct rte_eth_rss_reta_entry64 *reta_conf,
4100                          uint16_t reta_size)
4101 {
4102         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4103         uint16_t i, lut_size = pf->hash_lut_size;
4104         uint16_t idx, shift;
4105         uint8_t *lut;
4106         int ret;
4107
4108         if (reta_size != lut_size ||
4109                 reta_size > ETH_RSS_RETA_SIZE_512) {
4110                 PMD_DRV_LOG(ERR,
4111                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4112                         reta_size, lut_size);
4113                 return -EINVAL;
4114         }
4115
4116         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4117         if (!lut) {
4118                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4119                 return -ENOMEM;
4120         }
4121         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4122         if (ret)
4123                 goto out;
4124         for (i = 0; i < reta_size; i++) {
4125                 idx = i / RTE_RETA_GROUP_SIZE;
4126                 shift = i % RTE_RETA_GROUP_SIZE;
4127                 if (reta_conf[idx].mask & (1ULL << shift))
4128                         lut[i] = reta_conf[idx].reta[shift];
4129         }
4130         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4131
4132 out:
4133         rte_free(lut);
4134
4135         return ret;
4136 }
4137
4138 static int
4139 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4140                         struct rte_eth_rss_reta_entry64 *reta_conf,
4141                         uint16_t reta_size)
4142 {
4143         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4144         uint16_t i, lut_size = pf->hash_lut_size;
4145         uint16_t idx, shift;
4146         uint8_t *lut;
4147         int ret;
4148
4149         if (reta_size != lut_size ||
4150                 reta_size > ETH_RSS_RETA_SIZE_512) {
4151                 PMD_DRV_LOG(ERR,
4152                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4153                         reta_size, lut_size);
4154                 return -EINVAL;
4155         }
4156
4157         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4158         if (!lut) {
4159                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4160                 return -ENOMEM;
4161         }
4162
4163         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4164         if (ret)
4165                 goto out;
4166         for (i = 0; i < reta_size; i++) {
4167                 idx = i / RTE_RETA_GROUP_SIZE;
4168                 shift = i % RTE_RETA_GROUP_SIZE;
4169                 if (reta_conf[idx].mask & (1ULL << shift))
4170                         reta_conf[idx].reta[shift] = lut[i];
4171         }
4172
4173 out:
4174         rte_free(lut);
4175
4176         return ret;
4177 }
4178
4179 /**
4180  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4181  * @hw:   pointer to the HW structure
4182  * @mem:  pointer to mem struct to fill out
4183  * @size: size of memory requested
4184  * @alignment: what to align the allocation to
4185  **/
4186 enum i40e_status_code
4187 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4188                         struct i40e_dma_mem *mem,
4189                         u64 size,
4190                         u32 alignment)
4191 {
4192         const struct rte_memzone *mz = NULL;
4193         char z_name[RTE_MEMZONE_NAMESIZE];
4194
4195         if (!mem)
4196                 return I40E_ERR_PARAM;
4197
4198         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4199         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4200                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4201         if (!mz)
4202                 return I40E_ERR_NO_MEMORY;
4203
4204         mem->size = size;
4205         mem->va = mz->addr;
4206         mem->pa = mz->iova;
4207         mem->zone = (const void *)mz;
4208         PMD_DRV_LOG(DEBUG,
4209                 "memzone %s allocated with physical address: %"PRIu64,
4210                 mz->name, mem->pa);
4211
4212         return I40E_SUCCESS;
4213 }
4214
4215 /**
4216  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4217  * @hw:   pointer to the HW structure
4218  * @mem:  ptr to mem struct to free
4219  **/
4220 enum i40e_status_code
4221 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4222                     struct i40e_dma_mem *mem)
4223 {
4224         if (!mem)
4225                 return I40E_ERR_PARAM;
4226
4227         PMD_DRV_LOG(DEBUG,
4228                 "memzone %s to be freed with physical address: %"PRIu64,
4229                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4230         rte_memzone_free((const struct rte_memzone *)mem->zone);
4231         mem->zone = NULL;
4232         mem->va = NULL;
4233         mem->pa = (u64)0;
4234
4235         return I40E_SUCCESS;
4236 }
4237
4238 /**
4239  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4240  * @hw:   pointer to the HW structure
4241  * @mem:  pointer to mem struct to fill out
4242  * @size: size of memory requested
4243  **/
4244 enum i40e_status_code
4245 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4246                          struct i40e_virt_mem *mem,
4247                          u32 size)
4248 {
4249         if (!mem)
4250                 return I40E_ERR_PARAM;
4251
4252         mem->size = size;
4253         mem->va = rte_zmalloc("i40e", size, 0);
4254
4255         if (mem->va)
4256                 return I40E_SUCCESS;
4257         else
4258                 return I40E_ERR_NO_MEMORY;
4259 }
4260
4261 /**
4262  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4263  * @hw:   pointer to the HW structure
4264  * @mem:  pointer to mem struct to free
4265  **/
4266 enum i40e_status_code
4267 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4268                      struct i40e_virt_mem *mem)
4269 {
4270         if (!mem)
4271                 return I40E_ERR_PARAM;
4272
4273         rte_free(mem->va);
4274         mem->va = NULL;
4275
4276         return I40E_SUCCESS;
4277 }
4278
4279 void
4280 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4281 {
4282         rte_spinlock_init(&sp->spinlock);
4283 }
4284
4285 void
4286 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4287 {
4288         rte_spinlock_lock(&sp->spinlock);
4289 }
4290
4291 void
4292 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4293 {
4294         rte_spinlock_unlock(&sp->spinlock);
4295 }
4296
4297 void
4298 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4299 {
4300         return;
4301 }
4302
4303 /**
4304  * Get the hardware capabilities, which will be parsed
4305  * and saved into struct i40e_hw.
4306  */
4307 static int
4308 i40e_get_cap(struct i40e_hw *hw)
4309 {
4310         struct i40e_aqc_list_capabilities_element_resp *buf;
4311         uint16_t len, size = 0;
4312         int ret;
4313
4314         /* Calculate a huge enough buff for saving response data temporarily */
4315         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4316                                                 I40E_MAX_CAP_ELE_NUM;
4317         buf = rte_zmalloc("i40e", len, 0);
4318         if (!buf) {
4319                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4320                 return I40E_ERR_NO_MEMORY;
4321         }
4322
4323         /* Get, parse the capabilities and save it to hw */
4324         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4325                         i40e_aqc_opc_list_func_capabilities, NULL);
4326         if (ret != I40E_SUCCESS)
4327                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4328
4329         /* Free the temporary buffer after being used */
4330         rte_free(buf);
4331
4332         return ret;
4333 }
4334
4335 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4336 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
4337
4338 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4339                 const char *value,
4340                 void *opaque)
4341 {
4342         struct i40e_pf *pf;
4343         unsigned long num;
4344         char *end;
4345
4346         pf = (struct i40e_pf *)opaque;
4347         RTE_SET_USED(key);
4348
4349         errno = 0;
4350         num = strtoul(value, &end, 0);
4351         if (errno != 0 || end == value || *end != 0) {
4352                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4353                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4354                 return -(EINVAL);
4355         }
4356
4357         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4358                 pf->vf_nb_qp_max = (uint16_t)num;
4359         else
4360                 /* here return 0 to make next valid same argument work */
4361                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4362                             "power of 2 and equal or less than 16 !, Now it is "
4363                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4364
4365         return 0;
4366 }
4367
4368 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4369 {
4370         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4371         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4372         struct rte_kvargs *kvlist;
4373
4374         /* set default queue number per VF as 4 */
4375         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4376
4377         if (dev->device->devargs == NULL)
4378                 return 0;
4379
4380         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4381         if (kvlist == NULL)
4382                 return -(EINVAL);
4383
4384         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4385                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4386                             "the first invalid or last valid one is used !",
4387                             QUEUE_NUM_PER_VF_ARG);
4388
4389         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4390                            i40e_pf_parse_vf_queue_number_handler, pf);
4391
4392         rte_kvargs_free(kvlist);
4393
4394         return 0;
4395 }
4396
4397 static int
4398 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4399 {
4400         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4401         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4402         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4403         uint16_t qp_count = 0, vsi_count = 0;
4404
4405         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4406                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4407                 return -EINVAL;
4408         }
4409
4410         i40e_pf_config_vf_rxq_number(dev);
4411
4412         /* Add the parameter init for LFC */
4413         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4414         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4415         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4416
4417         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4418         pf->max_num_vsi = hw->func_caps.num_vsis;
4419         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4420         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4421
4422         /* FDir queue/VSI allocation */
4423         pf->fdir_qp_offset = 0;
4424         if (hw->func_caps.fd) {
4425                 pf->flags |= I40E_FLAG_FDIR;
4426                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4427         } else {
4428                 pf->fdir_nb_qps = 0;
4429         }
4430         qp_count += pf->fdir_nb_qps;
4431         vsi_count += 1;
4432
4433         /* LAN queue/VSI allocation */
4434         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4435         if (!hw->func_caps.rss) {
4436                 pf->lan_nb_qps = 1;
4437         } else {
4438                 pf->flags |= I40E_FLAG_RSS;
4439                 if (hw->mac.type == I40E_MAC_X722)
4440                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4441                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4442         }
4443         qp_count += pf->lan_nb_qps;
4444         vsi_count += 1;
4445
4446         /* VF queue/VSI allocation */
4447         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4448         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4449                 pf->flags |= I40E_FLAG_SRIOV;
4450                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4451                 pf->vf_num = pci_dev->max_vfs;
4452                 PMD_DRV_LOG(DEBUG,
4453                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4454                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4455         } else {
4456                 pf->vf_nb_qps = 0;
4457                 pf->vf_num = 0;
4458         }
4459         qp_count += pf->vf_nb_qps * pf->vf_num;
4460         vsi_count += pf->vf_num;
4461
4462         /* VMDq queue/VSI allocation */
4463         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4464         pf->vmdq_nb_qps = 0;
4465         pf->max_nb_vmdq_vsi = 0;
4466         if (hw->func_caps.vmdq) {
4467                 if (qp_count < hw->func_caps.num_tx_qp &&
4468                         vsi_count < hw->func_caps.num_vsis) {
4469                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4470                                 qp_count) / pf->vmdq_nb_qp_max;
4471
4472                         /* Limit the maximum number of VMDq vsi to the maximum
4473                          * ethdev can support
4474                          */
4475                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4476                                 hw->func_caps.num_vsis - vsi_count);
4477                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4478                                 ETH_64_POOLS);
4479                         if (pf->max_nb_vmdq_vsi) {
4480                                 pf->flags |= I40E_FLAG_VMDQ;
4481                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4482                                 PMD_DRV_LOG(DEBUG,
4483                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4484                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4485                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4486                         } else {
4487                                 PMD_DRV_LOG(INFO,
4488                                         "No enough queues left for VMDq");
4489                         }
4490                 } else {
4491                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4492                 }
4493         }
4494         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4495         vsi_count += pf->max_nb_vmdq_vsi;
4496
4497         if (hw->func_caps.dcb)
4498                 pf->flags |= I40E_FLAG_DCB;
4499
4500         if (qp_count > hw->func_caps.num_tx_qp) {
4501                 PMD_DRV_LOG(ERR,
4502                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4503                         qp_count, hw->func_caps.num_tx_qp);
4504                 return -EINVAL;
4505         }
4506         if (vsi_count > hw->func_caps.num_vsis) {
4507                 PMD_DRV_LOG(ERR,
4508                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4509                         vsi_count, hw->func_caps.num_vsis);
4510                 return -EINVAL;
4511         }
4512
4513         return 0;
4514 }
4515
4516 static int
4517 i40e_pf_get_switch_config(struct i40e_pf *pf)
4518 {
4519         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4520         struct i40e_aqc_get_switch_config_resp *switch_config;
4521         struct i40e_aqc_switch_config_element_resp *element;
4522         uint16_t start_seid = 0, num_reported;
4523         int ret;
4524
4525         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4526                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4527         if (!switch_config) {
4528                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4529                 return -ENOMEM;
4530         }
4531
4532         /* Get the switch configurations */
4533         ret = i40e_aq_get_switch_config(hw, switch_config,
4534                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4535         if (ret != I40E_SUCCESS) {
4536                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4537                 goto fail;
4538         }
4539         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4540         if (num_reported != 1) { /* The number should be 1 */
4541                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4542                 goto fail;
4543         }
4544
4545         /* Parse the switch configuration elements */
4546         element = &(switch_config->element[0]);
4547         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4548                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4549                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4550         } else
4551                 PMD_DRV_LOG(INFO, "Unknown element type");
4552
4553 fail:
4554         rte_free(switch_config);
4555
4556         return ret;
4557 }
4558
4559 static int
4560 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4561                         uint32_t num)
4562 {
4563         struct pool_entry *entry;
4564
4565         if (pool == NULL || num == 0)
4566                 return -EINVAL;
4567
4568         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4569         if (entry == NULL) {
4570                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4571                 return -ENOMEM;
4572         }
4573
4574         /* queue heap initialize */
4575         pool->num_free = num;
4576         pool->num_alloc = 0;
4577         pool->base = base;
4578         LIST_INIT(&pool->alloc_list);
4579         LIST_INIT(&pool->free_list);
4580
4581         /* Initialize element  */
4582         entry->base = 0;
4583         entry->len = num;
4584
4585         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4586         return 0;
4587 }
4588
4589 static void
4590 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4591 {
4592         struct pool_entry *entry, *next_entry;
4593
4594         if (pool == NULL)
4595                 return;
4596
4597         for (entry = LIST_FIRST(&pool->alloc_list);
4598                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4599                         entry = next_entry) {
4600                 LIST_REMOVE(entry, next);
4601                 rte_free(entry);
4602         }
4603
4604         for (entry = LIST_FIRST(&pool->free_list);
4605                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4606                         entry = next_entry) {
4607                 LIST_REMOVE(entry, next);
4608                 rte_free(entry);
4609         }
4610
4611         pool->num_free = 0;
4612         pool->num_alloc = 0;
4613         pool->base = 0;
4614         LIST_INIT(&pool->alloc_list);
4615         LIST_INIT(&pool->free_list);
4616 }
4617
4618 static int
4619 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4620                        uint32_t base)
4621 {
4622         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4623         uint32_t pool_offset;
4624         int insert;
4625
4626         if (pool == NULL) {
4627                 PMD_DRV_LOG(ERR, "Invalid parameter");
4628                 return -EINVAL;
4629         }
4630
4631         pool_offset = base - pool->base;
4632         /* Lookup in alloc list */
4633         LIST_FOREACH(entry, &pool->alloc_list, next) {
4634                 if (entry->base == pool_offset) {
4635                         valid_entry = entry;
4636                         LIST_REMOVE(entry, next);
4637                         break;
4638                 }
4639         }
4640
4641         /* Not find, return */
4642         if (valid_entry == NULL) {
4643                 PMD_DRV_LOG(ERR, "Failed to find entry");
4644                 return -EINVAL;
4645         }
4646
4647         /**
4648          * Found it, move it to free list  and try to merge.
4649          * In order to make merge easier, always sort it by qbase.
4650          * Find adjacent prev and last entries.
4651          */
4652         prev = next = NULL;
4653         LIST_FOREACH(entry, &pool->free_list, next) {
4654                 if (entry->base > valid_entry->base) {
4655                         next = entry;
4656                         break;
4657                 }
4658                 prev = entry;
4659         }
4660
4661         insert = 0;
4662         /* Try to merge with next one*/
4663         if (next != NULL) {
4664                 /* Merge with next one */
4665                 if (valid_entry->base + valid_entry->len == next->base) {
4666                         next->base = valid_entry->base;
4667                         next->len += valid_entry->len;
4668                         rte_free(valid_entry);
4669                         valid_entry = next;
4670                         insert = 1;
4671                 }
4672         }
4673
4674         if (prev != NULL) {
4675                 /* Merge with previous one */
4676                 if (prev->base + prev->len == valid_entry->base) {
4677                         prev->len += valid_entry->len;
4678                         /* If it merge with next one, remove next node */
4679                         if (insert == 1) {
4680                                 LIST_REMOVE(valid_entry, next);
4681                                 rte_free(valid_entry);
4682                         } else {
4683                                 rte_free(valid_entry);
4684                                 insert = 1;
4685                         }
4686                 }
4687         }
4688
4689         /* Not find any entry to merge, insert */
4690         if (insert == 0) {
4691                 if (prev != NULL)
4692                         LIST_INSERT_AFTER(prev, valid_entry, next);
4693                 else if (next != NULL)
4694                         LIST_INSERT_BEFORE(next, valid_entry, next);
4695                 else /* It's empty list, insert to head */
4696                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4697         }
4698
4699         pool->num_free += valid_entry->len;
4700         pool->num_alloc -= valid_entry->len;
4701
4702         return 0;
4703 }
4704
4705 static int
4706 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4707                        uint16_t num)
4708 {
4709         struct pool_entry *entry, *valid_entry;
4710
4711         if (pool == NULL || num == 0) {
4712                 PMD_DRV_LOG(ERR, "Invalid parameter");
4713                 return -EINVAL;
4714         }
4715
4716         if (pool->num_free < num) {
4717                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4718                             num, pool->num_free);
4719                 return -ENOMEM;
4720         }
4721
4722         valid_entry = NULL;
4723         /* Lookup  in free list and find most fit one */
4724         LIST_FOREACH(entry, &pool->free_list, next) {
4725                 if (entry->len >= num) {
4726                         /* Find best one */
4727                         if (entry->len == num) {
4728                                 valid_entry = entry;
4729                                 break;
4730                         }
4731                         if (valid_entry == NULL || valid_entry->len > entry->len)
4732                                 valid_entry = entry;
4733                 }
4734         }
4735
4736         /* Not find one to satisfy the request, return */
4737         if (valid_entry == NULL) {
4738                 PMD_DRV_LOG(ERR, "No valid entry found");
4739                 return -ENOMEM;
4740         }
4741         /**
4742          * The entry have equal queue number as requested,
4743          * remove it from alloc_list.
4744          */
4745         if (valid_entry->len == num) {
4746                 LIST_REMOVE(valid_entry, next);
4747         } else {
4748                 /**
4749                  * The entry have more numbers than requested,
4750                  * create a new entry for alloc_list and minus its
4751                  * queue base and number in free_list.
4752                  */
4753                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4754                 if (entry == NULL) {
4755                         PMD_DRV_LOG(ERR,
4756                                 "Failed to allocate memory for resource pool");
4757                         return -ENOMEM;
4758                 }
4759                 entry->base = valid_entry->base;
4760                 entry->len = num;
4761                 valid_entry->base += num;
4762                 valid_entry->len -= num;
4763                 valid_entry = entry;
4764         }
4765
4766         /* Insert it into alloc list, not sorted */
4767         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4768
4769         pool->num_free -= valid_entry->len;
4770         pool->num_alloc += valid_entry->len;
4771
4772         return valid_entry->base + pool->base;
4773 }
4774
4775 /**
4776  * bitmap_is_subset - Check whether src2 is subset of src1
4777  **/
4778 static inline int
4779 bitmap_is_subset(uint8_t src1, uint8_t src2)
4780 {
4781         return !((src1 ^ src2) & src2);
4782 }
4783
4784 static enum i40e_status_code
4785 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4786 {
4787         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4788
4789         /* If DCB is not supported, only default TC is supported */
4790         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4791                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4792                 return I40E_NOT_SUPPORTED;
4793         }
4794
4795         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4796                 PMD_DRV_LOG(ERR,
4797                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4798                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4799                 return I40E_NOT_SUPPORTED;
4800         }
4801         return I40E_SUCCESS;
4802 }
4803
4804 int
4805 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4806                                 struct i40e_vsi_vlan_pvid_info *info)
4807 {
4808         struct i40e_hw *hw;
4809         struct i40e_vsi_context ctxt;
4810         uint8_t vlan_flags = 0;
4811         int ret;
4812
4813         if (vsi == NULL || info == NULL) {
4814                 PMD_DRV_LOG(ERR, "invalid parameters");
4815                 return I40E_ERR_PARAM;
4816         }
4817
4818         if (info->on) {
4819                 vsi->info.pvid = info->config.pvid;
4820                 /**
4821                  * If insert pvid is enabled, only tagged pkts are
4822                  * allowed to be sent out.
4823                  */
4824                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4825                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4826         } else {
4827                 vsi->info.pvid = 0;
4828                 if (info->config.reject.tagged == 0)
4829                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4830
4831                 if (info->config.reject.untagged == 0)
4832                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4833         }
4834         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4835                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4836         vsi->info.port_vlan_flags |= vlan_flags;
4837         vsi->info.valid_sections =
4838                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4839         memset(&ctxt, 0, sizeof(ctxt));
4840         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4841         ctxt.seid = vsi->seid;
4842
4843         hw = I40E_VSI_TO_HW(vsi);
4844         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4845         if (ret != I40E_SUCCESS)
4846                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4847
4848         return ret;
4849 }
4850
4851 static int
4852 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4853 {
4854         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4855         int i, ret;
4856         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4857
4858         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4859         if (ret != I40E_SUCCESS)
4860                 return ret;
4861
4862         if (!vsi->seid) {
4863                 PMD_DRV_LOG(ERR, "seid not valid");
4864                 return -EINVAL;
4865         }
4866
4867         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4868         tc_bw_data.tc_valid_bits = enabled_tcmap;
4869         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4870                 tc_bw_data.tc_bw_credits[i] =
4871                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4872
4873         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4874         if (ret != I40E_SUCCESS) {
4875                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4876                 return ret;
4877         }
4878
4879         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4880                                         sizeof(vsi->info.qs_handle));
4881         return I40E_SUCCESS;
4882 }
4883
4884 static enum i40e_status_code
4885 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4886                                  struct i40e_aqc_vsi_properties_data *info,
4887                                  uint8_t enabled_tcmap)
4888 {
4889         enum i40e_status_code ret;
4890         int i, total_tc = 0;
4891         uint16_t qpnum_per_tc, bsf, qp_idx;
4892
4893         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4894         if (ret != I40E_SUCCESS)
4895                 return ret;
4896
4897         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4898                 if (enabled_tcmap & (1 << i))
4899                         total_tc++;
4900         if (total_tc == 0)
4901                 total_tc = 1;
4902         vsi->enabled_tc = enabled_tcmap;
4903
4904         /* Number of queues per enabled TC */
4905         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4906         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4907         bsf = rte_bsf32(qpnum_per_tc);
4908
4909         /* Adjust the queue number to actual queues that can be applied */
4910         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4911                 vsi->nb_qps = qpnum_per_tc * total_tc;
4912
4913         /**
4914          * Configure TC and queue mapping parameters, for enabled TC,
4915          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4916          * default queue will serve it.
4917          */
4918         qp_idx = 0;
4919         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4920                 if (vsi->enabled_tc & (1 << i)) {
4921                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4922                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4923                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4924                         qp_idx += qpnum_per_tc;
4925                 } else
4926                         info->tc_mapping[i] = 0;
4927         }
4928
4929         /* Associate queue number with VSI */
4930         if (vsi->type == I40E_VSI_SRIOV) {
4931                 info->mapping_flags |=
4932                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4933                 for (i = 0; i < vsi->nb_qps; i++)
4934                         info->queue_mapping[i] =
4935                                 rte_cpu_to_le_16(vsi->base_queue + i);
4936         } else {
4937                 info->mapping_flags |=
4938                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4939                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4940         }
4941         info->valid_sections |=
4942                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4943
4944         return I40E_SUCCESS;
4945 }
4946
4947 static int
4948 i40e_veb_release(struct i40e_veb *veb)
4949 {
4950         struct i40e_vsi *vsi;
4951         struct i40e_hw *hw;
4952
4953         if (veb == NULL)
4954                 return -EINVAL;
4955
4956         if (!TAILQ_EMPTY(&veb->head)) {
4957                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4958                 return -EACCES;
4959         }
4960         /* associate_vsi field is NULL for floating VEB */
4961         if (veb->associate_vsi != NULL) {
4962                 vsi = veb->associate_vsi;
4963                 hw = I40E_VSI_TO_HW(vsi);
4964
4965                 vsi->uplink_seid = veb->uplink_seid;
4966                 vsi->veb = NULL;
4967         } else {
4968                 veb->associate_pf->main_vsi->floating_veb = NULL;
4969                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4970         }
4971
4972         i40e_aq_delete_element(hw, veb->seid, NULL);
4973         rte_free(veb);
4974         return I40E_SUCCESS;
4975 }
4976
4977 /* Setup a veb */
4978 static struct i40e_veb *
4979 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4980 {
4981         struct i40e_veb *veb;
4982         int ret;
4983         struct i40e_hw *hw;
4984
4985         if (pf == NULL) {
4986                 PMD_DRV_LOG(ERR,
4987                             "veb setup failed, associated PF shouldn't null");
4988                 return NULL;
4989         }
4990         hw = I40E_PF_TO_HW(pf);
4991
4992         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4993         if (!veb) {
4994                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4995                 goto fail;
4996         }
4997
4998         veb->associate_vsi = vsi;
4999         veb->associate_pf = pf;
5000         TAILQ_INIT(&veb->head);
5001         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5002
5003         /* create floating veb if vsi is NULL */
5004         if (vsi != NULL) {
5005                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5006                                       I40E_DEFAULT_TCMAP, false,
5007                                       &veb->seid, false, NULL);
5008         } else {
5009                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5010                                       true, &veb->seid, false, NULL);
5011         }
5012
5013         if (ret != I40E_SUCCESS) {
5014                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5015                             hw->aq.asq_last_status);
5016                 goto fail;
5017         }
5018         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5019
5020         /* get statistics index */
5021         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5022                                 &veb->stats_idx, NULL, NULL, NULL);
5023         if (ret != I40E_SUCCESS) {
5024                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5025                             hw->aq.asq_last_status);
5026                 goto fail;
5027         }
5028         /* Get VEB bandwidth, to be implemented */
5029         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5030         if (vsi)
5031                 vsi->uplink_seid = veb->seid;
5032
5033         return veb;
5034 fail:
5035         rte_free(veb);
5036         return NULL;
5037 }
5038
5039 int
5040 i40e_vsi_release(struct i40e_vsi *vsi)
5041 {
5042         struct i40e_pf *pf;
5043         struct i40e_hw *hw;
5044         struct i40e_vsi_list *vsi_list;
5045         void *temp;
5046         int ret;
5047         struct i40e_mac_filter *f;
5048         uint16_t user_param;
5049
5050         if (!vsi)
5051                 return I40E_SUCCESS;
5052
5053         if (!vsi->adapter)
5054                 return -EFAULT;
5055
5056         user_param = vsi->user_param;
5057
5058         pf = I40E_VSI_TO_PF(vsi);
5059         hw = I40E_VSI_TO_HW(vsi);
5060
5061         /* VSI has child to attach, release child first */
5062         if (vsi->veb) {
5063                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5064                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5065                                 return -1;
5066                 }
5067                 i40e_veb_release(vsi->veb);
5068         }
5069
5070         if (vsi->floating_veb) {
5071                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5072                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5073                                 return -1;
5074                 }
5075         }
5076
5077         /* Remove all macvlan filters of the VSI */
5078         i40e_vsi_remove_all_macvlan_filter(vsi);
5079         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5080                 rte_free(f);
5081
5082         if (vsi->type != I40E_VSI_MAIN &&
5083             ((vsi->type != I40E_VSI_SRIOV) ||
5084             !pf->floating_veb_list[user_param])) {
5085                 /* Remove vsi from parent's sibling list */
5086                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5087                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5088                         return I40E_ERR_PARAM;
5089                 }
5090                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5091                                 &vsi->sib_vsi_list, list);
5092
5093                 /* Remove all switch element of the VSI */
5094                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5095                 if (ret != I40E_SUCCESS)
5096                         PMD_DRV_LOG(ERR, "Failed to delete element");
5097         }
5098
5099         if ((vsi->type == I40E_VSI_SRIOV) &&
5100             pf->floating_veb_list[user_param]) {
5101                 /* Remove vsi from parent's sibling list */
5102                 if (vsi->parent_vsi == NULL ||
5103                     vsi->parent_vsi->floating_veb == NULL) {
5104                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5105                         return I40E_ERR_PARAM;
5106                 }
5107                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5108                              &vsi->sib_vsi_list, list);
5109
5110                 /* Remove all switch element of the VSI */
5111                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5112                 if (ret != I40E_SUCCESS)
5113                         PMD_DRV_LOG(ERR, "Failed to delete element");
5114         }
5115
5116         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5117
5118         if (vsi->type != I40E_VSI_SRIOV)
5119                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5120         rte_free(vsi);
5121
5122         return I40E_SUCCESS;
5123 }
5124
5125 static int
5126 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5127 {
5128         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5129         struct i40e_aqc_remove_macvlan_element_data def_filter;
5130         struct i40e_mac_filter_info filter;
5131         int ret;
5132
5133         if (vsi->type != I40E_VSI_MAIN)
5134                 return I40E_ERR_CONFIG;
5135         memset(&def_filter, 0, sizeof(def_filter));
5136         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5137                                         ETH_ADDR_LEN);
5138         def_filter.vlan_tag = 0;
5139         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5140                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5141         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5142         if (ret != I40E_SUCCESS) {
5143                 struct i40e_mac_filter *f;
5144                 struct ether_addr *mac;
5145
5146                 PMD_DRV_LOG(DEBUG,
5147                             "Cannot remove the default macvlan filter");
5148                 /* It needs to add the permanent mac into mac list */
5149                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5150                 if (f == NULL) {
5151                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5152                         return I40E_ERR_NO_MEMORY;
5153                 }
5154                 mac = &f->mac_info.mac_addr;
5155                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5156                                 ETH_ADDR_LEN);
5157                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5158                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5159                 vsi->mac_num++;
5160
5161                 return ret;
5162         }
5163         rte_memcpy(&filter.mac_addr,
5164                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5165         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5166         return i40e_vsi_add_mac(vsi, &filter);
5167 }
5168
5169 /*
5170  * i40e_vsi_get_bw_config - Query VSI BW Information
5171  * @vsi: the VSI to be queried
5172  *
5173  * Returns 0 on success, negative value on failure
5174  */
5175 static enum i40e_status_code
5176 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5177 {
5178         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5179         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5180         struct i40e_hw *hw = &vsi->adapter->hw;
5181         i40e_status ret;
5182         int i;
5183         uint32_t bw_max;
5184
5185         memset(&bw_config, 0, sizeof(bw_config));
5186         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5187         if (ret != I40E_SUCCESS) {
5188                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5189                             hw->aq.asq_last_status);
5190                 return ret;
5191         }
5192
5193         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5194         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5195                                         &ets_sla_config, NULL);
5196         if (ret != I40E_SUCCESS) {
5197                 PMD_DRV_LOG(ERR,
5198                         "VSI failed to get TC bandwdith configuration %u",
5199                         hw->aq.asq_last_status);
5200                 return ret;
5201         }
5202
5203         /* store and print out BW info */
5204         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5205         vsi->bw_info.bw_max = bw_config.max_bw;
5206         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5207         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5208         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5209                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5210                      I40E_16_BIT_WIDTH);
5211         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5212                 vsi->bw_info.bw_ets_share_credits[i] =
5213                                 ets_sla_config.share_credits[i];
5214                 vsi->bw_info.bw_ets_credits[i] =
5215                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5216                 /* 4 bits per TC, 4th bit is reserved */
5217                 vsi->bw_info.bw_ets_max[i] =
5218                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5219                                   RTE_LEN2MASK(3, uint8_t));
5220                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5221                             vsi->bw_info.bw_ets_share_credits[i]);
5222                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5223                             vsi->bw_info.bw_ets_credits[i]);
5224                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5225                             vsi->bw_info.bw_ets_max[i]);
5226         }
5227
5228         return I40E_SUCCESS;
5229 }
5230
5231 /* i40e_enable_pf_lb
5232  * @pf: pointer to the pf structure
5233  *
5234  * allow loopback on pf
5235  */
5236 static inline void
5237 i40e_enable_pf_lb(struct i40e_pf *pf)
5238 {
5239         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5240         struct i40e_vsi_context ctxt;
5241         int ret;
5242
5243         /* Use the FW API if FW >= v5.0 */
5244         if (hw->aq.fw_maj_ver < 5) {
5245                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5246                 return;
5247         }
5248
5249         memset(&ctxt, 0, sizeof(ctxt));
5250         ctxt.seid = pf->main_vsi_seid;
5251         ctxt.pf_num = hw->pf_id;
5252         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5253         if (ret) {
5254                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5255                             ret, hw->aq.asq_last_status);
5256                 return;
5257         }
5258         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5259         ctxt.info.valid_sections =
5260                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5261         ctxt.info.switch_id |=
5262                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5263
5264         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5265         if (ret)
5266                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5267                             hw->aq.asq_last_status);
5268 }
5269
5270 /* Setup a VSI */
5271 struct i40e_vsi *
5272 i40e_vsi_setup(struct i40e_pf *pf,
5273                enum i40e_vsi_type type,
5274                struct i40e_vsi *uplink_vsi,
5275                uint16_t user_param)
5276 {
5277         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5278         struct i40e_vsi *vsi;
5279         struct i40e_mac_filter_info filter;
5280         int ret;
5281         struct i40e_vsi_context ctxt;
5282         struct ether_addr broadcast =
5283                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5284
5285         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5286             uplink_vsi == NULL) {
5287                 PMD_DRV_LOG(ERR,
5288                         "VSI setup failed, VSI link shouldn't be NULL");
5289                 return NULL;
5290         }
5291
5292         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5293                 PMD_DRV_LOG(ERR,
5294                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5295                 return NULL;
5296         }
5297
5298         /* two situations
5299          * 1.type is not MAIN and uplink vsi is not NULL
5300          * If uplink vsi didn't setup VEB, create one first under veb field
5301          * 2.type is SRIOV and the uplink is NULL
5302          * If floating VEB is NULL, create one veb under floating veb field
5303          */
5304
5305         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5306             uplink_vsi->veb == NULL) {
5307                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5308
5309                 if (uplink_vsi->veb == NULL) {
5310                         PMD_DRV_LOG(ERR, "VEB setup failed");
5311                         return NULL;
5312                 }
5313                 /* set ALLOWLOOPBACk on pf, when veb is created */
5314                 i40e_enable_pf_lb(pf);
5315         }
5316
5317         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5318             pf->main_vsi->floating_veb == NULL) {
5319                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5320
5321                 if (pf->main_vsi->floating_veb == NULL) {
5322                         PMD_DRV_LOG(ERR, "VEB setup failed");
5323                         return NULL;
5324                 }
5325         }
5326
5327         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5328         if (!vsi) {
5329                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5330                 return NULL;
5331         }
5332         TAILQ_INIT(&vsi->mac_list);
5333         vsi->type = type;
5334         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5335         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5336         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5337         vsi->user_param = user_param;
5338         vsi->vlan_anti_spoof_on = 0;
5339         vsi->vlan_filter_on = 0;
5340         /* Allocate queues */
5341         switch (vsi->type) {
5342         case I40E_VSI_MAIN  :
5343                 vsi->nb_qps = pf->lan_nb_qps;
5344                 break;
5345         case I40E_VSI_SRIOV :
5346                 vsi->nb_qps = pf->vf_nb_qps;
5347                 break;
5348         case I40E_VSI_VMDQ2:
5349                 vsi->nb_qps = pf->vmdq_nb_qps;
5350                 break;
5351         case I40E_VSI_FDIR:
5352                 vsi->nb_qps = pf->fdir_nb_qps;
5353                 break;
5354         default:
5355                 goto fail_mem;
5356         }
5357         /*
5358          * The filter status descriptor is reported in rx queue 0,
5359          * while the tx queue for fdir filter programming has no
5360          * such constraints, can be non-zero queues.
5361          * To simplify it, choose FDIR vsi use queue 0 pair.
5362          * To make sure it will use queue 0 pair, queue allocation
5363          * need be done before this function is called
5364          */
5365         if (type != I40E_VSI_FDIR) {
5366                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5367                         if (ret < 0) {
5368                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5369                                                 vsi->seid, ret);
5370                                 goto fail_mem;
5371                         }
5372                         vsi->base_queue = ret;
5373         } else
5374                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5375
5376         /* VF has MSIX interrupt in VF range, don't allocate here */
5377         if (type == I40E_VSI_MAIN) {
5378                 if (pf->support_multi_driver) {
5379                         /* If support multi-driver, need to use INT0 instead of
5380                          * allocating from msix pool. The Msix pool is init from
5381                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5382                          * to 1 without calling i40e_res_pool_alloc.
5383                          */
5384                         vsi->msix_intr = 0;
5385                         vsi->nb_msix = 1;
5386                 } else {
5387                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5388                                                   RTE_MIN(vsi->nb_qps,
5389                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5390                         if (ret < 0) {
5391                                 PMD_DRV_LOG(ERR,
5392                                             "VSI MAIN %d get heap failed %d",
5393                                             vsi->seid, ret);
5394                                 goto fail_queue_alloc;
5395                         }
5396                         vsi->msix_intr = ret;
5397                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5398                                                RTE_MAX_RXTX_INTR_VEC_ID);
5399                 }
5400         } else if (type != I40E_VSI_SRIOV) {
5401                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5402                 if (ret < 0) {
5403                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5404                         goto fail_queue_alloc;
5405                 }
5406                 vsi->msix_intr = ret;
5407                 vsi->nb_msix = 1;
5408         } else {
5409                 vsi->msix_intr = 0;
5410                 vsi->nb_msix = 0;
5411         }
5412
5413         /* Add VSI */
5414         if (type == I40E_VSI_MAIN) {
5415                 /* For main VSI, no need to add since it's default one */
5416                 vsi->uplink_seid = pf->mac_seid;
5417                 vsi->seid = pf->main_vsi_seid;
5418                 /* Bind queues with specific MSIX interrupt */
5419                 /**
5420                  * Needs 2 interrupt at least, one for misc cause which will
5421                  * enabled from OS side, Another for queues binding the
5422                  * interrupt from device side only.
5423                  */
5424
5425                 /* Get default VSI parameters from hardware */
5426                 memset(&ctxt, 0, sizeof(ctxt));
5427                 ctxt.seid = vsi->seid;
5428                 ctxt.pf_num = hw->pf_id;
5429                 ctxt.uplink_seid = vsi->uplink_seid;
5430                 ctxt.vf_num = 0;
5431                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5432                 if (ret != I40E_SUCCESS) {
5433                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5434                         goto fail_msix_alloc;
5435                 }
5436                 rte_memcpy(&vsi->info, &ctxt.info,
5437                         sizeof(struct i40e_aqc_vsi_properties_data));
5438                 vsi->vsi_id = ctxt.vsi_number;
5439                 vsi->info.valid_sections = 0;
5440
5441                 /* Configure tc, enabled TC0 only */
5442                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5443                         I40E_SUCCESS) {
5444                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5445                         goto fail_msix_alloc;
5446                 }
5447
5448                 /* TC, queue mapping */
5449                 memset(&ctxt, 0, sizeof(ctxt));
5450                 vsi->info.valid_sections |=
5451                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5452                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5453                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5454                 rte_memcpy(&ctxt.info, &vsi->info,
5455                         sizeof(struct i40e_aqc_vsi_properties_data));
5456                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5457                                                 I40E_DEFAULT_TCMAP);
5458                 if (ret != I40E_SUCCESS) {
5459                         PMD_DRV_LOG(ERR,
5460                                 "Failed to configure TC queue mapping");
5461                         goto fail_msix_alloc;
5462                 }
5463                 ctxt.seid = vsi->seid;
5464                 ctxt.pf_num = hw->pf_id;
5465                 ctxt.uplink_seid = vsi->uplink_seid;
5466                 ctxt.vf_num = 0;
5467
5468                 /* Update VSI parameters */
5469                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5470                 if (ret != I40E_SUCCESS) {
5471                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5472                         goto fail_msix_alloc;
5473                 }
5474
5475                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5476                                                 sizeof(vsi->info.tc_mapping));
5477                 rte_memcpy(&vsi->info.queue_mapping,
5478                                 &ctxt.info.queue_mapping,
5479                         sizeof(vsi->info.queue_mapping));
5480                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5481                 vsi->info.valid_sections = 0;
5482
5483                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5484                                 ETH_ADDR_LEN);
5485
5486                 /**
5487                  * Updating default filter settings are necessary to prevent
5488                  * reception of tagged packets.
5489                  * Some old firmware configurations load a default macvlan
5490                  * filter which accepts both tagged and untagged packets.
5491                  * The updating is to use a normal filter instead if needed.
5492                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5493                  * The firmware with correct configurations load the default
5494                  * macvlan filter which is expected and cannot be removed.
5495                  */
5496                 i40e_update_default_filter_setting(vsi);
5497                 i40e_config_qinq(hw, vsi);
5498         } else if (type == I40E_VSI_SRIOV) {
5499                 memset(&ctxt, 0, sizeof(ctxt));
5500                 /**
5501                  * For other VSI, the uplink_seid equals to uplink VSI's
5502                  * uplink_seid since they share same VEB
5503                  */
5504                 if (uplink_vsi == NULL)
5505                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5506                 else
5507                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5508                 ctxt.pf_num = hw->pf_id;
5509                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5510                 ctxt.uplink_seid = vsi->uplink_seid;
5511                 ctxt.connection_type = 0x1;
5512                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5513
5514                 /* Use the VEB configuration if FW >= v5.0 */
5515                 if (hw->aq.fw_maj_ver >= 5) {
5516                         /* Configure switch ID */
5517                         ctxt.info.valid_sections |=
5518                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5519                         ctxt.info.switch_id =
5520                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5521                 }
5522
5523                 /* Configure port/vlan */
5524                 ctxt.info.valid_sections |=
5525                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5526                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5527                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5528                                                 hw->func_caps.enabled_tcmap);
5529                 if (ret != I40E_SUCCESS) {
5530                         PMD_DRV_LOG(ERR,
5531                                 "Failed to configure TC queue mapping");
5532                         goto fail_msix_alloc;
5533                 }
5534
5535                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5536                 ctxt.info.valid_sections |=
5537                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5538                 /**
5539                  * Since VSI is not created yet, only configure parameter,
5540                  * will add vsi below.
5541                  */
5542
5543                 i40e_config_qinq(hw, vsi);
5544         } else if (type == I40E_VSI_VMDQ2) {
5545                 memset(&ctxt, 0, sizeof(ctxt));
5546                 /*
5547                  * For other VSI, the uplink_seid equals to uplink VSI's
5548                  * uplink_seid since they share same VEB
5549                  */
5550                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5551                 ctxt.pf_num = hw->pf_id;
5552                 ctxt.vf_num = 0;
5553                 ctxt.uplink_seid = vsi->uplink_seid;
5554                 ctxt.connection_type = 0x1;
5555                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5556
5557                 ctxt.info.valid_sections |=
5558                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5559                 /* user_param carries flag to enable loop back */
5560                 if (user_param) {
5561                         ctxt.info.switch_id =
5562                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5563                         ctxt.info.switch_id |=
5564                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5565                 }
5566
5567                 /* Configure port/vlan */
5568                 ctxt.info.valid_sections |=
5569                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5570                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5571                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5572                                                 I40E_DEFAULT_TCMAP);
5573                 if (ret != I40E_SUCCESS) {
5574                         PMD_DRV_LOG(ERR,
5575                                 "Failed to configure TC queue mapping");
5576                         goto fail_msix_alloc;
5577                 }
5578                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5579                 ctxt.info.valid_sections |=
5580                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5581         } else if (type == I40E_VSI_FDIR) {
5582                 memset(&ctxt, 0, sizeof(ctxt));
5583                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5584                 ctxt.pf_num = hw->pf_id;
5585                 ctxt.vf_num = 0;
5586                 ctxt.uplink_seid = vsi->uplink_seid;
5587                 ctxt.connection_type = 0x1;     /* regular data port */
5588                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5589                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5590                                                 I40E_DEFAULT_TCMAP);
5591                 if (ret != I40E_SUCCESS) {
5592                         PMD_DRV_LOG(ERR,
5593                                 "Failed to configure TC queue mapping.");
5594                         goto fail_msix_alloc;
5595                 }
5596                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5597                 ctxt.info.valid_sections |=
5598                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5599         } else {
5600                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5601                 goto fail_msix_alloc;
5602         }
5603
5604         if (vsi->type != I40E_VSI_MAIN) {
5605                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5606                 if (ret != I40E_SUCCESS) {
5607                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5608                                     hw->aq.asq_last_status);
5609                         goto fail_msix_alloc;
5610                 }
5611                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5612                 vsi->info.valid_sections = 0;
5613                 vsi->seid = ctxt.seid;
5614                 vsi->vsi_id = ctxt.vsi_number;
5615                 vsi->sib_vsi_list.vsi = vsi;
5616                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5617                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5618                                           &vsi->sib_vsi_list, list);
5619                 } else {
5620                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5621                                           &vsi->sib_vsi_list, list);
5622                 }
5623         }
5624
5625         /* MAC/VLAN configuration */
5626         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5627         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5628
5629         ret = i40e_vsi_add_mac(vsi, &filter);
5630         if (ret != I40E_SUCCESS) {
5631                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5632                 goto fail_msix_alloc;
5633         }
5634
5635         /* Get VSI BW information */
5636         i40e_vsi_get_bw_config(vsi);
5637         return vsi;
5638 fail_msix_alloc:
5639         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5640 fail_queue_alloc:
5641         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5642 fail_mem:
5643         rte_free(vsi);
5644         return NULL;
5645 }
5646
5647 /* Configure vlan filter on or off */
5648 int
5649 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5650 {
5651         int i, num;
5652         struct i40e_mac_filter *f;
5653         void *temp;
5654         struct i40e_mac_filter_info *mac_filter;
5655         enum rte_mac_filter_type desired_filter;
5656         int ret = I40E_SUCCESS;
5657
5658         if (on) {
5659                 /* Filter to match MAC and VLAN */
5660                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5661         } else {
5662                 /* Filter to match only MAC */
5663                 desired_filter = RTE_MAC_PERFECT_MATCH;
5664         }
5665
5666         num = vsi->mac_num;
5667
5668         mac_filter = rte_zmalloc("mac_filter_info_data",
5669                                  num * sizeof(*mac_filter), 0);
5670         if (mac_filter == NULL) {
5671                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5672                 return I40E_ERR_NO_MEMORY;
5673         }
5674
5675         i = 0;
5676
5677         /* Remove all existing mac */
5678         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5679                 mac_filter[i] = f->mac_info;
5680                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5681                 if (ret) {
5682                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5683                                     on ? "enable" : "disable");
5684                         goto DONE;
5685                 }
5686                 i++;
5687         }
5688
5689         /* Override with new filter */
5690         for (i = 0; i < num; i++) {
5691                 mac_filter[i].filter_type = desired_filter;
5692                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5693                 if (ret) {
5694                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5695                                     on ? "enable" : "disable");
5696                         goto DONE;
5697                 }
5698         }
5699
5700 DONE:
5701         rte_free(mac_filter);
5702         return ret;
5703 }
5704
5705 /* Configure vlan stripping on or off */
5706 int
5707 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5708 {
5709         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5710         struct i40e_vsi_context ctxt;
5711         uint8_t vlan_flags;
5712         int ret = I40E_SUCCESS;
5713
5714         /* Check if it has been already on or off */
5715         if (vsi->info.valid_sections &
5716                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5717                 if (on) {
5718                         if ((vsi->info.port_vlan_flags &
5719                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5720                                 return 0; /* already on */
5721                 } else {
5722                         if ((vsi->info.port_vlan_flags &
5723                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5724                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5725                                 return 0; /* already off */
5726                 }
5727         }
5728
5729         if (on)
5730                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5731         else
5732                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5733         vsi->info.valid_sections =
5734                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5735         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5736         vsi->info.port_vlan_flags |= vlan_flags;
5737         ctxt.seid = vsi->seid;
5738         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5739         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5740         if (ret)
5741                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5742                             on ? "enable" : "disable");
5743
5744         return ret;
5745 }
5746
5747 static int
5748 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5749 {
5750         struct rte_eth_dev_data *data = dev->data;
5751         int ret;
5752         int mask = 0;
5753
5754         /* Apply vlan offload setting */
5755         mask = ETH_VLAN_STRIP_MASK |
5756                ETH_VLAN_FILTER_MASK |
5757                ETH_VLAN_EXTEND_MASK;
5758         ret = i40e_vlan_offload_set(dev, mask);
5759         if (ret) {
5760                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5761                 return ret;
5762         }
5763
5764         /* Apply pvid setting */
5765         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5766                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5767         if (ret)
5768                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5769
5770         return ret;
5771 }
5772
5773 static int
5774 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5775 {
5776         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5777
5778         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5779 }
5780
5781 static int
5782 i40e_update_flow_control(struct i40e_hw *hw)
5783 {
5784 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5785         struct i40e_link_status link_status;
5786         uint32_t rxfc = 0, txfc = 0, reg;
5787         uint8_t an_info;
5788         int ret;
5789
5790         memset(&link_status, 0, sizeof(link_status));
5791         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5792         if (ret != I40E_SUCCESS) {
5793                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5794                 goto write_reg; /* Disable flow control */
5795         }
5796
5797         an_info = hw->phy.link_info.an_info;
5798         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5799                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5800                 ret = I40E_ERR_NOT_READY;
5801                 goto write_reg; /* Disable flow control */
5802         }
5803         /**
5804          * If link auto negotiation is enabled, flow control needs to
5805          * be configured according to it
5806          */
5807         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5808         case I40E_LINK_PAUSE_RXTX:
5809                 rxfc = 1;
5810                 txfc = 1;
5811                 hw->fc.current_mode = I40E_FC_FULL;
5812                 break;
5813         case I40E_AQ_LINK_PAUSE_RX:
5814                 rxfc = 1;
5815                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5816                 break;
5817         case I40E_AQ_LINK_PAUSE_TX:
5818                 txfc = 1;
5819                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5820                 break;
5821         default:
5822                 hw->fc.current_mode = I40E_FC_NONE;
5823                 break;
5824         }
5825
5826 write_reg:
5827         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5828                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5829         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5830         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5831         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5832         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5833
5834         return ret;
5835 }
5836
5837 /* PF setup */
5838 static int
5839 i40e_pf_setup(struct i40e_pf *pf)
5840 {
5841         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5842         struct i40e_filter_control_settings settings;
5843         struct i40e_vsi *vsi;
5844         int ret;
5845
5846         /* Clear all stats counters */
5847         pf->offset_loaded = FALSE;
5848         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5849         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5850         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5851         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5852
5853         ret = i40e_pf_get_switch_config(pf);
5854         if (ret != I40E_SUCCESS) {
5855                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5856                 return ret;
5857         }
5858
5859         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
5860         if (ret)
5861                 PMD_INIT_LOG(WARNING,
5862                         "failed to allocate switch domain for device %d", ret);
5863
5864         if (pf->flags & I40E_FLAG_FDIR) {
5865                 /* make queue allocated first, let FDIR use queue pair 0*/
5866                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5867                 if (ret != I40E_FDIR_QUEUE_ID) {
5868                         PMD_DRV_LOG(ERR,
5869                                 "queue allocation fails for FDIR: ret =%d",
5870                                 ret);
5871                         pf->flags &= ~I40E_FLAG_FDIR;
5872                 }
5873         }
5874         /*  main VSI setup */
5875         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5876         if (!vsi) {
5877                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5878                 return I40E_ERR_NOT_READY;
5879         }
5880         pf->main_vsi = vsi;
5881
5882         /* Configure filter control */
5883         memset(&settings, 0, sizeof(settings));
5884         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5885                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5886         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5887                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5888         else {
5889                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5890                         hw->func_caps.rss_table_size);
5891                 return I40E_ERR_PARAM;
5892         }
5893         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5894                 hw->func_caps.rss_table_size);
5895         pf->hash_lut_size = hw->func_caps.rss_table_size;
5896
5897         /* Enable ethtype and macvlan filters */
5898         settings.enable_ethtype = TRUE;
5899         settings.enable_macvlan = TRUE;
5900         ret = i40e_set_filter_control(hw, &settings);
5901         if (ret)
5902                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5903                                                                 ret);
5904
5905         /* Update flow control according to the auto negotiation */
5906         i40e_update_flow_control(hw);
5907
5908         return I40E_SUCCESS;
5909 }
5910
5911 int
5912 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5913 {
5914         uint32_t reg;
5915         uint16_t j;
5916
5917         /**
5918          * Set or clear TX Queue Disable flags,
5919          * which is required by hardware.
5920          */
5921         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5922         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5923
5924         /* Wait until the request is finished */
5925         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5926                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5927                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5928                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5929                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5930                                                         & 0x1))) {
5931                         break;
5932                 }
5933         }
5934         if (on) {
5935                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5936                         return I40E_SUCCESS; /* already on, skip next steps */
5937
5938                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5939                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5940         } else {
5941                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5942                         return I40E_SUCCESS; /* already off, skip next steps */
5943                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5944         }
5945         /* Write the register */
5946         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5947         /* Check the result */
5948         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5949                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5950                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5951                 if (on) {
5952                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5953                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5954                                 break;
5955                 } else {
5956                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5957                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5958                                 break;
5959                 }
5960         }
5961         /* Check if it is timeout */
5962         if (j >= I40E_CHK_Q_ENA_COUNT) {
5963                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5964                             (on ? "enable" : "disable"), q_idx);
5965                 return I40E_ERR_TIMEOUT;
5966         }
5967
5968         return I40E_SUCCESS;
5969 }
5970
5971 /* Swith on or off the tx queues */
5972 static int
5973 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5974 {
5975         struct rte_eth_dev_data *dev_data = pf->dev_data;
5976         struct i40e_tx_queue *txq;
5977         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5978         uint16_t i;
5979         int ret;
5980
5981         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5982                 txq = dev_data->tx_queues[i];
5983                 /* Don't operate the queue if not configured or
5984                  * if starting only per queue */
5985                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5986                         continue;
5987                 if (on)
5988                         ret = i40e_dev_tx_queue_start(dev, i);
5989                 else
5990                         ret = i40e_dev_tx_queue_stop(dev, i);
5991                 if ( ret != I40E_SUCCESS)
5992                         return ret;
5993         }
5994
5995         return I40E_SUCCESS;
5996 }
5997
5998 int
5999 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6000 {
6001         uint32_t reg;
6002         uint16_t j;
6003
6004         /* Wait until the request is finished */
6005         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6006                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6007                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6008                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6009                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6010                         break;
6011         }
6012
6013         if (on) {
6014                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6015                         return I40E_SUCCESS; /* Already on, skip next steps */
6016                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6017         } else {
6018                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6019                         return I40E_SUCCESS; /* Already off, skip next steps */
6020                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6021         }
6022
6023         /* Write the register */
6024         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6025         /* Check the result */
6026         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6027                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6028                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6029                 if (on) {
6030                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6031                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6032                                 break;
6033                 } else {
6034                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6035                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6036                                 break;
6037                 }
6038         }
6039
6040         /* Check if it is timeout */
6041         if (j >= I40E_CHK_Q_ENA_COUNT) {
6042                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6043                             (on ? "enable" : "disable"), q_idx);
6044                 return I40E_ERR_TIMEOUT;
6045         }
6046
6047         return I40E_SUCCESS;
6048 }
6049 /* Switch on or off the rx queues */
6050 static int
6051 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6052 {
6053         struct rte_eth_dev_data *dev_data = pf->dev_data;
6054         struct i40e_rx_queue *rxq;
6055         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6056         uint16_t i;
6057         int ret;
6058
6059         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6060                 rxq = dev_data->rx_queues[i];
6061                 /* Don't operate the queue if not configured or
6062                  * if starting only per queue */
6063                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6064                         continue;
6065                 if (on)
6066                         ret = i40e_dev_rx_queue_start(dev, i);
6067                 else
6068                         ret = i40e_dev_rx_queue_stop(dev, i);
6069                 if (ret != I40E_SUCCESS)
6070                         return ret;
6071         }
6072
6073         return I40E_SUCCESS;
6074 }
6075
6076 /* Switch on or off all the rx/tx queues */
6077 int
6078 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6079 {
6080         int ret;
6081
6082         if (on) {
6083                 /* enable rx queues before enabling tx queues */
6084                 ret = i40e_dev_switch_rx_queues(pf, on);
6085                 if (ret) {
6086                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6087                         return ret;
6088                 }
6089                 ret = i40e_dev_switch_tx_queues(pf, on);
6090         } else {
6091                 /* Stop tx queues before stopping rx queues */
6092                 ret = i40e_dev_switch_tx_queues(pf, on);
6093                 if (ret) {
6094                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6095                         return ret;
6096                 }
6097                 ret = i40e_dev_switch_rx_queues(pf, on);
6098         }
6099
6100         return ret;
6101 }
6102
6103 /* Initialize VSI for TX */
6104 static int
6105 i40e_dev_tx_init(struct i40e_pf *pf)
6106 {
6107         struct rte_eth_dev_data *data = pf->dev_data;
6108         uint16_t i;
6109         uint32_t ret = I40E_SUCCESS;
6110         struct i40e_tx_queue *txq;
6111
6112         for (i = 0; i < data->nb_tx_queues; i++) {
6113                 txq = data->tx_queues[i];
6114                 if (!txq || !txq->q_set)
6115                         continue;
6116                 ret = i40e_tx_queue_init(txq);
6117                 if (ret != I40E_SUCCESS)
6118                         break;
6119         }
6120         if (ret == I40E_SUCCESS)
6121                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6122                                      ->eth_dev);
6123
6124         return ret;
6125 }
6126
6127 /* Initialize VSI for RX */
6128 static int
6129 i40e_dev_rx_init(struct i40e_pf *pf)
6130 {
6131         struct rte_eth_dev_data *data = pf->dev_data;
6132         int ret = I40E_SUCCESS;
6133         uint16_t i;
6134         struct i40e_rx_queue *rxq;
6135
6136         i40e_pf_config_mq_rx(pf);
6137         for (i = 0; i < data->nb_rx_queues; i++) {
6138                 rxq = data->rx_queues[i];
6139                 if (!rxq || !rxq->q_set)
6140                         continue;
6141
6142                 ret = i40e_rx_queue_init(rxq);
6143                 if (ret != I40E_SUCCESS) {
6144                         PMD_DRV_LOG(ERR,
6145                                 "Failed to do RX queue initialization");
6146                         break;
6147                 }
6148         }
6149         if (ret == I40E_SUCCESS)
6150                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6151                                      ->eth_dev);
6152
6153         return ret;
6154 }
6155
6156 static int
6157 i40e_dev_rxtx_init(struct i40e_pf *pf)
6158 {
6159         int err;
6160
6161         err = i40e_dev_tx_init(pf);
6162         if (err) {
6163                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6164                 return err;
6165         }
6166         err = i40e_dev_rx_init(pf);
6167         if (err) {
6168                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6169                 return err;
6170         }
6171
6172         return err;
6173 }
6174
6175 static int
6176 i40e_vmdq_setup(struct rte_eth_dev *dev)
6177 {
6178         struct rte_eth_conf *conf = &dev->data->dev_conf;
6179         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6180         int i, err, conf_vsis, j, loop;
6181         struct i40e_vsi *vsi;
6182         struct i40e_vmdq_info *vmdq_info;
6183         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6184         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6185
6186         /*
6187          * Disable interrupt to avoid message from VF. Furthermore, it will
6188          * avoid race condition in VSI creation/destroy.
6189          */
6190         i40e_pf_disable_irq0(hw);
6191
6192         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6193                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6194                 return -ENOTSUP;
6195         }
6196
6197         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6198         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6199                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6200                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6201                         pf->max_nb_vmdq_vsi);
6202                 return -ENOTSUP;
6203         }
6204
6205         if (pf->vmdq != NULL) {
6206                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6207                 return 0;
6208         }
6209
6210         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6211                                 sizeof(*vmdq_info) * conf_vsis, 0);
6212
6213         if (pf->vmdq == NULL) {
6214                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6215                 return -ENOMEM;
6216         }
6217
6218         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6219
6220         /* Create VMDQ VSI */
6221         for (i = 0; i < conf_vsis; i++) {
6222                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6223                                 vmdq_conf->enable_loop_back);
6224                 if (vsi == NULL) {
6225                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6226                         err = -1;
6227                         goto err_vsi_setup;
6228                 }
6229                 vmdq_info = &pf->vmdq[i];
6230                 vmdq_info->pf = pf;
6231                 vmdq_info->vsi = vsi;
6232         }
6233         pf->nb_cfg_vmdq_vsi = conf_vsis;
6234
6235         /* Configure Vlan */
6236         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6237         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6238                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6239                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6240                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6241                                         vmdq_conf->pool_map[i].vlan_id, j);
6242
6243                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6244                                                 vmdq_conf->pool_map[i].vlan_id);
6245                                 if (err) {
6246                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6247                                         err = -1;
6248                                         goto err_vsi_setup;
6249                                 }
6250                         }
6251                 }
6252         }
6253
6254         i40e_pf_enable_irq0(hw);
6255
6256         return 0;
6257
6258 err_vsi_setup:
6259         for (i = 0; i < conf_vsis; i++)
6260                 if (pf->vmdq[i].vsi == NULL)
6261                         break;
6262                 else
6263                         i40e_vsi_release(pf->vmdq[i].vsi);
6264
6265         rte_free(pf->vmdq);
6266         pf->vmdq = NULL;
6267         i40e_pf_enable_irq0(hw);
6268         return err;
6269 }
6270
6271 static void
6272 i40e_stat_update_32(struct i40e_hw *hw,
6273                    uint32_t reg,
6274                    bool offset_loaded,
6275                    uint64_t *offset,
6276                    uint64_t *stat)
6277 {
6278         uint64_t new_data;
6279
6280         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6281         if (!offset_loaded)
6282                 *offset = new_data;
6283
6284         if (new_data >= *offset)
6285                 *stat = (uint64_t)(new_data - *offset);
6286         else
6287                 *stat = (uint64_t)((new_data +
6288                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6289 }
6290
6291 static void
6292 i40e_stat_update_48(struct i40e_hw *hw,
6293                    uint32_t hireg,
6294                    uint32_t loreg,
6295                    bool offset_loaded,
6296                    uint64_t *offset,
6297                    uint64_t *stat)
6298 {
6299         uint64_t new_data;
6300
6301         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6302         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6303                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6304
6305         if (!offset_loaded)
6306                 *offset = new_data;
6307
6308         if (new_data >= *offset)
6309                 *stat = new_data - *offset;
6310         else
6311                 *stat = (uint64_t)((new_data +
6312                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6313
6314         *stat &= I40E_48_BIT_MASK;
6315 }
6316
6317 /* Disable IRQ0 */
6318 void
6319 i40e_pf_disable_irq0(struct i40e_hw *hw)
6320 {
6321         /* Disable all interrupt types */
6322         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6323                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6324         I40E_WRITE_FLUSH(hw);
6325 }
6326
6327 /* Enable IRQ0 */
6328 void
6329 i40e_pf_enable_irq0(struct i40e_hw *hw)
6330 {
6331         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6332                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6333                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6334                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6335         I40E_WRITE_FLUSH(hw);
6336 }
6337
6338 static void
6339 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6340 {
6341         /* read pending request and disable first */
6342         i40e_pf_disable_irq0(hw);
6343         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6344         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6345                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6346
6347         if (no_queue)
6348                 /* Link no queues with irq0 */
6349                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6350                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6351 }
6352
6353 static void
6354 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6355 {
6356         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6357         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6358         int i;
6359         uint16_t abs_vf_id;
6360         uint32_t index, offset, val;
6361
6362         if (!pf->vfs)
6363                 return;
6364         /**
6365          * Try to find which VF trigger a reset, use absolute VF id to access
6366          * since the reg is global register.
6367          */
6368         for (i = 0; i < pf->vf_num; i++) {
6369                 abs_vf_id = hw->func_caps.vf_base_id + i;
6370                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6371                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6372                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6373                 /* VFR event occurred */
6374                 if (val & (0x1 << offset)) {
6375                         int ret;
6376
6377                         /* Clear the event first */
6378                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6379                                                         (0x1 << offset));
6380                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6381                         /**
6382                          * Only notify a VF reset event occurred,
6383                          * don't trigger another SW reset
6384                          */
6385                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6386                         if (ret != I40E_SUCCESS)
6387                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6388                 }
6389         }
6390 }
6391
6392 static void
6393 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6394 {
6395         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6396         int i;
6397
6398         for (i = 0; i < pf->vf_num; i++)
6399                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6400 }
6401
6402 static void
6403 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6404 {
6405         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6406         struct i40e_arq_event_info info;
6407         uint16_t pending, opcode;
6408         int ret;
6409
6410         info.buf_len = I40E_AQ_BUF_SZ;
6411         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6412         if (!info.msg_buf) {
6413                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6414                 return;
6415         }
6416
6417         pending = 1;
6418         while (pending) {
6419                 ret = i40e_clean_arq_element(hw, &info, &pending);
6420
6421                 if (ret != I40E_SUCCESS) {
6422                         PMD_DRV_LOG(INFO,
6423                                 "Failed to read msg from AdminQ, aq_err: %u",
6424                                 hw->aq.asq_last_status);
6425                         break;
6426                 }
6427                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6428
6429                 switch (opcode) {
6430                 case i40e_aqc_opc_send_msg_to_pf:
6431                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6432                         i40e_pf_host_handle_vf_msg(dev,
6433                                         rte_le_to_cpu_16(info.desc.retval),
6434                                         rte_le_to_cpu_32(info.desc.cookie_high),
6435                                         rte_le_to_cpu_32(info.desc.cookie_low),
6436                                         info.msg_buf,
6437                                         info.msg_len);
6438                         break;
6439                 case i40e_aqc_opc_get_link_status:
6440                         ret = i40e_dev_link_update(dev, 0);
6441                         if (!ret)
6442                                 _rte_eth_dev_callback_process(dev,
6443                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6444                         break;
6445                 default:
6446                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6447                                     opcode);
6448                         break;
6449                 }
6450         }
6451         rte_free(info.msg_buf);
6452 }
6453
6454 /**
6455  * Interrupt handler triggered by NIC  for handling
6456  * specific interrupt.
6457  *
6458  * @param handle
6459  *  Pointer to interrupt handle.
6460  * @param param
6461  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6462  *
6463  * @return
6464  *  void
6465  */
6466 static void
6467 i40e_dev_interrupt_handler(void *param)
6468 {
6469         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6470         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6471         uint32_t icr0;
6472
6473         /* Disable interrupt */
6474         i40e_pf_disable_irq0(hw);
6475
6476         /* read out interrupt causes */
6477         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6478
6479         /* No interrupt event indicated */
6480         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6481                 PMD_DRV_LOG(INFO, "No interrupt event");
6482                 goto done;
6483         }
6484         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6485                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6486         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6487                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6488         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6489                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6490         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6491                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6492         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6493                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6494         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6495                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6496         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6497                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6498
6499         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6500                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6501                 i40e_dev_handle_vfr_event(dev);
6502         }
6503         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6504                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6505                 i40e_dev_handle_aq_msg(dev);
6506         }
6507
6508 done:
6509         /* Enable interrupt */
6510         i40e_pf_enable_irq0(hw);
6511         rte_intr_enable(dev->intr_handle);
6512 }
6513
6514 int
6515 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6516                          struct i40e_macvlan_filter *filter,
6517                          int total)
6518 {
6519         int ele_num, ele_buff_size;
6520         int num, actual_num, i;
6521         uint16_t flags;
6522         int ret = I40E_SUCCESS;
6523         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6524         struct i40e_aqc_add_macvlan_element_data *req_list;
6525
6526         if (filter == NULL  || total == 0)
6527                 return I40E_ERR_PARAM;
6528         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6529         ele_buff_size = hw->aq.asq_buf_size;
6530
6531         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6532         if (req_list == NULL) {
6533                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6534                 return I40E_ERR_NO_MEMORY;
6535         }
6536
6537         num = 0;
6538         do {
6539                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6540                 memset(req_list, 0, ele_buff_size);
6541
6542                 for (i = 0; i < actual_num; i++) {
6543                         rte_memcpy(req_list[i].mac_addr,
6544                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6545                         req_list[i].vlan_tag =
6546                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6547
6548                         switch (filter[num + i].filter_type) {
6549                         case RTE_MAC_PERFECT_MATCH:
6550                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6551                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6552                                 break;
6553                         case RTE_MACVLAN_PERFECT_MATCH:
6554                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6555                                 break;
6556                         case RTE_MAC_HASH_MATCH:
6557                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6558                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6559                                 break;
6560                         case RTE_MACVLAN_HASH_MATCH:
6561                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6562                                 break;
6563                         default:
6564                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6565                                 ret = I40E_ERR_PARAM;
6566                                 goto DONE;
6567                         }
6568
6569                         req_list[i].queue_number = 0;
6570
6571                         req_list[i].flags = rte_cpu_to_le_16(flags);
6572                 }
6573
6574                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6575                                                 actual_num, NULL);
6576                 if (ret != I40E_SUCCESS) {
6577                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6578                         goto DONE;
6579                 }
6580                 num += actual_num;
6581         } while (num < total);
6582
6583 DONE:
6584         rte_free(req_list);
6585         return ret;
6586 }
6587
6588 int
6589 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6590                             struct i40e_macvlan_filter *filter,
6591                             int total)
6592 {
6593         int ele_num, ele_buff_size;
6594         int num, actual_num, i;
6595         uint16_t flags;
6596         int ret = I40E_SUCCESS;
6597         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6598         struct i40e_aqc_remove_macvlan_element_data *req_list;
6599
6600         if (filter == NULL  || total == 0)
6601                 return I40E_ERR_PARAM;
6602
6603         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6604         ele_buff_size = hw->aq.asq_buf_size;
6605
6606         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6607         if (req_list == NULL) {
6608                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6609                 return I40E_ERR_NO_MEMORY;
6610         }
6611
6612         num = 0;
6613         do {
6614                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6615                 memset(req_list, 0, ele_buff_size);
6616
6617                 for (i = 0; i < actual_num; i++) {
6618                         rte_memcpy(req_list[i].mac_addr,
6619                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6620                         req_list[i].vlan_tag =
6621                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6622
6623                         switch (filter[num + i].filter_type) {
6624                         case RTE_MAC_PERFECT_MATCH:
6625                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6626                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6627                                 break;
6628                         case RTE_MACVLAN_PERFECT_MATCH:
6629                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6630                                 break;
6631                         case RTE_MAC_HASH_MATCH:
6632                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6633                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6634                                 break;
6635                         case RTE_MACVLAN_HASH_MATCH:
6636                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6637                                 break;
6638                         default:
6639                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6640                                 ret = I40E_ERR_PARAM;
6641                                 goto DONE;
6642                         }
6643                         req_list[i].flags = rte_cpu_to_le_16(flags);
6644                 }
6645
6646                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6647                                                 actual_num, NULL);
6648                 if (ret != I40E_SUCCESS) {
6649                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6650                         goto DONE;
6651                 }
6652                 num += actual_num;
6653         } while (num < total);
6654
6655 DONE:
6656         rte_free(req_list);
6657         return ret;
6658 }
6659
6660 /* Find out specific MAC filter */
6661 static struct i40e_mac_filter *
6662 i40e_find_mac_filter(struct i40e_vsi *vsi,
6663                          struct ether_addr *macaddr)
6664 {
6665         struct i40e_mac_filter *f;
6666
6667         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6668                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6669                         return f;
6670         }
6671
6672         return NULL;
6673 }
6674
6675 static bool
6676 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6677                          uint16_t vlan_id)
6678 {
6679         uint32_t vid_idx, vid_bit;
6680
6681         if (vlan_id > ETH_VLAN_ID_MAX)
6682                 return 0;
6683
6684         vid_idx = I40E_VFTA_IDX(vlan_id);
6685         vid_bit = I40E_VFTA_BIT(vlan_id);
6686
6687         if (vsi->vfta[vid_idx] & vid_bit)
6688                 return 1;
6689         else
6690                 return 0;
6691 }
6692
6693 static void
6694 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6695                        uint16_t vlan_id, bool on)
6696 {
6697         uint32_t vid_idx, vid_bit;
6698
6699         vid_idx = I40E_VFTA_IDX(vlan_id);
6700         vid_bit = I40E_VFTA_BIT(vlan_id);
6701
6702         if (on)
6703                 vsi->vfta[vid_idx] |= vid_bit;
6704         else
6705                 vsi->vfta[vid_idx] &= ~vid_bit;
6706 }
6707
6708 void
6709 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6710                      uint16_t vlan_id, bool on)
6711 {
6712         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6713         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6714         int ret;
6715
6716         if (vlan_id > ETH_VLAN_ID_MAX)
6717                 return;
6718
6719         i40e_store_vlan_filter(vsi, vlan_id, on);
6720
6721         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6722                 return;
6723
6724         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6725
6726         if (on) {
6727                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6728                                        &vlan_data, 1, NULL);
6729                 if (ret != I40E_SUCCESS)
6730                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6731         } else {
6732                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6733                                           &vlan_data, 1, NULL);
6734                 if (ret != I40E_SUCCESS)
6735                         PMD_DRV_LOG(ERR,
6736                                     "Failed to remove vlan filter");
6737         }
6738 }
6739
6740 /**
6741  * Find all vlan options for specific mac addr,
6742  * return with actual vlan found.
6743  */
6744 int
6745 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6746                            struct i40e_macvlan_filter *mv_f,
6747                            int num, struct ether_addr *addr)
6748 {
6749         int i;
6750         uint32_t j, k;
6751
6752         /**
6753          * Not to use i40e_find_vlan_filter to decrease the loop time,
6754          * although the code looks complex.
6755           */
6756         if (num < vsi->vlan_num)
6757                 return I40E_ERR_PARAM;
6758
6759         i = 0;
6760         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6761                 if (vsi->vfta[j]) {
6762                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6763                                 if (vsi->vfta[j] & (1 << k)) {
6764                                         if (i > num - 1) {
6765                                                 PMD_DRV_LOG(ERR,
6766                                                         "vlan number doesn't match");
6767                                                 return I40E_ERR_PARAM;
6768                                         }
6769                                         rte_memcpy(&mv_f[i].macaddr,
6770                                                         addr, ETH_ADDR_LEN);
6771                                         mv_f[i].vlan_id =
6772                                                 j * I40E_UINT32_BIT_SIZE + k;
6773                                         i++;
6774                                 }
6775                         }
6776                 }
6777         }
6778         return I40E_SUCCESS;
6779 }
6780
6781 static inline int
6782 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6783                            struct i40e_macvlan_filter *mv_f,
6784                            int num,
6785                            uint16_t vlan)
6786 {
6787         int i = 0;
6788         struct i40e_mac_filter *f;
6789
6790         if (num < vsi->mac_num)
6791                 return I40E_ERR_PARAM;
6792
6793         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6794                 if (i > num - 1) {
6795                         PMD_DRV_LOG(ERR, "buffer number not match");
6796                         return I40E_ERR_PARAM;
6797                 }
6798                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6799                                 ETH_ADDR_LEN);
6800                 mv_f[i].vlan_id = vlan;
6801                 mv_f[i].filter_type = f->mac_info.filter_type;
6802                 i++;
6803         }
6804
6805         return I40E_SUCCESS;
6806 }
6807
6808 static int
6809 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6810 {
6811         int i, j, num;
6812         struct i40e_mac_filter *f;
6813         struct i40e_macvlan_filter *mv_f;
6814         int ret = I40E_SUCCESS;
6815
6816         if (vsi == NULL || vsi->mac_num == 0)
6817                 return I40E_ERR_PARAM;
6818
6819         /* Case that no vlan is set */
6820         if (vsi->vlan_num == 0)
6821                 num = vsi->mac_num;
6822         else
6823                 num = vsi->mac_num * vsi->vlan_num;
6824
6825         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6826         if (mv_f == NULL) {
6827                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6828                 return I40E_ERR_NO_MEMORY;
6829         }
6830
6831         i = 0;
6832         if (vsi->vlan_num == 0) {
6833                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6834                         rte_memcpy(&mv_f[i].macaddr,
6835                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6836                         mv_f[i].filter_type = f->mac_info.filter_type;
6837                         mv_f[i].vlan_id = 0;
6838                         i++;
6839                 }
6840         } else {
6841                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6842                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6843                                         vsi->vlan_num, &f->mac_info.mac_addr);
6844                         if (ret != I40E_SUCCESS)
6845                                 goto DONE;
6846                         for (j = i; j < i + vsi->vlan_num; j++)
6847                                 mv_f[j].filter_type = f->mac_info.filter_type;
6848                         i += vsi->vlan_num;
6849                 }
6850         }
6851
6852         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6853 DONE:
6854         rte_free(mv_f);
6855
6856         return ret;
6857 }
6858
6859 int
6860 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6861 {
6862         struct i40e_macvlan_filter *mv_f;
6863         int mac_num;
6864         int ret = I40E_SUCCESS;
6865
6866         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6867                 return I40E_ERR_PARAM;
6868
6869         /* If it's already set, just return */
6870         if (i40e_find_vlan_filter(vsi,vlan))
6871                 return I40E_SUCCESS;
6872
6873         mac_num = vsi->mac_num;
6874
6875         if (mac_num == 0) {
6876                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6877                 return I40E_ERR_PARAM;
6878         }
6879
6880         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6881
6882         if (mv_f == NULL) {
6883                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6884                 return I40E_ERR_NO_MEMORY;
6885         }
6886
6887         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6888
6889         if (ret != I40E_SUCCESS)
6890                 goto DONE;
6891
6892         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6893
6894         if (ret != I40E_SUCCESS)
6895                 goto DONE;
6896
6897         i40e_set_vlan_filter(vsi, vlan, 1);
6898
6899         vsi->vlan_num++;
6900         ret = I40E_SUCCESS;
6901 DONE:
6902         rte_free(mv_f);
6903         return ret;
6904 }
6905
6906 int
6907 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6908 {
6909         struct i40e_macvlan_filter *mv_f;
6910         int mac_num;
6911         int ret = I40E_SUCCESS;
6912
6913         /**
6914          * Vlan 0 is the generic filter for untagged packets
6915          * and can't be removed.
6916          */
6917         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6918                 return I40E_ERR_PARAM;
6919
6920         /* If can't find it, just return */
6921         if (!i40e_find_vlan_filter(vsi, vlan))
6922                 return I40E_ERR_PARAM;
6923
6924         mac_num = vsi->mac_num;
6925
6926         if (mac_num == 0) {
6927                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6928                 return I40E_ERR_PARAM;
6929         }
6930
6931         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6932
6933         if (mv_f == NULL) {
6934                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6935                 return I40E_ERR_NO_MEMORY;
6936         }
6937
6938         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6939
6940         if (ret != I40E_SUCCESS)
6941                 goto DONE;
6942
6943         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6944
6945         if (ret != I40E_SUCCESS)
6946                 goto DONE;
6947
6948         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6949         if (vsi->vlan_num == 1) {
6950                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6951                 if (ret != I40E_SUCCESS)
6952                         goto DONE;
6953
6954                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6955                 if (ret != I40E_SUCCESS)
6956                         goto DONE;
6957         }
6958
6959         i40e_set_vlan_filter(vsi, vlan, 0);
6960
6961         vsi->vlan_num--;
6962         ret = I40E_SUCCESS;
6963 DONE:
6964         rte_free(mv_f);
6965         return ret;
6966 }
6967
6968 int
6969 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6970 {
6971         struct i40e_mac_filter *f;
6972         struct i40e_macvlan_filter *mv_f;
6973         int i, vlan_num = 0;
6974         int ret = I40E_SUCCESS;
6975
6976         /* If it's add and we've config it, return */
6977         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6978         if (f != NULL)
6979                 return I40E_SUCCESS;
6980         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6981                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6982
6983                 /**
6984                  * If vlan_num is 0, that's the first time to add mac,
6985                  * set mask for vlan_id 0.
6986                  */
6987                 if (vsi->vlan_num == 0) {
6988                         i40e_set_vlan_filter(vsi, 0, 1);
6989                         vsi->vlan_num = 1;
6990                 }
6991                 vlan_num = vsi->vlan_num;
6992         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6993                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6994                 vlan_num = 1;
6995
6996         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6997         if (mv_f == NULL) {
6998                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6999                 return I40E_ERR_NO_MEMORY;
7000         }
7001
7002         for (i = 0; i < vlan_num; i++) {
7003                 mv_f[i].filter_type = mac_filter->filter_type;
7004                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7005                                 ETH_ADDR_LEN);
7006         }
7007
7008         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7009                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7010                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7011                                         &mac_filter->mac_addr);
7012                 if (ret != I40E_SUCCESS)
7013                         goto DONE;
7014         }
7015
7016         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7017         if (ret != I40E_SUCCESS)
7018                 goto DONE;
7019
7020         /* Add the mac addr into mac list */
7021         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7022         if (f == NULL) {
7023                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7024                 ret = I40E_ERR_NO_MEMORY;
7025                 goto DONE;
7026         }
7027         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7028                         ETH_ADDR_LEN);
7029         f->mac_info.filter_type = mac_filter->filter_type;
7030         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7031         vsi->mac_num++;
7032
7033         ret = I40E_SUCCESS;
7034 DONE:
7035         rte_free(mv_f);
7036
7037         return ret;
7038 }
7039
7040 int
7041 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7042 {
7043         struct i40e_mac_filter *f;
7044         struct i40e_macvlan_filter *mv_f;
7045         int i, vlan_num;
7046         enum rte_mac_filter_type filter_type;
7047         int ret = I40E_SUCCESS;
7048
7049         /* Can't find it, return an error */
7050         f = i40e_find_mac_filter(vsi, addr);
7051         if (f == NULL)
7052                 return I40E_ERR_PARAM;
7053
7054         vlan_num = vsi->vlan_num;
7055         filter_type = f->mac_info.filter_type;
7056         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7057                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7058                 if (vlan_num == 0) {
7059                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7060                         return I40E_ERR_PARAM;
7061                 }
7062         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7063                         filter_type == RTE_MAC_HASH_MATCH)
7064                 vlan_num = 1;
7065
7066         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7067         if (mv_f == NULL) {
7068                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7069                 return I40E_ERR_NO_MEMORY;
7070         }
7071
7072         for (i = 0; i < vlan_num; i++) {
7073                 mv_f[i].filter_type = filter_type;
7074                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7075                                 ETH_ADDR_LEN);
7076         }
7077         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7078                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7079                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7080                 if (ret != I40E_SUCCESS)
7081                         goto DONE;
7082         }
7083
7084         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7085         if (ret != I40E_SUCCESS)
7086                 goto DONE;
7087
7088         /* Remove the mac addr into mac list */
7089         TAILQ_REMOVE(&vsi->mac_list, f, next);
7090         rte_free(f);
7091         vsi->mac_num--;
7092
7093         ret = I40E_SUCCESS;
7094 DONE:
7095         rte_free(mv_f);
7096         return ret;
7097 }
7098
7099 /* Configure hash enable flags for RSS */
7100 uint64_t
7101 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7102 {
7103         uint64_t hena = 0;
7104         int i;
7105
7106         if (!flags)
7107                 return hena;
7108
7109         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7110                 if (flags & (1ULL << i))
7111                         hena |= adapter->pctypes_tbl[i];
7112         }
7113
7114         return hena;
7115 }
7116
7117 /* Parse the hash enable flags */
7118 uint64_t
7119 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7120 {
7121         uint64_t rss_hf = 0;
7122
7123         if (!flags)
7124                 return rss_hf;
7125         int i;
7126
7127         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7128                 if (flags & adapter->pctypes_tbl[i])
7129                         rss_hf |= (1ULL << i);
7130         }
7131         return rss_hf;
7132 }
7133
7134 /* Disable RSS */
7135 static void
7136 i40e_pf_disable_rss(struct i40e_pf *pf)
7137 {
7138         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7139
7140         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7141         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7142         I40E_WRITE_FLUSH(hw);
7143 }
7144
7145 int
7146 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7147 {
7148         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7149         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7150         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7151                            I40E_VFQF_HKEY_MAX_INDEX :
7152                            I40E_PFQF_HKEY_MAX_INDEX;
7153         int ret = 0;
7154
7155         if (!key || key_len == 0) {
7156                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7157                 return 0;
7158         } else if (key_len != (key_idx + 1) *
7159                 sizeof(uint32_t)) {
7160                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7161                 return -EINVAL;
7162         }
7163
7164         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7165                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7166                         (struct i40e_aqc_get_set_rss_key_data *)key;
7167
7168                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7169                 if (ret)
7170                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7171         } else {
7172                 uint32_t *hash_key = (uint32_t *)key;
7173                 uint16_t i;
7174
7175                 if (vsi->type == I40E_VSI_SRIOV) {
7176                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7177                                 I40E_WRITE_REG(
7178                                         hw,
7179                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7180                                         hash_key[i]);
7181
7182                 } else {
7183                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7184                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7185                                                hash_key[i]);
7186                 }
7187                 I40E_WRITE_FLUSH(hw);
7188         }
7189
7190         return ret;
7191 }
7192
7193 static int
7194 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7195 {
7196         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7197         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7198         uint32_t reg;
7199         int ret;
7200
7201         if (!key || !key_len)
7202                 return -EINVAL;
7203
7204         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7205                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7206                         (struct i40e_aqc_get_set_rss_key_data *)key);
7207                 if (ret) {
7208                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7209                         return ret;
7210                 }
7211         } else {
7212                 uint32_t *key_dw = (uint32_t *)key;
7213                 uint16_t i;
7214
7215                 if (vsi->type == I40E_VSI_SRIOV) {
7216                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7217                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7218                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7219                         }
7220                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7221                                    sizeof(uint32_t);
7222                 } else {
7223                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7224                                 reg = I40E_PFQF_HKEY(i);
7225                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7226                         }
7227                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7228                                    sizeof(uint32_t);
7229                 }
7230         }
7231         return 0;
7232 }
7233
7234 static int
7235 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7236 {
7237         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7238         uint64_t hena;
7239         int ret;
7240
7241         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7242                                rss_conf->rss_key_len);
7243         if (ret)
7244                 return ret;
7245
7246         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7247         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7248         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7249         I40E_WRITE_FLUSH(hw);
7250
7251         return 0;
7252 }
7253
7254 static int
7255 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7256                          struct rte_eth_rss_conf *rss_conf)
7257 {
7258         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7259         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7260         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7261         uint64_t hena;
7262
7263         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7264         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7265
7266         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7267                 if (rss_hf != 0) /* Enable RSS */
7268                         return -EINVAL;
7269                 return 0; /* Nothing to do */
7270         }
7271         /* RSS enabled */
7272         if (rss_hf == 0) /* Disable RSS */
7273                 return -EINVAL;
7274
7275         return i40e_hw_rss_hash_set(pf, rss_conf);
7276 }
7277
7278 static int
7279 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7280                            struct rte_eth_rss_conf *rss_conf)
7281 {
7282         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7283         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7284         uint64_t hena;
7285
7286         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7287                          &rss_conf->rss_key_len);
7288
7289         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7290         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7291         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7292
7293         return 0;
7294 }
7295
7296 static int
7297 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7298 {
7299         switch (filter_type) {
7300         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7301                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7302                 break;
7303         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7304                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7305                 break;
7306         case RTE_TUNNEL_FILTER_IMAC_TENID:
7307                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7308                 break;
7309         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7310                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7311                 break;
7312         case ETH_TUNNEL_FILTER_IMAC:
7313                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7314                 break;
7315         case ETH_TUNNEL_FILTER_OIP:
7316                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7317                 break;
7318         case ETH_TUNNEL_FILTER_IIP:
7319                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7320                 break;
7321         default:
7322                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7323                 return -EINVAL;
7324         }
7325
7326         return 0;
7327 }
7328
7329 /* Convert tunnel filter structure */
7330 static int
7331 i40e_tunnel_filter_convert(
7332         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7333         struct i40e_tunnel_filter *tunnel_filter)
7334 {
7335         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7336                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7337         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7338                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7339         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7340         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7341              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7342             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7343                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7344         else
7345                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7346         tunnel_filter->input.flags = cld_filter->element.flags;
7347         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7348         tunnel_filter->queue = cld_filter->element.queue_number;
7349         rte_memcpy(tunnel_filter->input.general_fields,
7350                    cld_filter->general_fields,
7351                    sizeof(cld_filter->general_fields));
7352
7353         return 0;
7354 }
7355
7356 /* Check if there exists the tunnel filter */
7357 struct i40e_tunnel_filter *
7358 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7359                              const struct i40e_tunnel_filter_input *input)
7360 {
7361         int ret;
7362
7363         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7364         if (ret < 0)
7365                 return NULL;
7366
7367         return tunnel_rule->hash_map[ret];
7368 }
7369
7370 /* Add a tunnel filter into the SW list */
7371 static int
7372 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7373                              struct i40e_tunnel_filter *tunnel_filter)
7374 {
7375         struct i40e_tunnel_rule *rule = &pf->tunnel;
7376         int ret;
7377
7378         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7379         if (ret < 0) {
7380                 PMD_DRV_LOG(ERR,
7381                             "Failed to insert tunnel filter to hash table %d!",
7382                             ret);
7383                 return ret;
7384         }
7385         rule->hash_map[ret] = tunnel_filter;
7386
7387         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7388
7389         return 0;
7390 }
7391
7392 /* Delete a tunnel filter from the SW list */
7393 int
7394 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7395                           struct i40e_tunnel_filter_input *input)
7396 {
7397         struct i40e_tunnel_rule *rule = &pf->tunnel;
7398         struct i40e_tunnel_filter *tunnel_filter;
7399         int ret;
7400
7401         ret = rte_hash_del_key(rule->hash_table, input);
7402         if (ret < 0) {
7403                 PMD_DRV_LOG(ERR,
7404                             "Failed to delete tunnel filter to hash table %d!",
7405                             ret);
7406                 return ret;
7407         }
7408         tunnel_filter = rule->hash_map[ret];
7409         rule->hash_map[ret] = NULL;
7410
7411         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7412         rte_free(tunnel_filter);
7413
7414         return 0;
7415 }
7416
7417 int
7418 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7419                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7420                         uint8_t add)
7421 {
7422         uint16_t ip_type;
7423         uint32_t ipv4_addr, ipv4_addr_le;
7424         uint8_t i, tun_type = 0;
7425         /* internal varialbe to convert ipv6 byte order */
7426         uint32_t convert_ipv6[4];
7427         int val, ret = 0;
7428         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7429         struct i40e_vsi *vsi = pf->main_vsi;
7430         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7431         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7432         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7433         struct i40e_tunnel_filter *tunnel, *node;
7434         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7435
7436         cld_filter = rte_zmalloc("tunnel_filter",
7437                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7438         0);
7439
7440         if (NULL == cld_filter) {
7441                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7442                 return -ENOMEM;
7443         }
7444         pfilter = cld_filter;
7445
7446         ether_addr_copy(&tunnel_filter->outer_mac,
7447                         (struct ether_addr *)&pfilter->element.outer_mac);
7448         ether_addr_copy(&tunnel_filter->inner_mac,
7449                         (struct ether_addr *)&pfilter->element.inner_mac);
7450
7451         pfilter->element.inner_vlan =
7452                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7453         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7454                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7455                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7456                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7457                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7458                                 &ipv4_addr_le,
7459                                 sizeof(pfilter->element.ipaddr.v4.data));
7460         } else {
7461                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7462                 for (i = 0; i < 4; i++) {
7463                         convert_ipv6[i] =
7464                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7465                 }
7466                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7467                            &convert_ipv6,
7468                            sizeof(pfilter->element.ipaddr.v6.data));
7469         }
7470
7471         /* check tunneled type */
7472         switch (tunnel_filter->tunnel_type) {
7473         case RTE_TUNNEL_TYPE_VXLAN:
7474                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7475                 break;
7476         case RTE_TUNNEL_TYPE_NVGRE:
7477                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7478                 break;
7479         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7480                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7481                 break;
7482         default:
7483                 /* Other tunnel types is not supported. */
7484                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7485                 rte_free(cld_filter);
7486                 return -EINVAL;
7487         }
7488
7489         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7490                                        &pfilter->element.flags);
7491         if (val < 0) {
7492                 rte_free(cld_filter);
7493                 return -EINVAL;
7494         }
7495
7496         pfilter->element.flags |= rte_cpu_to_le_16(
7497                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7498                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7499         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7500         pfilter->element.queue_number =
7501                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7502
7503         /* Check if there is the filter in SW list */
7504         memset(&check_filter, 0, sizeof(check_filter));
7505         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7506         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7507         if (add && node) {
7508                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7509                 rte_free(cld_filter);
7510                 return -EINVAL;
7511         }
7512
7513         if (!add && !node) {
7514                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7515                 rte_free(cld_filter);
7516                 return -EINVAL;
7517         }
7518
7519         if (add) {
7520                 ret = i40e_aq_add_cloud_filters(hw,
7521                                         vsi->seid, &cld_filter->element, 1);
7522                 if (ret < 0) {
7523                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7524                         rte_free(cld_filter);
7525                         return -ENOTSUP;
7526                 }
7527                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7528                 if (tunnel == NULL) {
7529                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7530                         rte_free(cld_filter);
7531                         return -ENOMEM;
7532                 }
7533
7534                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7535                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7536                 if (ret < 0)
7537                         rte_free(tunnel);
7538         } else {
7539                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7540                                                    &cld_filter->element, 1);
7541                 if (ret < 0) {
7542                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7543                         rte_free(cld_filter);
7544                         return -ENOTSUP;
7545                 }
7546                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7547         }
7548
7549         rte_free(cld_filter);
7550         return ret;
7551 }
7552
7553 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7554 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7555 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7556 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7557 #define I40E_TR_GRE_KEY_MASK                    0x400
7558 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7559 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7560
7561 static enum
7562 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7563 {
7564         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7565         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7566         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7567         enum i40e_status_code status = I40E_SUCCESS;
7568
7569         if (pf->support_multi_driver) {
7570                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7571                 return I40E_NOT_SUPPORTED;
7572         }
7573
7574         memset(&filter_replace, 0,
7575                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7576         memset(&filter_replace_buf, 0,
7577                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7578
7579         /* create L1 filter */
7580         filter_replace.old_filter_type =
7581                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7582         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7583         filter_replace.tr_bit = 0;
7584
7585         /* Prepare the buffer, 3 entries */
7586         filter_replace_buf.data[0] =
7587                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7588         filter_replace_buf.data[0] |=
7589                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7590         filter_replace_buf.data[2] = 0xFF;
7591         filter_replace_buf.data[3] = 0xFF;
7592         filter_replace_buf.data[4] =
7593                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7594         filter_replace_buf.data[4] |=
7595                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7596         filter_replace_buf.data[7] = 0xF0;
7597         filter_replace_buf.data[8]
7598                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7599         filter_replace_buf.data[8] |=
7600                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7601         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7602                 I40E_TR_GENEVE_KEY_MASK |
7603                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7604         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7605                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7606                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7607
7608         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7609                                                &filter_replace_buf);
7610         if (!status) {
7611                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7612                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7613                             "cloud l1 type is changed from 0x%x to 0x%x",
7614                             filter_replace.old_filter_type,
7615                             filter_replace.new_filter_type);
7616         }
7617         return status;
7618 }
7619
7620 static enum
7621 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7622 {
7623         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7624         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7625         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7626         enum i40e_status_code status = I40E_SUCCESS;
7627
7628         if (pf->support_multi_driver) {
7629                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7630                 return I40E_NOT_SUPPORTED;
7631         }
7632
7633         /* For MPLSoUDP */
7634         memset(&filter_replace, 0,
7635                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7636         memset(&filter_replace_buf, 0,
7637                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7638         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7639                 I40E_AQC_MIRROR_CLOUD_FILTER;
7640         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7641         filter_replace.new_filter_type =
7642                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7643         /* Prepare the buffer, 2 entries */
7644         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7645         filter_replace_buf.data[0] |=
7646                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7647         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7648         filter_replace_buf.data[4] |=
7649                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7650         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7651                                                &filter_replace_buf);
7652         if (status < 0)
7653                 return status;
7654         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7655                     "cloud filter type is changed from 0x%x to 0x%x",
7656                     filter_replace.old_filter_type,
7657                     filter_replace.new_filter_type);
7658
7659         /* For MPLSoGRE */
7660         memset(&filter_replace, 0,
7661                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7662         memset(&filter_replace_buf, 0,
7663                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7664
7665         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7666                 I40E_AQC_MIRROR_CLOUD_FILTER;
7667         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7668         filter_replace.new_filter_type =
7669                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7670         /* Prepare the buffer, 2 entries */
7671         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7672         filter_replace_buf.data[0] |=
7673                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7674         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7675         filter_replace_buf.data[4] |=
7676                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7677
7678         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7679                                                &filter_replace_buf);
7680         if (!status) {
7681                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7682                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7683                             "cloud filter type is changed from 0x%x to 0x%x",
7684                             filter_replace.old_filter_type,
7685                             filter_replace.new_filter_type);
7686         }
7687         return status;
7688 }
7689
7690 static enum i40e_status_code
7691 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7692 {
7693         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7694         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7695         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7696         enum i40e_status_code status = I40E_SUCCESS;
7697
7698         if (pf->support_multi_driver) {
7699                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7700                 return I40E_NOT_SUPPORTED;
7701         }
7702
7703         /* For GTP-C */
7704         memset(&filter_replace, 0,
7705                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7706         memset(&filter_replace_buf, 0,
7707                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7708         /* create L1 filter */
7709         filter_replace.old_filter_type =
7710                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7711         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7712         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7713                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7714         /* Prepare the buffer, 2 entries */
7715         filter_replace_buf.data[0] =
7716                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7717         filter_replace_buf.data[0] |=
7718                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7719         filter_replace_buf.data[2] = 0xFF;
7720         filter_replace_buf.data[3] = 0xFF;
7721         filter_replace_buf.data[4] =
7722                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7723         filter_replace_buf.data[4] |=
7724                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7725         filter_replace_buf.data[6] = 0xFF;
7726         filter_replace_buf.data[7] = 0xFF;
7727         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7728                                                &filter_replace_buf);
7729         if (status < 0)
7730                 return status;
7731         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7732                     "cloud l1 type is changed from 0x%x to 0x%x",
7733                     filter_replace.old_filter_type,
7734                     filter_replace.new_filter_type);
7735
7736         /* for GTP-U */
7737         memset(&filter_replace, 0,
7738                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7739         memset(&filter_replace_buf, 0,
7740                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7741         /* create L1 filter */
7742         filter_replace.old_filter_type =
7743                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7744         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7745         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7746                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7747         /* Prepare the buffer, 2 entries */
7748         filter_replace_buf.data[0] =
7749                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7750         filter_replace_buf.data[0] |=
7751                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7752         filter_replace_buf.data[2] = 0xFF;
7753         filter_replace_buf.data[3] = 0xFF;
7754         filter_replace_buf.data[4] =
7755                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7756         filter_replace_buf.data[4] |=
7757                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7758         filter_replace_buf.data[6] = 0xFF;
7759         filter_replace_buf.data[7] = 0xFF;
7760
7761         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7762                                                &filter_replace_buf);
7763         if (!status) {
7764                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7765                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7766                             "cloud l1 type is changed from 0x%x to 0x%x",
7767                             filter_replace.old_filter_type,
7768                             filter_replace.new_filter_type);
7769         }
7770         return status;
7771 }
7772
7773 static enum
7774 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7775 {
7776         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7777         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7778         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7779         enum i40e_status_code status = I40E_SUCCESS;
7780
7781         if (pf->support_multi_driver) {
7782                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7783                 return I40E_NOT_SUPPORTED;
7784         }
7785
7786         /* for GTP-C */
7787         memset(&filter_replace, 0,
7788                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7789         memset(&filter_replace_buf, 0,
7790                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7791         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7792         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7793         filter_replace.new_filter_type =
7794                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7795         /* Prepare the buffer, 2 entries */
7796         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7797         filter_replace_buf.data[0] |=
7798                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7799         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7800         filter_replace_buf.data[4] |=
7801                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7802         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7803                                                &filter_replace_buf);
7804         if (status < 0)
7805                 return status;
7806         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7807                     "cloud filter type is changed from 0x%x to 0x%x",
7808                     filter_replace.old_filter_type,
7809                     filter_replace.new_filter_type);
7810
7811         /* for GTP-U */
7812         memset(&filter_replace, 0,
7813                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7814         memset(&filter_replace_buf, 0,
7815                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7816         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7817         filter_replace.old_filter_type =
7818                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7819         filter_replace.new_filter_type =
7820                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7821         /* Prepare the buffer, 2 entries */
7822         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7823         filter_replace_buf.data[0] |=
7824                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7825         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7826         filter_replace_buf.data[4] |=
7827                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7828
7829         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7830                                                &filter_replace_buf);
7831         if (!status) {
7832                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7833                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7834                             "cloud filter type is changed from 0x%x to 0x%x",
7835                             filter_replace.old_filter_type,
7836                             filter_replace.new_filter_type);
7837         }
7838         return status;
7839 }
7840
7841 int
7842 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7843                       struct i40e_tunnel_filter_conf *tunnel_filter,
7844                       uint8_t add)
7845 {
7846         uint16_t ip_type;
7847         uint32_t ipv4_addr, ipv4_addr_le;
7848         uint8_t i, tun_type = 0;
7849         /* internal variable to convert ipv6 byte order */
7850         uint32_t convert_ipv6[4];
7851         int val, ret = 0;
7852         struct i40e_pf_vf *vf = NULL;
7853         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7854         struct i40e_vsi *vsi;
7855         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7856         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7857         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7858         struct i40e_tunnel_filter *tunnel, *node;
7859         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7860         uint32_t teid_le;
7861         bool big_buffer = 0;
7862
7863         cld_filter = rte_zmalloc("tunnel_filter",
7864                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7865                          0);
7866
7867         if (cld_filter == NULL) {
7868                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7869                 return -ENOMEM;
7870         }
7871         pfilter = cld_filter;
7872
7873         ether_addr_copy(&tunnel_filter->outer_mac,
7874                         (struct ether_addr *)&pfilter->element.outer_mac);
7875         ether_addr_copy(&tunnel_filter->inner_mac,
7876                         (struct ether_addr *)&pfilter->element.inner_mac);
7877
7878         pfilter->element.inner_vlan =
7879                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7880         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7881                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7882                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7883                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7884                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7885                                 &ipv4_addr_le,
7886                                 sizeof(pfilter->element.ipaddr.v4.data));
7887         } else {
7888                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7889                 for (i = 0; i < 4; i++) {
7890                         convert_ipv6[i] =
7891                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7892                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7893                 }
7894                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7895                            &convert_ipv6,
7896                            sizeof(pfilter->element.ipaddr.v6.data));
7897         }
7898
7899         /* check tunneled type */
7900         switch (tunnel_filter->tunnel_type) {
7901         case I40E_TUNNEL_TYPE_VXLAN:
7902                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7903                 break;
7904         case I40E_TUNNEL_TYPE_NVGRE:
7905                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7906                 break;
7907         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7908                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7909                 break;
7910         case I40E_TUNNEL_TYPE_MPLSoUDP:
7911                 if (!pf->mpls_replace_flag) {
7912                         i40e_replace_mpls_l1_filter(pf);
7913                         i40e_replace_mpls_cloud_filter(pf);
7914                         pf->mpls_replace_flag = 1;
7915                 }
7916                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7917                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7918                         teid_le >> 4;
7919                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7920                         (teid_le & 0xF) << 12;
7921                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7922                         0x40;
7923                 big_buffer = 1;
7924                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7925                 break;
7926         case I40E_TUNNEL_TYPE_MPLSoGRE:
7927                 if (!pf->mpls_replace_flag) {
7928                         i40e_replace_mpls_l1_filter(pf);
7929                         i40e_replace_mpls_cloud_filter(pf);
7930                         pf->mpls_replace_flag = 1;
7931                 }
7932                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7933                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7934                         teid_le >> 4;
7935                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7936                         (teid_le & 0xF) << 12;
7937                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7938                         0x0;
7939                 big_buffer = 1;
7940                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7941                 break;
7942         case I40E_TUNNEL_TYPE_GTPC:
7943                 if (!pf->gtp_replace_flag) {
7944                         i40e_replace_gtp_l1_filter(pf);
7945                         i40e_replace_gtp_cloud_filter(pf);
7946                         pf->gtp_replace_flag = 1;
7947                 }
7948                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7949                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7950                         (teid_le >> 16) & 0xFFFF;
7951                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7952                         teid_le & 0xFFFF;
7953                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7954                         0x0;
7955                 big_buffer = 1;
7956                 break;
7957         case I40E_TUNNEL_TYPE_GTPU:
7958                 if (!pf->gtp_replace_flag) {
7959                         i40e_replace_gtp_l1_filter(pf);
7960                         i40e_replace_gtp_cloud_filter(pf);
7961                         pf->gtp_replace_flag = 1;
7962                 }
7963                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7964                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7965                         (teid_le >> 16) & 0xFFFF;
7966                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7967                         teid_le & 0xFFFF;
7968                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7969                         0x0;
7970                 big_buffer = 1;
7971                 break;
7972         case I40E_TUNNEL_TYPE_QINQ:
7973                 if (!pf->qinq_replace_flag) {
7974                         ret = i40e_cloud_filter_qinq_create(pf);
7975                         if (ret < 0)
7976                                 PMD_DRV_LOG(DEBUG,
7977                                             "QinQ tunnel filter already created.");
7978                         pf->qinq_replace_flag = 1;
7979                 }
7980                 /*      Add in the General fields the values of
7981                  *      the Outer and Inner VLAN
7982                  *      Big Buffer should be set, see changes in
7983                  *      i40e_aq_add_cloud_filters
7984                  */
7985                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7986                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7987                 big_buffer = 1;
7988                 break;
7989         default:
7990                 /* Other tunnel types is not supported. */
7991                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7992                 rte_free(cld_filter);
7993                 return -EINVAL;
7994         }
7995
7996         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7997                 pfilter->element.flags =
7998                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7999         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8000                 pfilter->element.flags =
8001                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8002         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8003                 pfilter->element.flags =
8004                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8005         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8006                 pfilter->element.flags =
8007                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8008         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8009                 pfilter->element.flags |=
8010                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8011         else {
8012                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8013                                                 &pfilter->element.flags);
8014                 if (val < 0) {
8015                         rte_free(cld_filter);
8016                         return -EINVAL;
8017                 }
8018         }
8019
8020         pfilter->element.flags |= rte_cpu_to_le_16(
8021                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8022                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8023         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8024         pfilter->element.queue_number =
8025                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8026
8027         if (!tunnel_filter->is_to_vf)
8028                 vsi = pf->main_vsi;
8029         else {
8030                 if (tunnel_filter->vf_id >= pf->vf_num) {
8031                         PMD_DRV_LOG(ERR, "Invalid argument.");
8032                         rte_free(cld_filter);
8033                         return -EINVAL;
8034                 }
8035                 vf = &pf->vfs[tunnel_filter->vf_id];
8036                 vsi = vf->vsi;
8037         }
8038
8039         /* Check if there is the filter in SW list */
8040         memset(&check_filter, 0, sizeof(check_filter));
8041         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8042         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8043         check_filter.vf_id = tunnel_filter->vf_id;
8044         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8045         if (add && node) {
8046                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8047                 rte_free(cld_filter);
8048                 return -EINVAL;
8049         }
8050
8051         if (!add && !node) {
8052                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8053                 rte_free(cld_filter);
8054                 return -EINVAL;
8055         }
8056
8057         if (add) {
8058                 if (big_buffer)
8059                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
8060                                                    vsi->seid, cld_filter, 1);
8061                 else
8062                         ret = i40e_aq_add_cloud_filters(hw,
8063                                         vsi->seid, &cld_filter->element, 1);
8064                 if (ret < 0) {
8065                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8066                         rte_free(cld_filter);
8067                         return -ENOTSUP;
8068                 }
8069                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8070                 if (tunnel == NULL) {
8071                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8072                         rte_free(cld_filter);
8073                         return -ENOMEM;
8074                 }
8075
8076                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8077                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8078                 if (ret < 0)
8079                         rte_free(tunnel);
8080         } else {
8081                 if (big_buffer)
8082                         ret = i40e_aq_remove_cloud_filters_big_buffer(
8083                                 hw, vsi->seid, cld_filter, 1);
8084                 else
8085                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
8086                                                    &cld_filter->element, 1);
8087                 if (ret < 0) {
8088                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8089                         rte_free(cld_filter);
8090                         return -ENOTSUP;
8091                 }
8092                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8093         }
8094
8095         rte_free(cld_filter);
8096         return ret;
8097 }
8098
8099 static int
8100 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8101 {
8102         uint8_t i;
8103
8104         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8105                 if (pf->vxlan_ports[i] == port)
8106                         return i;
8107         }
8108
8109         return -1;
8110 }
8111
8112 static int
8113 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8114 {
8115         int  idx, ret;
8116         uint8_t filter_idx;
8117         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8118
8119         idx = i40e_get_vxlan_port_idx(pf, port);
8120
8121         /* Check if port already exists */
8122         if (idx >= 0) {
8123                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8124                 return -EINVAL;
8125         }
8126
8127         /* Now check if there is space to add the new port */
8128         idx = i40e_get_vxlan_port_idx(pf, 0);
8129         if (idx < 0) {
8130                 PMD_DRV_LOG(ERR,
8131                         "Maximum number of UDP ports reached, not adding port %d",
8132                         port);
8133                 return -ENOSPC;
8134         }
8135
8136         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8137                                         &filter_idx, NULL);
8138         if (ret < 0) {
8139                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8140                 return -1;
8141         }
8142
8143         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8144                          port,  filter_idx);
8145
8146         /* New port: add it and mark its index in the bitmap */
8147         pf->vxlan_ports[idx] = port;
8148         pf->vxlan_bitmap |= (1 << idx);
8149
8150         if (!(pf->flags & I40E_FLAG_VXLAN))
8151                 pf->flags |= I40E_FLAG_VXLAN;
8152
8153         return 0;
8154 }
8155
8156 static int
8157 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8158 {
8159         int idx;
8160         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8161
8162         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8163                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8164                 return -EINVAL;
8165         }
8166
8167         idx = i40e_get_vxlan_port_idx(pf, port);
8168
8169         if (idx < 0) {
8170                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8171                 return -EINVAL;
8172         }
8173
8174         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8175                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8176                 return -1;
8177         }
8178
8179         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8180                         port, idx);
8181
8182         pf->vxlan_ports[idx] = 0;
8183         pf->vxlan_bitmap &= ~(1 << idx);
8184
8185         if (!pf->vxlan_bitmap)
8186                 pf->flags &= ~I40E_FLAG_VXLAN;
8187
8188         return 0;
8189 }
8190
8191 /* Add UDP tunneling port */
8192 static int
8193 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8194                              struct rte_eth_udp_tunnel *udp_tunnel)
8195 {
8196         int ret = 0;
8197         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8198
8199         if (udp_tunnel == NULL)
8200                 return -EINVAL;
8201
8202         switch (udp_tunnel->prot_type) {
8203         case RTE_TUNNEL_TYPE_VXLAN:
8204                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8205                 break;
8206
8207         case RTE_TUNNEL_TYPE_GENEVE:
8208         case RTE_TUNNEL_TYPE_TEREDO:
8209                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8210                 ret = -1;
8211                 break;
8212
8213         default:
8214                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8215                 ret = -1;
8216                 break;
8217         }
8218
8219         return ret;
8220 }
8221
8222 /* Remove UDP tunneling port */
8223 static int
8224 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8225                              struct rte_eth_udp_tunnel *udp_tunnel)
8226 {
8227         int ret = 0;
8228         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8229
8230         if (udp_tunnel == NULL)
8231                 return -EINVAL;
8232
8233         switch (udp_tunnel->prot_type) {
8234         case RTE_TUNNEL_TYPE_VXLAN:
8235                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8236                 break;
8237         case RTE_TUNNEL_TYPE_GENEVE:
8238         case RTE_TUNNEL_TYPE_TEREDO:
8239                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8240                 ret = -1;
8241                 break;
8242         default:
8243                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8244                 ret = -1;
8245                 break;
8246         }
8247
8248         return ret;
8249 }
8250
8251 /* Calculate the maximum number of contiguous PF queues that are configured */
8252 static int
8253 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8254 {
8255         struct rte_eth_dev_data *data = pf->dev_data;
8256         int i, num;
8257         struct i40e_rx_queue *rxq;
8258
8259         num = 0;
8260         for (i = 0; i < pf->lan_nb_qps; i++) {
8261                 rxq = data->rx_queues[i];
8262                 if (rxq && rxq->q_set)
8263                         num++;
8264                 else
8265                         break;
8266         }
8267
8268         return num;
8269 }
8270
8271 /* Configure RSS */
8272 static int
8273 i40e_pf_config_rss(struct i40e_pf *pf)
8274 {
8275         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8276         struct rte_eth_rss_conf rss_conf;
8277         uint32_t i, lut = 0;
8278         uint16_t j, num;
8279
8280         /*
8281          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8282          * It's necessary to calculate the actual PF queues that are configured.
8283          */
8284         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8285                 num = i40e_pf_calc_configured_queues_num(pf);
8286         else
8287                 num = pf->dev_data->nb_rx_queues;
8288
8289         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8290         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8291                         num);
8292
8293         if (num == 0) {
8294                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8295                 return -ENOTSUP;
8296         }
8297
8298         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8299                 if (j == num)
8300                         j = 0;
8301                 lut = (lut << 8) | (j & ((0x1 <<
8302                         hw->func_caps.rss_table_entry_width) - 1));
8303                 if ((i & 3) == 3)
8304                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8305         }
8306
8307         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8308         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8309                 i40e_pf_disable_rss(pf);
8310                 return 0;
8311         }
8312         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8313                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8314                 /* Random default keys */
8315                 static uint32_t rss_key_default[] = {0x6b793944,
8316                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8317                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8318                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8319
8320                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8321                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8322                                                         sizeof(uint32_t);
8323         }
8324
8325         return i40e_hw_rss_hash_set(pf, &rss_conf);
8326 }
8327
8328 static int
8329 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8330                                struct rte_eth_tunnel_filter_conf *filter)
8331 {
8332         if (pf == NULL || filter == NULL) {
8333                 PMD_DRV_LOG(ERR, "Invalid parameter");
8334                 return -EINVAL;
8335         }
8336
8337         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8338                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8339                 return -EINVAL;
8340         }
8341
8342         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8343                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8344                 return -EINVAL;
8345         }
8346
8347         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8348                 (is_zero_ether_addr(&filter->outer_mac))) {
8349                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8350                 return -EINVAL;
8351         }
8352
8353         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8354                 (is_zero_ether_addr(&filter->inner_mac))) {
8355                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8356                 return -EINVAL;
8357         }
8358
8359         return 0;
8360 }
8361
8362 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8363 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8364 static int
8365 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8366 {
8367         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8368         uint32_t val, reg;
8369         int ret = -EINVAL;
8370
8371         if (pf->support_multi_driver) {
8372                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8373                 return -ENOTSUP;
8374         }
8375
8376         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8377         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8378
8379         if (len == 3) {
8380                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8381         } else if (len == 4) {
8382                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8383         } else {
8384                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8385                 return ret;
8386         }
8387
8388         if (reg != val) {
8389                 ret = i40e_aq_debug_write_global_register(hw,
8390                                                    I40E_GL_PRS_FVBM(2),
8391                                                    reg, NULL);
8392                 if (ret != 0)
8393                         return ret;
8394                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8395                             "with value 0x%08x",
8396                             I40E_GL_PRS_FVBM(2), reg);
8397                 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8398         } else {
8399                 ret = 0;
8400         }
8401         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8402                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8403
8404         return ret;
8405 }
8406
8407 static int
8408 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8409 {
8410         int ret = -EINVAL;
8411
8412         if (!hw || !cfg)
8413                 return -EINVAL;
8414
8415         switch (cfg->cfg_type) {
8416         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8417                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8418                 break;
8419         default:
8420                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8421                 break;
8422         }
8423
8424         return ret;
8425 }
8426
8427 static int
8428 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8429                                enum rte_filter_op filter_op,
8430                                void *arg)
8431 {
8432         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8433         int ret = I40E_ERR_PARAM;
8434
8435         switch (filter_op) {
8436         case RTE_ETH_FILTER_SET:
8437                 ret = i40e_dev_global_config_set(hw,
8438                         (struct rte_eth_global_cfg *)arg);
8439                 break;
8440         default:
8441                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8442                 break;
8443         }
8444
8445         return ret;
8446 }
8447
8448 static int
8449 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8450                           enum rte_filter_op filter_op,
8451                           void *arg)
8452 {
8453         struct rte_eth_tunnel_filter_conf *filter;
8454         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8455         int ret = I40E_SUCCESS;
8456
8457         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8458
8459         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8460                 return I40E_ERR_PARAM;
8461
8462         switch (filter_op) {
8463         case RTE_ETH_FILTER_NOP:
8464                 if (!(pf->flags & I40E_FLAG_VXLAN))
8465                         ret = I40E_NOT_SUPPORTED;
8466                 break;
8467         case RTE_ETH_FILTER_ADD:
8468                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8469                 break;
8470         case RTE_ETH_FILTER_DELETE:
8471                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8472                 break;
8473         default:
8474                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8475                 ret = I40E_ERR_PARAM;
8476                 break;
8477         }
8478
8479         return ret;
8480 }
8481
8482 static int
8483 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8484 {
8485         int ret = 0;
8486         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8487
8488         /* RSS setup */
8489         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8490                 ret = i40e_pf_config_rss(pf);
8491         else
8492                 i40e_pf_disable_rss(pf);
8493
8494         return ret;
8495 }
8496
8497 /* Get the symmetric hash enable configurations per port */
8498 static void
8499 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8500 {
8501         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8502
8503         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8504 }
8505
8506 /* Set the symmetric hash enable configurations per port */
8507 static void
8508 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8509 {
8510         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8511
8512         if (enable > 0) {
8513                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8514                         PMD_DRV_LOG(INFO,
8515                                 "Symmetric hash has already been enabled");
8516                         return;
8517                 }
8518                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8519         } else {
8520                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8521                         PMD_DRV_LOG(INFO,
8522                                 "Symmetric hash has already been disabled");
8523                         return;
8524                 }
8525                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8526         }
8527         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8528         I40E_WRITE_FLUSH(hw);
8529 }
8530
8531 /*
8532  * Get global configurations of hash function type and symmetric hash enable
8533  * per flow type (pctype). Note that global configuration means it affects all
8534  * the ports on the same NIC.
8535  */
8536 static int
8537 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8538                                    struct rte_eth_hash_global_conf *g_cfg)
8539 {
8540         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8541         uint32_t reg;
8542         uint16_t i, j;
8543
8544         memset(g_cfg, 0, sizeof(*g_cfg));
8545         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8546         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8547                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8548         else
8549                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8550         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8551                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8552
8553         /*
8554          * As i40e supports less than 64 flow types, only first 64 bits need to
8555          * be checked.
8556          */
8557         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8558                 g_cfg->valid_bit_mask[i] = 0ULL;
8559                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8560         }
8561
8562         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8563
8564         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8565                 if (!adapter->pctypes_tbl[i])
8566                         continue;
8567                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8568                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8569                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8570                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8571                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8572                                         g_cfg->sym_hash_enable_mask[0] |=
8573                                                                 (1ULL << i);
8574                                 }
8575                         }
8576                 }
8577         }
8578
8579         return 0;
8580 }
8581
8582 static int
8583 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8584                               const struct rte_eth_hash_global_conf *g_cfg)
8585 {
8586         uint32_t i;
8587         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8588
8589         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8590                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8591                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8592                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8593                                                 g_cfg->hash_func);
8594                 return -EINVAL;
8595         }
8596
8597         /*
8598          * As i40e supports less than 64 flow types, only first 64 bits need to
8599          * be checked.
8600          */
8601         mask0 = g_cfg->valid_bit_mask[0];
8602         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8603                 if (i == 0) {
8604                         /* Check if any unsupported flow type configured */
8605                         if ((mask0 | i40e_mask) ^ i40e_mask)
8606                                 goto mask_err;
8607                 } else {
8608                         if (g_cfg->valid_bit_mask[i])
8609                                 goto mask_err;
8610                 }
8611         }
8612
8613         return 0;
8614
8615 mask_err:
8616         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8617
8618         return -EINVAL;
8619 }
8620
8621 /*
8622  * Set global configurations of hash function type and symmetric hash enable
8623  * per flow type (pctype). Note any modifying global configuration will affect
8624  * all the ports on the same NIC.
8625  */
8626 static int
8627 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8628                                    struct rte_eth_hash_global_conf *g_cfg)
8629 {
8630         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8631         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8632         int ret;
8633         uint16_t i, j;
8634         uint32_t reg;
8635         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8636
8637         if (pf->support_multi_driver) {
8638                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8639                 return -ENOTSUP;
8640         }
8641
8642         /* Check the input parameters */
8643         ret = i40e_hash_global_config_check(adapter, g_cfg);
8644         if (ret < 0)
8645                 return ret;
8646
8647         /*
8648          * As i40e supports less than 64 flow types, only first 64 bits need to
8649          * be configured.
8650          */
8651         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8652                 if (mask0 & (1UL << i)) {
8653                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8654                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8655
8656                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8657                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8658                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8659                                         i40e_write_global_rx_ctl(hw,
8660                                                           I40E_GLQF_HSYM(j),
8661                                                           reg);
8662                         }
8663                         i40e_global_cfg_warning(I40E_WARNING_HSYM);
8664                 }
8665         }
8666
8667         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8668         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8669                 /* Toeplitz */
8670                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8671                         PMD_DRV_LOG(DEBUG,
8672                                 "Hash function already set to Toeplitz");
8673                         goto out;
8674                 }
8675                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8676         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8677                 /* Simple XOR */
8678                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8679                         PMD_DRV_LOG(DEBUG,
8680                                 "Hash function already set to Simple XOR");
8681                         goto out;
8682                 }
8683                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8684         } else
8685                 /* Use the default, and keep it as it is */
8686                 goto out;
8687
8688         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8689         i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8690
8691 out:
8692         I40E_WRITE_FLUSH(hw);
8693
8694         return 0;
8695 }
8696
8697 /**
8698  * Valid input sets for hash and flow director filters per PCTYPE
8699  */
8700 static uint64_t
8701 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8702                 enum rte_filter_type filter)
8703 {
8704         uint64_t valid;
8705
8706         static const uint64_t valid_hash_inset_table[] = {
8707                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8708                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8709                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8710                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8711                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8712                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8713                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8714                         I40E_INSET_FLEX_PAYLOAD,
8715                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8716                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8717                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8718                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8719                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8720                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8721                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8722                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8723                         I40E_INSET_FLEX_PAYLOAD,
8724                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8725                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8726                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8727                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8728                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8729                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8730                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8731                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8732                         I40E_INSET_FLEX_PAYLOAD,
8733                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8734                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8735                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8736                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8737                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8738                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8739                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8740                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8741                         I40E_INSET_FLEX_PAYLOAD,
8742                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8743                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8744                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8745                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8746                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8747                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8748                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8749                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8750                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8751                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8752                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8753                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8754                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8755                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8756                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8757                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8758                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8759                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8760                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8761                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8762                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8763                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8764                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8765                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8766                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8767                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8768                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8769                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8770                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8771                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8772                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8773                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8774                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8775                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8776                         I40E_INSET_FLEX_PAYLOAD,
8777                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8778                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8779                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8780                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8781                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8782                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8783                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8784                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8785                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8786                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8787                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8788                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8789                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8790                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8791                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8792                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8793                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8794                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8795                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8796                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8797                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8798                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8799                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8800                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8801                         I40E_INSET_FLEX_PAYLOAD,
8802                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8803                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8804                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8805                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8806                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8807                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8808                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8809                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8810                         I40E_INSET_FLEX_PAYLOAD,
8811                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8812                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8813                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8814                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8815                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8816                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8817                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8818                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8819                         I40E_INSET_FLEX_PAYLOAD,
8820                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8821                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8822                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8823                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8824                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8825                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8826                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8827                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8828                         I40E_INSET_FLEX_PAYLOAD,
8829                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8830                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8831                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8832                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8833                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8834                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8835                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8836                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8837                         I40E_INSET_FLEX_PAYLOAD,
8838                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8839                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8840                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8841                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8842                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8843                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8844                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8845                         I40E_INSET_FLEX_PAYLOAD,
8846                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8847                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8848                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8849                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8850                         I40E_INSET_FLEX_PAYLOAD,
8851         };
8852
8853         /**
8854          * Flow director supports only fields defined in
8855          * union rte_eth_fdir_flow.
8856          */
8857         static const uint64_t valid_fdir_inset_table[] = {
8858                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8859                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8860                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8861                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8862                 I40E_INSET_IPV4_TTL,
8863                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8864                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8865                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8866                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8867                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8868                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8869                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8870                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8871                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8872                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8873                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8874                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8875                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8876                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8877                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8878                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8879                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8880                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8881                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8882                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8883                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8884                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8885                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8886                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8887                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8888                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8889                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8890                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8891                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8892                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8893                 I40E_INSET_SCTP_VT,
8894                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8895                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8896                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8897                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8898                 I40E_INSET_IPV4_TTL,
8899                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8900                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8901                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8902                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8903                 I40E_INSET_IPV6_HOP_LIMIT,
8904                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8905                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8906                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8907                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8908                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8909                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8910                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8911                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8912                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8913                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8914                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8915                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8916                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8917                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8918                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8919                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8920                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8921                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8922                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8923                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8924                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8925                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8926                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8927                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8928                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8929                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8930                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8931                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8932                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8933                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8934                 I40E_INSET_SCTP_VT,
8935                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8936                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8937                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8938                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8939                 I40E_INSET_IPV6_HOP_LIMIT,
8940                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8941                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8942                 I40E_INSET_LAST_ETHER_TYPE,
8943         };
8944
8945         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8946                 return 0;
8947         if (filter == RTE_ETH_FILTER_HASH)
8948                 valid = valid_hash_inset_table[pctype];
8949         else
8950                 valid = valid_fdir_inset_table[pctype];
8951
8952         return valid;
8953 }
8954
8955 /**
8956  * Validate if the input set is allowed for a specific PCTYPE
8957  */
8958 int
8959 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8960                 enum rte_filter_type filter, uint64_t inset)
8961 {
8962         uint64_t valid;
8963
8964         valid = i40e_get_valid_input_set(pctype, filter);
8965         if (inset & (~valid))
8966                 return -EINVAL;
8967
8968         return 0;
8969 }
8970
8971 /* default input set fields combination per pctype */
8972 uint64_t
8973 i40e_get_default_input_set(uint16_t pctype)
8974 {
8975         static const uint64_t default_inset_table[] = {
8976                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8977                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8978                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8979                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8980                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8981                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8982                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8983                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8984                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8985                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8986                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8987                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8988                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8989                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8990                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8991                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8992                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8993                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8994                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8995                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8996                         I40E_INSET_SCTP_VT,
8997                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8998                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8999                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9000                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9001                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9002                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9003                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9004                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9005                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9006                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9007                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9008                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9009                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9010                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9011                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9012                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9013                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9014                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9015                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9016                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9017                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9018                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9019                         I40E_INSET_SCTP_VT,
9020                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9021                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9022                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9023                         I40E_INSET_LAST_ETHER_TYPE,
9024         };
9025
9026         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9027                 return 0;
9028
9029         return default_inset_table[pctype];
9030 }
9031
9032 /**
9033  * Parse the input set from index to logical bit masks
9034  */
9035 static int
9036 i40e_parse_input_set(uint64_t *inset,
9037                      enum i40e_filter_pctype pctype,
9038                      enum rte_eth_input_set_field *field,
9039                      uint16_t size)
9040 {
9041         uint16_t i, j;
9042         int ret = -EINVAL;
9043
9044         static const struct {
9045                 enum rte_eth_input_set_field field;
9046                 uint64_t inset;
9047         } inset_convert_table[] = {
9048                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9049                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9050                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9051                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9052                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9053                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9054                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9055                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9056                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9057                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9058                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9059                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9060                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9061                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9062                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9063                         I40E_INSET_IPV6_NEXT_HDR},
9064                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9065                         I40E_INSET_IPV6_HOP_LIMIT},
9066                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9067                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9068                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9069                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9070                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9071                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9072                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9073                         I40E_INSET_SCTP_VT},
9074                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9075                         I40E_INSET_TUNNEL_DMAC},
9076                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9077                         I40E_INSET_VLAN_TUNNEL},
9078                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9079                         I40E_INSET_TUNNEL_ID},
9080                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9081                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9082                         I40E_INSET_FLEX_PAYLOAD_W1},
9083                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9084                         I40E_INSET_FLEX_PAYLOAD_W2},
9085                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9086                         I40E_INSET_FLEX_PAYLOAD_W3},
9087                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9088                         I40E_INSET_FLEX_PAYLOAD_W4},
9089                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9090                         I40E_INSET_FLEX_PAYLOAD_W5},
9091                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9092                         I40E_INSET_FLEX_PAYLOAD_W6},
9093                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9094                         I40E_INSET_FLEX_PAYLOAD_W7},
9095                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9096                         I40E_INSET_FLEX_PAYLOAD_W8},
9097         };
9098
9099         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9100                 return ret;
9101
9102         /* Only one item allowed for default or all */
9103         if (size == 1) {
9104                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9105                         *inset = i40e_get_default_input_set(pctype);
9106                         return 0;
9107                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9108                         *inset = I40E_INSET_NONE;
9109                         return 0;
9110                 }
9111         }
9112
9113         for (i = 0, *inset = 0; i < size; i++) {
9114                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9115                         if (field[i] == inset_convert_table[j].field) {
9116                                 *inset |= inset_convert_table[j].inset;
9117                                 break;
9118                         }
9119                 }
9120
9121                 /* It contains unsupported input set, return immediately */
9122                 if (j == RTE_DIM(inset_convert_table))
9123                         return ret;
9124         }
9125
9126         return 0;
9127 }
9128
9129 /**
9130  * Translate the input set from bit masks to register aware bit masks
9131  * and vice versa
9132  */
9133 uint64_t
9134 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9135 {
9136         uint64_t val = 0;
9137         uint16_t i;
9138
9139         struct inset_map {
9140                 uint64_t inset;
9141                 uint64_t inset_reg;
9142         };
9143
9144         static const struct inset_map inset_map_common[] = {
9145                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9146                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9147                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9148                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9149                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9150                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9151                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9152                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9153                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9154                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9155                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9156                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9157                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9158                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9159                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9160                 {I40E_INSET_TUNNEL_DMAC,
9161                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9162                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9163                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9164                 {I40E_INSET_TUNNEL_SRC_PORT,
9165                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9166                 {I40E_INSET_TUNNEL_DST_PORT,
9167                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9168                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9169                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9170                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9171                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9172                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9173                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9174                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9175                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9176                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9177         };
9178
9179     /* some different registers map in x722*/
9180         static const struct inset_map inset_map_diff_x722[] = {
9181                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9182                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9183                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9184                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9185         };
9186
9187         static const struct inset_map inset_map_diff_not_x722[] = {
9188                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9189                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9190                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9191                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9192         };
9193
9194         if (input == 0)
9195                 return val;
9196
9197         /* Translate input set to register aware inset */
9198         if (type == I40E_MAC_X722) {
9199                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9200                         if (input & inset_map_diff_x722[i].inset)
9201                                 val |= inset_map_diff_x722[i].inset_reg;
9202                 }
9203         } else {
9204                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9205                         if (input & inset_map_diff_not_x722[i].inset)
9206                                 val |= inset_map_diff_not_x722[i].inset_reg;
9207                 }
9208         }
9209
9210         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9211                 if (input & inset_map_common[i].inset)
9212                         val |= inset_map_common[i].inset_reg;
9213         }
9214
9215         return val;
9216 }
9217
9218 int
9219 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9220 {
9221         uint8_t i, idx = 0;
9222         uint64_t inset_need_mask = inset;
9223
9224         static const struct {
9225                 uint64_t inset;
9226                 uint32_t mask;
9227         } inset_mask_map[] = {
9228                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9229                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9230                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9231                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9232                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9233                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9234                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9235                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9236         };
9237
9238         if (!inset || !mask || !nb_elem)
9239                 return 0;
9240
9241         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9242                 /* Clear the inset bit, if no MASK is required,
9243                  * for example proto + ttl
9244                  */
9245                 if ((inset & inset_mask_map[i].inset) ==
9246                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9247                         inset_need_mask &= ~inset_mask_map[i].inset;
9248                 if (!inset_need_mask)
9249                         return 0;
9250         }
9251         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9252                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9253                     inset_mask_map[i].inset) {
9254                         if (idx >= nb_elem) {
9255                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9256                                 return -EINVAL;
9257                         }
9258                         mask[idx] = inset_mask_map[i].mask;
9259                         idx++;
9260                 }
9261         }
9262
9263         return idx;
9264 }
9265
9266 void
9267 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9268 {
9269         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9270
9271         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9272         if (reg != val)
9273                 i40e_write_rx_ctl(hw, addr, val);
9274         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9275                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9276 }
9277
9278 void
9279 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9280 {
9281         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9282
9283         if (reg != val)
9284                 i40e_write_rx_ctl(hw, addr, val);
9285         PMD_DRV_LOG(DEBUG,
9286                     "Global register [0x%08x] original: 0x%08x, after: 0x%08x",
9287                     addr, reg, (uint32_t)i40e_read_rx_ctl(hw, addr));
9288 }
9289
9290 static void
9291 i40e_filter_input_set_init(struct i40e_pf *pf)
9292 {
9293         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9294         enum i40e_filter_pctype pctype;
9295         uint64_t input_set, inset_reg;
9296         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9297         int num, i;
9298         uint16_t flow_type;
9299
9300         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9301              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9302                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9303
9304                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9305                         continue;
9306
9307                 input_set = i40e_get_default_input_set(pctype);
9308
9309                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9310                                                    I40E_INSET_MASK_NUM_REG);
9311                 if (num < 0)
9312                         return;
9313                 if (pf->support_multi_driver && num > 0) {
9314                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9315                         return;
9316                 }
9317                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9318                                         input_set);
9319
9320                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9321                                       (uint32_t)(inset_reg & UINT32_MAX));
9322                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9323                                      (uint32_t)((inset_reg >>
9324                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9325                 if (!pf->support_multi_driver) {
9326                         i40e_check_write_global_reg(hw,
9327                                             I40E_GLQF_HASH_INSET(0, pctype),
9328                                             (uint32_t)(inset_reg & UINT32_MAX));
9329                         i40e_check_write_global_reg(hw,
9330                                              I40E_GLQF_HASH_INSET(1, pctype),
9331                                              (uint32_t)((inset_reg >>
9332                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9333
9334                         for (i = 0; i < num; i++) {
9335                                 i40e_check_write_global_reg(hw,
9336                                                     I40E_GLQF_FD_MSK(i, pctype),
9337                                                     mask_reg[i]);
9338                                 i40e_check_write_global_reg(hw,
9339                                                   I40E_GLQF_HASH_MSK(i, pctype),
9340                                                   mask_reg[i]);
9341                         }
9342                         /*clear unused mask registers of the pctype */
9343                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9344                                 i40e_check_write_global_reg(hw,
9345                                                     I40E_GLQF_FD_MSK(i, pctype),
9346                                                     0);
9347                                 i40e_check_write_global_reg(hw,
9348                                                   I40E_GLQF_HASH_MSK(i, pctype),
9349                                                   0);
9350                         }
9351                 } else {
9352                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9353                 }
9354                 I40E_WRITE_FLUSH(hw);
9355
9356                 /* store the default input set */
9357                 if (!pf->support_multi_driver)
9358                         pf->hash_input_set[pctype] = input_set;
9359                 pf->fdir.input_set[pctype] = input_set;
9360         }
9361
9362         if (!pf->support_multi_driver) {
9363                 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9364                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9365                 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9366         }
9367 }
9368
9369 int
9370 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9371                          struct rte_eth_input_set_conf *conf)
9372 {
9373         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9374         enum i40e_filter_pctype pctype;
9375         uint64_t input_set, inset_reg = 0;
9376         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9377         int ret, i, num;
9378
9379         if (!conf) {
9380                 PMD_DRV_LOG(ERR, "Invalid pointer");
9381                 return -EFAULT;
9382         }
9383         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9384             conf->op != RTE_ETH_INPUT_SET_ADD) {
9385                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9386                 return -EINVAL;
9387         }
9388
9389         if (pf->support_multi_driver) {
9390                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9391                 return -ENOTSUP;
9392         }
9393
9394         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9395         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9396                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9397                 return -EINVAL;
9398         }
9399
9400         if (hw->mac.type == I40E_MAC_X722) {
9401                 /* get translated pctype value in fd pctype register */
9402                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9403                         I40E_GLQF_FD_PCTYPES((int)pctype));
9404         }
9405
9406         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9407                                    conf->inset_size);
9408         if (ret) {
9409                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9410                 return -EINVAL;
9411         }
9412
9413         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9414                 /* get inset value in register */
9415                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9416                 inset_reg <<= I40E_32_BIT_WIDTH;
9417                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9418                 input_set |= pf->hash_input_set[pctype];
9419         }
9420         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9421                                            I40E_INSET_MASK_NUM_REG);
9422         if (num < 0)
9423                 return -EINVAL;
9424
9425         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9426
9427         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9428                                     (uint32_t)(inset_reg & UINT32_MAX));
9429         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9430                                     (uint32_t)((inset_reg >>
9431                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9432         i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9433
9434         for (i = 0; i < num; i++)
9435                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9436                                             mask_reg[i]);
9437         /*clear unused mask registers of the pctype */
9438         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9439                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9440                                             0);
9441         i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9442         I40E_WRITE_FLUSH(hw);
9443
9444         pf->hash_input_set[pctype] = input_set;
9445         return 0;
9446 }
9447
9448 int
9449 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9450                          struct rte_eth_input_set_conf *conf)
9451 {
9452         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9453         enum i40e_filter_pctype pctype;
9454         uint64_t input_set, inset_reg = 0;
9455         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9456         int ret, i, num;
9457
9458         if (!hw || !conf) {
9459                 PMD_DRV_LOG(ERR, "Invalid pointer");
9460                 return -EFAULT;
9461         }
9462         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9463             conf->op != RTE_ETH_INPUT_SET_ADD) {
9464                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9465                 return -EINVAL;
9466         }
9467
9468         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9469
9470         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9471                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9472                 return -EINVAL;
9473         }
9474
9475         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9476                                    conf->inset_size);
9477         if (ret) {
9478                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9479                 return -EINVAL;
9480         }
9481
9482         /* get inset value in register */
9483         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9484         inset_reg <<= I40E_32_BIT_WIDTH;
9485         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9486
9487         /* Can not change the inset reg for flex payload for fdir,
9488          * it is done by writing I40E_PRTQF_FD_FLXINSET
9489          * in i40e_set_flex_mask_on_pctype.
9490          */
9491         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9492                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9493         else
9494                 input_set |= pf->fdir.input_set[pctype];
9495         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9496                                            I40E_INSET_MASK_NUM_REG);
9497         if (num < 0)
9498                 return -EINVAL;
9499         if (pf->support_multi_driver && num > 0) {
9500                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9501                 return -ENOTSUP;
9502         }
9503
9504         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9505
9506         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9507                               (uint32_t)(inset_reg & UINT32_MAX));
9508         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9509                              (uint32_t)((inset_reg >>
9510                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9511
9512         if (!pf->support_multi_driver) {
9513                 for (i = 0; i < num; i++)
9514                         i40e_check_write_global_reg(hw,
9515                                                     I40E_GLQF_FD_MSK(i, pctype),
9516                                                     mask_reg[i]);
9517                 /*clear unused mask registers of the pctype */
9518                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9519                         i40e_check_write_global_reg(hw,
9520                                                     I40E_GLQF_FD_MSK(i, pctype),
9521                                                     0);
9522                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9523         } else {
9524                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9525         }
9526         I40E_WRITE_FLUSH(hw);
9527
9528         pf->fdir.input_set[pctype] = input_set;
9529         return 0;
9530 }
9531
9532 static int
9533 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9534 {
9535         int ret = 0;
9536
9537         if (!hw || !info) {
9538                 PMD_DRV_LOG(ERR, "Invalid pointer");
9539                 return -EFAULT;
9540         }
9541
9542         switch (info->info_type) {
9543         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9544                 i40e_get_symmetric_hash_enable_per_port(hw,
9545                                         &(info->info.enable));
9546                 break;
9547         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9548                 ret = i40e_get_hash_filter_global_config(hw,
9549                                 &(info->info.global_conf));
9550                 break;
9551         default:
9552                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9553                                                         info->info_type);
9554                 ret = -EINVAL;
9555                 break;
9556         }
9557
9558         return ret;
9559 }
9560
9561 static int
9562 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9563 {
9564         int ret = 0;
9565
9566         if (!hw || !info) {
9567                 PMD_DRV_LOG(ERR, "Invalid pointer");
9568                 return -EFAULT;
9569         }
9570
9571         switch (info->info_type) {
9572         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9573                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9574                 break;
9575         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9576                 ret = i40e_set_hash_filter_global_config(hw,
9577                                 &(info->info.global_conf));
9578                 break;
9579         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9580                 ret = i40e_hash_filter_inset_select(hw,
9581                                                &(info->info.input_set_conf));
9582                 break;
9583
9584         default:
9585                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9586                                                         info->info_type);
9587                 ret = -EINVAL;
9588                 break;
9589         }
9590
9591         return ret;
9592 }
9593
9594 /* Operations for hash function */
9595 static int
9596 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9597                       enum rte_filter_op filter_op,
9598                       void *arg)
9599 {
9600         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9601         int ret = 0;
9602
9603         switch (filter_op) {
9604         case RTE_ETH_FILTER_NOP:
9605                 break;
9606         case RTE_ETH_FILTER_GET:
9607                 ret = i40e_hash_filter_get(hw,
9608                         (struct rte_eth_hash_filter_info *)arg);
9609                 break;
9610         case RTE_ETH_FILTER_SET:
9611                 ret = i40e_hash_filter_set(hw,
9612                         (struct rte_eth_hash_filter_info *)arg);
9613                 break;
9614         default:
9615                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9616                                                                 filter_op);
9617                 ret = -ENOTSUP;
9618                 break;
9619         }
9620
9621         return ret;
9622 }
9623
9624 /* Convert ethertype filter structure */
9625 static int
9626 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9627                               struct i40e_ethertype_filter *filter)
9628 {
9629         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9630         filter->input.ether_type = input->ether_type;
9631         filter->flags = input->flags;
9632         filter->queue = input->queue;
9633
9634         return 0;
9635 }
9636
9637 /* Check if there exists the ehtertype filter */
9638 struct i40e_ethertype_filter *
9639 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9640                                 const struct i40e_ethertype_filter_input *input)
9641 {
9642         int ret;
9643
9644         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9645         if (ret < 0)
9646                 return NULL;
9647
9648         return ethertype_rule->hash_map[ret];
9649 }
9650
9651 /* Add ethertype filter in SW list */
9652 static int
9653 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9654                                 struct i40e_ethertype_filter *filter)
9655 {
9656         struct i40e_ethertype_rule *rule = &pf->ethertype;
9657         int ret;
9658
9659         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9660         if (ret < 0) {
9661                 PMD_DRV_LOG(ERR,
9662                             "Failed to insert ethertype filter"
9663                             " to hash table %d!",
9664                             ret);
9665                 return ret;
9666         }
9667         rule->hash_map[ret] = filter;
9668
9669         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9670
9671         return 0;
9672 }
9673
9674 /* Delete ethertype filter in SW list */
9675 int
9676 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9677                              struct i40e_ethertype_filter_input *input)
9678 {
9679         struct i40e_ethertype_rule *rule = &pf->ethertype;
9680         struct i40e_ethertype_filter *filter;
9681         int ret;
9682
9683         ret = rte_hash_del_key(rule->hash_table, input);
9684         if (ret < 0) {
9685                 PMD_DRV_LOG(ERR,
9686                             "Failed to delete ethertype filter"
9687                             " to hash table %d!",
9688                             ret);
9689                 return ret;
9690         }
9691         filter = rule->hash_map[ret];
9692         rule->hash_map[ret] = NULL;
9693
9694         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9695         rte_free(filter);
9696
9697         return 0;
9698 }
9699
9700 /*
9701  * Configure ethertype filter, which can director packet by filtering
9702  * with mac address and ether_type or only ether_type
9703  */
9704 int
9705 i40e_ethertype_filter_set(struct i40e_pf *pf,
9706                         struct rte_eth_ethertype_filter *filter,
9707                         bool add)
9708 {
9709         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9710         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9711         struct i40e_ethertype_filter *ethertype_filter, *node;
9712         struct i40e_ethertype_filter check_filter;
9713         struct i40e_control_filter_stats stats;
9714         uint16_t flags = 0;
9715         int ret;
9716
9717         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9718                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9719                 return -EINVAL;
9720         }
9721         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9722                 filter->ether_type == ETHER_TYPE_IPv6) {
9723                 PMD_DRV_LOG(ERR,
9724                         "unsupported ether_type(0x%04x) in control packet filter.",
9725                         filter->ether_type);
9726                 return -EINVAL;
9727         }
9728         if (filter->ether_type == ETHER_TYPE_VLAN)
9729                 PMD_DRV_LOG(WARNING,
9730                         "filter vlan ether_type in first tag is not supported.");
9731
9732         /* Check if there is the filter in SW list */
9733         memset(&check_filter, 0, sizeof(check_filter));
9734         i40e_ethertype_filter_convert(filter, &check_filter);
9735         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9736                                                &check_filter.input);
9737         if (add && node) {
9738                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9739                 return -EINVAL;
9740         }
9741
9742         if (!add && !node) {
9743                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9744                 return -EINVAL;
9745         }
9746
9747         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9748                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9749         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9750                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9751         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9752
9753         memset(&stats, 0, sizeof(stats));
9754         ret = i40e_aq_add_rem_control_packet_filter(hw,
9755                         filter->mac_addr.addr_bytes,
9756                         filter->ether_type, flags,
9757                         pf->main_vsi->seid,
9758                         filter->queue, add, &stats, NULL);
9759
9760         PMD_DRV_LOG(INFO,
9761                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9762                 ret, stats.mac_etype_used, stats.etype_used,
9763                 stats.mac_etype_free, stats.etype_free);
9764         if (ret < 0)
9765                 return -ENOSYS;
9766
9767         /* Add or delete a filter in SW list */
9768         if (add) {
9769                 ethertype_filter = rte_zmalloc("ethertype_filter",
9770                                        sizeof(*ethertype_filter), 0);
9771                 if (ethertype_filter == NULL) {
9772                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9773                         return -ENOMEM;
9774                 }
9775
9776                 rte_memcpy(ethertype_filter, &check_filter,
9777                            sizeof(check_filter));
9778                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9779                 if (ret < 0)
9780                         rte_free(ethertype_filter);
9781         } else {
9782                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9783         }
9784
9785         return ret;
9786 }
9787
9788 /*
9789  * Handle operations for ethertype filter.
9790  */
9791 static int
9792 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9793                                 enum rte_filter_op filter_op,
9794                                 void *arg)
9795 {
9796         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9797         int ret = 0;
9798
9799         if (filter_op == RTE_ETH_FILTER_NOP)
9800                 return ret;
9801
9802         if (arg == NULL) {
9803                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9804                             filter_op);
9805                 return -EINVAL;
9806         }
9807
9808         switch (filter_op) {
9809         case RTE_ETH_FILTER_ADD:
9810                 ret = i40e_ethertype_filter_set(pf,
9811                         (struct rte_eth_ethertype_filter *)arg,
9812                         TRUE);
9813                 break;
9814         case RTE_ETH_FILTER_DELETE:
9815                 ret = i40e_ethertype_filter_set(pf,
9816                         (struct rte_eth_ethertype_filter *)arg,
9817                         FALSE);
9818                 break;
9819         default:
9820                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9821                 ret = -ENOSYS;
9822                 break;
9823         }
9824         return ret;
9825 }
9826
9827 static int
9828 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9829                      enum rte_filter_type filter_type,
9830                      enum rte_filter_op filter_op,
9831                      void *arg)
9832 {
9833         int ret = 0;
9834
9835         if (dev == NULL)
9836                 return -EINVAL;
9837
9838         switch (filter_type) {
9839         case RTE_ETH_FILTER_NONE:
9840                 /* For global configuration */
9841                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9842                 break;
9843         case RTE_ETH_FILTER_HASH:
9844                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9845                 break;
9846         case RTE_ETH_FILTER_MACVLAN:
9847                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9848                 break;
9849         case RTE_ETH_FILTER_ETHERTYPE:
9850                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9851                 break;
9852         case RTE_ETH_FILTER_TUNNEL:
9853                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9854                 break;
9855         case RTE_ETH_FILTER_FDIR:
9856                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9857                 break;
9858         case RTE_ETH_FILTER_GENERIC:
9859                 if (filter_op != RTE_ETH_FILTER_GET)
9860                         return -EINVAL;
9861                 *(const void **)arg = &i40e_flow_ops;
9862                 break;
9863         default:
9864                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9865                                                         filter_type);
9866                 ret = -EINVAL;
9867                 break;
9868         }
9869
9870         return ret;
9871 }
9872
9873 /*
9874  * Check and enable Extended Tag.
9875  * Enabling Extended Tag is important for 40G performance.
9876  */
9877 static void
9878 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9879 {
9880         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9881         uint32_t buf = 0;
9882         int ret;
9883
9884         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9885                                       PCI_DEV_CAP_REG);
9886         if (ret < 0) {
9887                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9888                             PCI_DEV_CAP_REG);
9889                 return;
9890         }
9891         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9892                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9893                 return;
9894         }
9895
9896         buf = 0;
9897         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9898                                       PCI_DEV_CTRL_REG);
9899         if (ret < 0) {
9900                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9901                             PCI_DEV_CTRL_REG);
9902                 return;
9903         }
9904         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9905                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9906                 return;
9907         }
9908         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9909         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9910                                        PCI_DEV_CTRL_REG);
9911         if (ret < 0) {
9912                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9913                             PCI_DEV_CTRL_REG);
9914                 return;
9915         }
9916 }
9917
9918 /*
9919  * As some registers wouldn't be reset unless a global hardware reset,
9920  * hardware initialization is needed to put those registers into an
9921  * expected initial state.
9922  */
9923 static void
9924 i40e_hw_init(struct rte_eth_dev *dev)
9925 {
9926         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9927
9928         i40e_enable_extended_tag(dev);
9929
9930         /* clear the PF Queue Filter control register */
9931         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9932
9933         /* Disable symmetric hash per port */
9934         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9935 }
9936
9937 /*
9938  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9939  * however this function will return only one highest pctype index,
9940  * which is not quite correct. This is known problem of i40e driver
9941  * and needs to be fixed later.
9942  */
9943 enum i40e_filter_pctype
9944 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9945 {
9946         int i;
9947         uint64_t pctype_mask;
9948
9949         if (flow_type < I40E_FLOW_TYPE_MAX) {
9950                 pctype_mask = adapter->pctypes_tbl[flow_type];
9951                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9952                         if (pctype_mask & (1ULL << i))
9953                                 return (enum i40e_filter_pctype)i;
9954                 }
9955         }
9956         return I40E_FILTER_PCTYPE_INVALID;
9957 }
9958
9959 uint16_t
9960 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9961                         enum i40e_filter_pctype pctype)
9962 {
9963         uint16_t flowtype;
9964         uint64_t pctype_mask = 1ULL << pctype;
9965
9966         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9967              flowtype++) {
9968                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9969                         return flowtype;
9970         }
9971
9972         return RTE_ETH_FLOW_UNKNOWN;
9973 }
9974
9975 /*
9976  * On X710, performance number is far from the expectation on recent firmware
9977  * versions; on XL710, performance number is also far from the expectation on
9978  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9979  * mode is enabled and port MAC address is equal to the packet destination MAC
9980  * address. The fix for this issue may not be integrated in the following
9981  * firmware version. So the workaround in software driver is needed. It needs
9982  * to modify the initial values of 3 internal only registers for both X710 and
9983  * XL710. Note that the values for X710 or XL710 could be different, and the
9984  * workaround can be removed when it is fixed in firmware in the future.
9985  */
9986
9987 /* For both X710 and XL710 */
9988 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9989 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9990 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9991
9992 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9993 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9994
9995 /* For X722 */
9996 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9997 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9998
9999 /* For X710 */
10000 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10001 /* For XL710 */
10002 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10003 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10004
10005 static int
10006 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10007 {
10008         enum i40e_status_code status;
10009         struct i40e_aq_get_phy_abilities_resp phy_ab;
10010         int ret = -ENOTSUP;
10011         int retries = 0;
10012
10013         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10014                                               NULL);
10015
10016         while (status) {
10017                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10018                         status);
10019                 retries++;
10020                 rte_delay_us(100000);
10021                 if  (retries < 5)
10022                         status = i40e_aq_get_phy_capabilities(hw, false,
10023                                         true, &phy_ab, NULL);
10024                 else
10025                         return ret;
10026         }
10027         return 0;
10028 }
10029
10030 static void
10031 i40e_configure_registers(struct i40e_hw *hw)
10032 {
10033         static struct {
10034                 uint32_t addr;
10035                 uint64_t val;
10036         } reg_table[] = {
10037                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10038                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10039                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10040         };
10041         uint64_t reg;
10042         uint32_t i;
10043         int ret;
10044
10045         for (i = 0; i < RTE_DIM(reg_table); i++) {
10046                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10047                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10048                                 reg_table[i].val =
10049                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10050                         else /* For X710/XL710/XXV710 */
10051                                 if (hw->aq.fw_maj_ver < 6)
10052                                         reg_table[i].val =
10053                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10054                                 else
10055                                         reg_table[i].val =
10056                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10057                 }
10058
10059                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10060                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10061                                 reg_table[i].val =
10062                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10063                         else /* For X710/XL710/XXV710 */
10064                                 reg_table[i].val =
10065                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10066                 }
10067
10068                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10069                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
10070                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
10071                                 reg_table[i].val =
10072                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
10073                         else /* For X710 */
10074                                 reg_table[i].val =
10075                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
10076                 }
10077
10078                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10079                                                         &reg, NULL);
10080                 if (ret < 0) {
10081                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10082                                                         reg_table[i].addr);
10083                         break;
10084                 }
10085                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10086                                                 reg_table[i].addr, reg);
10087                 if (reg == reg_table[i].val)
10088                         continue;
10089
10090                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10091                                                 reg_table[i].val, NULL);
10092                 if (ret < 0) {
10093                         PMD_DRV_LOG(ERR,
10094                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10095                                 reg_table[i].val, reg_table[i].addr);
10096                         break;
10097                 }
10098                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10099                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10100         }
10101 }
10102
10103 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10104 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10105 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10106 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10107 static int
10108 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10109 {
10110         uint32_t reg;
10111         int ret;
10112
10113         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10114                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10115                 return -EINVAL;
10116         }
10117
10118         /* Configure for double VLAN RX stripping */
10119         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10120         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10121                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10122                 ret = i40e_aq_debug_write_register(hw,
10123                                                    I40E_VSI_TSR(vsi->vsi_id),
10124                                                    reg, NULL);
10125                 if (ret < 0) {
10126                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10127                                     vsi->vsi_id);
10128                         return I40E_ERR_CONFIG;
10129                 }
10130         }
10131
10132         /* Configure for double VLAN TX insertion */
10133         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10134         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10135                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10136                 ret = i40e_aq_debug_write_register(hw,
10137                                                    I40E_VSI_L2TAGSTXVALID(
10138                                                    vsi->vsi_id), reg, NULL);
10139                 if (ret < 0) {
10140                         PMD_DRV_LOG(ERR,
10141                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10142                                 vsi->vsi_id);
10143                         return I40E_ERR_CONFIG;
10144                 }
10145         }
10146
10147         return 0;
10148 }
10149
10150 /**
10151  * i40e_aq_add_mirror_rule
10152  * @hw: pointer to the hardware structure
10153  * @seid: VEB seid to add mirror rule to
10154  * @dst_id: destination vsi seid
10155  * @entries: Buffer which contains the entities to be mirrored
10156  * @count: number of entities contained in the buffer
10157  * @rule_id:the rule_id of the rule to be added
10158  *
10159  * Add a mirror rule for a given veb.
10160  *
10161  **/
10162 static enum i40e_status_code
10163 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10164                         uint16_t seid, uint16_t dst_id,
10165                         uint16_t rule_type, uint16_t *entries,
10166                         uint16_t count, uint16_t *rule_id)
10167 {
10168         struct i40e_aq_desc desc;
10169         struct i40e_aqc_add_delete_mirror_rule cmd;
10170         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10171                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10172                 &desc.params.raw;
10173         uint16_t buff_len;
10174         enum i40e_status_code status;
10175
10176         i40e_fill_default_direct_cmd_desc(&desc,
10177                                           i40e_aqc_opc_add_mirror_rule);
10178         memset(&cmd, 0, sizeof(cmd));
10179
10180         buff_len = sizeof(uint16_t) * count;
10181         desc.datalen = rte_cpu_to_le_16(buff_len);
10182         if (buff_len > 0)
10183                 desc.flags |= rte_cpu_to_le_16(
10184                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10185         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10186                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10187         cmd.num_entries = rte_cpu_to_le_16(count);
10188         cmd.seid = rte_cpu_to_le_16(seid);
10189         cmd.destination = rte_cpu_to_le_16(dst_id);
10190
10191         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10192         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10193         PMD_DRV_LOG(INFO,
10194                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10195                 hw->aq.asq_last_status, resp->rule_id,
10196                 resp->mirror_rules_used, resp->mirror_rules_free);
10197         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10198
10199         return status;
10200 }
10201
10202 /**
10203  * i40e_aq_del_mirror_rule
10204  * @hw: pointer to the hardware structure
10205  * @seid: VEB seid to add mirror rule to
10206  * @entries: Buffer which contains the entities to be mirrored
10207  * @count: number of entities contained in the buffer
10208  * @rule_id:the rule_id of the rule to be delete
10209  *
10210  * Delete a mirror rule for a given veb.
10211  *
10212  **/
10213 static enum i40e_status_code
10214 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10215                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10216                 uint16_t count, uint16_t rule_id)
10217 {
10218         struct i40e_aq_desc desc;
10219         struct i40e_aqc_add_delete_mirror_rule cmd;
10220         uint16_t buff_len = 0;
10221         enum i40e_status_code status;
10222         void *buff = NULL;
10223
10224         i40e_fill_default_direct_cmd_desc(&desc,
10225                                           i40e_aqc_opc_delete_mirror_rule);
10226         memset(&cmd, 0, sizeof(cmd));
10227         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10228                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10229                                                           I40E_AQ_FLAG_RD));
10230                 cmd.num_entries = count;
10231                 buff_len = sizeof(uint16_t) * count;
10232                 desc.datalen = rte_cpu_to_le_16(buff_len);
10233                 buff = (void *)entries;
10234         } else
10235                 /* rule id is filled in destination field for deleting mirror rule */
10236                 cmd.destination = rte_cpu_to_le_16(rule_id);
10237
10238         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10239                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10240         cmd.seid = rte_cpu_to_le_16(seid);
10241
10242         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10243         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10244
10245         return status;
10246 }
10247
10248 /**
10249  * i40e_mirror_rule_set
10250  * @dev: pointer to the hardware structure
10251  * @mirror_conf: mirror rule info
10252  * @sw_id: mirror rule's sw_id
10253  * @on: enable/disable
10254  *
10255  * set a mirror rule.
10256  *
10257  **/
10258 static int
10259 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10260                         struct rte_eth_mirror_conf *mirror_conf,
10261                         uint8_t sw_id, uint8_t on)
10262 {
10263         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10264         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10265         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10266         struct i40e_mirror_rule *parent = NULL;
10267         uint16_t seid, dst_seid, rule_id;
10268         uint16_t i, j = 0;
10269         int ret;
10270
10271         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10272
10273         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10274                 PMD_DRV_LOG(ERR,
10275                         "mirror rule can not be configured without veb or vfs.");
10276                 return -ENOSYS;
10277         }
10278         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10279                 PMD_DRV_LOG(ERR, "mirror table is full.");
10280                 return -ENOSPC;
10281         }
10282         if (mirror_conf->dst_pool > pf->vf_num) {
10283                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10284                                  mirror_conf->dst_pool);
10285                 return -EINVAL;
10286         }
10287
10288         seid = pf->main_vsi->veb->seid;
10289
10290         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10291                 if (sw_id <= it->index) {
10292                         mirr_rule = it;
10293                         break;
10294                 }
10295                 parent = it;
10296         }
10297         if (mirr_rule && sw_id == mirr_rule->index) {
10298                 if (on) {
10299                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10300                         return -EEXIST;
10301                 } else {
10302                         ret = i40e_aq_del_mirror_rule(hw, seid,
10303                                         mirr_rule->rule_type,
10304                                         mirr_rule->entries,
10305                                         mirr_rule->num_entries, mirr_rule->id);
10306                         if (ret < 0) {
10307                                 PMD_DRV_LOG(ERR,
10308                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10309                                         ret, hw->aq.asq_last_status);
10310                                 return -ENOSYS;
10311                         }
10312                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10313                         rte_free(mirr_rule);
10314                         pf->nb_mirror_rule--;
10315                         return 0;
10316                 }
10317         } else if (!on) {
10318                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10319                 return -ENOENT;
10320         }
10321
10322         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10323                                 sizeof(struct i40e_mirror_rule) , 0);
10324         if (!mirr_rule) {
10325                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10326                 return I40E_ERR_NO_MEMORY;
10327         }
10328         switch (mirror_conf->rule_type) {
10329         case ETH_MIRROR_VLAN:
10330                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10331                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10332                                 mirr_rule->entries[j] =
10333                                         mirror_conf->vlan.vlan_id[i];
10334                                 j++;
10335                         }
10336                 }
10337                 if (j == 0) {
10338                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10339                         rte_free(mirr_rule);
10340                         return -EINVAL;
10341                 }
10342                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10343                 break;
10344         case ETH_MIRROR_VIRTUAL_POOL_UP:
10345         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10346                 /* check if the specified pool bit is out of range */
10347                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10348                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10349                         rte_free(mirr_rule);
10350                         return -EINVAL;
10351                 }
10352                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10353                         if (mirror_conf->pool_mask & (1ULL << i)) {
10354                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10355                                 j++;
10356                         }
10357                 }
10358                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10359                         /* add pf vsi to entries */
10360                         mirr_rule->entries[j] = pf->main_vsi_seid;
10361                         j++;
10362                 }
10363                 if (j == 0) {
10364                         PMD_DRV_LOG(ERR, "pool is not specified.");
10365                         rte_free(mirr_rule);
10366                         return -EINVAL;
10367                 }
10368                 /* egress and ingress in aq commands means from switch but not port */
10369                 mirr_rule->rule_type =
10370                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10371                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10372                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10373                 break;
10374         case ETH_MIRROR_UPLINK_PORT:
10375                 /* egress and ingress in aq commands means from switch but not port*/
10376                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10377                 break;
10378         case ETH_MIRROR_DOWNLINK_PORT:
10379                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10380                 break;
10381         default:
10382                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10383                         mirror_conf->rule_type);
10384                 rte_free(mirr_rule);
10385                 return -EINVAL;
10386         }
10387
10388         /* If the dst_pool is equal to vf_num, consider it as PF */
10389         if (mirror_conf->dst_pool == pf->vf_num)
10390                 dst_seid = pf->main_vsi_seid;
10391         else
10392                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10393
10394         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10395                                       mirr_rule->rule_type, mirr_rule->entries,
10396                                       j, &rule_id);
10397         if (ret < 0) {
10398                 PMD_DRV_LOG(ERR,
10399                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10400                         ret, hw->aq.asq_last_status);
10401                 rte_free(mirr_rule);
10402                 return -ENOSYS;
10403         }
10404
10405         mirr_rule->index = sw_id;
10406         mirr_rule->num_entries = j;
10407         mirr_rule->id = rule_id;
10408         mirr_rule->dst_vsi_seid = dst_seid;
10409
10410         if (parent)
10411                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10412         else
10413                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10414
10415         pf->nb_mirror_rule++;
10416         return 0;
10417 }
10418
10419 /**
10420  * i40e_mirror_rule_reset
10421  * @dev: pointer to the device
10422  * @sw_id: mirror rule's sw_id
10423  *
10424  * reset a mirror rule.
10425  *
10426  **/
10427 static int
10428 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10429 {
10430         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10431         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10432         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10433         uint16_t seid;
10434         int ret;
10435
10436         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10437
10438         seid = pf->main_vsi->veb->seid;
10439
10440         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10441                 if (sw_id == it->index) {
10442                         mirr_rule = it;
10443                         break;
10444                 }
10445         }
10446         if (mirr_rule) {
10447                 ret = i40e_aq_del_mirror_rule(hw, seid,
10448                                 mirr_rule->rule_type,
10449                                 mirr_rule->entries,
10450                                 mirr_rule->num_entries, mirr_rule->id);
10451                 if (ret < 0) {
10452                         PMD_DRV_LOG(ERR,
10453                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10454                                 ret, hw->aq.asq_last_status);
10455                         return -ENOSYS;
10456                 }
10457                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10458                 rte_free(mirr_rule);
10459                 pf->nb_mirror_rule--;
10460         } else {
10461                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10462                 return -ENOENT;
10463         }
10464         return 0;
10465 }
10466
10467 static uint64_t
10468 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10469 {
10470         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10471         uint64_t systim_cycles;
10472
10473         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10474         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10475                         << 32;
10476
10477         return systim_cycles;
10478 }
10479
10480 static uint64_t
10481 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10482 {
10483         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10484         uint64_t rx_tstamp;
10485
10486         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10487         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10488                         << 32;
10489
10490         return rx_tstamp;
10491 }
10492
10493 static uint64_t
10494 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10495 {
10496         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10497         uint64_t tx_tstamp;
10498
10499         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10500         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10501                         << 32;
10502
10503         return tx_tstamp;
10504 }
10505
10506 static void
10507 i40e_start_timecounters(struct rte_eth_dev *dev)
10508 {
10509         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10510         struct i40e_adapter *adapter =
10511                         (struct i40e_adapter *)dev->data->dev_private;
10512         struct rte_eth_link link;
10513         uint32_t tsync_inc_l;
10514         uint32_t tsync_inc_h;
10515
10516         /* Get current link speed. */
10517         i40e_dev_link_update(dev, 1);
10518         rte_eth_linkstatus_get(dev, &link);
10519
10520         switch (link.link_speed) {
10521         case ETH_SPEED_NUM_40G:
10522                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10523                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10524                 break;
10525         case ETH_SPEED_NUM_10G:
10526                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10527                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10528                 break;
10529         case ETH_SPEED_NUM_1G:
10530                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10531                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10532                 break;
10533         default:
10534                 tsync_inc_l = 0x0;
10535                 tsync_inc_h = 0x0;
10536         }
10537
10538         /* Set the timesync increment value. */
10539         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10540         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10541
10542         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10543         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10544         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10545
10546         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10547         adapter->systime_tc.cc_shift = 0;
10548         adapter->systime_tc.nsec_mask = 0;
10549
10550         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10551         adapter->rx_tstamp_tc.cc_shift = 0;
10552         adapter->rx_tstamp_tc.nsec_mask = 0;
10553
10554         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10555         adapter->tx_tstamp_tc.cc_shift = 0;
10556         adapter->tx_tstamp_tc.nsec_mask = 0;
10557 }
10558
10559 static int
10560 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10561 {
10562         struct i40e_adapter *adapter =
10563                         (struct i40e_adapter *)dev->data->dev_private;
10564
10565         adapter->systime_tc.nsec += delta;
10566         adapter->rx_tstamp_tc.nsec += delta;
10567         adapter->tx_tstamp_tc.nsec += delta;
10568
10569         return 0;
10570 }
10571
10572 static int
10573 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10574 {
10575         uint64_t ns;
10576         struct i40e_adapter *adapter =
10577                         (struct i40e_adapter *)dev->data->dev_private;
10578
10579         ns = rte_timespec_to_ns(ts);
10580
10581         /* Set the timecounters to a new value. */
10582         adapter->systime_tc.nsec = ns;
10583         adapter->rx_tstamp_tc.nsec = ns;
10584         adapter->tx_tstamp_tc.nsec = ns;
10585
10586         return 0;
10587 }
10588
10589 static int
10590 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10591 {
10592         uint64_t ns, systime_cycles;
10593         struct i40e_adapter *adapter =
10594                         (struct i40e_adapter *)dev->data->dev_private;
10595
10596         systime_cycles = i40e_read_systime_cyclecounter(dev);
10597         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10598         *ts = rte_ns_to_timespec(ns);
10599
10600         return 0;
10601 }
10602
10603 static int
10604 i40e_timesync_enable(struct rte_eth_dev *dev)
10605 {
10606         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10607         uint32_t tsync_ctl_l;
10608         uint32_t tsync_ctl_h;
10609
10610         /* Stop the timesync system time. */
10611         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10612         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10613         /* Reset the timesync system time value. */
10614         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10615         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10616
10617         i40e_start_timecounters(dev);
10618
10619         /* Clear timesync registers. */
10620         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10621         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10622         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10623         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10624         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10625         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10626
10627         /* Enable timestamping of PTP packets. */
10628         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10629         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10630
10631         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10632         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10633         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10634
10635         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10636         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10637
10638         return 0;
10639 }
10640
10641 static int
10642 i40e_timesync_disable(struct rte_eth_dev *dev)
10643 {
10644         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10645         uint32_t tsync_ctl_l;
10646         uint32_t tsync_ctl_h;
10647
10648         /* Disable timestamping of transmitted PTP packets. */
10649         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10650         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10651
10652         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10653         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10654
10655         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10656         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10657
10658         /* Reset the timesync increment value. */
10659         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10660         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10661
10662         return 0;
10663 }
10664
10665 static int
10666 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10667                                 struct timespec *timestamp, uint32_t flags)
10668 {
10669         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10670         struct i40e_adapter *adapter =
10671                 (struct i40e_adapter *)dev->data->dev_private;
10672
10673         uint32_t sync_status;
10674         uint32_t index = flags & 0x03;
10675         uint64_t rx_tstamp_cycles;
10676         uint64_t ns;
10677
10678         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10679         if ((sync_status & (1 << index)) == 0)
10680                 return -EINVAL;
10681
10682         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10683         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10684         *timestamp = rte_ns_to_timespec(ns);
10685
10686         return 0;
10687 }
10688
10689 static int
10690 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10691                                 struct timespec *timestamp)
10692 {
10693         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10694         struct i40e_adapter *adapter =
10695                 (struct i40e_adapter *)dev->data->dev_private;
10696
10697         uint32_t sync_status;
10698         uint64_t tx_tstamp_cycles;
10699         uint64_t ns;
10700
10701         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10702         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10703                 return -EINVAL;
10704
10705         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10706         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10707         *timestamp = rte_ns_to_timespec(ns);
10708
10709         return 0;
10710 }
10711
10712 /*
10713  * i40e_parse_dcb_configure - parse dcb configure from user
10714  * @dev: the device being configured
10715  * @dcb_cfg: pointer of the result of parse
10716  * @*tc_map: bit map of enabled traffic classes
10717  *
10718  * Returns 0 on success, negative value on failure
10719  */
10720 static int
10721 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10722                          struct i40e_dcbx_config *dcb_cfg,
10723                          uint8_t *tc_map)
10724 {
10725         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10726         uint8_t i, tc_bw, bw_lf;
10727
10728         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10729
10730         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10731         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10732                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10733                 return -EINVAL;
10734         }
10735
10736         /* assume each tc has the same bw */
10737         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10738         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10739                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10740         /* to ensure the sum of tcbw is equal to 100 */
10741         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10742         for (i = 0; i < bw_lf; i++)
10743                 dcb_cfg->etscfg.tcbwtable[i]++;
10744
10745         /* assume each tc has the same Transmission Selection Algorithm */
10746         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10747                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10748
10749         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10750                 dcb_cfg->etscfg.prioritytable[i] =
10751                                 dcb_rx_conf->dcb_tc[i];
10752
10753         /* FW needs one App to configure HW */
10754         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10755         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10756         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10757         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10758
10759         if (dcb_rx_conf->nb_tcs == 0)
10760                 *tc_map = 1; /* tc0 only */
10761         else
10762                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10763
10764         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10765                 dcb_cfg->pfc.willing = 0;
10766                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10767                 dcb_cfg->pfc.pfcenable = *tc_map;
10768         }
10769         return 0;
10770 }
10771
10772
10773 static enum i40e_status_code
10774 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10775                               struct i40e_aqc_vsi_properties_data *info,
10776                               uint8_t enabled_tcmap)
10777 {
10778         enum i40e_status_code ret;
10779         int i, total_tc = 0;
10780         uint16_t qpnum_per_tc, bsf, qp_idx;
10781         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10782         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10783         uint16_t used_queues;
10784
10785         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10786         if (ret != I40E_SUCCESS)
10787                 return ret;
10788
10789         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10790                 if (enabled_tcmap & (1 << i))
10791                         total_tc++;
10792         }
10793         if (total_tc == 0)
10794                 total_tc = 1;
10795         vsi->enabled_tc = enabled_tcmap;
10796
10797         /* different VSI has different queues assigned */
10798         if (vsi->type == I40E_VSI_MAIN)
10799                 used_queues = dev_data->nb_rx_queues -
10800                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10801         else if (vsi->type == I40E_VSI_VMDQ2)
10802                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10803         else {
10804                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10805                 return I40E_ERR_NO_AVAILABLE_VSI;
10806         }
10807
10808         qpnum_per_tc = used_queues / total_tc;
10809         /* Number of queues per enabled TC */
10810         if (qpnum_per_tc == 0) {
10811                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10812                 return I40E_ERR_INVALID_QP_ID;
10813         }
10814         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10815                                 I40E_MAX_Q_PER_TC);
10816         bsf = rte_bsf32(qpnum_per_tc);
10817
10818         /**
10819          * Configure TC and queue mapping parameters, for enabled TC,
10820          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10821          * default queue will serve it.
10822          */
10823         qp_idx = 0;
10824         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10825                 if (vsi->enabled_tc & (1 << i)) {
10826                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10827                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10828                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10829                         qp_idx += qpnum_per_tc;
10830                 } else
10831                         info->tc_mapping[i] = 0;
10832         }
10833
10834         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10835         if (vsi->type == I40E_VSI_SRIOV) {
10836                 info->mapping_flags |=
10837                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10838                 for (i = 0; i < vsi->nb_qps; i++)
10839                         info->queue_mapping[i] =
10840                                 rte_cpu_to_le_16(vsi->base_queue + i);
10841         } else {
10842                 info->mapping_flags |=
10843                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10844                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10845         }
10846         info->valid_sections |=
10847                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10848
10849         return I40E_SUCCESS;
10850 }
10851
10852 /*
10853  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10854  * @veb: VEB to be configured
10855  * @tc_map: enabled TC bitmap
10856  *
10857  * Returns 0 on success, negative value on failure
10858  */
10859 static enum i40e_status_code
10860 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10861 {
10862         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10863         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10864         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10865         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10866         enum i40e_status_code ret = I40E_SUCCESS;
10867         int i;
10868         uint32_t bw_max;
10869
10870         /* Check if enabled_tc is same as existing or new TCs */
10871         if (veb->enabled_tc == tc_map)
10872                 return ret;
10873
10874         /* configure tc bandwidth */
10875         memset(&veb_bw, 0, sizeof(veb_bw));
10876         veb_bw.tc_valid_bits = tc_map;
10877         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10878         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10879                 if (tc_map & BIT_ULL(i))
10880                         veb_bw.tc_bw_share_credits[i] = 1;
10881         }
10882         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10883                                                    &veb_bw, NULL);
10884         if (ret) {
10885                 PMD_INIT_LOG(ERR,
10886                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10887                         hw->aq.asq_last_status);
10888                 return ret;
10889         }
10890
10891         memset(&ets_query, 0, sizeof(ets_query));
10892         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10893                                                    &ets_query, NULL);
10894         if (ret != I40E_SUCCESS) {
10895                 PMD_DRV_LOG(ERR,
10896                         "Failed to get switch_comp ETS configuration %u",
10897                         hw->aq.asq_last_status);
10898                 return ret;
10899         }
10900         memset(&bw_query, 0, sizeof(bw_query));
10901         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10902                                                   &bw_query, NULL);
10903         if (ret != I40E_SUCCESS) {
10904                 PMD_DRV_LOG(ERR,
10905                         "Failed to get switch_comp bandwidth configuration %u",
10906                         hw->aq.asq_last_status);
10907                 return ret;
10908         }
10909
10910         /* store and print out BW info */
10911         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10912         veb->bw_info.bw_max = ets_query.tc_bw_max;
10913         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10914         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10915         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10916                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10917                      I40E_16_BIT_WIDTH);
10918         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10919                 veb->bw_info.bw_ets_share_credits[i] =
10920                                 bw_query.tc_bw_share_credits[i];
10921                 veb->bw_info.bw_ets_credits[i] =
10922                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10923                 /* 4 bits per TC, 4th bit is reserved */
10924                 veb->bw_info.bw_ets_max[i] =
10925                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10926                                   RTE_LEN2MASK(3, uint8_t));
10927                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10928                             veb->bw_info.bw_ets_share_credits[i]);
10929                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10930                             veb->bw_info.bw_ets_credits[i]);
10931                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10932                             veb->bw_info.bw_ets_max[i]);
10933         }
10934
10935         veb->enabled_tc = tc_map;
10936
10937         return ret;
10938 }
10939
10940
10941 /*
10942  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10943  * @vsi: VSI to be configured
10944  * @tc_map: enabled TC bitmap
10945  *
10946  * Returns 0 on success, negative value on failure
10947  */
10948 static enum i40e_status_code
10949 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10950 {
10951         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10952         struct i40e_vsi_context ctxt;
10953         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10954         enum i40e_status_code ret = I40E_SUCCESS;
10955         int i;
10956
10957         /* Check if enabled_tc is same as existing or new TCs */
10958         if (vsi->enabled_tc == tc_map)
10959                 return ret;
10960
10961         /* configure tc bandwidth */
10962         memset(&bw_data, 0, sizeof(bw_data));
10963         bw_data.tc_valid_bits = tc_map;
10964         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10965         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10966                 if (tc_map & BIT_ULL(i))
10967                         bw_data.tc_bw_credits[i] = 1;
10968         }
10969         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10970         if (ret) {
10971                 PMD_INIT_LOG(ERR,
10972                         "AQ command Config VSI BW allocation per TC failed = %d",
10973                         hw->aq.asq_last_status);
10974                 goto out;
10975         }
10976         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10977                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10978
10979         /* Update Queue Pairs Mapping for currently enabled UPs */
10980         ctxt.seid = vsi->seid;
10981         ctxt.pf_num = hw->pf_id;
10982         ctxt.vf_num = 0;
10983         ctxt.uplink_seid = vsi->uplink_seid;
10984         ctxt.info = vsi->info;
10985         i40e_get_cap(hw);
10986         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10987         if (ret)
10988                 goto out;
10989
10990         /* Update the VSI after updating the VSI queue-mapping information */
10991         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10992         if (ret) {
10993                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10994                         hw->aq.asq_last_status);
10995                 goto out;
10996         }
10997         /* update the local VSI info with updated queue map */
10998         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10999                                         sizeof(vsi->info.tc_mapping));
11000         rte_memcpy(&vsi->info.queue_mapping,
11001                         &ctxt.info.queue_mapping,
11002                 sizeof(vsi->info.queue_mapping));
11003         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11004         vsi->info.valid_sections = 0;
11005
11006         /* query and update current VSI BW information */
11007         ret = i40e_vsi_get_bw_config(vsi);
11008         if (ret) {
11009                 PMD_INIT_LOG(ERR,
11010                          "Failed updating vsi bw info, err %s aq_err %s",
11011                          i40e_stat_str(hw, ret),
11012                          i40e_aq_str(hw, hw->aq.asq_last_status));
11013                 goto out;
11014         }
11015
11016         vsi->enabled_tc = tc_map;
11017
11018 out:
11019         return ret;
11020 }
11021
11022 /*
11023  * i40e_dcb_hw_configure - program the dcb setting to hw
11024  * @pf: pf the configuration is taken on
11025  * @new_cfg: new configuration
11026  * @tc_map: enabled TC bitmap
11027  *
11028  * Returns 0 on success, negative value on failure
11029  */
11030 static enum i40e_status_code
11031 i40e_dcb_hw_configure(struct i40e_pf *pf,
11032                       struct i40e_dcbx_config *new_cfg,
11033                       uint8_t tc_map)
11034 {
11035         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11036         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11037         struct i40e_vsi *main_vsi = pf->main_vsi;
11038         struct i40e_vsi_list *vsi_list;
11039         enum i40e_status_code ret;
11040         int i;
11041         uint32_t val;
11042
11043         /* Use the FW API if FW > v4.4*/
11044         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11045               (hw->aq.fw_maj_ver >= 5))) {
11046                 PMD_INIT_LOG(ERR,
11047                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11048                 return I40E_ERR_FIRMWARE_API_VERSION;
11049         }
11050
11051         /* Check if need reconfiguration */
11052         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11053                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11054                 return I40E_SUCCESS;
11055         }
11056
11057         /* Copy the new config to the current config */
11058         *old_cfg = *new_cfg;
11059         old_cfg->etsrec = old_cfg->etscfg;
11060         ret = i40e_set_dcb_config(hw);
11061         if (ret) {
11062                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11063                          i40e_stat_str(hw, ret),
11064                          i40e_aq_str(hw, hw->aq.asq_last_status));
11065                 return ret;
11066         }
11067         /* set receive Arbiter to RR mode and ETS scheme by default */
11068         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11069                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11070                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11071                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11072                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11073                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11074                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11075                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11076                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11077                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11078                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11079                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11080                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11081         }
11082         /* get local mib to check whether it is configured correctly */
11083         /* IEEE mode */
11084         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11085         /* Get Local DCB Config */
11086         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11087                                      &hw->local_dcbx_config);
11088
11089         /* if Veb is created, need to update TC of it at first */
11090         if (main_vsi->veb) {
11091                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11092                 if (ret)
11093                         PMD_INIT_LOG(WARNING,
11094                                  "Failed configuring TC for VEB seid=%d",
11095                                  main_vsi->veb->seid);
11096         }
11097         /* Update each VSI */
11098         i40e_vsi_config_tc(main_vsi, tc_map);
11099         if (main_vsi->veb) {
11100                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11101                         /* Beside main VSI and VMDQ VSIs, only enable default
11102                          * TC for other VSIs
11103                          */
11104                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11105                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11106                                                          tc_map);
11107                         else
11108                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11109                                                          I40E_DEFAULT_TCMAP);
11110                         if (ret)
11111                                 PMD_INIT_LOG(WARNING,
11112                                         "Failed configuring TC for VSI seid=%d",
11113                                         vsi_list->vsi->seid);
11114                         /* continue */
11115                 }
11116         }
11117         return I40E_SUCCESS;
11118 }
11119
11120 /*
11121  * i40e_dcb_init_configure - initial dcb config
11122  * @dev: device being configured
11123  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11124  *
11125  * Returns 0 on success, negative value on failure
11126  */
11127 int
11128 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11129 {
11130         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11131         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11132         int i, ret = 0;
11133
11134         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11135                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11136                 return -ENOTSUP;
11137         }
11138
11139         /* DCB initialization:
11140          * Update DCB configuration from the Firmware and configure
11141          * LLDP MIB change event.
11142          */
11143         if (sw_dcb == TRUE) {
11144                 ret = i40e_init_dcb(hw);
11145                 /* If lldp agent is stopped, the return value from
11146                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11147                  * adminq status. Otherwise, it should return success.
11148                  */
11149                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11150                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11151                         memset(&hw->local_dcbx_config, 0,
11152                                 sizeof(struct i40e_dcbx_config));
11153                         /* set dcb default configuration */
11154                         hw->local_dcbx_config.etscfg.willing = 0;
11155                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11156                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11157                         hw->local_dcbx_config.etscfg.tsatable[0] =
11158                                                 I40E_IEEE_TSA_ETS;
11159                         /* all UPs mapping to TC0 */
11160                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11161                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11162                         hw->local_dcbx_config.etsrec =
11163                                 hw->local_dcbx_config.etscfg;
11164                         hw->local_dcbx_config.pfc.willing = 0;
11165                         hw->local_dcbx_config.pfc.pfccap =
11166                                                 I40E_MAX_TRAFFIC_CLASS;
11167                         /* FW needs one App to configure HW */
11168                         hw->local_dcbx_config.numapps = 1;
11169                         hw->local_dcbx_config.app[0].selector =
11170                                                 I40E_APP_SEL_ETHTYPE;
11171                         hw->local_dcbx_config.app[0].priority = 3;
11172                         hw->local_dcbx_config.app[0].protocolid =
11173                                                 I40E_APP_PROTOID_FCOE;
11174                         ret = i40e_set_dcb_config(hw);
11175                         if (ret) {
11176                                 PMD_INIT_LOG(ERR,
11177                                         "default dcb config fails. err = %d, aq_err = %d.",
11178                                         ret, hw->aq.asq_last_status);
11179                                 return -ENOSYS;
11180                         }
11181                 } else {
11182                         PMD_INIT_LOG(ERR,
11183                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11184                                 ret, hw->aq.asq_last_status);
11185                         return -ENOTSUP;
11186                 }
11187         } else {
11188                 ret = i40e_aq_start_lldp(hw, NULL);
11189                 if (ret != I40E_SUCCESS)
11190                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11191
11192                 ret = i40e_init_dcb(hw);
11193                 if (!ret) {
11194                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11195                                 PMD_INIT_LOG(ERR,
11196                                         "HW doesn't support DCBX offload.");
11197                                 return -ENOTSUP;
11198                         }
11199                 } else {
11200                         PMD_INIT_LOG(ERR,
11201                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11202                                 ret, hw->aq.asq_last_status);
11203                         return -ENOTSUP;
11204                 }
11205         }
11206         return 0;
11207 }
11208
11209 /*
11210  * i40e_dcb_setup - setup dcb related config
11211  * @dev: device being configured
11212  *
11213  * Returns 0 on success, negative value on failure
11214  */
11215 static int
11216 i40e_dcb_setup(struct rte_eth_dev *dev)
11217 {
11218         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11219         struct i40e_dcbx_config dcb_cfg;
11220         uint8_t tc_map = 0;
11221         int ret = 0;
11222
11223         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11224                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11225                 return -ENOTSUP;
11226         }
11227
11228         if (pf->vf_num != 0)
11229                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11230
11231         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11232         if (ret) {
11233                 PMD_INIT_LOG(ERR, "invalid dcb config");
11234                 return -EINVAL;
11235         }
11236         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11237         if (ret) {
11238                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11239                 return -ENOSYS;
11240         }
11241
11242         return 0;
11243 }
11244
11245 static int
11246 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11247                       struct rte_eth_dcb_info *dcb_info)
11248 {
11249         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11250         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11251         struct i40e_vsi *vsi = pf->main_vsi;
11252         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11253         uint16_t bsf, tc_mapping;
11254         int i, j = 0;
11255
11256         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11257                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11258         else
11259                 dcb_info->nb_tcs = 1;
11260         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11261                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11262         for (i = 0; i < dcb_info->nb_tcs; i++)
11263                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11264
11265         /* get queue mapping if vmdq is disabled */
11266         if (!pf->nb_cfg_vmdq_vsi) {
11267                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11268                         if (!(vsi->enabled_tc & (1 << i)))
11269                                 continue;
11270                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11271                         dcb_info->tc_queue.tc_rxq[j][i].base =
11272                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11273                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11274                         dcb_info->tc_queue.tc_txq[j][i].base =
11275                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11276                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11277                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11278                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11279                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11280                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11281                 }
11282                 return 0;
11283         }
11284
11285         /* get queue mapping if vmdq is enabled */
11286         do {
11287                 vsi = pf->vmdq[j].vsi;
11288                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11289                         if (!(vsi->enabled_tc & (1 << i)))
11290                                 continue;
11291                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11292                         dcb_info->tc_queue.tc_rxq[j][i].base =
11293                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11294                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11295                         dcb_info->tc_queue.tc_txq[j][i].base =
11296                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11297                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11298                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11299                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11300                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11301                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11302                 }
11303                 j++;
11304         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11305         return 0;
11306 }
11307
11308 static int
11309 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11310 {
11311         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11312         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11313         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11314         uint16_t msix_intr;
11315
11316         msix_intr = intr_handle->intr_vec[queue_id];
11317         if (msix_intr == I40E_MISC_VEC_ID)
11318                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11319                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11320                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11321                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11322         else
11323                 I40E_WRITE_REG(hw,
11324                                I40E_PFINT_DYN_CTLN(msix_intr -
11325                                                    I40E_RX_VEC_START),
11326                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11327                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11328                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11329
11330         I40E_WRITE_FLUSH(hw);
11331         rte_intr_enable(&pci_dev->intr_handle);
11332
11333         return 0;
11334 }
11335
11336 static int
11337 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11338 {
11339         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11340         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11341         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11342         uint16_t msix_intr;
11343
11344         msix_intr = intr_handle->intr_vec[queue_id];
11345         if (msix_intr == I40E_MISC_VEC_ID)
11346                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11347                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11348         else
11349                 I40E_WRITE_REG(hw,
11350                                I40E_PFINT_DYN_CTLN(msix_intr -
11351                                                    I40E_RX_VEC_START),
11352                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11353         I40E_WRITE_FLUSH(hw);
11354
11355         return 0;
11356 }
11357
11358 static int i40e_get_regs(struct rte_eth_dev *dev,
11359                          struct rte_dev_reg_info *regs)
11360 {
11361         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11362         uint32_t *ptr_data = regs->data;
11363         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11364         const struct i40e_reg_info *reg_info;
11365
11366         if (ptr_data == NULL) {
11367                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11368                 regs->width = sizeof(uint32_t);
11369                 return 0;
11370         }
11371
11372         /* The first few registers have to be read using AQ operations */
11373         reg_idx = 0;
11374         while (i40e_regs_adminq[reg_idx].name) {
11375                 reg_info = &i40e_regs_adminq[reg_idx++];
11376                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11377                         for (arr_idx2 = 0;
11378                                         arr_idx2 <= reg_info->count2;
11379                                         arr_idx2++) {
11380                                 reg_offset = arr_idx * reg_info->stride1 +
11381                                         arr_idx2 * reg_info->stride2;
11382                                 reg_offset += reg_info->base_addr;
11383                                 ptr_data[reg_offset >> 2] =
11384                                         i40e_read_rx_ctl(hw, reg_offset);
11385                         }
11386         }
11387
11388         /* The remaining registers can be read using primitives */
11389         reg_idx = 0;
11390         while (i40e_regs_others[reg_idx].name) {
11391                 reg_info = &i40e_regs_others[reg_idx++];
11392                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11393                         for (arr_idx2 = 0;
11394                                         arr_idx2 <= reg_info->count2;
11395                                         arr_idx2++) {
11396                                 reg_offset = arr_idx * reg_info->stride1 +
11397                                         arr_idx2 * reg_info->stride2;
11398                                 reg_offset += reg_info->base_addr;
11399                                 ptr_data[reg_offset >> 2] =
11400                                         I40E_READ_REG(hw, reg_offset);
11401                         }
11402         }
11403
11404         return 0;
11405 }
11406
11407 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11408 {
11409         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11410
11411         /* Convert word count to byte count */
11412         return hw->nvm.sr_size << 1;
11413 }
11414
11415 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11416                            struct rte_dev_eeprom_info *eeprom)
11417 {
11418         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11419         uint16_t *data = eeprom->data;
11420         uint16_t offset, length, cnt_words;
11421         int ret_code;
11422
11423         offset = eeprom->offset >> 1;
11424         length = eeprom->length >> 1;
11425         cnt_words = length;
11426
11427         if (offset > hw->nvm.sr_size ||
11428                 offset + length > hw->nvm.sr_size) {
11429                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11430                 return -EINVAL;
11431         }
11432
11433         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11434
11435         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11436         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11437                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11438                 return -EIO;
11439         }
11440
11441         return 0;
11442 }
11443
11444 static int i40e_get_module_info(struct rte_eth_dev *dev,
11445                                 struct rte_eth_dev_module_info *modinfo)
11446 {
11447         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11448         uint32_t sff8472_comp = 0;
11449         uint32_t sff8472_swap = 0;
11450         uint32_t sff8636_rev = 0;
11451         i40e_status status;
11452         uint32_t type = 0;
11453
11454         /* Check if firmware supports reading module EEPROM. */
11455         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11456                 PMD_DRV_LOG(ERR,
11457                             "Module EEPROM memory read not supported. "
11458                             "Please update the NVM image.\n");
11459                 return -EINVAL;
11460         }
11461
11462         status = i40e_update_link_info(hw);
11463         if (status)
11464                 return -EIO;
11465
11466         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11467                 PMD_DRV_LOG(ERR,
11468                             "Cannot read module EEPROM memory. "
11469                             "No module connected.\n");
11470                 return -EINVAL;
11471         }
11472
11473         type = hw->phy.link_info.module_type[0];
11474
11475         switch (type) {
11476         case I40E_MODULE_TYPE_SFP:
11477                 status = i40e_aq_get_phy_register(hw,
11478                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11479                                 I40E_I2C_EEPROM_DEV_ADDR,
11480                                 I40E_MODULE_SFF_8472_COMP,
11481                                 &sff8472_comp, NULL);
11482                 if (status)
11483                         return -EIO;
11484
11485                 status = i40e_aq_get_phy_register(hw,
11486                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11487                                 I40E_I2C_EEPROM_DEV_ADDR,
11488                                 I40E_MODULE_SFF_8472_SWAP,
11489                                 &sff8472_swap, NULL);
11490                 if (status)
11491                         return -EIO;
11492
11493                 /* Check if the module requires address swap to access
11494                  * the other EEPROM memory page.
11495                  */
11496                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11497                         PMD_DRV_LOG(WARNING,
11498                                     "Module address swap to access "
11499                                     "page 0xA2 is not supported.\n");
11500                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11501                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11502                 } else if (sff8472_comp == 0x00) {
11503                         /* Module is not SFF-8472 compliant */
11504                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11505                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11506                 } else {
11507                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11508                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11509                 }
11510                 break;
11511         case I40E_MODULE_TYPE_QSFP_PLUS:
11512                 /* Read from memory page 0. */
11513                 status = i40e_aq_get_phy_register(hw,
11514                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11515                                 0,
11516                                 I40E_MODULE_REVISION_ADDR,
11517                                 &sff8636_rev, NULL);
11518                 if (status)
11519                         return -EIO;
11520                 /* Determine revision compliance byte */
11521                 if (sff8636_rev > 0x02) {
11522                         /* Module is SFF-8636 compliant */
11523                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11524                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11525                 } else {
11526                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11527                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11528                 }
11529                 break;
11530         case I40E_MODULE_TYPE_QSFP28:
11531                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11532                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11533                 break;
11534         default:
11535                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11536                 return -EINVAL;
11537         }
11538         return 0;
11539 }
11540
11541 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11542                                   struct rte_dev_eeprom_info *info)
11543 {
11544         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11545         bool is_sfp = false;
11546         i40e_status status;
11547         uint8_t *data = info->data;
11548         uint32_t value = 0;
11549         uint32_t i;
11550
11551         if (!info || !info->length || !data)
11552                 return -EINVAL;
11553
11554         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11555                 is_sfp = true;
11556
11557         for (i = 0; i < info->length; i++) {
11558                 u32 offset = i + info->offset;
11559                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11560
11561                 /* Check if we need to access the other memory page */
11562                 if (is_sfp) {
11563                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11564                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11565                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11566                         }
11567                 } else {
11568                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11569                                 /* Compute memory page number and offset. */
11570                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11571                                 addr++;
11572                         }
11573                 }
11574                 status = i40e_aq_get_phy_register(hw,
11575                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11576                                 addr, offset, &value, NULL);
11577                 if (status)
11578                         return -EIO;
11579                 data[i] = (uint8_t)value;
11580         }
11581         return 0;
11582 }
11583
11584 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11585                                      struct ether_addr *mac_addr)
11586 {
11587         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11588         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11589         struct i40e_vsi *vsi = pf->main_vsi;
11590         struct i40e_mac_filter_info mac_filter;
11591         struct i40e_mac_filter *f;
11592         int ret;
11593
11594         if (!is_valid_assigned_ether_addr(mac_addr)) {
11595                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11596                 return -EINVAL;
11597         }
11598
11599         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11600                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11601                         break;
11602         }
11603
11604         if (f == NULL) {
11605                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11606                 return -EIO;
11607         }
11608
11609         mac_filter = f->mac_info;
11610         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11611         if (ret != I40E_SUCCESS) {
11612                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11613                 return -EIO;
11614         }
11615         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11616         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11617         if (ret != I40E_SUCCESS) {
11618                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11619                 return -EIO;
11620         }
11621         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11622
11623         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11624                                         mac_addr->addr_bytes, NULL);
11625         if (ret != I40E_SUCCESS) {
11626                 PMD_DRV_LOG(ERR, "Failed to change mac");
11627                 return -EIO;
11628         }
11629
11630         return 0;
11631 }
11632
11633 static int
11634 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11635 {
11636         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11637         struct rte_eth_dev_data *dev_data = pf->dev_data;
11638         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11639         int ret = 0;
11640
11641         /* check if mtu is within the allowed range */
11642         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11643                 return -EINVAL;
11644
11645         /* mtu setting is forbidden if port is start */
11646         if (dev_data->dev_started) {
11647                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11648                             dev_data->port_id);
11649                 return -EBUSY;
11650         }
11651
11652         if (frame_size > ETHER_MAX_LEN)
11653                 dev_data->dev_conf.rxmode.offloads |=
11654                         DEV_RX_OFFLOAD_JUMBO_FRAME;
11655         else
11656                 dev_data->dev_conf.rxmode.offloads &=
11657                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11658
11659         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11660
11661         return ret;
11662 }
11663
11664 /* Restore ethertype filter */
11665 static void
11666 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11667 {
11668         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11669         struct i40e_ethertype_filter_list
11670                 *ethertype_list = &pf->ethertype.ethertype_list;
11671         struct i40e_ethertype_filter *f;
11672         struct i40e_control_filter_stats stats;
11673         uint16_t flags;
11674
11675         TAILQ_FOREACH(f, ethertype_list, rules) {
11676                 flags = 0;
11677                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11678                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11679                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11680                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11681                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11682
11683                 memset(&stats, 0, sizeof(stats));
11684                 i40e_aq_add_rem_control_packet_filter(hw,
11685                                             f->input.mac_addr.addr_bytes,
11686                                             f->input.ether_type,
11687                                             flags, pf->main_vsi->seid,
11688                                             f->queue, 1, &stats, NULL);
11689         }
11690         PMD_DRV_LOG(INFO, "Ethertype filter:"
11691                     " mac_etype_used = %u, etype_used = %u,"
11692                     " mac_etype_free = %u, etype_free = %u",
11693                     stats.mac_etype_used, stats.etype_used,
11694                     stats.mac_etype_free, stats.etype_free);
11695 }
11696
11697 /* Restore tunnel filter */
11698 static void
11699 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11700 {
11701         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11702         struct i40e_vsi *vsi;
11703         struct i40e_pf_vf *vf;
11704         struct i40e_tunnel_filter_list
11705                 *tunnel_list = &pf->tunnel.tunnel_list;
11706         struct i40e_tunnel_filter *f;
11707         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11708         bool big_buffer = 0;
11709
11710         TAILQ_FOREACH(f, tunnel_list, rules) {
11711                 if (!f->is_to_vf)
11712                         vsi = pf->main_vsi;
11713                 else {
11714                         vf = &pf->vfs[f->vf_id];
11715                         vsi = vf->vsi;
11716                 }
11717                 memset(&cld_filter, 0, sizeof(cld_filter));
11718                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11719                         (struct ether_addr *)&cld_filter.element.outer_mac);
11720                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11721                         (struct ether_addr *)&cld_filter.element.inner_mac);
11722                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11723                 cld_filter.element.flags = f->input.flags;
11724                 cld_filter.element.tenant_id = f->input.tenant_id;
11725                 cld_filter.element.queue_number = f->queue;
11726                 rte_memcpy(cld_filter.general_fields,
11727                            f->input.general_fields,
11728                            sizeof(f->input.general_fields));
11729
11730                 if (((f->input.flags &
11731                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11732                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11733                     ((f->input.flags &
11734                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11735                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11736                     ((f->input.flags &
11737                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11738                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11739                         big_buffer = 1;
11740
11741                 if (big_buffer)
11742                         i40e_aq_add_cloud_filters_big_buffer(hw,
11743                                              vsi->seid, &cld_filter, 1);
11744                 else
11745                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11746                                                   &cld_filter.element, 1);
11747         }
11748 }
11749
11750 /* Restore rss filter */
11751 static inline void
11752 i40e_rss_filter_restore(struct i40e_pf *pf)
11753 {
11754         struct i40e_rte_flow_rss_conf *conf =
11755                                         &pf->rss_info;
11756         if (conf->conf.queue_num)
11757                 i40e_config_rss_filter(pf, conf, TRUE);
11758 }
11759
11760 static void
11761 i40e_filter_restore(struct i40e_pf *pf)
11762 {
11763         i40e_ethertype_filter_restore(pf);
11764         i40e_tunnel_filter_restore(pf);
11765         i40e_fdir_filter_restore(pf);
11766         i40e_rss_filter_restore(pf);
11767 }
11768
11769 static bool
11770 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11771 {
11772         if (strcmp(dev->device->driver->name, drv->driver.name))
11773                 return false;
11774
11775         return true;
11776 }
11777
11778 bool
11779 is_i40e_supported(struct rte_eth_dev *dev)
11780 {
11781         return is_device_supported(dev, &rte_i40e_pmd);
11782 }
11783
11784 struct i40e_customized_pctype*
11785 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11786 {
11787         int i;
11788
11789         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11790                 if (pf->customized_pctype[i].index == index)
11791                         return &pf->customized_pctype[i];
11792         }
11793         return NULL;
11794 }
11795
11796 static int
11797 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11798                               uint32_t pkg_size, uint32_t proto_num,
11799                               struct rte_pmd_i40e_proto_info *proto,
11800                               enum rte_pmd_i40e_package_op op)
11801 {
11802         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11803         uint32_t pctype_num;
11804         struct rte_pmd_i40e_ptype_info *pctype;
11805         uint32_t buff_size;
11806         struct i40e_customized_pctype *new_pctype = NULL;
11807         uint8_t proto_id;
11808         uint8_t pctype_value;
11809         char name[64];
11810         uint32_t i, j, n;
11811         int ret;
11812
11813         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11814             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11815                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11816                 return -1;
11817         }
11818
11819         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11820                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11821                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11822         if (ret) {
11823                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11824                 return -1;
11825         }
11826         if (!pctype_num) {
11827                 PMD_DRV_LOG(INFO, "No new pctype added");
11828                 return -1;
11829         }
11830
11831         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11832         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11833         if (!pctype) {
11834                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11835                 return -1;
11836         }
11837         /* get information about new pctype list */
11838         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11839                                         (uint8_t *)pctype, buff_size,
11840                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11841         if (ret) {
11842                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11843                 rte_free(pctype);
11844                 return -1;
11845         }
11846
11847         /* Update customized pctype. */
11848         for (i = 0; i < pctype_num; i++) {
11849                 pctype_value = pctype[i].ptype_id;
11850                 memset(name, 0, sizeof(name));
11851                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11852                         proto_id = pctype[i].protocols[j];
11853                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11854                                 continue;
11855                         for (n = 0; n < proto_num; n++) {
11856                                 if (proto[n].proto_id != proto_id)
11857                                         continue;
11858                                 strcat(name, proto[n].name);
11859                                 strcat(name, "_");
11860                                 break;
11861                         }
11862                 }
11863                 name[strlen(name) - 1] = '\0';
11864                 if (!strcmp(name, "GTPC"))
11865                         new_pctype =
11866                                 i40e_find_customized_pctype(pf,
11867                                                       I40E_CUSTOMIZED_GTPC);
11868                 else if (!strcmp(name, "GTPU_IPV4"))
11869                         new_pctype =
11870                                 i40e_find_customized_pctype(pf,
11871                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11872                 else if (!strcmp(name, "GTPU_IPV6"))
11873                         new_pctype =
11874                                 i40e_find_customized_pctype(pf,
11875                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11876                 else if (!strcmp(name, "GTPU"))
11877                         new_pctype =
11878                                 i40e_find_customized_pctype(pf,
11879                                                       I40E_CUSTOMIZED_GTPU);
11880                 if (new_pctype) {
11881                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11882                                 new_pctype->pctype = pctype_value;
11883                                 new_pctype->valid = true;
11884                         } else {
11885                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11886                                 new_pctype->valid = false;
11887                         }
11888                 }
11889         }
11890
11891         rte_free(pctype);
11892         return 0;
11893 }
11894
11895 static int
11896 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11897                              uint32_t pkg_size, uint32_t proto_num,
11898                              struct rte_pmd_i40e_proto_info *proto,
11899                              enum rte_pmd_i40e_package_op op)
11900 {
11901         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11902         uint16_t port_id = dev->data->port_id;
11903         uint32_t ptype_num;
11904         struct rte_pmd_i40e_ptype_info *ptype;
11905         uint32_t buff_size;
11906         uint8_t proto_id;
11907         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11908         uint32_t i, j, n;
11909         bool in_tunnel;
11910         int ret;
11911
11912         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11913             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11914                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11915                 return -1;
11916         }
11917
11918         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11919                 rte_pmd_i40e_ptype_mapping_reset(port_id);
11920                 return 0;
11921         }
11922
11923         /* get information about new ptype num */
11924         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11925                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11926                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11927         if (ret) {
11928                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11929                 return ret;
11930         }
11931         if (!ptype_num) {
11932                 PMD_DRV_LOG(INFO, "No new ptype added");
11933                 return -1;
11934         }
11935
11936         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11937         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11938         if (!ptype) {
11939                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11940                 return -1;
11941         }
11942
11943         /* get information about new ptype list */
11944         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11945                                         (uint8_t *)ptype, buff_size,
11946                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11947         if (ret) {
11948                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11949                 rte_free(ptype);
11950                 return ret;
11951         }
11952
11953         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11954         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11955         if (!ptype_mapping) {
11956                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11957                 rte_free(ptype);
11958                 return -1;
11959         }
11960
11961         /* Update ptype mapping table. */
11962         for (i = 0; i < ptype_num; i++) {
11963                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11964                 ptype_mapping[i].sw_ptype = 0;
11965                 in_tunnel = false;
11966                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11967                         proto_id = ptype[i].protocols[j];
11968                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11969                                 continue;
11970                         for (n = 0; n < proto_num; n++) {
11971                                 if (proto[n].proto_id != proto_id)
11972                                         continue;
11973                                 memset(name, 0, sizeof(name));
11974                                 strcpy(name, proto[n].name);
11975                                 if (!strncasecmp(name, "PPPOE", 5))
11976                                         ptype_mapping[i].sw_ptype |=
11977                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11978                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11979                                          !in_tunnel) {
11980                                         ptype_mapping[i].sw_ptype |=
11981                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11982                                         ptype_mapping[i].sw_ptype |=
11983                                                 RTE_PTYPE_L4_FRAG;
11984                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11985                                            in_tunnel) {
11986                                         ptype_mapping[i].sw_ptype |=
11987                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11988                                         ptype_mapping[i].sw_ptype |=
11989                                                 RTE_PTYPE_INNER_L4_FRAG;
11990                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
11991                                         ptype_mapping[i].sw_ptype |=
11992                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11993                                         in_tunnel = true;
11994                                 } else if (!strncasecmp(name, "IPV4", 4) &&
11995                                            !in_tunnel)
11996                                         ptype_mapping[i].sw_ptype |=
11997                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11998                                 else if (!strncasecmp(name, "IPV4", 4) &&
11999                                          in_tunnel)
12000                                         ptype_mapping[i].sw_ptype |=
12001                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12002                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12003                                          !in_tunnel) {
12004                                         ptype_mapping[i].sw_ptype |=
12005                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12006                                         ptype_mapping[i].sw_ptype |=
12007                                                 RTE_PTYPE_L4_FRAG;
12008                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12009                                            in_tunnel) {
12010                                         ptype_mapping[i].sw_ptype |=
12011                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12012                                         ptype_mapping[i].sw_ptype |=
12013                                                 RTE_PTYPE_INNER_L4_FRAG;
12014                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12015                                         ptype_mapping[i].sw_ptype |=
12016                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12017                                         in_tunnel = true;
12018                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12019                                            !in_tunnel)
12020                                         ptype_mapping[i].sw_ptype |=
12021                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12022                                 else if (!strncasecmp(name, "IPV6", 4) &&
12023                                          in_tunnel)
12024                                         ptype_mapping[i].sw_ptype |=
12025                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12026                                 else if (!strncasecmp(name, "UDP", 3) &&
12027                                          !in_tunnel)
12028                                         ptype_mapping[i].sw_ptype |=
12029                                                 RTE_PTYPE_L4_UDP;
12030                                 else if (!strncasecmp(name, "UDP", 3) &&
12031                                          in_tunnel)
12032                                         ptype_mapping[i].sw_ptype |=
12033                                                 RTE_PTYPE_INNER_L4_UDP;
12034                                 else if (!strncasecmp(name, "TCP", 3) &&
12035                                          !in_tunnel)
12036                                         ptype_mapping[i].sw_ptype |=
12037                                                 RTE_PTYPE_L4_TCP;
12038                                 else if (!strncasecmp(name, "TCP", 3) &&
12039                                          in_tunnel)
12040                                         ptype_mapping[i].sw_ptype |=
12041                                                 RTE_PTYPE_INNER_L4_TCP;
12042                                 else if (!strncasecmp(name, "SCTP", 4) &&
12043                                          !in_tunnel)
12044                                         ptype_mapping[i].sw_ptype |=
12045                                                 RTE_PTYPE_L4_SCTP;
12046                                 else if (!strncasecmp(name, "SCTP", 4) &&
12047                                          in_tunnel)
12048                                         ptype_mapping[i].sw_ptype |=
12049                                                 RTE_PTYPE_INNER_L4_SCTP;
12050                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12051                                           !strncasecmp(name, "ICMPV6", 6)) &&
12052                                          !in_tunnel)
12053                                         ptype_mapping[i].sw_ptype |=
12054                                                 RTE_PTYPE_L4_ICMP;
12055                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12056                                           !strncasecmp(name, "ICMPV6", 6)) &&
12057                                          in_tunnel)
12058                                         ptype_mapping[i].sw_ptype |=
12059                                                 RTE_PTYPE_INNER_L4_ICMP;
12060                                 else if (!strncasecmp(name, "GTPC", 4)) {
12061                                         ptype_mapping[i].sw_ptype |=
12062                                                 RTE_PTYPE_TUNNEL_GTPC;
12063                                         in_tunnel = true;
12064                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12065                                         ptype_mapping[i].sw_ptype |=
12066                                                 RTE_PTYPE_TUNNEL_GTPU;
12067                                         in_tunnel = true;
12068                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12069                                         ptype_mapping[i].sw_ptype |=
12070                                                 RTE_PTYPE_TUNNEL_GRENAT;
12071                                         in_tunnel = true;
12072                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
12073                                         ptype_mapping[i].sw_ptype |=
12074                                                 RTE_PTYPE_TUNNEL_L2TP;
12075                                         in_tunnel = true;
12076                                 }
12077
12078                                 break;
12079                         }
12080                 }
12081         }
12082
12083         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12084                                                 ptype_num, 0);
12085         if (ret)
12086                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12087
12088         rte_free(ptype_mapping);
12089         rte_free(ptype);
12090         return ret;
12091 }
12092
12093 void
12094 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12095                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12096 {
12097         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12098         uint32_t proto_num;
12099         struct rte_pmd_i40e_proto_info *proto;
12100         uint32_t buff_size;
12101         uint32_t i;
12102         int ret;
12103
12104         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12105             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12106                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12107                 return;
12108         }
12109
12110         /* get information about protocol number */
12111         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12112                                        (uint8_t *)&proto_num, sizeof(proto_num),
12113                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12114         if (ret) {
12115                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12116                 return;
12117         }
12118         if (!proto_num) {
12119                 PMD_DRV_LOG(INFO, "No new protocol added");
12120                 return;
12121         }
12122
12123         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12124         proto = rte_zmalloc("new_proto", buff_size, 0);
12125         if (!proto) {
12126                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12127                 return;
12128         }
12129
12130         /* get information about protocol list */
12131         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12132                                         (uint8_t *)proto, buff_size,
12133                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12134         if (ret) {
12135                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12136                 rte_free(proto);
12137                 return;
12138         }
12139
12140         /* Check if GTP is supported. */
12141         for (i = 0; i < proto_num; i++) {
12142                 if (!strncmp(proto[i].name, "GTP", 3)) {
12143                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12144                                 pf->gtp_support = true;
12145                         else
12146                                 pf->gtp_support = false;
12147                         break;
12148                 }
12149         }
12150
12151         /* Update customized pctype info */
12152         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12153                                             proto_num, proto, op);
12154         if (ret)
12155                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12156
12157         /* Update customized ptype info */
12158         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12159                                            proto_num, proto, op);
12160         if (ret)
12161                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12162
12163         rte_free(proto);
12164 }
12165
12166 /* Create a QinQ cloud filter
12167  *
12168  * The Fortville NIC has limited resources for tunnel filters,
12169  * so we can only reuse existing filters.
12170  *
12171  * In step 1 we define which Field Vector fields can be used for
12172  * filter types.
12173  * As we do not have the inner tag defined as a field,
12174  * we have to define it first, by reusing one of L1 entries.
12175  *
12176  * In step 2 we are replacing one of existing filter types with
12177  * a new one for QinQ.
12178  * As we reusing L1 and replacing L2, some of the default filter
12179  * types will disappear,which depends on L1 and L2 entries we reuse.
12180  *
12181  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12182  *
12183  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12184  *              later when we define the cloud filter.
12185  *      a.      Valid_flags.replace_cloud = 0
12186  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12187  *      c.      New_filter = 0x10
12188  *      d.      TR bit = 0xff (optional, not used here)
12189  *      e.      Buffer – 2 entries:
12190  *              i.      Byte 0 = 8 (outer vlan FV index).
12191  *                      Byte 1 = 0 (rsv)
12192  *                      Byte 2-3 = 0x0fff
12193  *              ii.     Byte 0 = 37 (inner vlan FV index).
12194  *                      Byte 1 =0 (rsv)
12195  *                      Byte 2-3 = 0x0fff
12196  *
12197  * Step 2:
12198  * 2.   Create cloud filter using two L1 filters entries: stag and
12199  *              new filter(outer vlan+ inner vlan)
12200  *      a.      Valid_flags.replace_cloud = 1
12201  *      b.      Old_filter = 1 (instead of outer IP)
12202  *      c.      New_filter = 0x10
12203  *      d.      Buffer – 2 entries:
12204  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12205  *                      Byte 1-3 = 0 (rsv)
12206  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12207  *                      Byte 9-11 = 0 (rsv)
12208  */
12209 static int
12210 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12211 {
12212         int ret = -ENOTSUP;
12213         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12214         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12215         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12216
12217         if (pf->support_multi_driver) {
12218                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12219                 return ret;
12220         }
12221
12222         /* Init */
12223         memset(&filter_replace, 0,
12224                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12225         memset(&filter_replace_buf, 0,
12226                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12227
12228         /* create L1 filter */
12229         filter_replace.old_filter_type =
12230                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12231         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12232         filter_replace.tr_bit = 0;
12233
12234         /* Prepare the buffer, 2 entries */
12235         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12236         filter_replace_buf.data[0] |=
12237                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12238         /* Field Vector 12b mask */
12239         filter_replace_buf.data[2] = 0xff;
12240         filter_replace_buf.data[3] = 0x0f;
12241         filter_replace_buf.data[4] =
12242                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12243         filter_replace_buf.data[4] |=
12244                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12245         /* Field Vector 12b mask */
12246         filter_replace_buf.data[6] = 0xff;
12247         filter_replace_buf.data[7] = 0x0f;
12248         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12249                         &filter_replace_buf);
12250         if (ret != I40E_SUCCESS)
12251                 return ret;
12252         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
12253                     "cloud l1 type is changed from 0x%x to 0x%x",
12254                     filter_replace.old_filter_type,
12255                     filter_replace.new_filter_type);
12256
12257         /* Apply the second L2 cloud filter */
12258         memset(&filter_replace, 0,
12259                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12260         memset(&filter_replace_buf, 0,
12261                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12262
12263         /* create L2 filter, input for L2 filter will be L1 filter  */
12264         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12265         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12266         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12267
12268         /* Prepare the buffer, 2 entries */
12269         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12270         filter_replace_buf.data[0] |=
12271                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12272         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12273         filter_replace_buf.data[4] |=
12274                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12275         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12276                         &filter_replace_buf);
12277         if (!ret) {
12278                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
12279                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
12280                             "cloud filter type is changed from 0x%x to 0x%x",
12281                             filter_replace.old_filter_type,
12282                             filter_replace.new_filter_type);
12283         }
12284         return ret;
12285 }
12286
12287 int
12288 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12289                    const struct rte_flow_action_rss *in)
12290 {
12291         if (in->key_len > RTE_DIM(out->key) ||
12292             in->queue_num > RTE_DIM(out->queue))
12293                 return -EINVAL;
12294         out->conf = (struct rte_flow_action_rss){
12295                 .func = in->func,
12296                 .level = in->level,
12297                 .types = in->types,
12298                 .key_len = in->key_len,
12299                 .queue_num = in->queue_num,
12300                 .key = memcpy(out->key, in->key, in->key_len),
12301                 .queue = memcpy(out->queue, in->queue,
12302                                 sizeof(*in->queue) * in->queue_num),
12303         };
12304         return 0;
12305 }
12306
12307 int
12308 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12309                      const struct rte_flow_action_rss *with)
12310 {
12311         return (comp->func == with->func &&
12312                 comp->level == with->level &&
12313                 comp->types == with->types &&
12314                 comp->key_len == with->key_len &&
12315                 comp->queue_num == with->queue_num &&
12316                 !memcmp(comp->key, with->key, with->key_len) &&
12317                 !memcmp(comp->queue, with->queue,
12318                         sizeof(*with->queue) * with->queue_num));
12319 }
12320
12321 int
12322 i40e_config_rss_filter(struct i40e_pf *pf,
12323                 struct i40e_rte_flow_rss_conf *conf, bool add)
12324 {
12325         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12326         uint32_t i, lut = 0;
12327         uint16_t j, num;
12328         struct rte_eth_rss_conf rss_conf = {
12329                 .rss_key = conf->conf.key_len ?
12330                         (void *)(uintptr_t)conf->conf.key : NULL,
12331                 .rss_key_len = conf->conf.key_len,
12332                 .rss_hf = conf->conf.types,
12333         };
12334         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12335
12336         if (!add) {
12337                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12338                         i40e_pf_disable_rss(pf);
12339                         memset(rss_info, 0,
12340                                 sizeof(struct i40e_rte_flow_rss_conf));
12341                         return 0;
12342                 }
12343                 return -EINVAL;
12344         }
12345
12346         if (rss_info->conf.queue_num)
12347                 return -EINVAL;
12348
12349         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12350          * It's necessary to calculate the actual PF queues that are configured.
12351          */
12352         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12353                 num = i40e_pf_calc_configured_queues_num(pf);
12354         else
12355                 num = pf->dev_data->nb_rx_queues;
12356
12357         num = RTE_MIN(num, conf->conf.queue_num);
12358         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12359                         num);
12360
12361         if (num == 0) {
12362                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12363                 return -ENOTSUP;
12364         }
12365
12366         /* Fill in redirection table */
12367         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12368                 if (j == num)
12369                         j = 0;
12370                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12371                         hw->func_caps.rss_table_entry_width) - 1));
12372                 if ((i & 3) == 3)
12373                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12374         }
12375
12376         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12377                 i40e_pf_disable_rss(pf);
12378                 return 0;
12379         }
12380         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12381                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12382                 /* Random default keys */
12383                 static uint32_t rss_key_default[] = {0x6b793944,
12384                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12385                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12386                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12387
12388                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12389                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12390                                                         sizeof(uint32_t);
12391         }
12392
12393         i40e_hw_rss_hash_set(pf, &rss_conf);
12394
12395         if (i40e_rss_conf_init(rss_info, &conf->conf))
12396                 return -EINVAL;
12397
12398         return 0;
12399 }
12400
12401 RTE_INIT(i40e_init_log);
12402 static void
12403 i40e_init_log(void)
12404 {
12405         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12406         if (i40e_logtype_init >= 0)
12407                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12408         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12409         if (i40e_logtype_driver >= 0)
12410                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12411 }
12412
12413 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12414                               QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12415                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");