drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_eal.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memzone.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memcpy.h>
  24 #include <rte_alarm.h>
  25 #include <rte_dev.h>
  26 #include <rte_eth_ctrl.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "base/i40e_diag.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45
  46 #define I40E_CLEAR_PXE_WAIT_MS     200
  47
  48 /* Maximun number of capability elements */
  49 #define I40E_MAX_CAP_ELE_NUM       128
  50
  51 /* Wait count and interval */
  52 #define I40E_CHK_Q_ENA_COUNT       1000
  53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  54
  55 /* Maximun number of VSI */
  56 #define I40E_MAX_NUM_VSIS          (384UL)
  57
  58 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  59
  60 /* Flow control default timer */
  61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  62
  63 /* Flow control enable fwd bit */
  64 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  65
  66 /* Receive Packet Buffer size */
  67 #define I40E_RXPBSIZE (968 * 1024)
  68
  69 /* Kilobytes shift */
  70 #define I40E_KILOSHIFT 10
  71
  72 /* Flow control default high water */
  73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  74
  75 /* Flow control default low water */
  76 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Receive Average Packet Size in Byte*/
  79 #define I40E_PACKET_AVERAGE_SIZE 128
  80
  81 /* Mask of PF interrupt causes */
  82 #define I40E_PFINT_ICR0_ENA_MASK ( \
  83                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  84                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  85                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  86                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  87                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  92
  93 #define I40E_FLOW_TYPES ( \
  94         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  99         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 104         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 105
 106 /* Additional timesync values. */
 107 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 108 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 109 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 110 #define I40E_PRTTSYN_TSYNENA     0x80000000
 111 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 112 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 113
 114 /**
 115  * Below are values for writing un-exposed registers suggested
 116  * by silicon experts
 117  */
 118 /* Destination MAC address */
 119 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 120 /* Source MAC address */
 121 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 123 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 125 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 126 /* Single VLAN tag in the inner L2 header */
 127 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 128 /* Source IPv4 address */
 129 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 130 /* Destination IPv4 address */
 131 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 132 /* Source IPv4 address for X722 */
 133 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 134 /* Destination IPv4 address for X722 */
 135 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 136 /* IPv4 Protocol for X722 */
 137 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 138 /* IPv4 Time to Live for X722 */
 139 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 140 /* IPv4 Type of Service (TOS) */
 141 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 142 /* IPv4 Protocol */
 143 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 144 /* IPv4 Time to Live */
 145 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 146 /* Source IPv6 address */
 147 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 148 /* Destination IPv6 address */
 149 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 150 /* IPv6 Traffic Class (TC) */
 151 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 152 /* IPv6 Next Header */
 153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 154 /* IPv6 Hop Limit */
 155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 156 /* Source L4 port */
 157 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 158 /* Destination L4 port */
 159 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 160 /* SCTP verification tag */
 161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 164 /* Source port of tunneling UDP */
 165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 166 /* Destination port of tunneling UDP */
 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 168 /* UDP Tunneling ID, NVGRE/GRE key */
 169 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 170 /* Last ether type */
 171 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 172 /* Tunneling outer destination IPv4 address */
 173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 174 /* Tunneling outer destination IPv6 address */
 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 176 /* 1st word of flex payload */
 177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 178 /* 2nd word of flex payload */
 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 180 /* 3rd word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 182 /* 4th word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 184 /* 5th word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 186 /* 6th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 188 /* 7th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 190 /* 8th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 192 /* all 8 words flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 194 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 195
 196 #define I40E_TRANSLATE_INSET 0
 197 #define I40E_TRANSLATE_REG   1
 198
 199 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 200 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 201 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 202 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 204 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 205
 206 /* PCI offset for querying capability */
 207 #define PCI_DEV_CAP_REG            0xA4
 208 /* PCI offset for enabling/disabling Extended Tag */
 209 #define PCI_DEV_CTRL_REG           0xA8
 210 /* Bit mask of Extended Tag capability */
 211 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 212 /* Bit shift of Extended Tag enable/disable */
 213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 214 /* Bit mask of Extended Tag enable/disable */
 215 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 216
 217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 219 static int i40e_dev_configure(struct rte_eth_dev *dev);
 220 static int i40e_dev_start(struct rte_eth_dev *dev);
 221 static void i40e_dev_stop(struct rte_eth_dev *dev);
 222 static void i40e_dev_close(struct rte_eth_dev *dev);
 223 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_stats *stats);
 232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 233                                struct rte_eth_xstat *xstats, unsigned n);
 234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 235                                      struct rte_eth_xstat_name *xstats_names,
 236                                      unsigned limit);
 237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 239                                             uint16_t queue_id,
 240                                             uint8_t stat_idx,
 241                                             uint8_t is_rx);
 242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 243                                 char *fw_version, size_t fw_size);
 244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 245                               struct rte_eth_dev_info *dev_info);
 246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 247                                 uint16_t vlan_id,
 248                                 int on);
 249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 250                               enum rte_vlan_type vlan_type,
 251                               uint16_t tpid);
 252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                                       uint16_t queue,
 255                                       int on);
 256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 260                               struct rte_eth_fc_conf *fc_conf);
 261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 264                                        struct rte_eth_pfc_conf *pfc_conf);
 265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 266                             struct ether_addr *mac_addr,
 267                             uint32_t index,
 268                             uint32_t pool);
 269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 271                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 272                                     uint16_t reta_size);
 273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 274                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 275                                    uint16_t reta_size);
 276
 277 static int i40e_get_cap(struct i40e_hw *hw);
 278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 279 static int i40e_pf_setup(struct i40e_pf *pf);
 280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 284                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 285 static void i40e_stat_update_48(struct i40e_hw *hw,
 286                                uint32_t hireg,
 287                                uint32_t loreg,
 288                                bool offset_loaded,
 289                                uint64_t *offset,
 290                                uint64_t *stat);
 291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 292 static void i40e_dev_interrupt_handler(void *param);
 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 294                                 uint32_t base, uint32_t num);
 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 297                         uint32_t base);
 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 299                         uint16_t num);
 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 301 static int i40e_veb_release(struct i40e_veb *veb);
 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 303                                                 struct i40e_vsi *vsi);
 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 374                                       struct ether_addr *mac_addr);
 375
 376 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 377
 378 static int i40e_ethertype_filter_convert(
 379         const struct rte_eth_ethertype_filter *input,
 380         struct i40e_ethertype_filter *filter);
 381 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 382                                    struct i40e_ethertype_filter *filter);
 383
 384 static int i40e_tunnel_filter_convert(
 385         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 386         struct i40e_tunnel_filter *tunnel_filter);
 387 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 388                                 struct i40e_tunnel_filter *tunnel_filter);
 389 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 390
 391 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 392 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 393 static void i40e_filter_restore(struct i40e_pf *pf);
 394 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 395
 396 int i40e_logtype_init;
 397 int i40e_logtype_driver;
 398
 399 static const struct rte_pci_id pci_id_i40e_map[] = {
 400         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 401         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 402         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 403         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 404         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 420         { .vendor_id = 0, /* sentinel */ },
 421 };
 422
 423 static const struct eth_dev_ops i40e_eth_dev_ops = {
 424         .dev_configure                = i40e_dev_configure,
 425         .dev_start                    = i40e_dev_start,
 426         .dev_stop                     = i40e_dev_stop,
 427         .dev_close                    = i40e_dev_close,
 428         .dev_reset                    = i40e_dev_reset,
 429         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 430         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 431         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 432         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 433         .dev_set_link_up              = i40e_dev_set_link_up,
 434         .dev_set_link_down            = i40e_dev_set_link_down,
 435         .link_update                  = i40e_dev_link_update,
 436         .stats_get                    = i40e_dev_stats_get,
 437         .xstats_get                   = i40e_dev_xstats_get,
 438         .xstats_get_names             = i40e_dev_xstats_get_names,
 439         .stats_reset                  = i40e_dev_stats_reset,
 440         .xstats_reset                 = i40e_dev_stats_reset,
 441         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 442         .fw_version_get               = i40e_fw_version_get,
 443         .dev_infos_get                = i40e_dev_info_get,
 444         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 445         .vlan_filter_set              = i40e_vlan_filter_set,
 446         .vlan_tpid_set                = i40e_vlan_tpid_set,
 447         .vlan_offload_set             = i40e_vlan_offload_set,
 448         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 449         .vlan_pvid_set                = i40e_vlan_pvid_set,
 450         .rx_queue_start               = i40e_dev_rx_queue_start,
 451         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 452         .tx_queue_start               = i40e_dev_tx_queue_start,
 453         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 454         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 455         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 456         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 457         .rx_queue_release             = i40e_dev_rx_queue_release,
 458         .rx_queue_count               = i40e_dev_rx_queue_count,
 459         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 460         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 461         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 462         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 463         .tx_queue_release             = i40e_dev_tx_queue_release,
 464         .dev_led_on                   = i40e_dev_led_on,
 465         .dev_led_off                  = i40e_dev_led_off,
 466         .flow_ctrl_get                = i40e_flow_ctrl_get,
 467         .flow_ctrl_set                = i40e_flow_ctrl_set,
 468         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 469         .mac_addr_add                 = i40e_macaddr_add,
 470         .mac_addr_remove              = i40e_macaddr_remove,
 471         .reta_update                  = i40e_dev_rss_reta_update,
 472         .reta_query                   = i40e_dev_rss_reta_query,
 473         .rss_hash_update              = i40e_dev_rss_hash_update,
 474         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 475         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 476         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 477         .filter_ctrl                  = i40e_dev_filter_ctrl,
 478         .rxq_info_get                 = i40e_rxq_info_get,
 479         .txq_info_get                 = i40e_txq_info_get,
 480         .mirror_rule_set              = i40e_mirror_rule_set,
 481         .mirror_rule_reset            = i40e_mirror_rule_reset,
 482         .timesync_enable              = i40e_timesync_enable,
 483         .timesync_disable             = i40e_timesync_disable,
 484         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 485         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 486         .get_dcb_info                 = i40e_dev_get_dcb_info,
 487         .timesync_adjust_time         = i40e_timesync_adjust_time,
 488         .timesync_read_time           = i40e_timesync_read_time,
 489         .timesync_write_time          = i40e_timesync_write_time,
 490         .get_reg                      = i40e_get_regs,
 491         .get_eeprom_length            = i40e_get_eeprom_length,
 492         .get_eeprom                   = i40e_get_eeprom,
 493         .mac_addr_set                 = i40e_set_default_mac_addr,
 494         .mtu_set                      = i40e_dev_mtu_set,
 495         .tm_ops_get                   = i40e_tm_ops_get,
 496 };
 497
 498 /* store statistics names and its offset in stats structure */
 499 struct rte_i40e_xstats_name_off {
 500         char name[RTE_ETH_XSTATS_NAME_SIZE];
 501         unsigned offset;
 502 };
 503
 504 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 505         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 506         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 507         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 508         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 509         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 510                 rx_unknown_protocol)},
 511         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 512         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 513         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 514         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 515 };
 516
 517 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 518                 sizeof(rte_i40e_stats_strings[0]))
 519
 520 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 521         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 522                 tx_dropped_link_down)},
 523         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 524         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 525                 illegal_bytes)},
 526         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 527         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 528                 mac_local_faults)},
 529         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 530                 mac_remote_faults)},
 531         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 532                 rx_length_errors)},
 533         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 534         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 535         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 536         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 537         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 538         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 539                 rx_size_127)},
 540         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 541                 rx_size_255)},
 542         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 543                 rx_size_511)},
 544         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 545                 rx_size_1023)},
 546         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 547                 rx_size_1522)},
 548         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 549                 rx_size_big)},
 550         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 551                 rx_undersize)},
 552         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 553                 rx_oversize)},
 554         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 555                 mac_short_packet_dropped)},
 556         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 557                 rx_fragments)},
 558         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 559         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 560         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 561                 tx_size_127)},
 562         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 563                 tx_size_255)},
 564         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 565                 tx_size_511)},
 566         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 567                 tx_size_1023)},
 568         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 569                 tx_size_1522)},
 570         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 571                 tx_size_big)},
 572         {"rx_flow_director_atr_match_packets",
 573                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 574         {"rx_flow_director_sb_match_packets",
 575                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 576         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 577                 tx_lpi_status)},
 578         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 579                 rx_lpi_status)},
 580         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 581                 tx_lpi_count)},
 582         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 583                 rx_lpi_count)},
 584 };
 585
 586 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 587                 sizeof(rte_i40e_hw_port_strings[0]))
 588
 589 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 590         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 591                 priority_xon_rx)},
 592         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 593                 priority_xoff_rx)},
 594 };
 595
 596 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 597                 sizeof(rte_i40e_rxq_prio_strings[0]))
 598
 599 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 600         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 601                 priority_xon_tx)},
 602         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 603                 priority_xoff_tx)},
 604         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 605                 priority_xon_2_xoff)},
 606 };
 607
 608 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 609                 sizeof(rte_i40e_txq_prio_strings[0]))
 610
 611 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 612         struct rte_pci_device *pci_dev)
 613 {
 614         return rte_eth_dev_pci_generic_probe(pci_dev,
 615                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 616 }
 617
 618 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 619 {
 620         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 621 }
 622
 623 static struct rte_pci_driver rte_i40e_pmd = {
 624         .id_table = pci_id_i40e_map,
 625         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 626                      RTE_PCI_DRV_IOVA_AS_VA,
 627         .probe = eth_i40e_pci_probe,
 628         .remove = eth_i40e_pci_remove,
 629 };
 630
 631 static inline int
 632 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 633                                      struct rte_eth_link *link)
 634 {
 635         struct rte_eth_link *dst = link;
 636         struct rte_eth_link *src = &(dev->data->dev_link);
 637
 638         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 639                                         *(uint64_t *)src) == 0)
 640                 return -1;
 641
 642         return 0;
 643 }
 644
 645 static inline int
 646 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 647                                       struct rte_eth_link *link)
 648 {
 649         struct rte_eth_link *dst = &(dev->data->dev_link);
 650         struct rte_eth_link *src = link;
 651
 652         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 653                                         *(uint64_t *)src) == 0)
 654                 return -1;
 655
 656         return 0;
 657 }
 658
 659 static inline void
 660 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
 661 {
 662         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 663         PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
 664                     "with value 0x%08x",
 665                     reg_addr, reg_val);
 666 }
 667
 668 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 669 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 670 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 671
 672 #ifndef I40E_GLQF_ORT
 673 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 674 #endif
 675 #ifndef I40E_GLQF_PIT
 676 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 677 #endif
 678 #ifndef I40E_GLQF_L3_MAP
 679 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 680 #endif
 681
 682 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 683 {
 684         /*
 685          * Initialize registers for parsing packet type of QinQ
 686          * This should be removed from code once proper
 687          * configuration API is added to avoid configuration conflicts
 688          * between ports of the same device.
 689          */
 690         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 691         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 692         i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
 693 }
 694
 695 static inline void i40e_config_automask(struct i40e_pf *pf)
 696 {
 697         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 698         uint32_t val;
 699
 700         /* INTENA flag is not auto-cleared for interrupt */
 701         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 702         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 703                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 704
 705         /* If support multi-driver, PF will use INT0. */
 706         if (!pf->support_multi_driver)
 707                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 708
 709         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 710 }
 711
 712 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 713
 714 /*
 715  * Add a ethertype filter to drop all flow control frames transmitted
 716  * from VSIs.
 717 */
 718 static void
 719 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 720 {
 721         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 722         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 723                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 724                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 725         int ret;
 726
 727         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 728                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 729                                 pf->main_vsi_seid, 0,
 730                                 TRUE, NULL, NULL);
 731         if (ret)
 732                 PMD_INIT_LOG(ERR,
 733                         "Failed to add filter to drop flow control frames from VSIs.");
 734 }
 735
 736 static int
 737 floating_veb_list_handler(__rte_unused const char *key,
 738                           const char *floating_veb_value,
 739                           void *opaque)
 740 {
 741         int idx = 0;
 742         unsigned int count = 0;
 743         char *end = NULL;
 744         int min, max;
 745         bool *vf_floating_veb = opaque;
 746
 747         while (isblank(*floating_veb_value))
 748                 floating_veb_value++;
 749
 750         /* Reset floating VEB configuration for VFs */
 751         for (idx = 0; idx < I40E_MAX_VF; idx++)
 752                 vf_floating_veb[idx] = false;
 753
 754         min = I40E_MAX_VF;
 755         do {
 756                 while (isblank(*floating_veb_value))
 757                         floating_veb_value++;
 758                 if (*floating_veb_value == '\0')
 759                         return -1;
 760                 errno = 0;
 761                 idx = strtoul(floating_veb_value, &end, 10);
 762                 if (errno || end == NULL)
 763                         return -1;
 764                 while (isblank(*end))
 765                         end++;
 766                 if (*end == '-') {
 767                         min = idx;
 768                 } else if ((*end == ';') || (*end == '\0')) {
 769                         max = idx;
 770                         if (min == I40E_MAX_VF)
 771                                 min = idx;
 772                         if (max >= I40E_MAX_VF)
 773                                 max = I40E_MAX_VF - 1;
 774                         for (idx = min; idx <= max; idx++) {
 775                                 vf_floating_veb[idx] = true;
 776                                 count++;
 777                         }
 778                         min = I40E_MAX_VF;
 779                 } else {
 780                         return -1;
 781                 }
 782                 floating_veb_value = end + 1;
 783         } while (*end != '\0');
 784
 785         if (count == 0)
 786                 return -1;
 787
 788         return 0;
 789 }
 790
 791 static void
 792 config_vf_floating_veb(struct rte_devargs *devargs,
 793                        uint16_t floating_veb,
 794                        bool *vf_floating_veb)
 795 {
 796         struct rte_kvargs *kvlist;
 797         int i;
 798         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 799
 800         if (!floating_veb)
 801                 return;
 802         /* All the VFs attach to the floating VEB by default
 803          * when the floating VEB is enabled.
 804          */
 805         for (i = 0; i < I40E_MAX_VF; i++)
 806                 vf_floating_veb[i] = true;
 807
 808         if (devargs == NULL)
 809                 return;
 810
 811         kvlist = rte_kvargs_parse(devargs->args, NULL);
 812         if (kvlist == NULL)
 813                 return;
 814
 815         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 816                 rte_kvargs_free(kvlist);
 817                 return;
 818         }
 819         /* When the floating_veb_list parameter exists, all the VFs
 820          * will attach to the legacy VEB firstly, then configure VFs
 821          * to the floating VEB according to the floating_veb_list.
 822          */
 823         if (rte_kvargs_process(kvlist, floating_veb_list,
 824                                floating_veb_list_handler,
 825                                vf_floating_veb) < 0) {
 826                 rte_kvargs_free(kvlist);
 827                 return;
 828         }
 829         rte_kvargs_free(kvlist);
 830 }
 831
 832 static int
 833 i40e_check_floating_handler(__rte_unused const char *key,
 834                             const char *value,
 835                             __rte_unused void *opaque)
 836 {
 837         if (strcmp(value, "1"))
 838                 return -1;
 839
 840         return 0;
 841 }
 842
 843 static int
 844 is_floating_veb_supported(struct rte_devargs *devargs)
 845 {
 846         struct rte_kvargs *kvlist;
 847         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 848
 849         if (devargs == NULL)
 850                 return 0;
 851
 852         kvlist = rte_kvargs_parse(devargs->args, NULL);
 853         if (kvlist == NULL)
 854                 return 0;
 855
 856         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 857                 rte_kvargs_free(kvlist);
 858                 return 0;
 859         }
 860         /* Floating VEB is enabled when there's key-value:
 861          * enable_floating_veb=1
 862          */
 863         if (rte_kvargs_process(kvlist, floating_veb_key,
 864                                i40e_check_floating_handler, NULL) < 0) {
 865                 rte_kvargs_free(kvlist);
 866                 return 0;
 867         }
 868         rte_kvargs_free(kvlist);
 869
 870         return 1;
 871 }
 872
 873 static void
 874 config_floating_veb(struct rte_eth_dev *dev)
 875 {
 876         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 877         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 878         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 879
 880         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 881
 882         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 883                 pf->floating_veb =
 884                         is_floating_veb_supported(pci_dev->device.devargs);
 885                 config_vf_floating_veb(pci_dev->device.devargs,
 886                                        pf->floating_veb,
 887                                        pf->floating_veb_list);
 888         } else {
 889                 pf->floating_veb = false;
 890         }
 891 }
 892
 893 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 894 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 895
 896 static int
 897 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 898 {
 899         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 900         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 901         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 902         int ret;
 903
 904         struct rte_hash_parameters ethertype_hash_params = {
 905                 .name = ethertype_hash_name,
 906                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 907                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 908                 .hash_func = rte_hash_crc,
 909                 .hash_func_init_val = 0,
 910                 .socket_id = rte_socket_id(),
 911         };
 912
 913         /* Initialize ethertype filter rule list and hash */
 914         TAILQ_INIT(&ethertype_rule->ethertype_list);
 915         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 916                  "ethertype_%s", dev->device->name);
 917         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 918         if (!ethertype_rule->hash_table) {
 919                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 920                 return -EINVAL;
 921         }
 922         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 923                                        sizeof(struct i40e_ethertype_filter *) *
 924                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 925                                        0);
 926         if (!ethertype_rule->hash_map) {
 927                 PMD_INIT_LOG(ERR,
 928                              "Failed to allocate memory for ethertype hash map!");
 929                 ret = -ENOMEM;
 930                 goto err_ethertype_hash_map_alloc;
 931         }
 932
 933         return 0;
 934
 935 err_ethertype_hash_map_alloc:
 936         rte_hash_free(ethertype_rule->hash_table);
 937
 938         return ret;
 939 }
 940
 941 static int
 942 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 943 {
 944         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 945         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 946         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 947         int ret;
 948
 949         struct rte_hash_parameters tunnel_hash_params = {
 950                 .name = tunnel_hash_name,
 951                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 952                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 953                 .hash_func = rte_hash_crc,
 954                 .hash_func_init_val = 0,
 955                 .socket_id = rte_socket_id(),
 956         };
 957
 958         /* Initialize tunnel filter rule list and hash */
 959         TAILQ_INIT(&tunnel_rule->tunnel_list);
 960         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 961                  "tunnel_%s", dev->device->name);
 962         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 963         if (!tunnel_rule->hash_table) {
 964                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 965                 return -EINVAL;
 966         }
 967         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 968                                     sizeof(struct i40e_tunnel_filter *) *
 969                                     I40E_MAX_TUNNEL_FILTER_NUM,
 970                                     0);
 971         if (!tunnel_rule->hash_map) {
 972                 PMD_INIT_LOG(ERR,
 973                              "Failed to allocate memory for tunnel hash map!");
 974                 ret = -ENOMEM;
 975                 goto err_tunnel_hash_map_alloc;
 976         }
 977
 978         return 0;
 979
 980 err_tunnel_hash_map_alloc:
 981         rte_hash_free(tunnel_rule->hash_table);
 982
 983         return ret;
 984 }
 985
 986 static int
 987 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 988 {
 989         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 990         struct i40e_fdir_info *fdir_info = &pf->fdir;
 991         char fdir_hash_name[RTE_HASH_NAMESIZE];
 992         int ret;
 993
 994         struct rte_hash_parameters fdir_hash_params = {
 995                 .name = fdir_hash_name,
 996                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 997                 .key_len = sizeof(struct i40e_fdir_input),
 998                 .hash_func = rte_hash_crc,
 999                 .hash_func_init_val = 0,
1000                 .socket_id = rte_socket_id(),
1001         };
1002
1003         /* Initialize flow director filter rule list and hash */
1004         TAILQ_INIT(&fdir_info->fdir_list);
1005         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1006                  "fdir_%s", dev->device->name);
1007         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1008         if (!fdir_info->hash_table) {
1009                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1010                 return -EINVAL;
1011         }
1012         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1013                                           sizeof(struct i40e_fdir_filter *) *
1014                                           I40E_MAX_FDIR_FILTER_NUM,
1015                                           0);
1016         if (!fdir_info->hash_map) {
1017                 PMD_INIT_LOG(ERR,
1018                              "Failed to allocate memory for fdir hash map!");
1019                 ret = -ENOMEM;
1020                 goto err_fdir_hash_map_alloc;
1021         }
1022         return 0;
1023
1024 err_fdir_hash_map_alloc:
1025         rte_hash_free(fdir_info->hash_table);
1026
1027         return ret;
1028 }
1029
1030 static void
1031 i40e_init_customized_info(struct i40e_pf *pf)
1032 {
1033         int i;
1034
1035         /* Initialize customized pctype */
1036         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1037                 pf->customized_pctype[i].index = i;
1038                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1039                 pf->customized_pctype[i].valid = false;
1040         }
1041
1042         pf->gtp_support = false;
1043 }
1044
1045 void
1046 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1047 {
1048         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1049         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1050         struct i40e_queue_regions *info = &pf->queue_region;
1051         uint16_t i;
1052
1053         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1054                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1055
1056         memset(info, 0, sizeof(struct i40e_queue_regions));
1057 }
1058
1059 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
1060
1061 static int
1062 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1063                                const char *value,
1064                                void *opaque)
1065 {
1066         struct i40e_pf *pf;
1067         unsigned long support_multi_driver;
1068         char *end;
1069
1070         pf = (struct i40e_pf *)opaque;
1071
1072         errno = 0;
1073         support_multi_driver = strtoul(value, &end, 10);
1074         if (errno != 0 || end == value || *end != 0) {
1075                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1076                 return -(EINVAL);
1077         }
1078
1079         if (support_multi_driver == 1 || support_multi_driver == 0)
1080                 pf->support_multi_driver = (bool)support_multi_driver;
1081         else
1082                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1083                             "enable global configuration by default."
1084                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1085         return 0;
1086 }
1087
1088 static int
1089 i40e_support_multi_driver(struct rte_eth_dev *dev)
1090 {
1091         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1092         static const char *const valid_keys[] = {
1093                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1094         struct rte_kvargs *kvlist;
1095
1096         /* Enable global configuration by default */
1097         pf->support_multi_driver = false;
1098
1099         if (!dev->device->devargs)
1100                 return 0;
1101
1102         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1103         if (!kvlist)
1104                 return -EINVAL;
1105
1106         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1107                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1108                             "the first invalid or last valid one is used !",
1109                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1110
1111         rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1112                            i40e_parse_multi_drv_handler, pf);
1113         rte_kvargs_free(kvlist);
1114         return 0;
1115 }
1116
1117 static int
1118 eth_i40e_dev_init(struct rte_eth_dev *dev)
1119 {
1120         struct rte_pci_device *pci_dev;
1121         struct rte_intr_handle *intr_handle;
1122         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1123         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1124         struct i40e_vsi *vsi;
1125         int ret;
1126         uint32_t len;
1127         uint8_t aq_fail = 0;
1128
1129         PMD_INIT_FUNC_TRACE();
1130
1131         dev->dev_ops = &i40e_eth_dev_ops;
1132         dev->rx_pkt_burst = i40e_recv_pkts;
1133         dev->tx_pkt_burst = i40e_xmit_pkts;
1134         dev->tx_pkt_prepare = i40e_prep_pkts;
1135
1136         /* for secondary processes, we don't initialise any further as primary
1137          * has already done this work. Only check we don't need a different
1138          * RX function */
1139         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1140                 i40e_set_rx_function(dev);
1141                 i40e_set_tx_function(dev);
1142                 return 0;
1143         }
1144         i40e_set_default_ptype_table(dev);
1145         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1146         intr_handle = &pci_dev->intr_handle;
1147
1148         rte_eth_copy_pci_info(dev, pci_dev);
1149
1150         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1151         pf->adapter->eth_dev = dev;
1152         pf->dev_data = dev->data;
1153
1154         hw->back = I40E_PF_TO_ADAPTER(pf);
1155         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1156         if (!hw->hw_addr) {
1157                 PMD_INIT_LOG(ERR,
1158                         "Hardware is not available, as address is NULL");
1159                 return -ENODEV;
1160         }
1161
1162         hw->vendor_id = pci_dev->id.vendor_id;
1163         hw->device_id = pci_dev->id.device_id;
1164         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1165         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1166         hw->bus.device = pci_dev->addr.devid;
1167         hw->bus.func = pci_dev->addr.function;
1168         hw->adapter_stopped = 0;
1169
1170         /* Check if need to support multi-driver */
1171         i40e_support_multi_driver(dev);
1172
1173         /* Make sure all is clean before doing PF reset */
1174         i40e_clear_hw(hw);
1175
1176         /* Initialize the hardware */
1177         i40e_hw_init(dev);
1178
1179         /* Reset here to make sure all is clean for each PF */
1180         ret = i40e_pf_reset(hw);
1181         if (ret) {
1182                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1183                 return ret;
1184         }
1185
1186         /* Initialize the shared code (base driver) */
1187         ret = i40e_init_shared_code(hw);
1188         if (ret) {
1189                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1190                 return ret;
1191         }
1192
1193         i40e_config_automask(pf);
1194
1195         i40e_set_default_pctype_table(dev);
1196
1197         /*
1198          * To work around the NVM issue, initialize registers
1199          * for packet type of QinQ by software.
1200          * It should be removed once issues are fixed in NVM.
1201          */
1202         if (!pf->support_multi_driver)
1203                 i40e_GLQF_reg_init(hw);
1204
1205         /* Initialize the input set for filters (hash and fd) to default value */
1206         i40e_filter_input_set_init(pf);
1207
1208         /* Initialize the parameters for adminq */
1209         i40e_init_adminq_parameter(hw);
1210         ret = i40e_init_adminq(hw);
1211         if (ret != I40E_SUCCESS) {
1212                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1213                 return -EIO;
1214         }
1215         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1216                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1217                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1218                      ((hw->nvm.version >> 12) & 0xf),
1219                      ((hw->nvm.version >> 4) & 0xff),
1220                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1221
1222         /* initialise the L3_MAP register */
1223         if (!pf->support_multi_driver) {
1224                 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1225                                                    0x00000028,  NULL);
1226                 if (ret)
1227                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1228                                      ret);
1229                 PMD_INIT_LOG(DEBUG,
1230                              "Global register 0x%08x is changed with 0x28",
1231                              I40E_GLQF_L3_MAP(40));
1232                 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1233         }
1234
1235         /* Need the special FW version to support floating VEB */
1236         config_floating_veb(dev);
1237         /* Clear PXE mode */
1238         i40e_clear_pxe_mode(hw);
1239         i40e_dev_sync_phy_type(hw);
1240
1241         /*
1242          * On X710, performance number is far from the expectation on recent
1243          * firmware versions. The fix for this issue may not be integrated in
1244          * the following firmware version. So the workaround in software driver
1245          * is needed. It needs to modify the initial values of 3 internal only
1246          * registers. Note that the workaround can be removed when it is fixed
1247          * in firmware in the future.
1248          */
1249         i40e_configure_registers(hw);
1250
1251         /* Get hw capabilities */
1252         ret = i40e_get_cap(hw);
1253         if (ret != I40E_SUCCESS) {
1254                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1255                 goto err_get_capabilities;
1256         }
1257
1258         /* Initialize parameters for PF */
1259         ret = i40e_pf_parameter_init(dev);
1260         if (ret != 0) {
1261                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1262                 goto err_parameter_init;
1263         }
1264
1265         /* Initialize the queue management */
1266         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1267         if (ret < 0) {
1268                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1269                 goto err_qp_pool_init;
1270         }
1271         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1272                                 hw->func_caps.num_msix_vectors - 1);
1273         if (ret < 0) {
1274                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1275                 goto err_msix_pool_init;
1276         }
1277
1278         /* Initialize lan hmc */
1279         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1280                                 hw->func_caps.num_rx_qp, 0, 0);
1281         if (ret != I40E_SUCCESS) {
1282                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1283                 goto err_init_lan_hmc;
1284         }
1285
1286         /* Configure lan hmc */
1287         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1288         if (ret != I40E_SUCCESS) {
1289                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1290                 goto err_configure_lan_hmc;
1291         }
1292
1293         /* Get and check the mac address */
1294         i40e_get_mac_addr(hw, hw->mac.addr);
1295         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1296                 PMD_INIT_LOG(ERR, "mac address is not valid");
1297                 ret = -EIO;
1298                 goto err_get_mac_addr;
1299         }
1300         /* Copy the permanent MAC address */
1301         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1302                         (struct ether_addr *) hw->mac.perm_addr);
1303
1304         /* Disable flow control */
1305         hw->fc.requested_mode = I40E_FC_NONE;
1306         i40e_set_fc(hw, &aq_fail, TRUE);
1307
1308         /* Set the global registers with default ether type value */
1309         if (!pf->support_multi_driver) {
1310                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1311                                          ETHER_TYPE_VLAN);
1312                 if (ret != I40E_SUCCESS) {
1313                         PMD_INIT_LOG(ERR,
1314                                      "Failed to set the default outer "
1315                                      "VLAN ether type");
1316                         goto err_setup_pf_switch;
1317                 }
1318         }
1319
1320         /* PF setup, which includes VSI setup */
1321         ret = i40e_pf_setup(pf);
1322         if (ret) {
1323                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1324                 goto err_setup_pf_switch;
1325         }
1326
1327         /* reset all stats of the device, including pf and main vsi */
1328         i40e_dev_stats_reset(dev);
1329
1330         vsi = pf->main_vsi;
1331
1332         /* Disable double vlan by default */
1333         i40e_vsi_config_double_vlan(vsi, FALSE);
1334
1335         /* Disable S-TAG identification when floating_veb is disabled */
1336         if (!pf->floating_veb) {
1337                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1338                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1339                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1340                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1341                 }
1342         }
1343
1344         if (!vsi->max_macaddrs)
1345                 len = ETHER_ADDR_LEN;
1346         else
1347                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1348
1349         /* Should be after VSI initialized */
1350         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1351         if (!dev->data->mac_addrs) {
1352                 PMD_INIT_LOG(ERR,
1353                         "Failed to allocated memory for storing mac address");
1354                 goto err_mac_alloc;
1355         }
1356         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1357                                         &dev->data->mac_addrs[0]);
1358
1359         /* Init dcb to sw mode by default */
1360         ret = i40e_dcb_init_configure(dev, TRUE);
1361         if (ret != I40E_SUCCESS) {
1362                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1363                 pf->flags &= ~I40E_FLAG_DCB;
1364         }
1365         /* Update HW struct after DCB configuration */
1366         i40e_get_cap(hw);
1367
1368         /* initialize pf host driver to setup SRIOV resource if applicable */
1369         i40e_pf_host_init(dev);
1370
1371         /* register callback func to eal lib */
1372         rte_intr_callback_register(intr_handle,
1373                                    i40e_dev_interrupt_handler, dev);
1374
1375         /* configure and enable device interrupt */
1376         i40e_pf_config_irq0(hw, TRUE);
1377         i40e_pf_enable_irq0(hw);
1378
1379         /* enable uio intr after callback register */
1380         rte_intr_enable(intr_handle);
1381
1382         /* By default disable flexible payload in global configuration */
1383         if (!pf->support_multi_driver)
1384                 i40e_flex_payload_reg_set_default(hw);
1385
1386         /*
1387          * Add an ethertype filter to drop all flow control frames transmitted
1388          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1389          * frames to wire.
1390          */
1391         i40e_add_tx_flow_control_drop_filter(pf);
1392
1393         /* Set the max frame size to 0x2600 by default,
1394          * in case other drivers changed the default value.
1395          */
1396         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1397
1398         /* initialize mirror rule list */
1399         TAILQ_INIT(&pf->mirror_list);
1400
1401         /* initialize Traffic Manager configuration */
1402         i40e_tm_conf_init(dev);
1403
1404         /* Initialize customized information */
1405         i40e_init_customized_info(pf);
1406
1407         ret = i40e_init_ethtype_filter_list(dev);
1408         if (ret < 0)
1409                 goto err_init_ethtype_filter_list;
1410         ret = i40e_init_tunnel_filter_list(dev);
1411         if (ret < 0)
1412                 goto err_init_tunnel_filter_list;
1413         ret = i40e_init_fdir_filter_list(dev);
1414         if (ret < 0)
1415                 goto err_init_fdir_filter_list;
1416
1417         /* initialize queue region configuration */
1418         i40e_init_queue_region_conf(dev);
1419
1420         /* initialize rss configuration from rte_flow */
1421         memset(&pf->rss_info, 0,
1422                 sizeof(struct i40e_rte_flow_rss_conf));
1423
1424         return 0;
1425
1426 err_init_fdir_filter_list:
1427         rte_free(pf->tunnel.hash_table);
1428         rte_free(pf->tunnel.hash_map);
1429 err_init_tunnel_filter_list:
1430         rte_free(pf->ethertype.hash_table);
1431         rte_free(pf->ethertype.hash_map);
1432 err_init_ethtype_filter_list:
1433         rte_free(dev->data->mac_addrs);
1434 err_mac_alloc:
1435         i40e_vsi_release(pf->main_vsi);
1436 err_setup_pf_switch:
1437 err_get_mac_addr:
1438 err_configure_lan_hmc:
1439         (void)i40e_shutdown_lan_hmc(hw);
1440 err_init_lan_hmc:
1441         i40e_res_pool_destroy(&pf->msix_pool);
1442 err_msix_pool_init:
1443         i40e_res_pool_destroy(&pf->qp_pool);
1444 err_qp_pool_init:
1445 err_parameter_init:
1446 err_get_capabilities:
1447         (void)i40e_shutdown_adminq(hw);
1448
1449         return ret;
1450 }
1451
1452 static void
1453 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1454 {
1455         struct i40e_ethertype_filter *p_ethertype;
1456         struct i40e_ethertype_rule *ethertype_rule;
1457
1458         ethertype_rule = &pf->ethertype;
1459         /* Remove all ethertype filter rules and hash */
1460         if (ethertype_rule->hash_map)
1461                 rte_free(ethertype_rule->hash_map);
1462         if (ethertype_rule->hash_table)
1463                 rte_hash_free(ethertype_rule->hash_table);
1464
1465         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1466                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1467                              p_ethertype, rules);
1468                 rte_free(p_ethertype);
1469         }
1470 }
1471
1472 static void
1473 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1474 {
1475         struct i40e_tunnel_filter *p_tunnel;
1476         struct i40e_tunnel_rule *tunnel_rule;
1477
1478         tunnel_rule = &pf->tunnel;
1479         /* Remove all tunnel director rules and hash */
1480         if (tunnel_rule->hash_map)
1481                 rte_free(tunnel_rule->hash_map);
1482         if (tunnel_rule->hash_table)
1483                 rte_hash_free(tunnel_rule->hash_table);
1484
1485         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1486                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1487                 rte_free(p_tunnel);
1488         }
1489 }
1490
1491 static void
1492 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1493 {
1494         struct i40e_fdir_filter *p_fdir;
1495         struct i40e_fdir_info *fdir_info;
1496
1497         fdir_info = &pf->fdir;
1498         /* Remove all flow director rules and hash */
1499         if (fdir_info->hash_map)
1500                 rte_free(fdir_info->hash_map);
1501         if (fdir_info->hash_table)
1502                 rte_hash_free(fdir_info->hash_table);
1503
1504         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1505                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1506                 rte_free(p_fdir);
1507         }
1508 }
1509
1510 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1511 {
1512         /*
1513          * Disable by default flexible payload
1514          * for corresponding L2/L3/L4 layers.
1515          */
1516         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1517         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1518         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1519         i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
1520 }
1521
1522 static int
1523 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1524 {
1525         struct i40e_pf *pf;
1526         struct rte_pci_device *pci_dev;
1527         struct rte_intr_handle *intr_handle;
1528         struct i40e_hw *hw;
1529         struct i40e_filter_control_settings settings;
1530         struct rte_flow *p_flow;
1531         int ret;
1532         uint8_t aq_fail = 0;
1533
1534         PMD_INIT_FUNC_TRACE();
1535
1536         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1537                 return 0;
1538
1539         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1540         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1541         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1542         intr_handle = &pci_dev->intr_handle;
1543
1544         if (hw->adapter_stopped == 0)
1545                 i40e_dev_close(dev);
1546
1547         dev->dev_ops = NULL;
1548         dev->rx_pkt_burst = NULL;
1549         dev->tx_pkt_burst = NULL;
1550
1551         /* Clear PXE mode */
1552         i40e_clear_pxe_mode(hw);
1553
1554         /* Unconfigure filter control */
1555         memset(&settings, 0, sizeof(settings));
1556         ret = i40e_set_filter_control(hw, &settings);
1557         if (ret)
1558                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1559                                         ret);
1560
1561         /* Disable flow control */
1562         hw->fc.requested_mode = I40E_FC_NONE;
1563         i40e_set_fc(hw, &aq_fail, TRUE);
1564
1565         /* uninitialize pf host driver */
1566         i40e_pf_host_uninit(dev);
1567
1568         rte_free(dev->data->mac_addrs);
1569         dev->data->mac_addrs = NULL;
1570
1571         /* disable uio intr before callback unregister */
1572         rte_intr_disable(intr_handle);
1573
1574         /* register callback func to eal lib */
1575         rte_intr_callback_unregister(intr_handle,
1576                                      i40e_dev_interrupt_handler, dev);
1577
1578         i40e_rm_ethtype_filter_list(pf);
1579         i40e_rm_tunnel_filter_list(pf);
1580         i40e_rm_fdir_filter_list(pf);
1581
1582         /* Remove all flows */
1583         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1584                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1585                 rte_free(p_flow);
1586         }
1587
1588         /* Remove all Traffic Manager configuration */
1589         i40e_tm_conf_uninit(dev);
1590
1591         return 0;
1592 }
1593
1594 static int
1595 i40e_dev_configure(struct rte_eth_dev *dev)
1596 {
1597         struct i40e_adapter *ad =
1598                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1599         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1600         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1601         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1602         int i, ret;
1603
1604         ret = i40e_dev_sync_phy_type(hw);
1605         if (ret)
1606                 return ret;
1607
1608         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1609          * bulk allocation or vector Rx preconditions we will reset it.
1610          */
1611         ad->rx_bulk_alloc_allowed = true;
1612         ad->rx_vec_allowed = true;
1613         ad->tx_simple_allowed = true;
1614         ad->tx_vec_allowed = true;
1615
1616         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1617                 ret = i40e_fdir_setup(pf);
1618                 if (ret != I40E_SUCCESS) {
1619                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1620                         return -ENOTSUP;
1621                 }
1622                 ret = i40e_fdir_configure(dev);
1623                 if (ret < 0) {
1624                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1625                         goto err;
1626                 }
1627         } else
1628                 i40e_fdir_teardown(pf);
1629
1630         ret = i40e_dev_init_vlan(dev);
1631         if (ret < 0)
1632                 goto err;
1633
1634         /* VMDQ setup.
1635          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1636          *  RSS setting have different requirements.
1637          *  General PMD driver call sequence are NIC init, configure,
1638          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1639          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1640          *  applicable. So, VMDQ setting has to be done before
1641          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1642          *  For RSS setting, it will try to calculate actual configured RX queue
1643          *  number, which will be available after rx_queue_setup(). dev_start()
1644          *  function is good to place RSS setup.
1645          */
1646         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1647                 ret = i40e_vmdq_setup(dev);
1648                 if (ret)
1649                         goto err;
1650         }
1651
1652         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1653                 ret = i40e_dcb_setup(dev);
1654                 if (ret) {
1655                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1656                         goto err_dcb;
1657                 }
1658         }
1659
1660         TAILQ_INIT(&pf->flow_list);
1661
1662         return 0;
1663
1664 err_dcb:
1665         /* need to release vmdq resource if exists */
1666         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1667                 i40e_vsi_release(pf->vmdq[i].vsi);
1668                 pf->vmdq[i].vsi = NULL;
1669         }
1670         rte_free(pf->vmdq);
1671         pf->vmdq = NULL;
1672 err:
1673         /* need to release fdir resource if exists */
1674         i40e_fdir_teardown(pf);
1675         return ret;
1676 }
1677
1678 void
1679 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1680 {
1681         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1682         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1683         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1684         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1685         uint16_t msix_vect = vsi->msix_intr;
1686         uint16_t i;
1687
1688         for (i = 0; i < vsi->nb_qps; i++) {
1689                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1690                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1691                 rte_wmb();
1692         }
1693
1694         if (vsi->type != I40E_VSI_SRIOV) {
1695                 if (!rte_intr_allow_others(intr_handle)) {
1696                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1697                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1698                         I40E_WRITE_REG(hw,
1699                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1700                                        0);
1701                 } else {
1702                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1703                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1704                         I40E_WRITE_REG(hw,
1705                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1706                                                        msix_vect - 1), 0);
1707                 }
1708         } else {
1709                 uint32_t reg;
1710                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1711                         vsi->user_param + (msix_vect - 1);
1712
1713                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1714                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1715         }
1716         I40E_WRITE_FLUSH(hw);
1717 }
1718
1719 static void
1720 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1721                        int base_queue, int nb_queue,
1722                        uint16_t itr_idx)
1723 {
1724         int i;
1725         uint32_t val;
1726         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1727         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1728
1729         /* Bind all RX queues to allocated MSIX interrupt */
1730         for (i = 0; i < nb_queue; i++) {
1731                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1732                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1733                         ((base_queue + i + 1) <<
1734                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1735                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1736                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1737
1738                 if (i == nb_queue - 1)
1739                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1740                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1741         }
1742
1743         /* Write first RX queue to Link list register as the head element */
1744         if (vsi->type != I40E_VSI_SRIOV) {
1745                 uint16_t interval =
1746                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,
1747                                                pf->support_multi_driver);
1748
1749                 if (msix_vect == I40E_MISC_VEC_ID) {
1750                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1751                                        (base_queue <<
1752                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1753                                        (0x0 <<
1754                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1755                         I40E_WRITE_REG(hw,
1756                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1757                                        interval);
1758                 } else {
1759                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1760                                        (base_queue <<
1761                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1762                                        (0x0 <<
1763                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1764                         I40E_WRITE_REG(hw,
1765                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1766                                                        msix_vect - 1),
1767                                        interval);
1768                 }
1769         } else {
1770                 uint32_t reg;
1771
1772                 if (msix_vect == I40E_MISC_VEC_ID) {
1773                         I40E_WRITE_REG(hw,
1774                                        I40E_VPINT_LNKLST0(vsi->user_param),
1775                                        (base_queue <<
1776                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1777                                        (0x0 <<
1778                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1779                 } else {
1780                         /* num_msix_vectors_vf needs to minus irq0 */
1781                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1782                                 vsi->user_param + (msix_vect - 1);
1783
1784                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1785                                        (base_queue <<
1786                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1787                                        (0x0 <<
1788                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1789                 }
1790         }
1791
1792         I40E_WRITE_FLUSH(hw);
1793 }
1794
1795 void
1796 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1797 {
1798         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1799         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1800         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1801         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1802         uint16_t msix_vect = vsi->msix_intr;
1803         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1804         uint16_t queue_idx = 0;
1805         int record = 0;
1806         int i;
1807
1808         for (i = 0; i < vsi->nb_qps; i++) {
1809                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1810                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1811         }
1812
1813         /* VF bind interrupt */
1814         if (vsi->type == I40E_VSI_SRIOV) {
1815                 __vsi_queues_bind_intr(vsi, msix_vect,
1816                                        vsi->base_queue, vsi->nb_qps,
1817                                        itr_idx);
1818                 return;
1819         }
1820
1821         /* PF & VMDq bind interrupt */
1822         if (rte_intr_dp_is_en(intr_handle)) {
1823                 if (vsi->type == I40E_VSI_MAIN) {
1824                         queue_idx = 0;
1825                         record = 1;
1826                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1827                         struct i40e_vsi *main_vsi =
1828                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1829                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1830                         record = 1;
1831                 }
1832         }
1833
1834         for (i = 0; i < vsi->nb_used_qps; i++) {
1835                 if (nb_msix <= 1) {
1836                         if (!rte_intr_allow_others(intr_handle))
1837                                 /* allow to share MISC_VEC_ID */
1838                                 msix_vect = I40E_MISC_VEC_ID;
1839
1840                         /* no enough msix_vect, map all to one */
1841                         __vsi_queues_bind_intr(vsi, msix_vect,
1842                                                vsi->base_queue + i,
1843                                                vsi->nb_used_qps - i,
1844                                                itr_idx);
1845                         for (; !!record && i < vsi->nb_used_qps; i++)
1846                                 intr_handle->intr_vec[queue_idx + i] =
1847                                         msix_vect;
1848                         break;
1849                 }
1850                 /* 1:1 queue/msix_vect mapping */
1851                 __vsi_queues_bind_intr(vsi, msix_vect,
1852                                        vsi->base_queue + i, 1,
1853                                        itr_idx);
1854                 if (!!record)
1855                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1856
1857                 msix_vect++;
1858                 nb_msix--;
1859         }
1860 }
1861
1862 static void
1863 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1864 {
1865         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1866         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1867         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1868         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1869         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1870         uint16_t msix_intr, i;
1871
1872         if (rte_intr_allow_others(intr_handle) || !pf->support_multi_driver)
1873                 for (i = 0; i < vsi->nb_msix; i++) {
1874                         msix_intr = vsi->msix_intr + i;
1875                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1876                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1877                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1878                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1879                 }
1880         else
1881                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1882                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1883                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1884                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1885
1886         I40E_WRITE_FLUSH(hw);
1887 }
1888
1889 static void
1890 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1891 {
1892         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1893         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1894         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1895         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1896         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1897         uint16_t msix_intr, i;
1898
1899         if (rte_intr_allow_others(intr_handle) || !pf->support_multi_driver)
1900                 for (i = 0; i < vsi->nb_msix; i++) {
1901                         msix_intr = vsi->msix_intr + i;
1902                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1903                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1904                 }
1905         else
1906                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1907                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1908
1909         I40E_WRITE_FLUSH(hw);
1910 }
1911
1912 static inline uint8_t
1913 i40e_parse_link_speeds(uint16_t link_speeds)
1914 {
1915         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1916
1917         if (link_speeds & ETH_LINK_SPEED_40G)
1918                 link_speed |= I40E_LINK_SPEED_40GB;
1919         if (link_speeds & ETH_LINK_SPEED_25G)
1920                 link_speed |= I40E_LINK_SPEED_25GB;
1921         if (link_speeds & ETH_LINK_SPEED_20G)
1922                 link_speed |= I40E_LINK_SPEED_20GB;
1923         if (link_speeds & ETH_LINK_SPEED_10G)
1924                 link_speed |= I40E_LINK_SPEED_10GB;
1925         if (link_speeds & ETH_LINK_SPEED_1G)
1926                 link_speed |= I40E_LINK_SPEED_1GB;
1927         if (link_speeds & ETH_LINK_SPEED_100M)
1928                 link_speed |= I40E_LINK_SPEED_100MB;
1929
1930         return link_speed;
1931 }
1932
1933 static int
1934 i40e_phy_conf_link(struct i40e_hw *hw,
1935                    uint8_t abilities,
1936                    uint8_t force_speed,
1937                    bool is_up)
1938 {
1939         enum i40e_status_code status;
1940         struct i40e_aq_get_phy_abilities_resp phy_ab;
1941         struct i40e_aq_set_phy_config phy_conf;
1942         enum i40e_aq_phy_type cnt;
1943         uint32_t phy_type_mask = 0;
1944
1945         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1946                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1947                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1948                         I40E_AQ_PHY_FLAG_LOW_POWER;
1949         const uint8_t advt = I40E_LINK_SPEED_40GB |
1950                         I40E_LINK_SPEED_25GB |
1951                         I40E_LINK_SPEED_10GB |
1952                         I40E_LINK_SPEED_1GB |
1953                         I40E_LINK_SPEED_100MB;
1954         int ret = -ENOTSUP;
1955
1956
1957         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1958                                               NULL);
1959         if (status)
1960                 return ret;
1961
1962         /* If link already up, no need to set up again */
1963         if (is_up && phy_ab.phy_type != 0)
1964                 return I40E_SUCCESS;
1965
1966         memset(&phy_conf, 0, sizeof(phy_conf));
1967
1968         /* bits 0-2 use the values from get_phy_abilities_resp */
1969         abilities &= ~mask;
1970         abilities |= phy_ab.abilities & mask;
1971
1972         /* update ablities and speed */
1973         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1974                 phy_conf.link_speed = advt;
1975         else
1976                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1977
1978         phy_conf.abilities = abilities;
1979
1980
1981
1982         /* To enable link, phy_type mask needs to include each type */
1983         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1984                 phy_type_mask |= 1 << cnt;
1985
1986         /* use get_phy_abilities_resp value for the rest */
1987         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1988         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1989                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1990                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1991         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1992         phy_conf.eee_capability = phy_ab.eee_capability;
1993         phy_conf.eeer = phy_ab.eeer_val;
1994         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1995
1996         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1997                     phy_ab.abilities, phy_ab.link_speed);
1998         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1999                     phy_conf.abilities, phy_conf.link_speed);
2000
2001         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2002         if (status)
2003                 return ret;
2004
2005         return I40E_SUCCESS;
2006 }
2007
2008 static int
2009 i40e_apply_link_speed(struct rte_eth_dev *dev)
2010 {
2011         uint8_t speed;
2012         uint8_t abilities = 0;
2013         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2014         struct rte_eth_conf *conf = &dev->data->dev_conf;
2015
2016         speed = i40e_parse_link_speeds(conf->link_speeds);
2017         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2018         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2019                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2020         abilities |= I40E_AQ_PHY_LINK_ENABLED;
2021
2022         return i40e_phy_conf_link(hw, abilities, speed, true);
2023 }
2024
2025 static int
2026 i40e_dev_start(struct rte_eth_dev *dev)
2027 {
2028         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2029         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2030         struct i40e_vsi *main_vsi = pf->main_vsi;
2031         int ret, i;
2032         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2033         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2034         uint32_t intr_vector = 0;
2035         struct i40e_vsi *vsi;
2036
2037         hw->adapter_stopped = 0;
2038
2039         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2040                 PMD_INIT_LOG(ERR,
2041                 "Invalid link_speeds for port %u, autonegotiation disabled",
2042                               dev->data->port_id);
2043                 return -EINVAL;
2044         }
2045
2046         rte_intr_disable(intr_handle);
2047
2048         if ((rte_intr_cap_multiple(intr_handle) ||
2049              !RTE_ETH_DEV_SRIOV(dev).active) &&
2050             dev->data->dev_conf.intr_conf.rxq != 0) {
2051                 intr_vector = dev->data->nb_rx_queues;
2052                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2053                 if (ret)
2054                         return ret;
2055         }
2056
2057         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2058                 intr_handle->intr_vec =
2059                         rte_zmalloc("intr_vec",
2060                                     dev->data->nb_rx_queues * sizeof(int),
2061                                     0);
2062                 if (!intr_handle->intr_vec) {
2063                         PMD_INIT_LOG(ERR,
2064                                 "Failed to allocate %d rx_queues intr_vec",
2065                                 dev->data->nb_rx_queues);
2066                         return -ENOMEM;
2067                 }
2068         }
2069
2070         /* Initialize VSI */
2071         ret = i40e_dev_rxtx_init(pf);
2072         if (ret != I40E_SUCCESS) {
2073                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2074                 goto err_up;
2075         }
2076
2077         /* Map queues with MSIX interrupt */
2078         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2079                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2080         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2081         i40e_vsi_enable_queues_intr(main_vsi);
2082
2083         /* Map VMDQ VSI queues with MSIX interrupt */
2084         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2085                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2086                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2087                                           I40E_ITR_INDEX_DEFAULT);
2088                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2089         }
2090
2091         /* enable FDIR MSIX interrupt */
2092         if (pf->fdir.fdir_vsi) {
2093                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2094                                           I40E_ITR_INDEX_NONE);
2095                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2096         }
2097
2098         /* Enable all queues which have been configured */
2099         ret = i40e_dev_switch_queues(pf, TRUE);
2100
2101         if (ret != I40E_SUCCESS) {
2102                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2103                 goto err_up;
2104         }
2105
2106         /* Enable receiving broadcast packets */
2107         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2108         if (ret != I40E_SUCCESS)
2109                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2110
2111         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2112                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2113                                                 true, NULL);
2114                 if (ret != I40E_SUCCESS)
2115                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2116         }
2117
2118         /* Enable the VLAN promiscuous mode. */
2119         if (pf->vfs) {
2120                 for (i = 0; i < pf->vf_num; i++) {
2121                         vsi = pf->vfs[i].vsi;
2122                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2123                                                      true, NULL);
2124                 }
2125         }
2126
2127         /* Enable mac loopback mode */
2128         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2129             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2130                 ret = i40e_diag_set_loopback(hw, dev->data->dev_conf.lpbk_mode);
2131                 if (ret != I40E_SUCCESS) {
2132                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2133                         goto err_up;
2134                 }
2135         }
2136
2137         /* Apply link configure */
2138         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2139                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2140                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2141                                 ETH_LINK_SPEED_40G)) {
2142                 PMD_DRV_LOG(ERR, "Invalid link setting");
2143                 goto err_up;
2144         }
2145         ret = i40e_apply_link_speed(dev);
2146         if (I40E_SUCCESS != ret) {
2147                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2148                 goto err_up;
2149         }
2150
2151         if (!rte_intr_allow_others(intr_handle)) {
2152                 rte_intr_callback_unregister(intr_handle,
2153                                              i40e_dev_interrupt_handler,
2154                                              (void *)dev);
2155                 /* configure and enable device interrupt */
2156                 i40e_pf_config_irq0(hw, FALSE);
2157                 i40e_pf_enable_irq0(hw);
2158
2159                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2160                         PMD_INIT_LOG(INFO,
2161                                 "lsc won't enable because of no intr multiplex");
2162         } else {
2163                 ret = i40e_aq_set_phy_int_mask(hw,
2164                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2165                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2166                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2167                 if (ret != I40E_SUCCESS)
2168                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2169
2170                 /* Call get_link_info aq commond to enable/disable LSE */
2171                 i40e_dev_link_update(dev, 0);
2172         }
2173
2174         /* enable uio intr after callback register */
2175         rte_intr_enable(intr_handle);
2176
2177         i40e_filter_restore(pf);
2178
2179         if (pf->tm_conf.root && !pf->tm_conf.committed)
2180                 PMD_DRV_LOG(WARNING,
2181                             "please call hierarchy_commit() "
2182                             "before starting the port");
2183
2184         return I40E_SUCCESS;
2185
2186 err_up:
2187         i40e_dev_switch_queues(pf, FALSE);
2188         i40e_dev_clear_queues(dev);
2189
2190         return ret;
2191 }
2192
2193 static void
2194 i40e_dev_stop(struct rte_eth_dev *dev)
2195 {
2196         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2197         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2198         struct i40e_vsi *main_vsi = pf->main_vsi;
2199         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2200         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2201         int i;
2202
2203         if (hw->adapter_stopped == 1)
2204                 return;
2205         /* Disable all queues */
2206         i40e_dev_switch_queues(pf, FALSE);
2207
2208         /* un-map queues with interrupt registers */
2209         i40e_vsi_disable_queues_intr(main_vsi);
2210         i40e_vsi_queues_unbind_intr(main_vsi);
2211
2212         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2213                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2214                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2215         }
2216
2217         if (pf->fdir.fdir_vsi) {
2218                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2219                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2220         }
2221         /* Clear all queues and release memory */
2222         i40e_dev_clear_queues(dev);
2223
2224         /* Set link down */
2225         i40e_dev_set_link_down(dev);
2226
2227         if (!rte_intr_allow_others(intr_handle))
2228                 /* resume to the default handler */
2229                 rte_intr_callback_register(intr_handle,
2230                                            i40e_dev_interrupt_handler,
2231                                            (void *)dev);
2232
2233         /* Clean datapath event and queue/vec mapping */
2234         rte_intr_efd_disable(intr_handle);
2235         if (intr_handle->intr_vec) {
2236                 rte_free(intr_handle->intr_vec);
2237                 intr_handle->intr_vec = NULL;
2238         }
2239
2240         /* reset hierarchy commit */
2241         pf->tm_conf.committed = false;
2242
2243         hw->adapter_stopped = 1;
2244 }
2245
2246 static void
2247 i40e_dev_close(struct rte_eth_dev *dev)
2248 {
2249         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2250         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2251         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2252         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2253         struct i40e_mirror_rule *p_mirror;
2254         uint32_t reg;
2255         int i;
2256         int ret;
2257
2258         PMD_INIT_FUNC_TRACE();
2259
2260         i40e_dev_stop(dev);
2261
2262         /* Remove all mirror rules */
2263         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2264                 ret = i40e_aq_del_mirror_rule(hw,
2265                                               pf->main_vsi->veb->seid,
2266                                               p_mirror->rule_type,
2267                                               p_mirror->entries,
2268                                               p_mirror->num_entries,
2269                                               p_mirror->id);
2270                 if (ret < 0)
2271                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2272                                     "status = %d, aq_err = %d.", ret,
2273                                     hw->aq.asq_last_status);
2274
2275                 /* remove mirror software resource anyway */
2276                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2277                 rte_free(p_mirror);
2278                 pf->nb_mirror_rule--;
2279         }
2280
2281         i40e_dev_free_queues(dev);
2282
2283         /* Disable interrupt */
2284         i40e_pf_disable_irq0(hw);
2285         rte_intr_disable(intr_handle);
2286
2287         /* shutdown and destroy the HMC */
2288         i40e_shutdown_lan_hmc(hw);
2289
2290         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2291                 i40e_vsi_release(pf->vmdq[i].vsi);
2292                 pf->vmdq[i].vsi = NULL;
2293         }
2294         rte_free(pf->vmdq);
2295         pf->vmdq = NULL;
2296
2297         /* release all the existing VSIs and VEBs */
2298         i40e_fdir_teardown(pf);
2299         i40e_vsi_release(pf->main_vsi);
2300
2301         /* shutdown the adminq */
2302         i40e_aq_queue_shutdown(hw, true);
2303         i40e_shutdown_adminq(hw);
2304
2305         i40e_res_pool_destroy(&pf->qp_pool);
2306         i40e_res_pool_destroy(&pf->msix_pool);
2307
2308         /* Disable flexible payload in global configuration */
2309         if (!pf->support_multi_driver)
2310                 i40e_flex_payload_reg_set_default(hw);
2311
2312         /* force a PF reset to clean anything leftover */
2313         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2314         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2315                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2316         I40E_WRITE_FLUSH(hw);
2317 }
2318
2319 /*
2320  * Reset PF device only to re-initialize resources in PMD layer
2321  */
2322 static int
2323 i40e_dev_reset(struct rte_eth_dev *dev)
2324 {
2325         int ret;
2326
2327         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2328          * its VF to make them align with it. The detailed notification
2329          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2330          * To avoid unexpected behavior in VF, currently reset of PF with
2331          * SR-IOV activation is not supported. It might be supported later.
2332          */
2333         if (dev->data->sriov.active)
2334                 return -ENOTSUP;
2335
2336         ret = eth_i40e_dev_uninit(dev);
2337         if (ret)
2338                 return ret;
2339
2340         ret = eth_i40e_dev_init(dev);
2341
2342         return ret;
2343 }
2344
2345 static void
2346 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2347 {
2348         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2349         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2350         struct i40e_vsi *vsi = pf->main_vsi;
2351         int status;
2352
2353         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2354                                                      true, NULL, true);
2355         if (status != I40E_SUCCESS)
2356                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2357
2358         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2359                                                         TRUE, NULL);
2360         if (status != I40E_SUCCESS)
2361                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2362
2363 }
2364
2365 static void
2366 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2367 {
2368         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2369         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2370         struct i40e_vsi *vsi = pf->main_vsi;
2371         int status;
2372
2373         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2374                                                      false, NULL, true);
2375         if (status != I40E_SUCCESS)
2376                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2377
2378         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2379                                                         false, NULL);
2380         if (status != I40E_SUCCESS)
2381                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2382 }
2383
2384 static void
2385 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2386 {
2387         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2388         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389         struct i40e_vsi *vsi = pf->main_vsi;
2390         int ret;
2391
2392         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2393         if (ret != I40E_SUCCESS)
2394                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2395 }
2396
2397 static void
2398 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2399 {
2400         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2401         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2402         struct i40e_vsi *vsi = pf->main_vsi;
2403         int ret;
2404
2405         if (dev->data->promiscuous == 1)
2406                 return; /* must remain in all_multicast mode */
2407
2408         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2409                                 vsi->seid, FALSE, NULL);
2410         if (ret != I40E_SUCCESS)
2411                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2412 }
2413
2414 /*
2415  * Set device link up.
2416  */
2417 static int
2418 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2419 {
2420         /* re-apply link speed setting */
2421         return i40e_apply_link_speed(dev);
2422 }
2423
2424 /*
2425  * Set device link down.
2426  */
2427 static int
2428 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2429 {
2430         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2431         uint8_t abilities = 0;
2432         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2433
2434         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2435         return i40e_phy_conf_link(hw, abilities, speed, false);
2436 }
2437
2438 int
2439 i40e_dev_link_update(struct rte_eth_dev *dev,
2440                      int wait_to_complete)
2441 {
2442 #define CHECK_INTERVAL 100  /* 100ms */
2443 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2444         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2445         struct i40e_link_status link_status;
2446         struct rte_eth_link link, old;
2447         int status;
2448         unsigned rep_cnt = MAX_REPEAT_TIME;
2449         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2450
2451         memset(&link, 0, sizeof(link));
2452         memset(&old, 0, sizeof(old));
2453         memset(&link_status, 0, sizeof(link_status));
2454         rte_i40e_dev_atomic_read_link_status(dev, &old);
2455
2456         do {
2457                 /* Get link status information from hardware */
2458                 status = i40e_aq_get_link_info(hw, enable_lse,
2459                                                 &link_status, NULL);
2460                 if (status != I40E_SUCCESS) {
2461                         link.link_speed = ETH_SPEED_NUM_100M;
2462                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2463                         PMD_DRV_LOG(ERR, "Failed to get link info");
2464                         goto out;
2465                 }
2466
2467                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2468                 if (!wait_to_complete || link.link_status)
2469                         break;
2470
2471                 rte_delay_ms(CHECK_INTERVAL);
2472         } while (--rep_cnt);
2473
2474         if (!link.link_status)
2475                 goto out;
2476
2477         /* i40e uses full duplex only */
2478         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2479
2480         /* Parse the link status */
2481         switch (link_status.link_speed) {
2482         case I40E_LINK_SPEED_100MB:
2483                 link.link_speed = ETH_SPEED_NUM_100M;
2484                 break;
2485         case I40E_LINK_SPEED_1GB:
2486                 link.link_speed = ETH_SPEED_NUM_1G;
2487                 break;
2488         case I40E_LINK_SPEED_10GB:
2489                 link.link_speed = ETH_SPEED_NUM_10G;
2490                 break;
2491         case I40E_LINK_SPEED_20GB:
2492                 link.link_speed = ETH_SPEED_NUM_20G;
2493                 break;
2494         case I40E_LINK_SPEED_25GB:
2495                 link.link_speed = ETH_SPEED_NUM_25G;
2496                 break;
2497         case I40E_LINK_SPEED_40GB:
2498                 link.link_speed = ETH_SPEED_NUM_40G;
2499                 break;
2500         default:
2501                 link.link_speed = ETH_SPEED_NUM_100M;
2502                 break;
2503         }
2504
2505         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2506                         ETH_LINK_SPEED_FIXED);
2507
2508 out:
2509         rte_i40e_dev_atomic_write_link_status(dev, &link);
2510         if (link.link_status == old.link_status)
2511                 return -1;
2512
2513         i40e_notify_all_vfs_link_status(dev);
2514
2515         return 0;
2516 }
2517
2518 /* Get all the statistics of a VSI */
2519 void
2520 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2521 {
2522         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2523         struct i40e_eth_stats *nes = &vsi->eth_stats;
2524         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2525         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2526
2527         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2528                             vsi->offset_loaded, &oes->rx_bytes,
2529                             &nes->rx_bytes);
2530         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2531                             vsi->offset_loaded, &oes->rx_unicast,
2532                             &nes->rx_unicast);
2533         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2534                             vsi->offset_loaded, &oes->rx_multicast,
2535                             &nes->rx_multicast);
2536         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2537                             vsi->offset_loaded, &oes->rx_broadcast,
2538                             &nes->rx_broadcast);
2539         /* exclude CRC bytes */
2540         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2541                 nes->rx_broadcast) * ETHER_CRC_LEN;
2542
2543         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2544                             &oes->rx_discards, &nes->rx_discards);
2545         /* GLV_REPC not supported */
2546         /* GLV_RMPC not supported */
2547         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2548                             &oes->rx_unknown_protocol,
2549                             &nes->rx_unknown_protocol);
2550         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2551                             vsi->offset_loaded, &oes->tx_bytes,
2552                             &nes->tx_bytes);
2553         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2554                             vsi->offset_loaded, &oes->tx_unicast,
2555                             &nes->tx_unicast);
2556         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2557                             vsi->offset_loaded, &oes->tx_multicast,
2558                             &nes->tx_multicast);
2559         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2560                             vsi->offset_loaded,  &oes->tx_broadcast,
2561                             &nes->tx_broadcast);
2562         /* GLV_TDPC not supported */
2563         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2564                             &oes->tx_errors, &nes->tx_errors);
2565         vsi->offset_loaded = true;
2566
2567         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2568                     vsi->vsi_id);
2569         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2570         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2571         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2572         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2573         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2574         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2575                     nes->rx_unknown_protocol);
2576         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2577         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2578         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2579         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2580         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2581         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2582         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2583                     vsi->vsi_id);
2584 }
2585
2586 static void
2587 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2588 {
2589         unsigned int i;
2590         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2591         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2592
2593         /* Get rx/tx bytes of internal transfer packets */
2594         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2595                         I40E_GLV_GORCL(hw->port),
2596                         pf->offset_loaded,
2597                         &pf->internal_stats_offset.rx_bytes,
2598                         &pf->internal_stats.rx_bytes);
2599
2600         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2601                         I40E_GLV_GOTCL(hw->port),
2602                         pf->offset_loaded,
2603                         &pf->internal_stats_offset.tx_bytes,
2604                         &pf->internal_stats.tx_bytes);
2605         /* Get total internal rx packet count */
2606         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2607                             I40E_GLV_UPRCL(hw->port),
2608                             pf->offset_loaded,
2609                             &pf->internal_stats_offset.rx_unicast,
2610                             &pf->internal_stats.rx_unicast);
2611         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2612                             I40E_GLV_MPRCL(hw->port),
2613                             pf->offset_loaded,
2614                             &pf->internal_stats_offset.rx_multicast,
2615                             &pf->internal_stats.rx_multicast);
2616         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2617                             I40E_GLV_BPRCL(hw->port),
2618                             pf->offset_loaded,
2619                             &pf->internal_stats_offset.rx_broadcast,
2620                             &pf->internal_stats.rx_broadcast);
2621         /* Get total internal tx packet count */
2622         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2623                             I40E_GLV_UPTCL(hw->port),
2624                             pf->offset_loaded,
2625                             &pf->internal_stats_offset.tx_unicast,
2626                             &pf->internal_stats.tx_unicast);
2627         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2628                             I40E_GLV_MPTCL(hw->port),
2629                             pf->offset_loaded,
2630                             &pf->internal_stats_offset.tx_multicast,
2631                             &pf->internal_stats.tx_multicast);
2632         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2633                             I40E_GLV_BPTCL(hw->port),
2634                             pf->offset_loaded,
2635                             &pf->internal_stats_offset.tx_broadcast,
2636                             &pf->internal_stats.tx_broadcast);
2637
2638         /* exclude CRC size */
2639         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2640                 pf->internal_stats.rx_multicast +
2641                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2642
2643         /* Get statistics of struct i40e_eth_stats */
2644         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2645                             I40E_GLPRT_GORCL(hw->port),
2646                             pf->offset_loaded, &os->eth.rx_bytes,
2647                             &ns->eth.rx_bytes);
2648         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2649                             I40E_GLPRT_UPRCL(hw->port),
2650                             pf->offset_loaded, &os->eth.rx_unicast,
2651                             &ns->eth.rx_unicast);
2652         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2653                             I40E_GLPRT_MPRCL(hw->port),
2654                             pf->offset_loaded, &os->eth.rx_multicast,
2655                             &ns->eth.rx_multicast);
2656         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2657                             I40E_GLPRT_BPRCL(hw->port),
2658                             pf->offset_loaded, &os->eth.rx_broadcast,
2659                             &ns->eth.rx_broadcast);
2660         /* Workaround: CRC size should not be included in byte statistics,
2661          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2662          */
2663         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2664                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2665
2666         /* exclude internal rx bytes
2667          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2668          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2669          * value.
2670          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2671          */
2672         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2673                 ns->eth.rx_bytes = 0;
2674         else
2675                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2676
2677         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2678                 ns->eth.rx_unicast = 0;
2679         else
2680                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2681
2682         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2683                 ns->eth.rx_multicast = 0;
2684         else
2685                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2686
2687         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2688                 ns->eth.rx_broadcast = 0;
2689         else
2690                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2691
2692         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2693                             pf->offset_loaded, &os->eth.rx_discards,
2694                             &ns->eth.rx_discards);
2695         /* GLPRT_REPC not supported */
2696         /* GLPRT_RMPC not supported */
2697         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2698                             pf->offset_loaded,
2699                             &os->eth.rx_unknown_protocol,
2700                             &ns->eth.rx_unknown_protocol);
2701         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2702                             I40E_GLPRT_GOTCL(hw->port),
2703                             pf->offset_loaded, &os->eth.tx_bytes,
2704                             &ns->eth.tx_bytes);
2705         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2706                             I40E_GLPRT_UPTCL(hw->port),
2707                             pf->offset_loaded, &os->eth.tx_unicast,
2708                             &ns->eth.tx_unicast);
2709         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2710                             I40E_GLPRT_MPTCL(hw->port),
2711                             pf->offset_loaded, &os->eth.tx_multicast,
2712                             &ns->eth.tx_multicast);
2713         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2714                             I40E_GLPRT_BPTCL(hw->port),
2715                             pf->offset_loaded, &os->eth.tx_broadcast,
2716                             &ns->eth.tx_broadcast);
2717         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2718                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2719
2720         /* exclude internal tx bytes
2721          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2722          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2723          * value.
2724          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2725          */
2726         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2727                 ns->eth.tx_bytes = 0;
2728         else
2729                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2730
2731         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2732                 ns->eth.tx_unicast = 0;
2733         else
2734                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2735
2736         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2737                 ns->eth.tx_multicast = 0;
2738         else
2739                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2740
2741         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2742                 ns->eth.tx_broadcast = 0;
2743         else
2744                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2745
2746         /* GLPRT_TEPC not supported */
2747
2748         /* additional port specific stats */
2749         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2750                             pf->offset_loaded, &os->tx_dropped_link_down,
2751                             &ns->tx_dropped_link_down);
2752         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2753                             pf->offset_loaded, &os->crc_errors,
2754                             &ns->crc_errors);
2755         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2756                             pf->offset_loaded, &os->illegal_bytes,
2757                             &ns->illegal_bytes);
2758         /* GLPRT_ERRBC not supported */
2759         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2760                             pf->offset_loaded, &os->mac_local_faults,
2761                             &ns->mac_local_faults);
2762         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2763                             pf->offset_loaded, &os->mac_remote_faults,
2764                             &ns->mac_remote_faults);
2765         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2766                             pf->offset_loaded, &os->rx_length_errors,
2767                             &ns->rx_length_errors);
2768         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2769                             pf->offset_loaded, &os->link_xon_rx,
2770                             &ns->link_xon_rx);
2771         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2772                             pf->offset_loaded, &os->link_xoff_rx,
2773                             &ns->link_xoff_rx);
2774         for (i = 0; i < 8; i++) {
2775                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2776                                     pf->offset_loaded,
2777                                     &os->priority_xon_rx[i],
2778                                     &ns->priority_xon_rx[i]);
2779                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2780                                     pf->offset_loaded,
2781                                     &os->priority_xoff_rx[i],
2782                                     &ns->priority_xoff_rx[i]);
2783         }
2784         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2785                             pf->offset_loaded, &os->link_xon_tx,
2786                             &ns->link_xon_tx);
2787         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2788                             pf->offset_loaded, &os->link_xoff_tx,
2789                             &ns->link_xoff_tx);
2790         for (i = 0; i < 8; i++) {
2791                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2792                                     pf->offset_loaded,
2793                                     &os->priority_xon_tx[i],
2794                                     &ns->priority_xon_tx[i]);
2795                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2796                                     pf->offset_loaded,
2797                                     &os->priority_xoff_tx[i],
2798                                     &ns->priority_xoff_tx[i]);
2799                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2800                                     pf->offset_loaded,
2801                                     &os->priority_xon_2_xoff[i],
2802                                     &ns->priority_xon_2_xoff[i]);
2803         }
2804         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2805                             I40E_GLPRT_PRC64L(hw->port),
2806                             pf->offset_loaded, &os->rx_size_64,
2807                             &ns->rx_size_64);
2808         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2809                             I40E_GLPRT_PRC127L(hw->port),
2810                             pf->offset_loaded, &os->rx_size_127,
2811                             &ns->rx_size_127);
2812         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2813                             I40E_GLPRT_PRC255L(hw->port),
2814                             pf->offset_loaded, &os->rx_size_255,
2815                             &ns->rx_size_255);
2816         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2817                             I40E_GLPRT_PRC511L(hw->port),
2818                             pf->offset_loaded, &os->rx_size_511,
2819                             &ns->rx_size_511);
2820         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2821                             I40E_GLPRT_PRC1023L(hw->port),
2822                             pf->offset_loaded, &os->rx_size_1023,
2823                             &ns->rx_size_1023);
2824         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2825                             I40E_GLPRT_PRC1522L(hw->port),
2826                             pf->offset_loaded, &os->rx_size_1522,
2827                             &ns->rx_size_1522);
2828         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2829                             I40E_GLPRT_PRC9522L(hw->port),
2830                             pf->offset_loaded, &os->rx_size_big,
2831                             &ns->rx_size_big);
2832         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2833                             pf->offset_loaded, &os->rx_undersize,
2834                             &ns->rx_undersize);
2835         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2836                             pf->offset_loaded, &os->rx_fragments,
2837                             &ns->rx_fragments);
2838         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2839                             pf->offset_loaded, &os->rx_oversize,
2840                             &ns->rx_oversize);
2841         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2842                             pf->offset_loaded, &os->rx_jabber,
2843                             &ns->rx_jabber);
2844         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2845                             I40E_GLPRT_PTC64L(hw->port),
2846                             pf->offset_loaded, &os->tx_size_64,
2847                             &ns->tx_size_64);
2848         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2849                             I40E_GLPRT_PTC127L(hw->port),
2850                             pf->offset_loaded, &os->tx_size_127,
2851                             &ns->tx_size_127);
2852         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2853                             I40E_GLPRT_PTC255L(hw->port),
2854                             pf->offset_loaded, &os->tx_size_255,
2855                             &ns->tx_size_255);
2856         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2857                             I40E_GLPRT_PTC511L(hw->port),
2858                             pf->offset_loaded, &os->tx_size_511,
2859                             &ns->tx_size_511);
2860         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2861                             I40E_GLPRT_PTC1023L(hw->port),
2862                             pf->offset_loaded, &os->tx_size_1023,
2863                             &ns->tx_size_1023);
2864         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2865                             I40E_GLPRT_PTC1522L(hw->port),
2866                             pf->offset_loaded, &os->tx_size_1522,
2867                             &ns->tx_size_1522);
2868         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2869                             I40E_GLPRT_PTC9522L(hw->port),
2870                             pf->offset_loaded, &os->tx_size_big,
2871                             &ns->tx_size_big);
2872         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2873                            pf->offset_loaded,
2874                            &os->fd_sb_match, &ns->fd_sb_match);
2875         /* GLPRT_MSPDC not supported */
2876         /* GLPRT_XEC not supported */
2877
2878         pf->offset_loaded = true;
2879
2880         if (pf->main_vsi)
2881                 i40e_update_vsi_stats(pf->main_vsi);
2882 }
2883
2884 /* Get all statistics of a port */
2885 static int
2886 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2887 {
2888         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2889         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2891         unsigned i;
2892
2893         /* call read registers - updates values, now write them to struct */
2894         i40e_read_stats_registers(pf, hw);
2895
2896         stats->ipackets = ns->eth.rx_unicast +
2897                         ns->eth.rx_multicast +
2898                         ns->eth.rx_broadcast -
2899                         ns->eth.rx_discards -
2900                         pf->main_vsi->eth_stats.rx_discards;
2901         stats->opackets = ns->eth.tx_unicast +
2902                         ns->eth.tx_multicast +
2903                         ns->eth.tx_broadcast;
2904         stats->ibytes   = ns->eth.rx_bytes;
2905         stats->obytes   = ns->eth.tx_bytes;
2906         stats->oerrors  = ns->eth.tx_errors +
2907                         pf->main_vsi->eth_stats.tx_errors;
2908
2909         /* Rx Errors */
2910         stats->imissed  = ns->eth.rx_discards +
2911                         pf->main_vsi->eth_stats.rx_discards;
2912         stats->ierrors  = ns->crc_errors +
2913                         ns->rx_length_errors + ns->rx_undersize +
2914                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2915
2916         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2917         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2918         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2919         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2920         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2921         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2922         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2923                     ns->eth.rx_unknown_protocol);
2924         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2925         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2926         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2927         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2928         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2929         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2930
2931         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2932                     ns->tx_dropped_link_down);
2933         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2934         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2935                     ns->illegal_bytes);
2936         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2937         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2938                     ns->mac_local_faults);
2939         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2940                     ns->mac_remote_faults);
2941         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2942                     ns->rx_length_errors);
2943         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2944         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2945         for (i = 0; i < 8; i++) {
2946                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2947                                 i, ns->priority_xon_rx[i]);
2948                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2949                                 i, ns->priority_xoff_rx[i]);
2950         }
2951         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2952         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2953         for (i = 0; i < 8; i++) {
2954                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2955                                 i, ns->priority_xon_tx[i]);
2956                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2957                                 i, ns->priority_xoff_tx[i]);
2958                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2959                                 i, ns->priority_xon_2_xoff[i]);
2960         }
2961         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2962         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2963         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2964         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2965         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2966         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2967         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2968         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2969         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2970         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2971         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2972         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2973         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2974         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2975         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2976         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2977         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2978         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2979         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2980                         ns->mac_short_packet_dropped);
2981         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2982                     ns->checksum_error);
2983         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2984         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2985         return 0;
2986 }
2987
2988 /* Reset the statistics */
2989 static void
2990 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2991 {
2992         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2993         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2994
2995         /* Mark PF and VSI stats to update the offset, aka "reset" */
2996         pf->offset_loaded = false;
2997         if (pf->main_vsi)
2998                 pf->main_vsi->offset_loaded = false;
2999
3000         /* read the stats, reading current register values into offset */
3001         i40e_read_stats_registers(pf, hw);
3002 }
3003
3004 static uint32_t
3005 i40e_xstats_calc_num(void)
3006 {
3007         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3008                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3009                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3010 }
3011
3012 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3013                                      struct rte_eth_xstat_name *xstats_names,
3014                                      __rte_unused unsigned limit)
3015 {
3016         unsigned count = 0;
3017         unsigned i, prio;
3018
3019         if (xstats_names == NULL)
3020                 return i40e_xstats_calc_num();
3021
3022         /* Note: limit checked in rte_eth_xstats_names() */
3023
3024         /* Get stats from i40e_eth_stats struct */
3025         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3026                 snprintf(xstats_names[count].name,
3027                          sizeof(xstats_names[count].name),
3028                          "%s", rte_i40e_stats_strings[i].name);
3029                 count++;
3030         }
3031
3032         /* Get individiual stats from i40e_hw_port struct */
3033         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3034                 snprintf(xstats_names[count].name,
3035                         sizeof(xstats_names[count].name),
3036                          "%s", rte_i40e_hw_port_strings[i].name);
3037                 count++;
3038         }
3039
3040         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3041                 for (prio = 0; prio < 8; prio++) {
3042                         snprintf(xstats_names[count].name,
3043                                  sizeof(xstats_names[count].name),
3044                                  "rx_priority%u_%s", prio,
3045                                  rte_i40e_rxq_prio_strings[i].name);
3046                         count++;
3047                 }
3048         }
3049
3050         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3051                 for (prio = 0; prio < 8; prio++) {
3052                         snprintf(xstats_names[count].name,
3053                                  sizeof(xstats_names[count].name),
3054                                  "tx_priority%u_%s", prio,
3055                                  rte_i40e_txq_prio_strings[i].name);
3056                         count++;
3057                 }
3058         }
3059         return count;
3060 }
3061
3062 static int
3063 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3064                     unsigned n)
3065 {
3066         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3067         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068         unsigned i, count, prio;
3069         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3070
3071         count = i40e_xstats_calc_num();
3072         if (n < count)
3073                 return count;
3074
3075         i40e_read_stats_registers(pf, hw);
3076
3077         if (xstats == NULL)
3078                 return 0;
3079
3080         count = 0;
3081
3082         /* Get stats from i40e_eth_stats struct */
3083         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3084                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3085                         rte_i40e_stats_strings[i].offset);
3086                 xstats[count].id = count;
3087                 count++;
3088         }
3089
3090         /* Get individiual stats from i40e_hw_port struct */
3091         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3092                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3093                         rte_i40e_hw_port_strings[i].offset);
3094                 xstats[count].id = count;
3095                 count++;
3096         }
3097
3098         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3099                 for (prio = 0; prio < 8; prio++) {
3100                         xstats[count].value =
3101                                 *(uint64_t *)(((char *)hw_stats) +
3102                                 rte_i40e_rxq_prio_strings[i].offset +
3103                                 (sizeof(uint64_t) * prio));
3104                         xstats[count].id = count;
3105                         count++;
3106                 }
3107         }
3108
3109         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3110                 for (prio = 0; prio < 8; prio++) {
3111                         xstats[count].value =
3112                                 *(uint64_t *)(((char *)hw_stats) +
3113                                 rte_i40e_txq_prio_strings[i].offset +
3114                                 (sizeof(uint64_t) * prio));
3115                         xstats[count].id = count;
3116                         count++;
3117                 }
3118         }
3119
3120         return count;
3121 }
3122
3123 static int
3124 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3125                                  __rte_unused uint16_t queue_id,
3126                                  __rte_unused uint8_t stat_idx,
3127                                  __rte_unused uint8_t is_rx)
3128 {
3129         PMD_INIT_FUNC_TRACE();
3130
3131         return -ENOSYS;
3132 }
3133
3134 static int
3135 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3136 {
3137         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3138         u32 full_ver;
3139         u8 ver, patch;
3140         u16 build;
3141         int ret;
3142
3143         full_ver = hw->nvm.oem_ver;
3144         ver = (u8)(full_ver >> 24);
3145         build = (u16)((full_ver >> 8) & 0xffff);
3146         patch = (u8)(full_ver & 0xff);
3147
3148         ret = snprintf(fw_version, fw_size,
3149                  "%d.%d%d 0x%08x %d.%d.%d",
3150                  ((hw->nvm.version >> 12) & 0xf),
3151                  ((hw->nvm.version >> 4) & 0xff),
3152                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3153                  ver, build, patch);
3154
3155         ret += 1; /* add the size of '\0' */
3156         if (fw_size < (u32)ret)
3157                 return ret;
3158         else
3159                 return 0;
3160 }
3161
3162 static void
3163 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3164 {
3165         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3166         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3167         struct i40e_vsi *vsi = pf->main_vsi;
3168         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3169
3170         dev_info->pci_dev = pci_dev;
3171         dev_info->max_rx_queues = vsi->nb_qps;
3172         dev_info->max_tx_queues = vsi->nb_qps;
3173         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3174         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3175         dev_info->max_mac_addrs = vsi->max_macaddrs;
3176         dev_info->max_vfs = pci_dev->max_vfs;
3177         dev_info->rx_offload_capa =
3178                 DEV_RX_OFFLOAD_VLAN_STRIP |
3179                 DEV_RX_OFFLOAD_QINQ_STRIP |
3180                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3181                 DEV_RX_OFFLOAD_UDP_CKSUM |
3182                 DEV_RX_OFFLOAD_TCP_CKSUM |
3183                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3184                 DEV_RX_OFFLOAD_CRC_STRIP;
3185         dev_info->tx_offload_capa =
3186                 DEV_TX_OFFLOAD_VLAN_INSERT |
3187                 DEV_TX_OFFLOAD_QINQ_INSERT |
3188                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3189                 DEV_TX_OFFLOAD_UDP_CKSUM |
3190                 DEV_TX_OFFLOAD_TCP_CKSUM |
3191                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3192                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3193                 DEV_TX_OFFLOAD_TCP_TSO |
3194                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3195                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3196                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3197                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3198         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3199                                                 sizeof(uint32_t);
3200         dev_info->reta_size = pf->hash_lut_size;
3201         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3202
3203         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3204                 .rx_thresh = {
3205                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3206                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3207                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3208                 },
3209                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3210                 .rx_drop_en = 0,
3211         };
3212
3213         dev_info->default_txconf = (struct rte_eth_txconf) {
3214                 .tx_thresh = {
3215                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3216                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3217                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3218                 },
3219                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3220                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3221                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3222                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3223         };
3224
3225         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3226                 .nb_max = I40E_MAX_RING_DESC,
3227                 .nb_min = I40E_MIN_RING_DESC,
3228                 .nb_align = I40E_ALIGN_RING_DESC,
3229         };
3230
3231         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3232                 .nb_max = I40E_MAX_RING_DESC,
3233                 .nb_min = I40E_MIN_RING_DESC,
3234                 .nb_align = I40E_ALIGN_RING_DESC,
3235                 .nb_seg_max = I40E_TX_MAX_SEG,
3236                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3237         };
3238
3239         if (pf->flags & I40E_FLAG_VMDQ) {
3240                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3241                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3242                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3243                                                 pf->max_nb_vmdq_vsi;
3244                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3245                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3246                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3247         }
3248
3249         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3250                 /* For XL710 */
3251                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3252         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3253                 /* For XXV710 */
3254                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3255         else
3256                 /* For X710 */
3257                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3258 }
3259
3260 static int
3261 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3262 {
3263         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3264         struct i40e_vsi *vsi = pf->main_vsi;
3265         PMD_INIT_FUNC_TRACE();
3266
3267         if (on)
3268                 return i40e_vsi_add_vlan(vsi, vlan_id);
3269         else
3270                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3271 }
3272
3273 static int
3274 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3275                                 enum rte_vlan_type vlan_type,
3276                                 uint16_t tpid, int qinq)
3277 {
3278         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3279         uint64_t reg_r = 0;
3280         uint64_t reg_w = 0;
3281         uint16_t reg_id = 3;
3282         int ret;
3283
3284         if (qinq) {
3285                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3286                         reg_id = 2;
3287         }
3288
3289         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3290                                           &reg_r, NULL);
3291         if (ret != I40E_SUCCESS) {
3292                 PMD_DRV_LOG(ERR,
3293                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3294                            reg_id);
3295                 return -EIO;
3296         }
3297         PMD_DRV_LOG(DEBUG,
3298                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3299                     reg_id, reg_r);
3300
3301         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3302         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3303         if (reg_r == reg_w) {
3304                 PMD_DRV_LOG(DEBUG, "No need to write");
3305                 return 0;
3306         }
3307
3308         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3309                                            reg_w, NULL);
3310         if (ret != I40E_SUCCESS) {
3311                 PMD_DRV_LOG(ERR,
3312                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3313                             reg_id);
3314                 return -EIO;
3315         }
3316         PMD_DRV_LOG(DEBUG,
3317                     "Global register 0x%08x is changed with value 0x%08x",
3318                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3319
3320         return 0;
3321 }
3322
3323 static int
3324 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3325                    enum rte_vlan_type vlan_type,
3326                    uint16_t tpid)
3327 {
3328         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3329         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3330         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3331         int ret = 0;
3332
3333         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3334              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3335             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3336                 PMD_DRV_LOG(ERR,
3337                             "Unsupported vlan type.");
3338                 return -EINVAL;
3339         }
3340
3341         if (pf->support_multi_driver) {
3342                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3343                 return -ENOTSUP;
3344         }
3345
3346         /* 802.1ad frames ability is added in NVM API 1.7*/
3347         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3348                 if (qinq) {
3349                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3350                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3351                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3352                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3353                 } else {
3354                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3355                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3356                 }
3357                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3358                 if (ret != I40E_SUCCESS) {
3359                         PMD_DRV_LOG(ERR,
3360                                     "Set switch config failed aq_err: %d",
3361                                     hw->aq.asq_last_status);
3362                         ret = -EIO;
3363                 }
3364         } else
3365                 /* If NVM API < 1.7, keep the register setting */
3366                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3367                                                       tpid, qinq);
3368         i40e_global_cfg_warning(I40E_WARNING_TPID);
3369
3370         return ret;
3371 }
3372
3373 static int
3374 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3375 {
3376         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3377         struct i40e_vsi *vsi = pf->main_vsi;
3378
3379         if (mask & ETH_VLAN_FILTER_MASK) {
3380                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3381                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3382                 else
3383                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3384         }
3385
3386         if (mask & ETH_VLAN_STRIP_MASK) {
3387                 /* Enable or disable VLAN stripping */
3388                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3389                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3390                 else
3391                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3392         }
3393
3394         if (mask & ETH_VLAN_EXTEND_MASK) {
3395                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3396                         i40e_vsi_config_double_vlan(vsi, TRUE);
3397                         /* Set global registers with default ethertype. */
3398                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3399                                            ETHER_TYPE_VLAN);
3400                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3401                                            ETHER_TYPE_VLAN);
3402                 }
3403                 else
3404                         i40e_vsi_config_double_vlan(vsi, FALSE);
3405         }
3406
3407         return 0;
3408 }
3409
3410 static void
3411 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3412                           __rte_unused uint16_t queue,
3413                           __rte_unused int on)
3414 {
3415         PMD_INIT_FUNC_TRACE();
3416 }
3417
3418 static int
3419 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3420 {
3421         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3422         struct i40e_vsi *vsi = pf->main_vsi;
3423         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3424         struct i40e_vsi_vlan_pvid_info info;
3425
3426         memset(&info, 0, sizeof(info));
3427         info.on = on;
3428         if (info.on)
3429                 info.config.pvid = pvid;
3430         else {
3431                 info.config.reject.tagged =
3432                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3433                 info.config.reject.untagged =
3434                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3435         }
3436
3437         return i40e_vsi_vlan_pvid_set(vsi, &info);
3438 }
3439
3440 static int
3441 i40e_dev_led_on(struct rte_eth_dev *dev)
3442 {
3443         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3444         uint32_t mode = i40e_led_get(hw);
3445
3446         if (mode == 0)
3447                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3448
3449         return 0;
3450 }
3451
3452 static int
3453 i40e_dev_led_off(struct rte_eth_dev *dev)
3454 {
3455         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3456         uint32_t mode = i40e_led_get(hw);
3457
3458         if (mode != 0)
3459                 i40e_led_set(hw, 0, false);
3460
3461         return 0;
3462 }
3463
3464 static int
3465 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3466 {
3467         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3468         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3469
3470         fc_conf->pause_time = pf->fc_conf.pause_time;
3471
3472         /* read out from register, in case they are modified by other port */
3473         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3474                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3475         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3476                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3477
3478         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3479         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3480
3481          /* Return current mode according to actual setting*/
3482         switch (hw->fc.current_mode) {
3483         case I40E_FC_FULL:
3484                 fc_conf->mode = RTE_FC_FULL;
3485                 break;
3486         case I40E_FC_TX_PAUSE:
3487                 fc_conf->mode = RTE_FC_TX_PAUSE;
3488                 break;
3489         case I40E_FC_RX_PAUSE:
3490                 fc_conf->mode = RTE_FC_RX_PAUSE;
3491                 break;
3492         case I40E_FC_NONE:
3493         default:
3494                 fc_conf->mode = RTE_FC_NONE;
3495         };
3496
3497         return 0;
3498 }
3499
3500 static int
3501 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3502 {
3503         uint32_t mflcn_reg, fctrl_reg, reg;
3504         uint32_t max_high_water;
3505         uint8_t i, aq_failure;
3506         int err;
3507         struct i40e_hw *hw;
3508         struct i40e_pf *pf;
3509         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3510                 [RTE_FC_NONE] = I40E_FC_NONE,
3511                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3512                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3513                 [RTE_FC_FULL] = I40E_FC_FULL
3514         };
3515
3516         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3517
3518         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3519         if ((fc_conf->high_water > max_high_water) ||
3520                         (fc_conf->high_water < fc_conf->low_water)) {
3521                 PMD_INIT_LOG(ERR,
3522                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3523                         max_high_water);
3524                 return -EINVAL;
3525         }
3526
3527         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3528         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3529         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3530
3531         pf->fc_conf.pause_time = fc_conf->pause_time;
3532         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3533         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3534
3535         PMD_INIT_FUNC_TRACE();
3536
3537         /* All the link flow control related enable/disable register
3538          * configuration is handle by the F/W
3539          */
3540         err = i40e_set_fc(hw, &aq_failure, true);
3541         if (err < 0)
3542                 return -ENOSYS;
3543
3544         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3545                 /* Configure flow control refresh threshold,
3546                  * the value for stat_tx_pause_refresh_timer[8]
3547                  * is used for global pause operation.
3548                  */
3549
3550                 I40E_WRITE_REG(hw,
3551                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3552                                pf->fc_conf.pause_time);
3553
3554                 /* configure the timer value included in transmitted pause
3555                  * frame,
3556                  * the value for stat_tx_pause_quanta[8] is used for global
3557                  * pause operation
3558                  */
3559                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3560                                pf->fc_conf.pause_time);
3561
3562                 fctrl_reg = I40E_READ_REG(hw,
3563                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3564
3565                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3566                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3567                 else
3568                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3569
3570                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3571                                fctrl_reg);
3572         } else {
3573                 /* Configure pause time (2 TCs per register) */
3574                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3575                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3576                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3577
3578                 /* Configure flow control refresh threshold value */
3579                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3580                                pf->fc_conf.pause_time / 2);
3581
3582                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3583
3584                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3585                  *depending on configuration
3586                  */
3587                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3588                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3589                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3590                 } else {
3591                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3592                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3593                 }
3594
3595                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3596         }
3597
3598         if (!pf->support_multi_driver) {
3599                 /* config water marker both based on the packets and bytes */
3600                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3601                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3602                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3603                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3604                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3605                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3606                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3607                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3608                                   << I40E_KILOSHIFT);
3609                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3610                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3611                                    << I40E_KILOSHIFT);
3612                 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3613         } else {
3614                 PMD_DRV_LOG(ERR,
3615                             "Water marker configuration is not supported.");
3616         }
3617
3618         I40E_WRITE_FLUSH(hw);
3619
3620         return 0;
3621 }
3622
3623 static int
3624 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3625                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3626 {
3627         PMD_INIT_FUNC_TRACE();
3628
3629         return -ENOSYS;
3630 }
3631
3632 /* Add a MAC address, and update filters */
3633 static int
3634 i40e_macaddr_add(struct rte_eth_dev *dev,
3635                  struct ether_addr *mac_addr,
3636                  __rte_unused uint32_t index,
3637                  uint32_t pool)
3638 {
3639         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3640         struct i40e_mac_filter_info mac_filter;
3641         struct i40e_vsi *vsi;
3642         int ret;
3643
3644         /* If VMDQ not enabled or configured, return */
3645         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3646                           !pf->nb_cfg_vmdq_vsi)) {
3647                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3648                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3649                         pool);
3650                 return -ENOTSUP;
3651         }
3652
3653         if (pool > pf->nb_cfg_vmdq_vsi) {
3654                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3655                                 pool, pf->nb_cfg_vmdq_vsi);
3656                 return -EINVAL;
3657         }
3658
3659         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3660         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3661                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3662         else
3663                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3664
3665         if (pool == 0)
3666                 vsi = pf->main_vsi;
3667         else
3668                 vsi = pf->vmdq[pool - 1].vsi;
3669
3670         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3671         if (ret != I40E_SUCCESS) {
3672                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3673                 return -ENODEV;
3674         }
3675         return 0;
3676 }
3677
3678 /* Remove a MAC address, and update filters */
3679 static void
3680 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3681 {
3682         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3683         struct i40e_vsi *vsi;
3684         struct rte_eth_dev_data *data = dev->data;
3685         struct ether_addr *macaddr;
3686         int ret;
3687         uint32_t i;
3688         uint64_t pool_sel;
3689
3690         macaddr = &(data->mac_addrs[index]);
3691
3692         pool_sel = dev->data->mac_pool_sel[index];
3693
3694         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3695                 if (pool_sel & (1ULL << i)) {
3696                         if (i == 0)
3697                                 vsi = pf->main_vsi;
3698                         else {
3699                                 /* No VMDQ pool enabled or configured */
3700                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3701                                         (i > pf->nb_cfg_vmdq_vsi)) {
3702                                         PMD_DRV_LOG(ERR,
3703                                                 "No VMDQ pool enabled/configured");
3704                                         return;
3705                                 }
3706                                 vsi = pf->vmdq[i - 1].vsi;
3707                         }
3708                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3709
3710                         if (ret) {
3711                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3712                                 return;
3713                         }
3714                 }
3715         }
3716 }
3717
3718 /* Set perfect match or hash match of MAC and VLAN for a VF */
3719 static int
3720 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3721                  struct rte_eth_mac_filter *filter,
3722                  bool add)
3723 {
3724         struct i40e_hw *hw;
3725         struct i40e_mac_filter_info mac_filter;
3726         struct ether_addr old_mac;
3727         struct ether_addr *new_mac;
3728         struct i40e_pf_vf *vf = NULL;
3729         uint16_t vf_id;
3730         int ret;
3731
3732         if (pf == NULL) {
3733                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3734                 return -EINVAL;
3735         }
3736         hw = I40E_PF_TO_HW(pf);
3737
3738         if (filter == NULL) {
3739                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3740                 return -EINVAL;
3741         }
3742
3743         new_mac = &filter->mac_addr;
3744
3745         if (is_zero_ether_addr(new_mac)) {
3746                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3747                 return -EINVAL;
3748         }
3749
3750         vf_id = filter->dst_id;
3751
3752         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3753                 PMD_DRV_LOG(ERR, "Invalid argument.");
3754                 return -EINVAL;
3755         }
3756         vf = &pf->vfs[vf_id];
3757
3758         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3759                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3760                 return -EINVAL;
3761         }
3762
3763         if (add) {
3764                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3765                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3766                                 ETHER_ADDR_LEN);
3767                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3768                                  ETHER_ADDR_LEN);
3769
3770                 mac_filter.filter_type = filter->filter_type;
3771                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3772                 if (ret != I40E_SUCCESS) {
3773                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3774                         return -1;
3775                 }
3776                 ether_addr_copy(new_mac, &pf->dev_addr);
3777         } else {
3778                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3779                                 ETHER_ADDR_LEN);
3780                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3781                 if (ret != I40E_SUCCESS) {
3782                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3783                         return -1;
3784                 }
3785
3786                 /* Clear device address as it has been removed */
3787                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3788                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3789         }
3790
3791         return 0;
3792 }
3793
3794 /* MAC filter handle */
3795 static int
3796 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3797                 void *arg)
3798 {
3799         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3800         struct rte_eth_mac_filter *filter;
3801         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3802         int ret = I40E_NOT_SUPPORTED;
3803
3804         filter = (struct rte_eth_mac_filter *)(arg);
3805
3806         switch (filter_op) {
3807         case RTE_ETH_FILTER_NOP:
3808                 ret = I40E_SUCCESS;
3809                 break;
3810         case RTE_ETH_FILTER_ADD:
3811                 i40e_pf_disable_irq0(hw);
3812                 if (filter->is_vf)
3813                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3814                 i40e_pf_enable_irq0(hw);
3815                 break;
3816         case RTE_ETH_FILTER_DELETE:
3817                 i40e_pf_disable_irq0(hw);
3818                 if (filter->is_vf)
3819                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3820                 i40e_pf_enable_irq0(hw);
3821                 break;
3822         default:
3823                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3824                 ret = I40E_ERR_PARAM;
3825                 break;
3826         }
3827
3828         return ret;
3829 }
3830
3831 static int
3832 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3833 {
3834         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3835         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3836         uint32_t reg;
3837         int ret;
3838
3839         if (!lut)
3840                 return -EINVAL;
3841
3842         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3843                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3844                                           lut, lut_size);
3845                 if (ret) {
3846                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3847                         return ret;
3848                 }
3849         } else {
3850                 uint32_t *lut_dw = (uint32_t *)lut;
3851                 uint16_t i, lut_size_dw = lut_size / 4;
3852
3853                 if (vsi->type == I40E_VSI_SRIOV) {
3854                         for (i = 0; i <= lut_size_dw; i++) {
3855                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
3856                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
3857                         }
3858                 } else {
3859                         for (i = 0; i < lut_size_dw; i++)
3860                                 lut_dw[i] = I40E_READ_REG(hw,
3861                                                           I40E_PFQF_HLUT(i));
3862                 }
3863         }
3864
3865         return 0;
3866 }
3867
3868 int
3869 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3870 {
3871         struct i40e_pf *pf;
3872         struct i40e_hw *hw;
3873         int ret;
3874
3875         if (!vsi || !lut)
3876                 return -EINVAL;
3877
3878         pf = I40E_VSI_TO_PF(vsi);
3879         hw = I40E_VSI_TO_HW(vsi);
3880
3881         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3882                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3883                                           lut, lut_size);
3884                 if (ret) {
3885                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3886                         return ret;
3887                 }
3888         } else {
3889                 uint32_t *lut_dw = (uint32_t *)lut;
3890                 uint16_t i, lut_size_dw = lut_size / 4;
3891
3892                 if (vsi->type == I40E_VSI_SRIOV) {
3893                         for (i = 0; i < lut_size_dw; i++)
3894                                 I40E_WRITE_REG(
3895                                         hw,
3896                                         I40E_VFQF_HLUT1(i, vsi->user_param),
3897                                         lut_dw[i]);
3898                 } else {
3899                         for (i = 0; i < lut_size_dw; i++)
3900                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
3901                                                lut_dw[i]);
3902                 }
3903                 I40E_WRITE_FLUSH(hw);
3904         }
3905
3906         return 0;
3907 }
3908
3909 static int
3910 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3911                          struct rte_eth_rss_reta_entry64 *reta_conf,
3912                          uint16_t reta_size)
3913 {
3914         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3915         uint16_t i, lut_size = pf->hash_lut_size;
3916         uint16_t idx, shift;
3917         uint8_t *lut;
3918         int ret;
3919
3920         if (reta_size != lut_size ||
3921                 reta_size > ETH_RSS_RETA_SIZE_512) {
3922                 PMD_DRV_LOG(ERR,
3923                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3924                         reta_size, lut_size);
3925                 return -EINVAL;
3926         }
3927
3928         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3929         if (!lut) {
3930                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3931                 return -ENOMEM;
3932         }
3933         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3934         if (ret)
3935                 goto out;
3936         for (i = 0; i < reta_size; i++) {
3937                 idx = i / RTE_RETA_GROUP_SIZE;
3938                 shift = i % RTE_RETA_GROUP_SIZE;
3939                 if (reta_conf[idx].mask & (1ULL << shift))
3940                         lut[i] = reta_conf[idx].reta[shift];
3941         }
3942         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3943
3944 out:
3945         rte_free(lut);
3946
3947         return ret;
3948 }
3949
3950 static int
3951 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3952                         struct rte_eth_rss_reta_entry64 *reta_conf,
3953                         uint16_t reta_size)
3954 {
3955         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3956         uint16_t i, lut_size = pf->hash_lut_size;
3957         uint16_t idx, shift;
3958         uint8_t *lut;
3959         int ret;
3960
3961         if (reta_size != lut_size ||
3962                 reta_size > ETH_RSS_RETA_SIZE_512) {
3963                 PMD_DRV_LOG(ERR,
3964                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3965                         reta_size, lut_size);
3966                 return -EINVAL;
3967         }
3968
3969         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3970         if (!lut) {
3971                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3972                 return -ENOMEM;
3973         }
3974
3975         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3976         if (ret)
3977                 goto out;
3978         for (i = 0; i < reta_size; i++) {
3979                 idx = i / RTE_RETA_GROUP_SIZE;
3980                 shift = i % RTE_RETA_GROUP_SIZE;
3981                 if (reta_conf[idx].mask & (1ULL << shift))
3982                         reta_conf[idx].reta[shift] = lut[i];
3983         }
3984
3985 out:
3986         rte_free(lut);
3987
3988         return ret;
3989 }
3990
3991 /**
3992  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3993  * @hw:   pointer to the HW structure
3994  * @mem:  pointer to mem struct to fill out
3995  * @size: size of memory requested
3996  * @alignment: what to align the allocation to
3997  **/
3998 enum i40e_status_code
3999 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4000                         struct i40e_dma_mem *mem,
4001                         u64 size,
4002                         u32 alignment)
4003 {
4004         const struct rte_memzone *mz = NULL;
4005         char z_name[RTE_MEMZONE_NAMESIZE];
4006
4007         if (!mem)
4008                 return I40E_ERR_PARAM;
4009
4010         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4011         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
4012                                          alignment, RTE_PGSIZE_2M);
4013         if (!mz)
4014                 return I40E_ERR_NO_MEMORY;
4015
4016         mem->size = size;
4017         mem->va = mz->addr;
4018         mem->pa = mz->iova;
4019         mem->zone = (const void *)mz;
4020         PMD_DRV_LOG(DEBUG,
4021                 "memzone %s allocated with physical address: %"PRIu64,
4022                 mz->name, mem->pa);
4023
4024         return I40E_SUCCESS;
4025 }
4026
4027 /**
4028  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4029  * @hw:   pointer to the HW structure
4030  * @mem:  ptr to mem struct to free
4031  **/
4032 enum i40e_status_code
4033 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4034                     struct i40e_dma_mem *mem)
4035 {
4036         if (!mem)
4037                 return I40E_ERR_PARAM;
4038
4039         PMD_DRV_LOG(DEBUG,
4040                 "memzone %s to be freed with physical address: %"PRIu64,
4041                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4042         rte_memzone_free((const struct rte_memzone *)mem->zone);
4043         mem->zone = NULL;
4044         mem->va = NULL;
4045         mem->pa = (u64)0;
4046
4047         return I40E_SUCCESS;
4048 }
4049
4050 /**
4051  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4052  * @hw:   pointer to the HW structure
4053  * @mem:  pointer to mem struct to fill out
4054  * @size: size of memory requested
4055  **/
4056 enum i40e_status_code
4057 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4058                          struct i40e_virt_mem *mem,
4059                          u32 size)
4060 {
4061         if (!mem)
4062                 return I40E_ERR_PARAM;
4063
4064         mem->size = size;
4065         mem->va = rte_zmalloc("i40e", size, 0);
4066
4067         if (mem->va)
4068                 return I40E_SUCCESS;
4069         else
4070                 return I40E_ERR_NO_MEMORY;
4071 }
4072
4073 /**
4074  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4075  * @hw:   pointer to the HW structure
4076  * @mem:  pointer to mem struct to free
4077  **/
4078 enum i40e_status_code
4079 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4080                      struct i40e_virt_mem *mem)
4081 {
4082         if (!mem)
4083                 return I40E_ERR_PARAM;
4084
4085         rte_free(mem->va);
4086         mem->va = NULL;
4087
4088         return I40E_SUCCESS;
4089 }
4090
4091 void
4092 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4093 {
4094         rte_spinlock_init(&sp->spinlock);
4095 }
4096
4097 void
4098 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4099 {
4100         rte_spinlock_lock(&sp->spinlock);
4101 }
4102
4103 void
4104 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4105 {
4106         rte_spinlock_unlock(&sp->spinlock);
4107 }
4108
4109 void
4110 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4111 {
4112         return;
4113 }
4114
4115 /**
4116  * Get the hardware capabilities, which will be parsed
4117  * and saved into struct i40e_hw.
4118  */
4119 static int
4120 i40e_get_cap(struct i40e_hw *hw)
4121 {
4122         struct i40e_aqc_list_capabilities_element_resp *buf;
4123         uint16_t len, size = 0;
4124         int ret;
4125
4126         /* Calculate a huge enough buff for saving response data temporarily */
4127         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4128                                                 I40E_MAX_CAP_ELE_NUM;
4129         buf = rte_zmalloc("i40e", len, 0);
4130         if (!buf) {
4131                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4132                 return I40E_ERR_NO_MEMORY;
4133         }
4134
4135         /* Get, parse the capabilities and save it to hw */
4136         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4137                         i40e_aqc_opc_list_func_capabilities, NULL);
4138         if (ret != I40E_SUCCESS)
4139                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4140
4141         /* Free the temporary buffer after being used */
4142         rte_free(buf);
4143
4144         return ret;
4145 }
4146
4147 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4148 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
4149
4150 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4151                 const char *value,
4152                 void *opaque)
4153 {
4154         struct i40e_pf *pf;
4155         unsigned long num;
4156         char *end;
4157
4158         pf = (struct i40e_pf *)opaque;
4159         RTE_SET_USED(key);
4160
4161         errno = 0;
4162         num = strtoul(value, &end, 0);
4163         if (errno != 0 || end == value || *end != 0) {
4164                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4165                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4166                 return -(EINVAL);
4167         }
4168
4169         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4170                 pf->vf_nb_qp_max = (uint16_t)num;
4171         else
4172                 /* here return 0 to make next valid same argument work */
4173                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4174                             "power of 2 and equal or less than 16 !, Now it is "
4175                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4176
4177         return 0;
4178 }
4179
4180 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4181 {
4182         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4183         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4184         struct rte_kvargs *kvlist;
4185
4186         /* set default queue number per VF as 4 */
4187         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4188
4189         if (dev->device->devargs == NULL)
4190                 return 0;
4191
4192         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4193         if (kvlist == NULL)
4194                 return -(EINVAL);
4195
4196         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4197                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4198                             "the first invalid or last valid one is used !",
4199                             QUEUE_NUM_PER_VF_ARG);
4200
4201         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4202                            i40e_pf_parse_vf_queue_number_handler, pf);
4203
4204         rte_kvargs_free(kvlist);
4205
4206         return 0;
4207 }
4208
4209 static int
4210 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4211 {
4212         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4213         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4214         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4215         uint16_t qp_count = 0, vsi_count = 0;
4216
4217         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4218                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4219                 return -EINVAL;
4220         }
4221
4222         i40e_pf_config_vf_rxq_number(dev);
4223
4224         /* Add the parameter init for LFC */
4225         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4226         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4227         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4228
4229         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4230         pf->max_num_vsi = hw->func_caps.num_vsis;
4231         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4232         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4233
4234         /* FDir queue/VSI allocation */
4235         pf->fdir_qp_offset = 0;
4236         if (hw->func_caps.fd) {
4237                 pf->flags |= I40E_FLAG_FDIR;
4238                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4239         } else {
4240                 pf->fdir_nb_qps = 0;
4241         }
4242         qp_count += pf->fdir_nb_qps;
4243         vsi_count += 1;
4244
4245         /* LAN queue/VSI allocation */
4246         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4247         if (!hw->func_caps.rss) {
4248                 pf->lan_nb_qps = 1;
4249         } else {
4250                 pf->flags |= I40E_FLAG_RSS;
4251                 if (hw->mac.type == I40E_MAC_X722)
4252                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4253                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4254         }
4255         qp_count += pf->lan_nb_qps;
4256         vsi_count += 1;
4257
4258         /* VF queue/VSI allocation */
4259         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4260         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4261                 pf->flags |= I40E_FLAG_SRIOV;
4262                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4263                 pf->vf_num = pci_dev->max_vfs;
4264                 PMD_DRV_LOG(DEBUG,
4265                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4266                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4267         } else {
4268                 pf->vf_nb_qps = 0;
4269                 pf->vf_num = 0;
4270         }
4271         qp_count += pf->vf_nb_qps * pf->vf_num;
4272         vsi_count += pf->vf_num;
4273
4274         /* VMDq queue/VSI allocation */
4275         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4276         pf->vmdq_nb_qps = 0;
4277         pf->max_nb_vmdq_vsi = 0;
4278         if (hw->func_caps.vmdq) {
4279                 if (qp_count < hw->func_caps.num_tx_qp &&
4280                         vsi_count < hw->func_caps.num_vsis) {
4281                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4282                                 qp_count) / pf->vmdq_nb_qp_max;
4283
4284                         /* Limit the maximum number of VMDq vsi to the maximum
4285                          * ethdev can support
4286                          */
4287                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4288                                 hw->func_caps.num_vsis - vsi_count);
4289                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4290                                 ETH_64_POOLS);
4291                         if (pf->max_nb_vmdq_vsi) {
4292                                 pf->flags |= I40E_FLAG_VMDQ;
4293                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4294                                 PMD_DRV_LOG(DEBUG,
4295                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4296                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4297                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4298                         } else {
4299                                 PMD_DRV_LOG(INFO,
4300                                         "No enough queues left for VMDq");
4301                         }
4302                 } else {
4303                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4304                 }
4305         }
4306         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4307         vsi_count += pf->max_nb_vmdq_vsi;
4308
4309         if (hw->func_caps.dcb)
4310                 pf->flags |= I40E_FLAG_DCB;
4311
4312         if (qp_count > hw->func_caps.num_tx_qp) {
4313                 PMD_DRV_LOG(ERR,
4314                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4315                         qp_count, hw->func_caps.num_tx_qp);
4316                 return -EINVAL;
4317         }
4318         if (vsi_count > hw->func_caps.num_vsis) {
4319                 PMD_DRV_LOG(ERR,
4320                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4321                         vsi_count, hw->func_caps.num_vsis);
4322                 return -EINVAL;
4323         }
4324
4325         return 0;
4326 }
4327
4328 static int
4329 i40e_pf_get_switch_config(struct i40e_pf *pf)
4330 {
4331         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4332         struct i40e_aqc_get_switch_config_resp *switch_config;
4333         struct i40e_aqc_switch_config_element_resp *element;
4334         uint16_t start_seid = 0, num_reported;
4335         int ret;
4336
4337         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4338                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4339         if (!switch_config) {
4340                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4341                 return -ENOMEM;
4342         }
4343
4344         /* Get the switch configurations */
4345         ret = i40e_aq_get_switch_config(hw, switch_config,
4346                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4347         if (ret != I40E_SUCCESS) {
4348                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4349                 goto fail;
4350         }
4351         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4352         if (num_reported != 1) { /* The number should be 1 */
4353                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4354                 goto fail;
4355         }
4356
4357         /* Parse the switch configuration elements */
4358         element = &(switch_config->element[0]);
4359         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4360                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4361                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4362         } else
4363                 PMD_DRV_LOG(INFO, "Unknown element type");
4364
4365 fail:
4366         rte_free(switch_config);
4367
4368         return ret;
4369 }
4370
4371 static int
4372 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4373                         uint32_t num)
4374 {
4375         struct pool_entry *entry;
4376
4377         if (pool == NULL || num == 0)
4378                 return -EINVAL;
4379
4380         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4381         if (entry == NULL) {
4382                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4383                 return -ENOMEM;
4384         }
4385
4386         /* queue heap initialize */
4387         pool->num_free = num;
4388         pool->num_alloc = 0;
4389         pool->base = base;
4390         LIST_INIT(&pool->alloc_list);
4391         LIST_INIT(&pool->free_list);
4392
4393         /* Initialize element  */
4394         entry->base = 0;
4395         entry->len = num;
4396
4397         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4398         return 0;
4399 }
4400
4401 static void
4402 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4403 {
4404         struct pool_entry *entry, *next_entry;
4405
4406         if (pool == NULL)
4407                 return;
4408
4409         for (entry = LIST_FIRST(&pool->alloc_list);
4410                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4411                         entry = next_entry) {
4412                 LIST_REMOVE(entry, next);
4413                 rte_free(entry);
4414         }
4415
4416         for (entry = LIST_FIRST(&pool->free_list);
4417                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4418                         entry = next_entry) {
4419                 LIST_REMOVE(entry, next);
4420                 rte_free(entry);
4421         }
4422
4423         pool->num_free = 0;
4424         pool->num_alloc = 0;
4425         pool->base = 0;
4426         LIST_INIT(&pool->alloc_list);
4427         LIST_INIT(&pool->free_list);
4428 }
4429
4430 static int
4431 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4432                        uint32_t base)
4433 {
4434         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4435         uint32_t pool_offset;
4436         int insert;
4437
4438         if (pool == NULL) {
4439                 PMD_DRV_LOG(ERR, "Invalid parameter");
4440                 return -EINVAL;
4441         }
4442
4443         pool_offset = base - pool->base;
4444         /* Lookup in alloc list */
4445         LIST_FOREACH(entry, &pool->alloc_list, next) {
4446                 if (entry->base == pool_offset) {
4447                         valid_entry = entry;
4448                         LIST_REMOVE(entry, next);
4449                         break;
4450                 }
4451         }
4452
4453         /* Not find, return */
4454         if (valid_entry == NULL) {
4455                 PMD_DRV_LOG(ERR, "Failed to find entry");
4456                 return -EINVAL;
4457         }
4458
4459         /**
4460          * Found it, move it to free list  and try to merge.
4461          * In order to make merge easier, always sort it by qbase.
4462          * Find adjacent prev and last entries.
4463          */
4464         prev = next = NULL;
4465         LIST_FOREACH(entry, &pool->free_list, next) {
4466                 if (entry->base > valid_entry->base) {
4467                         next = entry;
4468                         break;
4469                 }
4470                 prev = entry;
4471         }
4472
4473         insert = 0;
4474         /* Try to merge with next one*/
4475         if (next != NULL) {
4476                 /* Merge with next one */
4477                 if (valid_entry->base + valid_entry->len == next->base) {
4478                         next->base = valid_entry->base;
4479                         next->len += valid_entry->len;
4480                         rte_free(valid_entry);
4481                         valid_entry = next;
4482                         insert = 1;
4483                 }
4484         }
4485
4486         if (prev != NULL) {
4487                 /* Merge with previous one */
4488                 if (prev->base + prev->len == valid_entry->base) {
4489                         prev->len += valid_entry->len;
4490                         /* If it merge with next one, remove next node */
4491                         if (insert == 1) {
4492                                 LIST_REMOVE(valid_entry, next);
4493                                 rte_free(valid_entry);
4494                         } else {
4495                                 rte_free(valid_entry);
4496                                 insert = 1;
4497                         }
4498                 }
4499         }
4500
4501         /* Not find any entry to merge, insert */
4502         if (insert == 0) {
4503                 if (prev != NULL)
4504                         LIST_INSERT_AFTER(prev, valid_entry, next);
4505                 else if (next != NULL)
4506                         LIST_INSERT_BEFORE(next, valid_entry, next);
4507                 else /* It's empty list, insert to head */
4508                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4509         }
4510
4511         pool->num_free += valid_entry->len;
4512         pool->num_alloc -= valid_entry->len;
4513
4514         return 0;
4515 }
4516
4517 static int
4518 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4519                        uint16_t num)
4520 {
4521         struct pool_entry *entry, *valid_entry;
4522
4523         if (pool == NULL || num == 0) {
4524                 PMD_DRV_LOG(ERR, "Invalid parameter");
4525                 return -EINVAL;
4526         }
4527
4528         if (pool->num_free < num) {
4529                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4530                             num, pool->num_free);
4531                 return -ENOMEM;
4532         }
4533
4534         valid_entry = NULL;
4535         /* Lookup  in free list and find most fit one */
4536         LIST_FOREACH(entry, &pool->free_list, next) {
4537                 if (entry->len >= num) {
4538                         /* Find best one */
4539                         if (entry->len == num) {
4540                                 valid_entry = entry;
4541                                 break;
4542                         }
4543                         if (valid_entry == NULL || valid_entry->len > entry->len)
4544                                 valid_entry = entry;
4545                 }
4546         }
4547
4548         /* Not find one to satisfy the request, return */
4549         if (valid_entry == NULL) {
4550                 PMD_DRV_LOG(ERR, "No valid entry found");
4551                 return -ENOMEM;
4552         }
4553         /**
4554          * The entry have equal queue number as requested,
4555          * remove it from alloc_list.
4556          */
4557         if (valid_entry->len == num) {
4558                 LIST_REMOVE(valid_entry, next);
4559         } else {
4560                 /**
4561                  * The entry have more numbers than requested,
4562                  * create a new entry for alloc_list and minus its
4563                  * queue base and number in free_list.
4564                  */
4565                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4566                 if (entry == NULL) {
4567                         PMD_DRV_LOG(ERR,
4568                                 "Failed to allocate memory for resource pool");
4569                         return -ENOMEM;
4570                 }
4571                 entry->base = valid_entry->base;
4572                 entry->len = num;
4573                 valid_entry->base += num;
4574                 valid_entry->len -= num;
4575                 valid_entry = entry;
4576         }
4577
4578         /* Insert it into alloc list, not sorted */
4579         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4580
4581         pool->num_free -= valid_entry->len;
4582         pool->num_alloc += valid_entry->len;
4583
4584         return valid_entry->base + pool->base;
4585 }
4586
4587 /**
4588  * bitmap_is_subset - Check whether src2 is subset of src1
4589  **/
4590 static inline int
4591 bitmap_is_subset(uint8_t src1, uint8_t src2)
4592 {
4593         return !((src1 ^ src2) & src2);
4594 }
4595
4596 static enum i40e_status_code
4597 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4598 {
4599         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4600
4601         /* If DCB is not supported, only default TC is supported */
4602         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4603                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4604                 return I40E_NOT_SUPPORTED;
4605         }
4606
4607         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4608                 PMD_DRV_LOG(ERR,
4609                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4610                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4611                 return I40E_NOT_SUPPORTED;
4612         }
4613         return I40E_SUCCESS;
4614 }
4615
4616 int
4617 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4618                                 struct i40e_vsi_vlan_pvid_info *info)
4619 {
4620         struct i40e_hw *hw;
4621         struct i40e_vsi_context ctxt;
4622         uint8_t vlan_flags = 0;
4623         int ret;
4624
4625         if (vsi == NULL || info == NULL) {
4626                 PMD_DRV_LOG(ERR, "invalid parameters");
4627                 return I40E_ERR_PARAM;
4628         }
4629
4630         if (info->on) {
4631                 vsi->info.pvid = info->config.pvid;
4632                 /**
4633                  * If insert pvid is enabled, only tagged pkts are
4634                  * allowed to be sent out.
4635                  */
4636                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4637                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4638         } else {
4639                 vsi->info.pvid = 0;
4640                 if (info->config.reject.tagged == 0)
4641                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4642
4643                 if (info->config.reject.untagged == 0)
4644                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4645         }
4646         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4647                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4648         vsi->info.port_vlan_flags |= vlan_flags;
4649         vsi->info.valid_sections =
4650                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4651         memset(&ctxt, 0, sizeof(ctxt));
4652         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4653         ctxt.seid = vsi->seid;
4654
4655         hw = I40E_VSI_TO_HW(vsi);
4656         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4657         if (ret != I40E_SUCCESS)
4658                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4659
4660         return ret;
4661 }
4662
4663 static int
4664 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4665 {
4666         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4667         int i, ret;
4668         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4669
4670         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4671         if (ret != I40E_SUCCESS)
4672                 return ret;
4673
4674         if (!vsi->seid) {
4675                 PMD_DRV_LOG(ERR, "seid not valid");
4676                 return -EINVAL;
4677         }
4678
4679         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4680         tc_bw_data.tc_valid_bits = enabled_tcmap;
4681         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4682                 tc_bw_data.tc_bw_credits[i] =
4683                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4684
4685         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4686         if (ret != I40E_SUCCESS) {
4687                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4688                 return ret;
4689         }
4690
4691         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4692                                         sizeof(vsi->info.qs_handle));
4693         return I40E_SUCCESS;
4694 }
4695
4696 static enum i40e_status_code
4697 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4698                                  struct i40e_aqc_vsi_properties_data *info,
4699                                  uint8_t enabled_tcmap)
4700 {
4701         enum i40e_status_code ret;
4702         int i, total_tc = 0;
4703         uint16_t qpnum_per_tc, bsf, qp_idx;
4704
4705         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4706         if (ret != I40E_SUCCESS)
4707                 return ret;
4708
4709         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4710                 if (enabled_tcmap & (1 << i))
4711                         total_tc++;
4712         if (total_tc == 0)
4713                 total_tc = 1;
4714         vsi->enabled_tc = enabled_tcmap;
4715
4716         /* Number of queues per enabled TC */
4717         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4718         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4719         bsf = rte_bsf32(qpnum_per_tc);
4720
4721         /* Adjust the queue number to actual queues that can be applied */
4722         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4723                 vsi->nb_qps = qpnum_per_tc * total_tc;
4724
4725         /**
4726          * Configure TC and queue mapping parameters, for enabled TC,
4727          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4728          * default queue will serve it.
4729          */
4730         qp_idx = 0;
4731         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4732                 if (vsi->enabled_tc & (1 << i)) {
4733                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4734                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4735                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4736                         qp_idx += qpnum_per_tc;
4737                 } else
4738                         info->tc_mapping[i] = 0;
4739         }
4740
4741         /* Associate queue number with VSI */
4742         if (vsi->type == I40E_VSI_SRIOV) {
4743                 info->mapping_flags |=
4744                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4745                 for (i = 0; i < vsi->nb_qps; i++)
4746                         info->queue_mapping[i] =
4747                                 rte_cpu_to_le_16(vsi->base_queue + i);
4748         } else {
4749                 info->mapping_flags |=
4750                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4751                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4752         }
4753         info->valid_sections |=
4754                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4755
4756         return I40E_SUCCESS;
4757 }
4758
4759 static int
4760 i40e_veb_release(struct i40e_veb *veb)
4761 {
4762         struct i40e_vsi *vsi;
4763         struct i40e_hw *hw;
4764
4765         if (veb == NULL)
4766                 return -EINVAL;
4767
4768         if (!TAILQ_EMPTY(&veb->head)) {
4769                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4770                 return -EACCES;
4771         }
4772         /* associate_vsi field is NULL for floating VEB */
4773         if (veb->associate_vsi != NULL) {
4774                 vsi = veb->associate_vsi;
4775                 hw = I40E_VSI_TO_HW(vsi);
4776
4777                 vsi->uplink_seid = veb->uplink_seid;
4778                 vsi->veb = NULL;
4779         } else {
4780                 veb->associate_pf->main_vsi->floating_veb = NULL;
4781                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4782         }
4783
4784         i40e_aq_delete_element(hw, veb->seid, NULL);
4785         rte_free(veb);
4786         return I40E_SUCCESS;
4787 }
4788
4789 /* Setup a veb */
4790 static struct i40e_veb *
4791 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4792 {
4793         struct i40e_veb *veb;
4794         int ret;
4795         struct i40e_hw *hw;
4796
4797         if (pf == NULL) {
4798                 PMD_DRV_LOG(ERR,
4799                             "veb setup failed, associated PF shouldn't null");
4800                 return NULL;
4801         }
4802         hw = I40E_PF_TO_HW(pf);
4803
4804         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4805         if (!veb) {
4806                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4807                 goto fail;
4808         }
4809
4810         veb->associate_vsi = vsi;
4811         veb->associate_pf = pf;
4812         TAILQ_INIT(&veb->head);
4813         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4814
4815         /* create floating veb if vsi is NULL */
4816         if (vsi != NULL) {
4817                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4818                                       I40E_DEFAULT_TCMAP, false,
4819                                       &veb->seid, false, NULL);
4820         } else {
4821                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4822                                       true, &veb->seid, false, NULL);
4823         }
4824
4825         if (ret != I40E_SUCCESS) {
4826                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4827                             hw->aq.asq_last_status);
4828                 goto fail;
4829         }
4830         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4831
4832         /* get statistics index */
4833         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4834                                 &veb->stats_idx, NULL, NULL, NULL);
4835         if (ret != I40E_SUCCESS) {
4836                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4837                             hw->aq.asq_last_status);
4838                 goto fail;
4839         }
4840         /* Get VEB bandwidth, to be implemented */
4841         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4842         if (vsi)
4843                 vsi->uplink_seid = veb->seid;
4844
4845         return veb;
4846 fail:
4847         rte_free(veb);
4848         return NULL;
4849 }
4850
4851 int
4852 i40e_vsi_release(struct i40e_vsi *vsi)
4853 {
4854         struct i40e_pf *pf;
4855         struct i40e_hw *hw;
4856         struct i40e_vsi_list *vsi_list;
4857         void *temp;
4858         int ret;
4859         struct i40e_mac_filter *f;
4860         uint16_t user_param;
4861
4862         if (!vsi)
4863                 return I40E_SUCCESS;
4864
4865         if (!vsi->adapter)
4866                 return -EFAULT;
4867
4868         user_param = vsi->user_param;
4869
4870         pf = I40E_VSI_TO_PF(vsi);
4871         hw = I40E_VSI_TO_HW(vsi);
4872
4873         /* VSI has child to attach, release child first */
4874         if (vsi->veb) {
4875                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4876                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4877                                 return -1;
4878                 }
4879                 i40e_veb_release(vsi->veb);
4880         }
4881
4882         if (vsi->floating_veb) {
4883                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4884                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4885                                 return -1;
4886                 }
4887         }
4888
4889         /* Remove all macvlan filters of the VSI */
4890         i40e_vsi_remove_all_macvlan_filter(vsi);
4891         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4892                 rte_free(f);
4893
4894         if (vsi->type != I40E_VSI_MAIN &&
4895             ((vsi->type != I40E_VSI_SRIOV) ||
4896             !pf->floating_veb_list[user_param])) {
4897                 /* Remove vsi from parent's sibling list */
4898                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4899                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4900                         return I40E_ERR_PARAM;
4901                 }
4902                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4903                                 &vsi->sib_vsi_list, list);
4904
4905                 /* Remove all switch element of the VSI */
4906                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4907                 if (ret != I40E_SUCCESS)
4908                         PMD_DRV_LOG(ERR, "Failed to delete element");
4909         }
4910
4911         if ((vsi->type == I40E_VSI_SRIOV) &&
4912             pf->floating_veb_list[user_param]) {
4913                 /* Remove vsi from parent's sibling list */
4914                 if (vsi->parent_vsi == NULL ||
4915                     vsi->parent_vsi->floating_veb == NULL) {
4916                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4917                         return I40E_ERR_PARAM;
4918                 }
4919                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4920                              &vsi->sib_vsi_list, list);
4921
4922                 /* Remove all switch element of the VSI */
4923                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4924                 if (ret != I40E_SUCCESS)
4925                         PMD_DRV_LOG(ERR, "Failed to delete element");
4926         }
4927
4928         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4929
4930         if (vsi->type != I40E_VSI_SRIOV)
4931                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4932         rte_free(vsi);
4933
4934         return I40E_SUCCESS;
4935 }
4936
4937 static int
4938 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4939 {
4940         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4941         struct i40e_aqc_remove_macvlan_element_data def_filter;
4942         struct i40e_mac_filter_info filter;
4943         int ret;
4944
4945         if (vsi->type != I40E_VSI_MAIN)
4946                 return I40E_ERR_CONFIG;
4947         memset(&def_filter, 0, sizeof(def_filter));
4948         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4949                                         ETH_ADDR_LEN);
4950         def_filter.vlan_tag = 0;
4951         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4952                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4953         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4954         if (ret != I40E_SUCCESS) {
4955                 struct i40e_mac_filter *f;
4956                 struct ether_addr *mac;
4957
4958                 PMD_DRV_LOG(DEBUG,
4959                             "Cannot remove the default macvlan filter");
4960                 /* It needs to add the permanent mac into mac list */
4961                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4962                 if (f == NULL) {
4963                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4964                         return I40E_ERR_NO_MEMORY;
4965                 }
4966                 mac = &f->mac_info.mac_addr;
4967                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4968                                 ETH_ADDR_LEN);
4969                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4970                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4971                 vsi->mac_num++;
4972
4973                 return ret;
4974         }
4975         rte_memcpy(&filter.mac_addr,
4976                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4977         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4978         return i40e_vsi_add_mac(vsi, &filter);
4979 }
4980
4981 /*
4982  * i40e_vsi_get_bw_config - Query VSI BW Information
4983  * @vsi: the VSI to be queried
4984  *
4985  * Returns 0 on success, negative value on failure
4986  */
4987 static enum i40e_status_code
4988 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4989 {
4990         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4991         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4992         struct i40e_hw *hw = &vsi->adapter->hw;
4993         i40e_status ret;
4994         int i;
4995         uint32_t bw_max;
4996
4997         memset(&bw_config, 0, sizeof(bw_config));
4998         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4999         if (ret != I40E_SUCCESS) {
5000                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5001                             hw->aq.asq_last_status);
5002                 return ret;
5003         }
5004
5005         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5006         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5007                                         &ets_sla_config, NULL);
5008         if (ret != I40E_SUCCESS) {
5009                 PMD_DRV_LOG(ERR,
5010                         "VSI failed to get TC bandwdith configuration %u",
5011                         hw->aq.asq_last_status);
5012                 return ret;
5013         }
5014
5015         /* store and print out BW info */
5016         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5017         vsi->bw_info.bw_max = bw_config.max_bw;
5018         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5019         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5020         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5021                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5022                      I40E_16_BIT_WIDTH);
5023         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5024                 vsi->bw_info.bw_ets_share_credits[i] =
5025                                 ets_sla_config.share_credits[i];
5026                 vsi->bw_info.bw_ets_credits[i] =
5027                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5028                 /* 4 bits per TC, 4th bit is reserved */
5029                 vsi->bw_info.bw_ets_max[i] =
5030                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5031                                   RTE_LEN2MASK(3, uint8_t));
5032                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5033                             vsi->bw_info.bw_ets_share_credits[i]);
5034                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5035                             vsi->bw_info.bw_ets_credits[i]);
5036                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5037                             vsi->bw_info.bw_ets_max[i]);
5038         }
5039
5040         return I40E_SUCCESS;
5041 }
5042
5043 /* i40e_enable_pf_lb
5044  * @pf: pointer to the pf structure
5045  *
5046  * allow loopback on pf
5047  */
5048 static inline void
5049 i40e_enable_pf_lb(struct i40e_pf *pf)
5050 {
5051         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5052         struct i40e_vsi_context ctxt;
5053         int ret;
5054
5055         /* Use the FW API if FW >= v5.0 */
5056         if (hw->aq.fw_maj_ver < 5) {
5057                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5058                 return;
5059         }
5060
5061         memset(&ctxt, 0, sizeof(ctxt));
5062         ctxt.seid = pf->main_vsi_seid;
5063         ctxt.pf_num = hw->pf_id;
5064         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5065         if (ret) {
5066                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5067                             ret, hw->aq.asq_last_status);
5068                 return;
5069         }
5070         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5071         ctxt.info.valid_sections =
5072                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5073         ctxt.info.switch_id |=
5074                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5075
5076         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5077         if (ret)
5078                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5079                             hw->aq.asq_last_status);
5080 }
5081
5082 /* Setup a VSI */
5083 struct i40e_vsi *
5084 i40e_vsi_setup(struct i40e_pf *pf,
5085                enum i40e_vsi_type type,
5086                struct i40e_vsi *uplink_vsi,
5087                uint16_t user_param)
5088 {
5089         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5090         struct i40e_vsi *vsi;
5091         struct i40e_mac_filter_info filter;
5092         int ret;
5093         struct i40e_vsi_context ctxt;
5094         struct ether_addr broadcast =
5095                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5096
5097         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5098             uplink_vsi == NULL) {
5099                 PMD_DRV_LOG(ERR,
5100                         "VSI setup failed, VSI link shouldn't be NULL");
5101                 return NULL;
5102         }
5103
5104         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5105                 PMD_DRV_LOG(ERR,
5106                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5107                 return NULL;
5108         }
5109
5110         /* two situations
5111          * 1.type is not MAIN and uplink vsi is not NULL
5112          * If uplink vsi didn't setup VEB, create one first under veb field
5113          * 2.type is SRIOV and the uplink is NULL
5114          * If floating VEB is NULL, create one veb under floating veb field
5115          */
5116
5117         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5118             uplink_vsi->veb == NULL) {
5119                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5120
5121                 if (uplink_vsi->veb == NULL) {
5122                         PMD_DRV_LOG(ERR, "VEB setup failed");
5123                         return NULL;
5124                 }
5125                 /* set ALLOWLOOPBACk on pf, when veb is created */
5126                 i40e_enable_pf_lb(pf);
5127         }
5128
5129         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5130             pf->main_vsi->floating_veb == NULL) {
5131                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5132
5133                 if (pf->main_vsi->floating_veb == NULL) {
5134                         PMD_DRV_LOG(ERR, "VEB setup failed");
5135                         return NULL;
5136                 }
5137         }
5138
5139         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5140         if (!vsi) {
5141                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5142                 return NULL;
5143         }
5144         TAILQ_INIT(&vsi->mac_list);
5145         vsi->type = type;
5146         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5147         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5148         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5149         vsi->user_param = user_param;
5150         vsi->vlan_anti_spoof_on = 0;
5151         vsi->vlan_filter_on = 0;
5152         /* Allocate queues */
5153         switch (vsi->type) {
5154         case I40E_VSI_MAIN  :
5155                 vsi->nb_qps = pf->lan_nb_qps;
5156                 break;
5157         case I40E_VSI_SRIOV :
5158                 vsi->nb_qps = pf->vf_nb_qps;
5159                 break;
5160         case I40E_VSI_VMDQ2:
5161                 vsi->nb_qps = pf->vmdq_nb_qps;
5162                 break;
5163         case I40E_VSI_FDIR:
5164                 vsi->nb_qps = pf->fdir_nb_qps;
5165                 break;
5166         default:
5167                 goto fail_mem;
5168         }
5169         /*
5170          * The filter status descriptor is reported in rx queue 0,
5171          * while the tx queue for fdir filter programming has no
5172          * such constraints, can be non-zero queues.
5173          * To simplify it, choose FDIR vsi use queue 0 pair.
5174          * To make sure it will use queue 0 pair, queue allocation
5175          * need be done before this function is called
5176          */
5177         if (type != I40E_VSI_FDIR) {
5178                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5179                         if (ret < 0) {
5180                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5181                                                 vsi->seid, ret);
5182                                 goto fail_mem;
5183                         }
5184                         vsi->base_queue = ret;
5185         } else
5186                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5187
5188         /* VF has MSIX interrupt in VF range, don't allocate here */
5189         if (type == I40E_VSI_MAIN) {
5190                 if (pf->support_multi_driver) {
5191                         /* If support multi-driver, need to use INT0 instead of
5192                          * allocating from msix pool. The Msix pool is init from
5193                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5194                          * to 1 without calling i40e_res_pool_alloc.
5195                          */
5196                         vsi->msix_intr = 0;
5197                         vsi->nb_msix = 1;
5198                 } else {
5199                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5200                                                   RTE_MIN(vsi->nb_qps,
5201                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5202                         if (ret < 0) {
5203                                 PMD_DRV_LOG(ERR,
5204                                             "VSI MAIN %d get heap failed %d",
5205                                             vsi->seid, ret);
5206                                 goto fail_queue_alloc;
5207                         }
5208                         vsi->msix_intr = ret;
5209                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5210                                                RTE_MAX_RXTX_INTR_VEC_ID);
5211                 }
5212         } else if (type != I40E_VSI_SRIOV) {
5213                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5214                 if (ret < 0) {
5215                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5216                         goto fail_queue_alloc;
5217                 }
5218                 vsi->msix_intr = ret;
5219                 vsi->nb_msix = 1;
5220         } else {
5221                 vsi->msix_intr = 0;
5222                 vsi->nb_msix = 0;
5223         }
5224
5225         /* Add VSI */
5226         if (type == I40E_VSI_MAIN) {
5227                 /* For main VSI, no need to add since it's default one */
5228                 vsi->uplink_seid = pf->mac_seid;
5229                 vsi->seid = pf->main_vsi_seid;
5230                 /* Bind queues with specific MSIX interrupt */
5231                 /**
5232                  * Needs 2 interrupt at least, one for misc cause which will
5233                  * enabled from OS side, Another for queues binding the
5234                  * interrupt from device side only.
5235                  */
5236
5237                 /* Get default VSI parameters from hardware */
5238                 memset(&ctxt, 0, sizeof(ctxt));
5239                 ctxt.seid = vsi->seid;
5240                 ctxt.pf_num = hw->pf_id;
5241                 ctxt.uplink_seid = vsi->uplink_seid;
5242                 ctxt.vf_num = 0;
5243                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5244                 if (ret != I40E_SUCCESS) {
5245                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5246                         goto fail_msix_alloc;
5247                 }
5248                 rte_memcpy(&vsi->info, &ctxt.info,
5249                         sizeof(struct i40e_aqc_vsi_properties_data));
5250                 vsi->vsi_id = ctxt.vsi_number;
5251                 vsi->info.valid_sections = 0;
5252
5253                 /* Configure tc, enabled TC0 only */
5254                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5255                         I40E_SUCCESS) {
5256                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5257                         goto fail_msix_alloc;
5258                 }
5259
5260                 /* TC, queue mapping */
5261                 memset(&ctxt, 0, sizeof(ctxt));
5262                 vsi->info.valid_sections |=
5263                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5264                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5265                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5266                 rte_memcpy(&ctxt.info, &vsi->info,
5267                         sizeof(struct i40e_aqc_vsi_properties_data));
5268                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5269                                                 I40E_DEFAULT_TCMAP);
5270                 if (ret != I40E_SUCCESS) {
5271                         PMD_DRV_LOG(ERR,
5272                                 "Failed to configure TC queue mapping");
5273                         goto fail_msix_alloc;
5274                 }
5275                 ctxt.seid = vsi->seid;
5276                 ctxt.pf_num = hw->pf_id;
5277                 ctxt.uplink_seid = vsi->uplink_seid;
5278                 ctxt.vf_num = 0;
5279
5280                 /* Update VSI parameters */
5281                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5282                 if (ret != I40E_SUCCESS) {
5283                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5284                         goto fail_msix_alloc;
5285                 }
5286
5287                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5288                                                 sizeof(vsi->info.tc_mapping));
5289                 rte_memcpy(&vsi->info.queue_mapping,
5290                                 &ctxt.info.queue_mapping,
5291                         sizeof(vsi->info.queue_mapping));
5292                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5293                 vsi->info.valid_sections = 0;
5294
5295                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5296                                 ETH_ADDR_LEN);
5297
5298                 /**
5299                  * Updating default filter settings are necessary to prevent
5300                  * reception of tagged packets.
5301                  * Some old firmware configurations load a default macvlan
5302                  * filter which accepts both tagged and untagged packets.
5303                  * The updating is to use a normal filter instead if needed.
5304                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5305                  * The firmware with correct configurations load the default
5306                  * macvlan filter which is expected and cannot be removed.
5307                  */
5308                 i40e_update_default_filter_setting(vsi);
5309                 i40e_config_qinq(hw, vsi);
5310         } else if (type == I40E_VSI_SRIOV) {
5311                 memset(&ctxt, 0, sizeof(ctxt));
5312                 /**
5313                  * For other VSI, the uplink_seid equals to uplink VSI's
5314                  * uplink_seid since they share same VEB
5315                  */
5316                 if (uplink_vsi == NULL)
5317                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5318                 else
5319                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5320                 ctxt.pf_num = hw->pf_id;
5321                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5322                 ctxt.uplink_seid = vsi->uplink_seid;
5323                 ctxt.connection_type = 0x1;
5324                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5325
5326                 /* Use the VEB configuration if FW >= v5.0 */
5327                 if (hw->aq.fw_maj_ver >= 5) {
5328                         /* Configure switch ID */
5329                         ctxt.info.valid_sections |=
5330                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5331                         ctxt.info.switch_id =
5332                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5333                 }
5334
5335                 /* Configure port/vlan */
5336                 ctxt.info.valid_sections |=
5337                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5338                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5339                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5340                                                 hw->func_caps.enabled_tcmap);
5341                 if (ret != I40E_SUCCESS) {
5342                         PMD_DRV_LOG(ERR,
5343                                 "Failed to configure TC queue mapping");
5344                         goto fail_msix_alloc;
5345                 }
5346
5347                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5348                 ctxt.info.valid_sections |=
5349                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5350                 /**
5351                  * Since VSI is not created yet, only configure parameter,
5352                  * will add vsi below.
5353                  */
5354
5355                 i40e_config_qinq(hw, vsi);
5356         } else if (type == I40E_VSI_VMDQ2) {
5357                 memset(&ctxt, 0, sizeof(ctxt));
5358                 /*
5359                  * For other VSI, the uplink_seid equals to uplink VSI's
5360                  * uplink_seid since they share same VEB
5361                  */
5362                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5363                 ctxt.pf_num = hw->pf_id;
5364                 ctxt.vf_num = 0;
5365                 ctxt.uplink_seid = vsi->uplink_seid;
5366                 ctxt.connection_type = 0x1;
5367                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5368
5369                 ctxt.info.valid_sections |=
5370                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5371                 /* user_param carries flag to enable loop back */
5372                 if (user_param) {
5373                         ctxt.info.switch_id =
5374                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5375                         ctxt.info.switch_id |=
5376                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5377                 }
5378
5379                 /* Configure port/vlan */
5380                 ctxt.info.valid_sections |=
5381                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5382                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5383                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5384                                                 I40E_DEFAULT_TCMAP);
5385                 if (ret != I40E_SUCCESS) {
5386                         PMD_DRV_LOG(ERR,
5387                                 "Failed to configure TC queue mapping");
5388                         goto fail_msix_alloc;
5389                 }
5390                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5391                 ctxt.info.valid_sections |=
5392                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5393         } else if (type == I40E_VSI_FDIR) {
5394                 memset(&ctxt, 0, sizeof(ctxt));
5395                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5396                 ctxt.pf_num = hw->pf_id;
5397                 ctxt.vf_num = 0;
5398                 ctxt.uplink_seid = vsi->uplink_seid;
5399                 ctxt.connection_type = 0x1;     /* regular data port */
5400                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5401                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5402                                                 I40E_DEFAULT_TCMAP);
5403                 if (ret != I40E_SUCCESS) {
5404                         PMD_DRV_LOG(ERR,
5405                                 "Failed to configure TC queue mapping.");
5406                         goto fail_msix_alloc;
5407                 }
5408                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5409                 ctxt.info.valid_sections |=
5410                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5411         } else {
5412                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5413                 goto fail_msix_alloc;
5414         }
5415
5416         if (vsi->type != I40E_VSI_MAIN) {
5417                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5418                 if (ret != I40E_SUCCESS) {
5419                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5420                                     hw->aq.asq_last_status);
5421                         goto fail_msix_alloc;
5422                 }
5423                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5424                 vsi->info.valid_sections = 0;
5425                 vsi->seid = ctxt.seid;
5426                 vsi->vsi_id = ctxt.vsi_number;
5427                 vsi->sib_vsi_list.vsi = vsi;
5428                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5429                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5430                                           &vsi->sib_vsi_list, list);
5431                 } else {
5432                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5433                                           &vsi->sib_vsi_list, list);
5434                 }
5435         }
5436
5437         /* MAC/VLAN configuration */
5438         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5439         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5440
5441         ret = i40e_vsi_add_mac(vsi, &filter);
5442         if (ret != I40E_SUCCESS) {
5443                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5444                 goto fail_msix_alloc;
5445         }
5446
5447         /* Get VSI BW information */
5448         i40e_vsi_get_bw_config(vsi);
5449         return vsi;
5450 fail_msix_alloc:
5451         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5452 fail_queue_alloc:
5453         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5454 fail_mem:
5455         rte_free(vsi);
5456         return NULL;
5457 }
5458
5459 /* Configure vlan filter on or off */
5460 int
5461 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5462 {
5463         int i, num;
5464         struct i40e_mac_filter *f;
5465         void *temp;
5466         struct i40e_mac_filter_info *mac_filter;
5467         enum rte_mac_filter_type desired_filter;
5468         int ret = I40E_SUCCESS;
5469
5470         if (on) {
5471                 /* Filter to match MAC and VLAN */
5472                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5473         } else {
5474                 /* Filter to match only MAC */
5475                 desired_filter = RTE_MAC_PERFECT_MATCH;
5476         }
5477
5478         num = vsi->mac_num;
5479
5480         mac_filter = rte_zmalloc("mac_filter_info_data",
5481                                  num * sizeof(*mac_filter), 0);
5482         if (mac_filter == NULL) {
5483                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5484                 return I40E_ERR_NO_MEMORY;
5485         }
5486
5487         i = 0;
5488
5489         /* Remove all existing mac */
5490         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5491                 mac_filter[i] = f->mac_info;
5492                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5493                 if (ret) {
5494                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5495                                     on ? "enable" : "disable");
5496                         goto DONE;
5497                 }
5498                 i++;
5499         }
5500
5501         /* Override with new filter */
5502         for (i = 0; i < num; i++) {
5503                 mac_filter[i].filter_type = desired_filter;
5504                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5505                 if (ret) {
5506                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5507                                     on ? "enable" : "disable");
5508                         goto DONE;
5509                 }
5510         }
5511
5512 DONE:
5513         rte_free(mac_filter);
5514         return ret;
5515 }
5516
5517 /* Configure vlan stripping on or off */
5518 int
5519 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5520 {
5521         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5522         struct i40e_vsi_context ctxt;
5523         uint8_t vlan_flags;
5524         int ret = I40E_SUCCESS;
5525
5526         /* Check if it has been already on or off */
5527         if (vsi->info.valid_sections &
5528                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5529                 if (on) {
5530                         if ((vsi->info.port_vlan_flags &
5531                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5532                                 return 0; /* already on */
5533                 } else {
5534                         if ((vsi->info.port_vlan_flags &
5535                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5536                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5537                                 return 0; /* already off */
5538                 }
5539         }
5540
5541         if (on)
5542                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5543         else
5544                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5545         vsi->info.valid_sections =
5546                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5547         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5548         vsi->info.port_vlan_flags |= vlan_flags;
5549         ctxt.seid = vsi->seid;
5550         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5551         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5552         if (ret)
5553                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5554                             on ? "enable" : "disable");
5555
5556         return ret;
5557 }
5558
5559 static int
5560 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5561 {
5562         struct rte_eth_dev_data *data = dev->data;
5563         int ret;
5564         int mask = 0;
5565
5566         /* Apply vlan offload setting */
5567         mask = ETH_VLAN_STRIP_MASK |
5568                ETH_VLAN_FILTER_MASK |
5569                ETH_VLAN_EXTEND_MASK;
5570         ret = i40e_vlan_offload_set(dev, mask);
5571         if (ret) {
5572                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5573                 return ret;
5574         }
5575
5576         /* Apply pvid setting */
5577         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5578                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5579         if (ret)
5580                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5581
5582         return ret;
5583 }
5584
5585 static int
5586 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5587 {
5588         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5589
5590         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5591 }
5592
5593 static int
5594 i40e_update_flow_control(struct i40e_hw *hw)
5595 {
5596 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5597         struct i40e_link_status link_status;
5598         uint32_t rxfc = 0, txfc = 0, reg;
5599         uint8_t an_info;
5600         int ret;
5601
5602         memset(&link_status, 0, sizeof(link_status));
5603         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5604         if (ret != I40E_SUCCESS) {
5605                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5606                 goto write_reg; /* Disable flow control */
5607         }
5608
5609         an_info = hw->phy.link_info.an_info;
5610         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5611                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5612                 ret = I40E_ERR_NOT_READY;
5613                 goto write_reg; /* Disable flow control */
5614         }
5615         /**
5616          * If link auto negotiation is enabled, flow control needs to
5617          * be configured according to it
5618          */
5619         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5620         case I40E_LINK_PAUSE_RXTX:
5621                 rxfc = 1;
5622                 txfc = 1;
5623                 hw->fc.current_mode = I40E_FC_FULL;
5624                 break;
5625         case I40E_AQ_LINK_PAUSE_RX:
5626                 rxfc = 1;
5627                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5628                 break;
5629         case I40E_AQ_LINK_PAUSE_TX:
5630                 txfc = 1;
5631                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5632                 break;
5633         default:
5634                 hw->fc.current_mode = I40E_FC_NONE;
5635                 break;
5636         }
5637
5638 write_reg:
5639         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5640                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5641         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5642         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5643         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5644         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5645
5646         return ret;
5647 }
5648
5649 /* PF setup */
5650 static int
5651 i40e_pf_setup(struct i40e_pf *pf)
5652 {
5653         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5654         struct i40e_filter_control_settings settings;
5655         struct i40e_vsi *vsi;
5656         int ret;
5657
5658         /* Clear all stats counters */
5659         pf->offset_loaded = FALSE;
5660         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5661         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5662         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5663         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5664
5665         ret = i40e_pf_get_switch_config(pf);
5666         if (ret != I40E_SUCCESS) {
5667                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5668                 return ret;
5669         }
5670         if (pf->flags & I40E_FLAG_FDIR) {
5671                 /* make queue allocated first, let FDIR use queue pair 0*/
5672                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5673                 if (ret != I40E_FDIR_QUEUE_ID) {
5674                         PMD_DRV_LOG(ERR,
5675                                 "queue allocation fails for FDIR: ret =%d",
5676                                 ret);
5677                         pf->flags &= ~I40E_FLAG_FDIR;
5678                 }
5679         }
5680         /*  main VSI setup */
5681         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5682         if (!vsi) {
5683                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5684                 return I40E_ERR_NOT_READY;
5685         }
5686         pf->main_vsi = vsi;
5687
5688         /* Configure filter control */
5689         memset(&settings, 0, sizeof(settings));
5690         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5691                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5692         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5693                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5694         else {
5695                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5696                         hw->func_caps.rss_table_size);
5697                 return I40E_ERR_PARAM;
5698         }
5699         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5700                 hw->func_caps.rss_table_size);
5701         pf->hash_lut_size = hw->func_caps.rss_table_size;
5702
5703         /* Enable ethtype and macvlan filters */
5704         settings.enable_ethtype = TRUE;
5705         settings.enable_macvlan = TRUE;
5706         ret = i40e_set_filter_control(hw, &settings);
5707         if (ret)
5708                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5709                                                                 ret);
5710
5711         /* Update flow control according to the auto negotiation */
5712         i40e_update_flow_control(hw);
5713
5714         return I40E_SUCCESS;
5715 }
5716
5717 int
5718 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5719 {
5720         uint32_t reg;
5721         uint16_t j;
5722
5723         /**
5724          * Set or clear TX Queue Disable flags,
5725          * which is required by hardware.
5726          */
5727         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5728         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5729
5730         /* Wait until the request is finished */
5731         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5732                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5733                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5734                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5735                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5736                                                         & 0x1))) {
5737                         break;
5738                 }
5739         }
5740         if (on) {
5741                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5742                         return I40E_SUCCESS; /* already on, skip next steps */
5743
5744                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5745                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5746         } else {
5747                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5748                         return I40E_SUCCESS; /* already off, skip next steps */
5749                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5750         }
5751         /* Write the register */
5752         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5753         /* Check the result */
5754         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5755                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5756                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5757                 if (on) {
5758                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5759                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5760                                 break;
5761                 } else {
5762                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5763                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5764                                 break;
5765                 }
5766         }
5767         /* Check if it is timeout */
5768         if (j >= I40E_CHK_Q_ENA_COUNT) {
5769                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5770                             (on ? "enable" : "disable"), q_idx);
5771                 return I40E_ERR_TIMEOUT;
5772         }
5773
5774         return I40E_SUCCESS;
5775 }
5776
5777 /* Swith on or off the tx queues */
5778 static int
5779 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5780 {
5781         struct rte_eth_dev_data *dev_data = pf->dev_data;
5782         struct i40e_tx_queue *txq;
5783         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5784         uint16_t i;
5785         int ret;
5786
5787         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5788                 txq = dev_data->tx_queues[i];
5789                 /* Don't operate the queue if not configured or
5790                  * if starting only per queue */
5791                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5792                         continue;
5793                 if (on)
5794                         ret = i40e_dev_tx_queue_start(dev, i);
5795                 else
5796                         ret = i40e_dev_tx_queue_stop(dev, i);
5797                 if ( ret != I40E_SUCCESS)
5798                         return ret;
5799         }
5800
5801         return I40E_SUCCESS;
5802 }
5803
5804 int
5805 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5806 {
5807         uint32_t reg;
5808         uint16_t j;
5809
5810         /* Wait until the request is finished */
5811         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5812                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5813                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5814                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5815                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5816                         break;
5817         }
5818
5819         if (on) {
5820                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5821                         return I40E_SUCCESS; /* Already on, skip next steps */
5822                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5823         } else {
5824                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5825                         return I40E_SUCCESS; /* Already off, skip next steps */
5826                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5827         }
5828
5829         /* Write the register */
5830         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5831         /* Check the result */
5832         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5833                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5834                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5835                 if (on) {
5836                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5837                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5838                                 break;
5839                 } else {
5840                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5841                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5842                                 break;
5843                 }
5844         }
5845
5846         /* Check if it is timeout */
5847         if (j >= I40E_CHK_Q_ENA_COUNT) {
5848                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5849                             (on ? "enable" : "disable"), q_idx);
5850                 return I40E_ERR_TIMEOUT;
5851         }
5852
5853         return I40E_SUCCESS;
5854 }
5855 /* Switch on or off the rx queues */
5856 static int
5857 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5858 {
5859         struct rte_eth_dev_data *dev_data = pf->dev_data;
5860         struct i40e_rx_queue *rxq;
5861         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5862         uint16_t i;
5863         int ret;
5864
5865         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5866                 rxq = dev_data->rx_queues[i];
5867                 /* Don't operate the queue if not configured or
5868                  * if starting only per queue */
5869                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5870                         continue;
5871                 if (on)
5872                         ret = i40e_dev_rx_queue_start(dev, i);
5873                 else
5874                         ret = i40e_dev_rx_queue_stop(dev, i);
5875                 if (ret != I40E_SUCCESS)
5876                         return ret;
5877         }
5878
5879         return I40E_SUCCESS;
5880 }
5881
5882 /* Switch on or off all the rx/tx queues */
5883 int
5884 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5885 {
5886         int ret;
5887
5888         if (on) {
5889                 /* enable rx queues before enabling tx queues */
5890                 ret = i40e_dev_switch_rx_queues(pf, on);
5891                 if (ret) {
5892                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5893                         return ret;
5894                 }
5895                 ret = i40e_dev_switch_tx_queues(pf, on);
5896         } else {
5897                 /* Stop tx queues before stopping rx queues */
5898                 ret = i40e_dev_switch_tx_queues(pf, on);
5899                 if (ret) {
5900                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5901                         return ret;
5902                 }
5903                 ret = i40e_dev_switch_rx_queues(pf, on);
5904         }
5905
5906         return ret;
5907 }
5908
5909 /* Initialize VSI for TX */
5910 static int
5911 i40e_dev_tx_init(struct i40e_pf *pf)
5912 {
5913         struct rte_eth_dev_data *data = pf->dev_data;
5914         uint16_t i;
5915         uint32_t ret = I40E_SUCCESS;
5916         struct i40e_tx_queue *txq;
5917
5918         for (i = 0; i < data->nb_tx_queues; i++) {
5919                 txq = data->tx_queues[i];
5920                 if (!txq || !txq->q_set)
5921                         continue;
5922                 ret = i40e_tx_queue_init(txq);
5923                 if (ret != I40E_SUCCESS)
5924                         break;
5925         }
5926         if (ret == I40E_SUCCESS)
5927                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5928                                      ->eth_dev);
5929
5930         return ret;
5931 }
5932
5933 /* Initialize VSI for RX */
5934 static int
5935 i40e_dev_rx_init(struct i40e_pf *pf)
5936 {
5937         struct rte_eth_dev_data *data = pf->dev_data;
5938         int ret = I40E_SUCCESS;
5939         uint16_t i;
5940         struct i40e_rx_queue *rxq;
5941
5942         i40e_pf_config_mq_rx(pf);
5943         for (i = 0; i < data->nb_rx_queues; i++) {
5944                 rxq = data->rx_queues[i];
5945                 if (!rxq || !rxq->q_set)
5946                         continue;
5947
5948                 ret = i40e_rx_queue_init(rxq);
5949                 if (ret != I40E_SUCCESS) {
5950                         PMD_DRV_LOG(ERR,
5951                                 "Failed to do RX queue initialization");
5952                         break;
5953                 }
5954         }
5955         if (ret == I40E_SUCCESS)
5956                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5957                                      ->eth_dev);
5958
5959         return ret;
5960 }
5961
5962 static int
5963 i40e_dev_rxtx_init(struct i40e_pf *pf)
5964 {
5965         int err;
5966
5967         err = i40e_dev_tx_init(pf);
5968         if (err) {
5969                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5970                 return err;
5971         }
5972         err = i40e_dev_rx_init(pf);
5973         if (err) {
5974                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5975                 return err;
5976         }
5977
5978         return err;
5979 }
5980
5981 static int
5982 i40e_vmdq_setup(struct rte_eth_dev *dev)
5983 {
5984         struct rte_eth_conf *conf = &dev->data->dev_conf;
5985         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5986         int i, err, conf_vsis, j, loop;
5987         struct i40e_vsi *vsi;
5988         struct i40e_vmdq_info *vmdq_info;
5989         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5990         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5991
5992         /*
5993          * Disable interrupt to avoid message from VF. Furthermore, it will
5994          * avoid race condition in VSI creation/destroy.
5995          */
5996         i40e_pf_disable_irq0(hw);
5997
5998         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5999                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6000                 return -ENOTSUP;
6001         }
6002
6003         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6004         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6005                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6006                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6007                         pf->max_nb_vmdq_vsi);
6008                 return -ENOTSUP;
6009         }
6010
6011         if (pf->vmdq != NULL) {
6012                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6013                 return 0;
6014         }
6015
6016         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6017                                 sizeof(*vmdq_info) * conf_vsis, 0);
6018
6019         if (pf->vmdq == NULL) {
6020                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6021                 return -ENOMEM;
6022         }
6023
6024         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6025
6026         /* Create VMDQ VSI */
6027         for (i = 0; i < conf_vsis; i++) {
6028                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6029                                 vmdq_conf->enable_loop_back);
6030                 if (vsi == NULL) {
6031                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6032                         err = -1;
6033                         goto err_vsi_setup;
6034                 }
6035                 vmdq_info = &pf->vmdq[i];
6036                 vmdq_info->pf = pf;
6037                 vmdq_info->vsi = vsi;
6038         }
6039         pf->nb_cfg_vmdq_vsi = conf_vsis;
6040
6041         /* Configure Vlan */
6042         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6043         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6044                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6045                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6046                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6047                                         vmdq_conf->pool_map[i].vlan_id, j);
6048
6049                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6050                                                 vmdq_conf->pool_map[i].vlan_id);
6051                                 if (err) {
6052                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6053                                         err = -1;
6054                                         goto err_vsi_setup;
6055                                 }
6056                         }
6057                 }
6058         }
6059
6060         i40e_pf_enable_irq0(hw);
6061
6062         return 0;
6063
6064 err_vsi_setup:
6065         for (i = 0; i < conf_vsis; i++)
6066                 if (pf->vmdq[i].vsi == NULL)
6067                         break;
6068                 else
6069                         i40e_vsi_release(pf->vmdq[i].vsi);
6070
6071         rte_free(pf->vmdq);
6072         pf->vmdq = NULL;
6073         i40e_pf_enable_irq0(hw);
6074         return err;
6075 }
6076
6077 static void
6078 i40e_stat_update_32(struct i40e_hw *hw,
6079                    uint32_t reg,
6080                    bool offset_loaded,
6081                    uint64_t *offset,
6082                    uint64_t *stat)
6083 {
6084         uint64_t new_data;
6085
6086         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6087         if (!offset_loaded)
6088                 *offset = new_data;
6089
6090         if (new_data >= *offset)
6091                 *stat = (uint64_t)(new_data - *offset);
6092         else
6093                 *stat = (uint64_t)((new_data +
6094                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6095 }
6096
6097 static void
6098 i40e_stat_update_48(struct i40e_hw *hw,
6099                    uint32_t hireg,
6100                    uint32_t loreg,
6101                    bool offset_loaded,
6102                    uint64_t *offset,
6103                    uint64_t *stat)
6104 {
6105         uint64_t new_data;
6106
6107         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6108         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6109                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6110
6111         if (!offset_loaded)
6112                 *offset = new_data;
6113
6114         if (new_data >= *offset)
6115                 *stat = new_data - *offset;
6116         else
6117                 *stat = (uint64_t)((new_data +
6118                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6119
6120         *stat &= I40E_48_BIT_MASK;
6121 }
6122
6123 /* Disable IRQ0 */
6124 void
6125 i40e_pf_disable_irq0(struct i40e_hw *hw)
6126 {
6127         /* Disable all interrupt types */
6128         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6129                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6130         I40E_WRITE_FLUSH(hw);
6131 }
6132
6133 /* Enable IRQ0 */
6134 void
6135 i40e_pf_enable_irq0(struct i40e_hw *hw)
6136 {
6137         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6138                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6139                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6140                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6141         I40E_WRITE_FLUSH(hw);
6142 }
6143
6144 static void
6145 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6146 {
6147         /* read pending request and disable first */
6148         i40e_pf_disable_irq0(hw);
6149         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6150         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6151                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6152
6153         if (no_queue)
6154                 /* Link no queues with irq0 */
6155                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6156                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6157 }
6158
6159 static void
6160 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6161 {
6162         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6163         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6164         int i;
6165         uint16_t abs_vf_id;
6166         uint32_t index, offset, val;
6167
6168         if (!pf->vfs)
6169                 return;
6170         /**
6171          * Try to find which VF trigger a reset, use absolute VF id to access
6172          * since the reg is global register.
6173          */
6174         for (i = 0; i < pf->vf_num; i++) {
6175                 abs_vf_id = hw->func_caps.vf_base_id + i;
6176                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6177                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6178                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6179                 /* VFR event occurred */
6180                 if (val & (0x1 << offset)) {
6181                         int ret;
6182
6183                         /* Clear the event first */
6184                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6185                                                         (0x1 << offset));
6186                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6187                         /**
6188                          * Only notify a VF reset event occurred,
6189                          * don't trigger another SW reset
6190                          */
6191                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6192                         if (ret != I40E_SUCCESS)
6193                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6194                 }
6195         }
6196 }
6197
6198 static void
6199 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6200 {
6201         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6202         int i;
6203
6204         for (i = 0; i < pf->vf_num; i++)
6205                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6206 }
6207
6208 static void
6209 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6210 {
6211         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6212         struct i40e_arq_event_info info;
6213         uint16_t pending, opcode;
6214         int ret;
6215
6216         info.buf_len = I40E_AQ_BUF_SZ;
6217         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6218         if (!info.msg_buf) {
6219                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6220                 return;
6221         }
6222
6223         pending = 1;
6224         while (pending) {
6225                 ret = i40e_clean_arq_element(hw, &info, &pending);
6226
6227                 if (ret != I40E_SUCCESS) {
6228                         PMD_DRV_LOG(INFO,
6229                                 "Failed to read msg from AdminQ, aq_err: %u",
6230                                 hw->aq.asq_last_status);
6231                         break;
6232                 }
6233                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6234
6235                 switch (opcode) {
6236                 case i40e_aqc_opc_send_msg_to_pf:
6237                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6238                         i40e_pf_host_handle_vf_msg(dev,
6239                                         rte_le_to_cpu_16(info.desc.retval),
6240                                         rte_le_to_cpu_32(info.desc.cookie_high),
6241                                         rte_le_to_cpu_32(info.desc.cookie_low),
6242                                         info.msg_buf,
6243                                         info.msg_len);
6244                         break;
6245                 case i40e_aqc_opc_get_link_status:
6246                         ret = i40e_dev_link_update(dev, 0);
6247                         if (!ret)
6248                                 _rte_eth_dev_callback_process(dev,
6249                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6250                         break;
6251                 default:
6252                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6253                                     opcode);
6254                         break;
6255                 }
6256         }
6257         rte_free(info.msg_buf);
6258 }
6259
6260 /**
6261  * Interrupt handler triggered by NIC  for handling
6262  * specific interrupt.
6263  *
6264  * @param handle
6265  *  Pointer to interrupt handle.
6266  * @param param
6267  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6268  *
6269  * @return
6270  *  void
6271  */
6272 static void
6273 i40e_dev_interrupt_handler(void *param)
6274 {
6275         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6276         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6277         uint32_t icr0;
6278
6279         /* Disable interrupt */
6280         i40e_pf_disable_irq0(hw);
6281
6282         /* read out interrupt causes */
6283         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6284
6285         /* No interrupt event indicated */
6286         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6287                 PMD_DRV_LOG(INFO, "No interrupt event");
6288                 goto done;
6289         }
6290         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6291                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6292         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6293                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6294         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6295                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6296         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6297                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6298         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6299                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6300         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6301                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6302         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6303                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6304
6305         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6306                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6307                 i40e_dev_handle_vfr_event(dev);
6308         }
6309         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6310                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6311                 i40e_dev_handle_aq_msg(dev);
6312         }
6313
6314 done:
6315         /* Enable interrupt */
6316         i40e_pf_enable_irq0(hw);
6317         rte_intr_enable(dev->intr_handle);
6318 }
6319
6320 int
6321 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6322                          struct i40e_macvlan_filter *filter,
6323                          int total)
6324 {
6325         int ele_num, ele_buff_size;
6326         int num, actual_num, i;
6327         uint16_t flags;
6328         int ret = I40E_SUCCESS;
6329         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6330         struct i40e_aqc_add_macvlan_element_data *req_list;
6331
6332         if (filter == NULL  || total == 0)
6333                 return I40E_ERR_PARAM;
6334         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6335         ele_buff_size = hw->aq.asq_buf_size;
6336
6337         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6338         if (req_list == NULL) {
6339                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6340                 return I40E_ERR_NO_MEMORY;
6341         }
6342
6343         num = 0;
6344         do {
6345                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6346                 memset(req_list, 0, ele_buff_size);
6347
6348                 for (i = 0; i < actual_num; i++) {
6349                         rte_memcpy(req_list[i].mac_addr,
6350                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6351                         req_list[i].vlan_tag =
6352                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6353
6354                         switch (filter[num + i].filter_type) {
6355                         case RTE_MAC_PERFECT_MATCH:
6356                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6357                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6358                                 break;
6359                         case RTE_MACVLAN_PERFECT_MATCH:
6360                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6361                                 break;
6362                         case RTE_MAC_HASH_MATCH:
6363                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6364                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6365                                 break;
6366                         case RTE_MACVLAN_HASH_MATCH:
6367                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6368                                 break;
6369                         default:
6370                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6371                                 ret = I40E_ERR_PARAM;
6372                                 goto DONE;
6373                         }
6374
6375                         req_list[i].queue_number = 0;
6376
6377                         req_list[i].flags = rte_cpu_to_le_16(flags);
6378                 }
6379
6380                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6381                                                 actual_num, NULL);
6382                 if (ret != I40E_SUCCESS) {
6383                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6384                         goto DONE;
6385                 }
6386                 num += actual_num;
6387         } while (num < total);
6388
6389 DONE:
6390         rte_free(req_list);
6391         return ret;
6392 }
6393
6394 int
6395 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6396                             struct i40e_macvlan_filter *filter,
6397                             int total)
6398 {
6399         int ele_num, ele_buff_size;
6400         int num, actual_num, i;
6401         uint16_t flags;
6402         int ret = I40E_SUCCESS;
6403         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6404         struct i40e_aqc_remove_macvlan_element_data *req_list;
6405
6406         if (filter == NULL  || total == 0)
6407                 return I40E_ERR_PARAM;
6408
6409         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6410         ele_buff_size = hw->aq.asq_buf_size;
6411
6412         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6413         if (req_list == NULL) {
6414                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6415                 return I40E_ERR_NO_MEMORY;
6416         }
6417
6418         num = 0;
6419         do {
6420                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6421                 memset(req_list, 0, ele_buff_size);
6422
6423                 for (i = 0; i < actual_num; i++) {
6424                         rte_memcpy(req_list[i].mac_addr,
6425                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6426                         req_list[i].vlan_tag =
6427                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6428
6429                         switch (filter[num + i].filter_type) {
6430                         case RTE_MAC_PERFECT_MATCH:
6431                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6432                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6433                                 break;
6434                         case RTE_MACVLAN_PERFECT_MATCH:
6435                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6436                                 break;
6437                         case RTE_MAC_HASH_MATCH:
6438                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6439                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6440                                 break;
6441                         case RTE_MACVLAN_HASH_MATCH:
6442                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6443                                 break;
6444                         default:
6445                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6446                                 ret = I40E_ERR_PARAM;
6447                                 goto DONE;
6448                         }
6449                         req_list[i].flags = rte_cpu_to_le_16(flags);
6450                 }
6451
6452                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6453                                                 actual_num, NULL);
6454                 if (ret != I40E_SUCCESS) {
6455                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6456                         goto DONE;
6457                 }
6458                 num += actual_num;
6459         } while (num < total);
6460
6461 DONE:
6462         rte_free(req_list);
6463         return ret;
6464 }
6465
6466 /* Find out specific MAC filter */
6467 static struct i40e_mac_filter *
6468 i40e_find_mac_filter(struct i40e_vsi *vsi,
6469                          struct ether_addr *macaddr)
6470 {
6471         struct i40e_mac_filter *f;
6472
6473         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6474                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6475                         return f;
6476         }
6477
6478         return NULL;
6479 }
6480
6481 static bool
6482 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6483                          uint16_t vlan_id)
6484 {
6485         uint32_t vid_idx, vid_bit;
6486
6487         if (vlan_id > ETH_VLAN_ID_MAX)
6488                 return 0;
6489
6490         vid_idx = I40E_VFTA_IDX(vlan_id);
6491         vid_bit = I40E_VFTA_BIT(vlan_id);
6492
6493         if (vsi->vfta[vid_idx] & vid_bit)
6494                 return 1;
6495         else
6496                 return 0;
6497 }
6498
6499 static void
6500 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6501                        uint16_t vlan_id, bool on)
6502 {
6503         uint32_t vid_idx, vid_bit;
6504
6505         vid_idx = I40E_VFTA_IDX(vlan_id);
6506         vid_bit = I40E_VFTA_BIT(vlan_id);
6507
6508         if (on)
6509                 vsi->vfta[vid_idx] |= vid_bit;
6510         else
6511                 vsi->vfta[vid_idx] &= ~vid_bit;
6512 }
6513
6514 void
6515 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6516                      uint16_t vlan_id, bool on)
6517 {
6518         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6519         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6520         int ret;
6521
6522         if (vlan_id > ETH_VLAN_ID_MAX)
6523                 return;
6524
6525         i40e_store_vlan_filter(vsi, vlan_id, on);
6526
6527         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6528                 return;
6529
6530         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6531
6532         if (on) {
6533                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6534                                        &vlan_data, 1, NULL);
6535                 if (ret != I40E_SUCCESS)
6536                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6537         } else {
6538                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6539                                           &vlan_data, 1, NULL);
6540                 if (ret != I40E_SUCCESS)
6541                         PMD_DRV_LOG(ERR,
6542                                     "Failed to remove vlan filter");
6543         }
6544 }
6545
6546 /**
6547  * Find all vlan options for specific mac addr,
6548  * return with actual vlan found.
6549  */
6550 int
6551 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6552                            struct i40e_macvlan_filter *mv_f,
6553                            int num, struct ether_addr *addr)
6554 {
6555         int i;
6556         uint32_t j, k;
6557
6558         /**
6559          * Not to use i40e_find_vlan_filter to decrease the loop time,
6560          * although the code looks complex.
6561           */
6562         if (num < vsi->vlan_num)
6563                 return I40E_ERR_PARAM;
6564
6565         i = 0;
6566         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6567                 if (vsi->vfta[j]) {
6568                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6569                                 if (vsi->vfta[j] & (1 << k)) {
6570                                         if (i > num - 1) {
6571                                                 PMD_DRV_LOG(ERR,
6572                                                         "vlan number doesn't match");
6573                                                 return I40E_ERR_PARAM;
6574                                         }
6575                                         rte_memcpy(&mv_f[i].macaddr,
6576                                                         addr, ETH_ADDR_LEN);
6577                                         mv_f[i].vlan_id =
6578                                                 j * I40E_UINT32_BIT_SIZE + k;
6579                                         i++;
6580                                 }
6581                         }
6582                 }
6583         }
6584         return I40E_SUCCESS;
6585 }
6586
6587 static inline int
6588 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6589                            struct i40e_macvlan_filter *mv_f,
6590                            int num,
6591                            uint16_t vlan)
6592 {
6593         int i = 0;
6594         struct i40e_mac_filter *f;
6595
6596         if (num < vsi->mac_num)
6597                 return I40E_ERR_PARAM;
6598
6599         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6600                 if (i > num - 1) {
6601                         PMD_DRV_LOG(ERR, "buffer number not match");
6602                         return I40E_ERR_PARAM;
6603                 }
6604                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6605                                 ETH_ADDR_LEN);
6606                 mv_f[i].vlan_id = vlan;
6607                 mv_f[i].filter_type = f->mac_info.filter_type;
6608                 i++;
6609         }
6610
6611         return I40E_SUCCESS;
6612 }
6613
6614 static int
6615 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6616 {
6617         int i, j, num;
6618         struct i40e_mac_filter *f;
6619         struct i40e_macvlan_filter *mv_f;
6620         int ret = I40E_SUCCESS;
6621
6622         if (vsi == NULL || vsi->mac_num == 0)
6623                 return I40E_ERR_PARAM;
6624
6625         /* Case that no vlan is set */
6626         if (vsi->vlan_num == 0)
6627                 num = vsi->mac_num;
6628         else
6629                 num = vsi->mac_num * vsi->vlan_num;
6630
6631         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6632         if (mv_f == NULL) {
6633                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6634                 return I40E_ERR_NO_MEMORY;
6635         }
6636
6637         i = 0;
6638         if (vsi->vlan_num == 0) {
6639                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6640                         rte_memcpy(&mv_f[i].macaddr,
6641                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6642                         mv_f[i].filter_type = f->mac_info.filter_type;
6643                         mv_f[i].vlan_id = 0;
6644                         i++;
6645                 }
6646         } else {
6647                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6648                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6649                                         vsi->vlan_num, &f->mac_info.mac_addr);
6650                         if (ret != I40E_SUCCESS)
6651                                 goto DONE;
6652                         for (j = i; j < i + vsi->vlan_num; j++)
6653                                 mv_f[j].filter_type = f->mac_info.filter_type;
6654                         i += vsi->vlan_num;
6655                 }
6656         }
6657
6658         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6659 DONE:
6660         rte_free(mv_f);
6661
6662         return ret;
6663 }
6664
6665 int
6666 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6667 {
6668         struct i40e_macvlan_filter *mv_f;
6669         int mac_num;
6670         int ret = I40E_SUCCESS;
6671
6672         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6673                 return I40E_ERR_PARAM;
6674
6675         /* If it's already set, just return */
6676         if (i40e_find_vlan_filter(vsi,vlan))
6677                 return I40E_SUCCESS;
6678
6679         mac_num = vsi->mac_num;
6680
6681         if (mac_num == 0) {
6682                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6683                 return I40E_ERR_PARAM;
6684         }
6685
6686         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6687
6688         if (mv_f == NULL) {
6689                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6690                 return I40E_ERR_NO_MEMORY;
6691         }
6692
6693         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6694
6695         if (ret != I40E_SUCCESS)
6696                 goto DONE;
6697
6698         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6699
6700         if (ret != I40E_SUCCESS)
6701                 goto DONE;
6702
6703         i40e_set_vlan_filter(vsi, vlan, 1);
6704
6705         vsi->vlan_num++;
6706         ret = I40E_SUCCESS;
6707 DONE:
6708         rte_free(mv_f);
6709         return ret;
6710 }
6711
6712 int
6713 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6714 {
6715         struct i40e_macvlan_filter *mv_f;
6716         int mac_num;
6717         int ret = I40E_SUCCESS;
6718
6719         /**
6720          * Vlan 0 is the generic filter for untagged packets
6721          * and can't be removed.
6722          */
6723         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6724                 return I40E_ERR_PARAM;
6725
6726         /* If can't find it, just return */
6727         if (!i40e_find_vlan_filter(vsi, vlan))
6728                 return I40E_ERR_PARAM;
6729
6730         mac_num = vsi->mac_num;
6731
6732         if (mac_num == 0) {
6733                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6734                 return I40E_ERR_PARAM;
6735         }
6736
6737         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6738
6739         if (mv_f == NULL) {
6740                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6741                 return I40E_ERR_NO_MEMORY;
6742         }
6743
6744         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6745
6746         if (ret != I40E_SUCCESS)
6747                 goto DONE;
6748
6749         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6750
6751         if (ret != I40E_SUCCESS)
6752                 goto DONE;
6753
6754         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6755         if (vsi->vlan_num == 1) {
6756                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6757                 if (ret != I40E_SUCCESS)
6758                         goto DONE;
6759
6760                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6761                 if (ret != I40E_SUCCESS)
6762                         goto DONE;
6763         }
6764
6765         i40e_set_vlan_filter(vsi, vlan, 0);
6766
6767         vsi->vlan_num--;
6768         ret = I40E_SUCCESS;
6769 DONE:
6770         rte_free(mv_f);
6771         return ret;
6772 }
6773
6774 int
6775 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6776 {
6777         struct i40e_mac_filter *f;
6778         struct i40e_macvlan_filter *mv_f;
6779         int i, vlan_num = 0;
6780         int ret = I40E_SUCCESS;
6781
6782         /* If it's add and we've config it, return */
6783         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6784         if (f != NULL)
6785                 return I40E_SUCCESS;
6786         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6787                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6788
6789                 /**
6790                  * If vlan_num is 0, that's the first time to add mac,
6791                  * set mask for vlan_id 0.
6792                  */
6793                 if (vsi->vlan_num == 0) {
6794                         i40e_set_vlan_filter(vsi, 0, 1);
6795                         vsi->vlan_num = 1;
6796                 }
6797                 vlan_num = vsi->vlan_num;
6798         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6799                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6800                 vlan_num = 1;
6801
6802         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6803         if (mv_f == NULL) {
6804                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6805                 return I40E_ERR_NO_MEMORY;
6806         }
6807
6808         for (i = 0; i < vlan_num; i++) {
6809                 mv_f[i].filter_type = mac_filter->filter_type;
6810                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6811                                 ETH_ADDR_LEN);
6812         }
6813
6814         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6815                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6816                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6817                                         &mac_filter->mac_addr);
6818                 if (ret != I40E_SUCCESS)
6819                         goto DONE;
6820         }
6821
6822         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6823         if (ret != I40E_SUCCESS)
6824                 goto DONE;
6825
6826         /* Add the mac addr into mac list */
6827         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6828         if (f == NULL) {
6829                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6830                 ret = I40E_ERR_NO_MEMORY;
6831                 goto DONE;
6832         }
6833         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6834                         ETH_ADDR_LEN);
6835         f->mac_info.filter_type = mac_filter->filter_type;
6836         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6837         vsi->mac_num++;
6838
6839         ret = I40E_SUCCESS;
6840 DONE:
6841         rte_free(mv_f);
6842
6843         return ret;
6844 }
6845
6846 int
6847 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6848 {
6849         struct i40e_mac_filter *f;
6850         struct i40e_macvlan_filter *mv_f;
6851         int i, vlan_num;
6852         enum rte_mac_filter_type filter_type;
6853         int ret = I40E_SUCCESS;
6854
6855         /* Can't find it, return an error */
6856         f = i40e_find_mac_filter(vsi, addr);
6857         if (f == NULL)
6858                 return I40E_ERR_PARAM;
6859
6860         vlan_num = vsi->vlan_num;
6861         filter_type = f->mac_info.filter_type;
6862         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6863                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6864                 if (vlan_num == 0) {
6865                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6866                         return I40E_ERR_PARAM;
6867                 }
6868         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6869                         filter_type == RTE_MAC_HASH_MATCH)
6870                 vlan_num = 1;
6871
6872         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6873         if (mv_f == NULL) {
6874                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6875                 return I40E_ERR_NO_MEMORY;
6876         }
6877
6878         for (i = 0; i < vlan_num; i++) {
6879                 mv_f[i].filter_type = filter_type;
6880                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6881                                 ETH_ADDR_LEN);
6882         }
6883         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6884                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6885                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6886                 if (ret != I40E_SUCCESS)
6887                         goto DONE;
6888         }
6889
6890         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6891         if (ret != I40E_SUCCESS)
6892                 goto DONE;
6893
6894         /* Remove the mac addr into mac list */
6895         TAILQ_REMOVE(&vsi->mac_list, f, next);
6896         rte_free(f);
6897         vsi->mac_num--;
6898
6899         ret = I40E_SUCCESS;
6900 DONE:
6901         rte_free(mv_f);
6902         return ret;
6903 }
6904
6905 /* Configure hash enable flags for RSS */
6906 uint64_t
6907 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6908 {
6909         uint64_t hena = 0;
6910         int i;
6911
6912         if (!flags)
6913                 return hena;
6914
6915         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6916                 if (flags & (1ULL << i))
6917                         hena |= adapter->pctypes_tbl[i];
6918         }
6919
6920         return hena;
6921 }
6922
6923 /* Parse the hash enable flags */
6924 uint64_t
6925 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6926 {
6927         uint64_t rss_hf = 0;
6928
6929         if (!flags)
6930                 return rss_hf;
6931         int i;
6932
6933         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6934                 if (flags & adapter->pctypes_tbl[i])
6935                         rss_hf |= (1ULL << i);
6936         }
6937         return rss_hf;
6938 }
6939
6940 /* Disable RSS */
6941 static void
6942 i40e_pf_disable_rss(struct i40e_pf *pf)
6943 {
6944         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6945
6946         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6947         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6948         I40E_WRITE_FLUSH(hw);
6949 }
6950
6951 int
6952 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6953 {
6954         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6955         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6956         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
6957                            I40E_VFQF_HKEY_MAX_INDEX :
6958                            I40E_PFQF_HKEY_MAX_INDEX;
6959         int ret = 0;
6960
6961         if (!key || key_len == 0) {
6962                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6963                 return 0;
6964         } else if (key_len != (key_idx + 1) *
6965                 sizeof(uint32_t)) {
6966                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6967                 return -EINVAL;
6968         }
6969
6970         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6971                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6972                         (struct i40e_aqc_get_set_rss_key_data *)key;
6973
6974                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6975                 if (ret)
6976                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6977         } else {
6978                 uint32_t *hash_key = (uint32_t *)key;
6979                 uint16_t i;
6980
6981                 if (vsi->type == I40E_VSI_SRIOV) {
6982                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
6983                                 I40E_WRITE_REG(
6984                                         hw,
6985                                         I40E_VFQF_HKEY1(i, vsi->user_param),
6986                                         hash_key[i]);
6987
6988                 } else {
6989                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6990                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
6991                                                hash_key[i]);
6992                 }
6993                 I40E_WRITE_FLUSH(hw);
6994         }
6995
6996         return ret;
6997 }
6998
6999 static int
7000 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7001 {
7002         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7003         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7004         uint32_t reg;
7005         int ret;
7006
7007         if (!key || !key_len)
7008                 return -EINVAL;
7009
7010         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7011                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7012                         (struct i40e_aqc_get_set_rss_key_data *)key);
7013                 if (ret) {
7014                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7015                         return ret;
7016                 }
7017         } else {
7018                 uint32_t *key_dw = (uint32_t *)key;
7019                 uint16_t i;
7020
7021                 if (vsi->type == I40E_VSI_SRIOV) {
7022                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7023                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7024                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7025                         }
7026                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7027                                    sizeof(uint32_t);
7028                 } else {
7029                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7030                                 reg = I40E_PFQF_HKEY(i);
7031                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7032                         }
7033                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7034                                    sizeof(uint32_t);
7035                 }
7036         }
7037         return 0;
7038 }
7039
7040 static int
7041 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7042 {
7043         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7044         uint64_t hena;
7045         int ret;
7046
7047         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7048                                rss_conf->rss_key_len);
7049         if (ret)
7050                 return ret;
7051
7052         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7053         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7054         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7055         I40E_WRITE_FLUSH(hw);
7056
7057         return 0;
7058 }
7059
7060 static int
7061 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7062                          struct rte_eth_rss_conf *rss_conf)
7063 {
7064         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7065         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7066         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7067         uint64_t hena;
7068
7069         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7070         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7071
7072         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7073                 if (rss_hf != 0) /* Enable RSS */
7074                         return -EINVAL;
7075                 return 0; /* Nothing to do */
7076         }
7077         /* RSS enabled */
7078         if (rss_hf == 0) /* Disable RSS */
7079                 return -EINVAL;
7080
7081         return i40e_hw_rss_hash_set(pf, rss_conf);
7082 }
7083
7084 static int
7085 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7086                            struct rte_eth_rss_conf *rss_conf)
7087 {
7088         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7089         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7090         uint64_t hena;
7091
7092         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7093                          &rss_conf->rss_key_len);
7094
7095         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7096         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7097         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7098
7099         return 0;
7100 }
7101
7102 static int
7103 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7104 {
7105         switch (filter_type) {
7106         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7107                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7108                 break;
7109         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7110                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7111                 break;
7112         case RTE_TUNNEL_FILTER_IMAC_TENID:
7113                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7114                 break;
7115         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7116                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7117                 break;
7118         case ETH_TUNNEL_FILTER_IMAC:
7119                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7120                 break;
7121         case ETH_TUNNEL_FILTER_OIP:
7122                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7123                 break;
7124         case ETH_TUNNEL_FILTER_IIP:
7125                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7126                 break;
7127         default:
7128                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7129                 return -EINVAL;
7130         }
7131
7132         return 0;
7133 }
7134
7135 /* Convert tunnel filter structure */
7136 static int
7137 i40e_tunnel_filter_convert(
7138         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7139         struct i40e_tunnel_filter *tunnel_filter)
7140 {
7141         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7142                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7143         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7144                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7145         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7146         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7147              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7148             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7149                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7150         else
7151                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7152         tunnel_filter->input.flags = cld_filter->element.flags;
7153         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7154         tunnel_filter->queue = cld_filter->element.queue_number;
7155         rte_memcpy(tunnel_filter->input.general_fields,
7156                    cld_filter->general_fields,
7157                    sizeof(cld_filter->general_fields));
7158
7159         return 0;
7160 }
7161
7162 /* Check if there exists the tunnel filter */
7163 struct i40e_tunnel_filter *
7164 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7165                              const struct i40e_tunnel_filter_input *input)
7166 {
7167         int ret;
7168
7169         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7170         if (ret < 0)
7171                 return NULL;
7172
7173         return tunnel_rule->hash_map[ret];
7174 }
7175
7176 /* Add a tunnel filter into the SW list */
7177 static int
7178 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7179                              struct i40e_tunnel_filter *tunnel_filter)
7180 {
7181         struct i40e_tunnel_rule *rule = &pf->tunnel;
7182         int ret;
7183
7184         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7185         if (ret < 0) {
7186                 PMD_DRV_LOG(ERR,
7187                             "Failed to insert tunnel filter to hash table %d!",
7188                             ret);
7189                 return ret;
7190         }
7191         rule->hash_map[ret] = tunnel_filter;
7192
7193         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7194
7195         return 0;
7196 }
7197
7198 /* Delete a tunnel filter from the SW list */
7199 int
7200 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7201                           struct i40e_tunnel_filter_input *input)
7202 {
7203         struct i40e_tunnel_rule *rule = &pf->tunnel;
7204         struct i40e_tunnel_filter *tunnel_filter;
7205         int ret;
7206
7207         ret = rte_hash_del_key(rule->hash_table, input);
7208         if (ret < 0) {
7209                 PMD_DRV_LOG(ERR,
7210                             "Failed to delete tunnel filter to hash table %d!",
7211                             ret);
7212                 return ret;
7213         }
7214         tunnel_filter = rule->hash_map[ret];
7215         rule->hash_map[ret] = NULL;
7216
7217         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7218         rte_free(tunnel_filter);
7219
7220         return 0;
7221 }
7222
7223 int
7224 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7225                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7226                         uint8_t add)
7227 {
7228         uint16_t ip_type;
7229         uint32_t ipv4_addr, ipv4_addr_le;
7230         uint8_t i, tun_type = 0;
7231         /* internal varialbe to convert ipv6 byte order */
7232         uint32_t convert_ipv6[4];
7233         int val, ret = 0;
7234         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7235         struct i40e_vsi *vsi = pf->main_vsi;
7236         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7237         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7238         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7239         struct i40e_tunnel_filter *tunnel, *node;
7240         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7241
7242         cld_filter = rte_zmalloc("tunnel_filter",
7243                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7244         0);
7245
7246         if (NULL == cld_filter) {
7247                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7248                 return -ENOMEM;
7249         }
7250         pfilter = cld_filter;
7251
7252         ether_addr_copy(&tunnel_filter->outer_mac,
7253                         (struct ether_addr *)&pfilter->element.outer_mac);
7254         ether_addr_copy(&tunnel_filter->inner_mac,
7255                         (struct ether_addr *)&pfilter->element.inner_mac);
7256
7257         pfilter->element.inner_vlan =
7258                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7259         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7260                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7261                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7262                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7263                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7264                                 &ipv4_addr_le,
7265                                 sizeof(pfilter->element.ipaddr.v4.data));
7266         } else {
7267                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7268                 for (i = 0; i < 4; i++) {
7269                         convert_ipv6[i] =
7270                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7271                 }
7272                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7273                            &convert_ipv6,
7274                            sizeof(pfilter->element.ipaddr.v6.data));
7275         }
7276
7277         /* check tunneled type */
7278         switch (tunnel_filter->tunnel_type) {
7279         case RTE_TUNNEL_TYPE_VXLAN:
7280                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7281                 break;
7282         case RTE_TUNNEL_TYPE_NVGRE:
7283                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7284                 break;
7285         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7286                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7287                 break;
7288         default:
7289                 /* Other tunnel types is not supported. */
7290                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7291                 rte_free(cld_filter);
7292                 return -EINVAL;
7293         }
7294
7295         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7296                                        &pfilter->element.flags);
7297         if (val < 0) {
7298                 rte_free(cld_filter);
7299                 return -EINVAL;
7300         }
7301
7302         pfilter->element.flags |= rte_cpu_to_le_16(
7303                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7304                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7305         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7306         pfilter->element.queue_number =
7307                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7308
7309         /* Check if there is the filter in SW list */
7310         memset(&check_filter, 0, sizeof(check_filter));
7311         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7312         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7313         if (add && node) {
7314                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7315                 rte_free(cld_filter);
7316                 return -EINVAL;
7317         }
7318
7319         if (!add && !node) {
7320                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7321                 rte_free(cld_filter);
7322                 return -EINVAL;
7323         }
7324
7325         if (add) {
7326                 ret = i40e_aq_add_cloud_filters(hw,
7327                                         vsi->seid, &cld_filter->element, 1);
7328                 if (ret < 0) {
7329                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7330                         rte_free(cld_filter);
7331                         return -ENOTSUP;
7332                 }
7333                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7334                 if (tunnel == NULL) {
7335                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7336                         rte_free(cld_filter);
7337                         return -ENOMEM;
7338                 }
7339
7340                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7341                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7342                 if (ret < 0)
7343                         rte_free(tunnel);
7344         } else {
7345                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7346                                                    &cld_filter->element, 1);
7347                 if (ret < 0) {
7348                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7349                         rte_free(cld_filter);
7350                         return -ENOTSUP;
7351                 }
7352                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7353         }
7354
7355         rte_free(cld_filter);
7356         return ret;
7357 }
7358
7359 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7360 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7361 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7362 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7363 #define I40E_TR_GRE_KEY_MASK                    0x400
7364 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7365 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7366
7367 static enum
7368 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7369 {
7370         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7371         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7372         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7373         enum i40e_status_code status = I40E_SUCCESS;
7374
7375         if (pf->support_multi_driver) {
7376                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7377                 return I40E_NOT_SUPPORTED;
7378         }
7379
7380         memset(&filter_replace, 0,
7381                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7382         memset(&filter_replace_buf, 0,
7383                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7384
7385         /* create L1 filter */
7386         filter_replace.old_filter_type =
7387                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7388         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7389         filter_replace.tr_bit = 0;
7390
7391         /* Prepare the buffer, 3 entries */
7392         filter_replace_buf.data[0] =
7393                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7394         filter_replace_buf.data[0] |=
7395                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7396         filter_replace_buf.data[2] = 0xFF;
7397         filter_replace_buf.data[3] = 0xFF;
7398         filter_replace_buf.data[4] =
7399                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7400         filter_replace_buf.data[4] |=
7401                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7402         filter_replace_buf.data[7] = 0xF0;
7403         filter_replace_buf.data[8]
7404                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7405         filter_replace_buf.data[8] |=
7406                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7407         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7408                 I40E_TR_GENEVE_KEY_MASK |
7409                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7410         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7411                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7412                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7413
7414         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7415                                                &filter_replace_buf);
7416         if (!status) {
7417                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7418                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7419                             "cloud l1 type is changed from 0x%x to 0x%x",
7420                             filter_replace.old_filter_type,
7421                             filter_replace.new_filter_type);
7422         }
7423         return status;
7424 }
7425
7426 static enum
7427 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7428 {
7429         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7430         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7431         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7432         enum i40e_status_code status = I40E_SUCCESS;
7433
7434         if (pf->support_multi_driver) {
7435                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7436                 return I40E_NOT_SUPPORTED;
7437         }
7438
7439         /* For MPLSoUDP */
7440         memset(&filter_replace, 0,
7441                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7442         memset(&filter_replace_buf, 0,
7443                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7444         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7445                 I40E_AQC_MIRROR_CLOUD_FILTER;
7446         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7447         filter_replace.new_filter_type =
7448                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7449         /* Prepare the buffer, 2 entries */
7450         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7451         filter_replace_buf.data[0] |=
7452                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7453         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7454         filter_replace_buf.data[4] |=
7455                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7456         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7457                                                &filter_replace_buf);
7458         if (status < 0)
7459                 return status;
7460         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7461                     "cloud filter type is changed from 0x%x to 0x%x",
7462                     filter_replace.old_filter_type,
7463                     filter_replace.new_filter_type);
7464
7465         /* For MPLSoGRE */
7466         memset(&filter_replace, 0,
7467                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7468         memset(&filter_replace_buf, 0,
7469                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7470
7471         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7472                 I40E_AQC_MIRROR_CLOUD_FILTER;
7473         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7474         filter_replace.new_filter_type =
7475                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7476         /* Prepare the buffer, 2 entries */
7477         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7478         filter_replace_buf.data[0] |=
7479                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7480         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7481         filter_replace_buf.data[4] |=
7482                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7483
7484         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7485                                                &filter_replace_buf);
7486         if (!status) {
7487                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7488                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7489                             "cloud filter type is changed from 0x%x to 0x%x",
7490                             filter_replace.old_filter_type,
7491                             filter_replace.new_filter_type);
7492         }
7493         return status;
7494 }
7495
7496 static enum i40e_status_code
7497 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7498 {
7499         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7500         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7501         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7502         enum i40e_status_code status = I40E_SUCCESS;
7503
7504         if (pf->support_multi_driver) {
7505                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7506                 return I40E_NOT_SUPPORTED;
7507         }
7508
7509         /* For GTP-C */
7510         memset(&filter_replace, 0,
7511                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7512         memset(&filter_replace_buf, 0,
7513                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7514         /* create L1 filter */
7515         filter_replace.old_filter_type =
7516                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7517         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7518         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7519                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7520         /* Prepare the buffer, 2 entries */
7521         filter_replace_buf.data[0] =
7522                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7523         filter_replace_buf.data[0] |=
7524                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7525         filter_replace_buf.data[2] = 0xFF;
7526         filter_replace_buf.data[3] = 0xFF;
7527         filter_replace_buf.data[4] =
7528                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7529         filter_replace_buf.data[4] |=
7530                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7531         filter_replace_buf.data[6] = 0xFF;
7532         filter_replace_buf.data[7] = 0xFF;
7533         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7534                                                &filter_replace_buf);
7535         if (status < 0)
7536                 return status;
7537         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7538                     "cloud l1 type is changed from 0x%x to 0x%x",
7539                     filter_replace.old_filter_type,
7540                     filter_replace.new_filter_type);
7541
7542         /* for GTP-U */
7543         memset(&filter_replace, 0,
7544                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7545         memset(&filter_replace_buf, 0,
7546                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7547         /* create L1 filter */
7548         filter_replace.old_filter_type =
7549                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7550         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7551         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7552                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7553         /* Prepare the buffer, 2 entries */
7554         filter_replace_buf.data[0] =
7555                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7556         filter_replace_buf.data[0] |=
7557                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7558         filter_replace_buf.data[2] = 0xFF;
7559         filter_replace_buf.data[3] = 0xFF;
7560         filter_replace_buf.data[4] =
7561                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7562         filter_replace_buf.data[4] |=
7563                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7564         filter_replace_buf.data[6] = 0xFF;
7565         filter_replace_buf.data[7] = 0xFF;
7566
7567         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7568                                                &filter_replace_buf);
7569         if (!status) {
7570                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7571                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7572                             "cloud l1 type is changed from 0x%x to 0x%x",
7573                             filter_replace.old_filter_type,
7574                             filter_replace.new_filter_type);
7575         }
7576         return status;
7577 }
7578
7579 static enum
7580 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7581 {
7582         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7583         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7584         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7585         enum i40e_status_code status = I40E_SUCCESS;
7586
7587         if (pf->support_multi_driver) {
7588                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7589                 return I40E_NOT_SUPPORTED;
7590         }
7591
7592         /* for GTP-C */
7593         memset(&filter_replace, 0,
7594                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7595         memset(&filter_replace_buf, 0,
7596                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7597         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7598         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7599         filter_replace.new_filter_type =
7600                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7601         /* Prepare the buffer, 2 entries */
7602         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7603         filter_replace_buf.data[0] |=
7604                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7605         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7606         filter_replace_buf.data[4] |=
7607                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7608         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7609                                                &filter_replace_buf);
7610         if (status < 0)
7611                 return status;
7612         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7613                     "cloud filter type is changed from 0x%x to 0x%x",
7614                     filter_replace.old_filter_type,
7615                     filter_replace.new_filter_type);
7616
7617         /* for GTP-U */
7618         memset(&filter_replace, 0,
7619                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7620         memset(&filter_replace_buf, 0,
7621                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7622         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7623         filter_replace.old_filter_type =
7624                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7625         filter_replace.new_filter_type =
7626                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7627         /* Prepare the buffer, 2 entries */
7628         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7629         filter_replace_buf.data[0] |=
7630                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7631         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7632         filter_replace_buf.data[4] |=
7633                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7634
7635         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7636                                                &filter_replace_buf);
7637         if (!status) {
7638                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7639                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7640                             "cloud filter type is changed from 0x%x to 0x%x",
7641                             filter_replace.old_filter_type,
7642                             filter_replace.new_filter_type);
7643         }
7644         return status;
7645 }
7646
7647 int
7648 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7649                       struct i40e_tunnel_filter_conf *tunnel_filter,
7650                       uint8_t add)
7651 {
7652         uint16_t ip_type;
7653         uint32_t ipv4_addr, ipv4_addr_le;
7654         uint8_t i, tun_type = 0;
7655         /* internal variable to convert ipv6 byte order */
7656         uint32_t convert_ipv6[4];
7657         int val, ret = 0;
7658         struct i40e_pf_vf *vf = NULL;
7659         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7660         struct i40e_vsi *vsi;
7661         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7662         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7663         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7664         struct i40e_tunnel_filter *tunnel, *node;
7665         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7666         uint32_t teid_le;
7667         bool big_buffer = 0;
7668
7669         cld_filter = rte_zmalloc("tunnel_filter",
7670                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7671                          0);
7672
7673         if (cld_filter == NULL) {
7674                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7675                 return -ENOMEM;
7676         }
7677         pfilter = cld_filter;
7678
7679         ether_addr_copy(&tunnel_filter->outer_mac,
7680                         (struct ether_addr *)&pfilter->element.outer_mac);
7681         ether_addr_copy(&tunnel_filter->inner_mac,
7682                         (struct ether_addr *)&pfilter->element.inner_mac);
7683
7684         pfilter->element.inner_vlan =
7685                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7686         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7687                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7688                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7689                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7690                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7691                                 &ipv4_addr_le,
7692                                 sizeof(pfilter->element.ipaddr.v4.data));
7693         } else {
7694                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7695                 for (i = 0; i < 4; i++) {
7696                         convert_ipv6[i] =
7697                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7698                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7699                 }
7700                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7701                            &convert_ipv6,
7702                            sizeof(pfilter->element.ipaddr.v6.data));
7703         }
7704
7705         /* check tunneled type */
7706         switch (tunnel_filter->tunnel_type) {
7707         case I40E_TUNNEL_TYPE_VXLAN:
7708                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7709                 break;
7710         case I40E_TUNNEL_TYPE_NVGRE:
7711                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7712                 break;
7713         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7714                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7715                 break;
7716         case I40E_TUNNEL_TYPE_MPLSoUDP:
7717                 if (!pf->mpls_replace_flag) {
7718                         i40e_replace_mpls_l1_filter(pf);
7719                         i40e_replace_mpls_cloud_filter(pf);
7720                         pf->mpls_replace_flag = 1;
7721                 }
7722                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7723                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7724                         teid_le >> 4;
7725                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7726                         (teid_le & 0xF) << 12;
7727                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7728                         0x40;
7729                 big_buffer = 1;
7730                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7731                 break;
7732         case I40E_TUNNEL_TYPE_MPLSoGRE:
7733                 if (!pf->mpls_replace_flag) {
7734                         i40e_replace_mpls_l1_filter(pf);
7735                         i40e_replace_mpls_cloud_filter(pf);
7736                         pf->mpls_replace_flag = 1;
7737                 }
7738                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7739                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7740                         teid_le >> 4;
7741                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7742                         (teid_le & 0xF) << 12;
7743                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7744                         0x0;
7745                 big_buffer = 1;
7746                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7747                 break;
7748         case I40E_TUNNEL_TYPE_GTPC:
7749                 if (!pf->gtp_replace_flag) {
7750                         i40e_replace_gtp_l1_filter(pf);
7751                         i40e_replace_gtp_cloud_filter(pf);
7752                         pf->gtp_replace_flag = 1;
7753                 }
7754                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7755                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7756                         (teid_le >> 16) & 0xFFFF;
7757                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7758                         teid_le & 0xFFFF;
7759                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7760                         0x0;
7761                 big_buffer = 1;
7762                 break;
7763         case I40E_TUNNEL_TYPE_GTPU:
7764                 if (!pf->gtp_replace_flag) {
7765                         i40e_replace_gtp_l1_filter(pf);
7766                         i40e_replace_gtp_cloud_filter(pf);
7767                         pf->gtp_replace_flag = 1;
7768                 }
7769                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7770                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7771                         (teid_le >> 16) & 0xFFFF;
7772                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7773                         teid_le & 0xFFFF;
7774                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7775                         0x0;
7776                 big_buffer = 1;
7777                 break;
7778         case I40E_TUNNEL_TYPE_QINQ:
7779                 if (!pf->qinq_replace_flag) {
7780                         ret = i40e_cloud_filter_qinq_create(pf);
7781                         if (ret < 0)
7782                                 PMD_DRV_LOG(DEBUG,
7783                                             "QinQ tunnel filter already created.");
7784                         pf->qinq_replace_flag = 1;
7785                 }
7786                 /*      Add in the General fields the values of
7787                  *      the Outer and Inner VLAN
7788                  *      Big Buffer should be set, see changes in
7789                  *      i40e_aq_add_cloud_filters
7790                  */
7791                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7792                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7793                 big_buffer = 1;
7794                 break;
7795         default:
7796                 /* Other tunnel types is not supported. */
7797                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7798                 rte_free(cld_filter);
7799                 return -EINVAL;
7800         }
7801
7802         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7803                 pfilter->element.flags =
7804                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7805         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7806                 pfilter->element.flags =
7807                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7808         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7809                 pfilter->element.flags =
7810                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7811         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7812                 pfilter->element.flags =
7813                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7814         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7815                 pfilter->element.flags |=
7816                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7817         else {
7818                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7819                                                 &pfilter->element.flags);
7820                 if (val < 0) {
7821                         rte_free(cld_filter);
7822                         return -EINVAL;
7823                 }
7824         }
7825
7826         pfilter->element.flags |= rte_cpu_to_le_16(
7827                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7828                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7829         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7830         pfilter->element.queue_number =
7831                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7832
7833         if (!tunnel_filter->is_to_vf)
7834                 vsi = pf->main_vsi;
7835         else {
7836                 if (tunnel_filter->vf_id >= pf->vf_num) {
7837                         PMD_DRV_LOG(ERR, "Invalid argument.");
7838                         rte_free(cld_filter);
7839                         return -EINVAL;
7840                 }
7841                 vf = &pf->vfs[tunnel_filter->vf_id];
7842                 vsi = vf->vsi;
7843         }
7844
7845         /* Check if there is the filter in SW list */
7846         memset(&check_filter, 0, sizeof(check_filter));
7847         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7848         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7849         check_filter.vf_id = tunnel_filter->vf_id;
7850         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7851         if (add && node) {
7852                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7853                 rte_free(cld_filter);
7854                 return -EINVAL;
7855         }
7856
7857         if (!add && !node) {
7858                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7859                 rte_free(cld_filter);
7860                 return -EINVAL;
7861         }
7862
7863         if (add) {
7864                 if (big_buffer)
7865                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7866                                                    vsi->seid, cld_filter, 1);
7867                 else
7868                         ret = i40e_aq_add_cloud_filters(hw,
7869                                         vsi->seid, &cld_filter->element, 1);
7870                 if (ret < 0) {
7871                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7872                         rte_free(cld_filter);
7873                         return -ENOTSUP;
7874                 }
7875                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7876                 if (tunnel == NULL) {
7877                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7878                         rte_free(cld_filter);
7879                         return -ENOMEM;
7880                 }
7881
7882                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7883                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7884                 if (ret < 0)
7885                         rte_free(tunnel);
7886         } else {
7887                 if (big_buffer)
7888                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7889                                 hw, vsi->seid, cld_filter, 1);
7890                 else
7891                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7892                                                    &cld_filter->element, 1);
7893                 if (ret < 0) {
7894                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7895                         rte_free(cld_filter);
7896                         return -ENOTSUP;
7897                 }
7898                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7899         }
7900
7901         rte_free(cld_filter);
7902         return ret;
7903 }
7904
7905 static int
7906 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7907 {
7908         uint8_t i;
7909
7910         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7911                 if (pf->vxlan_ports[i] == port)
7912                         return i;
7913         }
7914
7915         return -1;
7916 }
7917
7918 static int
7919 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7920 {
7921         int  idx, ret;
7922         uint8_t filter_idx;
7923         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7924
7925         idx = i40e_get_vxlan_port_idx(pf, port);
7926
7927         /* Check if port already exists */
7928         if (idx >= 0) {
7929                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7930                 return -EINVAL;
7931         }
7932
7933         /* Now check if there is space to add the new port */
7934         idx = i40e_get_vxlan_port_idx(pf, 0);
7935         if (idx < 0) {
7936                 PMD_DRV_LOG(ERR,
7937                         "Maximum number of UDP ports reached, not adding port %d",
7938                         port);
7939                 return -ENOSPC;
7940         }
7941
7942         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7943                                         &filter_idx, NULL);
7944         if (ret < 0) {
7945                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7946                 return -1;
7947         }
7948
7949         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7950                          port,  filter_idx);
7951
7952         /* New port: add it and mark its index in the bitmap */
7953         pf->vxlan_ports[idx] = port;
7954         pf->vxlan_bitmap |= (1 << idx);
7955
7956         if (!(pf->flags & I40E_FLAG_VXLAN))
7957                 pf->flags |= I40E_FLAG_VXLAN;
7958
7959         return 0;
7960 }
7961
7962 static int
7963 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7964 {
7965         int idx;
7966         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7967
7968         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7969                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7970                 return -EINVAL;
7971         }
7972
7973         idx = i40e_get_vxlan_port_idx(pf, port);
7974
7975         if (idx < 0) {
7976                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7977                 return -EINVAL;
7978         }
7979
7980         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7981                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7982                 return -1;
7983         }
7984
7985         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7986                         port, idx);
7987
7988         pf->vxlan_ports[idx] = 0;
7989         pf->vxlan_bitmap &= ~(1 << idx);
7990
7991         if (!pf->vxlan_bitmap)
7992                 pf->flags &= ~I40E_FLAG_VXLAN;
7993
7994         return 0;
7995 }
7996
7997 /* Add UDP tunneling port */
7998 static int
7999 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8000                              struct rte_eth_udp_tunnel *udp_tunnel)
8001 {
8002         int ret = 0;
8003         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8004
8005         if (udp_tunnel == NULL)
8006                 return -EINVAL;
8007
8008         switch (udp_tunnel->prot_type) {
8009         case RTE_TUNNEL_TYPE_VXLAN:
8010                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8011                 break;
8012
8013         case RTE_TUNNEL_TYPE_GENEVE:
8014         case RTE_TUNNEL_TYPE_TEREDO:
8015                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8016                 ret = -1;
8017                 break;
8018
8019         default:
8020                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8021                 ret = -1;
8022                 break;
8023         }
8024
8025         return ret;
8026 }
8027
8028 /* Remove UDP tunneling port */
8029 static int
8030 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8031                              struct rte_eth_udp_tunnel *udp_tunnel)
8032 {
8033         int ret = 0;
8034         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8035
8036         if (udp_tunnel == NULL)
8037                 return -EINVAL;
8038
8039         switch (udp_tunnel->prot_type) {
8040         case RTE_TUNNEL_TYPE_VXLAN:
8041                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8042                 break;
8043         case RTE_TUNNEL_TYPE_GENEVE:
8044         case RTE_TUNNEL_TYPE_TEREDO:
8045                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8046                 ret = -1;
8047                 break;
8048         default:
8049                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8050                 ret = -1;
8051                 break;
8052         }
8053
8054         return ret;
8055 }
8056
8057 /* Calculate the maximum number of contiguous PF queues that are configured */
8058 static int
8059 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8060 {
8061         struct rte_eth_dev_data *data = pf->dev_data;
8062         int i, num;
8063         struct i40e_rx_queue *rxq;
8064
8065         num = 0;
8066         for (i = 0; i < pf->lan_nb_qps; i++) {
8067                 rxq = data->rx_queues[i];
8068                 if (rxq && rxq->q_set)
8069                         num++;
8070                 else
8071                         break;
8072         }
8073
8074         return num;
8075 }
8076
8077 /* Configure RSS */
8078 static int
8079 i40e_pf_config_rss(struct i40e_pf *pf)
8080 {
8081         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8082         struct rte_eth_rss_conf rss_conf;
8083         uint32_t i, lut = 0;
8084         uint16_t j, num;
8085
8086         /*
8087          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8088          * It's necessary to calculate the actual PF queues that are configured.
8089          */
8090         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8091                 num = i40e_pf_calc_configured_queues_num(pf);
8092         else
8093                 num = pf->dev_data->nb_rx_queues;
8094
8095         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8096         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8097                         num);
8098
8099         if (num == 0) {
8100                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8101                 return -ENOTSUP;
8102         }
8103
8104         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8105                 if (j == num)
8106                         j = 0;
8107                 lut = (lut << 8) | (j & ((0x1 <<
8108                         hw->func_caps.rss_table_entry_width) - 1));
8109                 if ((i & 3) == 3)
8110                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8111         }
8112
8113         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8114         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8115                 i40e_pf_disable_rss(pf);
8116                 return 0;
8117         }
8118         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8119                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8120                 /* Random default keys */
8121                 static uint32_t rss_key_default[] = {0x6b793944,
8122                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8123                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8124                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8125
8126                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8127                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8128                                                         sizeof(uint32_t);
8129         }
8130
8131         return i40e_hw_rss_hash_set(pf, &rss_conf);
8132 }
8133
8134 static int
8135 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8136                                struct rte_eth_tunnel_filter_conf *filter)
8137 {
8138         if (pf == NULL || filter == NULL) {
8139                 PMD_DRV_LOG(ERR, "Invalid parameter");
8140                 return -EINVAL;
8141         }
8142
8143         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8144                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8145                 return -EINVAL;
8146         }
8147
8148         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8149                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8150                 return -EINVAL;
8151         }
8152
8153         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8154                 (is_zero_ether_addr(&filter->outer_mac))) {
8155                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8156                 return -EINVAL;
8157         }
8158
8159         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8160                 (is_zero_ether_addr(&filter->inner_mac))) {
8161                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8162                 return -EINVAL;
8163         }
8164
8165         return 0;
8166 }
8167
8168 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8169 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8170 static int
8171 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8172 {
8173         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8174         uint32_t val, reg;
8175         int ret = -EINVAL;
8176
8177         if (pf->support_multi_driver) {
8178                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8179                 return -ENOTSUP;
8180         }
8181
8182         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8183         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8184
8185         if (len == 3) {
8186                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8187         } else if (len == 4) {
8188                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8189         } else {
8190                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8191                 return ret;
8192         }
8193
8194         if (reg != val) {
8195                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
8196                                                    reg, NULL);
8197                 if (ret != 0)
8198                         return ret;
8199                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8200                             "with value 0x%08x",
8201                             I40E_GL_PRS_FVBM(2), reg);
8202                 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8203         } else {
8204                 ret = 0;
8205         }
8206         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8207                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8208
8209         return ret;
8210 }
8211
8212 static int
8213 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8214 {
8215         int ret = -EINVAL;
8216
8217         if (!hw || !cfg)
8218                 return -EINVAL;
8219
8220         switch (cfg->cfg_type) {
8221         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8222                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8223                 break;
8224         default:
8225                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8226                 break;
8227         }
8228
8229         return ret;
8230 }
8231
8232 static int
8233 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8234                                enum rte_filter_op filter_op,
8235                                void *arg)
8236 {
8237         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8238         int ret = I40E_ERR_PARAM;
8239
8240         switch (filter_op) {
8241         case RTE_ETH_FILTER_SET:
8242                 ret = i40e_dev_global_config_set(hw,
8243                         (struct rte_eth_global_cfg *)arg);
8244                 break;
8245         default:
8246                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8247                 break;
8248         }
8249
8250         return ret;
8251 }
8252
8253 static int
8254 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8255                           enum rte_filter_op filter_op,
8256                           void *arg)
8257 {
8258         struct rte_eth_tunnel_filter_conf *filter;
8259         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8260         int ret = I40E_SUCCESS;
8261
8262         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8263
8264         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8265                 return I40E_ERR_PARAM;
8266
8267         switch (filter_op) {
8268         case RTE_ETH_FILTER_NOP:
8269                 if (!(pf->flags & I40E_FLAG_VXLAN))
8270                         ret = I40E_NOT_SUPPORTED;
8271                 break;
8272         case RTE_ETH_FILTER_ADD:
8273                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8274                 break;
8275         case RTE_ETH_FILTER_DELETE:
8276                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8277                 break;
8278         default:
8279                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8280                 ret = I40E_ERR_PARAM;
8281                 break;
8282         }
8283
8284         return ret;
8285 }
8286
8287 static int
8288 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8289 {
8290         int ret = 0;
8291         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8292
8293         /* RSS setup */
8294         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8295                 ret = i40e_pf_config_rss(pf);
8296         else
8297                 i40e_pf_disable_rss(pf);
8298
8299         return ret;
8300 }
8301
8302 /* Get the symmetric hash enable configurations per port */
8303 static void
8304 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8305 {
8306         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8307
8308         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8309 }
8310
8311 /* Set the symmetric hash enable configurations per port */
8312 static void
8313 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8314 {
8315         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8316
8317         if (enable > 0) {
8318                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8319                         PMD_DRV_LOG(INFO,
8320                                 "Symmetric hash has already been enabled");
8321                         return;
8322                 }
8323                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8324         } else {
8325                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8326                         PMD_DRV_LOG(INFO,
8327                                 "Symmetric hash has already been disabled");
8328                         return;
8329                 }
8330                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8331         }
8332         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8333         I40E_WRITE_FLUSH(hw);
8334 }
8335
8336 /*
8337  * Get global configurations of hash function type and symmetric hash enable
8338  * per flow type (pctype). Note that global configuration means it affects all
8339  * the ports on the same NIC.
8340  */
8341 static int
8342 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8343                                    struct rte_eth_hash_global_conf *g_cfg)
8344 {
8345         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8346         uint32_t reg;
8347         uint16_t i, j;
8348
8349         memset(g_cfg, 0, sizeof(*g_cfg));
8350         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8351         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8352                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8353         else
8354                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8355         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8356                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8357
8358         /*
8359          * As i40e supports less than 64 flow types, only first 64 bits need to
8360          * be checked.
8361          */
8362         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8363                 g_cfg->valid_bit_mask[i] = 0ULL;
8364                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8365         }
8366
8367         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8368
8369         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8370                 if (!adapter->pctypes_tbl[i])
8371                         continue;
8372                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8373                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8374                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8375                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8376                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8377                                         g_cfg->sym_hash_enable_mask[0] |=
8378                                                                 (1ULL << i);
8379                                 }
8380                         }
8381                 }
8382         }
8383
8384         return 0;
8385 }
8386
8387 static int
8388 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8389                               const struct rte_eth_hash_global_conf *g_cfg)
8390 {
8391         uint32_t i;
8392         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8393
8394         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8395                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8396                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8397                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8398                                                 g_cfg->hash_func);
8399                 return -EINVAL;
8400         }
8401
8402         /*
8403          * As i40e supports less than 64 flow types, only first 64 bits need to
8404          * be checked.
8405          */
8406         mask0 = g_cfg->valid_bit_mask[0];
8407         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8408                 if (i == 0) {
8409                         /* Check if any unsupported flow type configured */
8410                         if ((mask0 | i40e_mask) ^ i40e_mask)
8411                                 goto mask_err;
8412                 } else {
8413                         if (g_cfg->valid_bit_mask[i])
8414                                 goto mask_err;
8415                 }
8416         }
8417
8418         return 0;
8419
8420 mask_err:
8421         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8422
8423         return -EINVAL;
8424 }
8425
8426 /*
8427  * Set global configurations of hash function type and symmetric hash enable
8428  * per flow type (pctype). Note any modifying global configuration will affect
8429  * all the ports on the same NIC.
8430  */
8431 static int
8432 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8433                                    struct rte_eth_hash_global_conf *g_cfg)
8434 {
8435         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8436         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8437         int ret;
8438         uint16_t i, j;
8439         uint32_t reg;
8440         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8441
8442         if (pf->support_multi_driver) {
8443                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8444                 return -ENOTSUP;
8445         }
8446
8447         /* Check the input parameters */
8448         ret = i40e_hash_global_config_check(adapter, g_cfg);
8449         if (ret < 0)
8450                 return ret;
8451
8452         /*
8453          * As i40e supports less than 64 flow types, only first 64 bits need to
8454          * be configured.
8455          */
8456         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8457                 if (mask0 & (1UL << i)) {
8458                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8459                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8460
8461                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8462                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8463                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8464                                         i40e_write_global_rx_ctl(hw,
8465                                                           I40E_GLQF_HSYM(j),
8466                                                           reg);
8467                         }
8468                         i40e_global_cfg_warning(I40E_WARNING_HSYM);
8469                 }
8470         }
8471
8472         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8473         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8474                 /* Toeplitz */
8475                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8476                         PMD_DRV_LOG(DEBUG,
8477                                 "Hash function already set to Toeplitz");
8478                         goto out;
8479                 }
8480                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8481         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8482                 /* Simple XOR */
8483                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8484                         PMD_DRV_LOG(DEBUG,
8485                                 "Hash function already set to Simple XOR");
8486                         goto out;
8487                 }
8488                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8489         } else
8490                 /* Use the default, and keep it as it is */
8491                 goto out;
8492
8493         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8494         i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8495
8496 out:
8497         I40E_WRITE_FLUSH(hw);
8498
8499         return 0;
8500 }
8501
8502 /**
8503  * Valid input sets for hash and flow director filters per PCTYPE
8504  */
8505 static uint64_t
8506 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8507                 enum rte_filter_type filter)
8508 {
8509         uint64_t valid;
8510
8511         static const uint64_t valid_hash_inset_table[] = {
8512                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8513                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8514                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8515                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8516                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8517                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8518                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8519                         I40E_INSET_FLEX_PAYLOAD,
8520                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8521                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8522                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8523                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8524                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8525                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8526                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8527                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8528                         I40E_INSET_FLEX_PAYLOAD,
8529                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8530                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8531                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8532                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8533                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8534                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8535                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8536                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8537                         I40E_INSET_FLEX_PAYLOAD,
8538                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8539                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8540                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8541                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8542                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8543                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8544                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8545                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8546                         I40E_INSET_FLEX_PAYLOAD,
8547                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8548                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8549                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8550                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8551                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8552                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8553                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8554                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8555                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8556                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8557                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8558                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8559                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8560                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8561                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8562                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8563                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8564                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8565                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8566                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8567                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8568                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8569                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8570                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8571                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8572                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8573                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8574                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8575                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8576                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8577                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8578                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8579                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8580                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8581                         I40E_INSET_FLEX_PAYLOAD,
8582                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8583                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8584                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8585                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8586                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8587                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8588                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8589                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8590                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8591                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8592                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8593                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8594                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8595                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8596                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8597                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8598                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8599                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8600                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8601                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8602                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8603                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8604                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8605                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8606                         I40E_INSET_FLEX_PAYLOAD,
8607                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8608                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8609                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8610                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8611                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8612                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8613                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8614                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8615                         I40E_INSET_FLEX_PAYLOAD,
8616                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8617                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8618                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8619                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8620                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8621                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8622                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8623                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8624                         I40E_INSET_FLEX_PAYLOAD,
8625                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8626                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8627                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8628                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8629                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8630                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8631                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8632                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8633                         I40E_INSET_FLEX_PAYLOAD,
8634                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8635                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8636                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8637                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8638                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8639                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8640                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8641                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8642                         I40E_INSET_FLEX_PAYLOAD,
8643                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8644                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8645                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8646                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8647                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8648                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8649                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8650                         I40E_INSET_FLEX_PAYLOAD,
8651                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8652                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8653                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8654                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8655                         I40E_INSET_FLEX_PAYLOAD,
8656         };
8657
8658         /**
8659          * Flow director supports only fields defined in
8660          * union rte_eth_fdir_flow.
8661          */
8662         static const uint64_t valid_fdir_inset_table[] = {
8663                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8664                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8665                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8666                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8667                 I40E_INSET_IPV4_TTL,
8668                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8669                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8670                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8671                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8672                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8673                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8674                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8675                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8676                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8677                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8678                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8679                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8680                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8681                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8682                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8683                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8684                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8685                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8686                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8687                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8688                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8689                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8690                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8691                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8692                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8693                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8694                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8695                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8696                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8697                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8698                 I40E_INSET_SCTP_VT,
8699                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8700                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8701                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8702                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8703                 I40E_INSET_IPV4_TTL,
8704                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8705                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8706                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8707                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8708                 I40E_INSET_IPV6_HOP_LIMIT,
8709                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8710                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8711                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8712                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8713                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8714                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8715                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8716                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8717                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8718                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8719                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8720                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8721                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8722                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8723                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8724                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8725                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8726                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8727                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8728                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8729                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8730                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8731                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8732                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8733                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8734                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8735                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8736                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8737                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8738                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8739                 I40E_INSET_SCTP_VT,
8740                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8741                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8742                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8743                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8744                 I40E_INSET_IPV6_HOP_LIMIT,
8745                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8746                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8747                 I40E_INSET_LAST_ETHER_TYPE,
8748         };
8749
8750         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8751                 return 0;
8752         if (filter == RTE_ETH_FILTER_HASH)
8753                 valid = valid_hash_inset_table[pctype];
8754         else
8755                 valid = valid_fdir_inset_table[pctype];
8756
8757         return valid;
8758 }
8759
8760 /**
8761  * Validate if the input set is allowed for a specific PCTYPE
8762  */
8763 int
8764 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8765                 enum rte_filter_type filter, uint64_t inset)
8766 {
8767         uint64_t valid;
8768
8769         valid = i40e_get_valid_input_set(pctype, filter);
8770         if (inset & (~valid))
8771                 return -EINVAL;
8772
8773         return 0;
8774 }
8775
8776 /* default input set fields combination per pctype */
8777 uint64_t
8778 i40e_get_default_input_set(uint16_t pctype)
8779 {
8780         static const uint64_t default_inset_table[] = {
8781                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8782                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8783                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8784                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8785                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8786                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8787                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8788                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8789                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8790                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8791                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8792                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8793                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8794                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8795                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8796                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8797                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8798                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8799                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8800                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8801                         I40E_INSET_SCTP_VT,
8802                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8803                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8804                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8805                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8806                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8807                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8808                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8809                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8810                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8811                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8812                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8813                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8814                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8815                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8816                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8817                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8818                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8819                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8820                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8821                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8822                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8823                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8824                         I40E_INSET_SCTP_VT,
8825                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8826                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8827                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8828                         I40E_INSET_LAST_ETHER_TYPE,
8829         };
8830
8831         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8832                 return 0;
8833
8834         return default_inset_table[pctype];
8835 }
8836
8837 /**
8838  * Parse the input set from index to logical bit masks
8839  */
8840 static int
8841 i40e_parse_input_set(uint64_t *inset,
8842                      enum i40e_filter_pctype pctype,
8843                      enum rte_eth_input_set_field *field,
8844                      uint16_t size)
8845 {
8846         uint16_t i, j;
8847         int ret = -EINVAL;
8848
8849         static const struct {
8850                 enum rte_eth_input_set_field field;
8851                 uint64_t inset;
8852         } inset_convert_table[] = {
8853                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8854                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8855                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8856                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8857                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8858                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8859                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8860                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8861                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8862                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8863                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8864                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8865                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8866                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8867                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8868                         I40E_INSET_IPV6_NEXT_HDR},
8869                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8870                         I40E_INSET_IPV6_HOP_LIMIT},
8871                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8872                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8873                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8874                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8875                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8876                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8877                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8878                         I40E_INSET_SCTP_VT},
8879                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8880                         I40E_INSET_TUNNEL_DMAC},
8881                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8882                         I40E_INSET_VLAN_TUNNEL},
8883                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8884                         I40E_INSET_TUNNEL_ID},
8885                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8886                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8887                         I40E_INSET_FLEX_PAYLOAD_W1},
8888                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8889                         I40E_INSET_FLEX_PAYLOAD_W2},
8890                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8891                         I40E_INSET_FLEX_PAYLOAD_W3},
8892                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8893                         I40E_INSET_FLEX_PAYLOAD_W4},
8894                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8895                         I40E_INSET_FLEX_PAYLOAD_W5},
8896                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8897                         I40E_INSET_FLEX_PAYLOAD_W6},
8898                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8899                         I40E_INSET_FLEX_PAYLOAD_W7},
8900                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8901                         I40E_INSET_FLEX_PAYLOAD_W8},
8902         };
8903
8904         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8905                 return ret;
8906
8907         /* Only one item allowed for default or all */
8908         if (size == 1) {
8909                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8910                         *inset = i40e_get_default_input_set(pctype);
8911                         return 0;
8912                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8913                         *inset = I40E_INSET_NONE;
8914                         return 0;
8915                 }
8916         }
8917
8918         for (i = 0, *inset = 0; i < size; i++) {
8919                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8920                         if (field[i] == inset_convert_table[j].field) {
8921                                 *inset |= inset_convert_table[j].inset;
8922                                 break;
8923                         }
8924                 }
8925
8926                 /* It contains unsupported input set, return immediately */
8927                 if (j == RTE_DIM(inset_convert_table))
8928                         return ret;
8929         }
8930
8931         return 0;
8932 }
8933
8934 /**
8935  * Translate the input set from bit masks to register aware bit masks
8936  * and vice versa
8937  */
8938 uint64_t
8939 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8940 {
8941         uint64_t val = 0;
8942         uint16_t i;
8943
8944         struct inset_map {
8945                 uint64_t inset;
8946                 uint64_t inset_reg;
8947         };
8948
8949         static const struct inset_map inset_map_common[] = {
8950                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8951                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8952                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8953                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8954                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8955                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8956                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8957                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8958                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8959                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8960                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8961                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8962                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8963                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8964                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8965                 {I40E_INSET_TUNNEL_DMAC,
8966                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8967                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8968                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8969                 {I40E_INSET_TUNNEL_SRC_PORT,
8970                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8971                 {I40E_INSET_TUNNEL_DST_PORT,
8972                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8973                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8974                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8975                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8976                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8977                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8978                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8979                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8980                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8981                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8982         };
8983
8984     /* some different registers map in x722*/
8985         static const struct inset_map inset_map_diff_x722[] = {
8986                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8987                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8988                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8989                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8990         };
8991
8992         static const struct inset_map inset_map_diff_not_x722[] = {
8993                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8994                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8995                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8996                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8997         };
8998
8999         if (input == 0)
9000                 return val;
9001
9002         /* Translate input set to register aware inset */
9003         if (type == I40E_MAC_X722) {
9004                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9005                         if (input & inset_map_diff_x722[i].inset)
9006                                 val |= inset_map_diff_x722[i].inset_reg;
9007                 }
9008         } else {
9009                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9010                         if (input & inset_map_diff_not_x722[i].inset)
9011                                 val |= inset_map_diff_not_x722[i].inset_reg;
9012                 }
9013         }
9014
9015         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9016                 if (input & inset_map_common[i].inset)
9017                         val |= inset_map_common[i].inset_reg;
9018         }
9019
9020         return val;
9021 }
9022
9023 int
9024 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9025 {
9026         uint8_t i, idx = 0;
9027         uint64_t inset_need_mask = inset;
9028
9029         static const struct {
9030                 uint64_t inset;
9031                 uint32_t mask;
9032         } inset_mask_map[] = {
9033                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9034                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9035                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9036                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9037                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9038                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9039                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9040                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9041         };
9042
9043         if (!inset || !mask || !nb_elem)
9044                 return 0;
9045
9046         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9047                 /* Clear the inset bit, if no MASK is required,
9048                  * for example proto + ttl
9049                  */
9050                 if ((inset & inset_mask_map[i].inset) ==
9051                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9052                         inset_need_mask &= ~inset_mask_map[i].inset;
9053                 if (!inset_need_mask)
9054                         return 0;
9055         }
9056         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9057                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9058                     inset_mask_map[i].inset) {
9059                         if (idx >= nb_elem) {
9060                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9061                                 return -EINVAL;
9062                         }
9063                         mask[idx] = inset_mask_map[i].mask;
9064                         idx++;
9065                 }
9066         }
9067
9068         return idx;
9069 }
9070
9071 void
9072 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9073 {
9074         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9075
9076         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9077         if (reg != val)
9078                 i40e_write_rx_ctl(hw, addr, val);
9079         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9080                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9081 }
9082
9083 void
9084 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9085 {
9086         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9087
9088         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9089         if (reg != val)
9090                 i40e_write_global_rx_ctl(hw, addr, val);
9091         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9092                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9093 }
9094
9095 static void
9096 i40e_filter_input_set_init(struct i40e_pf *pf)
9097 {
9098         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9099         enum i40e_filter_pctype pctype;
9100         uint64_t input_set, inset_reg;
9101         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9102         int num, i;
9103         uint16_t flow_type;
9104
9105         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9106              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9107                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9108
9109                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9110                         continue;
9111
9112                 input_set = i40e_get_default_input_set(pctype);
9113
9114                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9115                                                    I40E_INSET_MASK_NUM_REG);
9116                 if (num < 0)
9117                         return;
9118                 if (pf->support_multi_driver && num > 0) {
9119                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9120                         return;
9121                 }
9122                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9123                                         input_set);
9124
9125                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9126                                       (uint32_t)(inset_reg & UINT32_MAX));
9127                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9128                                      (uint32_t)((inset_reg >>
9129                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9130                 if (!pf->support_multi_driver) {
9131                         i40e_check_write_global_reg(hw,
9132                                             I40E_GLQF_HASH_INSET(0, pctype),
9133                                             (uint32_t)(inset_reg & UINT32_MAX));
9134                         i40e_check_write_global_reg(hw,
9135                                              I40E_GLQF_HASH_INSET(1, pctype),
9136                                              (uint32_t)((inset_reg >>
9137                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9138
9139                         for (i = 0; i < num; i++) {
9140                                 i40e_check_write_global_reg(hw,
9141                                                     I40E_GLQF_FD_MSK(i, pctype),
9142                                                     mask_reg[i]);
9143                                 i40e_check_write_global_reg(hw,
9144                                                   I40E_GLQF_HASH_MSK(i, pctype),
9145                                                   mask_reg[i]);
9146                         }
9147                         /*clear unused mask registers of the pctype */
9148                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9149                                 i40e_check_write_global_reg(hw,
9150                                                     I40E_GLQF_FD_MSK(i, pctype),
9151                                                     0);
9152                                 i40e_check_write_global_reg(hw,
9153                                                   I40E_GLQF_HASH_MSK(i, pctype),
9154                                                   0);
9155                         }
9156                 } else {
9157                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9158                 }
9159                 I40E_WRITE_FLUSH(hw);
9160
9161                 /* store the default input set */
9162                 if (!pf->support_multi_driver)
9163                         pf->hash_input_set[pctype] = input_set;
9164                 pf->fdir.input_set[pctype] = input_set;
9165         }
9166
9167         if (!pf->support_multi_driver) {
9168                 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9169                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9170                 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9171         }
9172 }
9173
9174 int
9175 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9176                          struct rte_eth_input_set_conf *conf)
9177 {
9178         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9179         enum i40e_filter_pctype pctype;
9180         uint64_t input_set, inset_reg = 0;
9181         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9182         int ret, i, num;
9183
9184         if (!conf) {
9185                 PMD_DRV_LOG(ERR, "Invalid pointer");
9186                 return -EFAULT;
9187         }
9188         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9189             conf->op != RTE_ETH_INPUT_SET_ADD) {
9190                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9191                 return -EINVAL;
9192         }
9193
9194         if (pf->support_multi_driver) {
9195                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9196                 return -ENOTSUP;
9197         }
9198
9199         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9200         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9201                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9202                 return -EINVAL;
9203         }
9204
9205         if (hw->mac.type == I40E_MAC_X722) {
9206                 /* get translated pctype value in fd pctype register */
9207                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9208                         I40E_GLQF_FD_PCTYPES((int)pctype));
9209         }
9210
9211         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9212                                    conf->inset_size);
9213         if (ret) {
9214                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9215                 return -EINVAL;
9216         }
9217
9218         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9219                 /* get inset value in register */
9220                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9221                 inset_reg <<= I40E_32_BIT_WIDTH;
9222                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9223                 input_set |= pf->hash_input_set[pctype];
9224         }
9225         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9226                                            I40E_INSET_MASK_NUM_REG);
9227         if (num < 0)
9228                 return -EINVAL;
9229
9230         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9231
9232         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9233                                     (uint32_t)(inset_reg & UINT32_MAX));
9234         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9235                                     (uint32_t)((inset_reg >>
9236                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9237         i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9238
9239         for (i = 0; i < num; i++)
9240                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9241                                             mask_reg[i]);
9242         /*clear unused mask registers of the pctype */
9243         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9244                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9245                                             0);
9246         i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9247         I40E_WRITE_FLUSH(hw);
9248
9249         pf->hash_input_set[pctype] = input_set;
9250         return 0;
9251 }
9252
9253 int
9254 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9255                          struct rte_eth_input_set_conf *conf)
9256 {
9257         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9258         enum i40e_filter_pctype pctype;
9259         uint64_t input_set, inset_reg = 0;
9260         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9261         int ret, i, num;
9262
9263         if (!hw || !conf) {
9264                 PMD_DRV_LOG(ERR, "Invalid pointer");
9265                 return -EFAULT;
9266         }
9267         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9268             conf->op != RTE_ETH_INPUT_SET_ADD) {
9269                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9270                 return -EINVAL;
9271         }
9272
9273         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9274
9275         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9276                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9277                 return -EINVAL;
9278         }
9279
9280         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9281                                    conf->inset_size);
9282         if (ret) {
9283                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9284                 return -EINVAL;
9285         }
9286
9287         /* get inset value in register */
9288         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9289         inset_reg <<= I40E_32_BIT_WIDTH;
9290         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9291
9292         /* Can not change the inset reg for flex payload for fdir,
9293          * it is done by writing I40E_PRTQF_FD_FLXINSET
9294          * in i40e_set_flex_mask_on_pctype.
9295          */
9296         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9297                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9298         else
9299                 input_set |= pf->fdir.input_set[pctype];
9300         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9301                                            I40E_INSET_MASK_NUM_REG);
9302         if (num < 0)
9303                 return -EINVAL;
9304         if (pf->support_multi_driver && num > 0) {
9305                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9306                 return -ENOTSUP;
9307         }
9308
9309         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9310
9311         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9312                               (uint32_t)(inset_reg & UINT32_MAX));
9313         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9314                              (uint32_t)((inset_reg >>
9315                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9316
9317         if (!pf->support_multi_driver) {
9318                 for (i = 0; i < num; i++)
9319                         i40e_check_write_global_reg(hw,
9320                                                     I40E_GLQF_FD_MSK(i, pctype),
9321                                                     mask_reg[i]);
9322                 /*clear unused mask registers of the pctype */
9323                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9324                         i40e_check_write_global_reg(hw,
9325                                                     I40E_GLQF_FD_MSK(i, pctype),
9326                                                     0);
9327                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9328         } else {
9329                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9330         }
9331         I40E_WRITE_FLUSH(hw);
9332
9333         pf->fdir.input_set[pctype] = input_set;
9334         return 0;
9335 }
9336
9337 static int
9338 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9339 {
9340         int ret = 0;
9341
9342         if (!hw || !info) {
9343                 PMD_DRV_LOG(ERR, "Invalid pointer");
9344                 return -EFAULT;
9345         }
9346
9347         switch (info->info_type) {
9348         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9349                 i40e_get_symmetric_hash_enable_per_port(hw,
9350                                         &(info->info.enable));
9351                 break;
9352         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9353                 ret = i40e_get_hash_filter_global_config(hw,
9354                                 &(info->info.global_conf));
9355                 break;
9356         default:
9357                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9358                                                         info->info_type);
9359                 ret = -EINVAL;
9360                 break;
9361         }
9362
9363         return ret;
9364 }
9365
9366 static int
9367 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9368 {
9369         int ret = 0;
9370
9371         if (!hw || !info) {
9372                 PMD_DRV_LOG(ERR, "Invalid pointer");
9373                 return -EFAULT;
9374         }
9375
9376         switch (info->info_type) {
9377         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9378                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9379                 break;
9380         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9381                 ret = i40e_set_hash_filter_global_config(hw,
9382                                 &(info->info.global_conf));
9383                 break;
9384         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9385                 ret = i40e_hash_filter_inset_select(hw,
9386                                                &(info->info.input_set_conf));
9387                 break;
9388
9389         default:
9390                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9391                                                         info->info_type);
9392                 ret = -EINVAL;
9393                 break;
9394         }
9395
9396         return ret;
9397 }
9398
9399 /* Operations for hash function */
9400 static int
9401 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9402                       enum rte_filter_op filter_op,
9403                       void *arg)
9404 {
9405         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9406         int ret = 0;
9407
9408         switch (filter_op) {
9409         case RTE_ETH_FILTER_NOP:
9410                 break;
9411         case RTE_ETH_FILTER_GET:
9412                 ret = i40e_hash_filter_get(hw,
9413                         (struct rte_eth_hash_filter_info *)arg);
9414                 break;
9415         case RTE_ETH_FILTER_SET:
9416                 ret = i40e_hash_filter_set(hw,
9417                         (struct rte_eth_hash_filter_info *)arg);
9418                 break;
9419         default:
9420                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9421                                                                 filter_op);
9422                 ret = -ENOTSUP;
9423                 break;
9424         }
9425
9426         return ret;
9427 }
9428
9429 /* Convert ethertype filter structure */
9430 static int
9431 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9432                               struct i40e_ethertype_filter *filter)
9433 {
9434         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9435         filter->input.ether_type = input->ether_type;
9436         filter->flags = input->flags;
9437         filter->queue = input->queue;
9438
9439         return 0;
9440 }
9441
9442 /* Check if there exists the ehtertype filter */
9443 struct i40e_ethertype_filter *
9444 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9445                                 const struct i40e_ethertype_filter_input *input)
9446 {
9447         int ret;
9448
9449         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9450         if (ret < 0)
9451                 return NULL;
9452
9453         return ethertype_rule->hash_map[ret];
9454 }
9455
9456 /* Add ethertype filter in SW list */
9457 static int
9458 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9459                                 struct i40e_ethertype_filter *filter)
9460 {
9461         struct i40e_ethertype_rule *rule = &pf->ethertype;
9462         int ret;
9463
9464         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9465         if (ret < 0) {
9466                 PMD_DRV_LOG(ERR,
9467                             "Failed to insert ethertype filter"
9468                             " to hash table %d!",
9469                             ret);
9470                 return ret;
9471         }
9472         rule->hash_map[ret] = filter;
9473
9474         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9475
9476         return 0;
9477 }
9478
9479 /* Delete ethertype filter in SW list */
9480 int
9481 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9482                              struct i40e_ethertype_filter_input *input)
9483 {
9484         struct i40e_ethertype_rule *rule = &pf->ethertype;
9485         struct i40e_ethertype_filter *filter;
9486         int ret;
9487
9488         ret = rte_hash_del_key(rule->hash_table, input);
9489         if (ret < 0) {
9490                 PMD_DRV_LOG(ERR,
9491                             "Failed to delete ethertype filter"
9492                             " to hash table %d!",
9493                             ret);
9494                 return ret;
9495         }
9496         filter = rule->hash_map[ret];
9497         rule->hash_map[ret] = NULL;
9498
9499         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9500         rte_free(filter);
9501
9502         return 0;
9503 }
9504
9505 /*
9506  * Configure ethertype filter, which can director packet by filtering
9507  * with mac address and ether_type or only ether_type
9508  */
9509 int
9510 i40e_ethertype_filter_set(struct i40e_pf *pf,
9511                         struct rte_eth_ethertype_filter *filter,
9512                         bool add)
9513 {
9514         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9515         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9516         struct i40e_ethertype_filter *ethertype_filter, *node;
9517         struct i40e_ethertype_filter check_filter;
9518         struct i40e_control_filter_stats stats;
9519         uint16_t flags = 0;
9520         int ret;
9521
9522         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9523                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9524                 return -EINVAL;
9525         }
9526         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9527                 filter->ether_type == ETHER_TYPE_IPv6) {
9528                 PMD_DRV_LOG(ERR,
9529                         "unsupported ether_type(0x%04x) in control packet filter.",
9530                         filter->ether_type);
9531                 return -EINVAL;
9532         }
9533         if (filter->ether_type == ETHER_TYPE_VLAN)
9534                 PMD_DRV_LOG(WARNING,
9535                         "filter vlan ether_type in first tag is not supported.");
9536
9537         /* Check if there is the filter in SW list */
9538         memset(&check_filter, 0, sizeof(check_filter));
9539         i40e_ethertype_filter_convert(filter, &check_filter);
9540         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9541                                                &check_filter.input);
9542         if (add && node) {
9543                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9544                 return -EINVAL;
9545         }
9546
9547         if (!add && !node) {
9548                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9549                 return -EINVAL;
9550         }
9551
9552         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9553                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9554         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9555                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9556         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9557
9558         memset(&stats, 0, sizeof(stats));
9559         ret = i40e_aq_add_rem_control_packet_filter(hw,
9560                         filter->mac_addr.addr_bytes,
9561                         filter->ether_type, flags,
9562                         pf->main_vsi->seid,
9563                         filter->queue, add, &stats, NULL);
9564
9565         PMD_DRV_LOG(INFO,
9566                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9567                 ret, stats.mac_etype_used, stats.etype_used,
9568                 stats.mac_etype_free, stats.etype_free);
9569         if (ret < 0)
9570                 return -ENOSYS;
9571
9572         /* Add or delete a filter in SW list */
9573         if (add) {
9574                 ethertype_filter = rte_zmalloc("ethertype_filter",
9575                                        sizeof(*ethertype_filter), 0);
9576                 if (ethertype_filter == NULL) {
9577                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9578                         return -ENOMEM;
9579                 }
9580
9581                 rte_memcpy(ethertype_filter, &check_filter,
9582                            sizeof(check_filter));
9583                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9584                 if (ret < 0)
9585                         rte_free(ethertype_filter);
9586         } else {
9587                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9588         }
9589
9590         return ret;
9591 }
9592
9593 /*
9594  * Handle operations for ethertype filter.
9595  */
9596 static int
9597 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9598                                 enum rte_filter_op filter_op,
9599                                 void *arg)
9600 {
9601         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9602         int ret = 0;
9603
9604         if (filter_op == RTE_ETH_FILTER_NOP)
9605                 return ret;
9606
9607         if (arg == NULL) {
9608                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9609                             filter_op);
9610                 return -EINVAL;
9611         }
9612
9613         switch (filter_op) {
9614         case RTE_ETH_FILTER_ADD:
9615                 ret = i40e_ethertype_filter_set(pf,
9616                         (struct rte_eth_ethertype_filter *)arg,
9617                         TRUE);
9618                 break;
9619         case RTE_ETH_FILTER_DELETE:
9620                 ret = i40e_ethertype_filter_set(pf,
9621                         (struct rte_eth_ethertype_filter *)arg,
9622                         FALSE);
9623                 break;
9624         default:
9625                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9626                 ret = -ENOSYS;
9627                 break;
9628         }
9629         return ret;
9630 }
9631
9632 static int
9633 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9634                      enum rte_filter_type filter_type,
9635                      enum rte_filter_op filter_op,
9636                      void *arg)
9637 {
9638         int ret = 0;
9639
9640         if (dev == NULL)
9641                 return -EINVAL;
9642
9643         switch (filter_type) {
9644         case RTE_ETH_FILTER_NONE:
9645                 /* For global configuration */
9646                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9647                 break;
9648         case RTE_ETH_FILTER_HASH:
9649                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9650                 break;
9651         case RTE_ETH_FILTER_MACVLAN:
9652                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9653                 break;
9654         case RTE_ETH_FILTER_ETHERTYPE:
9655                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9656                 break;
9657         case RTE_ETH_FILTER_TUNNEL:
9658                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9659                 break;
9660         case RTE_ETH_FILTER_FDIR:
9661                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9662                 break;
9663         case RTE_ETH_FILTER_GENERIC:
9664                 if (filter_op != RTE_ETH_FILTER_GET)
9665                         return -EINVAL;
9666                 *(const void **)arg = &i40e_flow_ops;
9667                 break;
9668         default:
9669                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9670                                                         filter_type);
9671                 ret = -EINVAL;
9672                 break;
9673         }
9674
9675         return ret;
9676 }
9677
9678 /*
9679  * Check and enable Extended Tag.
9680  * Enabling Extended Tag is important for 40G performance.
9681  */
9682 static void
9683 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9684 {
9685         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9686         uint32_t buf = 0;
9687         int ret;
9688
9689         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9690                                       PCI_DEV_CAP_REG);
9691         if (ret < 0) {
9692                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9693                             PCI_DEV_CAP_REG);
9694                 return;
9695         }
9696         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9697                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9698                 return;
9699         }
9700
9701         buf = 0;
9702         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9703                                       PCI_DEV_CTRL_REG);
9704         if (ret < 0) {
9705                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9706                             PCI_DEV_CTRL_REG);
9707                 return;
9708         }
9709         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9710                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9711                 return;
9712         }
9713         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9714         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9715                                        PCI_DEV_CTRL_REG);
9716         if (ret < 0) {
9717                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9718                             PCI_DEV_CTRL_REG);
9719                 return;
9720         }
9721 }
9722
9723 /*
9724  * As some registers wouldn't be reset unless a global hardware reset,
9725  * hardware initialization is needed to put those registers into an
9726  * expected initial state.
9727  */
9728 static void
9729 i40e_hw_init(struct rte_eth_dev *dev)
9730 {
9731         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9732
9733         i40e_enable_extended_tag(dev);
9734
9735         /* clear the PF Queue Filter control register */
9736         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9737
9738         /* Disable symmetric hash per port */
9739         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9740 }
9741
9742 /*
9743  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9744  * however this function will return only one highest pctype index,
9745  * which is not quite correct. This is known problem of i40e driver
9746  * and needs to be fixed later.
9747  */
9748 enum i40e_filter_pctype
9749 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9750 {
9751         int i;
9752         uint64_t pctype_mask;
9753
9754         if (flow_type < I40E_FLOW_TYPE_MAX) {
9755                 pctype_mask = adapter->pctypes_tbl[flow_type];
9756                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9757                         if (pctype_mask & (1ULL << i))
9758                                 return (enum i40e_filter_pctype)i;
9759                 }
9760         }
9761         return I40E_FILTER_PCTYPE_INVALID;
9762 }
9763
9764 uint16_t
9765 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9766                         enum i40e_filter_pctype pctype)
9767 {
9768         uint16_t flowtype;
9769         uint64_t pctype_mask = 1ULL << pctype;
9770
9771         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9772              flowtype++) {
9773                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9774                         return flowtype;
9775         }
9776
9777         return RTE_ETH_FLOW_UNKNOWN;
9778 }
9779
9780 /*
9781  * On X710, performance number is far from the expectation on recent firmware
9782  * versions; on XL710, performance number is also far from the expectation on
9783  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9784  * mode is enabled and port MAC address is equal to the packet destination MAC
9785  * address. The fix for this issue may not be integrated in the following
9786  * firmware version. So the workaround in software driver is needed. It needs
9787  * to modify the initial values of 3 internal only registers for both X710 and
9788  * XL710. Note that the values for X710 or XL710 could be different, and the
9789  * workaround can be removed when it is fixed in firmware in the future.
9790  */
9791
9792 /* For both X710 and XL710 */
9793 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9794 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9795 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9796
9797 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9798 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9799
9800 /* For X722 */
9801 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9802 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9803
9804 /* For X710 */
9805 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9806 /* For XL710 */
9807 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9808 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9809
9810 static int
9811 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9812 {
9813         enum i40e_status_code status;
9814         struct i40e_aq_get_phy_abilities_resp phy_ab;
9815         int ret = -ENOTSUP;
9816         int retries = 0;
9817
9818         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9819                                               NULL);
9820
9821         while (status) {
9822                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9823                         status);
9824                 retries++;
9825                 rte_delay_us(100000);
9826                 if  (retries < 5)
9827                         status = i40e_aq_get_phy_capabilities(hw, false,
9828                                         true, &phy_ab, NULL);
9829                 else
9830                         return ret;
9831         }
9832         return 0;
9833 }
9834
9835 static void
9836 i40e_configure_registers(struct i40e_hw *hw)
9837 {
9838         static struct {
9839                 uint32_t addr;
9840                 uint64_t val;
9841         } reg_table[] = {
9842                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9843                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9844                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9845         };
9846         uint64_t reg;
9847         uint32_t i;
9848         int ret;
9849
9850         for (i = 0; i < RTE_DIM(reg_table); i++) {
9851                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9852                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9853                                 reg_table[i].val =
9854                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9855                         else /* For X710/XL710/XXV710 */
9856                                 if (hw->aq.fw_maj_ver < 6)
9857                                         reg_table[i].val =
9858                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9859                                 else
9860                                         reg_table[i].val =
9861                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9862                 }
9863
9864                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9865                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9866                                 reg_table[i].val =
9867                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9868                         else /* For X710/XL710/XXV710 */
9869                                 reg_table[i].val =
9870                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9871                 }
9872
9873                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9874                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9875                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9876                                 reg_table[i].val =
9877                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9878                         else /* For X710 */
9879                                 reg_table[i].val =
9880                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9881                 }
9882
9883                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9884                                                         &reg, NULL);
9885                 if (ret < 0) {
9886                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9887                                                         reg_table[i].addr);
9888                         break;
9889                 }
9890                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9891                                                 reg_table[i].addr, reg);
9892                 if (reg == reg_table[i].val)
9893                         continue;
9894
9895                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9896                                                 reg_table[i].val, NULL);
9897                 if (ret < 0) {
9898                         PMD_DRV_LOG(ERR,
9899                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9900                                 reg_table[i].val, reg_table[i].addr);
9901                         break;
9902                 }
9903                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9904                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9905         }
9906 }
9907
9908 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9909 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9910 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9911 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9912 static int
9913 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9914 {
9915         uint32_t reg;
9916         int ret;
9917
9918         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9919                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9920                 return -EINVAL;
9921         }
9922
9923         /* Configure for double VLAN RX stripping */
9924         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9925         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9926                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9927                 ret = i40e_aq_debug_write_register(hw,
9928                                                    I40E_VSI_TSR(vsi->vsi_id),
9929                                                    reg, NULL);
9930                 if (ret < 0) {
9931                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9932                                     vsi->vsi_id);
9933                         return I40E_ERR_CONFIG;
9934                 }
9935         }
9936
9937         /* Configure for double VLAN TX insertion */
9938         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9939         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9940                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9941                 ret = i40e_aq_debug_write_register(hw,
9942                                                    I40E_VSI_L2TAGSTXVALID(
9943                                                    vsi->vsi_id), reg, NULL);
9944                 if (ret < 0) {
9945                         PMD_DRV_LOG(ERR,
9946                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9947                                 vsi->vsi_id);
9948                         return I40E_ERR_CONFIG;
9949                 }
9950         }
9951
9952         return 0;
9953 }
9954
9955 /**
9956  * i40e_aq_add_mirror_rule
9957  * @hw: pointer to the hardware structure
9958  * @seid: VEB seid to add mirror rule to
9959  * @dst_id: destination vsi seid
9960  * @entries: Buffer which contains the entities to be mirrored
9961  * @count: number of entities contained in the buffer
9962  * @rule_id:the rule_id of the rule to be added
9963  *
9964  * Add a mirror rule for a given veb.
9965  *
9966  **/
9967 static enum i40e_status_code
9968 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9969                         uint16_t seid, uint16_t dst_id,
9970                         uint16_t rule_type, uint16_t *entries,
9971                         uint16_t count, uint16_t *rule_id)
9972 {
9973         struct i40e_aq_desc desc;
9974         struct i40e_aqc_add_delete_mirror_rule cmd;
9975         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9976                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9977                 &desc.params.raw;
9978         uint16_t buff_len;
9979         enum i40e_status_code status;
9980
9981         i40e_fill_default_direct_cmd_desc(&desc,
9982                                           i40e_aqc_opc_add_mirror_rule);
9983         memset(&cmd, 0, sizeof(cmd));
9984
9985         buff_len = sizeof(uint16_t) * count;
9986         desc.datalen = rte_cpu_to_le_16(buff_len);
9987         if (buff_len > 0)
9988                 desc.flags |= rte_cpu_to_le_16(
9989                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9990         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9991                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9992         cmd.num_entries = rte_cpu_to_le_16(count);
9993         cmd.seid = rte_cpu_to_le_16(seid);
9994         cmd.destination = rte_cpu_to_le_16(dst_id);
9995
9996         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9997         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9998         PMD_DRV_LOG(INFO,
9999                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10000                 hw->aq.asq_last_status, resp->rule_id,
10001                 resp->mirror_rules_used, resp->mirror_rules_free);
10002         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10003
10004         return status;
10005 }
10006
10007 /**
10008  * i40e_aq_del_mirror_rule
10009  * @hw: pointer to the hardware structure
10010  * @seid: VEB seid to add mirror rule to
10011  * @entries: Buffer which contains the entities to be mirrored
10012  * @count: number of entities contained in the buffer
10013  * @rule_id:the rule_id of the rule to be delete
10014  *
10015  * Delete a mirror rule for a given veb.
10016  *
10017  **/
10018 static enum i40e_status_code
10019 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10020                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10021                 uint16_t count, uint16_t rule_id)
10022 {
10023         struct i40e_aq_desc desc;
10024         struct i40e_aqc_add_delete_mirror_rule cmd;
10025         uint16_t buff_len = 0;
10026         enum i40e_status_code status;
10027         void *buff = NULL;
10028
10029         i40e_fill_default_direct_cmd_desc(&desc,
10030                                           i40e_aqc_opc_delete_mirror_rule);
10031         memset(&cmd, 0, sizeof(cmd));
10032         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10033                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10034                                                           I40E_AQ_FLAG_RD));
10035                 cmd.num_entries = count;
10036                 buff_len = sizeof(uint16_t) * count;
10037                 desc.datalen = rte_cpu_to_le_16(buff_len);
10038                 buff = (void *)entries;
10039         } else
10040                 /* rule id is filled in destination field for deleting mirror rule */
10041                 cmd.destination = rte_cpu_to_le_16(rule_id);
10042
10043         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10044                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10045         cmd.seid = rte_cpu_to_le_16(seid);
10046
10047         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10048         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10049
10050         return status;
10051 }
10052
10053 /**
10054  * i40e_mirror_rule_set
10055  * @dev: pointer to the hardware structure
10056  * @mirror_conf: mirror rule info
10057  * @sw_id: mirror rule's sw_id
10058  * @on: enable/disable
10059  *
10060  * set a mirror rule.
10061  *
10062  **/
10063 static int
10064 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10065                         struct rte_eth_mirror_conf *mirror_conf,
10066                         uint8_t sw_id, uint8_t on)
10067 {
10068         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10069         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10070         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10071         struct i40e_mirror_rule *parent = NULL;
10072         uint16_t seid, dst_seid, rule_id;
10073         uint16_t i, j = 0;
10074         int ret;
10075
10076         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10077
10078         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10079                 PMD_DRV_LOG(ERR,
10080                         "mirror rule can not be configured without veb or vfs.");
10081                 return -ENOSYS;
10082         }
10083         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10084                 PMD_DRV_LOG(ERR, "mirror table is full.");
10085                 return -ENOSPC;
10086         }
10087         if (mirror_conf->dst_pool > pf->vf_num) {
10088                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10089                                  mirror_conf->dst_pool);
10090                 return -EINVAL;
10091         }
10092
10093         seid = pf->main_vsi->veb->seid;
10094
10095         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10096                 if (sw_id <= it->index) {
10097                         mirr_rule = it;
10098                         break;
10099                 }
10100                 parent = it;
10101         }
10102         if (mirr_rule && sw_id == mirr_rule->index) {
10103                 if (on) {
10104                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10105                         return -EEXIST;
10106                 } else {
10107                         ret = i40e_aq_del_mirror_rule(hw, seid,
10108                                         mirr_rule->rule_type,
10109                                         mirr_rule->entries,
10110                                         mirr_rule->num_entries, mirr_rule->id);
10111                         if (ret < 0) {
10112                                 PMD_DRV_LOG(ERR,
10113                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10114                                         ret, hw->aq.asq_last_status);
10115                                 return -ENOSYS;
10116                         }
10117                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10118                         rte_free(mirr_rule);
10119                         pf->nb_mirror_rule--;
10120                         return 0;
10121                 }
10122         } else if (!on) {
10123                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10124                 return -ENOENT;
10125         }
10126
10127         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10128                                 sizeof(struct i40e_mirror_rule) , 0);
10129         if (!mirr_rule) {
10130                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10131                 return I40E_ERR_NO_MEMORY;
10132         }
10133         switch (mirror_conf->rule_type) {
10134         case ETH_MIRROR_VLAN:
10135                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10136                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10137                                 mirr_rule->entries[j] =
10138                                         mirror_conf->vlan.vlan_id[i];
10139                                 j++;
10140                         }
10141                 }
10142                 if (j == 0) {
10143                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10144                         rte_free(mirr_rule);
10145                         return -EINVAL;
10146                 }
10147                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10148                 break;
10149         case ETH_MIRROR_VIRTUAL_POOL_UP:
10150         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10151                 /* check if the specified pool bit is out of range */
10152                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10153                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10154                         rte_free(mirr_rule);
10155                         return -EINVAL;
10156                 }
10157                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10158                         if (mirror_conf->pool_mask & (1ULL << i)) {
10159                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10160                                 j++;
10161                         }
10162                 }
10163                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10164                         /* add pf vsi to entries */
10165                         mirr_rule->entries[j] = pf->main_vsi_seid;
10166                         j++;
10167                 }
10168                 if (j == 0) {
10169                         PMD_DRV_LOG(ERR, "pool is not specified.");
10170                         rte_free(mirr_rule);
10171                         return -EINVAL;
10172                 }
10173                 /* egress and ingress in aq commands means from switch but not port */
10174                 mirr_rule->rule_type =
10175                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10176                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10177                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10178                 break;
10179         case ETH_MIRROR_UPLINK_PORT:
10180                 /* egress and ingress in aq commands means from switch but not port*/
10181                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10182                 break;
10183         case ETH_MIRROR_DOWNLINK_PORT:
10184                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10185                 break;
10186         default:
10187                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10188                         mirror_conf->rule_type);
10189                 rte_free(mirr_rule);
10190                 return -EINVAL;
10191         }
10192
10193         /* If the dst_pool is equal to vf_num, consider it as PF */
10194         if (mirror_conf->dst_pool == pf->vf_num)
10195                 dst_seid = pf->main_vsi_seid;
10196         else
10197                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10198
10199         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10200                                       mirr_rule->rule_type, mirr_rule->entries,
10201                                       j, &rule_id);
10202         if (ret < 0) {
10203                 PMD_DRV_LOG(ERR,
10204                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10205                         ret, hw->aq.asq_last_status);
10206                 rte_free(mirr_rule);
10207                 return -ENOSYS;
10208         }
10209
10210         mirr_rule->index = sw_id;
10211         mirr_rule->num_entries = j;
10212         mirr_rule->id = rule_id;
10213         mirr_rule->dst_vsi_seid = dst_seid;
10214
10215         if (parent)
10216                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10217         else
10218                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10219
10220         pf->nb_mirror_rule++;
10221         return 0;
10222 }
10223
10224 /**
10225  * i40e_mirror_rule_reset
10226  * @dev: pointer to the device
10227  * @sw_id: mirror rule's sw_id
10228  *
10229  * reset a mirror rule.
10230  *
10231  **/
10232 static int
10233 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10234 {
10235         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10236         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10237         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10238         uint16_t seid;
10239         int ret;
10240
10241         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10242
10243         seid = pf->main_vsi->veb->seid;
10244
10245         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10246                 if (sw_id == it->index) {
10247                         mirr_rule = it;
10248                         break;
10249                 }
10250         }
10251         if (mirr_rule) {
10252                 ret = i40e_aq_del_mirror_rule(hw, seid,
10253                                 mirr_rule->rule_type,
10254                                 mirr_rule->entries,
10255                                 mirr_rule->num_entries, mirr_rule->id);
10256                 if (ret < 0) {
10257                         PMD_DRV_LOG(ERR,
10258                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10259                                 ret, hw->aq.asq_last_status);
10260                         return -ENOSYS;
10261                 }
10262                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10263                 rte_free(mirr_rule);
10264                 pf->nb_mirror_rule--;
10265         } else {
10266                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10267                 return -ENOENT;
10268         }
10269         return 0;
10270 }
10271
10272 static uint64_t
10273 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10274 {
10275         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10276         uint64_t systim_cycles;
10277
10278         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10279         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10280                         << 32;
10281
10282         return systim_cycles;
10283 }
10284
10285 static uint64_t
10286 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10287 {
10288         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10289         uint64_t rx_tstamp;
10290
10291         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10292         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10293                         << 32;
10294
10295         return rx_tstamp;
10296 }
10297
10298 static uint64_t
10299 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10300 {
10301         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10302         uint64_t tx_tstamp;
10303
10304         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10305         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10306                         << 32;
10307
10308         return tx_tstamp;
10309 }
10310
10311 static void
10312 i40e_start_timecounters(struct rte_eth_dev *dev)
10313 {
10314         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10315         struct i40e_adapter *adapter =
10316                         (struct i40e_adapter *)dev->data->dev_private;
10317         struct rte_eth_link link;
10318         uint32_t tsync_inc_l;
10319         uint32_t tsync_inc_h;
10320
10321         /* Get current link speed. */
10322         memset(&link, 0, sizeof(link));
10323         i40e_dev_link_update(dev, 1);
10324         rte_i40e_dev_atomic_read_link_status(dev, &link);
10325
10326         switch (link.link_speed) {
10327         case ETH_SPEED_NUM_40G:
10328                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10329                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10330                 break;
10331         case ETH_SPEED_NUM_10G:
10332                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10333                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10334                 break;
10335         case ETH_SPEED_NUM_1G:
10336                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10337                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10338                 break;
10339         default:
10340                 tsync_inc_l = 0x0;
10341                 tsync_inc_h = 0x0;
10342         }
10343
10344         /* Set the timesync increment value. */
10345         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10346         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10347
10348         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10349         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10350         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10351
10352         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10353         adapter->systime_tc.cc_shift = 0;
10354         adapter->systime_tc.nsec_mask = 0;
10355
10356         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10357         adapter->rx_tstamp_tc.cc_shift = 0;
10358         adapter->rx_tstamp_tc.nsec_mask = 0;
10359
10360         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10361         adapter->tx_tstamp_tc.cc_shift = 0;
10362         adapter->tx_tstamp_tc.nsec_mask = 0;
10363 }
10364
10365 static int
10366 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10367 {
10368         struct i40e_adapter *adapter =
10369                         (struct i40e_adapter *)dev->data->dev_private;
10370
10371         adapter->systime_tc.nsec += delta;
10372         adapter->rx_tstamp_tc.nsec += delta;
10373         adapter->tx_tstamp_tc.nsec += delta;
10374
10375         return 0;
10376 }
10377
10378 static int
10379 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10380 {
10381         uint64_t ns;
10382         struct i40e_adapter *adapter =
10383                         (struct i40e_adapter *)dev->data->dev_private;
10384
10385         ns = rte_timespec_to_ns(ts);
10386
10387         /* Set the timecounters to a new value. */
10388         adapter->systime_tc.nsec = ns;
10389         adapter->rx_tstamp_tc.nsec = ns;
10390         adapter->tx_tstamp_tc.nsec = ns;
10391
10392         return 0;
10393 }
10394
10395 static int
10396 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10397 {
10398         uint64_t ns, systime_cycles;
10399         struct i40e_adapter *adapter =
10400                         (struct i40e_adapter *)dev->data->dev_private;
10401
10402         systime_cycles = i40e_read_systime_cyclecounter(dev);
10403         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10404         *ts = rte_ns_to_timespec(ns);
10405
10406         return 0;
10407 }
10408
10409 static int
10410 i40e_timesync_enable(struct rte_eth_dev *dev)
10411 {
10412         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10413         uint32_t tsync_ctl_l;
10414         uint32_t tsync_ctl_h;
10415
10416         /* Stop the timesync system time. */
10417         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10418         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10419         /* Reset the timesync system time value. */
10420         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10421         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10422
10423         i40e_start_timecounters(dev);
10424
10425         /* Clear timesync registers. */
10426         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10427         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10428         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10429         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10430         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10431         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10432
10433         /* Enable timestamping of PTP packets. */
10434         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10435         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10436
10437         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10438         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10439         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10440
10441         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10442         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10443
10444         return 0;
10445 }
10446
10447 static int
10448 i40e_timesync_disable(struct rte_eth_dev *dev)
10449 {
10450         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10451         uint32_t tsync_ctl_l;
10452         uint32_t tsync_ctl_h;
10453
10454         /* Disable timestamping of transmitted PTP packets. */
10455         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10456         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10457
10458         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10459         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10460
10461         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10462         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10463
10464         /* Reset the timesync increment value. */
10465         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10466         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10467
10468         return 0;
10469 }
10470
10471 static int
10472 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10473                                 struct timespec *timestamp, uint32_t flags)
10474 {
10475         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10476         struct i40e_adapter *adapter =
10477                 (struct i40e_adapter *)dev->data->dev_private;
10478
10479         uint32_t sync_status;
10480         uint32_t index = flags & 0x03;
10481         uint64_t rx_tstamp_cycles;
10482         uint64_t ns;
10483
10484         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10485         if ((sync_status & (1 << index)) == 0)
10486                 return -EINVAL;
10487
10488         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10489         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10490         *timestamp = rte_ns_to_timespec(ns);
10491
10492         return 0;
10493 }
10494
10495 static int
10496 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10497                                 struct timespec *timestamp)
10498 {
10499         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10500         struct i40e_adapter *adapter =
10501                 (struct i40e_adapter *)dev->data->dev_private;
10502
10503         uint32_t sync_status;
10504         uint64_t tx_tstamp_cycles;
10505         uint64_t ns;
10506
10507         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10508         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10509                 return -EINVAL;
10510
10511         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10512         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10513         *timestamp = rte_ns_to_timespec(ns);
10514
10515         return 0;
10516 }
10517
10518 /*
10519  * i40e_parse_dcb_configure - parse dcb configure from user
10520  * @dev: the device being configured
10521  * @dcb_cfg: pointer of the result of parse
10522  * @*tc_map: bit map of enabled traffic classes
10523  *
10524  * Returns 0 on success, negative value on failure
10525  */
10526 static int
10527 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10528                          struct i40e_dcbx_config *dcb_cfg,
10529                          uint8_t *tc_map)
10530 {
10531         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10532         uint8_t i, tc_bw, bw_lf;
10533
10534         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10535
10536         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10537         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10538                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10539                 return -EINVAL;
10540         }
10541
10542         /* assume each tc has the same bw */
10543         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10544         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10545                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10546         /* to ensure the sum of tcbw is equal to 100 */
10547         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10548         for (i = 0; i < bw_lf; i++)
10549                 dcb_cfg->etscfg.tcbwtable[i]++;
10550
10551         /* assume each tc has the same Transmission Selection Algorithm */
10552         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10553                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10554
10555         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10556                 dcb_cfg->etscfg.prioritytable[i] =
10557                                 dcb_rx_conf->dcb_tc[i];
10558
10559         /* FW needs one App to configure HW */
10560         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10561         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10562         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10563         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10564
10565         if (dcb_rx_conf->nb_tcs == 0)
10566                 *tc_map = 1; /* tc0 only */
10567         else
10568                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10569
10570         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10571                 dcb_cfg->pfc.willing = 0;
10572                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10573                 dcb_cfg->pfc.pfcenable = *tc_map;
10574         }
10575         return 0;
10576 }
10577
10578
10579 static enum i40e_status_code
10580 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10581                               struct i40e_aqc_vsi_properties_data *info,
10582                               uint8_t enabled_tcmap)
10583 {
10584         enum i40e_status_code ret;
10585         int i, total_tc = 0;
10586         uint16_t qpnum_per_tc, bsf, qp_idx;
10587         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10588         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10589         uint16_t used_queues;
10590
10591         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10592         if (ret != I40E_SUCCESS)
10593                 return ret;
10594
10595         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10596                 if (enabled_tcmap & (1 << i))
10597                         total_tc++;
10598         }
10599         if (total_tc == 0)
10600                 total_tc = 1;
10601         vsi->enabled_tc = enabled_tcmap;
10602
10603         /* different VSI has different queues assigned */
10604         if (vsi->type == I40E_VSI_MAIN)
10605                 used_queues = dev_data->nb_rx_queues -
10606                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10607         else if (vsi->type == I40E_VSI_VMDQ2)
10608                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10609         else {
10610                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10611                 return I40E_ERR_NO_AVAILABLE_VSI;
10612         }
10613
10614         qpnum_per_tc = used_queues / total_tc;
10615         /* Number of queues per enabled TC */
10616         if (qpnum_per_tc == 0) {
10617                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10618                 return I40E_ERR_INVALID_QP_ID;
10619         }
10620         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10621                                 I40E_MAX_Q_PER_TC);
10622         bsf = rte_bsf32(qpnum_per_tc);
10623
10624         /**
10625          * Configure TC and queue mapping parameters, for enabled TC,
10626          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10627          * default queue will serve it.
10628          */
10629         qp_idx = 0;
10630         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10631                 if (vsi->enabled_tc & (1 << i)) {
10632                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10633                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10634                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10635                         qp_idx += qpnum_per_tc;
10636                 } else
10637                         info->tc_mapping[i] = 0;
10638         }
10639
10640         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10641         if (vsi->type == I40E_VSI_SRIOV) {
10642                 info->mapping_flags |=
10643                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10644                 for (i = 0; i < vsi->nb_qps; i++)
10645                         info->queue_mapping[i] =
10646                                 rte_cpu_to_le_16(vsi->base_queue + i);
10647         } else {
10648                 info->mapping_flags |=
10649                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10650                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10651         }
10652         info->valid_sections |=
10653                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10654
10655         return I40E_SUCCESS;
10656 }
10657
10658 /*
10659  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10660  * @veb: VEB to be configured
10661  * @tc_map: enabled TC bitmap
10662  *
10663  * Returns 0 on success, negative value on failure
10664  */
10665 static enum i40e_status_code
10666 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10667 {
10668         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10669         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10670         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10671         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10672         enum i40e_status_code ret = I40E_SUCCESS;
10673         int i;
10674         uint32_t bw_max;
10675
10676         /* Check if enabled_tc is same as existing or new TCs */
10677         if (veb->enabled_tc == tc_map)
10678                 return ret;
10679
10680         /* configure tc bandwidth */
10681         memset(&veb_bw, 0, sizeof(veb_bw));
10682         veb_bw.tc_valid_bits = tc_map;
10683         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10684         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10685                 if (tc_map & BIT_ULL(i))
10686                         veb_bw.tc_bw_share_credits[i] = 1;
10687         }
10688         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10689                                                    &veb_bw, NULL);
10690         if (ret) {
10691                 PMD_INIT_LOG(ERR,
10692                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10693                         hw->aq.asq_last_status);
10694                 return ret;
10695         }
10696
10697         memset(&ets_query, 0, sizeof(ets_query));
10698         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10699                                                    &ets_query, NULL);
10700         if (ret != I40E_SUCCESS) {
10701                 PMD_DRV_LOG(ERR,
10702                         "Failed to get switch_comp ETS configuration %u",
10703                         hw->aq.asq_last_status);
10704                 return ret;
10705         }
10706         memset(&bw_query, 0, sizeof(bw_query));
10707         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10708                                                   &bw_query, NULL);
10709         if (ret != I40E_SUCCESS) {
10710                 PMD_DRV_LOG(ERR,
10711                         "Failed to get switch_comp bandwidth configuration %u",
10712                         hw->aq.asq_last_status);
10713                 return ret;
10714         }
10715
10716         /* store and print out BW info */
10717         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10718         veb->bw_info.bw_max = ets_query.tc_bw_max;
10719         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10720         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10721         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10722                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10723                      I40E_16_BIT_WIDTH);
10724         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10725                 veb->bw_info.bw_ets_share_credits[i] =
10726                                 bw_query.tc_bw_share_credits[i];
10727                 veb->bw_info.bw_ets_credits[i] =
10728                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10729                 /* 4 bits per TC, 4th bit is reserved */
10730                 veb->bw_info.bw_ets_max[i] =
10731                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10732                                   RTE_LEN2MASK(3, uint8_t));
10733                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10734                             veb->bw_info.bw_ets_share_credits[i]);
10735                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10736                             veb->bw_info.bw_ets_credits[i]);
10737                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10738                             veb->bw_info.bw_ets_max[i]);
10739         }
10740
10741         veb->enabled_tc = tc_map;
10742
10743         return ret;
10744 }
10745
10746
10747 /*
10748  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10749  * @vsi: VSI to be configured
10750  * @tc_map: enabled TC bitmap
10751  *
10752  * Returns 0 on success, negative value on failure
10753  */
10754 static enum i40e_status_code
10755 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10756 {
10757         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10758         struct i40e_vsi_context ctxt;
10759         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10760         enum i40e_status_code ret = I40E_SUCCESS;
10761         int i;
10762
10763         /* Check if enabled_tc is same as existing or new TCs */
10764         if (vsi->enabled_tc == tc_map)
10765                 return ret;
10766
10767         /* configure tc bandwidth */
10768         memset(&bw_data, 0, sizeof(bw_data));
10769         bw_data.tc_valid_bits = tc_map;
10770         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10771         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10772                 if (tc_map & BIT_ULL(i))
10773                         bw_data.tc_bw_credits[i] = 1;
10774         }
10775         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10776         if (ret) {
10777                 PMD_INIT_LOG(ERR,
10778                         "AQ command Config VSI BW allocation per TC failed = %d",
10779                         hw->aq.asq_last_status);
10780                 goto out;
10781         }
10782         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10783                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10784
10785         /* Update Queue Pairs Mapping for currently enabled UPs */
10786         ctxt.seid = vsi->seid;
10787         ctxt.pf_num = hw->pf_id;
10788         ctxt.vf_num = 0;
10789         ctxt.uplink_seid = vsi->uplink_seid;
10790         ctxt.info = vsi->info;
10791         i40e_get_cap(hw);
10792         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10793         if (ret)
10794                 goto out;
10795
10796         /* Update the VSI after updating the VSI queue-mapping information */
10797         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10798         if (ret) {
10799                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10800                         hw->aq.asq_last_status);
10801                 goto out;
10802         }
10803         /* update the local VSI info with updated queue map */
10804         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10805                                         sizeof(vsi->info.tc_mapping));
10806         rte_memcpy(&vsi->info.queue_mapping,
10807                         &ctxt.info.queue_mapping,
10808                 sizeof(vsi->info.queue_mapping));
10809         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10810         vsi->info.valid_sections = 0;
10811
10812         /* query and update current VSI BW information */
10813         ret = i40e_vsi_get_bw_config(vsi);
10814         if (ret) {
10815                 PMD_INIT_LOG(ERR,
10816                          "Failed updating vsi bw info, err %s aq_err %s",
10817                          i40e_stat_str(hw, ret),
10818                          i40e_aq_str(hw, hw->aq.asq_last_status));
10819                 goto out;
10820         }
10821
10822         vsi->enabled_tc = tc_map;
10823
10824 out:
10825         return ret;
10826 }
10827
10828 /*
10829  * i40e_dcb_hw_configure - program the dcb setting to hw
10830  * @pf: pf the configuration is taken on
10831  * @new_cfg: new configuration
10832  * @tc_map: enabled TC bitmap
10833  *
10834  * Returns 0 on success, negative value on failure
10835  */
10836 static enum i40e_status_code
10837 i40e_dcb_hw_configure(struct i40e_pf *pf,
10838                       struct i40e_dcbx_config *new_cfg,
10839                       uint8_t tc_map)
10840 {
10841         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10842         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10843         struct i40e_vsi *main_vsi = pf->main_vsi;
10844         struct i40e_vsi_list *vsi_list;
10845         enum i40e_status_code ret;
10846         int i;
10847         uint32_t val;
10848
10849         /* Use the FW API if FW > v4.4*/
10850         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10851               (hw->aq.fw_maj_ver >= 5))) {
10852                 PMD_INIT_LOG(ERR,
10853                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10854                 return I40E_ERR_FIRMWARE_API_VERSION;
10855         }
10856
10857         /* Check if need reconfiguration */
10858         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10859                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10860                 return I40E_SUCCESS;
10861         }
10862
10863         /* Copy the new config to the current config */
10864         *old_cfg = *new_cfg;
10865         old_cfg->etsrec = old_cfg->etscfg;
10866         ret = i40e_set_dcb_config(hw);
10867         if (ret) {
10868                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10869                          i40e_stat_str(hw, ret),
10870                          i40e_aq_str(hw, hw->aq.asq_last_status));
10871                 return ret;
10872         }
10873         /* set receive Arbiter to RR mode and ETS scheme by default */
10874         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10875                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10876                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10877                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10878                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10879                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10880                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10881                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10882                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10883                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10884                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10885                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10886                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10887         }
10888         /* get local mib to check whether it is configured correctly */
10889         /* IEEE mode */
10890         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10891         /* Get Local DCB Config */
10892         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10893                                      &hw->local_dcbx_config);
10894
10895         /* if Veb is created, need to update TC of it at first */
10896         if (main_vsi->veb) {
10897                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10898                 if (ret)
10899                         PMD_INIT_LOG(WARNING,
10900                                  "Failed configuring TC for VEB seid=%d",
10901                                  main_vsi->veb->seid);
10902         }
10903         /* Update each VSI */
10904         i40e_vsi_config_tc(main_vsi, tc_map);
10905         if (main_vsi->veb) {
10906                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10907                         /* Beside main VSI and VMDQ VSIs, only enable default
10908                          * TC for other VSIs
10909                          */
10910                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10911                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10912                                                          tc_map);
10913                         else
10914                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10915                                                          I40E_DEFAULT_TCMAP);
10916                         if (ret)
10917                                 PMD_INIT_LOG(WARNING,
10918                                         "Failed configuring TC for VSI seid=%d",
10919                                         vsi_list->vsi->seid);
10920                         /* continue */
10921                 }
10922         }
10923         return I40E_SUCCESS;
10924 }
10925
10926 /*
10927  * i40e_dcb_init_configure - initial dcb config
10928  * @dev: device being configured
10929  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10930  *
10931  * Returns 0 on success, negative value on failure
10932  */
10933 int
10934 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10935 {
10936         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10937         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10938         int i, ret = 0;
10939
10940         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10941                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10942                 return -ENOTSUP;
10943         }
10944
10945         /* DCB initialization:
10946          * Update DCB configuration from the Firmware and configure
10947          * LLDP MIB change event.
10948          */
10949         if (sw_dcb == TRUE) {
10950                 ret = i40e_init_dcb(hw);
10951                 /* If lldp agent is stopped, the return value from
10952                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10953                  * adminq status. Otherwise, it should return success.
10954                  */
10955                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10956                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10957                         memset(&hw->local_dcbx_config, 0,
10958                                 sizeof(struct i40e_dcbx_config));
10959                         /* set dcb default configuration */
10960                         hw->local_dcbx_config.etscfg.willing = 0;
10961                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10962                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10963                         hw->local_dcbx_config.etscfg.tsatable[0] =
10964                                                 I40E_IEEE_TSA_ETS;
10965                         /* all UPs mapping to TC0 */
10966                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10967                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10968                         hw->local_dcbx_config.etsrec =
10969                                 hw->local_dcbx_config.etscfg;
10970                         hw->local_dcbx_config.pfc.willing = 0;
10971                         hw->local_dcbx_config.pfc.pfccap =
10972                                                 I40E_MAX_TRAFFIC_CLASS;
10973                         /* FW needs one App to configure HW */
10974                         hw->local_dcbx_config.numapps = 1;
10975                         hw->local_dcbx_config.app[0].selector =
10976                                                 I40E_APP_SEL_ETHTYPE;
10977                         hw->local_dcbx_config.app[0].priority = 3;
10978                         hw->local_dcbx_config.app[0].protocolid =
10979                                                 I40E_APP_PROTOID_FCOE;
10980                         ret = i40e_set_dcb_config(hw);
10981                         if (ret) {
10982                                 PMD_INIT_LOG(ERR,
10983                                         "default dcb config fails. err = %d, aq_err = %d.",
10984                                         ret, hw->aq.asq_last_status);
10985                                 return -ENOSYS;
10986                         }
10987                 } else {
10988                         PMD_INIT_LOG(ERR,
10989                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10990                                 ret, hw->aq.asq_last_status);
10991                         return -ENOTSUP;
10992                 }
10993         } else {
10994                 ret = i40e_aq_start_lldp(hw, NULL);
10995                 if (ret != I40E_SUCCESS)
10996                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10997
10998                 ret = i40e_init_dcb(hw);
10999                 if (!ret) {
11000                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11001                                 PMD_INIT_LOG(ERR,
11002                                         "HW doesn't support DCBX offload.");
11003                                 return -ENOTSUP;
11004                         }
11005                 } else {
11006                         PMD_INIT_LOG(ERR,
11007                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11008                                 ret, hw->aq.asq_last_status);
11009                         return -ENOTSUP;
11010                 }
11011         }
11012         return 0;
11013 }
11014
11015 /*
11016  * i40e_dcb_setup - setup dcb related config
11017  * @dev: device being configured
11018  *
11019  * Returns 0 on success, negative value on failure
11020  */
11021 static int
11022 i40e_dcb_setup(struct rte_eth_dev *dev)
11023 {
11024         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11025         struct i40e_dcbx_config dcb_cfg;
11026         uint8_t tc_map = 0;
11027         int ret = 0;
11028
11029         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11030                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11031                 return -ENOTSUP;
11032         }
11033
11034         if (pf->vf_num != 0)
11035                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11036
11037         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11038         if (ret) {
11039                 PMD_INIT_LOG(ERR, "invalid dcb config");
11040                 return -EINVAL;
11041         }
11042         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11043         if (ret) {
11044                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11045                 return -ENOSYS;
11046         }
11047
11048         return 0;
11049 }
11050
11051 static int
11052 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11053                       struct rte_eth_dcb_info *dcb_info)
11054 {
11055         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11056         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11057         struct i40e_vsi *vsi = pf->main_vsi;
11058         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11059         uint16_t bsf, tc_mapping;
11060         int i, j = 0;
11061
11062         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11063                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11064         else
11065                 dcb_info->nb_tcs = 1;
11066         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11067                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11068         for (i = 0; i < dcb_info->nb_tcs; i++)
11069                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11070
11071         /* get queue mapping if vmdq is disabled */
11072         if (!pf->nb_cfg_vmdq_vsi) {
11073                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11074                         if (!(vsi->enabled_tc & (1 << i)))
11075                                 continue;
11076                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11077                         dcb_info->tc_queue.tc_rxq[j][i].base =
11078                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11079                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11080                         dcb_info->tc_queue.tc_txq[j][i].base =
11081                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11082                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11083                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11084                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11085                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11086                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11087                 }
11088                 return 0;
11089         }
11090
11091         /* get queue mapping if vmdq is enabled */
11092         do {
11093                 vsi = pf->vmdq[j].vsi;
11094                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11095                         if (!(vsi->enabled_tc & (1 << i)))
11096                                 continue;
11097                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11098                         dcb_info->tc_queue.tc_rxq[j][i].base =
11099                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11100                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11101                         dcb_info->tc_queue.tc_txq[j][i].base =
11102                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11103                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11104                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11105                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11106                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11107                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11108                 }
11109                 j++;
11110         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11111         return 0;
11112 }
11113
11114 static int
11115 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11116 {
11117         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11118         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11119         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11120         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11121         uint16_t interval =
11122                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,
11123                                        pf->support_multi_driver);
11124         uint16_t msix_intr;
11125
11126         msix_intr = intr_handle->intr_vec[queue_id];
11127         if (msix_intr == I40E_MISC_VEC_ID)
11128                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11129                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11130                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11131                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
11132                                (interval <<
11133                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
11134         else
11135                 I40E_WRITE_REG(hw,
11136                                I40E_PFINT_DYN_CTLN(msix_intr -
11137                                                    I40E_RX_VEC_START),
11138                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11139                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11140                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
11141                                (interval <<
11142                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
11143
11144         I40E_WRITE_FLUSH(hw);
11145         rte_intr_enable(&pci_dev->intr_handle);
11146
11147         return 0;
11148 }
11149
11150 static int
11151 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11152 {
11153         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11154         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11155         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11156         uint16_t msix_intr;
11157
11158         msix_intr = intr_handle->intr_vec[queue_id];
11159         if (msix_intr == I40E_MISC_VEC_ID)
11160                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
11161         else
11162                 I40E_WRITE_REG(hw,
11163                                I40E_PFINT_DYN_CTLN(msix_intr -
11164                                                    I40E_RX_VEC_START),
11165                                0);
11166         I40E_WRITE_FLUSH(hw);
11167
11168         return 0;
11169 }
11170
11171 static int i40e_get_regs(struct rte_eth_dev *dev,
11172                          struct rte_dev_reg_info *regs)
11173 {
11174         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11175         uint32_t *ptr_data = regs->data;
11176         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11177         const struct i40e_reg_info *reg_info;
11178
11179         if (ptr_data == NULL) {
11180                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11181                 regs->width = sizeof(uint32_t);
11182                 return 0;
11183         }
11184
11185         /* The first few registers have to be read using AQ operations */
11186         reg_idx = 0;
11187         while (i40e_regs_adminq[reg_idx].name) {
11188                 reg_info = &i40e_regs_adminq[reg_idx++];
11189                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11190                         for (arr_idx2 = 0;
11191                                         arr_idx2 <= reg_info->count2;
11192                                         arr_idx2++) {
11193                                 reg_offset = arr_idx * reg_info->stride1 +
11194                                         arr_idx2 * reg_info->stride2;
11195                                 reg_offset += reg_info->base_addr;
11196                                 ptr_data[reg_offset >> 2] =
11197                                         i40e_read_rx_ctl(hw, reg_offset);
11198                         }
11199         }
11200
11201         /* The remaining registers can be read using primitives */
11202         reg_idx = 0;
11203         while (i40e_regs_others[reg_idx].name) {
11204                 reg_info = &i40e_regs_others[reg_idx++];
11205                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11206                         for (arr_idx2 = 0;
11207                                         arr_idx2 <= reg_info->count2;
11208                                         arr_idx2++) {
11209                                 reg_offset = arr_idx * reg_info->stride1 +
11210                                         arr_idx2 * reg_info->stride2;
11211                                 reg_offset += reg_info->base_addr;
11212                                 ptr_data[reg_offset >> 2] =
11213                                         I40E_READ_REG(hw, reg_offset);
11214                         }
11215         }
11216
11217         return 0;
11218 }
11219
11220 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11221 {
11222         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11223
11224         /* Convert word count to byte count */
11225         return hw->nvm.sr_size << 1;
11226 }
11227
11228 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11229                            struct rte_dev_eeprom_info *eeprom)
11230 {
11231         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11232         uint16_t *data = eeprom->data;
11233         uint16_t offset, length, cnt_words;
11234         int ret_code;
11235
11236         offset = eeprom->offset >> 1;
11237         length = eeprom->length >> 1;
11238         cnt_words = length;
11239
11240         if (offset > hw->nvm.sr_size ||
11241                 offset + length > hw->nvm.sr_size) {
11242                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11243                 return -EINVAL;
11244         }
11245
11246         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11247
11248         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11249         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11250                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11251                 return -EIO;
11252         }
11253
11254         return 0;
11255 }
11256
11257 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11258                                       struct ether_addr *mac_addr)
11259 {
11260         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11261         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11262         struct i40e_vsi *vsi = pf->main_vsi;
11263         struct i40e_mac_filter_info mac_filter;
11264         struct i40e_mac_filter *f;
11265         int ret;
11266
11267         if (!is_valid_assigned_ether_addr(mac_addr)) {
11268                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11269                 return;
11270         }
11271
11272         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11273                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11274                         break;
11275         }
11276
11277         if (f == NULL) {
11278                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11279                 return;
11280         }
11281
11282         mac_filter = f->mac_info;
11283         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11284         if (ret != I40E_SUCCESS) {
11285                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11286                 return;
11287         }
11288         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11289         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11290         if (ret != I40E_SUCCESS) {
11291                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11292                 return;
11293         }
11294         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11295
11296         i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11297                                   mac_addr->addr_bytes, NULL);
11298 }
11299
11300 static int
11301 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11302 {
11303         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11304         struct rte_eth_dev_data *dev_data = pf->dev_data;
11305         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11306         int ret = 0;
11307
11308         /* check if mtu is within the allowed range */
11309         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11310                 return -EINVAL;
11311
11312         /* mtu setting is forbidden if port is start */
11313         if (dev_data->dev_started) {
11314                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11315                             dev_data->port_id);
11316                 return -EBUSY;
11317         }
11318
11319         if (frame_size > ETHER_MAX_LEN)
11320                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
11321         else
11322                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
11323
11324         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11325
11326         return ret;
11327 }
11328
11329 /* Restore ethertype filter */
11330 static void
11331 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11332 {
11333         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11334         struct i40e_ethertype_filter_list
11335                 *ethertype_list = &pf->ethertype.ethertype_list;
11336         struct i40e_ethertype_filter *f;
11337         struct i40e_control_filter_stats stats;
11338         uint16_t flags;
11339
11340         TAILQ_FOREACH(f, ethertype_list, rules) {
11341                 flags = 0;
11342                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11343                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11344                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11345                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11346                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11347
11348                 memset(&stats, 0, sizeof(stats));
11349                 i40e_aq_add_rem_control_packet_filter(hw,
11350                                             f->input.mac_addr.addr_bytes,
11351                                             f->input.ether_type,
11352                                             flags, pf->main_vsi->seid,
11353                                             f->queue, 1, &stats, NULL);
11354         }
11355         PMD_DRV_LOG(INFO, "Ethertype filter:"
11356                     " mac_etype_used = %u, etype_used = %u,"
11357                     " mac_etype_free = %u, etype_free = %u",
11358                     stats.mac_etype_used, stats.etype_used,
11359                     stats.mac_etype_free, stats.etype_free);
11360 }
11361
11362 /* Restore tunnel filter */
11363 static void
11364 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11365 {
11366         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11367         struct i40e_vsi *vsi;
11368         struct i40e_pf_vf *vf;
11369         struct i40e_tunnel_filter_list
11370                 *tunnel_list = &pf->tunnel.tunnel_list;
11371         struct i40e_tunnel_filter *f;
11372         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11373         bool big_buffer = 0;
11374
11375         TAILQ_FOREACH(f, tunnel_list, rules) {
11376                 if (!f->is_to_vf)
11377                         vsi = pf->main_vsi;
11378                 else {
11379                         vf = &pf->vfs[f->vf_id];
11380                         vsi = vf->vsi;
11381                 }
11382                 memset(&cld_filter, 0, sizeof(cld_filter));
11383                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11384                         (struct ether_addr *)&cld_filter.element.outer_mac);
11385                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11386                         (struct ether_addr *)&cld_filter.element.inner_mac);
11387                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11388                 cld_filter.element.flags = f->input.flags;
11389                 cld_filter.element.tenant_id = f->input.tenant_id;
11390                 cld_filter.element.queue_number = f->queue;
11391                 rte_memcpy(cld_filter.general_fields,
11392                            f->input.general_fields,
11393                            sizeof(f->input.general_fields));
11394
11395                 if (((f->input.flags &
11396                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11397                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11398                     ((f->input.flags &
11399                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11400                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11401                     ((f->input.flags &
11402                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11403                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11404                         big_buffer = 1;
11405
11406                 if (big_buffer)
11407                         i40e_aq_add_cloud_filters_big_buffer(hw,
11408                                              vsi->seid, &cld_filter, 1);
11409                 else
11410                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11411                                                   &cld_filter.element, 1);
11412         }
11413 }
11414
11415 /* Restore rss filter */
11416 static inline void
11417 i40e_rss_filter_restore(struct i40e_pf *pf)
11418 {
11419         struct i40e_rte_flow_rss_conf *conf =
11420                                         &pf->rss_info;
11421         if (conf->num)
11422                 i40e_config_rss_filter(pf, conf, TRUE);
11423 }
11424
11425 static void
11426 i40e_filter_restore(struct i40e_pf *pf)
11427 {
11428         i40e_ethertype_filter_restore(pf);
11429         i40e_tunnel_filter_restore(pf);
11430         i40e_fdir_filter_restore(pf);
11431         i40e_rss_filter_restore(pf);
11432 }
11433
11434 static bool
11435 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11436 {
11437         if (strcmp(dev->device->driver->name, drv->driver.name))
11438                 return false;
11439
11440         return true;
11441 }
11442
11443 bool
11444 is_i40e_supported(struct rte_eth_dev *dev)
11445 {
11446         return is_device_supported(dev, &rte_i40e_pmd);
11447 }
11448
11449 struct i40e_customized_pctype*
11450 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11451 {
11452         int i;
11453
11454         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11455                 if (pf->customized_pctype[i].index == index)
11456                         return &pf->customized_pctype[i];
11457         }
11458         return NULL;
11459 }
11460
11461 static int
11462 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11463                               uint32_t pkg_size, uint32_t proto_num,
11464                               struct rte_pmd_i40e_proto_info *proto)
11465 {
11466         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11467         uint32_t pctype_num;
11468         struct rte_pmd_i40e_ptype_info *pctype;
11469         uint32_t buff_size;
11470         struct i40e_customized_pctype *new_pctype = NULL;
11471         uint8_t proto_id;
11472         uint8_t pctype_value;
11473         char name[64];
11474         uint32_t i, j, n;
11475         int ret;
11476
11477         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11478                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11479                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11480         if (ret) {
11481                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11482                 return -1;
11483         }
11484         if (!pctype_num) {
11485                 PMD_DRV_LOG(INFO, "No new pctype added");
11486                 return -1;
11487         }
11488
11489         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11490         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11491         if (!pctype) {
11492                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11493                 return -1;
11494         }
11495         /* get information about new pctype list */
11496         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11497                                         (uint8_t *)pctype, buff_size,
11498                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11499         if (ret) {
11500                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11501                 rte_free(pctype);
11502                 return -1;
11503         }
11504
11505         /* Update customized pctype. */
11506         for (i = 0; i < pctype_num; i++) {
11507                 pctype_value = pctype[i].ptype_id;
11508                 memset(name, 0, sizeof(name));
11509                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11510                         proto_id = pctype[i].protocols[j];
11511                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11512                                 continue;
11513                         for (n = 0; n < proto_num; n++) {
11514                                 if (proto[n].proto_id != proto_id)
11515                                         continue;
11516                                 strcat(name, proto[n].name);
11517                                 strcat(name, "_");
11518                                 break;
11519                         }
11520                 }
11521                 name[strlen(name) - 1] = '\0';
11522                 if (!strcmp(name, "GTPC"))
11523                         new_pctype =
11524                                 i40e_find_customized_pctype(pf,
11525                                                       I40E_CUSTOMIZED_GTPC);
11526                 else if (!strcmp(name, "GTPU_IPV4"))
11527                         new_pctype =
11528                                 i40e_find_customized_pctype(pf,
11529                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11530                 else if (!strcmp(name, "GTPU_IPV6"))
11531                         new_pctype =
11532                                 i40e_find_customized_pctype(pf,
11533                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11534                 else if (!strcmp(name, "GTPU"))
11535                         new_pctype =
11536                                 i40e_find_customized_pctype(pf,
11537                                                       I40E_CUSTOMIZED_GTPU);
11538                 if (new_pctype) {
11539                         new_pctype->pctype = pctype_value;
11540                         new_pctype->valid = true;
11541                 }
11542         }
11543
11544         rte_free(pctype);
11545         return 0;
11546 }
11547
11548 static int
11549 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11550                                uint32_t pkg_size, uint32_t proto_num,
11551                                struct rte_pmd_i40e_proto_info *proto)
11552 {
11553         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11554         uint16_t port_id = dev->data->port_id;
11555         uint32_t ptype_num;
11556         struct rte_pmd_i40e_ptype_info *ptype;
11557         uint32_t buff_size;
11558         uint8_t proto_id;
11559         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11560         uint32_t i, j, n;
11561         bool in_tunnel;
11562         int ret;
11563
11564         /* get information about new ptype num */
11565         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11566                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11567                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11568         if (ret) {
11569                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11570                 return ret;
11571         }
11572         if (!ptype_num) {
11573                 PMD_DRV_LOG(INFO, "No new ptype added");
11574                 return -1;
11575         }
11576
11577         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11578         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11579         if (!ptype) {
11580                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11581                 return -1;
11582         }
11583
11584         /* get information about new ptype list */
11585         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11586                                         (uint8_t *)ptype, buff_size,
11587                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11588         if (ret) {
11589                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11590                 rte_free(ptype);
11591                 return ret;
11592         }
11593
11594         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11595         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11596         if (!ptype_mapping) {
11597                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11598                 rte_free(ptype);
11599                 return -1;
11600         }
11601
11602         /* Update ptype mapping table. */
11603         for (i = 0; i < ptype_num; i++) {
11604                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11605                 ptype_mapping[i].sw_ptype = 0;
11606                 in_tunnel = false;
11607                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11608                         proto_id = ptype[i].protocols[j];
11609                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11610                                 continue;
11611                         for (n = 0; n < proto_num; n++) {
11612                                 if (proto[n].proto_id != proto_id)
11613                                         continue;
11614                                 memset(name, 0, sizeof(name));
11615                                 strcpy(name, proto[n].name);
11616                                 if (!strncasecmp(name, "PPPOE", 5))
11617                                         ptype_mapping[i].sw_ptype |=
11618                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11619                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11620                                          !in_tunnel) {
11621                                         ptype_mapping[i].sw_ptype |=
11622                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11623                                         ptype_mapping[i].sw_ptype |=
11624                                                 RTE_PTYPE_L4_FRAG;
11625                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11626                                            in_tunnel) {
11627                                         ptype_mapping[i].sw_ptype |=
11628                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11629                                         ptype_mapping[i].sw_ptype |=
11630                                                 RTE_PTYPE_INNER_L4_FRAG;
11631                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
11632                                         ptype_mapping[i].sw_ptype |=
11633                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11634                                         in_tunnel = true;
11635                                 } else if (!strncasecmp(name, "IPV4", 4) &&
11636                                            !in_tunnel)
11637                                         ptype_mapping[i].sw_ptype |=
11638                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11639                                 else if (!strncasecmp(name, "IPV4", 4) &&
11640                                          in_tunnel)
11641                                         ptype_mapping[i].sw_ptype |=
11642                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11643                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11644                                          !in_tunnel) {
11645                                         ptype_mapping[i].sw_ptype |=
11646                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11647                                         ptype_mapping[i].sw_ptype |=
11648                                                 RTE_PTYPE_L4_FRAG;
11649                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11650                                            in_tunnel) {
11651                                         ptype_mapping[i].sw_ptype |=
11652                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11653                                         ptype_mapping[i].sw_ptype |=
11654                                                 RTE_PTYPE_INNER_L4_FRAG;
11655                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
11656                                         ptype_mapping[i].sw_ptype |=
11657                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11658                                         in_tunnel = true;
11659                                 } else if (!strncasecmp(name, "IPV6", 4) &&
11660                                            !in_tunnel)
11661                                         ptype_mapping[i].sw_ptype |=
11662                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11663                                 else if (!strncasecmp(name, "IPV6", 4) &&
11664                                          in_tunnel)
11665                                         ptype_mapping[i].sw_ptype |=
11666                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11667                                 else if (!strncasecmp(name, "UDP", 3) &&
11668                                          !in_tunnel)
11669                                         ptype_mapping[i].sw_ptype |=
11670                                                 RTE_PTYPE_L4_UDP;
11671                                 else if (!strncasecmp(name, "UDP", 3) &&
11672                                          in_tunnel)
11673                                         ptype_mapping[i].sw_ptype |=
11674                                                 RTE_PTYPE_INNER_L4_UDP;
11675                                 else if (!strncasecmp(name, "TCP", 3) &&
11676                                          !in_tunnel)
11677                                         ptype_mapping[i].sw_ptype |=
11678                                                 RTE_PTYPE_L4_TCP;
11679                                 else if (!strncasecmp(name, "TCP", 3) &&
11680                                          in_tunnel)
11681                                         ptype_mapping[i].sw_ptype |=
11682                                                 RTE_PTYPE_INNER_L4_TCP;
11683                                 else if (!strncasecmp(name, "SCTP", 4) &&
11684                                          !in_tunnel)
11685                                         ptype_mapping[i].sw_ptype |=
11686                                                 RTE_PTYPE_L4_SCTP;
11687                                 else if (!strncasecmp(name, "SCTP", 4) &&
11688                                          in_tunnel)
11689                                         ptype_mapping[i].sw_ptype |=
11690                                                 RTE_PTYPE_INNER_L4_SCTP;
11691                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11692                                           !strncasecmp(name, "ICMPV6", 6)) &&
11693                                          !in_tunnel)
11694                                         ptype_mapping[i].sw_ptype |=
11695                                                 RTE_PTYPE_L4_ICMP;
11696                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11697                                           !strncasecmp(name, "ICMPV6", 6)) &&
11698                                          in_tunnel)
11699                                         ptype_mapping[i].sw_ptype |=
11700                                                 RTE_PTYPE_INNER_L4_ICMP;
11701                                 else if (!strncasecmp(name, "GTPC", 4)) {
11702                                         ptype_mapping[i].sw_ptype |=
11703                                                 RTE_PTYPE_TUNNEL_GTPC;
11704                                         in_tunnel = true;
11705                                 } else if (!strncasecmp(name, "GTPU", 4)) {
11706                                         ptype_mapping[i].sw_ptype |=
11707                                                 RTE_PTYPE_TUNNEL_GTPU;
11708                                         in_tunnel = true;
11709                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
11710                                         ptype_mapping[i].sw_ptype |=
11711                                                 RTE_PTYPE_TUNNEL_GRENAT;
11712                                         in_tunnel = true;
11713                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
11714                                         ptype_mapping[i].sw_ptype |=
11715                                                 RTE_PTYPE_TUNNEL_L2TP;
11716                                         in_tunnel = true;
11717                                 }
11718
11719                                 break;
11720                         }
11721                 }
11722         }
11723
11724         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11725                                                 ptype_num, 0);
11726         if (ret)
11727                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11728
11729         rte_free(ptype_mapping);
11730         rte_free(ptype);
11731         return ret;
11732 }
11733
11734 void
11735 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11736                               uint32_t pkg_size)
11737 {
11738         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11739         uint32_t proto_num;
11740         struct rte_pmd_i40e_proto_info *proto;
11741         uint32_t buff_size;
11742         uint32_t i;
11743         int ret;
11744
11745         /* get information about protocol number */
11746         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11747                                        (uint8_t *)&proto_num, sizeof(proto_num),
11748                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11749         if (ret) {
11750                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11751                 return;
11752         }
11753         if (!proto_num) {
11754                 PMD_DRV_LOG(INFO, "No new protocol added");
11755                 return;
11756         }
11757
11758         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11759         proto = rte_zmalloc("new_proto", buff_size, 0);
11760         if (!proto) {
11761                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11762                 return;
11763         }
11764
11765         /* get information about protocol list */
11766         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11767                                         (uint8_t *)proto, buff_size,
11768                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11769         if (ret) {
11770                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11771                 rte_free(proto);
11772                 return;
11773         }
11774
11775         /* Check if GTP is supported. */
11776         for (i = 0; i < proto_num; i++) {
11777                 if (!strncmp(proto[i].name, "GTP", 3)) {
11778                         pf->gtp_support = true;
11779                         break;
11780                 }
11781         }
11782
11783         /* Update customized pctype info */
11784         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11785                                             proto_num, proto);
11786         if (ret)
11787                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11788
11789         /* Update customized ptype info */
11790         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11791                                            proto_num, proto);
11792         if (ret)
11793                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11794
11795         rte_free(proto);
11796 }
11797
11798 /* Create a QinQ cloud filter
11799  *
11800  * The Fortville NIC has limited resources for tunnel filters,
11801  * so we can only reuse existing filters.
11802  *
11803  * In step 1 we define which Field Vector fields can be used for
11804  * filter types.
11805  * As we do not have the inner tag defined as a field,
11806  * we have to define it first, by reusing one of L1 entries.
11807  *
11808  * In step 2 we are replacing one of existing filter types with
11809  * a new one for QinQ.
11810  * As we reusing L1 and replacing L2, some of the default filter
11811  * types will disappear,which depends on L1 and L2 entries we reuse.
11812  *
11813  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11814  *
11815  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11816  *              later when we define the cloud filter.
11817  *      a.      Valid_flags.replace_cloud = 0
11818  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11819  *      c.      New_filter = 0x10
11820  *      d.      TR bit = 0xff (optional, not used here)
11821  *      e.      Buffer – 2 entries:
11822  *              i.      Byte 0 = 8 (outer vlan FV index).
11823  *                      Byte 1 = 0 (rsv)
11824  *                      Byte 2-3 = 0x0fff
11825  *              ii.     Byte 0 = 37 (inner vlan FV index).
11826  *                      Byte 1 =0 (rsv)
11827  *                      Byte 2-3 = 0x0fff
11828  *
11829  * Step 2:
11830  * 2.   Create cloud filter using two L1 filters entries: stag and
11831  *              new filter(outer vlan+ inner vlan)
11832  *      a.      Valid_flags.replace_cloud = 1
11833  *      b.      Old_filter = 1 (instead of outer IP)
11834  *      c.      New_filter = 0x10
11835  *      d.      Buffer – 2 entries:
11836  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11837  *                      Byte 1-3 = 0 (rsv)
11838  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11839  *                      Byte 9-11 = 0 (rsv)
11840  */
11841 static int
11842 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11843 {
11844         int ret = -ENOTSUP;
11845         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11846         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11847         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11848
11849         if (pf->support_multi_driver) {
11850                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
11851                 return ret;
11852         }
11853
11854         /* Init */
11855         memset(&filter_replace, 0,
11856                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11857         memset(&filter_replace_buf, 0,
11858                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11859
11860         /* create L1 filter */
11861         filter_replace.old_filter_type =
11862                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11863         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11864         filter_replace.tr_bit = 0;
11865
11866         /* Prepare the buffer, 2 entries */
11867         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11868         filter_replace_buf.data[0] |=
11869                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11870         /* Field Vector 12b mask */
11871         filter_replace_buf.data[2] = 0xff;
11872         filter_replace_buf.data[3] = 0x0f;
11873         filter_replace_buf.data[4] =
11874                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11875         filter_replace_buf.data[4] |=
11876                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11877         /* Field Vector 12b mask */
11878         filter_replace_buf.data[6] = 0xff;
11879         filter_replace_buf.data[7] = 0x0f;
11880         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11881                         &filter_replace_buf);
11882         if (ret != I40E_SUCCESS)
11883                 return ret;
11884         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11885                     "cloud l1 type is changed from 0x%x to 0x%x",
11886                     filter_replace.old_filter_type,
11887                     filter_replace.new_filter_type);
11888
11889         /* Apply the second L2 cloud filter */
11890         memset(&filter_replace, 0,
11891                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11892         memset(&filter_replace_buf, 0,
11893                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11894
11895         /* create L2 filter, input for L2 filter will be L1 filter  */
11896         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11897         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11898         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11899
11900         /* Prepare the buffer, 2 entries */
11901         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11902         filter_replace_buf.data[0] |=
11903                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11904         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11905         filter_replace_buf.data[4] |=
11906                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11907         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11908                         &filter_replace_buf);
11909         if (!ret) {
11910                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
11911                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11912                             "cloud filter type is changed from 0x%x to 0x%x",
11913                             filter_replace.old_filter_type,
11914                             filter_replace.new_filter_type);
11915         }
11916         return ret;
11917 }
11918
11919 int
11920 i40e_config_rss_filter(struct i40e_pf *pf,
11921                 struct i40e_rte_flow_rss_conf *conf, bool add)
11922 {
11923         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11924         uint32_t i, lut = 0;
11925         uint16_t j, num;
11926         struct rte_eth_rss_conf rss_conf = conf->rss_conf;
11927         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
11928
11929         if (!add) {
11930                 if (memcmp(conf, rss_info,
11931                         sizeof(struct i40e_rte_flow_rss_conf)) == 0) {
11932                         i40e_pf_disable_rss(pf);
11933                         memset(rss_info, 0,
11934                                 sizeof(struct i40e_rte_flow_rss_conf));
11935                         return 0;
11936                 }
11937                 return -EINVAL;
11938         }
11939
11940         if (rss_info->num)
11941                 return -EINVAL;
11942
11943         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
11944          * It's necessary to calculate the actual PF queues that are configured.
11945          */
11946         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
11947                 num = i40e_pf_calc_configured_queues_num(pf);
11948         else
11949                 num = pf->dev_data->nb_rx_queues;
11950
11951         num = RTE_MIN(num, conf->num);
11952         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
11953                         num);
11954
11955         if (num == 0) {
11956                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
11957                 return -ENOTSUP;
11958         }
11959
11960         /* Fill in redirection table */
11961         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
11962                 if (j == num)
11963                         j = 0;
11964                 lut = (lut << 8) | (conf->queue[j] & ((0x1 <<
11965                         hw->func_caps.rss_table_entry_width) - 1));
11966                 if ((i & 3) == 3)
11967                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
11968         }
11969
11970         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
11971                 i40e_pf_disable_rss(pf);
11972                 return 0;
11973         }
11974         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
11975                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
11976                 /* Random default keys */
11977                 static uint32_t rss_key_default[] = {0x6b793944,
11978                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
11979                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
11980                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
11981
11982                 rss_conf.rss_key = (uint8_t *)rss_key_default;
11983                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
11984                                                         sizeof(uint32_t);
11985         }
11986
11987         i40e_hw_rss_hash_set(pf, &rss_conf);
11988
11989         rte_memcpy(rss_info,
11990                 conf, sizeof(struct i40e_rte_flow_rss_conf));
11991
11992         return 0;
11993 }
11994
11995 RTE_INIT(i40e_init_log);
11996 static void
11997 i40e_init_log(void)
11998 {
11999         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12000         if (i40e_logtype_init >= 0)
12001                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12002         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12003         if (i40e_logtype_driver >= 0)
12004                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12005 }
12006
12007 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12008                               QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12009                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");