drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64
  65 /* Maximun number of MAC addresses */
  66 #define I40E_NUM_MACADDR_MAX       64
  67 #define I40E_CLEAR_PXE_WAIT_MS     200
  68
  69 /* Maximun number of capability elements */
  70 #define I40E_MAX_CAP_ELE_NUM       128
  71
  72 /* Wait count and inteval */
  73 #define I40E_CHK_Q_ENA_COUNT       1000
  74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  75
  76 /* Maximun number of VSI */
  77 #define I40E_MAX_NUM_VSIS          (384UL)
  78
  79 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  80
  81 /* Flow control default timer */
  82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  83
  84 /* Flow control default high water */
  85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  86
  87 /* Flow control default low water */
  88 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Receive Average Packet Size in Byte*/
 100 #define I40E_PACKET_AVERAGE_SIZE 128
 101
 102 /* Mask of PF interrupt causes */
 103 #define I40E_PFINT_ICR0_ENA_MASK ( \
 104                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 105                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 106                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 107                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 108                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 110                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 114
 115 #define I40E_FLOW_TYPES ( \
 116         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 127
 128 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 129 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 130 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 131 #define I40E_PRTTSYN_TSYNENA  0x80000000
 132 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 133
 134 #define I40E_MAX_PERCENT            100
 135 #define I40E_DEFAULT_DCB_APP_NUM    1
 136 #define I40E_DEFAULT_DCB_APP_PRIO   3
 137
 138 #define I40E_PRTQF_FD_INSET(_i, _j)  (0x00250000 + ((_i) * 64 + (_j) * 32))
 139 #define I40E_GLQF_FD_MSK(_i, _j)     (0x00267200 + ((_i) * 4 + (_j) * 8))
 140 #define I40E_GLQF_FD_MSK_FIELD       0x0000FFFF
 141 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))
 142 #define I40E_GLQF_HASH_MSK(_i, _j)   (0x00267A00 + ((_i) * 4 + (_j) * 8))
 143 #define I40E_GLQF_HASH_MSK_FIELD      0x0000FFFF
 144
 145 #define I40E_INSET_NONE            0x00000000000000000ULL
 146
 147 /* bit0 ~ bit 7 */
 148 #define I40E_INSET_DMAC            0x0000000000000001ULL
 149 #define I40E_INSET_SMAC            0x0000000000000002ULL
 150 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 151 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 152 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 153
 154 /* bit 8 ~ bit 15 */
 155 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 156 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 157 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 158 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 159 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 160 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 161 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 162
 163 /* bit 16 ~ bit 31 */
 164 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 165 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 166 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 167 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 168 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 169 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 170 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 171 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 172
 173 /* bit 32 ~ bit 47, tunnel fields */
 174 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 175 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 176 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 177 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 178 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 179 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 180
 181 /* bit 48 ~ bit 55 */
 182 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 183
 184 /* bit 56 ~ bit 63, Flex Payload */
 185 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 191 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 192 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 193 #define I40E_INSET_FLEX_PAYLOAD \
 194         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 195         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W3 | \
 196         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 197         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 198
 199 /**
 200  * Below are values for writing un-exposed registers suggested
 201  * by silicon experts
 202  */
 203 /* Destination MAC address */
 204 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 205 /* Source MAC address */
 206 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 207 /* VLAN tag in the outer L2 header */
 208 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000000800000ULL
 209 /* VLAN tag in the inner L2 header */
 210 #define I40E_REG_INSET_L2_INNER_VLAN             0x0000000001000000ULL
 211 /* Source IPv4 address */
 212 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 213 /* Destination IPv4 address */
 214 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 215 /* IPv4 Type of Service (TOS) */
 216 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 217 /* IPv4 Protocol */
 218 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 219 /* Source IPv6 address */
 220 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 221 /* Destination IPv6 address */
 222 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 223 /* IPv6 Traffic Class (TC) */
 224 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 225 /* IPv6 Next Header */
 226 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 227 /* Source L4 port */
 228 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 229 /* Destination L4 port */
 230 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 231 /* SCTP verification tag */
 232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 235 /* Source port of tunneling UDP */
 236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 237 /* Destination port of tunneling UDP */
 238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 239 /* UDP Tunneling ID, NVGRE/GRE key */
 240 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 241 /* Last ether type */
 242 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 243 /* Tunneling outer destination IPv4 address */
 244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 245 /* Tunneling outer destination IPv6 address */
 246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 247 /* 1st word of flex payload */
 248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 249 /* 2nd word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 251 /* 3rd word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 253 /* 4th word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 255 /* 5th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 257 /* 6th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 259 /* 7th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 261 /* 8th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 263
 264 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 265
 266 #define I40E_TRANSLATE_INSET 0
 267 #define I40E_TRANSLATE_REG   1
 268
 269 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 270 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 271 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 272 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 273
 274 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 275 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 276 static int i40e_dev_configure(struct rte_eth_dev *dev);
 277 static int i40e_dev_start(struct rte_eth_dev *dev);
 278 static void i40e_dev_stop(struct rte_eth_dev *dev);
 279 static void i40e_dev_close(struct rte_eth_dev *dev);
 280 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 281 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 282 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 283 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 284 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 285 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 286 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 287                                struct rte_eth_stats *stats);
 288 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 289                                struct rte_eth_xstats *xstats, unsigned n);
 290 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 291 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 292                                             uint16_t queue_id,
 293                                             uint8_t stat_idx,
 294                                             uint8_t is_rx);
 295 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 296                               struct rte_eth_dev_info *dev_info);
 297 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 298                                 uint16_t vlan_id,
 299                                 int on);
 300 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 301 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 302 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 303                                       uint16_t queue,
 304                                       int on);
 305 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 306 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 307 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 308 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 309                               struct rte_eth_fc_conf *fc_conf);
 310 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 311                               struct rte_eth_fc_conf *fc_conf);
 312 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 313                                        struct rte_eth_pfc_conf *pfc_conf);
 314 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 315                           struct ether_addr *mac_addr,
 316                           uint32_t index,
 317                           uint32_t pool);
 318 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 319 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 320                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 321                                     uint16_t reta_size);
 322 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 323                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 324                                    uint16_t reta_size);
 325
 326 static int i40e_get_cap(struct i40e_hw *hw);
 327 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 328 static int i40e_pf_setup(struct i40e_pf *pf);
 329 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 330 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 331 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 332 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 333 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 334                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 335 static void i40e_stat_update_48(struct i40e_hw *hw,
 336                                uint32_t hireg,
 337                                uint32_t loreg,
 338                                bool offset_loaded,
 339                                uint64_t *offset,
 340                                uint64_t *stat);
 341 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 342 static void i40e_dev_interrupt_handler(
 343                 __rte_unused struct rte_intr_handle *handle, void *param);
 344 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 345                                 uint32_t base, uint32_t num);
 346 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 347 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 348                         uint32_t base);
 349 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 350                         uint16_t num);
 351 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 352 static int i40e_veb_release(struct i40e_veb *veb);
 353 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 354                                                 struct i40e_vsi *vsi);
 355 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 356 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 357 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 358                                              struct i40e_macvlan_filter *mv_f,
 359                                              int num,
 360                                              struct ether_addr *addr);
 361 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 362                                              struct i40e_macvlan_filter *mv_f,
 363                                              int num,
 364                                              uint16_t vlan);
 365 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 366 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 367                                     struct rte_eth_rss_conf *rss_conf);
 368 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 369                                       struct rte_eth_rss_conf *rss_conf);
 370 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 371                                 struct rte_eth_udp_tunnel *udp_tunnel);
 372 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 373                                 struct rte_eth_udp_tunnel *udp_tunnel);
 374 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 375                         struct rte_eth_ethertype_filter *filter,
 376                         bool add);
 377 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 378                                 enum rte_filter_op filter_op,
 379                                 void *arg);
 380 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 381                                 enum rte_filter_type filter_type,
 382                                 enum rte_filter_op filter_op,
 383                                 void *arg);
 384 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 385                                   struct rte_eth_dcb_info *dcb_info);
 386 static void i40e_configure_registers(struct i40e_hw *hw);
 387 static void i40e_hw_init(struct i40e_hw *hw);
 388 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 389 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 390                         struct rte_eth_mirror_conf *mirror_conf,
 391                         uint8_t sw_id, uint8_t on);
 392 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 393
 394 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 395 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 396 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 397                                            struct timespec *timestamp,
 398                                            uint32_t flags);
 399 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 400                                            struct timespec *timestamp);
 401 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 402 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 403                                          uint16_t queue_id);
 404 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 405                                           uint16_t queue_id);
 406
 407 static const struct rte_pci_id pci_id_i40e_map[] = {
 408 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 409 #include "rte_pci_dev_ids.h"
 410 { .vendor_id = 0, /* sentinel */ },
 411 };
 412
 413 static const struct eth_dev_ops i40e_eth_dev_ops = {
 414         .dev_configure                = i40e_dev_configure,
 415         .dev_start                    = i40e_dev_start,
 416         .dev_stop                     = i40e_dev_stop,
 417         .dev_close                    = i40e_dev_close,
 418         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 419         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 420         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 421         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 422         .dev_set_link_up              = i40e_dev_set_link_up,
 423         .dev_set_link_down            = i40e_dev_set_link_down,
 424         .link_update                  = i40e_dev_link_update,
 425         .stats_get                    = i40e_dev_stats_get,
 426         .xstats_get                   = i40e_dev_xstats_get,
 427         .stats_reset                  = i40e_dev_stats_reset,
 428         .xstats_reset                 = i40e_dev_stats_reset,
 429         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 430         .dev_infos_get                = i40e_dev_info_get,
 431         .vlan_filter_set              = i40e_vlan_filter_set,
 432         .vlan_tpid_set                = i40e_vlan_tpid_set,
 433         .vlan_offload_set             = i40e_vlan_offload_set,
 434         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 435         .vlan_pvid_set                = i40e_vlan_pvid_set,
 436         .rx_queue_start               = i40e_dev_rx_queue_start,
 437         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 438         .tx_queue_start               = i40e_dev_tx_queue_start,
 439         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 440         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 441         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 442         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 443         .rx_queue_release             = i40e_dev_rx_queue_release,
 444         .rx_queue_count               = i40e_dev_rx_queue_count,
 445         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 446         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 447         .tx_queue_release             = i40e_dev_tx_queue_release,
 448         .dev_led_on                   = i40e_dev_led_on,
 449         .dev_led_off                  = i40e_dev_led_off,
 450         .flow_ctrl_get                = i40e_flow_ctrl_get,
 451         .flow_ctrl_set                = i40e_flow_ctrl_set,
 452         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 453         .mac_addr_add                 = i40e_macaddr_add,
 454         .mac_addr_remove              = i40e_macaddr_remove,
 455         .reta_update                  = i40e_dev_rss_reta_update,
 456         .reta_query                   = i40e_dev_rss_reta_query,
 457         .rss_hash_update              = i40e_dev_rss_hash_update,
 458         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 459         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 460         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 461         .filter_ctrl                  = i40e_dev_filter_ctrl,
 462         .rxq_info_get                 = i40e_rxq_info_get,
 463         .txq_info_get                 = i40e_txq_info_get,
 464         .mirror_rule_set              = i40e_mirror_rule_set,
 465         .mirror_rule_reset            = i40e_mirror_rule_reset,
 466         .timesync_enable              = i40e_timesync_enable,
 467         .timesync_disable             = i40e_timesync_disable,
 468         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 469         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 470         .get_dcb_info                 = i40e_dev_get_dcb_info,
 471 };
 472
 473 /* store statistics names and its offset in stats structure */
 474 struct rte_i40e_xstats_name_off {
 475         char name[RTE_ETH_XSTATS_NAME_SIZE];
 476         unsigned offset;
 477 };
 478
 479 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 480         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 481         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 482         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 483         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 484         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 485                 rx_unknown_protocol)},
 486         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 487         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 488         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 489         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 490 };
 491
 492 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 493         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 494                 tx_dropped_link_down)},
 495         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 496         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 497                 illegal_bytes)},
 498         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 499         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 500                 mac_local_faults)},
 501         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 502                 mac_remote_faults)},
 503         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 504                 rx_length_errors)},
 505         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 506         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 507         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 508         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 509         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 510         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 511                 rx_size_127)},
 512         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 513                 rx_size_255)},
 514         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 515                 rx_size_511)},
 516         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 517                 rx_size_1023)},
 518         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 519                 rx_size_1522)},
 520         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 521                 rx_size_big)},
 522         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 523                 rx_undersize)},
 524         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 525                 rx_oversize)},
 526         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 527                 mac_short_packet_dropped)},
 528         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 529                 rx_fragments)},
 530         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 531         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 532         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 533                 tx_size_127)},
 534         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 535                 tx_size_255)},
 536         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 537                 tx_size_511)},
 538         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 539                 tx_size_1023)},
 540         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 541                 tx_size_1522)},
 542         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 543                 tx_size_big)},
 544         {"rx_flow_director_atr_match_packets",
 545                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 546         {"rx_flow_director_sb_match_packets",
 547                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 548         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 549                 tx_lpi_status)},
 550         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 551                 rx_lpi_status)},
 552         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 553                 tx_lpi_count)},
 554         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 555                 rx_lpi_count)},
 556 };
 557
 558 /* Q Stats: 5 stats are exposed for each queue, implemented in xstats_get() */
 559 #define I40E_NB_HW_PORT_Q_STATS (8 * 5)
 560
 561 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 562                 sizeof(rte_i40e_stats_strings[0]))
 563 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 564                 sizeof(rte_i40e_hw_port_strings[0]))
 565 #define I40E_NB_XSTATS (I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + \
 566                 I40E_NB_HW_PORT_Q_STATS)
 567
 568 static struct eth_driver rte_i40e_pmd = {
 569         .pci_drv = {
 570                 .name = "rte_i40e_pmd",
 571                 .id_table = pci_id_i40e_map,
 572                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 573                         RTE_PCI_DRV_DETACHABLE,
 574         },
 575         .eth_dev_init = eth_i40e_dev_init,
 576         .eth_dev_uninit = eth_i40e_dev_uninit,
 577         .dev_private_size = sizeof(struct i40e_adapter),
 578 };
 579
 580 static inline int
 581 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 582                                      struct rte_eth_link *link)
 583 {
 584         struct rte_eth_link *dst = link;
 585         struct rte_eth_link *src = &(dev->data->dev_link);
 586
 587         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 588                                         *(uint64_t *)src) == 0)
 589                 return -1;
 590
 591         return 0;
 592 }
 593
 594 static inline int
 595 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 596                                       struct rte_eth_link *link)
 597 {
 598         struct rte_eth_link *dst = &(dev->data->dev_link);
 599         struct rte_eth_link *src = link;
 600
 601         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 602                                         *(uint64_t *)src) == 0)
 603                 return -1;
 604
 605         return 0;
 606 }
 607
 608 /*
 609  * Driver initialization routine.
 610  * Invoked once at EAL init time.
 611  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 612  */
 613 static int
 614 rte_i40e_pmd_init(const char *name __rte_unused,
 615                   const char *params __rte_unused)
 616 {
 617         PMD_INIT_FUNC_TRACE();
 618         rte_eth_driver_register(&rte_i40e_pmd);
 619
 620         return 0;
 621 }
 622
 623 static struct rte_driver rte_i40e_driver = {
 624         .type = PMD_PDEV,
 625         .init = rte_i40e_pmd_init,
 626 };
 627
 628 PMD_REGISTER_DRIVER(rte_i40e_driver);
 629
 630 /*
 631  * Initialize registers for flexible payload, which should be set by NVM.
 632  * This should be removed from code once it is fixed in NVM.
 633  */
 634 #ifndef I40E_GLQF_ORT
 635 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 636 #endif
 637 #ifndef I40E_GLQF_PIT
 638 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 639 #endif
 640
 641 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 642 {
 643         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 644         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 645         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 646         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 647         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 648         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 649         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 650         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 651         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 652         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 653
 654         /* GLQF_PIT Registers */
 655         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 656         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 657 }
 658
 659 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 660
 661 /*
 662  * Add a ethertype filter to drop all flow control frames transmitted
 663  * from VSIs.
 664 */
 665 static void
 666 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 667 {
 668         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 669         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 670                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 671                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 672         int ret;
 673
 674         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 675                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 676                                 pf->main_vsi_seid, 0,
 677                                 TRUE, NULL, NULL);
 678         if (ret)
 679                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 680                                   " frames from VSIs.");
 681 }
 682
 683 static int
 684 eth_i40e_dev_init(struct rte_eth_dev *dev)
 685 {
 686         struct rte_pci_device *pci_dev;
 687         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 688         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 689         struct i40e_vsi *vsi;
 690         int ret;
 691         uint32_t len;
 692         uint8_t aq_fail = 0;
 693
 694         PMD_INIT_FUNC_TRACE();
 695
 696         dev->dev_ops = &i40e_eth_dev_ops;
 697         dev->rx_pkt_burst = i40e_recv_pkts;
 698         dev->tx_pkt_burst = i40e_xmit_pkts;
 699
 700         /* for secondary processes, we don't initialise any further as primary
 701          * has already done this work. Only check we don't need a different
 702          * RX function */
 703         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 704                 i40e_set_rx_function(dev);
 705                 i40e_set_tx_function(dev);
 706                 return 0;
 707         }
 708         pci_dev = dev->pci_dev;
 709
 710         rte_eth_copy_pci_info(dev, pci_dev);
 711
 712         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 713         pf->adapter->eth_dev = dev;
 714         pf->dev_data = dev->data;
 715
 716         hw->back = I40E_PF_TO_ADAPTER(pf);
 717         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 718         if (!hw->hw_addr) {
 719                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 720                              "as address is NULL");
 721                 return -ENODEV;
 722         }
 723
 724         hw->vendor_id = pci_dev->id.vendor_id;
 725         hw->device_id = pci_dev->id.device_id;
 726         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 727         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 728         hw->bus.device = pci_dev->addr.devid;
 729         hw->bus.func = pci_dev->addr.function;
 730         hw->adapter_stopped = 0;
 731
 732         /* Make sure all is clean before doing PF reset */
 733         i40e_clear_hw(hw);
 734
 735         /* Initialize the hardware */
 736         i40e_hw_init(hw);
 737
 738         /* Reset here to make sure all is clean for each PF */
 739         ret = i40e_pf_reset(hw);
 740         if (ret) {
 741                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 742                 return ret;
 743         }
 744
 745         /* Initialize the shared code (base driver) */
 746         ret = i40e_init_shared_code(hw);
 747         if (ret) {
 748                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 749                 return ret;
 750         }
 751
 752         /*
 753          * To work around the NVM issue,initialize registers
 754          * for flexible payload by software.
 755          * It should be removed once issues are fixed in NVM.
 756          */
 757         i40e_flex_payload_reg_init(hw);
 758
 759         /* Initialize the parameters for adminq */
 760         i40e_init_adminq_parameter(hw);
 761         ret = i40e_init_adminq(hw);
 762         if (ret != I40E_SUCCESS) {
 763                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 764                 return -EIO;
 765         }
 766         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 767                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 768                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 769                      ((hw->nvm.version >> 12) & 0xf),
 770                      ((hw->nvm.version >> 4) & 0xff),
 771                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 772
 773         /* Clear PXE mode */
 774         i40e_clear_pxe_mode(hw);
 775
 776         /*
 777          * On X710, performance number is far from the expectation on recent
 778          * firmware versions. The fix for this issue may not be integrated in
 779          * the following firmware version. So the workaround in software driver
 780          * is needed. It needs to modify the initial values of 3 internal only
 781          * registers. Note that the workaround can be removed when it is fixed
 782          * in firmware in the future.
 783          */
 784         i40e_configure_registers(hw);
 785
 786         /* Get hw capabilities */
 787         ret = i40e_get_cap(hw);
 788         if (ret != I40E_SUCCESS) {
 789                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 790                 goto err_get_capabilities;
 791         }
 792
 793         /* Initialize parameters for PF */
 794         ret = i40e_pf_parameter_init(dev);
 795         if (ret != 0) {
 796                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 797                 goto err_parameter_init;
 798         }
 799
 800         /* Initialize the queue management */
 801         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 802         if (ret < 0) {
 803                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 804                 goto err_qp_pool_init;
 805         }
 806         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 807                                 hw->func_caps.num_msix_vectors - 1);
 808         if (ret < 0) {
 809                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 810                 goto err_msix_pool_init;
 811         }
 812
 813         /* Initialize lan hmc */
 814         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 815                                 hw->func_caps.num_rx_qp, 0, 0);
 816         if (ret != I40E_SUCCESS) {
 817                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 818                 goto err_init_lan_hmc;
 819         }
 820
 821         /* Configure lan hmc */
 822         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 823         if (ret != I40E_SUCCESS) {
 824                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 825                 goto err_configure_lan_hmc;
 826         }
 827
 828         /* Get and check the mac address */
 829         i40e_get_mac_addr(hw, hw->mac.addr);
 830         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 831                 PMD_INIT_LOG(ERR, "mac address is not valid");
 832                 ret = -EIO;
 833                 goto err_get_mac_addr;
 834         }
 835         /* Copy the permanent MAC address */
 836         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 837                         (struct ether_addr *) hw->mac.perm_addr);
 838
 839         /* Disable flow control */
 840         hw->fc.requested_mode = I40E_FC_NONE;
 841         i40e_set_fc(hw, &aq_fail, TRUE);
 842
 843         /* PF setup, which includes VSI setup */
 844         ret = i40e_pf_setup(pf);
 845         if (ret) {
 846                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 847                 goto err_setup_pf_switch;
 848         }
 849
 850         vsi = pf->main_vsi;
 851
 852         /* Disable double vlan by default */
 853         i40e_vsi_config_double_vlan(vsi, FALSE);
 854
 855         if (!vsi->max_macaddrs)
 856                 len = ETHER_ADDR_LEN;
 857         else
 858                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 859
 860         /* Should be after VSI initialized */
 861         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 862         if (!dev->data->mac_addrs) {
 863                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 864                                         "for storing mac address");
 865                 goto err_mac_alloc;
 866         }
 867         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 868                                         &dev->data->mac_addrs[0]);
 869
 870         /* initialize pf host driver to setup SRIOV resource if applicable */
 871         i40e_pf_host_init(dev);
 872
 873         /* register callback func to eal lib */
 874         rte_intr_callback_register(&(pci_dev->intr_handle),
 875                 i40e_dev_interrupt_handler, (void *)dev);
 876
 877         /* configure and enable device interrupt */
 878         i40e_pf_config_irq0(hw, TRUE);
 879         i40e_pf_enable_irq0(hw);
 880
 881         /* enable uio intr after callback register */
 882         rte_intr_enable(&(pci_dev->intr_handle));
 883         /*
 884          * Add an ethertype filter to drop all flow control frames transmitted
 885          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 886          * frames to wire.
 887          */
 888         i40e_add_tx_flow_control_drop_filter(pf);
 889
 890         /* initialize mirror rule list */
 891         TAILQ_INIT(&pf->mirror_list);
 892
 893         /* Init dcb to sw mode by default */
 894         ret = i40e_dcb_init_configure(dev, TRUE);
 895         if (ret != I40E_SUCCESS) {
 896                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 897                 pf->flags &= ~I40E_FLAG_DCB;
 898         }
 899
 900         return 0;
 901
 902 err_mac_alloc:
 903         i40e_vsi_release(pf->main_vsi);
 904 err_setup_pf_switch:
 905 err_get_mac_addr:
 906 err_configure_lan_hmc:
 907         (void)i40e_shutdown_lan_hmc(hw);
 908 err_init_lan_hmc:
 909         i40e_res_pool_destroy(&pf->msix_pool);
 910 err_msix_pool_init:
 911         i40e_res_pool_destroy(&pf->qp_pool);
 912 err_qp_pool_init:
 913 err_parameter_init:
 914 err_get_capabilities:
 915         (void)i40e_shutdown_adminq(hw);
 916
 917         return ret;
 918 }
 919
 920 static int
 921 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 922 {
 923         struct rte_pci_device *pci_dev;
 924         struct i40e_hw *hw;
 925         struct i40e_filter_control_settings settings;
 926         int ret;
 927         uint8_t aq_fail = 0;
 928
 929         PMD_INIT_FUNC_TRACE();
 930
 931         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 932                 return 0;
 933
 934         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 935         pci_dev = dev->pci_dev;
 936
 937         if (hw->adapter_stopped == 0)
 938                 i40e_dev_close(dev);
 939
 940         dev->dev_ops = NULL;
 941         dev->rx_pkt_burst = NULL;
 942         dev->tx_pkt_burst = NULL;
 943
 944         /* Disable LLDP */
 945         ret = i40e_aq_stop_lldp(hw, true, NULL);
 946         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 947                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 948
 949         /* Clear PXE mode */
 950         i40e_clear_pxe_mode(hw);
 951
 952         /* Unconfigure filter control */
 953         memset(&settings, 0, sizeof(settings));
 954         ret = i40e_set_filter_control(hw, &settings);
 955         if (ret)
 956                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 957                                         ret);
 958
 959         /* Disable flow control */
 960         hw->fc.requested_mode = I40E_FC_NONE;
 961         i40e_set_fc(hw, &aq_fail, TRUE);
 962
 963         /* uninitialize pf host driver */
 964         i40e_pf_host_uninit(dev);
 965
 966         rte_free(dev->data->mac_addrs);
 967         dev->data->mac_addrs = NULL;
 968
 969         /* disable uio intr before callback unregister */
 970         rte_intr_disable(&(pci_dev->intr_handle));
 971
 972         /* register callback func to eal lib */
 973         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 974                 i40e_dev_interrupt_handler, (void *)dev);
 975
 976         return 0;
 977 }
 978
 979 static int
 980 i40e_dev_configure(struct rte_eth_dev *dev)
 981 {
 982         struct i40e_adapter *ad =
 983                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 984         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 985         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 986         int i, ret;
 987
 988         /* Initialize to TRUE. If any of Rx queues doesn't meet the
 989          * bulk allocation or vector Rx preconditions we will reset it.
 990          */
 991         ad->rx_bulk_alloc_allowed = true;
 992         ad->rx_vec_allowed = true;
 993         ad->tx_simple_allowed = true;
 994         ad->tx_vec_allowed = true;
 995
 996         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 997                 ret = i40e_fdir_setup(pf);
 998                 if (ret != I40E_SUCCESS) {
 999                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1000                         return -ENOTSUP;
1001                 }
1002                 ret = i40e_fdir_configure(dev);
1003                 if (ret < 0) {
1004                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1005                         goto err;
1006                 }
1007         } else
1008                 i40e_fdir_teardown(pf);
1009
1010         ret = i40e_dev_init_vlan(dev);
1011         if (ret < 0)
1012                 goto err;
1013
1014         /* VMDQ setup.
1015          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1016          *  RSS setting have different requirements.
1017          *  General PMD driver call sequence are NIC init, configure,
1018          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1019          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1020          *  applicable. So, VMDQ setting has to be done before
1021          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1022          *  For RSS setting, it will try to calculate actual configured RX queue
1023          *  number, which will be available after rx_queue_setup(). dev_start()
1024          *  function is good to place RSS setup.
1025          */
1026         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1027                 ret = i40e_vmdq_setup(dev);
1028                 if (ret)
1029                         goto err;
1030         }
1031
1032         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1033                 ret = i40e_dcb_setup(dev);
1034                 if (ret) {
1035                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1036                         goto err_dcb;
1037                 }
1038         }
1039
1040         return 0;
1041
1042 err_dcb:
1043         /* need to release vmdq resource if exists */
1044         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1045                 i40e_vsi_release(pf->vmdq[i].vsi);
1046                 pf->vmdq[i].vsi = NULL;
1047         }
1048         rte_free(pf->vmdq);
1049         pf->vmdq = NULL;
1050 err:
1051         /* need to release fdir resource if exists */
1052         i40e_fdir_teardown(pf);
1053         return ret;
1054 }
1055
1056 void
1057 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1058 {
1059         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1060         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1061         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1062         uint16_t msix_vect = vsi->msix_intr;
1063         uint16_t i;
1064
1065         for (i = 0; i < vsi->nb_qps; i++) {
1066                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1067                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1068                 rte_wmb();
1069         }
1070
1071         if (vsi->type != I40E_VSI_SRIOV) {
1072                 if (!rte_intr_allow_others(intr_handle)) {
1073                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1074                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1075                         I40E_WRITE_REG(hw,
1076                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1077                                        0);
1078                 } else {
1079                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1080                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1081                         I40E_WRITE_REG(hw,
1082                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1083                                                        msix_vect - 1), 0);
1084                 }
1085         } else {
1086                 uint32_t reg;
1087                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1088                         vsi->user_param + (msix_vect - 1);
1089
1090                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1091                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1092         }
1093         I40E_WRITE_FLUSH(hw);
1094 }
1095
1096 static void
1097 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1098                        int base_queue, int nb_queue)
1099 {
1100         int i;
1101         uint32_t val;
1102         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1103
1104         /* Bind all RX queues to allocated MSIX interrupt */
1105         for (i = 0; i < nb_queue; i++) {
1106                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1107                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1108                         ((base_queue + i + 1) <<
1109                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1110                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1111                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1112
1113                 if (i == nb_queue - 1)
1114                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1115                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1116         }
1117
1118         /* Write first RX queue to Link list register as the head element */
1119         if (vsi->type != I40E_VSI_SRIOV) {
1120                 uint16_t interval =
1121                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1122
1123                 if (msix_vect == I40E_MISC_VEC_ID) {
1124                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1125                                        (base_queue <<
1126                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1127                                        (0x0 <<
1128                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1129                         I40E_WRITE_REG(hw,
1130                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1131                                        interval);
1132                 } else {
1133                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1134                                        (base_queue <<
1135                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1136                                        (0x0 <<
1137                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1138                         I40E_WRITE_REG(hw,
1139                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1140                                                        msix_vect - 1),
1141                                        interval);
1142                 }
1143         } else {
1144                 uint32_t reg;
1145
1146                 if (msix_vect == I40E_MISC_VEC_ID) {
1147                         I40E_WRITE_REG(hw,
1148                                        I40E_VPINT_LNKLST0(vsi->user_param),
1149                                        (base_queue <<
1150                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1151                                        (0x0 <<
1152                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1153                 } else {
1154                         /* num_msix_vectors_vf needs to minus irq0 */
1155                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1156                                 vsi->user_param + (msix_vect - 1);
1157
1158                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1159                                        (base_queue <<
1160                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1161                                        (0x0 <<
1162                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1163                 }
1164         }
1165
1166         I40E_WRITE_FLUSH(hw);
1167 }
1168
1169 void
1170 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1171 {
1172         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1173         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1174         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1175         uint16_t msix_vect = vsi->msix_intr;
1176         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1177         uint16_t queue_idx = 0;
1178         int record = 0;
1179         uint32_t val;
1180         int i;
1181
1182         for (i = 0; i < vsi->nb_qps; i++) {
1183                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1184                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1185         }
1186
1187         /* INTENA flag is not auto-cleared for interrupt */
1188         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1189         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1190                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1191                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1192         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1193
1194         /* VF bind interrupt */
1195         if (vsi->type == I40E_VSI_SRIOV) {
1196                 __vsi_queues_bind_intr(vsi, msix_vect,
1197                                        vsi->base_queue, vsi->nb_qps);
1198                 return;
1199         }
1200
1201         /* PF & VMDq bind interrupt */
1202         if (rte_intr_dp_is_en(intr_handle)) {
1203                 if (vsi->type == I40E_VSI_MAIN) {
1204                         queue_idx = 0;
1205                         record = 1;
1206                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1207                         struct i40e_vsi *main_vsi =
1208                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1209                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1210                         record = 1;
1211                 }
1212         }
1213
1214         for (i = 0; i < vsi->nb_used_qps; i++) {
1215                 if (nb_msix <= 1) {
1216                         if (!rte_intr_allow_others(intr_handle))
1217                                 /* allow to share MISC_VEC_ID */
1218                                 msix_vect = I40E_MISC_VEC_ID;
1219
1220                         /* no enough msix_vect, map all to one */
1221                         __vsi_queues_bind_intr(vsi, msix_vect,
1222                                                vsi->base_queue + i,
1223                                                vsi->nb_used_qps - i);
1224                         for (; !!record && i < vsi->nb_used_qps; i++)
1225                                 intr_handle->intr_vec[queue_idx + i] =
1226                                         msix_vect;
1227                         break;
1228                 }
1229                 /* 1:1 queue/msix_vect mapping */
1230                 __vsi_queues_bind_intr(vsi, msix_vect,
1231                                        vsi->base_queue + i, 1);
1232                 if (!!record)
1233                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1234
1235                 msix_vect++;
1236                 nb_msix--;
1237         }
1238 }
1239
1240 static void
1241 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1242 {
1243         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1244         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1245         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1246         uint16_t interval = i40e_calc_itr_interval(\
1247                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1248         uint16_t msix_intr, i;
1249
1250         if (rte_intr_allow_others(intr_handle))
1251                 for (i = 0; i < vsi->nb_msix; i++) {
1252                         msix_intr = vsi->msix_intr + i;
1253                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1254                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1255                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1256                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1257                                 (interval <<
1258                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1259                 }
1260         else
1261                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1262                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1263                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1264                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1265                                (interval <<
1266                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1267
1268         I40E_WRITE_FLUSH(hw);
1269 }
1270
1271 static void
1272 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1273 {
1274         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1275         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1276         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1277         uint16_t msix_intr, i;
1278
1279         if (rte_intr_allow_others(intr_handle))
1280                 for (i = 0; i < vsi->nb_msix; i++) {
1281                         msix_intr = vsi->msix_intr + i;
1282                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1283                                        0);
1284                 }
1285         else
1286                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1287
1288         I40E_WRITE_FLUSH(hw);
1289 }
1290
1291 static inline uint8_t
1292 i40e_parse_link_speed(uint16_t eth_link_speed)
1293 {
1294         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1295
1296         switch (eth_link_speed) {
1297         case ETH_LINK_SPEED_40G:
1298                 link_speed = I40E_LINK_SPEED_40GB;
1299                 break;
1300         case ETH_LINK_SPEED_20G:
1301                 link_speed = I40E_LINK_SPEED_20GB;
1302                 break;
1303         case ETH_LINK_SPEED_10G:
1304                 link_speed = I40E_LINK_SPEED_10GB;
1305                 break;
1306         case ETH_LINK_SPEED_1000:
1307                 link_speed = I40E_LINK_SPEED_1GB;
1308                 break;
1309         case ETH_LINK_SPEED_100:
1310                 link_speed = I40E_LINK_SPEED_100MB;
1311                 break;
1312         }
1313
1314         return link_speed;
1315 }
1316
1317 static int
1318 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
1319 {
1320         enum i40e_status_code status;
1321         struct i40e_aq_get_phy_abilities_resp phy_ab;
1322         struct i40e_aq_set_phy_config phy_conf;
1323         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1324                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1325                         I40E_AQ_PHY_FLAG_LOW_POWER;
1326         const uint8_t advt = I40E_LINK_SPEED_40GB |
1327                         I40E_LINK_SPEED_10GB |
1328                         I40E_LINK_SPEED_1GB |
1329                         I40E_LINK_SPEED_100MB;
1330         int ret = -ENOTSUP;
1331
1332         /* Skip it on 40G interfaces, as a workaround for the link issue */
1333         if (i40e_is_40G_device(hw->device_id))
1334                 return I40E_SUCCESS;
1335
1336         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1337                                               NULL);
1338         if (status)
1339                 return ret;
1340
1341         memset(&phy_conf, 0, sizeof(phy_conf));
1342
1343         /* bits 0-2 use the values from get_phy_abilities_resp */
1344         abilities &= ~mask;
1345         abilities |= phy_ab.abilities & mask;
1346
1347         /* update ablities and speed */
1348         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1349                 phy_conf.link_speed = advt;
1350         else
1351                 phy_conf.link_speed = force_speed;
1352
1353         phy_conf.abilities = abilities;
1354
1355         /* use get_phy_abilities_resp value for the rest */
1356         phy_conf.phy_type = phy_ab.phy_type;
1357         phy_conf.eee_capability = phy_ab.eee_capability;
1358         phy_conf.eeer = phy_ab.eeer_val;
1359         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1360
1361         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1362                     phy_ab.abilities, phy_ab.link_speed);
1363         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1364                     phy_conf.abilities, phy_conf.link_speed);
1365
1366         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1367         if (status)
1368                 return ret;
1369
1370         return I40E_SUCCESS;
1371 }
1372
1373 static int
1374 i40e_apply_link_speed(struct rte_eth_dev *dev)
1375 {
1376         uint8_t speed;
1377         uint8_t abilities = 0;
1378         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1379         struct rte_eth_conf *conf = &dev->data->dev_conf;
1380
1381         speed = i40e_parse_link_speed(conf->link_speed);
1382         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1383         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1384                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1385         else
1386                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1387
1388         return i40e_phy_conf_link(hw, abilities, speed);
1389 }
1390
1391 static int
1392 i40e_dev_start(struct rte_eth_dev *dev)
1393 {
1394         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1395         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1396         struct i40e_vsi *main_vsi = pf->main_vsi;
1397         int ret, i;
1398         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1399         uint32_t intr_vector = 0;
1400
1401         hw->adapter_stopped = 0;
1402
1403         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1404                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1405                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1406                              dev->data->dev_conf.link_duplex,
1407                              dev->data->port_id);
1408                 return -EINVAL;
1409         }
1410
1411         rte_intr_disable(intr_handle);
1412
1413         if ((rte_intr_cap_multiple(intr_handle) ||
1414              !RTE_ETH_DEV_SRIOV(dev).active) &&
1415             dev->data->dev_conf.intr_conf.rxq != 0) {
1416                 intr_vector = dev->data->nb_rx_queues;
1417                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1418                         return -1;
1419         }
1420
1421         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1422                 intr_handle->intr_vec =
1423                         rte_zmalloc("intr_vec",
1424                                     dev->data->nb_rx_queues * sizeof(int),
1425                                     0);
1426                 if (!intr_handle->intr_vec) {
1427                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1428                                      " intr_vec\n", dev->data->nb_rx_queues);
1429                         return -ENOMEM;
1430                 }
1431         }
1432
1433         /* Initialize VSI */
1434         ret = i40e_dev_rxtx_init(pf);
1435         if (ret != I40E_SUCCESS) {
1436                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1437                 goto err_up;
1438         }
1439
1440         /* Map queues with MSIX interrupt */
1441         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1442                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1443         i40e_vsi_queues_bind_intr(main_vsi);
1444         i40e_vsi_enable_queues_intr(main_vsi);
1445
1446         /* Map VMDQ VSI queues with MSIX interrupt */
1447         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1448                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1449                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1450                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1451         }
1452
1453         /* enable FDIR MSIX interrupt */
1454         if (pf->fdir.fdir_vsi) {
1455                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1456                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1457         }
1458
1459         /* Enable all queues which have been configured */
1460         ret = i40e_dev_switch_queues(pf, TRUE);
1461         if (ret != I40E_SUCCESS) {
1462                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1463                 goto err_up;
1464         }
1465
1466         /* Enable receiving broadcast packets */
1467         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1468         if (ret != I40E_SUCCESS)
1469                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1470
1471         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1472                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1473                                                 true, NULL);
1474                 if (ret != I40E_SUCCESS)
1475                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1476         }
1477
1478         /* Apply link configure */
1479         ret = i40e_apply_link_speed(dev);
1480         if (I40E_SUCCESS != ret) {
1481                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1482                 goto err_up;
1483         }
1484
1485         if (!rte_intr_allow_others(intr_handle)) {
1486                 rte_intr_callback_unregister(intr_handle,
1487                                              i40e_dev_interrupt_handler,
1488                                              (void *)dev);
1489                 /* configure and enable device interrupt */
1490                 i40e_pf_config_irq0(hw, FALSE);
1491                 i40e_pf_enable_irq0(hw);
1492
1493                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1494                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1495                                      " no intr multiplex\n");
1496         }
1497
1498         /* enable uio intr after callback register */
1499         rte_intr_enable(intr_handle);
1500
1501         return I40E_SUCCESS;
1502
1503 err_up:
1504         i40e_dev_switch_queues(pf, FALSE);
1505         i40e_dev_clear_queues(dev);
1506
1507         return ret;
1508 }
1509
1510 static void
1511 i40e_dev_stop(struct rte_eth_dev *dev)
1512 {
1513         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1514         struct i40e_vsi *main_vsi = pf->main_vsi;
1515         struct i40e_mirror_rule *p_mirror;
1516         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1517         int i;
1518
1519         /* Disable all queues */
1520         i40e_dev_switch_queues(pf, FALSE);
1521
1522         /* un-map queues with interrupt registers */
1523         i40e_vsi_disable_queues_intr(main_vsi);
1524         i40e_vsi_queues_unbind_intr(main_vsi);
1525
1526         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1527                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1528                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1529         }
1530
1531         if (pf->fdir.fdir_vsi) {
1532                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1533                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1534         }
1535         /* Clear all queues and release memory */
1536         i40e_dev_clear_queues(dev);
1537
1538         /* Set link down */
1539         i40e_dev_set_link_down(dev);
1540
1541         /* Remove all mirror rules */
1542         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1543                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1544                 rte_free(p_mirror);
1545         }
1546         pf->nb_mirror_rule = 0;
1547
1548         if (!rte_intr_allow_others(intr_handle))
1549                 /* resume to the default handler */
1550                 rte_intr_callback_register(intr_handle,
1551                                            i40e_dev_interrupt_handler,
1552                                            (void *)dev);
1553
1554         /* Clean datapath event and queue/vec mapping */
1555         rte_intr_efd_disable(intr_handle);
1556         if (intr_handle->intr_vec) {
1557                 rte_free(intr_handle->intr_vec);
1558                 intr_handle->intr_vec = NULL;
1559         }
1560 }
1561
1562 static void
1563 i40e_dev_close(struct rte_eth_dev *dev)
1564 {
1565         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1566         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1567         uint32_t reg;
1568         int i;
1569
1570         PMD_INIT_FUNC_TRACE();
1571
1572         i40e_dev_stop(dev);
1573         hw->adapter_stopped = 1;
1574         i40e_dev_free_queues(dev);
1575
1576         /* Disable interrupt */
1577         i40e_pf_disable_irq0(hw);
1578         rte_intr_disable(&(dev->pci_dev->intr_handle));
1579
1580         /* shutdown and destroy the HMC */
1581         i40e_shutdown_lan_hmc(hw);
1582
1583         /* release all the existing VSIs and VEBs */
1584         i40e_fdir_teardown(pf);
1585         i40e_vsi_release(pf->main_vsi);
1586
1587         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1588                 i40e_vsi_release(pf->vmdq[i].vsi);
1589                 pf->vmdq[i].vsi = NULL;
1590         }
1591
1592         rte_free(pf->vmdq);
1593         pf->vmdq = NULL;
1594
1595         /* shutdown the adminq */
1596         i40e_aq_queue_shutdown(hw, true);
1597         i40e_shutdown_adminq(hw);
1598
1599         i40e_res_pool_destroy(&pf->qp_pool);
1600         i40e_res_pool_destroy(&pf->msix_pool);
1601
1602         /* force a PF reset to clean anything leftover */
1603         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1604         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1605                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1606         I40E_WRITE_FLUSH(hw);
1607 }
1608
1609 static void
1610 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1611 {
1612         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1613         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614         struct i40e_vsi *vsi = pf->main_vsi;
1615         int status;
1616
1617         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1618                                                         true, NULL);
1619         if (status != I40E_SUCCESS)
1620                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1621
1622         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1623                                                         TRUE, NULL);
1624         if (status != I40E_SUCCESS)
1625                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1626
1627 }
1628
1629 static void
1630 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1631 {
1632         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1633         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1634         struct i40e_vsi *vsi = pf->main_vsi;
1635         int status;
1636
1637         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1638                                                         false, NULL);
1639         if (status != I40E_SUCCESS)
1640                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1641
1642         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1643                                                         false, NULL);
1644         if (status != I40E_SUCCESS)
1645                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1646 }
1647
1648 static void
1649 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1650 {
1651         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1652         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653         struct i40e_vsi *vsi = pf->main_vsi;
1654         int ret;
1655
1656         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1657         if (ret != I40E_SUCCESS)
1658                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1659 }
1660
1661 static void
1662 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1663 {
1664         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1665         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1666         struct i40e_vsi *vsi = pf->main_vsi;
1667         int ret;
1668
1669         if (dev->data->promiscuous == 1)
1670                 return; /* must remain in all_multicast mode */
1671
1672         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1673                                 vsi->seid, FALSE, NULL);
1674         if (ret != I40E_SUCCESS)
1675                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1676 }
1677
1678 /*
1679  * Set device link up.
1680  */
1681 static int
1682 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1683 {
1684         /* re-apply link speed setting */
1685         return i40e_apply_link_speed(dev);
1686 }
1687
1688 /*
1689  * Set device link down.
1690  */
1691 static int
1692 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1693 {
1694         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1695         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1696         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1697
1698         return i40e_phy_conf_link(hw, abilities, speed);
1699 }
1700
1701 int
1702 i40e_dev_link_update(struct rte_eth_dev *dev,
1703                      int wait_to_complete)
1704 {
1705 #define CHECK_INTERVAL 100  /* 100ms */
1706 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1707         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1708         struct i40e_link_status link_status;
1709         struct rte_eth_link link, old;
1710         int status;
1711         unsigned rep_cnt = MAX_REPEAT_TIME;
1712
1713         memset(&link, 0, sizeof(link));
1714         memset(&old, 0, sizeof(old));
1715         memset(&link_status, 0, sizeof(link_status));
1716         rte_i40e_dev_atomic_read_link_status(dev, &old);
1717
1718         do {
1719                 /* Get link status information from hardware */
1720                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1721                 if (status != I40E_SUCCESS) {
1722                         link.link_speed = ETH_LINK_SPEED_100;
1723                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1724                         PMD_DRV_LOG(ERR, "Failed to get link info");
1725                         goto out;
1726                 }
1727
1728                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1729                 if (!wait_to_complete)
1730                         break;
1731
1732                 rte_delay_ms(CHECK_INTERVAL);
1733         } while (!link.link_status && rep_cnt--);
1734
1735         if (!link.link_status)
1736                 goto out;
1737
1738         /* i40e uses full duplex only */
1739         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1740
1741         /* Parse the link status */
1742         switch (link_status.link_speed) {
1743         case I40E_LINK_SPEED_100MB:
1744                 link.link_speed = ETH_LINK_SPEED_100;
1745                 break;
1746         case I40E_LINK_SPEED_1GB:
1747                 link.link_speed = ETH_LINK_SPEED_1000;
1748                 break;
1749         case I40E_LINK_SPEED_10GB:
1750                 link.link_speed = ETH_LINK_SPEED_10G;
1751                 break;
1752         case I40E_LINK_SPEED_20GB:
1753                 link.link_speed = ETH_LINK_SPEED_20G;
1754                 break;
1755         case I40E_LINK_SPEED_40GB:
1756                 link.link_speed = ETH_LINK_SPEED_40G;
1757                 break;
1758         default:
1759                 link.link_speed = ETH_LINK_SPEED_100;
1760                 break;
1761         }
1762
1763 out:
1764         rte_i40e_dev_atomic_write_link_status(dev, &link);
1765         if (link.link_status == old.link_status)
1766                 return -1;
1767
1768         return 0;
1769 }
1770
1771 /* Get all the statistics of a VSI */
1772 void
1773 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1774 {
1775         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1776         struct i40e_eth_stats *nes = &vsi->eth_stats;
1777         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1778         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1779
1780         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1781                             vsi->offset_loaded, &oes->rx_bytes,
1782                             &nes->rx_bytes);
1783         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1784                             vsi->offset_loaded, &oes->rx_unicast,
1785                             &nes->rx_unicast);
1786         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1787                             vsi->offset_loaded, &oes->rx_multicast,
1788                             &nes->rx_multicast);
1789         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1790                             vsi->offset_loaded, &oes->rx_broadcast,
1791                             &nes->rx_broadcast);
1792         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1793                             &oes->rx_discards, &nes->rx_discards);
1794         /* GLV_REPC not supported */
1795         /* GLV_RMPC not supported */
1796         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1797                             &oes->rx_unknown_protocol,
1798                             &nes->rx_unknown_protocol);
1799         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1800                             vsi->offset_loaded, &oes->tx_bytes,
1801                             &nes->tx_bytes);
1802         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1803                             vsi->offset_loaded, &oes->tx_unicast,
1804                             &nes->tx_unicast);
1805         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1806                             vsi->offset_loaded, &oes->tx_multicast,
1807                             &nes->tx_multicast);
1808         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1809                             vsi->offset_loaded,  &oes->tx_broadcast,
1810                             &nes->tx_broadcast);
1811         /* GLV_TDPC not supported */
1812         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1813                             &oes->tx_errors, &nes->tx_errors);
1814         vsi->offset_loaded = true;
1815
1816         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1817                     vsi->vsi_id);
1818         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1819         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1820         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1821         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1822         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1823         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1824                     nes->rx_unknown_protocol);
1825         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1826         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1827         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1828         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1829         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1830         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1831         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1832                     vsi->vsi_id);
1833 }
1834
1835 static void
1836 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1837 {
1838         unsigned int i;
1839         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1840         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1841         /* Get statistics of struct i40e_eth_stats */
1842         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1843                             I40E_GLPRT_GORCL(hw->port),
1844                             pf->offset_loaded, &os->eth.rx_bytes,
1845                             &ns->eth.rx_bytes);
1846         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1847                             I40E_GLPRT_UPRCL(hw->port),
1848                             pf->offset_loaded, &os->eth.rx_unicast,
1849                             &ns->eth.rx_unicast);
1850         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1851                             I40E_GLPRT_MPRCL(hw->port),
1852                             pf->offset_loaded, &os->eth.rx_multicast,
1853                             &ns->eth.rx_multicast);
1854         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1855                             I40E_GLPRT_BPRCL(hw->port),
1856                             pf->offset_loaded, &os->eth.rx_broadcast,
1857                             &ns->eth.rx_broadcast);
1858         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1859                             pf->offset_loaded, &os->eth.rx_discards,
1860                             &ns->eth.rx_discards);
1861         /* GLPRT_REPC not supported */
1862         /* GLPRT_RMPC not supported */
1863         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1864                             pf->offset_loaded,
1865                             &os->eth.rx_unknown_protocol,
1866                             &ns->eth.rx_unknown_protocol);
1867         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1868                             I40E_GLPRT_GOTCL(hw->port),
1869                             pf->offset_loaded, &os->eth.tx_bytes,
1870                             &ns->eth.tx_bytes);
1871         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1872                             I40E_GLPRT_UPTCL(hw->port),
1873                             pf->offset_loaded, &os->eth.tx_unicast,
1874                             &ns->eth.tx_unicast);
1875         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1876                             I40E_GLPRT_MPTCL(hw->port),
1877                             pf->offset_loaded, &os->eth.tx_multicast,
1878                             &ns->eth.tx_multicast);
1879         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1880                             I40E_GLPRT_BPTCL(hw->port),
1881                             pf->offset_loaded, &os->eth.tx_broadcast,
1882                             &ns->eth.tx_broadcast);
1883         /* GLPRT_TEPC not supported */
1884
1885         /* additional port specific stats */
1886         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1887                             pf->offset_loaded, &os->tx_dropped_link_down,
1888                             &ns->tx_dropped_link_down);
1889         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1890                             pf->offset_loaded, &os->crc_errors,
1891                             &ns->crc_errors);
1892         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1893                             pf->offset_loaded, &os->illegal_bytes,
1894                             &ns->illegal_bytes);
1895         /* GLPRT_ERRBC not supported */
1896         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1897                             pf->offset_loaded, &os->mac_local_faults,
1898                             &ns->mac_local_faults);
1899         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1900                             pf->offset_loaded, &os->mac_remote_faults,
1901                             &ns->mac_remote_faults);
1902         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1903                             pf->offset_loaded, &os->rx_length_errors,
1904                             &ns->rx_length_errors);
1905         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1906                             pf->offset_loaded, &os->link_xon_rx,
1907                             &ns->link_xon_rx);
1908         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1909                             pf->offset_loaded, &os->link_xoff_rx,
1910                             &ns->link_xoff_rx);
1911         for (i = 0; i < 8; i++) {
1912                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1913                                     pf->offset_loaded,
1914                                     &os->priority_xon_rx[i],
1915                                     &ns->priority_xon_rx[i]);
1916                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1917                                     pf->offset_loaded,
1918                                     &os->priority_xoff_rx[i],
1919                                     &ns->priority_xoff_rx[i]);
1920         }
1921         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1922                             pf->offset_loaded, &os->link_xon_tx,
1923                             &ns->link_xon_tx);
1924         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1925                             pf->offset_loaded, &os->link_xoff_tx,
1926                             &ns->link_xoff_tx);
1927         for (i = 0; i < 8; i++) {
1928                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1929                                     pf->offset_loaded,
1930                                     &os->priority_xon_tx[i],
1931                                     &ns->priority_xon_tx[i]);
1932                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1933                                     pf->offset_loaded,
1934                                     &os->priority_xoff_tx[i],
1935                                     &ns->priority_xoff_tx[i]);
1936                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1937                                     pf->offset_loaded,
1938                                     &os->priority_xon_2_xoff[i],
1939                                     &ns->priority_xon_2_xoff[i]);
1940         }
1941         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1942                             I40E_GLPRT_PRC64L(hw->port),
1943                             pf->offset_loaded, &os->rx_size_64,
1944                             &ns->rx_size_64);
1945         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1946                             I40E_GLPRT_PRC127L(hw->port),
1947                             pf->offset_loaded, &os->rx_size_127,
1948                             &ns->rx_size_127);
1949         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1950                             I40E_GLPRT_PRC255L(hw->port),
1951                             pf->offset_loaded, &os->rx_size_255,
1952                             &ns->rx_size_255);
1953         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1954                             I40E_GLPRT_PRC511L(hw->port),
1955                             pf->offset_loaded, &os->rx_size_511,
1956                             &ns->rx_size_511);
1957         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1958                             I40E_GLPRT_PRC1023L(hw->port),
1959                             pf->offset_loaded, &os->rx_size_1023,
1960                             &ns->rx_size_1023);
1961         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1962                             I40E_GLPRT_PRC1522L(hw->port),
1963                             pf->offset_loaded, &os->rx_size_1522,
1964                             &ns->rx_size_1522);
1965         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1966                             I40E_GLPRT_PRC9522L(hw->port),
1967                             pf->offset_loaded, &os->rx_size_big,
1968                             &ns->rx_size_big);
1969         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1970                             pf->offset_loaded, &os->rx_undersize,
1971                             &ns->rx_undersize);
1972         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1973                             pf->offset_loaded, &os->rx_fragments,
1974                             &ns->rx_fragments);
1975         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1976                             pf->offset_loaded, &os->rx_oversize,
1977                             &ns->rx_oversize);
1978         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1979                             pf->offset_loaded, &os->rx_jabber,
1980                             &ns->rx_jabber);
1981         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1982                             I40E_GLPRT_PTC64L(hw->port),
1983                             pf->offset_loaded, &os->tx_size_64,
1984                             &ns->tx_size_64);
1985         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1986                             I40E_GLPRT_PTC127L(hw->port),
1987                             pf->offset_loaded, &os->tx_size_127,
1988                             &ns->tx_size_127);
1989         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1990                             I40E_GLPRT_PTC255L(hw->port),
1991                             pf->offset_loaded, &os->tx_size_255,
1992                             &ns->tx_size_255);
1993         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1994                             I40E_GLPRT_PTC511L(hw->port),
1995                             pf->offset_loaded, &os->tx_size_511,
1996                             &ns->tx_size_511);
1997         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1998                             I40E_GLPRT_PTC1023L(hw->port),
1999                             pf->offset_loaded, &os->tx_size_1023,
2000                             &ns->tx_size_1023);
2001         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2002                             I40E_GLPRT_PTC1522L(hw->port),
2003                             pf->offset_loaded, &os->tx_size_1522,
2004                             &ns->tx_size_1522);
2005         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2006                             I40E_GLPRT_PTC9522L(hw->port),
2007                             pf->offset_loaded, &os->tx_size_big,
2008                             &ns->tx_size_big);
2009         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2010                            pf->offset_loaded,
2011                            &os->fd_sb_match, &ns->fd_sb_match);
2012         /* GLPRT_MSPDC not supported */
2013         /* GLPRT_XEC not supported */
2014
2015         pf->offset_loaded = true;
2016
2017         if (pf->main_vsi)
2018                 i40e_update_vsi_stats(pf->main_vsi);
2019 }
2020
2021 /* Get all statistics of a port */
2022 static void
2023 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2024 {
2025         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2026         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2027         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2028         unsigned i;
2029
2030         /* call read registers - updates values, now write them to struct */
2031         i40e_read_stats_registers(pf, hw);
2032
2033         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2034                         pf->main_vsi->eth_stats.rx_multicast +
2035                         pf->main_vsi->eth_stats.rx_broadcast -
2036                         pf->main_vsi->eth_stats.rx_discards;
2037         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2038                         pf->main_vsi->eth_stats.tx_multicast +
2039                         pf->main_vsi->eth_stats.tx_broadcast;
2040         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
2041         stats->obytes   = pf->main_vsi->eth_stats.tx_bytes;
2042         stats->oerrors  = ns->eth.tx_errors +
2043                         pf->main_vsi->eth_stats.tx_errors;
2044         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2045         stats->fdirmatch = ns->fd_sb_match;
2046
2047         /* Rx Errors */
2048         stats->ibadcrc  = ns->crc_errors;
2049         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
2050                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2051         stats->imissed  = ns->eth.rx_discards +
2052                         pf->main_vsi->eth_stats.rx_discards;
2053         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
2054
2055         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2056         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2057         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2058         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2059         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2060         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2061         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2062                     ns->eth.rx_unknown_protocol);
2063         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2064         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2065         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2066         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2067         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2068         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2069
2070         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2071                     ns->tx_dropped_link_down);
2072         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2073         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2074                     ns->illegal_bytes);
2075         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2076         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2077                     ns->mac_local_faults);
2078         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2079                     ns->mac_remote_faults);
2080         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2081                     ns->rx_length_errors);
2082         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2083         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2084         for (i = 0; i < 8; i++) {
2085                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2086                                 i, ns->priority_xon_rx[i]);
2087                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2088                                 i, ns->priority_xoff_rx[i]);
2089         }
2090         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2091         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2092         for (i = 0; i < 8; i++) {
2093                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2094                                 i, ns->priority_xon_tx[i]);
2095                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2096                                 i, ns->priority_xoff_tx[i]);
2097                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2098                                 i, ns->priority_xon_2_xoff[i]);
2099         }
2100         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2101         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2102         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2103         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2104         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2105         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2106         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2107         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2108         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2109         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2110         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2111         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2112         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2113         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2114         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2115         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2116         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2117         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2118         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2119                         ns->mac_short_packet_dropped);
2120         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2121                     ns->checksum_error);
2122         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2123         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2124 }
2125
2126 /* Reset the statistics */
2127 static void
2128 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2129 {
2130         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2131         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2132
2133         /* Mark PF and VSI stats to update the offset, aka "reset" */
2134         pf->offset_loaded = false;
2135         if (pf->main_vsi)
2136                 pf->main_vsi->offset_loaded = false;
2137
2138         /* read the stats, reading current register values into offset */
2139         i40e_read_stats_registers(pf, hw);
2140 }
2141
2142 static int
2143 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2144                     unsigned n)
2145 {
2146         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2147         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148         unsigned i, count = 0;
2149         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2150
2151         if (n < I40E_NB_XSTATS)
2152                 return I40E_NB_XSTATS;
2153
2154         i40e_read_stats_registers(pf, hw);
2155
2156         /* Reset */
2157         if (xstats == NULL)
2158                 return 0;
2159
2160         /* Get stats from i40e_eth_stats struct */
2161         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2162                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2163                          "%s", rte_i40e_stats_strings[i].name);
2164                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2165                         rte_i40e_stats_strings[i].offset);
2166                 count++;
2167         }
2168
2169         /* Get individiual stats from i40e_hw_port struct */
2170         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2171                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2172                          "%s", rte_i40e_hw_port_strings[i].name);
2173                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2174                                 rte_i40e_hw_port_strings[i].offset);
2175                 count++;
2176         }
2177
2178         /* Get per-queue stats from i40e_hw_port struct */
2179         for (i = 0; i < 8; i++) {
2180                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2181                          "rx_q%u_xon_priority_packets", i);
2182                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2183                                 offsetof(struct i40e_hw_port_stats,
2184                                          priority_xon_rx[i]));
2185                 count++;
2186
2187                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2188                          "rx_q%u_xoff_priority_packets", i);
2189                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2190                                 offsetof(struct i40e_hw_port_stats,
2191                                          priority_xoff_rx[i]));
2192                 count++;
2193
2194                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2195                          "tx_q%u_xon_priority_packets", i);
2196                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2197                                 offsetof(struct i40e_hw_port_stats,
2198                                          priority_xon_tx[i]));
2199                 count++;
2200
2201                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2202                          "tx_q%u_xoff_priority_packets", i);
2203                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2204                                 offsetof(struct i40e_hw_port_stats,
2205                                          priority_xoff_tx[i]));
2206                 count++;
2207
2208                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2209                          "xx_q%u_xon_to_xoff_priority_packets", i);
2210                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2211                                 offsetof(struct i40e_hw_port_stats,
2212                                          priority_xon_2_xoff[i]));
2213                 count++;
2214         }
2215
2216         return I40E_NB_XSTATS;
2217 }
2218
2219 static int
2220 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2221                                  __rte_unused uint16_t queue_id,
2222                                  __rte_unused uint8_t stat_idx,
2223                                  __rte_unused uint8_t is_rx)
2224 {
2225         PMD_INIT_FUNC_TRACE();
2226
2227         return -ENOSYS;
2228 }
2229
2230 static void
2231 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2232 {
2233         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2234         struct i40e_vsi *vsi = pf->main_vsi;
2235
2236         dev_info->max_rx_queues = vsi->nb_qps;
2237         dev_info->max_tx_queues = vsi->nb_qps;
2238         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2239         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2240         dev_info->max_mac_addrs = vsi->max_macaddrs;
2241         dev_info->max_vfs = dev->pci_dev->max_vfs;
2242         dev_info->rx_offload_capa =
2243                 DEV_RX_OFFLOAD_VLAN_STRIP |
2244                 DEV_RX_OFFLOAD_QINQ_STRIP |
2245                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2246                 DEV_RX_OFFLOAD_UDP_CKSUM |
2247                 DEV_RX_OFFLOAD_TCP_CKSUM;
2248         dev_info->tx_offload_capa =
2249                 DEV_TX_OFFLOAD_VLAN_INSERT |
2250                 DEV_TX_OFFLOAD_QINQ_INSERT |
2251                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2252                 DEV_TX_OFFLOAD_UDP_CKSUM |
2253                 DEV_TX_OFFLOAD_TCP_CKSUM |
2254                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2255                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2256                 DEV_TX_OFFLOAD_TCP_TSO;
2257         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2258                                                 sizeof(uint32_t);
2259         dev_info->reta_size = pf->hash_lut_size;
2260         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2261
2262         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2263                 .rx_thresh = {
2264                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2265                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2266                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2267                 },
2268                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2269                 .rx_drop_en = 0,
2270         };
2271
2272         dev_info->default_txconf = (struct rte_eth_txconf) {
2273                 .tx_thresh = {
2274                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2275                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2276                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2277                 },
2278                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2279                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2280                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2281                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2282         };
2283
2284         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2285                 .nb_max = I40E_MAX_RING_DESC,
2286                 .nb_min = I40E_MIN_RING_DESC,
2287                 .nb_align = I40E_ALIGN_RING_DESC,
2288         };
2289
2290         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2291                 .nb_max = I40E_MAX_RING_DESC,
2292                 .nb_min = I40E_MIN_RING_DESC,
2293                 .nb_align = I40E_ALIGN_RING_DESC,
2294         };
2295
2296         if (pf->flags & I40E_FLAG_VMDQ) {
2297                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2298                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2299                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2300                                                 pf->max_nb_vmdq_vsi;
2301                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2302                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2303                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2304         }
2305 }
2306
2307 static int
2308 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2309 {
2310         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2311         struct i40e_vsi *vsi = pf->main_vsi;
2312         PMD_INIT_FUNC_TRACE();
2313
2314         if (on)
2315                 return i40e_vsi_add_vlan(vsi, vlan_id);
2316         else
2317                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2318 }
2319
2320 static void
2321 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2322                    __rte_unused uint16_t tpid)
2323 {
2324         PMD_INIT_FUNC_TRACE();
2325 }
2326
2327 static void
2328 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2329 {
2330         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2331         struct i40e_vsi *vsi = pf->main_vsi;
2332
2333         if (mask & ETH_VLAN_STRIP_MASK) {
2334                 /* Enable or disable VLAN stripping */
2335                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2336                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2337                 else
2338                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2339         }
2340
2341         if (mask & ETH_VLAN_EXTEND_MASK) {
2342                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2343                         i40e_vsi_config_double_vlan(vsi, TRUE);
2344                 else
2345                         i40e_vsi_config_double_vlan(vsi, FALSE);
2346         }
2347 }
2348
2349 static void
2350 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2351                           __rte_unused uint16_t queue,
2352                           __rte_unused int on)
2353 {
2354         PMD_INIT_FUNC_TRACE();
2355 }
2356
2357 static int
2358 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2359 {
2360         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2361         struct i40e_vsi *vsi = pf->main_vsi;
2362         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2363         struct i40e_vsi_vlan_pvid_info info;
2364
2365         memset(&info, 0, sizeof(info));
2366         info.on = on;
2367         if (info.on)
2368                 info.config.pvid = pvid;
2369         else {
2370                 info.config.reject.tagged =
2371                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2372                 info.config.reject.untagged =
2373                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2374         }
2375
2376         return i40e_vsi_vlan_pvid_set(vsi, &info);
2377 }
2378
2379 static int
2380 i40e_dev_led_on(struct rte_eth_dev *dev)
2381 {
2382         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2383         uint32_t mode = i40e_led_get(hw);
2384
2385         if (mode == 0)
2386                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2387
2388         return 0;
2389 }
2390
2391 static int
2392 i40e_dev_led_off(struct rte_eth_dev *dev)
2393 {
2394         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2395         uint32_t mode = i40e_led_get(hw);
2396
2397         if (mode != 0)
2398                 i40e_led_set(hw, 0, false);
2399
2400         return 0;
2401 }
2402
2403 static int
2404 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2405 {
2406         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2407         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2408
2409         fc_conf->pause_time = pf->fc_conf.pause_time;
2410         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2411         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2412
2413          /* Return current mode according to actual setting*/
2414         switch (hw->fc.current_mode) {
2415         case I40E_FC_FULL:
2416                 fc_conf->mode = RTE_FC_FULL;
2417                 break;
2418         case I40E_FC_TX_PAUSE:
2419                 fc_conf->mode = RTE_FC_TX_PAUSE;
2420                 break;
2421         case I40E_FC_RX_PAUSE:
2422                 fc_conf->mode = RTE_FC_RX_PAUSE;
2423                 break;
2424         case I40E_FC_NONE:
2425         default:
2426                 fc_conf->mode = RTE_FC_NONE;
2427         };
2428
2429         return 0;
2430 }
2431
2432 static int
2433 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2434 {
2435         uint32_t mflcn_reg, fctrl_reg, reg;
2436         uint32_t max_high_water;
2437         uint8_t i, aq_failure;
2438         int err;
2439         struct i40e_hw *hw;
2440         struct i40e_pf *pf;
2441         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2442                 [RTE_FC_NONE] = I40E_FC_NONE,
2443                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2444                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2445                 [RTE_FC_FULL] = I40E_FC_FULL
2446         };
2447
2448         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2449
2450         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2451         if ((fc_conf->high_water > max_high_water) ||
2452                         (fc_conf->high_water < fc_conf->low_water)) {
2453                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2454                         "High_water must <= %d.", max_high_water);
2455                 return -EINVAL;
2456         }
2457
2458         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2459         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2460         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2461
2462         pf->fc_conf.pause_time = fc_conf->pause_time;
2463         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2464         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2465
2466         PMD_INIT_FUNC_TRACE();
2467
2468         /* All the link flow control related enable/disable register
2469          * configuration is handle by the F/W
2470          */
2471         err = i40e_set_fc(hw, &aq_failure, true);
2472         if (err < 0)
2473                 return -ENOSYS;
2474
2475         if (i40e_is_40G_device(hw->device_id)) {
2476                 /* Configure flow control refresh threshold,
2477                  * the value for stat_tx_pause_refresh_timer[8]
2478                  * is used for global pause operation.
2479                  */
2480
2481                 I40E_WRITE_REG(hw,
2482                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2483                                pf->fc_conf.pause_time);
2484
2485                 /* configure the timer value included in transmitted pause
2486                  * frame,
2487                  * the value for stat_tx_pause_quanta[8] is used for global
2488                  * pause operation
2489                  */
2490                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2491                                pf->fc_conf.pause_time);
2492
2493                 fctrl_reg = I40E_READ_REG(hw,
2494                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2495
2496                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2497                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2498                 else
2499                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2500
2501                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2502                                fctrl_reg);
2503         } else {
2504                 /* Configure pause time (2 TCs per register) */
2505                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2506                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2507                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2508
2509                 /* Configure flow control refresh threshold value */
2510                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2511                                pf->fc_conf.pause_time / 2);
2512
2513                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2514
2515                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2516                  *depending on configuration
2517                  */
2518                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2519                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2520                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2521                 } else {
2522                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2523                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2524                 }
2525
2526                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2527         }
2528
2529         /* config the water marker both based on the packets and bytes */
2530         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2531                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2532                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2533         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2534                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2535                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2536         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2537                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2538                        << I40E_KILOSHIFT);
2539         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2540                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2541                        << I40E_KILOSHIFT);
2542
2543         I40E_WRITE_FLUSH(hw);
2544
2545         return 0;
2546 }
2547
2548 static int
2549 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2550                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2551 {
2552         PMD_INIT_FUNC_TRACE();
2553
2554         return -ENOSYS;
2555 }
2556
2557 /* Add a MAC address, and update filters */
2558 static void
2559 i40e_macaddr_add(struct rte_eth_dev *dev,
2560                  struct ether_addr *mac_addr,
2561                  __rte_unused uint32_t index,
2562                  uint32_t pool)
2563 {
2564         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2565         struct i40e_mac_filter_info mac_filter;
2566         struct i40e_vsi *vsi;
2567         int ret;
2568
2569         /* If VMDQ not enabled or configured, return */
2570         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2571                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2572                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2573                         pool);
2574                 return;
2575         }
2576
2577         if (pool > pf->nb_cfg_vmdq_vsi) {
2578                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2579                                 pool, pf->nb_cfg_vmdq_vsi);
2580                 return;
2581         }
2582
2583         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2584         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2585
2586         if (pool == 0)
2587                 vsi = pf->main_vsi;
2588         else
2589                 vsi = pf->vmdq[pool - 1].vsi;
2590
2591         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2592         if (ret != I40E_SUCCESS) {
2593                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2594                 return;
2595         }
2596 }
2597
2598 /* Remove a MAC address, and update filters */
2599 static void
2600 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2601 {
2602         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2603         struct i40e_vsi *vsi;
2604         struct rte_eth_dev_data *data = dev->data;
2605         struct ether_addr *macaddr;
2606         int ret;
2607         uint32_t i;
2608         uint64_t pool_sel;
2609
2610         macaddr = &(data->mac_addrs[index]);
2611
2612         pool_sel = dev->data->mac_pool_sel[index];
2613
2614         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2615                 if (pool_sel & (1ULL << i)) {
2616                         if (i == 0)
2617                                 vsi = pf->main_vsi;
2618                         else {
2619                                 /* No VMDQ pool enabled or configured */
2620                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2621                                         (i > pf->nb_cfg_vmdq_vsi)) {
2622                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2623                                                         "/configured");
2624                                         return;
2625                                 }
2626                                 vsi = pf->vmdq[i - 1].vsi;
2627                         }
2628                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2629
2630                         if (ret) {
2631                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2632                                 return;
2633                         }
2634                 }
2635         }
2636 }
2637
2638 /* Set perfect match or hash match of MAC and VLAN for a VF */
2639 static int
2640 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2641                  struct rte_eth_mac_filter *filter,
2642                  bool add)
2643 {
2644         struct i40e_hw *hw;
2645         struct i40e_mac_filter_info mac_filter;
2646         struct ether_addr old_mac;
2647         struct ether_addr *new_mac;
2648         struct i40e_pf_vf *vf = NULL;
2649         uint16_t vf_id;
2650         int ret;
2651
2652         if (pf == NULL) {
2653                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2654                 return -EINVAL;
2655         }
2656         hw = I40E_PF_TO_HW(pf);
2657
2658         if (filter == NULL) {
2659                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2660                 return -EINVAL;
2661         }
2662
2663         new_mac = &filter->mac_addr;
2664
2665         if (is_zero_ether_addr(new_mac)) {
2666                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2667                 return -EINVAL;
2668         }
2669
2670         vf_id = filter->dst_id;
2671
2672         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2673                 PMD_DRV_LOG(ERR, "Invalid argument.");
2674                 return -EINVAL;
2675         }
2676         vf = &pf->vfs[vf_id];
2677
2678         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2679                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2680                 return -EINVAL;
2681         }
2682
2683         if (add) {
2684                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2685                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2686                                 ETHER_ADDR_LEN);
2687                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2688                                  ETHER_ADDR_LEN);
2689
2690                 mac_filter.filter_type = filter->filter_type;
2691                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2692                 if (ret != I40E_SUCCESS) {
2693                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2694                         return -1;
2695                 }
2696                 ether_addr_copy(new_mac, &pf->dev_addr);
2697         } else {
2698                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2699                                 ETHER_ADDR_LEN);
2700                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2701                 if (ret != I40E_SUCCESS) {
2702                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2703                         return -1;
2704                 }
2705
2706                 /* Clear device address as it has been removed */
2707                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2708                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2709         }
2710
2711         return 0;
2712 }
2713
2714 /* MAC filter handle */
2715 static int
2716 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2717                 void *arg)
2718 {
2719         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2720         struct rte_eth_mac_filter *filter;
2721         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2722         int ret = I40E_NOT_SUPPORTED;
2723
2724         filter = (struct rte_eth_mac_filter *)(arg);
2725
2726         switch (filter_op) {
2727         case RTE_ETH_FILTER_NOP:
2728                 ret = I40E_SUCCESS;
2729                 break;
2730         case RTE_ETH_FILTER_ADD:
2731                 i40e_pf_disable_irq0(hw);
2732                 if (filter->is_vf)
2733                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2734                 i40e_pf_enable_irq0(hw);
2735                 break;
2736         case RTE_ETH_FILTER_DELETE:
2737                 i40e_pf_disable_irq0(hw);
2738                 if (filter->is_vf)
2739                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2740                 i40e_pf_enable_irq0(hw);
2741                 break;
2742         default:
2743                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2744                 ret = I40E_ERR_PARAM;
2745                 break;
2746         }
2747
2748         return ret;
2749 }
2750
2751 static int
2752 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2753 {
2754         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2755         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2756         int ret;
2757
2758         if (!lut)
2759                 return -EINVAL;
2760
2761         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2762                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2763                                           lut, lut_size);
2764                 if (ret) {
2765                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2766                         return ret;
2767                 }
2768         } else {
2769                 uint32_t *lut_dw = (uint32_t *)lut;
2770                 uint16_t i, lut_size_dw = lut_size / 4;
2771
2772                 for (i = 0; i < lut_size_dw; i++)
2773                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2774         }
2775
2776         return 0;
2777 }
2778
2779 static int
2780 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2781 {
2782         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2783         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2784         int ret;
2785
2786         if (!vsi || !lut)
2787                 return -EINVAL;
2788
2789         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2790                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2791                                           lut, lut_size);
2792                 if (ret) {
2793                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2794                         return ret;
2795                 }
2796         } else {
2797                 uint32_t *lut_dw = (uint32_t *)lut;
2798                 uint16_t i, lut_size_dw = lut_size / 4;
2799
2800                 for (i = 0; i < lut_size_dw; i++)
2801                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2802                 I40E_WRITE_FLUSH(hw);
2803         }
2804
2805         return 0;
2806 }
2807
2808 static int
2809 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2810                          struct rte_eth_rss_reta_entry64 *reta_conf,
2811                          uint16_t reta_size)
2812 {
2813         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2814         uint16_t i, lut_size = pf->hash_lut_size;
2815         uint16_t idx, shift;
2816         uint8_t *lut;
2817         int ret;
2818
2819         if (reta_size != lut_size ||
2820                 reta_size > ETH_RSS_RETA_SIZE_512) {
2821                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2822                         "(%d) doesn't match the number hardware can supported "
2823                                         "(%d)\n", reta_size, lut_size);
2824                 return -EINVAL;
2825         }
2826
2827         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2828         if (!lut) {
2829                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2830                 return -ENOMEM;
2831         }
2832         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2833         if (ret)
2834                 goto out;
2835         for (i = 0; i < reta_size; i++) {
2836                 idx = i / RTE_RETA_GROUP_SIZE;
2837                 shift = i % RTE_RETA_GROUP_SIZE;
2838                 if (reta_conf[idx].mask & (1ULL << shift))
2839                         lut[i] = reta_conf[idx].reta[shift];
2840         }
2841         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2842
2843 out:
2844         rte_free(lut);
2845
2846         return ret;
2847 }
2848
2849 static int
2850 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2851                         struct rte_eth_rss_reta_entry64 *reta_conf,
2852                         uint16_t reta_size)
2853 {
2854         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2855         uint16_t i, lut_size = pf->hash_lut_size;
2856         uint16_t idx, shift;
2857         uint8_t *lut;
2858         int ret;
2859
2860         if (reta_size != lut_size ||
2861                 reta_size > ETH_RSS_RETA_SIZE_512) {
2862                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2863                         "(%d) doesn't match the number hardware can supported "
2864                                         "(%d)\n", reta_size, lut_size);
2865                 return -EINVAL;
2866         }
2867
2868         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2869         if (!lut) {
2870                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2871                 return -ENOMEM;
2872         }
2873
2874         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2875         if (ret)
2876                 goto out;
2877         for (i = 0; i < reta_size; i++) {
2878                 idx = i / RTE_RETA_GROUP_SIZE;
2879                 shift = i % RTE_RETA_GROUP_SIZE;
2880                 if (reta_conf[idx].mask & (1ULL << shift))
2881                         reta_conf[idx].reta[shift] = lut[i];
2882         }
2883
2884 out:
2885         rte_free(lut);
2886
2887         return ret;
2888 }
2889
2890 /**
2891  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2892  * @hw:   pointer to the HW structure
2893  * @mem:  pointer to mem struct to fill out
2894  * @size: size of memory requested
2895  * @alignment: what to align the allocation to
2896  **/
2897 enum i40e_status_code
2898 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2899                         struct i40e_dma_mem *mem,
2900                         u64 size,
2901                         u32 alignment)
2902 {
2903         const struct rte_memzone *mz = NULL;
2904         char z_name[RTE_MEMZONE_NAMESIZE];
2905
2906         if (!mem)
2907                 return I40E_ERR_PARAM;
2908
2909         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
2910 #ifdef RTE_LIBRTE_XEN_DOM0
2911         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2912                                          alignment, RTE_PGSIZE_2M);
2913 #else
2914         mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2915                                          alignment);
2916 #endif
2917         if (!mz)
2918                 return I40E_ERR_NO_MEMORY;
2919
2920         mem->size = size;
2921         mem->va = mz->addr;
2922 #ifdef RTE_LIBRTE_XEN_DOM0
2923         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2924 #else
2925         mem->pa = mz->phys_addr;
2926 #endif
2927         mem->zone = (const void *)mz;
2928         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
2929                     "%"PRIu64, mz->name, mem->pa);
2930
2931         return I40E_SUCCESS;
2932 }
2933
2934 /**
2935  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2936  * @hw:   pointer to the HW structure
2937  * @mem:  ptr to mem struct to free
2938  **/
2939 enum i40e_status_code
2940 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2941                     struct i40e_dma_mem *mem)
2942 {
2943         if (!mem)
2944                 return I40E_ERR_PARAM;
2945
2946         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
2947                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
2948                     mem->pa);
2949         rte_memzone_free((const struct rte_memzone *)mem->zone);
2950         mem->zone = NULL;
2951         mem->va = NULL;
2952         mem->pa = (u64)0;
2953
2954         return I40E_SUCCESS;
2955 }
2956
2957 /**
2958  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2959  * @hw:   pointer to the HW structure
2960  * @mem:  pointer to mem struct to fill out
2961  * @size: size of memory requested
2962  **/
2963 enum i40e_status_code
2964 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2965                          struct i40e_virt_mem *mem,
2966                          u32 size)
2967 {
2968         if (!mem)
2969                 return I40E_ERR_PARAM;
2970
2971         mem->size = size;
2972         mem->va = rte_zmalloc("i40e", size, 0);
2973
2974         if (mem->va)
2975                 return I40E_SUCCESS;
2976         else
2977                 return I40E_ERR_NO_MEMORY;
2978 }
2979
2980 /**
2981  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2982  * @hw:   pointer to the HW structure
2983  * @mem:  pointer to mem struct to free
2984  **/
2985 enum i40e_status_code
2986 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2987                      struct i40e_virt_mem *mem)
2988 {
2989         if (!mem)
2990                 return I40E_ERR_PARAM;
2991
2992         rte_free(mem->va);
2993         mem->va = NULL;
2994
2995         return I40E_SUCCESS;
2996 }
2997
2998 void
2999 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3000 {
3001         rte_spinlock_init(&sp->spinlock);
3002 }
3003
3004 void
3005 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3006 {
3007         rte_spinlock_lock(&sp->spinlock);
3008 }
3009
3010 void
3011 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3012 {
3013         rte_spinlock_unlock(&sp->spinlock);
3014 }
3015
3016 void
3017 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3018 {
3019         return;
3020 }
3021
3022 /**
3023  * Get the hardware capabilities, which will be parsed
3024  * and saved into struct i40e_hw.
3025  */
3026 static int
3027 i40e_get_cap(struct i40e_hw *hw)
3028 {
3029         struct i40e_aqc_list_capabilities_element_resp *buf;
3030         uint16_t len, size = 0;
3031         int ret;
3032
3033         /* Calculate a huge enough buff for saving response data temporarily */
3034         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3035                                                 I40E_MAX_CAP_ELE_NUM;
3036         buf = rte_zmalloc("i40e", len, 0);
3037         if (!buf) {
3038                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3039                 return I40E_ERR_NO_MEMORY;
3040         }
3041
3042         /* Get, parse the capabilities and save it to hw */
3043         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3044                         i40e_aqc_opc_list_func_capabilities, NULL);
3045         if (ret != I40E_SUCCESS)
3046                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3047
3048         /* Free the temporary buffer after being used */
3049         rte_free(buf);
3050
3051         return ret;
3052 }
3053
3054 static int
3055 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3056 {
3057         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3058         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3059         uint16_t qp_count = 0, vsi_count = 0;
3060
3061         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3062                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3063                 return -EINVAL;
3064         }
3065         /* Add the parameter init for LFC */
3066         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3067         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3068         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3069
3070         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3071         pf->max_num_vsi = hw->func_caps.num_vsis;
3072         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3073         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3074         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3075
3076         /* FDir queue/VSI allocation */
3077         pf->fdir_qp_offset = 0;
3078         if (hw->func_caps.fd) {
3079                 pf->flags |= I40E_FLAG_FDIR;
3080                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3081         } else {
3082                 pf->fdir_nb_qps = 0;
3083         }
3084         qp_count += pf->fdir_nb_qps;
3085         vsi_count += 1;
3086
3087         /* LAN queue/VSI allocation */
3088         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3089         if (!hw->func_caps.rss) {
3090                 pf->lan_nb_qps = 1;
3091         } else {
3092                 pf->flags |= I40E_FLAG_RSS;
3093                 if (hw->mac.type == I40E_MAC_X722)
3094                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3095                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3096         }
3097         qp_count += pf->lan_nb_qps;
3098         vsi_count += 1;
3099
3100         /* VF queue/VSI allocation */
3101         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3102         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3103                 pf->flags |= I40E_FLAG_SRIOV;
3104                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3105                 pf->vf_num = dev->pci_dev->max_vfs;
3106                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3107                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3108                             pf->vf_nb_qps * pf->vf_num);
3109         } else {
3110                 pf->vf_nb_qps = 0;
3111                 pf->vf_num = 0;
3112         }
3113         qp_count += pf->vf_nb_qps * pf->vf_num;
3114         vsi_count += pf->vf_num;
3115
3116         /* VMDq queue/VSI allocation */
3117         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3118         pf->vmdq_nb_qps = 0;
3119         pf->max_nb_vmdq_vsi = 0;
3120         if (hw->func_caps.vmdq) {
3121                 if (qp_count < hw->func_caps.num_tx_qp &&
3122                         vsi_count < hw->func_caps.num_vsis) {
3123                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3124                                 qp_count) / pf->vmdq_nb_qp_max;
3125
3126                         /* Limit the maximum number of VMDq vsi to the maximum
3127                          * ethdev can support
3128                          */
3129                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3130                                 hw->func_caps.num_vsis - vsi_count);
3131                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3132                                 ETH_64_POOLS);
3133                         if (pf->max_nb_vmdq_vsi) {
3134                                 pf->flags |= I40E_FLAG_VMDQ;
3135                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3136                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3137                                             "per VMDQ VSI, in total %u queues",
3138                                             pf->max_nb_vmdq_vsi,
3139                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3140                                             pf->max_nb_vmdq_vsi);
3141                         } else {
3142                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3143                                             "VMDq");
3144                         }
3145                 } else {
3146                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3147                 }
3148         }
3149         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3150         vsi_count += pf->max_nb_vmdq_vsi;
3151
3152         if (hw->func_caps.dcb)
3153                 pf->flags |= I40E_FLAG_DCB;
3154
3155         if (qp_count > hw->func_caps.num_tx_qp) {
3156                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3157                             "the hardware maximum %u", qp_count,
3158                             hw->func_caps.num_tx_qp);
3159                 return -EINVAL;
3160         }
3161         if (vsi_count > hw->func_caps.num_vsis) {
3162                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3163                             "the hardware maximum %u", vsi_count,
3164                             hw->func_caps.num_vsis);
3165                 return -EINVAL;
3166         }
3167
3168         return 0;
3169 }
3170
3171 static int
3172 i40e_pf_get_switch_config(struct i40e_pf *pf)
3173 {
3174         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3175         struct i40e_aqc_get_switch_config_resp *switch_config;
3176         struct i40e_aqc_switch_config_element_resp *element;
3177         uint16_t start_seid = 0, num_reported;
3178         int ret;
3179
3180         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3181                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3182         if (!switch_config) {
3183                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3184                 return -ENOMEM;
3185         }
3186
3187         /* Get the switch configurations */
3188         ret = i40e_aq_get_switch_config(hw, switch_config,
3189                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3190         if (ret != I40E_SUCCESS) {
3191                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3192                 goto fail;
3193         }
3194         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3195         if (num_reported != 1) { /* The number should be 1 */
3196                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3197                 goto fail;
3198         }
3199
3200         /* Parse the switch configuration elements */
3201         element = &(switch_config->element[0]);
3202         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3203                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3204                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3205         } else
3206                 PMD_DRV_LOG(INFO, "Unknown element type");
3207
3208 fail:
3209         rte_free(switch_config);
3210
3211         return ret;
3212 }
3213
3214 static int
3215 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3216                         uint32_t num)
3217 {
3218         struct pool_entry *entry;
3219
3220         if (pool == NULL || num == 0)
3221                 return -EINVAL;
3222
3223         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3224         if (entry == NULL) {
3225                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3226                 return -ENOMEM;
3227         }
3228
3229         /* queue heap initialize */
3230         pool->num_free = num;
3231         pool->num_alloc = 0;
3232         pool->base = base;
3233         LIST_INIT(&pool->alloc_list);
3234         LIST_INIT(&pool->free_list);
3235
3236         /* Initialize element  */
3237         entry->base = 0;
3238         entry->len = num;
3239
3240         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3241         return 0;
3242 }
3243
3244 static void
3245 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3246 {
3247         struct pool_entry *entry;
3248
3249         if (pool == NULL)
3250                 return;
3251
3252         LIST_FOREACH(entry, &pool->alloc_list, next) {
3253                 LIST_REMOVE(entry, next);
3254                 rte_free(entry);
3255         }
3256
3257         LIST_FOREACH(entry, &pool->free_list, next) {
3258                 LIST_REMOVE(entry, next);
3259                 rte_free(entry);
3260         }
3261
3262         pool->num_free = 0;
3263         pool->num_alloc = 0;
3264         pool->base = 0;
3265         LIST_INIT(&pool->alloc_list);
3266         LIST_INIT(&pool->free_list);
3267 }
3268
3269 static int
3270 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3271                        uint32_t base)
3272 {
3273         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3274         uint32_t pool_offset;
3275         int insert;
3276
3277         if (pool == NULL) {
3278                 PMD_DRV_LOG(ERR, "Invalid parameter");
3279                 return -EINVAL;
3280         }
3281
3282         pool_offset = base - pool->base;
3283         /* Lookup in alloc list */
3284         LIST_FOREACH(entry, &pool->alloc_list, next) {
3285                 if (entry->base == pool_offset) {
3286                         valid_entry = entry;
3287                         LIST_REMOVE(entry, next);
3288                         break;
3289                 }
3290         }
3291
3292         /* Not find, return */
3293         if (valid_entry == NULL) {
3294                 PMD_DRV_LOG(ERR, "Failed to find entry");
3295                 return -EINVAL;
3296         }
3297
3298         /**
3299          * Found it, move it to free list  and try to merge.
3300          * In order to make merge easier, always sort it by qbase.
3301          * Find adjacent prev and last entries.
3302          */
3303         prev = next = NULL;
3304         LIST_FOREACH(entry, &pool->free_list, next) {
3305                 if (entry->base > valid_entry->base) {
3306                         next = entry;
3307                         break;
3308                 }
3309                 prev = entry;
3310         }
3311
3312         insert = 0;
3313         /* Try to merge with next one*/
3314         if (next != NULL) {
3315                 /* Merge with next one */
3316                 if (valid_entry->base + valid_entry->len == next->base) {
3317                         next->base = valid_entry->base;
3318                         next->len += valid_entry->len;
3319                         rte_free(valid_entry);
3320                         valid_entry = next;
3321                         insert = 1;
3322                 }
3323         }
3324
3325         if (prev != NULL) {
3326                 /* Merge with previous one */
3327                 if (prev->base + prev->len == valid_entry->base) {
3328                         prev->len += valid_entry->len;
3329                         /* If it merge with next one, remove next node */
3330                         if (insert == 1) {
3331                                 LIST_REMOVE(valid_entry, next);
3332                                 rte_free(valid_entry);
3333                         } else {
3334                                 rte_free(valid_entry);
3335                                 insert = 1;
3336                         }
3337                 }
3338         }
3339
3340         /* Not find any entry to merge, insert */
3341         if (insert == 0) {
3342                 if (prev != NULL)
3343                         LIST_INSERT_AFTER(prev, valid_entry, next);
3344                 else if (next != NULL)
3345                         LIST_INSERT_BEFORE(next, valid_entry, next);
3346                 else /* It's empty list, insert to head */
3347                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3348         }
3349
3350         pool->num_free += valid_entry->len;
3351         pool->num_alloc -= valid_entry->len;
3352
3353         return 0;
3354 }
3355
3356 static int
3357 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3358                        uint16_t num)
3359 {
3360         struct pool_entry *entry, *valid_entry;
3361
3362         if (pool == NULL || num == 0) {
3363                 PMD_DRV_LOG(ERR, "Invalid parameter");
3364                 return -EINVAL;
3365         }
3366
3367         if (pool->num_free < num) {
3368                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3369                             num, pool->num_free);
3370                 return -ENOMEM;
3371         }
3372
3373         valid_entry = NULL;
3374         /* Lookup  in free list and find most fit one */
3375         LIST_FOREACH(entry, &pool->free_list, next) {
3376                 if (entry->len >= num) {
3377                         /* Find best one */
3378                         if (entry->len == num) {
3379                                 valid_entry = entry;
3380                                 break;
3381                         }
3382                         if (valid_entry == NULL || valid_entry->len > entry->len)
3383                                 valid_entry = entry;
3384                 }
3385         }
3386
3387         /* Not find one to satisfy the request, return */
3388         if (valid_entry == NULL) {
3389                 PMD_DRV_LOG(ERR, "No valid entry found");
3390                 return -ENOMEM;
3391         }
3392         /**
3393          * The entry have equal queue number as requested,
3394          * remove it from alloc_list.
3395          */
3396         if (valid_entry->len == num) {
3397                 LIST_REMOVE(valid_entry, next);
3398         } else {
3399                 /**
3400                  * The entry have more numbers than requested,
3401                  * create a new entry for alloc_list and minus its
3402                  * queue base and number in free_list.
3403                  */
3404                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3405                 if (entry == NULL) {
3406                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3407                                     "resource pool");
3408                         return -ENOMEM;
3409                 }
3410                 entry->base = valid_entry->base;
3411                 entry->len = num;
3412                 valid_entry->base += num;
3413                 valid_entry->len -= num;
3414                 valid_entry = entry;
3415         }
3416
3417         /* Insert it into alloc list, not sorted */
3418         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3419
3420         pool->num_free -= valid_entry->len;
3421         pool->num_alloc += valid_entry->len;
3422
3423         return (valid_entry->base + pool->base);
3424 }
3425
3426 /**
3427  * bitmap_is_subset - Check whether src2 is subset of src1
3428  **/
3429 static inline int
3430 bitmap_is_subset(uint8_t src1, uint8_t src2)
3431 {
3432         return !((src1 ^ src2) & src2);
3433 }
3434
3435 static enum i40e_status_code
3436 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3437 {
3438         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3439
3440         /* If DCB is not supported, only default TC is supported */
3441         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3442                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3443                 return I40E_NOT_SUPPORTED;
3444         }
3445
3446         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3447                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3448                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3449                             enabled_tcmap);
3450                 return I40E_NOT_SUPPORTED;
3451         }
3452         return I40E_SUCCESS;
3453 }
3454
3455 int
3456 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3457                                 struct i40e_vsi_vlan_pvid_info *info)
3458 {
3459         struct i40e_hw *hw;
3460         struct i40e_vsi_context ctxt;
3461         uint8_t vlan_flags = 0;
3462         int ret;
3463
3464         if (vsi == NULL || info == NULL) {
3465                 PMD_DRV_LOG(ERR, "invalid parameters");
3466                 return I40E_ERR_PARAM;
3467         }
3468
3469         if (info->on) {
3470                 vsi->info.pvid = info->config.pvid;
3471                 /**
3472                  * If insert pvid is enabled, only tagged pkts are
3473                  * allowed to be sent out.
3474                  */
3475                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3476                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3477         } else {
3478                 vsi->info.pvid = 0;
3479                 if (info->config.reject.tagged == 0)
3480                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3481
3482                 if (info->config.reject.untagged == 0)
3483                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3484         }
3485         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3486                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3487         vsi->info.port_vlan_flags |= vlan_flags;
3488         vsi->info.valid_sections =
3489                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3490         memset(&ctxt, 0, sizeof(ctxt));
3491         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3492         ctxt.seid = vsi->seid;
3493
3494         hw = I40E_VSI_TO_HW(vsi);
3495         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3496         if (ret != I40E_SUCCESS)
3497                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3498
3499         return ret;
3500 }
3501
3502 static int
3503 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3504 {
3505         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3506         int i, ret;
3507         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3508
3509         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3510         if (ret != I40E_SUCCESS)
3511                 return ret;
3512
3513         if (!vsi->seid) {
3514                 PMD_DRV_LOG(ERR, "seid not valid");
3515                 return -EINVAL;
3516         }
3517
3518         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3519         tc_bw_data.tc_valid_bits = enabled_tcmap;
3520         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3521                 tc_bw_data.tc_bw_credits[i] =
3522                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3523
3524         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3525         if (ret != I40E_SUCCESS) {
3526                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3527                 return ret;
3528         }
3529
3530         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3531                                         sizeof(vsi->info.qs_handle));
3532         return I40E_SUCCESS;
3533 }
3534
3535 static enum i40e_status_code
3536 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3537                                  struct i40e_aqc_vsi_properties_data *info,
3538                                  uint8_t enabled_tcmap)
3539 {
3540         enum i40e_status_code ret;
3541         int i, total_tc = 0;
3542         uint16_t qpnum_per_tc, bsf, qp_idx;
3543
3544         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3545         if (ret != I40E_SUCCESS)
3546                 return ret;
3547
3548         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3549                 if (enabled_tcmap & (1 << i))
3550                         total_tc++;
3551         vsi->enabled_tc = enabled_tcmap;
3552
3553         /* Number of queues per enabled TC */
3554         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3555         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3556         bsf = rte_bsf32(qpnum_per_tc);
3557
3558         /* Adjust the queue number to actual queues that can be applied */
3559         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3560                 vsi->nb_qps = qpnum_per_tc * total_tc;
3561
3562         /**
3563          * Configure TC and queue mapping parameters, for enabled TC,
3564          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3565          * default queue will serve it.
3566          */
3567         qp_idx = 0;
3568         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3569                 if (vsi->enabled_tc & (1 << i)) {
3570                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3571                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3572                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3573                         qp_idx += qpnum_per_tc;
3574                 } else
3575                         info->tc_mapping[i] = 0;
3576         }
3577
3578         /* Associate queue number with VSI */
3579         if (vsi->type == I40E_VSI_SRIOV) {
3580                 info->mapping_flags |=
3581                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3582                 for (i = 0; i < vsi->nb_qps; i++)
3583                         info->queue_mapping[i] =
3584                                 rte_cpu_to_le_16(vsi->base_queue + i);
3585         } else {
3586                 info->mapping_flags |=
3587                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3588                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3589         }
3590         info->valid_sections |=
3591                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3592
3593         return I40E_SUCCESS;
3594 }
3595
3596 static int
3597 i40e_veb_release(struct i40e_veb *veb)
3598 {
3599         struct i40e_vsi *vsi;
3600         struct i40e_hw *hw;
3601
3602         if (veb == NULL || veb->associate_vsi == NULL)
3603                 return -EINVAL;
3604
3605         if (!TAILQ_EMPTY(&veb->head)) {
3606                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3607                 return -EACCES;
3608         }
3609
3610         vsi = veb->associate_vsi;
3611         hw = I40E_VSI_TO_HW(vsi);
3612
3613         vsi->uplink_seid = veb->uplink_seid;
3614         i40e_aq_delete_element(hw, veb->seid, NULL);
3615         rte_free(veb);
3616         vsi->veb = NULL;
3617         return I40E_SUCCESS;
3618 }
3619
3620 /* Setup a veb */
3621 static struct i40e_veb *
3622 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3623 {
3624         struct i40e_veb *veb;
3625         int ret;
3626         struct i40e_hw *hw;
3627
3628         if (NULL == pf || vsi == NULL) {
3629                 PMD_DRV_LOG(ERR, "veb setup failed, "
3630                             "associated VSI shouldn't null");
3631                 return NULL;
3632         }
3633         hw = I40E_PF_TO_HW(pf);
3634
3635         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3636         if (!veb) {
3637                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3638                 goto fail;
3639         }
3640
3641         veb->associate_vsi = vsi;
3642         TAILQ_INIT(&veb->head);
3643         veb->uplink_seid = vsi->uplink_seid;
3644
3645         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3646                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3647
3648         if (ret != I40E_SUCCESS) {
3649                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3650                             hw->aq.asq_last_status);
3651                 goto fail;
3652         }
3653
3654         /* get statistics index */
3655         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3656                                 &veb->stats_idx, NULL, NULL, NULL);
3657         if (ret != I40E_SUCCESS) {
3658                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3659                             hw->aq.asq_last_status);
3660                 goto fail;
3661         }
3662
3663         /* Get VEB bandwidth, to be implemented */
3664         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3665         vsi->uplink_seid = veb->seid;
3666
3667         return veb;
3668 fail:
3669         rte_free(veb);
3670         return NULL;
3671 }
3672
3673 int
3674 i40e_vsi_release(struct i40e_vsi *vsi)
3675 {
3676         struct i40e_pf *pf;
3677         struct i40e_hw *hw;
3678         struct i40e_vsi_list *vsi_list;
3679         int ret;
3680         struct i40e_mac_filter *f;
3681
3682         if (!vsi)
3683                 return I40E_SUCCESS;
3684
3685         pf = I40E_VSI_TO_PF(vsi);
3686         hw = I40E_VSI_TO_HW(vsi);
3687
3688         /* VSI has child to attach, release child first */
3689         if (vsi->veb) {
3690                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3691                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3692                                 return -1;
3693                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3694                 }
3695                 i40e_veb_release(vsi->veb);
3696         }
3697
3698         /* Remove all macvlan filters of the VSI */
3699         i40e_vsi_remove_all_macvlan_filter(vsi);
3700         TAILQ_FOREACH(f, &vsi->mac_list, next)
3701                 rte_free(f);
3702
3703         if (vsi->type != I40E_VSI_MAIN) {
3704                 /* Remove vsi from parent's sibling list */
3705                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3706                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3707                         return I40E_ERR_PARAM;
3708                 }
3709                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3710                                 &vsi->sib_vsi_list, list);
3711
3712                 /* Remove all switch element of the VSI */
3713                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3714                 if (ret != I40E_SUCCESS)
3715                         PMD_DRV_LOG(ERR, "Failed to delete element");
3716         }
3717         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3718
3719         if (vsi->type != I40E_VSI_SRIOV)
3720                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3721         rte_free(vsi);
3722
3723         return I40E_SUCCESS;
3724 }
3725
3726 static int
3727 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3728 {
3729         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3730         struct i40e_aqc_remove_macvlan_element_data def_filter;
3731         struct i40e_mac_filter_info filter;
3732         int ret;
3733
3734         if (vsi->type != I40E_VSI_MAIN)
3735                 return I40E_ERR_CONFIG;
3736         memset(&def_filter, 0, sizeof(def_filter));
3737         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3738                                         ETH_ADDR_LEN);
3739         def_filter.vlan_tag = 0;
3740         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3741                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3742         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3743         if (ret != I40E_SUCCESS) {
3744                 struct i40e_mac_filter *f;
3745                 struct ether_addr *mac;
3746
3747                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3748                             "macvlan filter");
3749                 /* It needs to add the permanent mac into mac list */
3750                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3751                 if (f == NULL) {
3752                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3753                         return I40E_ERR_NO_MEMORY;
3754                 }
3755                 mac = &f->mac_info.mac_addr;
3756                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3757                                 ETH_ADDR_LEN);
3758                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3759                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3760                 vsi->mac_num++;
3761
3762                 return ret;
3763         }
3764         (void)rte_memcpy(&filter.mac_addr,
3765                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3766         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3767         return i40e_vsi_add_mac(vsi, &filter);
3768 }
3769
3770 static int
3771 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3772 {
3773         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3774         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3775         struct i40e_hw *hw = &vsi->adapter->hw;
3776         i40e_status ret;
3777         int i;
3778
3779         memset(&bw_config, 0, sizeof(bw_config));
3780         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3781         if (ret != I40E_SUCCESS) {
3782                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3783                             hw->aq.asq_last_status);
3784                 return ret;
3785         }
3786
3787         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3788         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3789                                         &ets_sla_config, NULL);
3790         if (ret != I40E_SUCCESS) {
3791                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3792                             "configuration %u", hw->aq.asq_last_status);
3793                 return ret;
3794         }
3795
3796         /* Not store the info yet, just print out */
3797         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3798         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3799         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3800                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3801                             ets_sla_config.share_credits[i]);
3802                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3803                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3804                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3805                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3806                             (i * 4));
3807         }
3808
3809         return 0;
3810 }
3811
3812 /* Setup a VSI */
3813 struct i40e_vsi *
3814 i40e_vsi_setup(struct i40e_pf *pf,
3815                enum i40e_vsi_type type,
3816                struct i40e_vsi *uplink_vsi,
3817                uint16_t user_param)
3818 {
3819         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3820         struct i40e_vsi *vsi;
3821         struct i40e_mac_filter_info filter;
3822         int ret;
3823         struct i40e_vsi_context ctxt;
3824         struct ether_addr broadcast =
3825                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3826
3827         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3828                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3829                             "VSI link shouldn't be NULL");
3830                 return NULL;
3831         }
3832
3833         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3834                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3835                             "uplink VSI should be NULL");
3836                 return NULL;
3837         }
3838
3839         /* If uplink vsi didn't setup VEB, create one first */
3840         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3841                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3842
3843                 if (NULL == uplink_vsi->veb) {
3844                         PMD_DRV_LOG(ERR, "VEB setup failed");
3845                         return NULL;
3846                 }
3847         }
3848
3849         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3850         if (!vsi) {
3851                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3852                 return NULL;
3853         }
3854         TAILQ_INIT(&vsi->mac_list);
3855         vsi->type = type;
3856         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3857         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3858         vsi->parent_vsi = uplink_vsi;
3859         vsi->user_param = user_param;
3860         /* Allocate queues */
3861         switch (vsi->type) {
3862         case I40E_VSI_MAIN  :
3863                 vsi->nb_qps = pf->lan_nb_qps;
3864                 break;
3865         case I40E_VSI_SRIOV :
3866                 vsi->nb_qps = pf->vf_nb_qps;
3867                 break;
3868         case I40E_VSI_VMDQ2:
3869                 vsi->nb_qps = pf->vmdq_nb_qps;
3870                 break;
3871         case I40E_VSI_FDIR:
3872                 vsi->nb_qps = pf->fdir_nb_qps;
3873                 break;
3874         default:
3875                 goto fail_mem;
3876         }
3877         /*
3878          * The filter status descriptor is reported in rx queue 0,
3879          * while the tx queue for fdir filter programming has no
3880          * such constraints, can be non-zero queues.
3881          * To simplify it, choose FDIR vsi use queue 0 pair.
3882          * To make sure it will use queue 0 pair, queue allocation
3883          * need be done before this function is called
3884          */
3885         if (type != I40E_VSI_FDIR) {
3886                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3887                         if (ret < 0) {
3888                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3889                                                 vsi->seid, ret);
3890                                 goto fail_mem;
3891                         }
3892                         vsi->base_queue = ret;
3893         } else
3894                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3895
3896         /* VF has MSIX interrupt in VF range, don't allocate here */
3897         if (type == I40E_VSI_MAIN) {
3898                 ret = i40e_res_pool_alloc(&pf->msix_pool,
3899                                           RTE_MIN(vsi->nb_qps,
3900                                                   RTE_MAX_RXTX_INTR_VEC_ID));
3901                 if (ret < 0) {
3902                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
3903                                     vsi->seid, ret);
3904                         goto fail_queue_alloc;
3905                 }
3906                 vsi->msix_intr = ret;
3907                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
3908         } else if (type != I40E_VSI_SRIOV) {
3909                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3910                 if (ret < 0) {
3911                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3912                         goto fail_queue_alloc;
3913                 }
3914                 vsi->msix_intr = ret;
3915                 vsi->nb_msix = 1;
3916         } else {
3917                 vsi->msix_intr = 0;
3918                 vsi->nb_msix = 0;
3919         }
3920
3921         /* Add VSI */
3922         if (type == I40E_VSI_MAIN) {
3923                 /* For main VSI, no need to add since it's default one */
3924                 vsi->uplink_seid = pf->mac_seid;
3925                 vsi->seid = pf->main_vsi_seid;
3926                 /* Bind queues with specific MSIX interrupt */
3927                 /**
3928                  * Needs 2 interrupt at least, one for misc cause which will
3929                  * enabled from OS side, Another for queues binding the
3930                  * interrupt from device side only.
3931                  */
3932
3933                 /* Get default VSI parameters from hardware */
3934                 memset(&ctxt, 0, sizeof(ctxt));
3935                 ctxt.seid = vsi->seid;
3936                 ctxt.pf_num = hw->pf_id;
3937                 ctxt.uplink_seid = vsi->uplink_seid;
3938                 ctxt.vf_num = 0;
3939                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3940                 if (ret != I40E_SUCCESS) {
3941                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3942                         goto fail_msix_alloc;
3943                 }
3944                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3945                         sizeof(struct i40e_aqc_vsi_properties_data));
3946                 vsi->vsi_id = ctxt.vsi_number;
3947                 vsi->info.valid_sections = 0;
3948
3949                 /* Configure tc, enabled TC0 only */
3950                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3951                         I40E_SUCCESS) {
3952                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3953                         goto fail_msix_alloc;
3954                 }
3955
3956                 /* TC, queue mapping */
3957                 memset(&ctxt, 0, sizeof(ctxt));
3958                 vsi->info.valid_sections |=
3959                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3960                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3961                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3962                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3963                         sizeof(struct i40e_aqc_vsi_properties_data));
3964                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3965                                                 I40E_DEFAULT_TCMAP);
3966                 if (ret != I40E_SUCCESS) {
3967                         PMD_DRV_LOG(ERR, "Failed to configure "
3968                                     "TC queue mapping");
3969                         goto fail_msix_alloc;
3970                 }
3971                 ctxt.seid = vsi->seid;
3972                 ctxt.pf_num = hw->pf_id;
3973                 ctxt.uplink_seid = vsi->uplink_seid;
3974                 ctxt.vf_num = 0;
3975
3976                 /* Update VSI parameters */
3977                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3978                 if (ret != I40E_SUCCESS) {
3979                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3980                         goto fail_msix_alloc;
3981                 }
3982
3983                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3984                                                 sizeof(vsi->info.tc_mapping));
3985                 (void)rte_memcpy(&vsi->info.queue_mapping,
3986                                 &ctxt.info.queue_mapping,
3987                         sizeof(vsi->info.queue_mapping));
3988                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3989                 vsi->info.valid_sections = 0;
3990
3991                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3992                                 ETH_ADDR_LEN);
3993
3994                 /**
3995                  * Updating default filter settings are necessary to prevent
3996                  * reception of tagged packets.
3997                  * Some old firmware configurations load a default macvlan
3998                  * filter which accepts both tagged and untagged packets.
3999                  * The updating is to use a normal filter instead if needed.
4000                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4001                  * The firmware with correct configurations load the default
4002                  * macvlan filter which is expected and cannot be removed.
4003                  */
4004                 i40e_update_default_filter_setting(vsi);
4005                 i40e_config_qinq(hw, vsi);
4006         } else if (type == I40E_VSI_SRIOV) {
4007                 memset(&ctxt, 0, sizeof(ctxt));
4008                 /**
4009                  * For other VSI, the uplink_seid equals to uplink VSI's
4010                  * uplink_seid since they share same VEB
4011                  */
4012                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4013                 ctxt.pf_num = hw->pf_id;
4014                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4015                 ctxt.uplink_seid = vsi->uplink_seid;
4016                 ctxt.connection_type = 0x1;
4017                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4018
4019                 /**
4020                  * Do not configure switch ID to enable VEB switch by
4021                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
4022                  * if the source mac address of packet sent from VF is not
4023                  * listed in the VEB's mac table, the VEB will switch the
4024                  * packet back to the VF. Need to enable it when HW issue
4025                  * is fixed.
4026                  */
4027
4028                 /* Configure port/vlan */
4029                 ctxt.info.valid_sections |=
4030                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4031                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4032                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4033                                                 I40E_DEFAULT_TCMAP);
4034                 if (ret != I40E_SUCCESS) {
4035                         PMD_DRV_LOG(ERR, "Failed to configure "
4036                                     "TC queue mapping");
4037                         goto fail_msix_alloc;
4038                 }
4039                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4040                 ctxt.info.valid_sections |=
4041                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4042                 /**
4043                  * Since VSI is not created yet, only configure parameter,
4044                  * will add vsi below.
4045                  */
4046
4047                 i40e_config_qinq(hw, vsi);
4048         } else if (type == I40E_VSI_VMDQ2) {
4049                 memset(&ctxt, 0, sizeof(ctxt));
4050                 /*
4051                  * For other VSI, the uplink_seid equals to uplink VSI's
4052                  * uplink_seid since they share same VEB
4053                  */
4054                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4055                 ctxt.pf_num = hw->pf_id;
4056                 ctxt.vf_num = 0;
4057                 ctxt.uplink_seid = vsi->uplink_seid;
4058                 ctxt.connection_type = 0x1;
4059                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4060
4061                 ctxt.info.valid_sections |=
4062                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4063                 /* user_param carries flag to enable loop back */
4064                 if (user_param) {
4065                         ctxt.info.switch_id =
4066                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4067                         ctxt.info.switch_id |=
4068                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4069                 }
4070
4071                 /* Configure port/vlan */
4072                 ctxt.info.valid_sections |=
4073                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4074                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4075                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4076                                                 I40E_DEFAULT_TCMAP);
4077                 if (ret != I40E_SUCCESS) {
4078                         PMD_DRV_LOG(ERR, "Failed to configure "
4079                                         "TC queue mapping");
4080                         goto fail_msix_alloc;
4081                 }
4082                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4083                 ctxt.info.valid_sections |=
4084                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4085         } else if (type == I40E_VSI_FDIR) {
4086                 memset(&ctxt, 0, sizeof(ctxt));
4087                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4088                 ctxt.pf_num = hw->pf_id;
4089                 ctxt.vf_num = 0;
4090                 ctxt.uplink_seid = vsi->uplink_seid;
4091                 ctxt.connection_type = 0x1;     /* regular data port */
4092                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4093                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4094                                                 I40E_DEFAULT_TCMAP);
4095                 if (ret != I40E_SUCCESS) {
4096                         PMD_DRV_LOG(ERR, "Failed to configure "
4097                                         "TC queue mapping.");
4098                         goto fail_msix_alloc;
4099                 }
4100                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4101                 ctxt.info.valid_sections |=
4102                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4103         } else {
4104                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4105                 goto fail_msix_alloc;
4106         }
4107
4108         if (vsi->type != I40E_VSI_MAIN) {
4109                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4110                 if (ret != I40E_SUCCESS) {
4111                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4112                                     hw->aq.asq_last_status);
4113                         goto fail_msix_alloc;
4114                 }
4115                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4116                 vsi->info.valid_sections = 0;
4117                 vsi->seid = ctxt.seid;
4118                 vsi->vsi_id = ctxt.vsi_number;
4119                 vsi->sib_vsi_list.vsi = vsi;
4120                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4121                                 &vsi->sib_vsi_list, list);
4122         }
4123
4124         /* MAC/VLAN configuration */
4125         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4126         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4127
4128         ret = i40e_vsi_add_mac(vsi, &filter);
4129         if (ret != I40E_SUCCESS) {
4130                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4131                 goto fail_msix_alloc;
4132         }
4133
4134         /* Get VSI BW information */
4135         i40e_vsi_dump_bw_config(vsi);
4136         return vsi;
4137 fail_msix_alloc:
4138         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4139 fail_queue_alloc:
4140         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4141 fail_mem:
4142         rte_free(vsi);
4143         return NULL;
4144 }
4145
4146 /* Configure vlan stripping on or off */
4147 int
4148 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4149 {
4150         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4151         struct i40e_vsi_context ctxt;
4152         uint8_t vlan_flags;
4153         int ret = I40E_SUCCESS;
4154
4155         /* Check if it has been already on or off */
4156         if (vsi->info.valid_sections &
4157                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4158                 if (on) {
4159                         if ((vsi->info.port_vlan_flags &
4160                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4161                                 return 0; /* already on */
4162                 } else {
4163                         if ((vsi->info.port_vlan_flags &
4164                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4165                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4166                                 return 0; /* already off */
4167                 }
4168         }
4169
4170         if (on)
4171                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4172         else
4173                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4174         vsi->info.valid_sections =
4175                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4176         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4177         vsi->info.port_vlan_flags |= vlan_flags;
4178         ctxt.seid = vsi->seid;
4179         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4180         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4181         if (ret)
4182                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4183                             on ? "enable" : "disable");
4184
4185         return ret;
4186 }
4187
4188 static int
4189 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4190 {
4191         struct rte_eth_dev_data *data = dev->data;
4192         int ret;
4193
4194         /* Apply vlan offload setting */
4195         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
4196
4197         /* Apply double-vlan setting, not implemented yet */
4198
4199         /* Apply pvid setting */
4200         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4201                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4202         if (ret)
4203                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4204
4205         return ret;
4206 }
4207
4208 static int
4209 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4210 {
4211         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4212
4213         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4214 }
4215
4216 static int
4217 i40e_update_flow_control(struct i40e_hw *hw)
4218 {
4219 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4220         struct i40e_link_status link_status;
4221         uint32_t rxfc = 0, txfc = 0, reg;
4222         uint8_t an_info;
4223         int ret;
4224
4225         memset(&link_status, 0, sizeof(link_status));
4226         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4227         if (ret != I40E_SUCCESS) {
4228                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4229                 goto write_reg; /* Disable flow control */
4230         }
4231
4232         an_info = hw->phy.link_info.an_info;
4233         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4234                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4235                 ret = I40E_ERR_NOT_READY;
4236                 goto write_reg; /* Disable flow control */
4237         }
4238         /**
4239          * If link auto negotiation is enabled, flow control needs to
4240          * be configured according to it
4241          */
4242         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4243         case I40E_LINK_PAUSE_RXTX:
4244                 rxfc = 1;
4245                 txfc = 1;
4246                 hw->fc.current_mode = I40E_FC_FULL;
4247                 break;
4248         case I40E_AQ_LINK_PAUSE_RX:
4249                 rxfc = 1;
4250                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4251                 break;
4252         case I40E_AQ_LINK_PAUSE_TX:
4253                 txfc = 1;
4254                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4255                 break;
4256         default:
4257                 hw->fc.current_mode = I40E_FC_NONE;
4258                 break;
4259         }
4260
4261 write_reg:
4262         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4263                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4264         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4265         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4266         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4267         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4268
4269         return ret;
4270 }
4271
4272 /* PF setup */
4273 static int
4274 i40e_pf_setup(struct i40e_pf *pf)
4275 {
4276         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4277         struct i40e_filter_control_settings settings;
4278         struct i40e_vsi *vsi;
4279         int ret;
4280
4281         /* Clear all stats counters */
4282         pf->offset_loaded = FALSE;
4283         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4284         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4285
4286         ret = i40e_pf_get_switch_config(pf);
4287         if (ret != I40E_SUCCESS) {
4288                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4289                 return ret;
4290         }
4291         if (pf->flags & I40E_FLAG_FDIR) {
4292                 /* make queue allocated first, let FDIR use queue pair 0*/
4293                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4294                 if (ret != I40E_FDIR_QUEUE_ID) {
4295                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4296                                     " ret =%d", ret);
4297                         pf->flags &= ~I40E_FLAG_FDIR;
4298                 }
4299         }
4300         /*  main VSI setup */
4301         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4302         if (!vsi) {
4303                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4304                 return I40E_ERR_NOT_READY;
4305         }
4306         pf->main_vsi = vsi;
4307
4308         /* Configure filter control */
4309         memset(&settings, 0, sizeof(settings));
4310         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4311                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4312         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4313                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4314         else {
4315                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4316                                                 hw->func_caps.rss_table_size);
4317                 return I40E_ERR_PARAM;
4318         }
4319         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4320                         "size: %u\n", hw->func_caps.rss_table_size);
4321         pf->hash_lut_size = hw->func_caps.rss_table_size;
4322
4323         /* Enable ethtype and macvlan filters */
4324         settings.enable_ethtype = TRUE;
4325         settings.enable_macvlan = TRUE;
4326         ret = i40e_set_filter_control(hw, &settings);
4327         if (ret)
4328                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4329                                                                 ret);
4330
4331         /* Update flow control according to the auto negotiation */
4332         i40e_update_flow_control(hw);
4333
4334         return I40E_SUCCESS;
4335 }
4336
4337 int
4338 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4339 {
4340         uint32_t reg;
4341         uint16_t j;
4342
4343         /**
4344          * Set or clear TX Queue Disable flags,
4345          * which is required by hardware.
4346          */
4347         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4348         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4349
4350         /* Wait until the request is finished */
4351         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4352                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4353                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4354                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4355                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4356                                                         & 0x1))) {
4357                         break;
4358                 }
4359         }
4360         if (on) {
4361                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4362                         return I40E_SUCCESS; /* already on, skip next steps */
4363
4364                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4365                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4366         } else {
4367                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4368                         return I40E_SUCCESS; /* already off, skip next steps */
4369                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4370         }
4371         /* Write the register */
4372         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4373         /* Check the result */
4374         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4375                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4376                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4377                 if (on) {
4378                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4379                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4380                                 break;
4381                 } else {
4382                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4383                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4384                                 break;
4385                 }
4386         }
4387         /* Check if it is timeout */
4388         if (j >= I40E_CHK_Q_ENA_COUNT) {
4389                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4390                             (on ? "enable" : "disable"), q_idx);
4391                 return I40E_ERR_TIMEOUT;
4392         }
4393
4394         return I40E_SUCCESS;
4395 }
4396
4397 /* Swith on or off the tx queues */
4398 static int
4399 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4400 {
4401         struct rte_eth_dev_data *dev_data = pf->dev_data;
4402         struct i40e_tx_queue *txq;
4403         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4404         uint16_t i;
4405         int ret;
4406
4407         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4408                 txq = dev_data->tx_queues[i];
4409                 /* Don't operate the queue if not configured or
4410                  * if starting only per queue */
4411                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4412                         continue;
4413                 if (on)
4414                         ret = i40e_dev_tx_queue_start(dev, i);
4415                 else
4416                         ret = i40e_dev_tx_queue_stop(dev, i);
4417                 if ( ret != I40E_SUCCESS)
4418                         return ret;
4419         }
4420
4421         return I40E_SUCCESS;
4422 }
4423
4424 int
4425 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4426 {
4427         uint32_t reg;
4428         uint16_t j;
4429
4430         /* Wait until the request is finished */
4431         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4432                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4433                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4434                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4435                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4436                         break;
4437         }
4438
4439         if (on) {
4440                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4441                         return I40E_SUCCESS; /* Already on, skip next steps */
4442                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4443         } else {
4444                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4445                         return I40E_SUCCESS; /* Already off, skip next steps */
4446                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4447         }
4448
4449         /* Write the register */
4450         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4451         /* Check the result */
4452         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4453                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4454                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4455                 if (on) {
4456                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4457                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4458                                 break;
4459                 } else {
4460                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4461                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4462                                 break;
4463                 }
4464         }
4465
4466         /* Check if it is timeout */
4467         if (j >= I40E_CHK_Q_ENA_COUNT) {
4468                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4469                             (on ? "enable" : "disable"), q_idx);
4470                 return I40E_ERR_TIMEOUT;
4471         }
4472
4473         return I40E_SUCCESS;
4474 }
4475 /* Switch on or off the rx queues */
4476 static int
4477 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4478 {
4479         struct rte_eth_dev_data *dev_data = pf->dev_data;
4480         struct i40e_rx_queue *rxq;
4481         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4482         uint16_t i;
4483         int ret;
4484
4485         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4486                 rxq = dev_data->rx_queues[i];
4487                 /* Don't operate the queue if not configured or
4488                  * if starting only per queue */
4489                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4490                         continue;
4491                 if (on)
4492                         ret = i40e_dev_rx_queue_start(dev, i);
4493                 else
4494                         ret = i40e_dev_rx_queue_stop(dev, i);
4495                 if (ret != I40E_SUCCESS)
4496                         return ret;
4497         }
4498
4499         return I40E_SUCCESS;
4500 }
4501
4502 /* Switch on or off all the rx/tx queues */
4503 int
4504 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4505 {
4506         int ret;
4507
4508         if (on) {
4509                 /* enable rx queues before enabling tx queues */
4510                 ret = i40e_dev_switch_rx_queues(pf, on);
4511                 if (ret) {
4512                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4513                         return ret;
4514                 }
4515                 ret = i40e_dev_switch_tx_queues(pf, on);
4516         } else {
4517                 /* Stop tx queues before stopping rx queues */
4518                 ret = i40e_dev_switch_tx_queues(pf, on);
4519                 if (ret) {
4520                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4521                         return ret;
4522                 }
4523                 ret = i40e_dev_switch_rx_queues(pf, on);
4524         }
4525
4526         return ret;
4527 }
4528
4529 /* Initialize VSI for TX */
4530 static int
4531 i40e_dev_tx_init(struct i40e_pf *pf)
4532 {
4533         struct rte_eth_dev_data *data = pf->dev_data;
4534         uint16_t i;
4535         uint32_t ret = I40E_SUCCESS;
4536         struct i40e_tx_queue *txq;
4537
4538         for (i = 0; i < data->nb_tx_queues; i++) {
4539                 txq = data->tx_queues[i];
4540                 if (!txq || !txq->q_set)
4541                         continue;
4542                 ret = i40e_tx_queue_init(txq);
4543                 if (ret != I40E_SUCCESS)
4544                         break;
4545         }
4546         if (ret == I40E_SUCCESS)
4547                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4548                                      ->eth_dev);
4549
4550         return ret;
4551 }
4552
4553 /* Initialize VSI for RX */
4554 static int
4555 i40e_dev_rx_init(struct i40e_pf *pf)
4556 {
4557         struct rte_eth_dev_data *data = pf->dev_data;
4558         int ret = I40E_SUCCESS;
4559         uint16_t i;
4560         struct i40e_rx_queue *rxq;
4561
4562         i40e_pf_config_mq_rx(pf);
4563         for (i = 0; i < data->nb_rx_queues; i++) {
4564                 rxq = data->rx_queues[i];
4565                 if (!rxq || !rxq->q_set)
4566                         continue;
4567
4568                 ret = i40e_rx_queue_init(rxq);
4569                 if (ret != I40E_SUCCESS) {
4570                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4571                                     "initialization");
4572                         break;
4573                 }
4574         }
4575         if (ret == I40E_SUCCESS)
4576                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4577                                      ->eth_dev);
4578
4579         return ret;
4580 }
4581
4582 static int
4583 i40e_dev_rxtx_init(struct i40e_pf *pf)
4584 {
4585         int err;
4586
4587         err = i40e_dev_tx_init(pf);
4588         if (err) {
4589                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4590                 return err;
4591         }
4592         err = i40e_dev_rx_init(pf);
4593         if (err) {
4594                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4595                 return err;
4596         }
4597
4598         return err;
4599 }
4600
4601 static int
4602 i40e_vmdq_setup(struct rte_eth_dev *dev)
4603 {
4604         struct rte_eth_conf *conf = &dev->data->dev_conf;
4605         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4606         int i, err, conf_vsis, j, loop;
4607         struct i40e_vsi *vsi;
4608         struct i40e_vmdq_info *vmdq_info;
4609         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4610         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4611
4612         /*
4613          * Disable interrupt to avoid message from VF. Furthermore, it will
4614          * avoid race condition in VSI creation/destroy.
4615          */
4616         i40e_pf_disable_irq0(hw);
4617
4618         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4619                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4620                 return -ENOTSUP;
4621         }
4622
4623         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4624         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4625                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4626                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4627                         pf->max_nb_vmdq_vsi);
4628                 return -ENOTSUP;
4629         }
4630
4631         if (pf->vmdq != NULL) {
4632                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4633                 return 0;
4634         }
4635
4636         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4637                                 sizeof(*vmdq_info) * conf_vsis, 0);
4638
4639         if (pf->vmdq == NULL) {
4640                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4641                 return -ENOMEM;
4642         }
4643
4644         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4645
4646         /* Create VMDQ VSI */
4647         for (i = 0; i < conf_vsis; i++) {
4648                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4649                                 vmdq_conf->enable_loop_back);
4650                 if (vsi == NULL) {
4651                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4652                         err = -1;
4653                         goto err_vsi_setup;
4654                 }
4655                 vmdq_info = &pf->vmdq[i];
4656                 vmdq_info->pf = pf;
4657                 vmdq_info->vsi = vsi;
4658         }
4659         pf->nb_cfg_vmdq_vsi = conf_vsis;
4660
4661         /* Configure Vlan */
4662         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4663         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4664                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4665                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4666                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4667                                         vmdq_conf->pool_map[i].vlan_id, j);
4668
4669                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4670                                                 vmdq_conf->pool_map[i].vlan_id);
4671                                 if (err) {
4672                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4673                                         err = -1;
4674                                         goto err_vsi_setup;
4675                                 }
4676                         }
4677                 }
4678         }
4679
4680         i40e_pf_enable_irq0(hw);
4681
4682         return 0;
4683
4684 err_vsi_setup:
4685         for (i = 0; i < conf_vsis; i++)
4686                 if (pf->vmdq[i].vsi == NULL)
4687                         break;
4688                 else
4689                         i40e_vsi_release(pf->vmdq[i].vsi);
4690
4691         rte_free(pf->vmdq);
4692         pf->vmdq = NULL;
4693         i40e_pf_enable_irq0(hw);
4694         return err;
4695 }
4696
4697 static void
4698 i40e_stat_update_32(struct i40e_hw *hw,
4699                    uint32_t reg,
4700                    bool offset_loaded,
4701                    uint64_t *offset,
4702                    uint64_t *stat)
4703 {
4704         uint64_t new_data;
4705
4706         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4707         if (!offset_loaded)
4708                 *offset = new_data;
4709
4710         if (new_data >= *offset)
4711                 *stat = (uint64_t)(new_data - *offset);
4712         else
4713                 *stat = (uint64_t)((new_data +
4714                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4715 }
4716
4717 static void
4718 i40e_stat_update_48(struct i40e_hw *hw,
4719                    uint32_t hireg,
4720                    uint32_t loreg,
4721                    bool offset_loaded,
4722                    uint64_t *offset,
4723                    uint64_t *stat)
4724 {
4725         uint64_t new_data;
4726
4727         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4728         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4729                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4730
4731         if (!offset_loaded)
4732                 *offset = new_data;
4733
4734         if (new_data >= *offset)
4735                 *stat = new_data - *offset;
4736         else
4737                 *stat = (uint64_t)((new_data +
4738                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4739
4740         *stat &= I40E_48_BIT_MASK;
4741 }
4742
4743 /* Disable IRQ0 */
4744 void
4745 i40e_pf_disable_irq0(struct i40e_hw *hw)
4746 {
4747         /* Disable all interrupt types */
4748         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4749         I40E_WRITE_FLUSH(hw);
4750 }
4751
4752 /* Enable IRQ0 */
4753 void
4754 i40e_pf_enable_irq0(struct i40e_hw *hw)
4755 {
4756         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4757                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4758                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4759                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4760         I40E_WRITE_FLUSH(hw);
4761 }
4762
4763 static void
4764 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4765 {
4766         /* read pending request and disable first */
4767         i40e_pf_disable_irq0(hw);
4768         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4769         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4770                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4771
4772         if (no_queue)
4773                 /* Link no queues with irq0 */
4774                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4775                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4776 }
4777
4778 static void
4779 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4780 {
4781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4782         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4783         int i;
4784         uint16_t abs_vf_id;
4785         uint32_t index, offset, val;
4786
4787         if (!pf->vfs)
4788                 return;
4789         /**
4790          * Try to find which VF trigger a reset, use absolute VF id to access
4791          * since the reg is global register.
4792          */
4793         for (i = 0; i < pf->vf_num; i++) {
4794                 abs_vf_id = hw->func_caps.vf_base_id + i;
4795                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4796                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4797                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4798                 /* VFR event occured */
4799                 if (val & (0x1 << offset)) {
4800                         int ret;
4801
4802                         /* Clear the event first */
4803                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4804                                                         (0x1 << offset));
4805                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4806                         /**
4807                          * Only notify a VF reset event occured,
4808                          * don't trigger another SW reset
4809                          */
4810                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4811                         if (ret != I40E_SUCCESS)
4812                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4813                 }
4814         }
4815 }
4816
4817 static void
4818 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4819 {
4820         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4821         struct i40e_arq_event_info info;
4822         uint16_t pending, opcode;
4823         int ret;
4824
4825         info.buf_len = I40E_AQ_BUF_SZ;
4826         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4827         if (!info.msg_buf) {
4828                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4829                 return;
4830         }
4831
4832         pending = 1;
4833         while (pending) {
4834                 ret = i40e_clean_arq_element(hw, &info, &pending);
4835
4836                 if (ret != I40E_SUCCESS) {
4837                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4838                                     "aq_err: %u", hw->aq.asq_last_status);
4839                         break;
4840                 }
4841                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4842
4843                 switch (opcode) {
4844                 case i40e_aqc_opc_send_msg_to_pf:
4845                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4846                         i40e_pf_host_handle_vf_msg(dev,
4847                                         rte_le_to_cpu_16(info.desc.retval),
4848                                         rte_le_to_cpu_32(info.desc.cookie_high),
4849                                         rte_le_to_cpu_32(info.desc.cookie_low),
4850                                         info.msg_buf,
4851                                         info.msg_len);
4852                         break;
4853                 default:
4854                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4855                                     opcode);
4856                         break;
4857                 }
4858         }
4859         rte_free(info.msg_buf);
4860 }
4861
4862 /*
4863  * Interrupt handler is registered as the alarm callback for handling LSC
4864  * interrupt in a definite of time, in order to wait the NIC into a stable
4865  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4866  * no need for link down interrupt.
4867  */
4868 static void
4869 i40e_dev_interrupt_delayed_handler(void *param)
4870 {
4871         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4872         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4873         uint32_t icr0;
4874
4875         /* read interrupt causes again */
4876         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4877
4878 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4879         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4880                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4881         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4882                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4883         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4884                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4885         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4886                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4887         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4888                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4889                                                                 "state\n");
4890         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4891                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4892         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4893                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4894 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4895
4896         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4897                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4898                 i40e_dev_handle_vfr_event(dev);
4899         }
4900         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4901                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4902                 i40e_dev_handle_aq_msg(dev);
4903         }
4904
4905         /* handle the link up interrupt in an alarm callback */
4906         i40e_dev_link_update(dev, 0);
4907         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4908
4909         i40e_pf_enable_irq0(hw);
4910         rte_intr_enable(&(dev->pci_dev->intr_handle));
4911 }
4912
4913 /**
4914  * Interrupt handler triggered by NIC  for handling
4915  * specific interrupt.
4916  *
4917  * @param handle
4918  *  Pointer to interrupt handle.
4919  * @param param
4920  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4921  *
4922  * @return
4923  *  void
4924  */
4925 static void
4926 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4927                            void *param)
4928 {
4929         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4930         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4931         uint32_t icr0;
4932
4933         /* Disable interrupt */
4934         i40e_pf_disable_irq0(hw);
4935
4936         /* read out interrupt causes */
4937         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4938
4939         /* No interrupt event indicated */
4940         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4941                 PMD_DRV_LOG(INFO, "No interrupt event");
4942                 goto done;
4943         }
4944 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4945         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4946                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4947         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4948                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4949         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4950                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4951         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4952                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4953         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4954                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4955         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4956                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4957         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4958                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4959 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4960
4961         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4962                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4963                 i40e_dev_handle_vfr_event(dev);
4964         }
4965         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4966                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4967                 i40e_dev_handle_aq_msg(dev);
4968         }
4969
4970         /* Link Status Change interrupt */
4971         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4972 #define I40E_US_PER_SECOND 1000000
4973                 struct rte_eth_link link;
4974
4975                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4976                 memset(&link, 0, sizeof(link));
4977                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4978                 i40e_dev_link_update(dev, 0);
4979
4980                 /*
4981                  * For link up interrupt, it needs to wait 1 second to let the
4982                  * hardware be a stable state. Otherwise several consecutive
4983                  * interrupts can be observed.
4984                  * For link down interrupt, no need to wait.
4985                  */
4986                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4987                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4988                         return;
4989                 else
4990                         _rte_eth_dev_callback_process(dev,
4991                                 RTE_ETH_EVENT_INTR_LSC);
4992         }
4993
4994 done:
4995         /* Enable interrupt */
4996         i40e_pf_enable_irq0(hw);
4997         rte_intr_enable(&(dev->pci_dev->intr_handle));
4998 }
4999
5000 static int
5001 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5002                          struct i40e_macvlan_filter *filter,
5003                          int total)
5004 {
5005         int ele_num, ele_buff_size;
5006         int num, actual_num, i;
5007         uint16_t flags;
5008         int ret = I40E_SUCCESS;
5009         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5010         struct i40e_aqc_add_macvlan_element_data *req_list;
5011
5012         if (filter == NULL  || total == 0)
5013                 return I40E_ERR_PARAM;
5014         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5015         ele_buff_size = hw->aq.asq_buf_size;
5016
5017         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5018         if (req_list == NULL) {
5019                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5020                 return I40E_ERR_NO_MEMORY;
5021         }
5022
5023         num = 0;
5024         do {
5025                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5026                 memset(req_list, 0, ele_buff_size);
5027
5028                 for (i = 0; i < actual_num; i++) {
5029                         (void)rte_memcpy(req_list[i].mac_addr,
5030                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5031                         req_list[i].vlan_tag =
5032                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5033
5034                         switch (filter[num + i].filter_type) {
5035                         case RTE_MAC_PERFECT_MATCH:
5036                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5037                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5038                                 break;
5039                         case RTE_MACVLAN_PERFECT_MATCH:
5040                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5041                                 break;
5042                         case RTE_MAC_HASH_MATCH:
5043                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5044                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5045                                 break;
5046                         case RTE_MACVLAN_HASH_MATCH:
5047                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5048                                 break;
5049                         default:
5050                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5051                                 ret = I40E_ERR_PARAM;
5052                                 goto DONE;
5053                         }
5054
5055                         req_list[i].queue_number = 0;
5056
5057                         req_list[i].flags = rte_cpu_to_le_16(flags);
5058                 }
5059
5060                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5061                                                 actual_num, NULL);
5062                 if (ret != I40E_SUCCESS) {
5063                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5064                         goto DONE;
5065                 }
5066                 num += actual_num;
5067         } while (num < total);
5068
5069 DONE:
5070         rte_free(req_list);
5071         return ret;
5072 }
5073
5074 static int
5075 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5076                             struct i40e_macvlan_filter *filter,
5077                             int total)
5078 {
5079         int ele_num, ele_buff_size;
5080         int num, actual_num, i;
5081         uint16_t flags;
5082         int ret = I40E_SUCCESS;
5083         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5084         struct i40e_aqc_remove_macvlan_element_data *req_list;
5085
5086         if (filter == NULL  || total == 0)
5087                 return I40E_ERR_PARAM;
5088
5089         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5090         ele_buff_size = hw->aq.asq_buf_size;
5091
5092         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5093         if (req_list == NULL) {
5094                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5095                 return I40E_ERR_NO_MEMORY;
5096         }
5097
5098         num = 0;
5099         do {
5100                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5101                 memset(req_list, 0, ele_buff_size);
5102
5103                 for (i = 0; i < actual_num; i++) {
5104                         (void)rte_memcpy(req_list[i].mac_addr,
5105                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5106                         req_list[i].vlan_tag =
5107                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5108
5109                         switch (filter[num + i].filter_type) {
5110                         case RTE_MAC_PERFECT_MATCH:
5111                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5112                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5113                                 break;
5114                         case RTE_MACVLAN_PERFECT_MATCH:
5115                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5116                                 break;
5117                         case RTE_MAC_HASH_MATCH:
5118                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5119                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5120                                 break;
5121                         case RTE_MACVLAN_HASH_MATCH:
5122                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5123                                 break;
5124                         default:
5125                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5126                                 ret = I40E_ERR_PARAM;
5127                                 goto DONE;
5128                         }
5129                         req_list[i].flags = rte_cpu_to_le_16(flags);
5130                 }
5131
5132                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5133                                                 actual_num, NULL);
5134                 if (ret != I40E_SUCCESS) {
5135                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5136                         goto DONE;
5137                 }
5138                 num += actual_num;
5139         } while (num < total);
5140
5141 DONE:
5142         rte_free(req_list);
5143         return ret;
5144 }
5145
5146 /* Find out specific MAC filter */
5147 static struct i40e_mac_filter *
5148 i40e_find_mac_filter(struct i40e_vsi *vsi,
5149                          struct ether_addr *macaddr)
5150 {
5151         struct i40e_mac_filter *f;
5152
5153         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5154                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5155                         return f;
5156         }
5157
5158         return NULL;
5159 }
5160
5161 static bool
5162 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5163                          uint16_t vlan_id)
5164 {
5165         uint32_t vid_idx, vid_bit;
5166
5167         if (vlan_id > ETH_VLAN_ID_MAX)
5168                 return 0;
5169
5170         vid_idx = I40E_VFTA_IDX(vlan_id);
5171         vid_bit = I40E_VFTA_BIT(vlan_id);
5172
5173         if (vsi->vfta[vid_idx] & vid_bit)
5174                 return 1;
5175         else
5176                 return 0;
5177 }
5178
5179 static void
5180 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5181                          uint16_t vlan_id, bool on)
5182 {
5183         uint32_t vid_idx, vid_bit;
5184
5185         if (vlan_id > ETH_VLAN_ID_MAX)
5186                 return;
5187
5188         vid_idx = I40E_VFTA_IDX(vlan_id);
5189         vid_bit = I40E_VFTA_BIT(vlan_id);
5190
5191         if (on)
5192                 vsi->vfta[vid_idx] |= vid_bit;
5193         else
5194                 vsi->vfta[vid_idx] &= ~vid_bit;
5195 }
5196
5197 /**
5198  * Find all vlan options for specific mac addr,
5199  * return with actual vlan found.
5200  */
5201 static inline int
5202 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5203                            struct i40e_macvlan_filter *mv_f,
5204                            int num, struct ether_addr *addr)
5205 {
5206         int i;
5207         uint32_t j, k;
5208
5209         /**
5210          * Not to use i40e_find_vlan_filter to decrease the loop time,
5211          * although the code looks complex.
5212           */
5213         if (num < vsi->vlan_num)
5214                 return I40E_ERR_PARAM;
5215
5216         i = 0;
5217         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5218                 if (vsi->vfta[j]) {
5219                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5220                                 if (vsi->vfta[j] & (1 << k)) {
5221                                         if (i > num - 1) {
5222                                                 PMD_DRV_LOG(ERR, "vlan number "
5223                                                             "not match");
5224                                                 return I40E_ERR_PARAM;
5225                                         }
5226                                         (void)rte_memcpy(&mv_f[i].macaddr,
5227                                                         addr, ETH_ADDR_LEN);
5228                                         mv_f[i].vlan_id =
5229                                                 j * I40E_UINT32_BIT_SIZE + k;
5230                                         i++;
5231                                 }
5232                         }
5233                 }
5234         }
5235         return I40E_SUCCESS;
5236 }
5237
5238 static inline int
5239 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5240                            struct i40e_macvlan_filter *mv_f,
5241                            int num,
5242                            uint16_t vlan)
5243 {
5244         int i = 0;
5245         struct i40e_mac_filter *f;
5246
5247         if (num < vsi->mac_num)
5248                 return I40E_ERR_PARAM;
5249
5250         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5251                 if (i > num - 1) {
5252                         PMD_DRV_LOG(ERR, "buffer number not match");
5253                         return I40E_ERR_PARAM;
5254                 }
5255                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5256                                 ETH_ADDR_LEN);
5257                 mv_f[i].vlan_id = vlan;
5258                 mv_f[i].filter_type = f->mac_info.filter_type;
5259                 i++;
5260         }
5261
5262         return I40E_SUCCESS;
5263 }
5264
5265 static int
5266 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5267 {
5268         int i, num;
5269         struct i40e_mac_filter *f;
5270         struct i40e_macvlan_filter *mv_f;
5271         int ret = I40E_SUCCESS;
5272
5273         if (vsi == NULL || vsi->mac_num == 0)
5274                 return I40E_ERR_PARAM;
5275
5276         /* Case that no vlan is set */
5277         if (vsi->vlan_num == 0)
5278                 num = vsi->mac_num;
5279         else
5280                 num = vsi->mac_num * vsi->vlan_num;
5281
5282         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5283         if (mv_f == NULL) {
5284                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5285                 return I40E_ERR_NO_MEMORY;
5286         }
5287
5288         i = 0;
5289         if (vsi->vlan_num == 0) {
5290                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5291                         (void)rte_memcpy(&mv_f[i].macaddr,
5292                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5293                         mv_f[i].vlan_id = 0;
5294                         i++;
5295                 }
5296         } else {
5297                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5298                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5299                                         vsi->vlan_num, &f->mac_info.mac_addr);
5300                         if (ret != I40E_SUCCESS)
5301                                 goto DONE;
5302                         i += vsi->vlan_num;
5303                 }
5304         }
5305
5306         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5307 DONE:
5308         rte_free(mv_f);
5309
5310         return ret;
5311 }
5312
5313 int
5314 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5315 {
5316         struct i40e_macvlan_filter *mv_f;
5317         int mac_num;
5318         int ret = I40E_SUCCESS;
5319
5320         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5321                 return I40E_ERR_PARAM;
5322
5323         /* If it's already set, just return */
5324         if (i40e_find_vlan_filter(vsi,vlan))
5325                 return I40E_SUCCESS;
5326
5327         mac_num = vsi->mac_num;
5328
5329         if (mac_num == 0) {
5330                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5331                 return I40E_ERR_PARAM;
5332         }
5333
5334         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5335
5336         if (mv_f == NULL) {
5337                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5338                 return I40E_ERR_NO_MEMORY;
5339         }
5340
5341         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5342
5343         if (ret != I40E_SUCCESS)
5344                 goto DONE;
5345
5346         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5347
5348         if (ret != I40E_SUCCESS)
5349                 goto DONE;
5350
5351         i40e_set_vlan_filter(vsi, vlan, 1);
5352
5353         vsi->vlan_num++;
5354         ret = I40E_SUCCESS;
5355 DONE:
5356         rte_free(mv_f);
5357         return ret;
5358 }
5359
5360 int
5361 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5362 {
5363         struct i40e_macvlan_filter *mv_f;
5364         int mac_num;
5365         int ret = I40E_SUCCESS;
5366
5367         /**
5368          * Vlan 0 is the generic filter for untagged packets
5369          * and can't be removed.
5370          */
5371         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5372                 return I40E_ERR_PARAM;
5373
5374         /* If can't find it, just return */
5375         if (!i40e_find_vlan_filter(vsi, vlan))
5376                 return I40E_ERR_PARAM;
5377
5378         mac_num = vsi->mac_num;
5379
5380         if (mac_num == 0) {
5381                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5382                 return I40E_ERR_PARAM;
5383         }
5384
5385         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5386
5387         if (mv_f == NULL) {
5388                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5389                 return I40E_ERR_NO_MEMORY;
5390         }
5391
5392         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5393
5394         if (ret != I40E_SUCCESS)
5395                 goto DONE;
5396
5397         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5398
5399         if (ret != I40E_SUCCESS)
5400                 goto DONE;
5401
5402         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5403         if (vsi->vlan_num == 1) {
5404                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5405                 if (ret != I40E_SUCCESS)
5406                         goto DONE;
5407
5408                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5409                 if (ret != I40E_SUCCESS)
5410                         goto DONE;
5411         }
5412
5413         i40e_set_vlan_filter(vsi, vlan, 0);
5414
5415         vsi->vlan_num--;
5416         ret = I40E_SUCCESS;
5417 DONE:
5418         rte_free(mv_f);
5419         return ret;
5420 }
5421
5422 int
5423 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5424 {
5425         struct i40e_mac_filter *f;
5426         struct i40e_macvlan_filter *mv_f;
5427         int i, vlan_num = 0;
5428         int ret = I40E_SUCCESS;
5429
5430         /* If it's add and we've config it, return */
5431         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5432         if (f != NULL)
5433                 return I40E_SUCCESS;
5434         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5435                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5436
5437                 /**
5438                  * If vlan_num is 0, that's the first time to add mac,
5439                  * set mask for vlan_id 0.
5440                  */
5441                 if (vsi->vlan_num == 0) {
5442                         i40e_set_vlan_filter(vsi, 0, 1);
5443                         vsi->vlan_num = 1;
5444                 }
5445                 vlan_num = vsi->vlan_num;
5446         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5447                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5448                 vlan_num = 1;
5449
5450         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5451         if (mv_f == NULL) {
5452                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5453                 return I40E_ERR_NO_MEMORY;
5454         }
5455
5456         for (i = 0; i < vlan_num; i++) {
5457                 mv_f[i].filter_type = mac_filter->filter_type;
5458                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5459                                 ETH_ADDR_LEN);
5460         }
5461
5462         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5463                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5464                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5465                                         &mac_filter->mac_addr);
5466                 if (ret != I40E_SUCCESS)
5467                         goto DONE;
5468         }
5469
5470         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5471         if (ret != I40E_SUCCESS)
5472                 goto DONE;
5473
5474         /* Add the mac addr into mac list */
5475         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5476         if (f == NULL) {
5477                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5478                 ret = I40E_ERR_NO_MEMORY;
5479                 goto DONE;
5480         }
5481         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5482                         ETH_ADDR_LEN);
5483         f->mac_info.filter_type = mac_filter->filter_type;
5484         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5485         vsi->mac_num++;
5486
5487         ret = I40E_SUCCESS;
5488 DONE:
5489         rte_free(mv_f);
5490
5491         return ret;
5492 }
5493
5494 int
5495 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5496 {
5497         struct i40e_mac_filter *f;
5498         struct i40e_macvlan_filter *mv_f;
5499         int i, vlan_num;
5500         enum rte_mac_filter_type filter_type;
5501         int ret = I40E_SUCCESS;
5502
5503         /* Can't find it, return an error */
5504         f = i40e_find_mac_filter(vsi, addr);
5505         if (f == NULL)
5506                 return I40E_ERR_PARAM;
5507
5508         vlan_num = vsi->vlan_num;
5509         filter_type = f->mac_info.filter_type;
5510         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5511                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5512                 if (vlan_num == 0) {
5513                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5514                         return I40E_ERR_PARAM;
5515                 }
5516         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5517                         filter_type == RTE_MAC_HASH_MATCH)
5518                 vlan_num = 1;
5519
5520         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5521         if (mv_f == NULL) {
5522                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5523                 return I40E_ERR_NO_MEMORY;
5524         }
5525
5526         for (i = 0; i < vlan_num; i++) {
5527                 mv_f[i].filter_type = filter_type;
5528                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5529                                 ETH_ADDR_LEN);
5530         }
5531         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5532                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5533                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5534                 if (ret != I40E_SUCCESS)
5535                         goto DONE;
5536         }
5537
5538         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5539         if (ret != I40E_SUCCESS)
5540                 goto DONE;
5541
5542         /* Remove the mac addr into mac list */
5543         TAILQ_REMOVE(&vsi->mac_list, f, next);
5544         rte_free(f);
5545         vsi->mac_num--;
5546
5547         ret = I40E_SUCCESS;
5548 DONE:
5549         rte_free(mv_f);
5550         return ret;
5551 }
5552
5553 /* Configure hash enable flags for RSS */
5554 uint64_t
5555 i40e_config_hena(uint64_t flags)
5556 {
5557         uint64_t hena = 0;
5558
5559         if (!flags)
5560                 return hena;
5561
5562         if (flags & ETH_RSS_FRAG_IPV4)
5563                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5564         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5565                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5566         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5567                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5568         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5569                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5570         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5571                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5572         if (flags & ETH_RSS_FRAG_IPV6)
5573                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5574         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5575                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5576         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5577                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5578         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5579                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5580         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5581                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5582         if (flags & ETH_RSS_L2_PAYLOAD)
5583                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5584
5585         return hena;
5586 }
5587
5588 /* Parse the hash enable flags */
5589 uint64_t
5590 i40e_parse_hena(uint64_t flags)
5591 {
5592         uint64_t rss_hf = 0;
5593
5594         if (!flags)
5595                 return rss_hf;
5596         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5597                 rss_hf |= ETH_RSS_FRAG_IPV4;
5598         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5599                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5600         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5601                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5602         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5603                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5604         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5605                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5606         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5607                 rss_hf |= ETH_RSS_FRAG_IPV6;
5608         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5609                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5610         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5611                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5612         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5613                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5614         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5615                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5616         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5617                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5618
5619         return rss_hf;
5620 }
5621
5622 /* Disable RSS */
5623 static void
5624 i40e_pf_disable_rss(struct i40e_pf *pf)
5625 {
5626         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5627         uint64_t hena;
5628
5629         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5630         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5631         hena &= ~I40E_RSS_HENA_ALL;
5632         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5633         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5634         I40E_WRITE_FLUSH(hw);
5635 }
5636
5637 static int
5638 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5639 {
5640         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5641         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5642         int ret = 0;
5643
5644         if (!key || key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) *
5645                 sizeof(uint32_t)))
5646                 return -EINVAL;
5647
5648         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5649                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5650                         (struct i40e_aqc_get_set_rss_key_data *)key;
5651
5652                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5653                 if (ret)
5654                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5655                                      "via AQ");
5656         } else {
5657                 uint32_t *hash_key = (uint32_t *)key;
5658                 uint16_t i;
5659
5660                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5661                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5662                 I40E_WRITE_FLUSH(hw);
5663         }
5664
5665         return ret;
5666 }
5667
5668 static int
5669 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5670 {
5671         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5672         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5673         int ret;
5674
5675         if (!key || !key_len)
5676                 return -EINVAL;
5677
5678         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5679                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5680                         (struct i40e_aqc_get_set_rss_key_data *)key);
5681                 if (ret) {
5682                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5683                         return ret;
5684                 }
5685         } else {
5686                 uint32_t *key_dw = (uint32_t *)key;
5687                 uint16_t i;
5688
5689                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5690                         key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5691         }
5692         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5693
5694         return 0;
5695 }
5696
5697 static int
5698 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5699 {
5700         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5701         uint64_t rss_hf;
5702         uint64_t hena;
5703         int ret;
5704
5705         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5706                                rss_conf->rss_key_len);
5707         if (ret)
5708                 return ret;
5709
5710         rss_hf = rss_conf->rss_hf;
5711         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5712         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5713         hena &= ~I40E_RSS_HENA_ALL;
5714         hena |= i40e_config_hena(rss_hf);
5715         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5716         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5717         I40E_WRITE_FLUSH(hw);
5718
5719         return 0;
5720 }
5721
5722 static int
5723 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5724                          struct rte_eth_rss_conf *rss_conf)
5725 {
5726         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5727         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5728         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5729         uint64_t hena;
5730
5731         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5732         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5733         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5734                 if (rss_hf != 0) /* Enable RSS */
5735                         return -EINVAL;
5736                 return 0; /* Nothing to do */
5737         }
5738         /* RSS enabled */
5739         if (rss_hf == 0) /* Disable RSS */
5740                 return -EINVAL;
5741
5742         return i40e_hw_rss_hash_set(pf, rss_conf);
5743 }
5744
5745 static int
5746 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5747                            struct rte_eth_rss_conf *rss_conf)
5748 {
5749         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5750         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5751         uint64_t hena;
5752
5753         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5754                          &rss_conf->rss_key_len);
5755
5756         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5757         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5758         rss_conf->rss_hf = i40e_parse_hena(hena);
5759
5760         return 0;
5761 }
5762
5763 static int
5764 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5765 {
5766         switch (filter_type) {
5767         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5768                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5769                 break;
5770         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5771                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5772                 break;
5773         case RTE_TUNNEL_FILTER_IMAC_TENID:
5774                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5775                 break;
5776         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5777                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5778                 break;
5779         case ETH_TUNNEL_FILTER_IMAC:
5780                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5781                 break;
5782         default:
5783                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5784                 return -EINVAL;
5785         }
5786
5787         return 0;
5788 }
5789
5790 static int
5791 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5792                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5793                         uint8_t add)
5794 {
5795         uint16_t ip_type;
5796         uint8_t tun_type = 0;
5797         int val, ret = 0;
5798         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5799         struct i40e_vsi *vsi = pf->main_vsi;
5800         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5801         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5802
5803         cld_filter = rte_zmalloc("tunnel_filter",
5804                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5805                 0);
5806
5807         if (NULL == cld_filter) {
5808                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5809                 return -EINVAL;
5810         }
5811         pfilter = cld_filter;
5812
5813         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5814                         sizeof(struct ether_addr));
5815         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5816                         sizeof(struct ether_addr));
5817
5818         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5819         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5820                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5821                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5822                                 &tunnel_filter->ip_addr,
5823                                 sizeof(pfilter->ipaddr.v4.data));
5824         } else {
5825                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5826                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5827                                 &tunnel_filter->ip_addr,
5828                                 sizeof(pfilter->ipaddr.v6.data));
5829         }
5830
5831         /* check tunneled type */
5832         switch (tunnel_filter->tunnel_type) {
5833         case RTE_TUNNEL_TYPE_VXLAN:
5834                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5835                 break;
5836         case RTE_TUNNEL_TYPE_NVGRE:
5837                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5838                 break;
5839         default:
5840                 /* Other tunnel types is not supported. */
5841                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5842                 rte_free(cld_filter);
5843                 return -EINVAL;
5844         }
5845
5846         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5847                                                 &pfilter->flags);
5848         if (val < 0) {
5849                 rte_free(cld_filter);
5850                 return -EINVAL;
5851         }
5852
5853         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5854                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5855         pfilter->tenant_id = tunnel_filter->tenant_id;
5856         pfilter->queue_number = tunnel_filter->queue_id;
5857
5858         if (add)
5859                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5860         else
5861                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5862                                                 cld_filter, 1);
5863
5864         rte_free(cld_filter);
5865         return ret;
5866 }
5867
5868 static int
5869 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5870 {
5871         uint8_t i;
5872
5873         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5874                 if (pf->vxlan_ports[i] == port)
5875                         return i;
5876         }
5877
5878         return -1;
5879 }
5880
5881 static int
5882 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5883 {
5884         int  idx, ret;
5885         uint8_t filter_idx;
5886         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5887
5888         idx = i40e_get_vxlan_port_idx(pf, port);
5889
5890         /* Check if port already exists */
5891         if (idx >= 0) {
5892                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5893                 return -EINVAL;
5894         }
5895
5896         /* Now check if there is space to add the new port */
5897         idx = i40e_get_vxlan_port_idx(pf, 0);
5898         if (idx < 0) {
5899                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5900                         "not adding port %d", port);
5901                 return -ENOSPC;
5902         }
5903
5904         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5905                                         &filter_idx, NULL);
5906         if (ret < 0) {
5907                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5908                 return -1;
5909         }
5910
5911         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5912                          port,  filter_idx);
5913
5914         /* New port: add it and mark its index in the bitmap */
5915         pf->vxlan_ports[idx] = port;
5916         pf->vxlan_bitmap |= (1 << idx);
5917
5918         if (!(pf->flags & I40E_FLAG_VXLAN))
5919                 pf->flags |= I40E_FLAG_VXLAN;
5920
5921         return 0;
5922 }
5923
5924 static int
5925 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5926 {
5927         int idx;
5928         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5929
5930         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5931                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5932                 return -EINVAL;
5933         }
5934
5935         idx = i40e_get_vxlan_port_idx(pf, port);
5936
5937         if (idx < 0) {
5938                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5939                 return -EINVAL;
5940         }
5941
5942         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5943                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5944                 return -1;
5945         }
5946
5947         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5948                         port, idx);
5949
5950         pf->vxlan_ports[idx] = 0;
5951         pf->vxlan_bitmap &= ~(1 << idx);
5952
5953         if (!pf->vxlan_bitmap)
5954                 pf->flags &= ~I40E_FLAG_VXLAN;
5955
5956         return 0;
5957 }
5958
5959 /* Add UDP tunneling port */
5960 static int
5961 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5962                         struct rte_eth_udp_tunnel *udp_tunnel)
5963 {
5964         int ret = 0;
5965         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5966
5967         if (udp_tunnel == NULL)
5968                 return -EINVAL;
5969
5970         switch (udp_tunnel->prot_type) {
5971         case RTE_TUNNEL_TYPE_VXLAN:
5972                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5973                 break;
5974
5975         case RTE_TUNNEL_TYPE_GENEVE:
5976         case RTE_TUNNEL_TYPE_TEREDO:
5977                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5978                 ret = -1;
5979                 break;
5980
5981         default:
5982                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5983                 ret = -1;
5984                 break;
5985         }
5986
5987         return ret;
5988 }
5989
5990 /* Remove UDP tunneling port */
5991 static int
5992 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5993                         struct rte_eth_udp_tunnel *udp_tunnel)
5994 {
5995         int ret = 0;
5996         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5997
5998         if (udp_tunnel == NULL)
5999                 return -EINVAL;
6000
6001         switch (udp_tunnel->prot_type) {
6002         case RTE_TUNNEL_TYPE_VXLAN:
6003                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6004                 break;
6005         case RTE_TUNNEL_TYPE_GENEVE:
6006         case RTE_TUNNEL_TYPE_TEREDO:
6007                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6008                 ret = -1;
6009                 break;
6010         default:
6011                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6012                 ret = -1;
6013                 break;
6014         }
6015
6016         return ret;
6017 }
6018
6019 /* Calculate the maximum number of contiguous PF queues that are configured */
6020 static int
6021 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6022 {
6023         struct rte_eth_dev_data *data = pf->dev_data;
6024         int i, num;
6025         struct i40e_rx_queue *rxq;
6026
6027         num = 0;
6028         for (i = 0; i < pf->lan_nb_qps; i++) {
6029                 rxq = data->rx_queues[i];
6030                 if (rxq && rxq->q_set)
6031                         num++;
6032                 else
6033                         break;
6034         }
6035
6036         return num;
6037 }
6038
6039 /* Configure RSS */
6040 static int
6041 i40e_pf_config_rss(struct i40e_pf *pf)
6042 {
6043         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6044         struct rte_eth_rss_conf rss_conf;
6045         uint32_t i, lut = 0;
6046         uint16_t j, num;
6047
6048         /*
6049          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6050          * It's necessary to calulate the actual PF queues that are configured.
6051          */
6052         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6053                 num = i40e_pf_calc_configured_queues_num(pf);
6054         else
6055                 num = pf->dev_data->nb_rx_queues;
6056
6057         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6058         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6059                         num);
6060
6061         if (num == 0) {
6062                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6063                 return -ENOTSUP;
6064         }
6065
6066         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6067                 if (j == num)
6068                         j = 0;
6069                 lut = (lut << 8) | (j & ((0x1 <<
6070                         hw->func_caps.rss_table_entry_width) - 1));
6071                 if ((i & 3) == 3)
6072                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6073         }
6074
6075         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6076         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6077                 i40e_pf_disable_rss(pf);
6078                 return 0;
6079         }
6080         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6081                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6082                 /* Random default keys */
6083                 static uint32_t rss_key_default[] = {0x6b793944,
6084                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6085                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6086                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6087
6088                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6089                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6090                                                         sizeof(uint32_t);
6091         }
6092
6093         return i40e_hw_rss_hash_set(pf, &rss_conf);
6094 }
6095
6096 static int
6097 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6098                                struct rte_eth_tunnel_filter_conf *filter)
6099 {
6100         if (pf == NULL || filter == NULL) {
6101                 PMD_DRV_LOG(ERR, "Invalid parameter");
6102                 return -EINVAL;
6103         }
6104
6105         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6106                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6107                 return -EINVAL;
6108         }
6109
6110         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6111                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6112                 return -EINVAL;
6113         }
6114
6115         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6116                 (is_zero_ether_addr(filter->outer_mac))) {
6117                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6118                 return -EINVAL;
6119         }
6120
6121         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6122                 (is_zero_ether_addr(filter->inner_mac))) {
6123                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6124                 return -EINVAL;
6125         }
6126
6127         return 0;
6128 }
6129
6130 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6131 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6132 static int
6133 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6134 {
6135         uint32_t val, reg;
6136         int ret = -EINVAL;
6137
6138         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6139         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6140
6141         if (len == 3) {
6142                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6143         } else if (len == 4) {
6144                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6145         } else {
6146                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6147                 return ret;
6148         }
6149
6150         if (reg != val) {
6151                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6152                                                    reg, NULL);
6153                 if (ret != 0)
6154                         return ret;
6155         } else {
6156                 ret = 0;
6157         }
6158         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6159                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6160
6161         return ret;
6162 }
6163
6164 static int
6165 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6166 {
6167         int ret = -EINVAL;
6168
6169         if (!hw || !cfg)
6170                 return -EINVAL;
6171
6172         switch (cfg->cfg_type) {
6173         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6174                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6175                 break;
6176         default:
6177                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6178                 break;
6179         }
6180
6181         return ret;
6182 }
6183
6184 static int
6185 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6186                                enum rte_filter_op filter_op,
6187                                void *arg)
6188 {
6189         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6190         int ret = I40E_ERR_PARAM;
6191
6192         switch (filter_op) {
6193         case RTE_ETH_FILTER_SET:
6194                 ret = i40e_dev_global_config_set(hw,
6195                         (struct rte_eth_global_cfg *)arg);
6196                 break;
6197         default:
6198                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6199                 break;
6200         }
6201
6202         return ret;
6203 }
6204
6205 static int
6206 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6207                           enum rte_filter_op filter_op,
6208                           void *arg)
6209 {
6210         struct rte_eth_tunnel_filter_conf *filter;
6211         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6212         int ret = I40E_SUCCESS;
6213
6214         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6215
6216         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6217                 return I40E_ERR_PARAM;
6218
6219         switch (filter_op) {
6220         case RTE_ETH_FILTER_NOP:
6221                 if (!(pf->flags & I40E_FLAG_VXLAN))
6222                         ret = I40E_NOT_SUPPORTED;
6223                 break;
6224         case RTE_ETH_FILTER_ADD:
6225                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6226                 break;
6227         case RTE_ETH_FILTER_DELETE:
6228                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6229                 break;
6230         default:
6231                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6232                 ret = I40E_ERR_PARAM;
6233                 break;
6234         }
6235
6236         return ret;
6237 }
6238
6239 static int
6240 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6241 {
6242         int ret = 0;
6243         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6244
6245         /* RSS setup */
6246         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6247                 ret = i40e_pf_config_rss(pf);
6248         else
6249                 i40e_pf_disable_rss(pf);
6250
6251         return ret;
6252 }
6253
6254 /* Get the symmetric hash enable configurations per port */
6255 static void
6256 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6257 {
6258         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6259
6260         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6261 }
6262
6263 /* Set the symmetric hash enable configurations per port */
6264 static void
6265 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6266 {
6267         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6268
6269         if (enable > 0) {
6270                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6271                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6272                                                         "been enabled");
6273                         return;
6274                 }
6275                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6276         } else {
6277                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6278                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6279                                                         "been disabled");
6280                         return;
6281                 }
6282                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6283         }
6284         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
6285         I40E_WRITE_FLUSH(hw);
6286 }
6287
6288 /*
6289  * Get global configurations of hash function type and symmetric hash enable
6290  * per flow type (pctype). Note that global configuration means it affects all
6291  * the ports on the same NIC.
6292  */
6293 static int
6294 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6295                                    struct rte_eth_hash_global_conf *g_cfg)
6296 {
6297         uint32_t reg, mask = I40E_FLOW_TYPES;
6298         uint16_t i;
6299         enum i40e_filter_pctype pctype;
6300
6301         memset(g_cfg, 0, sizeof(*g_cfg));
6302         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6303         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6304                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6305         else
6306                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6307         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6308                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6309
6310         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6311                 if (!(mask & (1UL << i)))
6312                         continue;
6313                 mask &= ~(1UL << i);
6314                 /* Bit set indicats the coresponding flow type is supported */
6315                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6316                 pctype = i40e_flowtype_to_pctype(i);
6317                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
6318                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6319                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6320         }
6321
6322         return 0;
6323 }
6324
6325 static int
6326 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6327 {
6328         uint32_t i;
6329         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6330
6331         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6332                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6333                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6334                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6335                                                 g_cfg->hash_func);
6336                 return -EINVAL;
6337         }
6338
6339         /*
6340          * As i40e supports less than 32 flow types, only first 32 bits need to
6341          * be checked.
6342          */
6343         mask0 = g_cfg->valid_bit_mask[0];
6344         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6345                 if (i == 0) {
6346                         /* Check if any unsupported flow type configured */
6347                         if ((mask0 | i40e_mask) ^ i40e_mask)
6348                                 goto mask_err;
6349                 } else {
6350                         if (g_cfg->valid_bit_mask[i])
6351                                 goto mask_err;
6352                 }
6353         }
6354
6355         return 0;
6356
6357 mask_err:
6358         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6359
6360         return -EINVAL;
6361 }
6362
6363 /*
6364  * Set global configurations of hash function type and symmetric hash enable
6365  * per flow type (pctype). Note any modifying global configuration will affect
6366  * all the ports on the same NIC.
6367  */
6368 static int
6369 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6370                                    struct rte_eth_hash_global_conf *g_cfg)
6371 {
6372         int ret;
6373         uint16_t i;
6374         uint32_t reg;
6375         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6376         enum i40e_filter_pctype pctype;
6377
6378         /* Check the input parameters */
6379         ret = i40e_hash_global_config_check(g_cfg);
6380         if (ret < 0)
6381                 return ret;
6382
6383         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6384                 if (!(mask0 & (1UL << i)))
6385                         continue;
6386                 mask0 &= ~(1UL << i);
6387                 pctype = i40e_flowtype_to_pctype(i);
6388                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6389                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6390                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
6391         }
6392
6393         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6394         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6395                 /* Toeplitz */
6396                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6397                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6398                                                                 "Toeplitz");
6399                         goto out;
6400                 }
6401                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6402         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6403                 /* Simple XOR */
6404                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6405                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6406                                                         "Simple XOR");
6407                         goto out;
6408                 }
6409                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6410         } else
6411                 /* Use the default, and keep it as it is */
6412                 goto out;
6413
6414         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6415
6416 out:
6417         I40E_WRITE_FLUSH(hw);
6418
6419         return 0;
6420 }
6421
6422 /**
6423  * Valid input sets for hash and flow director filters per PCTYPE
6424  */
6425 static uint64_t
6426 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6427                 enum rte_filter_type filter)
6428 {
6429         uint64_t valid;
6430
6431         static const uint64_t valid_hash_inset_table[] = {
6432                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6433                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6434                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6435                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6436                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6437                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6438                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6439                         I40E_INSET_FLEX_PAYLOAD,
6440                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6441                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6442                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6443                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6444                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6445                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6446                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6447                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6448                         I40E_INSET_FLEX_PAYLOAD,
6449                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6450                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6451                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6452                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6453                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6454                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6455                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6456                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6457                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6458                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6459                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6460                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6461                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6462                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6463                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6464                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6465                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6466                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6467                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6468                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6469                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6470                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6471                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6472                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6473                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6474                         I40E_INSET_FLEX_PAYLOAD,
6475                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6476                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6477                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6478                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6479                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6480                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6481                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6482                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6483                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6484                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6485                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6486                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6487                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6488                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6489                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6490                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6491                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6492                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6493                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6494                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6495                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6496                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6497                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6498                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6499                         I40E_INSET_FLEX_PAYLOAD,
6500                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6501                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6502                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6503                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6504                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6505                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6506                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6507                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6508                         I40E_INSET_FLEX_PAYLOAD,
6509                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6510                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6511                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6512                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6513                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6514                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6515                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6516                         I40E_INSET_FLEX_PAYLOAD,
6517                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6518                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6519                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6520                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6521                         I40E_INSET_FLEX_PAYLOAD,
6522         };
6523
6524         /**
6525          * Flow director supports only fields defined in
6526          * union rte_eth_fdir_flow.
6527          */
6528         static const uint64_t valid_fdir_inset_table[] = {
6529                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6530                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6531                 I40E_INSET_FLEX_PAYLOAD,
6532                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6533                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6534                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6535                 I40E_INSET_FLEX_PAYLOAD,
6536                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6537                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6538                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6539                 I40E_INSET_FLEX_PAYLOAD,
6540                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6541                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6542                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6543                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6544                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6545                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6546                 I40E_INSET_FLEX_PAYLOAD,
6547                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6548                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6549                 I40E_INSET_FLEX_PAYLOAD,
6550                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6551                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6552                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6553                 I40E_INSET_FLEX_PAYLOAD,
6554                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6555                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6556                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6557                 I40E_INSET_FLEX_PAYLOAD,
6558                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6559                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6560                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6561                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6562                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6563                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6564                 I40E_INSET_FLEX_PAYLOAD,
6565                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6566                 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6567         };
6568
6569         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6570                 return 0;
6571         if (filter == RTE_ETH_FILTER_HASH)
6572                 valid = valid_hash_inset_table[pctype];
6573         else
6574                 valid = valid_fdir_inset_table[pctype];
6575
6576         return valid;
6577 }
6578
6579 /**
6580  * Validate if the input set is allowed for a specific PCTYPE
6581  */
6582 static int
6583 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6584                 enum rte_filter_type filter, uint64_t inset)
6585 {
6586         uint64_t valid;
6587
6588         valid = i40e_get_valid_input_set(pctype, filter);
6589         if (inset & (~valid))
6590                 return -EINVAL;
6591
6592         return 0;
6593 }
6594
6595 /* default input set fields combination per pctype */
6596 static uint64_t
6597 i40e_get_default_input_set(uint16_t pctype)
6598 {
6599         static const uint64_t default_inset_table[] = {
6600                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6601                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6602                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6603                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6604                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6605                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6606                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6607                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6608                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6609                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6610                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6611                         I40E_INSET_SCTP_VT,
6612                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6613                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6614                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6615                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6616                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6617                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6618                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6619                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6620                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6621                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6622                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6623                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6624                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6625                         I40E_INSET_SCTP_VT,
6626                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6627                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6628                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6629                         I40E_INSET_LAST_ETHER_TYPE,
6630         };
6631
6632         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6633                 return 0;
6634
6635         return default_inset_table[pctype];
6636 }
6637
6638 /**
6639  * Parse the input set from index to logical bit masks
6640  */
6641 static int
6642 i40e_parse_input_set(uint64_t *inset,
6643                      enum i40e_filter_pctype pctype,
6644                      enum rte_eth_input_set_field *field,
6645                      uint16_t size)
6646 {
6647         uint16_t i, j;
6648         int ret = -EINVAL;
6649
6650         static const struct {
6651                 enum rte_eth_input_set_field field;
6652                 uint64_t inset;
6653         } inset_convert_table[] = {
6654                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6655                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6656                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6657                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6658                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6659                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6660                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6661                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6662                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6663                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6664                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6665                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6666                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6667                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6668                         I40E_INSET_IPV6_NEXT_HDR},
6669                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6670                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6671                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6672                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6673                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6674                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6675                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6676                         I40E_INSET_SCTP_VT},
6677                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6678                         I40E_INSET_TUNNEL_DMAC},
6679                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6680                         I40E_INSET_VLAN_TUNNEL},
6681                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6682                         I40E_INSET_TUNNEL_ID},
6683                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6684                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6685                         I40E_INSET_FLEX_PAYLOAD_W1},
6686                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6687                         I40E_INSET_FLEX_PAYLOAD_W2},
6688                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6689                         I40E_INSET_FLEX_PAYLOAD_W3},
6690                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6691                         I40E_INSET_FLEX_PAYLOAD_W4},
6692                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6693                         I40E_INSET_FLEX_PAYLOAD_W5},
6694                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6695                         I40E_INSET_FLEX_PAYLOAD_W6},
6696                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6697                         I40E_INSET_FLEX_PAYLOAD_W7},
6698                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6699                         I40E_INSET_FLEX_PAYLOAD_W8},
6700         };
6701
6702         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6703                 return ret;
6704
6705         /* Only one item allowed for default or all */
6706         if (size == 1) {
6707                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6708                         *inset = i40e_get_default_input_set(pctype);
6709                         return 0;
6710                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6711                         *inset = I40E_INSET_NONE;
6712                         return 0;
6713                 }
6714         }
6715
6716         for (i = 0, *inset = 0; i < size; i++) {
6717                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6718                         if (field[i] == inset_convert_table[j].field) {
6719                                 *inset |= inset_convert_table[j].inset;
6720                                 break;
6721                         }
6722                 }
6723
6724                 /* It contains unsupported input set, return immediately */
6725                 if (j == RTE_DIM(inset_convert_table))
6726                         return ret;
6727         }
6728
6729         return 0;
6730 }
6731
6732 /**
6733  * Translate the input set from bit masks to register aware bit masks
6734  * and vice versa
6735  */
6736 static uint64_t
6737 i40e_translate_input_set_reg(uint64_t input)
6738 {
6739         uint64_t val = 0;
6740         uint16_t i;
6741
6742         static const struct {
6743                 uint64_t inset;
6744                 uint64_t inset_reg;
6745         } inset_map[] = {
6746                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6747                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6748                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6749                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6750                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6751                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6752                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6753                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6754                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6755                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6756                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6757                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6758                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6759                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6760                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6761                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6762                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6763                 {I40E_INSET_TUNNEL_DMAC,
6764                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6765                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6766                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6767                 {I40E_INSET_TUNNEL_SRC_PORT,
6768                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6769                 {I40E_INSET_TUNNEL_DST_PORT,
6770                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6771                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6772                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6773                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6774                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6775                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6776                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6777                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6778                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6779                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6780         };
6781
6782         if (input == 0)
6783                 return val;
6784
6785         /* Translate input set to register aware inset */
6786         for (i = 0; i < RTE_DIM(inset_map); i++) {
6787                 if (input & inset_map[i].inset)
6788                         val |= inset_map[i].inset_reg;
6789         }
6790
6791         return val;
6792 }
6793
6794 static uint8_t
6795 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6796 {
6797         uint8_t i, idx = 0;
6798
6799         static const struct {
6800                 uint64_t inset;
6801                 uint32_t mask;
6802         } inset_mask_map[] = {
6803                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6804                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6805                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6806                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6807         };
6808
6809         if (!inset || !mask || !nb_elem)
6810                 return 0;
6811
6812         if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6813                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6814                         mask[i] = 0;
6815                 return I40E_INSET_MASK_NUM_REG;
6816         }
6817
6818         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6819                 if (idx >= nb_elem)
6820                         break;
6821                 if (inset & inset_mask_map[i].inset) {
6822                         mask[idx] = inset_mask_map[i].mask;
6823                         idx++;
6824                 }
6825         }
6826
6827         return idx;
6828 }
6829
6830 static uint64_t
6831 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
6832                             enum i40e_filter_pctype pctype)
6833 {
6834         uint64_t reg = 0;
6835
6836         if (filter == RTE_ETH_FILTER_HASH) {
6837                 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
6838                 reg <<= I40E_32_BIT_WIDTH;
6839                 reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
6840         } else if (filter == RTE_ETH_FILTER_FDIR) {
6841                 reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
6842                 reg <<= I40E_32_BIT_WIDTH;
6843                 reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
6844         }
6845
6846         return reg;
6847 }
6848
6849 static void
6850 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
6851 {
6852         uint32_t reg = I40E_READ_REG(hw, addr);
6853
6854         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
6855         if (reg != val)
6856                 I40E_WRITE_REG(hw, addr, val);
6857         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
6858                     (uint32_t)I40E_READ_REG(hw, addr));
6859 }
6860
6861 static int
6862 i40e_set_hash_inset_mask(struct i40e_hw *hw,
6863                          enum i40e_filter_pctype pctype,
6864                          enum rte_filter_input_set_op op,
6865                          uint32_t *mask_reg,
6866                          uint8_t num)
6867 {
6868         uint32_t reg;
6869         uint8_t i;
6870
6871         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6872                 return -EINVAL;
6873
6874         if (op == RTE_ETH_INPUT_SET_SELECT) {
6875                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6876                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6877                                              0);
6878                         if (i >= num)
6879                                 continue;
6880                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6881                                              mask_reg[i]);
6882                 }
6883         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6884                 uint8_t j, count = 0;
6885
6886                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6887                         reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
6888                         if (reg & I40E_GLQF_HASH_MSK_FIELD)
6889                                 count++;
6890                 }
6891                 if (count + num > I40E_INSET_MASK_NUM_REG)
6892                         return -EINVAL;
6893
6894                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6895                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6896                                              mask_reg[j]);
6897         }
6898
6899         return 0;
6900 }
6901
6902 static int
6903 i40e_set_fd_inset_mask(struct i40e_hw *hw,
6904                        enum i40e_filter_pctype pctype,
6905                        enum rte_filter_input_set_op op,
6906                        uint32_t *mask_reg,
6907                        uint8_t num)
6908 {
6909         uint32_t reg;
6910         uint8_t i;
6911
6912         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6913                 return -EINVAL;
6914
6915         if (op == RTE_ETH_INPUT_SET_SELECT) {
6916                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6917                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6918                                              0);
6919                         if (i >= num)
6920                                 continue;
6921                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6922                                              mask_reg[i]);
6923                 }
6924         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6925                 uint8_t j, count = 0;
6926
6927                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6928                         reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
6929                         if (reg & I40E_GLQF_FD_MSK_FIELD)
6930                                 count++;
6931                 }
6932                 if (count + num > I40E_INSET_MASK_NUM_REG)
6933                         return -EINVAL;
6934
6935                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6936                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6937                                              mask_reg[j]);
6938         }
6939
6940         return 0;
6941 }
6942
6943 int
6944 i40e_filter_inset_select(struct i40e_hw *hw,
6945                          struct rte_eth_input_set_conf *conf,
6946                          enum rte_filter_type filter)
6947 {
6948         enum i40e_filter_pctype pctype;
6949         uint64_t inset_reg = 0, input_set;
6950         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
6951         uint8_t num;
6952         int ret;
6953
6954         if (!hw || !conf) {
6955                 PMD_DRV_LOG(ERR, "Invalid pointer");
6956                 return -EFAULT;
6957         }
6958
6959         pctype = i40e_flowtype_to_pctype(conf->flow_type);
6960         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
6961                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
6962                             conf->flow_type);
6963                 return -EINVAL;
6964         }
6965         if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
6966                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6967                 return -EINVAL;
6968         }
6969
6970         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
6971                                    conf->inset_size);
6972         if (ret) {
6973                 PMD_DRV_LOG(ERR, "Failed to parse input set");
6974                 return -EINVAL;
6975         }
6976         if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
6977                 PMD_DRV_LOG(ERR, "Invalid input set");
6978                 return -EINVAL;
6979         }
6980
6981         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
6982                 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
6983         } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
6984                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
6985                 return -EINVAL;
6986         }
6987         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
6988                                            I40E_INSET_MASK_NUM_REG);
6989         inset_reg |= i40e_translate_input_set_reg(input_set);
6990
6991         if (filter == RTE_ETH_FILTER_HASH) {
6992                 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
6993                                                num);
6994                 if (ret)
6995                         return -EINVAL;
6996
6997                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
6998                                       (uint32_t)(inset_reg & UINT32_MAX));
6999                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7000                                      (uint32_t)((inset_reg >>
7001                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7002         } else if (filter == RTE_ETH_FILTER_FDIR) {
7003                 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
7004                                              num);
7005                 if (ret)
7006                         return -EINVAL;
7007
7008                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7009                                       (uint32_t)(inset_reg & UINT32_MAX));
7010                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7011                                      (uint32_t)((inset_reg >>
7012                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7013         } else {
7014                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7015                 return -EINVAL;
7016         }
7017         I40E_WRITE_FLUSH(hw);
7018
7019         return 0;
7020 }
7021
7022 static int
7023 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7024 {
7025         int ret = 0;
7026
7027         if (!hw || !info) {
7028                 PMD_DRV_LOG(ERR, "Invalid pointer");
7029                 return -EFAULT;
7030         }
7031
7032         switch (info->info_type) {
7033         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7034                 i40e_get_symmetric_hash_enable_per_port(hw,
7035                                         &(info->info.enable));
7036                 break;
7037         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7038                 ret = i40e_get_hash_filter_global_config(hw,
7039                                 &(info->info.global_conf));
7040                 break;
7041         default:
7042                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7043                                                         info->info_type);
7044                 ret = -EINVAL;
7045                 break;
7046         }
7047
7048         return ret;
7049 }
7050
7051 static int
7052 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7053 {
7054         int ret = 0;
7055
7056         if (!hw || !info) {
7057                 PMD_DRV_LOG(ERR, "Invalid pointer");
7058                 return -EFAULT;
7059         }
7060
7061         switch (info->info_type) {
7062         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7063                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7064                 break;
7065         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7066                 ret = i40e_set_hash_filter_global_config(hw,
7067                                 &(info->info.global_conf));
7068                 break;
7069         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7070                 ret = i40e_filter_inset_select(hw,
7071                                                &(info->info.input_set_conf),
7072                                                RTE_ETH_FILTER_HASH);
7073                 break;
7074
7075         default:
7076                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7077                                                         info->info_type);
7078                 ret = -EINVAL;
7079                 break;
7080         }
7081
7082         return ret;
7083 }
7084
7085 /* Operations for hash function */
7086 static int
7087 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7088                       enum rte_filter_op filter_op,
7089                       void *arg)
7090 {
7091         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7092         int ret = 0;
7093
7094         switch (filter_op) {
7095         case RTE_ETH_FILTER_NOP:
7096                 break;
7097         case RTE_ETH_FILTER_GET:
7098                 ret = i40e_hash_filter_get(hw,
7099                         (struct rte_eth_hash_filter_info *)arg);
7100                 break;
7101         case RTE_ETH_FILTER_SET:
7102                 ret = i40e_hash_filter_set(hw,
7103                         (struct rte_eth_hash_filter_info *)arg);
7104                 break;
7105         default:
7106                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7107                                                                 filter_op);
7108                 ret = -ENOTSUP;
7109                 break;
7110         }
7111
7112         return ret;
7113 }
7114
7115 /*
7116  * Configure ethertype filter, which can director packet by filtering
7117  * with mac address and ether_type or only ether_type
7118  */
7119 static int
7120 i40e_ethertype_filter_set(struct i40e_pf *pf,
7121                         struct rte_eth_ethertype_filter *filter,
7122                         bool add)
7123 {
7124         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7125         struct i40e_control_filter_stats stats;
7126         uint16_t flags = 0;
7127         int ret;
7128
7129         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7130                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7131                 return -EINVAL;
7132         }
7133         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7134                 filter->ether_type == ETHER_TYPE_IPv6) {
7135                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7136                         " control packet filter.", filter->ether_type);
7137                 return -EINVAL;
7138         }
7139         if (filter->ether_type == ETHER_TYPE_VLAN)
7140                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7141                         " not supported.");
7142
7143         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7144                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7145         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7146                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7147         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7148
7149         memset(&stats, 0, sizeof(stats));
7150         ret = i40e_aq_add_rem_control_packet_filter(hw,
7151                         filter->mac_addr.addr_bytes,
7152                         filter->ether_type, flags,
7153                         pf->main_vsi->seid,
7154                         filter->queue, add, &stats, NULL);
7155
7156         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7157                          " mac_etype_used = %u, etype_used = %u,"
7158                          " mac_etype_free = %u, etype_free = %u\n",
7159                          ret, stats.mac_etype_used, stats.etype_used,
7160                          stats.mac_etype_free, stats.etype_free);
7161         if (ret < 0)
7162                 return -ENOSYS;
7163         return 0;
7164 }
7165
7166 /*
7167  * Handle operations for ethertype filter.
7168  */
7169 static int
7170 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7171                                 enum rte_filter_op filter_op,
7172                                 void *arg)
7173 {
7174         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7175         int ret = 0;
7176
7177         if (filter_op == RTE_ETH_FILTER_NOP)
7178                 return ret;
7179
7180         if (arg == NULL) {
7181                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7182                             filter_op);
7183                 return -EINVAL;
7184         }
7185
7186         switch (filter_op) {
7187         case RTE_ETH_FILTER_ADD:
7188                 ret = i40e_ethertype_filter_set(pf,
7189                         (struct rte_eth_ethertype_filter *)arg,
7190                         TRUE);
7191                 break;
7192         case RTE_ETH_FILTER_DELETE:
7193                 ret = i40e_ethertype_filter_set(pf,
7194                         (struct rte_eth_ethertype_filter *)arg,
7195                         FALSE);
7196                 break;
7197         default:
7198                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7199                 ret = -ENOSYS;
7200                 break;
7201         }
7202         return ret;
7203 }
7204
7205 static int
7206 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7207                      enum rte_filter_type filter_type,
7208                      enum rte_filter_op filter_op,
7209                      void *arg)
7210 {
7211         int ret = 0;
7212
7213         if (dev == NULL)
7214                 return -EINVAL;
7215
7216         switch (filter_type) {
7217         case RTE_ETH_FILTER_NONE:
7218                 /* For global configuration */
7219                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7220                 break;
7221         case RTE_ETH_FILTER_HASH:
7222                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7223                 break;
7224         case RTE_ETH_FILTER_MACVLAN:
7225                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7226                 break;
7227         case RTE_ETH_FILTER_ETHERTYPE:
7228                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7229                 break;
7230         case RTE_ETH_FILTER_TUNNEL:
7231                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7232                 break;
7233         case RTE_ETH_FILTER_FDIR:
7234                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7235                 break;
7236         default:
7237                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7238                                                         filter_type);
7239                 ret = -EINVAL;
7240                 break;
7241         }
7242
7243         return ret;
7244 }
7245
7246 /*
7247  * As some registers wouldn't be reset unless a global hardware reset,
7248  * hardware initialization is needed to put those registers into an
7249  * expected initial state.
7250  */
7251 static void
7252 i40e_hw_init(struct i40e_hw *hw)
7253 {
7254         /* clear the PF Queue Filter control register */
7255         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
7256
7257         /* Disable symmetric hash per port */
7258         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7259 }
7260
7261 enum i40e_filter_pctype
7262 i40e_flowtype_to_pctype(uint16_t flow_type)
7263 {
7264         static const enum i40e_filter_pctype pctype_table[] = {
7265                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7266                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7267                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7268                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7269                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7270                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7271                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7272                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7273                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7274                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7275                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7276                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7277                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7278                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7279                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7280                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7281                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7282                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7283                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7284         };
7285
7286         return pctype_table[flow_type];
7287 }
7288
7289 uint16_t
7290 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7291 {
7292         static const uint16_t flowtype_table[] = {
7293                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7294                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7295                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7296                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7297                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7298                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7299                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7300                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7301                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7302                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7303                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7304                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7305                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7306                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7307                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7308                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7309                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7310                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7311                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7312         };
7313
7314         return flowtype_table[pctype];
7315 }
7316
7317 /*
7318  * On X710, performance number is far from the expectation on recent firmware
7319  * versions; on XL710, performance number is also far from the expectation on
7320  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7321  * mode is enabled and port MAC address is equal to the packet destination MAC
7322  * address. The fix for this issue may not be integrated in the following
7323  * firmware version. So the workaround in software driver is needed. It needs
7324  * to modify the initial values of 3 internal only registers for both X710 and
7325  * XL710. Note that the values for X710 or XL710 could be different, and the
7326  * workaround can be removed when it is fixed in firmware in the future.
7327  */
7328
7329 /* For both X710 and XL710 */
7330 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7331 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7332
7333 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7334 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7335
7336 /* For X710 */
7337 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7338 /* For XL710 */
7339 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7340 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7341
7342 static void
7343 i40e_configure_registers(struct i40e_hw *hw)
7344 {
7345         static struct {
7346                 uint32_t addr;
7347                 uint64_t val;
7348         } reg_table[] = {
7349                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7350                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7351                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7352         };
7353         uint64_t reg;
7354         uint32_t i;
7355         int ret;
7356
7357         for (i = 0; i < RTE_DIM(reg_table); i++) {
7358                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7359                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7360                                 reg_table[i].val =
7361                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7362                         else /* For X710 */
7363                                 reg_table[i].val =
7364                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7365                 }
7366
7367                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7368                                                         &reg, NULL);
7369                 if (ret < 0) {
7370                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7371                                                         reg_table[i].addr);
7372                         break;
7373                 }
7374                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7375                                                 reg_table[i].addr, reg);
7376                 if (reg == reg_table[i].val)
7377                         continue;
7378
7379                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7380                                                 reg_table[i].val, NULL);
7381                 if (ret < 0) {
7382                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7383                                 "address of 0x%"PRIx32, reg_table[i].val,
7384                                                         reg_table[i].addr);
7385                         break;
7386                 }
7387                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7388                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7389         }
7390 }
7391
7392 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7393 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7394 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7395 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7396 static int
7397 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7398 {
7399         uint32_t reg;
7400         int ret;
7401
7402         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7403                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7404                 return -EINVAL;
7405         }
7406
7407         /* Configure for double VLAN RX stripping */
7408         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7409         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7410                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7411                 ret = i40e_aq_debug_write_register(hw,
7412                                                    I40E_VSI_TSR(vsi->vsi_id),
7413                                                    reg, NULL);
7414                 if (ret < 0) {
7415                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7416                                     vsi->vsi_id);
7417                         return I40E_ERR_CONFIG;
7418                 }
7419         }
7420
7421         /* Configure for double VLAN TX insertion */
7422         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7423         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7424                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7425                 ret = i40e_aq_debug_write_register(hw,
7426                                                    I40E_VSI_L2TAGSTXVALID(
7427                                                    vsi->vsi_id), reg, NULL);
7428                 if (ret < 0) {
7429                         PMD_DRV_LOG(ERR, "Failed to update "
7430                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7431                         return I40E_ERR_CONFIG;
7432                 }
7433         }
7434
7435         return 0;
7436 }
7437
7438 /**
7439  * i40e_aq_add_mirror_rule
7440  * @hw: pointer to the hardware structure
7441  * @seid: VEB seid to add mirror rule to
7442  * @dst_id: destination vsi seid
7443  * @entries: Buffer which contains the entities to be mirrored
7444  * @count: number of entities contained in the buffer
7445  * @rule_id:the rule_id of the rule to be added
7446  *
7447  * Add a mirror rule for a given veb.
7448  *
7449  **/
7450 static enum i40e_status_code
7451 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7452                         uint16_t seid, uint16_t dst_id,
7453                         uint16_t rule_type, uint16_t *entries,
7454                         uint16_t count, uint16_t *rule_id)
7455 {
7456         struct i40e_aq_desc desc;
7457         struct i40e_aqc_add_delete_mirror_rule cmd;
7458         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7459                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7460                 &desc.params.raw;
7461         uint16_t buff_len;
7462         enum i40e_status_code status;
7463
7464         i40e_fill_default_direct_cmd_desc(&desc,
7465                                           i40e_aqc_opc_add_mirror_rule);
7466         memset(&cmd, 0, sizeof(cmd));
7467
7468         buff_len = sizeof(uint16_t) * count;
7469         desc.datalen = rte_cpu_to_le_16(buff_len);
7470         if (buff_len > 0)
7471                 desc.flags |= rte_cpu_to_le_16(
7472                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7473         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7474                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7475         cmd.num_entries = rte_cpu_to_le_16(count);
7476         cmd.seid = rte_cpu_to_le_16(seid);
7477         cmd.destination = rte_cpu_to_le_16(dst_id);
7478
7479         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7480         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7481         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7482                          "rule_id = %u"
7483                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7484                          hw->aq.asq_last_status, resp->rule_id,
7485                          resp->mirror_rules_used, resp->mirror_rules_free);
7486         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7487
7488         return status;
7489 }
7490
7491 /**
7492  * i40e_aq_del_mirror_rule
7493  * @hw: pointer to the hardware structure
7494  * @seid: VEB seid to add mirror rule to
7495  * @entries: Buffer which contains the entities to be mirrored
7496  * @count: number of entities contained in the buffer
7497  * @rule_id:the rule_id of the rule to be delete
7498  *
7499  * Delete a mirror rule for a given veb.
7500  *
7501  **/
7502 static enum i40e_status_code
7503 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7504                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7505                 uint16_t count, uint16_t rule_id)
7506 {
7507         struct i40e_aq_desc desc;
7508         struct i40e_aqc_add_delete_mirror_rule cmd;
7509         uint16_t buff_len = 0;
7510         enum i40e_status_code status;
7511         void *buff = NULL;
7512
7513         i40e_fill_default_direct_cmd_desc(&desc,
7514                                           i40e_aqc_opc_delete_mirror_rule);
7515         memset(&cmd, 0, sizeof(cmd));
7516         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7517                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7518                                                           I40E_AQ_FLAG_RD));
7519                 cmd.num_entries = count;
7520                 buff_len = sizeof(uint16_t) * count;
7521                 desc.datalen = rte_cpu_to_le_16(buff_len);
7522                 buff = (void *)entries;
7523         } else
7524                 /* rule id is filled in destination field for deleting mirror rule */
7525                 cmd.destination = rte_cpu_to_le_16(rule_id);
7526
7527         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7528                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7529         cmd.seid = rte_cpu_to_le_16(seid);
7530
7531         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7532         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7533
7534         return status;
7535 }
7536
7537 /**
7538  * i40e_mirror_rule_set
7539  * @dev: pointer to the hardware structure
7540  * @mirror_conf: mirror rule info
7541  * @sw_id: mirror rule's sw_id
7542  * @on: enable/disable
7543  *
7544  * set a mirror rule.
7545  *
7546  **/
7547 static int
7548 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7549                         struct rte_eth_mirror_conf *mirror_conf,
7550                         uint8_t sw_id, uint8_t on)
7551 {
7552         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7553         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7554         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7555         struct i40e_mirror_rule *parent = NULL;
7556         uint16_t seid, dst_seid, rule_id;
7557         uint16_t i, j = 0;
7558         int ret;
7559
7560         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7561
7562         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7563                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7564                         " without veb or vfs.");
7565                 return -ENOSYS;
7566         }
7567         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7568                 PMD_DRV_LOG(ERR, "mirror table is full.");
7569                 return -ENOSPC;
7570         }
7571         if (mirror_conf->dst_pool > pf->vf_num) {
7572                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7573                                  mirror_conf->dst_pool);
7574                 return -EINVAL;
7575         }
7576
7577         seid = pf->main_vsi->veb->seid;
7578
7579         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7580                 if (sw_id <= it->index) {
7581                         mirr_rule = it;
7582                         break;
7583                 }
7584                 parent = it;
7585         }
7586         if (mirr_rule && sw_id == mirr_rule->index) {
7587                 if (on) {
7588                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7589                         return -EEXIST;
7590                 } else {
7591                         ret = i40e_aq_del_mirror_rule(hw, seid,
7592                                         mirr_rule->rule_type,
7593                                         mirr_rule->entries,
7594                                         mirr_rule->num_entries, mirr_rule->id);
7595                         if (ret < 0) {
7596                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7597                                                    " ret = %d, aq_err = %d.",
7598                                                    ret, hw->aq.asq_last_status);
7599                                 return -ENOSYS;
7600                         }
7601                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7602                         rte_free(mirr_rule);
7603                         pf->nb_mirror_rule--;
7604                         return 0;
7605                 }
7606         } else if (!on) {
7607                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7608                 return -ENOENT;
7609         }
7610
7611         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7612                                 sizeof(struct i40e_mirror_rule) , 0);
7613         if (!mirr_rule) {
7614                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7615                 return I40E_ERR_NO_MEMORY;
7616         }
7617         switch (mirror_conf->rule_type) {
7618         case ETH_MIRROR_VLAN:
7619                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7620                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7621                                 mirr_rule->entries[j] =
7622                                         mirror_conf->vlan.vlan_id[i];
7623                                 j++;
7624                         }
7625                 }
7626                 if (j == 0) {
7627                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7628                         rte_free(mirr_rule);
7629                         return -EINVAL;
7630                 }
7631                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7632                 break;
7633         case ETH_MIRROR_VIRTUAL_POOL_UP:
7634         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7635                 /* check if the specified pool bit is out of range */
7636                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7637                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7638                         rte_free(mirr_rule);
7639                         return -EINVAL;
7640                 }
7641                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7642                         if (mirror_conf->pool_mask & (1ULL << i)) {
7643                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7644                                 j++;
7645                         }
7646                 }
7647                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7648                         /* add pf vsi to entries */
7649                         mirr_rule->entries[j] = pf->main_vsi_seid;
7650                         j++;
7651                 }
7652                 if (j == 0) {
7653                         PMD_DRV_LOG(ERR, "pool is not specified.");
7654                         rte_free(mirr_rule);
7655                         return -EINVAL;
7656                 }
7657                 /* egress and ingress in aq commands means from switch but not port */
7658                 mirr_rule->rule_type =
7659                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7660                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7661                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7662                 break;
7663         case ETH_MIRROR_UPLINK_PORT:
7664                 /* egress and ingress in aq commands means from switch but not port*/
7665                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7666                 break;
7667         case ETH_MIRROR_DOWNLINK_PORT:
7668                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7669                 break;
7670         default:
7671                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7672                         mirror_conf->rule_type);
7673                 rte_free(mirr_rule);
7674                 return -EINVAL;
7675         }
7676
7677         /* If the dst_pool is equal to vf_num, consider it as PF */
7678         if (mirror_conf->dst_pool == pf->vf_num)
7679                 dst_seid = pf->main_vsi_seid;
7680         else
7681                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7682
7683         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7684                                       mirr_rule->rule_type, mirr_rule->entries,
7685                                       j, &rule_id);
7686         if (ret < 0) {
7687                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7688                                    " ret = %d, aq_err = %d.",
7689                                    ret, hw->aq.asq_last_status);
7690                 rte_free(mirr_rule);
7691                 return -ENOSYS;
7692         }
7693
7694         mirr_rule->index = sw_id;
7695         mirr_rule->num_entries = j;
7696         mirr_rule->id = rule_id;
7697         mirr_rule->dst_vsi_seid = dst_seid;
7698
7699         if (parent)
7700                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7701         else
7702                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7703
7704         pf->nb_mirror_rule++;
7705         return 0;
7706 }
7707
7708 /**
7709  * i40e_mirror_rule_reset
7710  * @dev: pointer to the device
7711  * @sw_id: mirror rule's sw_id
7712  *
7713  * reset a mirror rule.
7714  *
7715  **/
7716 static int
7717 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7718 {
7719         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7720         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7721         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7722         uint16_t seid;
7723         int ret;
7724
7725         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7726
7727         seid = pf->main_vsi->veb->seid;
7728
7729         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7730                 if (sw_id == it->index) {
7731                         mirr_rule = it;
7732                         break;
7733                 }
7734         }
7735         if (mirr_rule) {
7736                 ret = i40e_aq_del_mirror_rule(hw, seid,
7737                                 mirr_rule->rule_type,
7738                                 mirr_rule->entries,
7739                                 mirr_rule->num_entries, mirr_rule->id);
7740                 if (ret < 0) {
7741                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7742                                            " status = %d, aq_err = %d.",
7743                                            ret, hw->aq.asq_last_status);
7744                         return -ENOSYS;
7745                 }
7746                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7747                 rte_free(mirr_rule);
7748                 pf->nb_mirror_rule--;
7749         } else {
7750                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7751                 return -ENOENT;
7752         }
7753         return 0;
7754 }
7755
7756 static int
7757 i40e_timesync_enable(struct rte_eth_dev *dev)
7758 {
7759         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7760         struct rte_eth_link *link = &dev->data->dev_link;
7761         uint32_t tsync_ctl_l;
7762         uint32_t tsync_ctl_h;
7763         uint32_t tsync_inc_l;
7764         uint32_t tsync_inc_h;
7765
7766         switch (link->link_speed) {
7767         case ETH_LINK_SPEED_40G:
7768                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
7769                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
7770                 break;
7771         case ETH_LINK_SPEED_10G:
7772                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
7773                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
7774                 break;
7775         case ETH_LINK_SPEED_1000:
7776                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
7777                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
7778                 break;
7779         default:
7780                 tsync_inc_l = 0x0;
7781                 tsync_inc_h = 0x0;
7782         }
7783
7784         /* Clear timesync registers. */
7785         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7786         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7787         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
7788         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
7789         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
7790         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
7791         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7792
7793         /* Set the timesync increment value. */
7794         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
7795         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
7796
7797         /* Enable timestamping of PTP packets. */
7798         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7799         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
7800
7801         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7802         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
7803         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
7804
7805         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7806         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7807
7808         return 0;
7809 }
7810
7811 static int
7812 i40e_timesync_disable(struct rte_eth_dev *dev)
7813 {
7814         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7815         uint32_t tsync_ctl_l;
7816         uint32_t tsync_ctl_h;
7817
7818         /* Disable timestamping of transmitted PTP packets. */
7819         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7820         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
7821
7822         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7823         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
7824
7825         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7826         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7827
7828         /* Set the timesync increment value. */
7829         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7830         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7831
7832         return 0;
7833 }
7834
7835 static int
7836 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7837                                 struct timespec *timestamp, uint32_t flags)
7838 {
7839         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7840         uint32_t sync_status;
7841         uint32_t rx_stmpl;
7842         uint32_t rx_stmph;
7843         uint32_t index = flags & 0x03;
7844
7845         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
7846         if ((sync_status & (1 << index)) == 0)
7847                 return -EINVAL;
7848
7849         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7850         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
7851
7852         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
7853         timestamp->tv_nsec = 0;
7854
7855         return  0;
7856 }
7857
7858 static int
7859 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7860                                 struct timespec *timestamp)
7861 {
7862         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7863         uint32_t sync_status;
7864         uint32_t tx_stmpl;
7865         uint32_t tx_stmph;
7866
7867         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7868         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
7869                 return -EINVAL;
7870
7871         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
7872         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7873
7874         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
7875         timestamp->tv_nsec = 0;
7876
7877         return  0;
7878 }
7879
7880 /*
7881  * i40e_parse_dcb_configure - parse dcb configure from user
7882  * @dev: the device being configured
7883  * @dcb_cfg: pointer of the result of parse
7884  * @*tc_map: bit map of enabled traffic classes
7885  *
7886  * Returns 0 on success, negative value on failure
7887  */
7888 static int
7889 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
7890                          struct i40e_dcbx_config *dcb_cfg,
7891                          uint8_t *tc_map)
7892 {
7893         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
7894         uint8_t i, tc_bw, bw_lf;
7895
7896         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
7897
7898         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7899         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
7900                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
7901                 return -EINVAL;
7902         }
7903
7904         /* assume each tc has the same bw */
7905         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
7906         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7907                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
7908         /* to ensure the sum of tcbw is equal to 100 */
7909         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
7910         for (i = 0; i < bw_lf; i++)
7911                 dcb_cfg->etscfg.tcbwtable[i]++;
7912
7913         /* assume each tc has the same Transmission Selection Algorithm */
7914         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7915                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
7916
7917         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
7918                 dcb_cfg->etscfg.prioritytable[i] =
7919                                 dcb_rx_conf->dcb_tc[i];
7920
7921         /* FW needs one App to configure HW */
7922         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
7923         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
7924         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
7925         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
7926
7927         if (dcb_rx_conf->nb_tcs == 0)
7928                 *tc_map = 1; /* tc0 only */
7929         else
7930                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
7931
7932         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
7933                 dcb_cfg->pfc.willing = 0;
7934                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
7935                 dcb_cfg->pfc.pfcenable = *tc_map;
7936         }
7937         return 0;
7938 }
7939
7940 /*
7941  * i40e_vsi_get_bw_info - Query VSI BW Information
7942  * @vsi: the VSI being queried
7943  *
7944  * Returns 0 on success, negative value on failure
7945  */
7946 static enum i40e_status_code
7947 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
7948 {
7949         struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
7950         struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
7951         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7952         enum i40e_status_code ret;
7953         int i;
7954         uint32_t tc_bw_max;
7955
7956         /* Get the VSI level BW configuration */
7957         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
7958         if (ret) {
7959                 PMD_INIT_LOG(ERR,
7960                          "couldn't get PF vsi bw config, err %s aq_err %s\n",
7961                          i40e_stat_str(hw, ret),
7962                          i40e_aq_str(hw, hw->aq.asq_last_status));
7963                 return ret;
7964         }
7965
7966         /* Get the VSI level BW configuration per TC */
7967         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
7968                                                   NULL);
7969         if (ret) {
7970                 PMD_INIT_LOG(ERR,
7971                          "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
7972                          i40e_stat_str(hw, ret),
7973                          i40e_aq_str(hw, hw->aq.asq_last_status));
7974                 return ret;
7975         }
7976
7977         if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
7978                 PMD_INIT_LOG(WARNING,
7979                          "Enabled TCs mismatch from querying VSI BW info"
7980                          " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
7981                          bw_ets_config.tc_valid_bits);
7982                 /* Still continuing */
7983         }
7984
7985         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
7986         vsi->bw_info.bw_max_quanta = bw_config.max_bw;
7987         tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
7988                     (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
7989         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7990                 vsi->bw_info.bw_ets_share_credits[i] =
7991                                 bw_ets_config.share_credits[i];
7992                 vsi->bw_info.bw_ets_limit_credits[i] =
7993                                 rte_le_to_cpu_16(bw_ets_config.credits[i]);
7994                 /* 3 bits out of 4 for each TC */
7995                 vsi->bw_info.bw_ets_max_quanta[i] =
7996                         (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
7997                 PMD_INIT_LOG(DEBUG,
7998                          "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
7999                          __func__, vsi->seid, i, bw_config.qs_handles[i]);
8000         }
8001
8002         return ret;
8003 }
8004
8005 static enum i40e_status_code
8006 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8007                               struct i40e_aqc_vsi_properties_data *info,
8008                               uint8_t enabled_tcmap)
8009 {
8010         enum i40e_status_code ret;
8011         int i, total_tc = 0;
8012         uint16_t qpnum_per_tc, bsf, qp_idx;
8013         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8014
8015         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8016         if (ret != I40E_SUCCESS)
8017                 return ret;
8018
8019         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8020                 if (enabled_tcmap & (1 << i))
8021                         total_tc++;
8022         }
8023         if (total_tc == 0)
8024                 total_tc = 1;
8025         vsi->enabled_tc = enabled_tcmap;
8026
8027         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
8028         /* Number of queues per enabled TC */
8029         if (qpnum_per_tc == 0) {
8030                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8031                 return I40E_ERR_INVALID_QP_ID;
8032         }
8033         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8034                                 I40E_MAX_Q_PER_TC);
8035         bsf = rte_bsf32(qpnum_per_tc);
8036
8037         /**
8038          * Configure TC and queue mapping parameters, for enabled TC,
8039          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8040          * default queue will serve it.
8041          */
8042         qp_idx = 0;
8043         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8044                 if (vsi->enabled_tc & (1 << i)) {
8045                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8046                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8047                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8048                         qp_idx += qpnum_per_tc;
8049                 } else
8050                         info->tc_mapping[i] = 0;
8051         }
8052
8053         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8054         if (vsi->type == I40E_VSI_SRIOV) {
8055                 info->mapping_flags |=
8056                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8057                 for (i = 0; i < vsi->nb_qps; i++)
8058                         info->queue_mapping[i] =
8059                                 rte_cpu_to_le_16(vsi->base_queue + i);
8060         } else {
8061                 info->mapping_flags |=
8062                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8063                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8064         }
8065         info->valid_sections |=
8066                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8067
8068         return I40E_SUCCESS;
8069 }
8070
8071 /*
8072  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8073  * @vsi: VSI to be configured
8074  * @tc_map: enabled TC bitmap
8075  *
8076  * Returns 0 on success, negative value on failure
8077  */
8078 static enum i40e_status_code
8079 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
8080 {
8081         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8082         struct i40e_vsi_context ctxt;
8083         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8084         enum i40e_status_code ret = I40E_SUCCESS;
8085         int i;
8086
8087         /* Check if enabled_tc is same as existing or new TCs */
8088         if (vsi->enabled_tc == tc_map)
8089                 return ret;
8090
8091         /* configure tc bandwidth */
8092         memset(&bw_data, 0, sizeof(bw_data));
8093         bw_data.tc_valid_bits = tc_map;
8094         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8095         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8096                 if (tc_map & BIT_ULL(i))
8097                         bw_data.tc_bw_credits[i] = 1;
8098         }
8099         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8100         if (ret) {
8101                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8102                         " per TC failed = %d",
8103                         hw->aq.asq_last_status);
8104                 goto out;
8105         }
8106         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8107                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8108
8109         /* Update Queue Pairs Mapping for currently enabled UPs */
8110         ctxt.seid = vsi->seid;
8111         ctxt.pf_num = hw->pf_id;
8112         ctxt.vf_num = 0;
8113         ctxt.uplink_seid = vsi->uplink_seid;
8114         ctxt.info = vsi->info;
8115         i40e_get_cap(hw);
8116         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8117         if (ret)
8118                 goto out;
8119
8120         /* Update the VSI after updating the VSI queue-mapping information */
8121         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8122         if (ret) {
8123                 PMD_INIT_LOG(ERR, "Failed to configure "
8124                             "TC queue mapping = %d",
8125                             hw->aq.asq_last_status);
8126                 goto out;
8127         }
8128         /* update the local VSI info with updated queue map */
8129         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8130                                         sizeof(vsi->info.tc_mapping));
8131         (void)rte_memcpy(&vsi->info.queue_mapping,
8132                         &ctxt.info.queue_mapping,
8133                 sizeof(vsi->info.queue_mapping));
8134         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8135         vsi->info.valid_sections = 0;
8136
8137         /* Update current VSI BW information */
8138         ret = i40e_vsi_get_bw_info(vsi);
8139         if (ret) {
8140                 PMD_INIT_LOG(ERR,
8141                          "Failed updating vsi bw info, err %s aq_err %s",
8142                          i40e_stat_str(hw, ret),
8143                          i40e_aq_str(hw, hw->aq.asq_last_status));
8144                 goto out;
8145         }
8146
8147         vsi->enabled_tc = tc_map;
8148
8149 out:
8150         return ret;
8151 }
8152
8153 /*
8154  * i40e_dcb_hw_configure - program the dcb setting to hw
8155  * @pf: pf the configuration is taken on
8156  * @new_cfg: new configuration
8157  * @tc_map: enabled TC bitmap
8158  *
8159  * Returns 0 on success, negative value on failure
8160  */
8161 static enum i40e_status_code
8162 i40e_dcb_hw_configure(struct i40e_pf *pf,
8163                       struct i40e_dcbx_config *new_cfg,
8164                       uint8_t tc_map)
8165 {
8166         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8167         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8168         struct i40e_vsi *main_vsi = pf->main_vsi;
8169         struct i40e_vsi_list *vsi_list;
8170         enum i40e_status_code ret;
8171         int i;
8172         uint32_t val;
8173
8174         /* Use the FW API if FW > v4.4*/
8175         if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
8176                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8177                                   " to configure DCB");
8178                 return I40E_ERR_FIRMWARE_API_VERSION;
8179         }
8180
8181         /* Check if need reconfiguration */
8182         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8183                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8184                 return I40E_SUCCESS;
8185         }
8186
8187         /* Copy the new config to the current config */
8188         *old_cfg = *new_cfg;
8189         old_cfg->etsrec = old_cfg->etscfg;
8190         ret = i40e_set_dcb_config(hw);
8191         if (ret) {
8192                 PMD_INIT_LOG(ERR,
8193                          "Set DCB Config failed, err %s aq_err %s\n",
8194                          i40e_stat_str(hw, ret),
8195                          i40e_aq_str(hw, hw->aq.asq_last_status));
8196                 return ret;
8197         }
8198         /* set receive Arbiter to RR mode and ETS scheme by default */
8199         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8200                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8201                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8202                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8203                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8204                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8205                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8206                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8207                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8208                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8209                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8210                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8211                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8212         }
8213         /* get local mib to check whether it is configured correctly */
8214         /* IEEE mode */
8215         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8216         /* Get Local DCB Config */
8217         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8218                                      &hw->local_dcbx_config);
8219
8220         /* Update each VSI */
8221         i40e_vsi_config_tc(main_vsi, tc_map);
8222         if (main_vsi->veb) {
8223                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8224                         /* Beside main VSI, only enable default
8225                          * TC for other VSIs
8226                          */
8227                         ret = i40e_vsi_config_tc(vsi_list->vsi,
8228                                                 I40E_DEFAULT_TCMAP);
8229                         if (ret)
8230                                 PMD_INIT_LOG(WARNING,
8231                                          "Failed configuring TC for VSI seid=%d\n",
8232                                          vsi_list->vsi->seid);
8233                         /* continue */
8234                 }
8235         }
8236         return I40E_SUCCESS;
8237 }
8238
8239 /*
8240  * i40e_dcb_init_configure - initial dcb config
8241  * @dev: device being configured
8242  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8243  *
8244  * Returns 0 on success, negative value on failure
8245  */
8246 static int
8247 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8248 {
8249         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8250         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8251         int ret = 0;
8252
8253         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8254                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8255                 return -ENOTSUP;
8256         }
8257
8258         /* DCB initialization:
8259          * Update DCB configuration from the Firmware and configure
8260          * LLDP MIB change event.
8261          */
8262         if (sw_dcb == TRUE) {
8263                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8264                 if (ret != I40E_SUCCESS)
8265                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8266
8267                 ret = i40e_init_dcb(hw);
8268                 /* if sw_dcb, lldp agent is stopped, the return from
8269                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8270                  * adminq status.
8271                  */
8272                 if (ret != I40E_SUCCESS &&
8273                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8274                         memset(&hw->local_dcbx_config, 0,
8275                                 sizeof(struct i40e_dcbx_config));
8276                         /* set dcb default configuration */
8277                         hw->local_dcbx_config.etscfg.willing = 0;
8278                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8279                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8280                         hw->local_dcbx_config.etscfg.tsatable[0] =
8281                                                 I40E_IEEE_TSA_ETS;
8282                         hw->local_dcbx_config.etsrec =
8283                                 hw->local_dcbx_config.etscfg;
8284                         hw->local_dcbx_config.pfc.willing = 0;
8285                         hw->local_dcbx_config.pfc.pfccap =
8286                                                 I40E_MAX_TRAFFIC_CLASS;
8287                         /* FW needs one App to configure HW */
8288                         hw->local_dcbx_config.numapps = 1;
8289                         hw->local_dcbx_config.app[0].selector =
8290                                                 I40E_APP_SEL_ETHTYPE;
8291                         hw->local_dcbx_config.app[0].priority = 3;
8292                         hw->local_dcbx_config.app[0].protocolid =
8293                                                 I40E_APP_PROTOID_FCOE;
8294                         ret = i40e_set_dcb_config(hw);
8295                         if (ret) {
8296                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8297                                         " err = %d, aq_err = %d.", ret,
8298                                           hw->aq.asq_last_status);
8299                                 return -ENOSYS;
8300                         }
8301                 } else {
8302                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8303                                           " aq_err = %d.", ret,
8304                                           hw->aq.asq_last_status);
8305                         return -ENOTSUP;
8306                 }
8307         } else {
8308                 ret = i40e_aq_start_lldp(hw, NULL);
8309                 if (ret != I40E_SUCCESS)
8310                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8311
8312                 ret = i40e_init_dcb(hw);
8313                 if (!ret) {
8314                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8315                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8316                                                   " DCBX offload.");
8317                                 return -ENOTSUP;
8318                         }
8319                 } else {
8320                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8321                                           " aq_err = %d.", ret,
8322                                           hw->aq.asq_last_status);
8323                         return -ENOTSUP;
8324                 }
8325         }
8326         return 0;
8327 }
8328
8329 /*
8330  * i40e_dcb_setup - setup dcb related config
8331  * @dev: device being configured
8332  *
8333  * Returns 0 on success, negative value on failure
8334  */
8335 static int
8336 i40e_dcb_setup(struct rte_eth_dev *dev)
8337 {
8338         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8339         struct i40e_dcbx_config dcb_cfg;
8340         uint8_t tc_map = 0;
8341         int ret = 0;
8342
8343         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8344                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8345                 return -ENOTSUP;
8346         }
8347
8348         if (pf->vf_num != 0 ||
8349             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8350                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8351
8352         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8353         if (ret) {
8354                 PMD_INIT_LOG(ERR, "invalid dcb config");
8355                 return -EINVAL;
8356         }
8357         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8358         if (ret) {
8359                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8360                 return -ENOSYS;
8361         }
8362
8363         return 0;
8364 }
8365
8366 static int
8367 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8368                       struct rte_eth_dcb_info *dcb_info)
8369 {
8370         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8371         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8372         struct i40e_vsi *vsi = pf->main_vsi;
8373         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8374         uint16_t bsf, tc_mapping;
8375         int i;
8376
8377         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8378                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8379         else
8380                 dcb_info->nb_tcs = 1;
8381         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8382                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8383         for (i = 0; i < dcb_info->nb_tcs; i++)
8384                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8385
8386         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8387                 if (vsi->enabled_tc & (1 << i)) {
8388                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8389                         /* only main vsi support multi TCs */
8390                         dcb_info->tc_queue.tc_rxq[0][i].base =
8391                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8392                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8393                         dcb_info->tc_queue.tc_txq[0][i].base =
8394                                 dcb_info->tc_queue.tc_rxq[0][i].base;
8395                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8396                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8397                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8398                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8399                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
8400                 }
8401         }
8402
8403         return 0;
8404 }
8405
8406 static int
8407 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8408 {
8409         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8410         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8411         uint16_t interval =
8412                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8413         uint16_t msix_intr;
8414
8415         msix_intr = intr_handle->intr_vec[queue_id];
8416         if (msix_intr == I40E_MISC_VEC_ID)
8417                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8418                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8419                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8420                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8421                                (interval <<
8422                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8423         else
8424                 I40E_WRITE_REG(hw,
8425                                I40E_PFINT_DYN_CTLN(msix_intr -
8426                                                    I40E_RX_VEC_START),
8427                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8428                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8429                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8430                                (interval <<
8431                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8432
8433         I40E_WRITE_FLUSH(hw);
8434         rte_intr_enable(&dev->pci_dev->intr_handle);
8435
8436         return 0;
8437 }
8438
8439 static int
8440 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8441 {
8442         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8443         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8444         uint16_t msix_intr;
8445
8446         msix_intr = intr_handle->intr_vec[queue_id];
8447         if (msix_intr == I40E_MISC_VEC_ID)
8448                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8449         else
8450                 I40E_WRITE_REG(hw,
8451                                I40E_PFINT_DYN_CTLN(msix_intr -
8452                                                    I40E_RX_VEC_START),
8453                                0);
8454         I40E_WRITE_FLUSH(hw);
8455
8456         return 0;
8457 }