drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_eth_ctrl.h>
  28 #include <rte_tailq.h>
  29 #include <rte_hash_crc.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45
  46 #define I40E_CLEAR_PXE_WAIT_MS     200
  47
  48 /* Maximun number of capability elements */
  49 #define I40E_MAX_CAP_ELE_NUM       128
  50
  51 /* Wait count and interval */
  52 #define I40E_CHK_Q_ENA_COUNT       1000
  53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  54
  55 /* Maximun number of VSI */
  56 #define I40E_MAX_NUM_VSIS          (384UL)
  57
  58 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  59
  60 /* Flow control default timer */
  61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  62
  63 /* Flow control enable fwd bit */
  64 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  65
  66 /* Receive Packet Buffer size */
  67 #define I40E_RXPBSIZE (968 * 1024)
  68
  69 /* Kilobytes shift */
  70 #define I40E_KILOSHIFT 10
  71
  72 /* Flow control default high water */
  73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  74
  75 /* Flow control default low water */
  76 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Receive Average Packet Size in Byte*/
  79 #define I40E_PACKET_AVERAGE_SIZE 128
  80
  81 /* Mask of PF interrupt causes */
  82 #define I40E_PFINT_ICR0_ENA_MASK ( \
  83                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  84                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  85                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  86                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  87                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  92
  93 #define I40E_FLOW_TYPES ( \
  94         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  99         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 104         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 105
 106 /* Additional timesync values. */
 107 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 108 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 109 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 110 #define I40E_PRTTSYN_TSYNENA     0x80000000
 111 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 112 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 113
 114 /**
 115  * Below are values for writing un-exposed registers suggested
 116  * by silicon experts
 117  */
 118 /* Destination MAC address */
 119 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 120 /* Source MAC address */
 121 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 123 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 125 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 126 /* Single VLAN tag in the inner L2 header */
 127 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 128 /* Source IPv4 address */
 129 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 130 /* Destination IPv4 address */
 131 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 132 /* Source IPv4 address for X722 */
 133 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 134 /* Destination IPv4 address for X722 */
 135 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 136 /* IPv4 Protocol for X722 */
 137 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 138 /* IPv4 Time to Live for X722 */
 139 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 140 /* IPv4 Type of Service (TOS) */
 141 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 142 /* IPv4 Protocol */
 143 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 144 /* IPv4 Time to Live */
 145 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 146 /* Source IPv6 address */
 147 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 148 /* Destination IPv6 address */
 149 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 150 /* IPv6 Traffic Class (TC) */
 151 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 152 /* IPv6 Next Header */
 153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 154 /* IPv6 Hop Limit */
 155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 156 /* Source L4 port */
 157 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 158 /* Destination L4 port */
 159 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 160 /* SCTP verification tag */
 161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 164 /* Source port of tunneling UDP */
 165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 166 /* Destination port of tunneling UDP */
 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 168 /* UDP Tunneling ID, NVGRE/GRE key */
 169 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 170 /* Last ether type */
 171 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 172 /* Tunneling outer destination IPv4 address */
 173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 174 /* Tunneling outer destination IPv6 address */
 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 176 /* 1st word of flex payload */
 177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 178 /* 2nd word of flex payload */
 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 180 /* 3rd word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 182 /* 4th word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 184 /* 5th word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 186 /* 6th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 188 /* 7th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 190 /* 8th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 192 /* all 8 words flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 194 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 195
 196 #define I40E_TRANSLATE_INSET 0
 197 #define I40E_TRANSLATE_REG   1
 198
 199 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 200 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 201 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 202 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 204 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 205
 206 /* PCI offset for querying capability */
 207 #define PCI_DEV_CAP_REG            0xA4
 208 /* PCI offset for enabling/disabling Extended Tag */
 209 #define PCI_DEV_CTRL_REG           0xA8
 210 /* Bit mask of Extended Tag capability */
 211 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 212 /* Bit shift of Extended Tag enable/disable */
 213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 214 /* Bit mask of Extended Tag enable/disable */
 215 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 216
 217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 219 static int i40e_dev_configure(struct rte_eth_dev *dev);
 220 static int i40e_dev_start(struct rte_eth_dev *dev);
 221 static void i40e_dev_stop(struct rte_eth_dev *dev);
 222 static void i40e_dev_close(struct rte_eth_dev *dev);
 223 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_stats *stats);
 232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 233                                struct rte_eth_xstat *xstats, unsigned n);
 234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 235                                      struct rte_eth_xstat_name *xstats_names,
 236                                      unsigned limit);
 237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 239                                             uint16_t queue_id,
 240                                             uint8_t stat_idx,
 241                                             uint8_t is_rx);
 242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 243                                 char *fw_version, size_t fw_size);
 244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 245                               struct rte_eth_dev_info *dev_info);
 246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 247                                 uint16_t vlan_id,
 248                                 int on);
 249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 250                               enum rte_vlan_type vlan_type,
 251                               uint16_t tpid);
 252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                                       uint16_t queue,
 255                                       int on);
 256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 260                               struct rte_eth_fc_conf *fc_conf);
 261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 264                                        struct rte_eth_pfc_conf *pfc_conf);
 265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 266                             struct ether_addr *mac_addr,
 267                             uint32_t index,
 268                             uint32_t pool);
 269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 271                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 272                                     uint16_t reta_size);
 273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 274                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 275                                    uint16_t reta_size);
 276
 277 static int i40e_get_cap(struct i40e_hw *hw);
 278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 279 static int i40e_pf_setup(struct i40e_pf *pf);
 280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 284                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 285 static void i40e_stat_update_48(struct i40e_hw *hw,
 286                                uint32_t hireg,
 287                                uint32_t loreg,
 288                                bool offset_loaded,
 289                                uint64_t *offset,
 290                                uint64_t *stat);
 291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 292 static void i40e_dev_interrupt_handler(void *param);
 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 294                                 uint32_t base, uint32_t num);
 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 297                         uint32_t base);
 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 299                         uint16_t num);
 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 301 static int i40e_veb_release(struct i40e_veb *veb);
 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 303                                                 struct i40e_vsi *vsi);
 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static int i40e_get_module_info(struct rte_eth_dev *dev,
 374                                 struct rte_eth_dev_module_info *modinfo);
 375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 376                                   struct rte_dev_eeprom_info *info);
 377
 378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 379                                       struct ether_addr *mac_addr);
 380
 381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 382
 383 static int i40e_ethertype_filter_convert(
 384         const struct rte_eth_ethertype_filter *input,
 385         struct i40e_ethertype_filter *filter);
 386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 387                                    struct i40e_ethertype_filter *filter);
 388
 389 static int i40e_tunnel_filter_convert(
 390         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 391         struct i40e_tunnel_filter *tunnel_filter);
 392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 393                                 struct i40e_tunnel_filter *tunnel_filter);
 394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 395
 396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 398 static void i40e_filter_restore(struct i40e_pf *pf);
 399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 400
 401 int i40e_logtype_init;
 402 int i40e_logtype_driver;
 403
 404 static const struct rte_pci_id pci_id_i40e_map[] = {
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 425         { .vendor_id = 0, /* sentinel */ },
 426 };
 427
 428 static const struct eth_dev_ops i40e_eth_dev_ops = {
 429         .dev_configure                = i40e_dev_configure,
 430         .dev_start                    = i40e_dev_start,
 431         .dev_stop                     = i40e_dev_stop,
 432         .dev_close                    = i40e_dev_close,
 433         .dev_reset                    = i40e_dev_reset,
 434         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 435         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 436         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 437         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 438         .dev_set_link_up              = i40e_dev_set_link_up,
 439         .dev_set_link_down            = i40e_dev_set_link_down,
 440         .link_update                  = i40e_dev_link_update,
 441         .stats_get                    = i40e_dev_stats_get,
 442         .xstats_get                   = i40e_dev_xstats_get,
 443         .xstats_get_names             = i40e_dev_xstats_get_names,
 444         .stats_reset                  = i40e_dev_stats_reset,
 445         .xstats_reset                 = i40e_dev_stats_reset,
 446         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 447         .fw_version_get               = i40e_fw_version_get,
 448         .dev_infos_get                = i40e_dev_info_get,
 449         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 450         .vlan_filter_set              = i40e_vlan_filter_set,
 451         .vlan_tpid_set                = i40e_vlan_tpid_set,
 452         .vlan_offload_set             = i40e_vlan_offload_set,
 453         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 454         .vlan_pvid_set                = i40e_vlan_pvid_set,
 455         .rx_queue_start               = i40e_dev_rx_queue_start,
 456         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 457         .tx_queue_start               = i40e_dev_tx_queue_start,
 458         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 459         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 460         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 461         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 462         .rx_queue_release             = i40e_dev_rx_queue_release,
 463         .rx_queue_count               = i40e_dev_rx_queue_count,
 464         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 465         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 466         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 467         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 468         .tx_queue_release             = i40e_dev_tx_queue_release,
 469         .dev_led_on                   = i40e_dev_led_on,
 470         .dev_led_off                  = i40e_dev_led_off,
 471         .flow_ctrl_get                = i40e_flow_ctrl_get,
 472         .flow_ctrl_set                = i40e_flow_ctrl_set,
 473         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 474         .mac_addr_add                 = i40e_macaddr_add,
 475         .mac_addr_remove              = i40e_macaddr_remove,
 476         .reta_update                  = i40e_dev_rss_reta_update,
 477         .reta_query                   = i40e_dev_rss_reta_query,
 478         .rss_hash_update              = i40e_dev_rss_hash_update,
 479         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 480         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 481         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 482         .filter_ctrl                  = i40e_dev_filter_ctrl,
 483         .rxq_info_get                 = i40e_rxq_info_get,
 484         .txq_info_get                 = i40e_txq_info_get,
 485         .mirror_rule_set              = i40e_mirror_rule_set,
 486         .mirror_rule_reset            = i40e_mirror_rule_reset,
 487         .timesync_enable              = i40e_timesync_enable,
 488         .timesync_disable             = i40e_timesync_disable,
 489         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 490         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 491         .get_dcb_info                 = i40e_dev_get_dcb_info,
 492         .timesync_adjust_time         = i40e_timesync_adjust_time,
 493         .timesync_read_time           = i40e_timesync_read_time,
 494         .timesync_write_time          = i40e_timesync_write_time,
 495         .get_reg                      = i40e_get_regs,
 496         .get_eeprom_length            = i40e_get_eeprom_length,
 497         .get_eeprom                   = i40e_get_eeprom,
 498         .get_module_info              = i40e_get_module_info,
 499         .get_module_eeprom            = i40e_get_module_eeprom,
 500         .mac_addr_set                 = i40e_set_default_mac_addr,
 501         .mtu_set                      = i40e_dev_mtu_set,
 502         .tm_ops_get                   = i40e_tm_ops_get,
 503 };
 504
 505 /* store statistics names and its offset in stats structure */
 506 struct rte_i40e_xstats_name_off {
 507         char name[RTE_ETH_XSTATS_NAME_SIZE];
 508         unsigned offset;
 509 };
 510
 511 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 512         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 513         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 514         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 515         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 516         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 517                 rx_unknown_protocol)},
 518         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 519         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 520         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 521         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 522 };
 523
 524 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 525                 sizeof(rte_i40e_stats_strings[0]))
 526
 527 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 528         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 529                 tx_dropped_link_down)},
 530         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 531         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 532                 illegal_bytes)},
 533         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 534         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 535                 mac_local_faults)},
 536         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 537                 mac_remote_faults)},
 538         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 539                 rx_length_errors)},
 540         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 541         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 542         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 543         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 544         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 545         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 546                 rx_size_127)},
 547         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 548                 rx_size_255)},
 549         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 550                 rx_size_511)},
 551         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 552                 rx_size_1023)},
 553         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 554                 rx_size_1522)},
 555         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 556                 rx_size_big)},
 557         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 558                 rx_undersize)},
 559         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 560                 rx_oversize)},
 561         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 562                 mac_short_packet_dropped)},
 563         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 564                 rx_fragments)},
 565         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 566         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 567         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 568                 tx_size_127)},
 569         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 570                 tx_size_255)},
 571         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 572                 tx_size_511)},
 573         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 574                 tx_size_1023)},
 575         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 576                 tx_size_1522)},
 577         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 578                 tx_size_big)},
 579         {"rx_flow_director_atr_match_packets",
 580                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 581         {"rx_flow_director_sb_match_packets",
 582                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 583         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 584                 tx_lpi_status)},
 585         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 586                 rx_lpi_status)},
 587         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 588                 tx_lpi_count)},
 589         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 590                 rx_lpi_count)},
 591 };
 592
 593 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 594                 sizeof(rte_i40e_hw_port_strings[0]))
 595
 596 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 597         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 598                 priority_xon_rx)},
 599         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 600                 priority_xoff_rx)},
 601 };
 602
 603 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 604                 sizeof(rte_i40e_rxq_prio_strings[0]))
 605
 606 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 607         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 608                 priority_xon_tx)},
 609         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xoff_tx)},
 611         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xon_2_xoff)},
 613 };
 614
 615 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 616                 sizeof(rte_i40e_txq_prio_strings[0]))
 617
 618 static int
 619 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 620         struct rte_pci_device *pci_dev)
 621 {
 622         char name[RTE_ETH_NAME_MAX_LEN];
 623         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 624         int i, retval;
 625
 626         if (pci_dev->device.devargs) {
 627                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 628                                 &eth_da);
 629                 if (retval)
 630                         return retval;
 631         }
 632
 633         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 634                 sizeof(struct i40e_adapter),
 635                 eth_dev_pci_specific_init, pci_dev,
 636                 eth_i40e_dev_init, NULL);
 637
 638         if (retval || eth_da.nb_representor_ports < 1)
 639                 return retval;
 640
 641         /* probe VF representor ports */
 642         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 643                 pci_dev->device.name);
 644
 645         if (pf_ethdev == NULL)
 646                 return -ENODEV;
 647
 648         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 649                 struct i40e_vf_representor representor = {
 650                         .vf_id = eth_da.representor_ports[i],
 651                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 652                                 pf_ethdev->data->dev_private)->switch_domain_id,
 653                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 654                                 pf_ethdev->data->dev_private)
 655                 };
 656
 657                 /* representor port net_bdf_port */
 658                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 659                         pci_dev->device.name, eth_da.representor_ports[i]);
 660
 661                 retval = rte_eth_dev_create(&pci_dev->device, name,
 662                         sizeof(struct i40e_vf_representor), NULL, NULL,
 663                         i40e_vf_representor_init, &representor);
 664
 665                 if (retval)
 666                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 667                                 "representor %s.", name);
 668         }
 669
 670         return 0;
 671 }
 672
 673 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 674 {
 675         struct rte_eth_dev *ethdev;
 676
 677         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 678         if (!ethdev)
 679                 return -ENODEV;
 680
 681
 682         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 683                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 684         else
 685                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 686 }
 687
 688 static struct rte_pci_driver rte_i40e_pmd = {
 689         .id_table = pci_id_i40e_map,
 690         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 691                      RTE_PCI_DRV_IOVA_AS_VA,
 692         .probe = eth_i40e_pci_probe,
 693         .remove = eth_i40e_pci_remove,
 694 };
 695
 696 static inline void
 697 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 698                          uint32_t reg_val)
 699 {
 700         uint32_t ori_reg_val;
 701         struct rte_eth_dev *dev;
 702
 703         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 704         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 705         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 706         if (ori_reg_val != reg_val)
 707                 PMD_DRV_LOG(WARNING,
 708                             "i40e device %s changed global register [0x%08x]."
 709                             " original: 0x%08x, new: 0x%08x",
 710                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 711 }
 712
 713 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 714 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 715 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 716
 717 #ifndef I40E_GLQF_ORT
 718 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 719 #endif
 720 #ifndef I40E_GLQF_PIT
 721 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 722 #endif
 723 #ifndef I40E_GLQF_L3_MAP
 724 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 725 #endif
 726
 727 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 728 {
 729         /*
 730          * Initialize registers for parsing packet type of QinQ
 731          * This should be removed from code once proper
 732          * configuration API is added to avoid configuration conflicts
 733          * between ports of the same device.
 734          */
 735         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 736         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 737 }
 738
 739 static inline void i40e_config_automask(struct i40e_pf *pf)
 740 {
 741         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 742         uint32_t val;
 743
 744         /* INTENA flag is not auto-cleared for interrupt */
 745         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 746         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 747                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 748
 749         /* If support multi-driver, PF will use INT0. */
 750         if (!pf->support_multi_driver)
 751                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 752
 753         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 754 }
 755
 756 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 757
 758 /*
 759  * Add a ethertype filter to drop all flow control frames transmitted
 760  * from VSIs.
 761 */
 762 static void
 763 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 764 {
 765         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 766         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 767                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 768                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 769         int ret;
 770
 771         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 772                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 773                                 pf->main_vsi_seid, 0,
 774                                 TRUE, NULL, NULL);
 775         if (ret)
 776                 PMD_INIT_LOG(ERR,
 777                         "Failed to add filter to drop flow control frames from VSIs.");
 778 }
 779
 780 static int
 781 floating_veb_list_handler(__rte_unused const char *key,
 782                           const char *floating_veb_value,
 783                           void *opaque)
 784 {
 785         int idx = 0;
 786         unsigned int count = 0;
 787         char *end = NULL;
 788         int min, max;
 789         bool *vf_floating_veb = opaque;
 790
 791         while (isblank(*floating_veb_value))
 792                 floating_veb_value++;
 793
 794         /* Reset floating VEB configuration for VFs */
 795         for (idx = 0; idx < I40E_MAX_VF; idx++)
 796                 vf_floating_veb[idx] = false;
 797
 798         min = I40E_MAX_VF;
 799         do {
 800                 while (isblank(*floating_veb_value))
 801                         floating_veb_value++;
 802                 if (*floating_veb_value == '\0')
 803                         return -1;
 804                 errno = 0;
 805                 idx = strtoul(floating_veb_value, &end, 10);
 806                 if (errno || end == NULL)
 807                         return -1;
 808                 while (isblank(*end))
 809                         end++;
 810                 if (*end == '-') {
 811                         min = idx;
 812                 } else if ((*end == ';') || (*end == '\0')) {
 813                         max = idx;
 814                         if (min == I40E_MAX_VF)
 815                                 min = idx;
 816                         if (max >= I40E_MAX_VF)
 817                                 max = I40E_MAX_VF - 1;
 818                         for (idx = min; idx <= max; idx++) {
 819                                 vf_floating_veb[idx] = true;
 820                                 count++;
 821                         }
 822                         min = I40E_MAX_VF;
 823                 } else {
 824                         return -1;
 825                 }
 826                 floating_veb_value = end + 1;
 827         } while (*end != '\0');
 828
 829         if (count == 0)
 830                 return -1;
 831
 832         return 0;
 833 }
 834
 835 static void
 836 config_vf_floating_veb(struct rte_devargs *devargs,
 837                        uint16_t floating_veb,
 838                        bool *vf_floating_veb)
 839 {
 840         struct rte_kvargs *kvlist;
 841         int i;
 842         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 843
 844         if (!floating_veb)
 845                 return;
 846         /* All the VFs attach to the floating VEB by default
 847          * when the floating VEB is enabled.
 848          */
 849         for (i = 0; i < I40E_MAX_VF; i++)
 850                 vf_floating_veb[i] = true;
 851
 852         if (devargs == NULL)
 853                 return;
 854
 855         kvlist = rte_kvargs_parse(devargs->args, NULL);
 856         if (kvlist == NULL)
 857                 return;
 858
 859         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 860                 rte_kvargs_free(kvlist);
 861                 return;
 862         }
 863         /* When the floating_veb_list parameter exists, all the VFs
 864          * will attach to the legacy VEB firstly, then configure VFs
 865          * to the floating VEB according to the floating_veb_list.
 866          */
 867         if (rte_kvargs_process(kvlist, floating_veb_list,
 868                                floating_veb_list_handler,
 869                                vf_floating_veb) < 0) {
 870                 rte_kvargs_free(kvlist);
 871                 return;
 872         }
 873         rte_kvargs_free(kvlist);
 874 }
 875
 876 static int
 877 i40e_check_floating_handler(__rte_unused const char *key,
 878                             const char *value,
 879                             __rte_unused void *opaque)
 880 {
 881         if (strcmp(value, "1"))
 882                 return -1;
 883
 884         return 0;
 885 }
 886
 887 static int
 888 is_floating_veb_supported(struct rte_devargs *devargs)
 889 {
 890         struct rte_kvargs *kvlist;
 891         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 892
 893         if (devargs == NULL)
 894                 return 0;
 895
 896         kvlist = rte_kvargs_parse(devargs->args, NULL);
 897         if (kvlist == NULL)
 898                 return 0;
 899
 900         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 901                 rte_kvargs_free(kvlist);
 902                 return 0;
 903         }
 904         /* Floating VEB is enabled when there's key-value:
 905          * enable_floating_veb=1
 906          */
 907         if (rte_kvargs_process(kvlist, floating_veb_key,
 908                                i40e_check_floating_handler, NULL) < 0) {
 909                 rte_kvargs_free(kvlist);
 910                 return 0;
 911         }
 912         rte_kvargs_free(kvlist);
 913
 914         return 1;
 915 }
 916
 917 static void
 918 config_floating_veb(struct rte_eth_dev *dev)
 919 {
 920         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 921         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 922         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 923
 924         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 925
 926         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 927                 pf->floating_veb =
 928                         is_floating_veb_supported(pci_dev->device.devargs);
 929                 config_vf_floating_veb(pci_dev->device.devargs,
 930                                        pf->floating_veb,
 931                                        pf->floating_veb_list);
 932         } else {
 933                 pf->floating_veb = false;
 934         }
 935 }
 936
 937 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 938 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 939
 940 static int
 941 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 942 {
 943         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 944         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 945         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 946         int ret;
 947
 948         struct rte_hash_parameters ethertype_hash_params = {
 949                 .name = ethertype_hash_name,
 950                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 951                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 952                 .hash_func = rte_hash_crc,
 953                 .hash_func_init_val = 0,
 954                 .socket_id = rte_socket_id(),
 955         };
 956
 957         /* Initialize ethertype filter rule list and hash */
 958         TAILQ_INIT(&ethertype_rule->ethertype_list);
 959         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 960                  "ethertype_%s", dev->device->name);
 961         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 962         if (!ethertype_rule->hash_table) {
 963                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 964                 return -EINVAL;
 965         }
 966         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 967                                        sizeof(struct i40e_ethertype_filter *) *
 968                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 969                                        0);
 970         if (!ethertype_rule->hash_map) {
 971                 PMD_INIT_LOG(ERR,
 972                              "Failed to allocate memory for ethertype hash map!");
 973                 ret = -ENOMEM;
 974                 goto err_ethertype_hash_map_alloc;
 975         }
 976
 977         return 0;
 978
 979 err_ethertype_hash_map_alloc:
 980         rte_hash_free(ethertype_rule->hash_table);
 981
 982         return ret;
 983 }
 984
 985 static int
 986 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 987 {
 988         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 989         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 990         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 991         int ret;
 992
 993         struct rte_hash_parameters tunnel_hash_params = {
 994                 .name = tunnel_hash_name,
 995                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 996                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 997                 .hash_func = rte_hash_crc,
 998                 .hash_func_init_val = 0,
 999                 .socket_id = rte_socket_id(),
1000         };
1001
1002         /* Initialize tunnel filter rule list and hash */
1003         TAILQ_INIT(&tunnel_rule->tunnel_list);
1004         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1005                  "tunnel_%s", dev->device->name);
1006         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1007         if (!tunnel_rule->hash_table) {
1008                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1009                 return -EINVAL;
1010         }
1011         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1012                                     sizeof(struct i40e_tunnel_filter *) *
1013                                     I40E_MAX_TUNNEL_FILTER_NUM,
1014                                     0);
1015         if (!tunnel_rule->hash_map) {
1016                 PMD_INIT_LOG(ERR,
1017                              "Failed to allocate memory for tunnel hash map!");
1018                 ret = -ENOMEM;
1019                 goto err_tunnel_hash_map_alloc;
1020         }
1021
1022         return 0;
1023
1024 err_tunnel_hash_map_alloc:
1025         rte_hash_free(tunnel_rule->hash_table);
1026
1027         return ret;
1028 }
1029
1030 static int
1031 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1032 {
1033         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1034         struct i40e_fdir_info *fdir_info = &pf->fdir;
1035         char fdir_hash_name[RTE_HASH_NAMESIZE];
1036         int ret;
1037
1038         struct rte_hash_parameters fdir_hash_params = {
1039                 .name = fdir_hash_name,
1040                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1041                 .key_len = sizeof(struct i40e_fdir_input),
1042                 .hash_func = rte_hash_crc,
1043                 .hash_func_init_val = 0,
1044                 .socket_id = rte_socket_id(),
1045         };
1046
1047         /* Initialize flow director filter rule list and hash */
1048         TAILQ_INIT(&fdir_info->fdir_list);
1049         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1050                  "fdir_%s", dev->device->name);
1051         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1052         if (!fdir_info->hash_table) {
1053                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1054                 return -EINVAL;
1055         }
1056         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1057                                           sizeof(struct i40e_fdir_filter *) *
1058                                           I40E_MAX_FDIR_FILTER_NUM,
1059                                           0);
1060         if (!fdir_info->hash_map) {
1061                 PMD_INIT_LOG(ERR,
1062                              "Failed to allocate memory for fdir hash map!");
1063                 ret = -ENOMEM;
1064                 goto err_fdir_hash_map_alloc;
1065         }
1066         return 0;
1067
1068 err_fdir_hash_map_alloc:
1069         rte_hash_free(fdir_info->hash_table);
1070
1071         return ret;
1072 }
1073
1074 static void
1075 i40e_init_customized_info(struct i40e_pf *pf)
1076 {
1077         int i;
1078
1079         /* Initialize customized pctype */
1080         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1081                 pf->customized_pctype[i].index = i;
1082                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1083                 pf->customized_pctype[i].valid = false;
1084         }
1085
1086         pf->gtp_support = false;
1087 }
1088
1089 void
1090 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1091 {
1092         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1093         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1094         struct i40e_queue_regions *info = &pf->queue_region;
1095         uint16_t i;
1096
1097         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1098                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1099
1100         memset(info, 0, sizeof(struct i40e_queue_regions));
1101 }
1102
1103 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
1104
1105 static int
1106 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1107                                const char *value,
1108                                void *opaque)
1109 {
1110         struct i40e_pf *pf;
1111         unsigned long support_multi_driver;
1112         char *end;
1113
1114         pf = (struct i40e_pf *)opaque;
1115
1116         errno = 0;
1117         support_multi_driver = strtoul(value, &end, 10);
1118         if (errno != 0 || end == value || *end != 0) {
1119                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1120                 return -(EINVAL);
1121         }
1122
1123         if (support_multi_driver == 1 || support_multi_driver == 0)
1124                 pf->support_multi_driver = (bool)support_multi_driver;
1125         else
1126                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1127                             "enable global configuration by default."
1128                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1129         return 0;
1130 }
1131
1132 static int
1133 i40e_support_multi_driver(struct rte_eth_dev *dev)
1134 {
1135         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1136         static const char *const valid_keys[] = {
1137                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1138         struct rte_kvargs *kvlist;
1139
1140         /* Enable global configuration by default */
1141         pf->support_multi_driver = false;
1142
1143         if (!dev->device->devargs)
1144                 return 0;
1145
1146         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1147         if (!kvlist)
1148                 return -EINVAL;
1149
1150         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1151                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1152                             "the first invalid or last valid one is used !",
1153                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1154
1155         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1156                                i40e_parse_multi_drv_handler, pf) < 0) {
1157                 rte_kvargs_free(kvlist);
1158                 return -EINVAL;
1159         }
1160
1161         rte_kvargs_free(kvlist);
1162         return 0;
1163 }
1164
1165 static int
1166 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1167                                     uint32_t reg_addr, uint64_t reg_val,
1168                                     struct i40e_asq_cmd_details *cmd_details)
1169 {
1170         uint64_t ori_reg_val;
1171         struct rte_eth_dev *dev;
1172         int ret;
1173
1174         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1175         if (ret != I40E_SUCCESS) {
1176                 PMD_DRV_LOG(ERR,
1177                             "Fail to debug read from 0x%08x",
1178                             reg_addr);
1179                 return -EIO;
1180         }
1181         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1182
1183         if (ori_reg_val != reg_val)
1184                 PMD_DRV_LOG(WARNING,
1185                             "i40e device %s changed global register [0x%08x]."
1186                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1187                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1188
1189         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1190 }
1191
1192 static int
1193 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1194 {
1195         struct rte_pci_device *pci_dev;
1196         struct rte_intr_handle *intr_handle;
1197         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1198         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1199         struct i40e_vsi *vsi;
1200         int ret;
1201         uint32_t len;
1202         uint8_t aq_fail = 0;
1203
1204         PMD_INIT_FUNC_TRACE();
1205
1206         dev->dev_ops = &i40e_eth_dev_ops;
1207         dev->rx_pkt_burst = i40e_recv_pkts;
1208         dev->tx_pkt_burst = i40e_xmit_pkts;
1209         dev->tx_pkt_prepare = i40e_prep_pkts;
1210
1211         /* for secondary processes, we don't initialise any further as primary
1212          * has already done this work. Only check we don't need a different
1213          * RX function */
1214         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1215                 i40e_set_rx_function(dev);
1216                 i40e_set_tx_function(dev);
1217                 return 0;
1218         }
1219         i40e_set_default_ptype_table(dev);
1220         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1221         intr_handle = &pci_dev->intr_handle;
1222
1223         rte_eth_copy_pci_info(dev, pci_dev);
1224
1225         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1226         pf->adapter->eth_dev = dev;
1227         pf->dev_data = dev->data;
1228
1229         hw->back = I40E_PF_TO_ADAPTER(pf);
1230         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1231         if (!hw->hw_addr) {
1232                 PMD_INIT_LOG(ERR,
1233                         "Hardware is not available, as address is NULL");
1234                 return -ENODEV;
1235         }
1236
1237         hw->vendor_id = pci_dev->id.vendor_id;
1238         hw->device_id = pci_dev->id.device_id;
1239         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1240         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1241         hw->bus.device = pci_dev->addr.devid;
1242         hw->bus.func = pci_dev->addr.function;
1243         hw->adapter_stopped = 0;
1244
1245         /* Check if need to support multi-driver */
1246         i40e_support_multi_driver(dev);
1247
1248         /* Make sure all is clean before doing PF reset */
1249         i40e_clear_hw(hw);
1250
1251         /* Initialize the hardware */
1252         i40e_hw_init(dev);
1253
1254         /* Reset here to make sure all is clean for each PF */
1255         ret = i40e_pf_reset(hw);
1256         if (ret) {
1257                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1258                 return ret;
1259         }
1260
1261         /* Initialize the shared code (base driver) */
1262         ret = i40e_init_shared_code(hw);
1263         if (ret) {
1264                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1265                 return ret;
1266         }
1267
1268         i40e_config_automask(pf);
1269
1270         i40e_set_default_pctype_table(dev);
1271
1272         /*
1273          * To work around the NVM issue, initialize registers
1274          * for packet type of QinQ by software.
1275          * It should be removed once issues are fixed in NVM.
1276          */
1277         if (!pf->support_multi_driver)
1278                 i40e_GLQF_reg_init(hw);
1279
1280         /* Initialize the input set for filters (hash and fd) to default value */
1281         i40e_filter_input_set_init(pf);
1282
1283         /* Initialize the parameters for adminq */
1284         i40e_init_adminq_parameter(hw);
1285         ret = i40e_init_adminq(hw);
1286         if (ret != I40E_SUCCESS) {
1287                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1288                 return -EIO;
1289         }
1290         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1291                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1292                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1293                      ((hw->nvm.version >> 12) & 0xf),
1294                      ((hw->nvm.version >> 4) & 0xff),
1295                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1296
1297         /* initialise the L3_MAP register */
1298         if (!pf->support_multi_driver) {
1299                 ret = i40e_aq_debug_write_global_register(hw,
1300                                                    I40E_GLQF_L3_MAP(40),
1301                                                    0x00000028,  NULL);
1302                 if (ret)
1303                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1304                                      ret);
1305                 PMD_INIT_LOG(DEBUG,
1306                              "Global register 0x%08x is changed with 0x28",
1307                              I40E_GLQF_L3_MAP(40));
1308         }
1309
1310         /* Need the special FW version to support floating VEB */
1311         config_floating_veb(dev);
1312         /* Clear PXE mode */
1313         i40e_clear_pxe_mode(hw);
1314         i40e_dev_sync_phy_type(hw);
1315
1316         /*
1317          * On X710, performance number is far from the expectation on recent
1318          * firmware versions. The fix for this issue may not be integrated in
1319          * the following firmware version. So the workaround in software driver
1320          * is needed. It needs to modify the initial values of 3 internal only
1321          * registers. Note that the workaround can be removed when it is fixed
1322          * in firmware in the future.
1323          */
1324         i40e_configure_registers(hw);
1325
1326         /* Get hw capabilities */
1327         ret = i40e_get_cap(hw);
1328         if (ret != I40E_SUCCESS) {
1329                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1330                 goto err_get_capabilities;
1331         }
1332
1333         /* Initialize parameters for PF */
1334         ret = i40e_pf_parameter_init(dev);
1335         if (ret != 0) {
1336                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1337                 goto err_parameter_init;
1338         }
1339
1340         /* Initialize the queue management */
1341         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1342         if (ret < 0) {
1343                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1344                 goto err_qp_pool_init;
1345         }
1346         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1347                                 hw->func_caps.num_msix_vectors - 1);
1348         if (ret < 0) {
1349                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1350                 goto err_msix_pool_init;
1351         }
1352
1353         /* Initialize lan hmc */
1354         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1355                                 hw->func_caps.num_rx_qp, 0, 0);
1356         if (ret != I40E_SUCCESS) {
1357                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1358                 goto err_init_lan_hmc;
1359         }
1360
1361         /* Configure lan hmc */
1362         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1363         if (ret != I40E_SUCCESS) {
1364                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1365                 goto err_configure_lan_hmc;
1366         }
1367
1368         /* Get and check the mac address */
1369         i40e_get_mac_addr(hw, hw->mac.addr);
1370         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1371                 PMD_INIT_LOG(ERR, "mac address is not valid");
1372                 ret = -EIO;
1373                 goto err_get_mac_addr;
1374         }
1375         /* Copy the permanent MAC address */
1376         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1377                         (struct ether_addr *) hw->mac.perm_addr);
1378
1379         /* Disable flow control */
1380         hw->fc.requested_mode = I40E_FC_NONE;
1381         i40e_set_fc(hw, &aq_fail, TRUE);
1382
1383         /* Set the global registers with default ether type value */
1384         if (!pf->support_multi_driver) {
1385                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1386                                          ETHER_TYPE_VLAN);
1387                 if (ret != I40E_SUCCESS) {
1388                         PMD_INIT_LOG(ERR,
1389                                      "Failed to set the default outer "
1390                                      "VLAN ether type");
1391                         goto err_setup_pf_switch;
1392                 }
1393         }
1394
1395         /* PF setup, which includes VSI setup */
1396         ret = i40e_pf_setup(pf);
1397         if (ret) {
1398                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1399                 goto err_setup_pf_switch;
1400         }
1401
1402         /* reset all stats of the device, including pf and main vsi */
1403         i40e_dev_stats_reset(dev);
1404
1405         vsi = pf->main_vsi;
1406
1407         /* Disable double vlan by default */
1408         i40e_vsi_config_double_vlan(vsi, FALSE);
1409
1410         /* Disable S-TAG identification when floating_veb is disabled */
1411         if (!pf->floating_veb) {
1412                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1413                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1414                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1415                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1416                 }
1417         }
1418
1419         if (!vsi->max_macaddrs)
1420                 len = ETHER_ADDR_LEN;
1421         else
1422                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1423
1424         /* Should be after VSI initialized */
1425         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1426         if (!dev->data->mac_addrs) {
1427                 PMD_INIT_LOG(ERR,
1428                         "Failed to allocated memory for storing mac address");
1429                 goto err_mac_alloc;
1430         }
1431         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1432                                         &dev->data->mac_addrs[0]);
1433
1434         /* Init dcb to sw mode by default */
1435         ret = i40e_dcb_init_configure(dev, TRUE);
1436         if (ret != I40E_SUCCESS) {
1437                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1438                 pf->flags &= ~I40E_FLAG_DCB;
1439         }
1440         /* Update HW struct after DCB configuration */
1441         i40e_get_cap(hw);
1442
1443         /* initialize pf host driver to setup SRIOV resource if applicable */
1444         i40e_pf_host_init(dev);
1445
1446         /* register callback func to eal lib */
1447         rte_intr_callback_register(intr_handle,
1448                                    i40e_dev_interrupt_handler, dev);
1449
1450         /* configure and enable device interrupt */
1451         i40e_pf_config_irq0(hw, TRUE);
1452         i40e_pf_enable_irq0(hw);
1453
1454         /* enable uio intr after callback register */
1455         rte_intr_enable(intr_handle);
1456
1457         /* By default disable flexible payload in global configuration */
1458         if (!pf->support_multi_driver)
1459                 i40e_flex_payload_reg_set_default(hw);
1460
1461         /*
1462          * Add an ethertype filter to drop all flow control frames transmitted
1463          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1464          * frames to wire.
1465          */
1466         i40e_add_tx_flow_control_drop_filter(pf);
1467
1468         /* Set the max frame size to 0x2600 by default,
1469          * in case other drivers changed the default value.
1470          */
1471         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1472
1473         /* initialize mirror rule list */
1474         TAILQ_INIT(&pf->mirror_list);
1475
1476         /* initialize Traffic Manager configuration */
1477         i40e_tm_conf_init(dev);
1478
1479         /* Initialize customized information */
1480         i40e_init_customized_info(pf);
1481
1482         ret = i40e_init_ethtype_filter_list(dev);
1483         if (ret < 0)
1484                 goto err_init_ethtype_filter_list;
1485         ret = i40e_init_tunnel_filter_list(dev);
1486         if (ret < 0)
1487                 goto err_init_tunnel_filter_list;
1488         ret = i40e_init_fdir_filter_list(dev);
1489         if (ret < 0)
1490                 goto err_init_fdir_filter_list;
1491
1492         /* initialize queue region configuration */
1493         i40e_init_queue_region_conf(dev);
1494
1495         /* initialize rss configuration from rte_flow */
1496         memset(&pf->rss_info, 0,
1497                 sizeof(struct i40e_rte_flow_rss_conf));
1498
1499         return 0;
1500
1501 err_init_fdir_filter_list:
1502         rte_free(pf->tunnel.hash_table);
1503         rte_free(pf->tunnel.hash_map);
1504 err_init_tunnel_filter_list:
1505         rte_free(pf->ethertype.hash_table);
1506         rte_free(pf->ethertype.hash_map);
1507 err_init_ethtype_filter_list:
1508         rte_free(dev->data->mac_addrs);
1509 err_mac_alloc:
1510         i40e_vsi_release(pf->main_vsi);
1511 err_setup_pf_switch:
1512 err_get_mac_addr:
1513 err_configure_lan_hmc:
1514         (void)i40e_shutdown_lan_hmc(hw);
1515 err_init_lan_hmc:
1516         i40e_res_pool_destroy(&pf->msix_pool);
1517 err_msix_pool_init:
1518         i40e_res_pool_destroy(&pf->qp_pool);
1519 err_qp_pool_init:
1520 err_parameter_init:
1521 err_get_capabilities:
1522         (void)i40e_shutdown_adminq(hw);
1523
1524         return ret;
1525 }
1526
1527 static void
1528 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1529 {
1530         struct i40e_ethertype_filter *p_ethertype;
1531         struct i40e_ethertype_rule *ethertype_rule;
1532
1533         ethertype_rule = &pf->ethertype;
1534         /* Remove all ethertype filter rules and hash */
1535         if (ethertype_rule->hash_map)
1536                 rte_free(ethertype_rule->hash_map);
1537         if (ethertype_rule->hash_table)
1538                 rte_hash_free(ethertype_rule->hash_table);
1539
1540         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1541                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1542                              p_ethertype, rules);
1543                 rte_free(p_ethertype);
1544         }
1545 }
1546
1547 static void
1548 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1549 {
1550         struct i40e_tunnel_filter *p_tunnel;
1551         struct i40e_tunnel_rule *tunnel_rule;
1552
1553         tunnel_rule = &pf->tunnel;
1554         /* Remove all tunnel director rules and hash */
1555         if (tunnel_rule->hash_map)
1556                 rte_free(tunnel_rule->hash_map);
1557         if (tunnel_rule->hash_table)
1558                 rte_hash_free(tunnel_rule->hash_table);
1559
1560         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1561                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1562                 rte_free(p_tunnel);
1563         }
1564 }
1565
1566 static void
1567 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1568 {
1569         struct i40e_fdir_filter *p_fdir;
1570         struct i40e_fdir_info *fdir_info;
1571
1572         fdir_info = &pf->fdir;
1573         /* Remove all flow director rules and hash */
1574         if (fdir_info->hash_map)
1575                 rte_free(fdir_info->hash_map);
1576         if (fdir_info->hash_table)
1577                 rte_hash_free(fdir_info->hash_table);
1578
1579         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1580                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1581                 rte_free(p_fdir);
1582         }
1583 }
1584
1585 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1586 {
1587         /*
1588          * Disable by default flexible payload
1589          * for corresponding L2/L3/L4 layers.
1590          */
1591         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1592         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1593         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1594 }
1595
1596 static int
1597 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1598 {
1599         struct i40e_pf *pf;
1600         struct rte_pci_device *pci_dev;
1601         struct rte_intr_handle *intr_handle;
1602         struct i40e_hw *hw;
1603         struct i40e_filter_control_settings settings;
1604         struct rte_flow *p_flow;
1605         int ret;
1606         uint8_t aq_fail = 0;
1607         int retries = 0;
1608
1609         PMD_INIT_FUNC_TRACE();
1610
1611         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1612                 return 0;
1613
1614         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1615         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1616         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1617         intr_handle = &pci_dev->intr_handle;
1618
1619         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1620         if (ret)
1621                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1622
1623         if (hw->adapter_stopped == 0)
1624                 i40e_dev_close(dev);
1625
1626         dev->dev_ops = NULL;
1627         dev->rx_pkt_burst = NULL;
1628         dev->tx_pkt_burst = NULL;
1629
1630         /* Clear PXE mode */
1631         i40e_clear_pxe_mode(hw);
1632
1633         /* Unconfigure filter control */
1634         memset(&settings, 0, sizeof(settings));
1635         ret = i40e_set_filter_control(hw, &settings);
1636         if (ret)
1637                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1638                                         ret);
1639
1640         /* Disable flow control */
1641         hw->fc.requested_mode = I40E_FC_NONE;
1642         i40e_set_fc(hw, &aq_fail, TRUE);
1643
1644         /* uninitialize pf host driver */
1645         i40e_pf_host_uninit(dev);
1646
1647         rte_free(dev->data->mac_addrs);
1648         dev->data->mac_addrs = NULL;
1649
1650         /* disable uio intr before callback unregister */
1651         rte_intr_disable(intr_handle);
1652
1653         /* unregister callback func to eal lib */
1654         do {
1655                 ret = rte_intr_callback_unregister(intr_handle,
1656                                 i40e_dev_interrupt_handler, dev);
1657                 if (ret >= 0) {
1658                         break;
1659                 } else if (ret != -EAGAIN) {
1660                         PMD_INIT_LOG(ERR,
1661                                  "intr callback unregister failed: %d",
1662                                  ret);
1663                         return ret;
1664                 }
1665                 i40e_msec_delay(500);
1666         } while (retries++ < 5);
1667
1668         i40e_rm_ethtype_filter_list(pf);
1669         i40e_rm_tunnel_filter_list(pf);
1670         i40e_rm_fdir_filter_list(pf);
1671
1672         /* Remove all flows */
1673         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1674                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1675                 rte_free(p_flow);
1676         }
1677
1678         /* Remove all Traffic Manager configuration */
1679         i40e_tm_conf_uninit(dev);
1680
1681         return 0;
1682 }
1683
1684 static int
1685 i40e_dev_configure(struct rte_eth_dev *dev)
1686 {
1687         struct i40e_adapter *ad =
1688                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1689         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1690         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1691         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1692         int i, ret;
1693
1694         ret = i40e_dev_sync_phy_type(hw);
1695         if (ret)
1696                 return ret;
1697
1698         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1699          * bulk allocation or vector Rx preconditions we will reset it.
1700          */
1701         ad->rx_bulk_alloc_allowed = true;
1702         ad->rx_vec_allowed = true;
1703         ad->tx_simple_allowed = true;
1704         ad->tx_vec_allowed = true;
1705
1706         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1707                 ret = i40e_fdir_setup(pf);
1708                 if (ret != I40E_SUCCESS) {
1709                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1710                         return -ENOTSUP;
1711                 }
1712                 ret = i40e_fdir_configure(dev);
1713                 if (ret < 0) {
1714                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1715                         goto err;
1716                 }
1717         } else
1718                 i40e_fdir_teardown(pf);
1719
1720         ret = i40e_dev_init_vlan(dev);
1721         if (ret < 0)
1722                 goto err;
1723
1724         /* VMDQ setup.
1725          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1726          *  RSS setting have different requirements.
1727          *  General PMD driver call sequence are NIC init, configure,
1728          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1729          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1730          *  applicable. So, VMDQ setting has to be done before
1731          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1732          *  For RSS setting, it will try to calculate actual configured RX queue
1733          *  number, which will be available after rx_queue_setup(). dev_start()
1734          *  function is good to place RSS setup.
1735          */
1736         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1737                 ret = i40e_vmdq_setup(dev);
1738                 if (ret)
1739                         goto err;
1740         }
1741
1742         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1743                 ret = i40e_dcb_setup(dev);
1744                 if (ret) {
1745                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1746                         goto err_dcb;
1747                 }
1748         }
1749
1750         TAILQ_INIT(&pf->flow_list);
1751
1752         return 0;
1753
1754 err_dcb:
1755         /* need to release vmdq resource if exists */
1756         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1757                 i40e_vsi_release(pf->vmdq[i].vsi);
1758                 pf->vmdq[i].vsi = NULL;
1759         }
1760         rte_free(pf->vmdq);
1761         pf->vmdq = NULL;
1762 err:
1763         /* need to release fdir resource if exists */
1764         i40e_fdir_teardown(pf);
1765         return ret;
1766 }
1767
1768 void
1769 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1770 {
1771         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1772         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1773         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1774         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1775         uint16_t msix_vect = vsi->msix_intr;
1776         uint16_t i;
1777
1778         for (i = 0; i < vsi->nb_qps; i++) {
1779                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1780                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1781                 rte_wmb();
1782         }
1783
1784         if (vsi->type != I40E_VSI_SRIOV) {
1785                 if (!rte_intr_allow_others(intr_handle)) {
1786                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1787                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1788                         I40E_WRITE_REG(hw,
1789                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1790                                        0);
1791                 } else {
1792                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1793                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1794                         I40E_WRITE_REG(hw,
1795                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1796                                                        msix_vect - 1), 0);
1797                 }
1798         } else {
1799                 uint32_t reg;
1800                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1801                         vsi->user_param + (msix_vect - 1);
1802
1803                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1804                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1805         }
1806         I40E_WRITE_FLUSH(hw);
1807 }
1808
1809 static void
1810 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1811                        int base_queue, int nb_queue,
1812                        uint16_t itr_idx)
1813 {
1814         int i;
1815         uint32_t val;
1816         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1817         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1818
1819         /* Bind all RX queues to allocated MSIX interrupt */
1820         for (i = 0; i < nb_queue; i++) {
1821                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1822                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1823                         ((base_queue + i + 1) <<
1824                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1825                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1826                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1827
1828                 if (i == nb_queue - 1)
1829                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1830                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1831         }
1832
1833         /* Write first RX queue to Link list register as the head element */
1834         if (vsi->type != I40E_VSI_SRIOV) {
1835                 uint16_t interval =
1836                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1837
1838                 if (msix_vect == I40E_MISC_VEC_ID) {
1839                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1840                                        (base_queue <<
1841                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1842                                        (0x0 <<
1843                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1844                         I40E_WRITE_REG(hw,
1845                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1846                                        interval);
1847                 } else {
1848                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1849                                        (base_queue <<
1850                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1851                                        (0x0 <<
1852                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1853                         I40E_WRITE_REG(hw,
1854                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1855                                                        msix_vect - 1),
1856                                        interval);
1857                 }
1858         } else {
1859                 uint32_t reg;
1860
1861                 if (msix_vect == I40E_MISC_VEC_ID) {
1862                         I40E_WRITE_REG(hw,
1863                                        I40E_VPINT_LNKLST0(vsi->user_param),
1864                                        (base_queue <<
1865                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1866                                        (0x0 <<
1867                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1868                 } else {
1869                         /* num_msix_vectors_vf needs to minus irq0 */
1870                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1871                                 vsi->user_param + (msix_vect - 1);
1872
1873                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1874                                        (base_queue <<
1875                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1876                                        (0x0 <<
1877                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1878                 }
1879         }
1880
1881         I40E_WRITE_FLUSH(hw);
1882 }
1883
1884 void
1885 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1886 {
1887         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1888         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1889         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1890         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1891         uint16_t msix_vect = vsi->msix_intr;
1892         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1893         uint16_t queue_idx = 0;
1894         int record = 0;
1895         int i;
1896
1897         for (i = 0; i < vsi->nb_qps; i++) {
1898                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1899                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1900         }
1901
1902         /* VF bind interrupt */
1903         if (vsi->type == I40E_VSI_SRIOV) {
1904                 __vsi_queues_bind_intr(vsi, msix_vect,
1905                                        vsi->base_queue, vsi->nb_qps,
1906                                        itr_idx);
1907                 return;
1908         }
1909
1910         /* PF & VMDq bind interrupt */
1911         if (rte_intr_dp_is_en(intr_handle)) {
1912                 if (vsi->type == I40E_VSI_MAIN) {
1913                         queue_idx = 0;
1914                         record = 1;
1915                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1916                         struct i40e_vsi *main_vsi =
1917                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1918                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1919                         record = 1;
1920                 }
1921         }
1922
1923         for (i = 0; i < vsi->nb_used_qps; i++) {
1924                 if (nb_msix <= 1) {
1925                         if (!rte_intr_allow_others(intr_handle))
1926                                 /* allow to share MISC_VEC_ID */
1927                                 msix_vect = I40E_MISC_VEC_ID;
1928
1929                         /* no enough msix_vect, map all to one */
1930                         __vsi_queues_bind_intr(vsi, msix_vect,
1931                                                vsi->base_queue + i,
1932                                                vsi->nb_used_qps - i,
1933                                                itr_idx);
1934                         for (; !!record && i < vsi->nb_used_qps; i++)
1935                                 intr_handle->intr_vec[queue_idx + i] =
1936                                         msix_vect;
1937                         break;
1938                 }
1939                 /* 1:1 queue/msix_vect mapping */
1940                 __vsi_queues_bind_intr(vsi, msix_vect,
1941                                        vsi->base_queue + i, 1,
1942                                        itr_idx);
1943                 if (!!record)
1944                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1945
1946                 msix_vect++;
1947                 nb_msix--;
1948         }
1949 }
1950
1951 static void
1952 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1953 {
1954         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1955         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1956         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1957         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1958         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1959         uint16_t msix_intr, i;
1960
1961         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1962                 for (i = 0; i < vsi->nb_msix; i++) {
1963                         msix_intr = vsi->msix_intr + i;
1964                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1965                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1966                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1967                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1968                 }
1969         else
1970                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1971                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1972                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1973                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1974
1975         I40E_WRITE_FLUSH(hw);
1976 }
1977
1978 static void
1979 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1980 {
1981         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1982         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1983         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1984         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1985         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1986         uint16_t msix_intr, i;
1987
1988         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1989                 for (i = 0; i < vsi->nb_msix; i++) {
1990                         msix_intr = vsi->msix_intr + i;
1991                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1992                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1993                 }
1994         else
1995                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1996                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1997
1998         I40E_WRITE_FLUSH(hw);
1999 }
2000
2001 static inline uint8_t
2002 i40e_parse_link_speeds(uint16_t link_speeds)
2003 {
2004         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2005
2006         if (link_speeds & ETH_LINK_SPEED_40G)
2007                 link_speed |= I40E_LINK_SPEED_40GB;
2008         if (link_speeds & ETH_LINK_SPEED_25G)
2009                 link_speed |= I40E_LINK_SPEED_25GB;
2010         if (link_speeds & ETH_LINK_SPEED_20G)
2011                 link_speed |= I40E_LINK_SPEED_20GB;
2012         if (link_speeds & ETH_LINK_SPEED_10G)
2013                 link_speed |= I40E_LINK_SPEED_10GB;
2014         if (link_speeds & ETH_LINK_SPEED_1G)
2015                 link_speed |= I40E_LINK_SPEED_1GB;
2016         if (link_speeds & ETH_LINK_SPEED_100M)
2017                 link_speed |= I40E_LINK_SPEED_100MB;
2018
2019         return link_speed;
2020 }
2021
2022 static int
2023 i40e_phy_conf_link(struct i40e_hw *hw,
2024                    uint8_t abilities,
2025                    uint8_t force_speed,
2026                    bool is_up)
2027 {
2028         enum i40e_status_code status;
2029         struct i40e_aq_get_phy_abilities_resp phy_ab;
2030         struct i40e_aq_set_phy_config phy_conf;
2031         enum i40e_aq_phy_type cnt;
2032         uint32_t phy_type_mask = 0;
2033
2034         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2035                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2036                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2037                         I40E_AQ_PHY_FLAG_LOW_POWER;
2038         const uint8_t advt = I40E_LINK_SPEED_40GB |
2039                         I40E_LINK_SPEED_25GB |
2040                         I40E_LINK_SPEED_10GB |
2041                         I40E_LINK_SPEED_1GB |
2042                         I40E_LINK_SPEED_100MB;
2043         int ret = -ENOTSUP;
2044
2045
2046         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2047                                               NULL);
2048         if (status)
2049                 return ret;
2050
2051         /* If link already up, no need to set up again */
2052         if (is_up && phy_ab.phy_type != 0)
2053                 return I40E_SUCCESS;
2054
2055         memset(&phy_conf, 0, sizeof(phy_conf));
2056
2057         /* bits 0-2 use the values from get_phy_abilities_resp */
2058         abilities &= ~mask;
2059         abilities |= phy_ab.abilities & mask;
2060
2061         /* update ablities and speed */
2062         if (abilities & I40E_AQ_PHY_AN_ENABLED)
2063                 phy_conf.link_speed = advt;
2064         else
2065                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
2066
2067         phy_conf.abilities = abilities;
2068
2069
2070
2071         /* PHY type mask needs to include each type except PHY type extension */
2072         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2073                 phy_type_mask |= 1 << cnt;
2074
2075         /* use get_phy_abilities_resp value for the rest */
2076         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2077         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2078                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2079                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2080         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2081         phy_conf.eee_capability = phy_ab.eee_capability;
2082         phy_conf.eeer = phy_ab.eeer_val;
2083         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2084
2085         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2086                     phy_ab.abilities, phy_ab.link_speed);
2087         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2088                     phy_conf.abilities, phy_conf.link_speed);
2089
2090         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2091         if (status)
2092                 return ret;
2093
2094         return I40E_SUCCESS;
2095 }
2096
2097 static int
2098 i40e_apply_link_speed(struct rte_eth_dev *dev)
2099 {
2100         uint8_t speed;
2101         uint8_t abilities = 0;
2102         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103         struct rte_eth_conf *conf = &dev->data->dev_conf;
2104
2105         speed = i40e_parse_link_speeds(conf->link_speeds);
2106         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2107         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2108                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2109         abilities |= I40E_AQ_PHY_LINK_ENABLED;
2110
2111         return i40e_phy_conf_link(hw, abilities, speed, true);
2112 }
2113
2114 static int
2115 i40e_dev_start(struct rte_eth_dev *dev)
2116 {
2117         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2118         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2119         struct i40e_vsi *main_vsi = pf->main_vsi;
2120         int ret, i;
2121         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2122         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2123         uint32_t intr_vector = 0;
2124         struct i40e_vsi *vsi;
2125
2126         hw->adapter_stopped = 0;
2127
2128         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2129                 PMD_INIT_LOG(ERR,
2130                 "Invalid link_speeds for port %u, autonegotiation disabled",
2131                               dev->data->port_id);
2132                 return -EINVAL;
2133         }
2134
2135         rte_intr_disable(intr_handle);
2136
2137         if ((rte_intr_cap_multiple(intr_handle) ||
2138              !RTE_ETH_DEV_SRIOV(dev).active) &&
2139             dev->data->dev_conf.intr_conf.rxq != 0) {
2140                 intr_vector = dev->data->nb_rx_queues;
2141                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2142                 if (ret)
2143                         return ret;
2144         }
2145
2146         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2147                 intr_handle->intr_vec =
2148                         rte_zmalloc("intr_vec",
2149                                     dev->data->nb_rx_queues * sizeof(int),
2150                                     0);
2151                 if (!intr_handle->intr_vec) {
2152                         PMD_INIT_LOG(ERR,
2153                                 "Failed to allocate %d rx_queues intr_vec",
2154                                 dev->data->nb_rx_queues);
2155                         return -ENOMEM;
2156                 }
2157         }
2158
2159         /* Initialize VSI */
2160         ret = i40e_dev_rxtx_init(pf);
2161         if (ret != I40E_SUCCESS) {
2162                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2163                 goto err_up;
2164         }
2165
2166         /* Map queues with MSIX interrupt */
2167         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2168                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2169         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2170         i40e_vsi_enable_queues_intr(main_vsi);
2171
2172         /* Map VMDQ VSI queues with MSIX interrupt */
2173         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2174                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2175                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2176                                           I40E_ITR_INDEX_DEFAULT);
2177                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2178         }
2179
2180         /* enable FDIR MSIX interrupt */
2181         if (pf->fdir.fdir_vsi) {
2182                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2183                                           I40E_ITR_INDEX_NONE);
2184                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2185         }
2186
2187         /* Enable all queues which have been configured */
2188         ret = i40e_dev_switch_queues(pf, TRUE);
2189         if (ret != I40E_SUCCESS) {
2190                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2191                 goto err_up;
2192         }
2193
2194         /* Enable receiving broadcast packets */
2195         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2196         if (ret != I40E_SUCCESS)
2197                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2198
2199         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2200                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2201                                                 true, NULL);
2202                 if (ret != I40E_SUCCESS)
2203                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2204         }
2205
2206         /* Enable the VLAN promiscuous mode. */
2207         if (pf->vfs) {
2208                 for (i = 0; i < pf->vf_num; i++) {
2209                         vsi = pf->vfs[i].vsi;
2210                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2211                                                      true, NULL);
2212                 }
2213         }
2214
2215         /* Enable mac loopback mode */
2216         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2217             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2218                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2219                 if (ret != I40E_SUCCESS) {
2220                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2221                         goto err_up;
2222                 }
2223         }
2224
2225         /* Apply link configure */
2226         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2227                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2228                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2229                                 ETH_LINK_SPEED_40G)) {
2230                 PMD_DRV_LOG(ERR, "Invalid link setting");
2231                 goto err_up;
2232         }
2233         ret = i40e_apply_link_speed(dev);
2234         if (I40E_SUCCESS != ret) {
2235                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2236                 goto err_up;
2237         }
2238
2239         if (!rte_intr_allow_others(intr_handle)) {
2240                 rte_intr_callback_unregister(intr_handle,
2241                                              i40e_dev_interrupt_handler,
2242                                              (void *)dev);
2243                 /* configure and enable device interrupt */
2244                 i40e_pf_config_irq0(hw, FALSE);
2245                 i40e_pf_enable_irq0(hw);
2246
2247                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2248                         PMD_INIT_LOG(INFO,
2249                                 "lsc won't enable because of no intr multiplex");
2250         } else {
2251                 ret = i40e_aq_set_phy_int_mask(hw,
2252                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2253                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2254                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2255                 if (ret != I40E_SUCCESS)
2256                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2257
2258                 /* Call get_link_info aq commond to enable/disable LSE */
2259                 i40e_dev_link_update(dev, 0);
2260         }
2261
2262         /* enable uio intr after callback register */
2263         rte_intr_enable(intr_handle);
2264
2265         i40e_filter_restore(pf);
2266
2267         if (pf->tm_conf.root && !pf->tm_conf.committed)
2268                 PMD_DRV_LOG(WARNING,
2269                             "please call hierarchy_commit() "
2270                             "before starting the port");
2271
2272         return I40E_SUCCESS;
2273
2274 err_up:
2275         i40e_dev_switch_queues(pf, FALSE);
2276         i40e_dev_clear_queues(dev);
2277
2278         return ret;
2279 }
2280
2281 static void
2282 i40e_dev_stop(struct rte_eth_dev *dev)
2283 {
2284         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2285         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2286         struct i40e_vsi *main_vsi = pf->main_vsi;
2287         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2288         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2289         int i;
2290
2291         if (hw->adapter_stopped == 1)
2292                 return;
2293         /* Disable all queues */
2294         i40e_dev_switch_queues(pf, FALSE);
2295
2296         /* un-map queues with interrupt registers */
2297         i40e_vsi_disable_queues_intr(main_vsi);
2298         i40e_vsi_queues_unbind_intr(main_vsi);
2299
2300         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2301                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2302                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2303         }
2304
2305         if (pf->fdir.fdir_vsi) {
2306                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2307                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2308         }
2309         /* Clear all queues and release memory */
2310         i40e_dev_clear_queues(dev);
2311
2312         /* Set link down */
2313         i40e_dev_set_link_down(dev);
2314
2315         if (!rte_intr_allow_others(intr_handle))
2316                 /* resume to the default handler */
2317                 rte_intr_callback_register(intr_handle,
2318                                            i40e_dev_interrupt_handler,
2319                                            (void *)dev);
2320
2321         /* Clean datapath event and queue/vec mapping */
2322         rte_intr_efd_disable(intr_handle);
2323         if (intr_handle->intr_vec) {
2324                 rte_free(intr_handle->intr_vec);
2325                 intr_handle->intr_vec = NULL;
2326         }
2327
2328         /* reset hierarchy commit */
2329         pf->tm_conf.committed = false;
2330
2331         hw->adapter_stopped = 1;
2332 }
2333
2334 static void
2335 i40e_dev_close(struct rte_eth_dev *dev)
2336 {
2337         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2338         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2339         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2340         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2341         struct i40e_mirror_rule *p_mirror;
2342         uint32_t reg;
2343         int i;
2344         int ret;
2345
2346         PMD_INIT_FUNC_TRACE();
2347
2348         i40e_dev_stop(dev);
2349
2350         /* Remove all mirror rules */
2351         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2352                 ret = i40e_aq_del_mirror_rule(hw,
2353                                               pf->main_vsi->veb->seid,
2354                                               p_mirror->rule_type,
2355                                               p_mirror->entries,
2356                                               p_mirror->num_entries,
2357                                               p_mirror->id);
2358                 if (ret < 0)
2359                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2360                                     "status = %d, aq_err = %d.", ret,
2361                                     hw->aq.asq_last_status);
2362
2363                 /* remove mirror software resource anyway */
2364                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2365                 rte_free(p_mirror);
2366                 pf->nb_mirror_rule--;
2367         }
2368
2369         i40e_dev_free_queues(dev);
2370
2371         /* Disable interrupt */
2372         i40e_pf_disable_irq0(hw);
2373         rte_intr_disable(intr_handle);
2374
2375         i40e_fdir_teardown(pf);
2376
2377         /* shutdown and destroy the HMC */
2378         i40e_shutdown_lan_hmc(hw);
2379
2380         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2381                 i40e_vsi_release(pf->vmdq[i].vsi);
2382                 pf->vmdq[i].vsi = NULL;
2383         }
2384         rte_free(pf->vmdq);
2385         pf->vmdq = NULL;
2386
2387         /* release all the existing VSIs and VEBs */
2388         i40e_vsi_release(pf->main_vsi);
2389
2390         /* shutdown the adminq */
2391         i40e_aq_queue_shutdown(hw, true);
2392         i40e_shutdown_adminq(hw);
2393
2394         i40e_res_pool_destroy(&pf->qp_pool);
2395         i40e_res_pool_destroy(&pf->msix_pool);
2396
2397         /* Disable flexible payload in global configuration */
2398         if (!pf->support_multi_driver)
2399                 i40e_flex_payload_reg_set_default(hw);
2400
2401         /* force a PF reset to clean anything leftover */
2402         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2403         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2404                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2405         I40E_WRITE_FLUSH(hw);
2406 }
2407
2408 /*
2409  * Reset PF device only to re-initialize resources in PMD layer
2410  */
2411 static int
2412 i40e_dev_reset(struct rte_eth_dev *dev)
2413 {
2414         int ret;
2415
2416         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2417          * its VF to make them align with it. The detailed notification
2418          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2419          * To avoid unexpected behavior in VF, currently reset of PF with
2420          * SR-IOV activation is not supported. It might be supported later.
2421          */
2422         if (dev->data->sriov.active)
2423                 return -ENOTSUP;
2424
2425         ret = eth_i40e_dev_uninit(dev);
2426         if (ret)
2427                 return ret;
2428
2429         ret = eth_i40e_dev_init(dev, NULL);
2430
2431         return ret;
2432 }
2433
2434 static void
2435 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2436 {
2437         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2438         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439         struct i40e_vsi *vsi = pf->main_vsi;
2440         int status;
2441
2442         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2443                                                      true, NULL, true);
2444         if (status != I40E_SUCCESS)
2445                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2446
2447         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2448                                                         TRUE, NULL);
2449         if (status != I40E_SUCCESS)
2450                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2451
2452 }
2453
2454 static void
2455 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2456 {
2457         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2458         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2459         struct i40e_vsi *vsi = pf->main_vsi;
2460         int status;
2461
2462         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2463                                                      false, NULL, true);
2464         if (status != I40E_SUCCESS)
2465                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2466
2467         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2468                                                         false, NULL);
2469         if (status != I40E_SUCCESS)
2470                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2471 }
2472
2473 static void
2474 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2475 {
2476         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2477         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2478         struct i40e_vsi *vsi = pf->main_vsi;
2479         int ret;
2480
2481         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2482         if (ret != I40E_SUCCESS)
2483                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2484 }
2485
2486 static void
2487 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2488 {
2489         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2490         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2491         struct i40e_vsi *vsi = pf->main_vsi;
2492         int ret;
2493
2494         if (dev->data->promiscuous == 1)
2495                 return; /* must remain in all_multicast mode */
2496
2497         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2498                                 vsi->seid, FALSE, NULL);
2499         if (ret != I40E_SUCCESS)
2500                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2501 }
2502
2503 /*
2504  * Set device link up.
2505  */
2506 static int
2507 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2508 {
2509         /* re-apply link speed setting */
2510         return i40e_apply_link_speed(dev);
2511 }
2512
2513 /*
2514  * Set device link down.
2515  */
2516 static int
2517 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2518 {
2519         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2520         uint8_t abilities = 0;
2521         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2522
2523         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2524         return i40e_phy_conf_link(hw, abilities, speed, false);
2525 }
2526
2527 static __rte_always_inline void
2528 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2529 {
2530 /* Link status registers and values*/
2531 #define I40E_PRTMAC_LINKSTA             0x001E2420
2532 #define I40E_REG_LINK_UP                0x40000080
2533 #define I40E_PRTMAC_MACC                0x001E24E0
2534 #define I40E_REG_MACC_25GB              0x00020000
2535 #define I40E_REG_SPEED_MASK             0x38000000
2536 #define I40E_REG_SPEED_100MB            0x00000000
2537 #define I40E_REG_SPEED_1GB              0x08000000
2538 #define I40E_REG_SPEED_10GB             0x10000000
2539 #define I40E_REG_SPEED_20GB             0x20000000
2540 #define I40E_REG_SPEED_25_40GB          0x18000000
2541         uint32_t link_speed;
2542         uint32_t reg_val;
2543
2544         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2545         link_speed = reg_val & I40E_REG_SPEED_MASK;
2546         reg_val &= I40E_REG_LINK_UP;
2547         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2548
2549         if (unlikely(link->link_status == 0))
2550                 return;
2551
2552         /* Parse the link status */
2553         switch (link_speed) {
2554         case I40E_REG_SPEED_100MB:
2555                 link->link_speed = ETH_SPEED_NUM_100M;
2556                 break;
2557         case I40E_REG_SPEED_1GB:
2558                 link->link_speed = ETH_SPEED_NUM_1G;
2559                 break;
2560         case I40E_REG_SPEED_10GB:
2561                 link->link_speed = ETH_SPEED_NUM_10G;
2562                 break;
2563         case I40E_REG_SPEED_20GB:
2564                 link->link_speed = ETH_SPEED_NUM_20G;
2565                 break;
2566         case I40E_REG_SPEED_25_40GB:
2567                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2568
2569                 if (reg_val & I40E_REG_MACC_25GB)
2570                         link->link_speed = ETH_SPEED_NUM_25G;
2571                 else
2572                         link->link_speed = ETH_SPEED_NUM_40G;
2573
2574                 break;
2575         default:
2576                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2577                 break;
2578         }
2579 }
2580
2581 static __rte_always_inline void
2582 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2583         bool enable_lse, int wait_to_complete)
2584 {
2585 #define CHECK_INTERVAL             100  /* 100ms */
2586 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2587         uint32_t rep_cnt = MAX_REPEAT_TIME;
2588         struct i40e_link_status link_status;
2589         int status;
2590
2591         memset(&link_status, 0, sizeof(link_status));
2592
2593         do {
2594                 memset(&link_status, 0, sizeof(link_status));
2595
2596                 /* Get link status information from hardware */
2597                 status = i40e_aq_get_link_info(hw, enable_lse,
2598                                                 &link_status, NULL);
2599                 if (unlikely(status != I40E_SUCCESS)) {
2600                         link->link_speed = ETH_SPEED_NUM_100M;
2601                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2602                         PMD_DRV_LOG(ERR, "Failed to get link info");
2603                         return;
2604                 }
2605
2606                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2607                 if (!wait_to_complete || link->link_status)
2608                         break;
2609
2610                 rte_delay_ms(CHECK_INTERVAL);
2611         } while (--rep_cnt);
2612
2613         /* Parse the link status */
2614         switch (link_status.link_speed) {
2615         case I40E_LINK_SPEED_100MB:
2616                 link->link_speed = ETH_SPEED_NUM_100M;
2617                 break;
2618         case I40E_LINK_SPEED_1GB:
2619                 link->link_speed = ETH_SPEED_NUM_1G;
2620                 break;
2621         case I40E_LINK_SPEED_10GB:
2622                 link->link_speed = ETH_SPEED_NUM_10G;
2623                 break;
2624         case I40E_LINK_SPEED_20GB:
2625                 link->link_speed = ETH_SPEED_NUM_20G;
2626                 break;
2627         case I40E_LINK_SPEED_25GB:
2628                 link->link_speed = ETH_SPEED_NUM_25G;
2629                 break;
2630         case I40E_LINK_SPEED_40GB:
2631                 link->link_speed = ETH_SPEED_NUM_40G;
2632                 break;
2633         default:
2634                 link->link_speed = ETH_SPEED_NUM_100M;
2635                 break;
2636         }
2637 }
2638
2639 int
2640 i40e_dev_link_update(struct rte_eth_dev *dev,
2641                      int wait_to_complete)
2642 {
2643         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2644         struct rte_eth_link link;
2645         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2646         int ret;
2647
2648         memset(&link, 0, sizeof(link));
2649
2650         /* i40e uses full duplex only */
2651         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2652         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2653                         ETH_LINK_SPEED_FIXED);
2654
2655         if (!wait_to_complete && !enable_lse)
2656                 update_link_reg(hw, &link);
2657         else
2658                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2659
2660         ret = rte_eth_linkstatus_set(dev, &link);
2661         i40e_notify_all_vfs_link_status(dev);
2662
2663         return ret;
2664 }
2665
2666 /* Get all the statistics of a VSI */
2667 void
2668 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2669 {
2670         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2671         struct i40e_eth_stats *nes = &vsi->eth_stats;
2672         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2673         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2674
2675         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2676                             vsi->offset_loaded, &oes->rx_bytes,
2677                             &nes->rx_bytes);
2678         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2679                             vsi->offset_loaded, &oes->rx_unicast,
2680                             &nes->rx_unicast);
2681         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2682                             vsi->offset_loaded, &oes->rx_multicast,
2683                             &nes->rx_multicast);
2684         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2685                             vsi->offset_loaded, &oes->rx_broadcast,
2686                             &nes->rx_broadcast);
2687         /* exclude CRC bytes */
2688         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2689                 nes->rx_broadcast) * ETHER_CRC_LEN;
2690
2691         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2692                             &oes->rx_discards, &nes->rx_discards);
2693         /* GLV_REPC not supported */
2694         /* GLV_RMPC not supported */
2695         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2696                             &oes->rx_unknown_protocol,
2697                             &nes->rx_unknown_protocol);
2698         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2699                             vsi->offset_loaded, &oes->tx_bytes,
2700                             &nes->tx_bytes);
2701         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2702                             vsi->offset_loaded, &oes->tx_unicast,
2703                             &nes->tx_unicast);
2704         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2705                             vsi->offset_loaded, &oes->tx_multicast,
2706                             &nes->tx_multicast);
2707         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2708                             vsi->offset_loaded,  &oes->tx_broadcast,
2709                             &nes->tx_broadcast);
2710         /* GLV_TDPC not supported */
2711         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2712                             &oes->tx_errors, &nes->tx_errors);
2713         vsi->offset_loaded = true;
2714
2715         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2716                     vsi->vsi_id);
2717         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2718         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2719         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2720         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2721         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2722         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2723                     nes->rx_unknown_protocol);
2724         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2725         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2726         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2727         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2728         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2729         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2730         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2731                     vsi->vsi_id);
2732 }
2733
2734 static void
2735 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2736 {
2737         unsigned int i;
2738         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2739         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2740
2741         /* Get rx/tx bytes of internal transfer packets */
2742         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2743                         I40E_GLV_GORCL(hw->port),
2744                         pf->offset_loaded,
2745                         &pf->internal_stats_offset.rx_bytes,
2746                         &pf->internal_stats.rx_bytes);
2747
2748         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2749                         I40E_GLV_GOTCL(hw->port),
2750                         pf->offset_loaded,
2751                         &pf->internal_stats_offset.tx_bytes,
2752                         &pf->internal_stats.tx_bytes);
2753         /* Get total internal rx packet count */
2754         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2755                             I40E_GLV_UPRCL(hw->port),
2756                             pf->offset_loaded,
2757                             &pf->internal_stats_offset.rx_unicast,
2758                             &pf->internal_stats.rx_unicast);
2759         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2760                             I40E_GLV_MPRCL(hw->port),
2761                             pf->offset_loaded,
2762                             &pf->internal_stats_offset.rx_multicast,
2763                             &pf->internal_stats.rx_multicast);
2764         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2765                             I40E_GLV_BPRCL(hw->port),
2766                             pf->offset_loaded,
2767                             &pf->internal_stats_offset.rx_broadcast,
2768                             &pf->internal_stats.rx_broadcast);
2769         /* Get total internal tx packet count */
2770         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2771                             I40E_GLV_UPTCL(hw->port),
2772                             pf->offset_loaded,
2773                             &pf->internal_stats_offset.tx_unicast,
2774                             &pf->internal_stats.tx_unicast);
2775         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2776                             I40E_GLV_MPTCL(hw->port),
2777                             pf->offset_loaded,
2778                             &pf->internal_stats_offset.tx_multicast,
2779                             &pf->internal_stats.tx_multicast);
2780         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2781                             I40E_GLV_BPTCL(hw->port),
2782                             pf->offset_loaded,
2783                             &pf->internal_stats_offset.tx_broadcast,
2784                             &pf->internal_stats.tx_broadcast);
2785
2786         /* exclude CRC size */
2787         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2788                 pf->internal_stats.rx_multicast +
2789                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2790
2791         /* Get statistics of struct i40e_eth_stats */
2792         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2793                             I40E_GLPRT_GORCL(hw->port),
2794                             pf->offset_loaded, &os->eth.rx_bytes,
2795                             &ns->eth.rx_bytes);
2796         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2797                             I40E_GLPRT_UPRCL(hw->port),
2798                             pf->offset_loaded, &os->eth.rx_unicast,
2799                             &ns->eth.rx_unicast);
2800         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2801                             I40E_GLPRT_MPRCL(hw->port),
2802                             pf->offset_loaded, &os->eth.rx_multicast,
2803                             &ns->eth.rx_multicast);
2804         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2805                             I40E_GLPRT_BPRCL(hw->port),
2806                             pf->offset_loaded, &os->eth.rx_broadcast,
2807                             &ns->eth.rx_broadcast);
2808         /* Workaround: CRC size should not be included in byte statistics,
2809          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2810          */
2811         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2812                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2813
2814         /* exclude internal rx bytes
2815          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2816          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2817          * value.
2818          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2819          */
2820         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2821                 ns->eth.rx_bytes = 0;
2822         else
2823                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2824
2825         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2826                 ns->eth.rx_unicast = 0;
2827         else
2828                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2829
2830         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2831                 ns->eth.rx_multicast = 0;
2832         else
2833                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2834
2835         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2836                 ns->eth.rx_broadcast = 0;
2837         else
2838                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2839
2840         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2841                             pf->offset_loaded, &os->eth.rx_discards,
2842                             &ns->eth.rx_discards);
2843         /* GLPRT_REPC not supported */
2844         /* GLPRT_RMPC not supported */
2845         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2846                             pf->offset_loaded,
2847                             &os->eth.rx_unknown_protocol,
2848                             &ns->eth.rx_unknown_protocol);
2849         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2850                             I40E_GLPRT_GOTCL(hw->port),
2851                             pf->offset_loaded, &os->eth.tx_bytes,
2852                             &ns->eth.tx_bytes);
2853         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2854                             I40E_GLPRT_UPTCL(hw->port),
2855                             pf->offset_loaded, &os->eth.tx_unicast,
2856                             &ns->eth.tx_unicast);
2857         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2858                             I40E_GLPRT_MPTCL(hw->port),
2859                             pf->offset_loaded, &os->eth.tx_multicast,
2860                             &ns->eth.tx_multicast);
2861         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2862                             I40E_GLPRT_BPTCL(hw->port),
2863                             pf->offset_loaded, &os->eth.tx_broadcast,
2864                             &ns->eth.tx_broadcast);
2865         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2866                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2867
2868         /* exclude internal tx bytes
2869          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2870          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2871          * value.
2872          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2873          */
2874         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2875                 ns->eth.tx_bytes = 0;
2876         else
2877                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2878
2879         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2880                 ns->eth.tx_unicast = 0;
2881         else
2882                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2883
2884         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2885                 ns->eth.tx_multicast = 0;
2886         else
2887                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2888
2889         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2890                 ns->eth.tx_broadcast = 0;
2891         else
2892                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2893
2894         /* GLPRT_TEPC not supported */
2895
2896         /* additional port specific stats */
2897         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2898                             pf->offset_loaded, &os->tx_dropped_link_down,
2899                             &ns->tx_dropped_link_down);
2900         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2901                             pf->offset_loaded, &os->crc_errors,
2902                             &ns->crc_errors);
2903         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2904                             pf->offset_loaded, &os->illegal_bytes,
2905                             &ns->illegal_bytes);
2906         /* GLPRT_ERRBC not supported */
2907         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2908                             pf->offset_loaded, &os->mac_local_faults,
2909                             &ns->mac_local_faults);
2910         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2911                             pf->offset_loaded, &os->mac_remote_faults,
2912                             &ns->mac_remote_faults);
2913         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2914                             pf->offset_loaded, &os->rx_length_errors,
2915                             &ns->rx_length_errors);
2916         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2917                             pf->offset_loaded, &os->link_xon_rx,
2918                             &ns->link_xon_rx);
2919         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2920                             pf->offset_loaded, &os->link_xoff_rx,
2921                             &ns->link_xoff_rx);
2922         for (i = 0; i < 8; i++) {
2923                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2924                                     pf->offset_loaded,
2925                                     &os->priority_xon_rx[i],
2926                                     &ns->priority_xon_rx[i]);
2927                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2928                                     pf->offset_loaded,
2929                                     &os->priority_xoff_rx[i],
2930                                     &ns->priority_xoff_rx[i]);
2931         }
2932         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2933                             pf->offset_loaded, &os->link_xon_tx,
2934                             &ns->link_xon_tx);
2935         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2936                             pf->offset_loaded, &os->link_xoff_tx,
2937                             &ns->link_xoff_tx);
2938         for (i = 0; i < 8; i++) {
2939                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2940                                     pf->offset_loaded,
2941                                     &os->priority_xon_tx[i],
2942                                     &ns->priority_xon_tx[i]);
2943                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2944                                     pf->offset_loaded,
2945                                     &os->priority_xoff_tx[i],
2946                                     &ns->priority_xoff_tx[i]);
2947                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2948                                     pf->offset_loaded,
2949                                     &os->priority_xon_2_xoff[i],
2950                                     &ns->priority_xon_2_xoff[i]);
2951         }
2952         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2953                             I40E_GLPRT_PRC64L(hw->port),
2954                             pf->offset_loaded, &os->rx_size_64,
2955                             &ns->rx_size_64);
2956         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2957                             I40E_GLPRT_PRC127L(hw->port),
2958                             pf->offset_loaded, &os->rx_size_127,
2959                             &ns->rx_size_127);
2960         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2961                             I40E_GLPRT_PRC255L(hw->port),
2962                             pf->offset_loaded, &os->rx_size_255,
2963                             &ns->rx_size_255);
2964         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2965                             I40E_GLPRT_PRC511L(hw->port),
2966                             pf->offset_loaded, &os->rx_size_511,
2967                             &ns->rx_size_511);
2968         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2969                             I40E_GLPRT_PRC1023L(hw->port),
2970                             pf->offset_loaded, &os->rx_size_1023,
2971                             &ns->rx_size_1023);
2972         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2973                             I40E_GLPRT_PRC1522L(hw->port),
2974                             pf->offset_loaded, &os->rx_size_1522,
2975                             &ns->rx_size_1522);
2976         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2977                             I40E_GLPRT_PRC9522L(hw->port),
2978                             pf->offset_loaded, &os->rx_size_big,
2979                             &ns->rx_size_big);
2980         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2981                             pf->offset_loaded, &os->rx_undersize,
2982                             &ns->rx_undersize);
2983         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2984                             pf->offset_loaded, &os->rx_fragments,
2985                             &ns->rx_fragments);
2986         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2987                             pf->offset_loaded, &os->rx_oversize,
2988                             &ns->rx_oversize);
2989         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2990                             pf->offset_loaded, &os->rx_jabber,
2991                             &ns->rx_jabber);
2992         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2993                             I40E_GLPRT_PTC64L(hw->port),
2994                             pf->offset_loaded, &os->tx_size_64,
2995                             &ns->tx_size_64);
2996         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2997                             I40E_GLPRT_PTC127L(hw->port),
2998                             pf->offset_loaded, &os->tx_size_127,
2999                             &ns->tx_size_127);
3000         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3001                             I40E_GLPRT_PTC255L(hw->port),
3002                             pf->offset_loaded, &os->tx_size_255,
3003                             &ns->tx_size_255);
3004         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3005                             I40E_GLPRT_PTC511L(hw->port),
3006                             pf->offset_loaded, &os->tx_size_511,
3007                             &ns->tx_size_511);
3008         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3009                             I40E_GLPRT_PTC1023L(hw->port),
3010                             pf->offset_loaded, &os->tx_size_1023,
3011                             &ns->tx_size_1023);
3012         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3013                             I40E_GLPRT_PTC1522L(hw->port),
3014                             pf->offset_loaded, &os->tx_size_1522,
3015                             &ns->tx_size_1522);
3016         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3017                             I40E_GLPRT_PTC9522L(hw->port),
3018                             pf->offset_loaded, &os->tx_size_big,
3019                             &ns->tx_size_big);
3020         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3021                            pf->offset_loaded,
3022                            &os->fd_sb_match, &ns->fd_sb_match);
3023         /* GLPRT_MSPDC not supported */
3024         /* GLPRT_XEC not supported */
3025
3026         pf->offset_loaded = true;
3027
3028         if (pf->main_vsi)
3029                 i40e_update_vsi_stats(pf->main_vsi);
3030 }
3031
3032 /* Get all statistics of a port */
3033 static int
3034 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3035 {
3036         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3037         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3038         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3039         unsigned i;
3040
3041         /* call read registers - updates values, now write them to struct */
3042         i40e_read_stats_registers(pf, hw);
3043
3044         stats->ipackets = ns->eth.rx_unicast +
3045                         ns->eth.rx_multicast +
3046                         ns->eth.rx_broadcast -
3047                         ns->eth.rx_discards -
3048                         pf->main_vsi->eth_stats.rx_discards;
3049         stats->opackets = ns->eth.tx_unicast +
3050                         ns->eth.tx_multicast +
3051                         ns->eth.tx_broadcast;
3052         stats->ibytes   = ns->eth.rx_bytes;
3053         stats->obytes   = ns->eth.tx_bytes;
3054         stats->oerrors  = ns->eth.tx_errors +
3055                         pf->main_vsi->eth_stats.tx_errors;
3056
3057         /* Rx Errors */
3058         stats->imissed  = ns->eth.rx_discards +
3059                         pf->main_vsi->eth_stats.rx_discards;
3060         stats->ierrors  = ns->crc_errors +
3061                         ns->rx_length_errors + ns->rx_undersize +
3062                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3063
3064         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3065         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3066         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3067         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3068         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3069         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3070         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3071                     ns->eth.rx_unknown_protocol);
3072         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3073         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3074         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3075         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3076         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3077         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3078
3079         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3080                     ns->tx_dropped_link_down);
3081         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3082         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3083                     ns->illegal_bytes);
3084         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3085         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3086                     ns->mac_local_faults);
3087         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3088                     ns->mac_remote_faults);
3089         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3090                     ns->rx_length_errors);
3091         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3092         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3093         for (i = 0; i < 8; i++) {
3094                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3095                                 i, ns->priority_xon_rx[i]);
3096                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3097                                 i, ns->priority_xoff_rx[i]);
3098         }
3099         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3100         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3101         for (i = 0; i < 8; i++) {
3102                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3103                                 i, ns->priority_xon_tx[i]);
3104                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3105                                 i, ns->priority_xoff_tx[i]);
3106                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3107                                 i, ns->priority_xon_2_xoff[i]);
3108         }
3109         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3110         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3111         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3112         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3113         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3114         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3115         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3116         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3117         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3118         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3119         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3120         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3121         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3122         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3123         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3124         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3125         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3126         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3127         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3128                         ns->mac_short_packet_dropped);
3129         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3130                     ns->checksum_error);
3131         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3132         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3133         return 0;
3134 }
3135
3136 /* Reset the statistics */
3137 static void
3138 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3139 {
3140         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3141         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3142
3143         /* Mark PF and VSI stats to update the offset, aka "reset" */
3144         pf->offset_loaded = false;
3145         if (pf->main_vsi)
3146                 pf->main_vsi->offset_loaded = false;
3147
3148         /* read the stats, reading current register values into offset */
3149         i40e_read_stats_registers(pf, hw);
3150 }
3151
3152 static uint32_t
3153 i40e_xstats_calc_num(void)
3154 {
3155         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3156                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3157                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3158 }
3159
3160 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3161                                      struct rte_eth_xstat_name *xstats_names,
3162                                      __rte_unused unsigned limit)
3163 {
3164         unsigned count = 0;
3165         unsigned i, prio;
3166
3167         if (xstats_names == NULL)
3168                 return i40e_xstats_calc_num();
3169
3170         /* Note: limit checked in rte_eth_xstats_names() */
3171
3172         /* Get stats from i40e_eth_stats struct */
3173         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3174                 snprintf(xstats_names[count].name,
3175                          sizeof(xstats_names[count].name),
3176                          "%s", rte_i40e_stats_strings[i].name);
3177                 count++;
3178         }
3179
3180         /* Get individiual stats from i40e_hw_port struct */
3181         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3182                 snprintf(xstats_names[count].name,
3183                         sizeof(xstats_names[count].name),
3184                          "%s", rte_i40e_hw_port_strings[i].name);
3185                 count++;
3186         }
3187
3188         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3189                 for (prio = 0; prio < 8; prio++) {
3190                         snprintf(xstats_names[count].name,
3191                                  sizeof(xstats_names[count].name),
3192                                  "rx_priority%u_%s", prio,
3193                                  rte_i40e_rxq_prio_strings[i].name);
3194                         count++;
3195                 }
3196         }
3197
3198         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3199                 for (prio = 0; prio < 8; prio++) {
3200                         snprintf(xstats_names[count].name,
3201                                  sizeof(xstats_names[count].name),
3202                                  "tx_priority%u_%s", prio,
3203                                  rte_i40e_txq_prio_strings[i].name);
3204                         count++;
3205                 }
3206         }
3207         return count;
3208 }
3209
3210 static int
3211 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3212                     unsigned n)
3213 {
3214         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3215         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3216         unsigned i, count, prio;
3217         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3218
3219         count = i40e_xstats_calc_num();
3220         if (n < count)
3221                 return count;
3222
3223         i40e_read_stats_registers(pf, hw);
3224
3225         if (xstats == NULL)
3226                 return 0;
3227
3228         count = 0;
3229
3230         /* Get stats from i40e_eth_stats struct */
3231         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3232                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3233                         rte_i40e_stats_strings[i].offset);
3234                 xstats[count].id = count;
3235                 count++;
3236         }
3237
3238         /* Get individiual stats from i40e_hw_port struct */
3239         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3240                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3241                         rte_i40e_hw_port_strings[i].offset);
3242                 xstats[count].id = count;
3243                 count++;
3244         }
3245
3246         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3247                 for (prio = 0; prio < 8; prio++) {
3248                         xstats[count].value =
3249                                 *(uint64_t *)(((char *)hw_stats) +
3250                                 rte_i40e_rxq_prio_strings[i].offset +
3251                                 (sizeof(uint64_t) * prio));
3252                         xstats[count].id = count;
3253                         count++;
3254                 }
3255         }
3256
3257         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3258                 for (prio = 0; prio < 8; prio++) {
3259                         xstats[count].value =
3260                                 *(uint64_t *)(((char *)hw_stats) +
3261                                 rte_i40e_txq_prio_strings[i].offset +
3262                                 (sizeof(uint64_t) * prio));
3263                         xstats[count].id = count;
3264                         count++;
3265                 }
3266         }
3267
3268         return count;
3269 }
3270
3271 static int
3272 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3273                                  __rte_unused uint16_t queue_id,
3274                                  __rte_unused uint8_t stat_idx,
3275                                  __rte_unused uint8_t is_rx)
3276 {
3277         PMD_INIT_FUNC_TRACE();
3278
3279         return -ENOSYS;
3280 }
3281
3282 static int
3283 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3284 {
3285         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3286         u32 full_ver;
3287         u8 ver, patch;
3288         u16 build;
3289         int ret;
3290
3291         full_ver = hw->nvm.oem_ver;
3292         ver = (u8)(full_ver >> 24);
3293         build = (u16)((full_ver >> 8) & 0xffff);
3294         patch = (u8)(full_ver & 0xff);
3295
3296         ret = snprintf(fw_version, fw_size,
3297                  "%d.%d%d 0x%08x %d.%d.%d",
3298                  ((hw->nvm.version >> 12) & 0xf),
3299                  ((hw->nvm.version >> 4) & 0xff),
3300                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3301                  ver, build, patch);
3302
3303         ret += 1; /* add the size of '\0' */
3304         if (fw_size < (u32)ret)
3305                 return ret;
3306         else
3307                 return 0;
3308 }
3309
3310 static void
3311 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3312 {
3313         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3314         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3315         struct i40e_vsi *vsi = pf->main_vsi;
3316         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3317
3318         dev_info->max_rx_queues = vsi->nb_qps;
3319         dev_info->max_tx_queues = vsi->nb_qps;
3320         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3321         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3322         dev_info->max_mac_addrs = vsi->max_macaddrs;
3323         dev_info->max_vfs = pci_dev->max_vfs;
3324         dev_info->rx_queue_offload_capa = 0;
3325         dev_info->rx_offload_capa =
3326                 DEV_RX_OFFLOAD_VLAN_STRIP |
3327                 DEV_RX_OFFLOAD_QINQ_STRIP |
3328                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3329                 DEV_RX_OFFLOAD_UDP_CKSUM |
3330                 DEV_RX_OFFLOAD_TCP_CKSUM |
3331                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3332                 DEV_RX_OFFLOAD_CRC_STRIP |
3333                 DEV_RX_OFFLOAD_KEEP_CRC |
3334                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3335                 DEV_RX_OFFLOAD_VLAN_FILTER |
3336                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3337
3338         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3339         dev_info->tx_offload_capa =
3340                 DEV_TX_OFFLOAD_VLAN_INSERT |
3341                 DEV_TX_OFFLOAD_QINQ_INSERT |
3342                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3343                 DEV_TX_OFFLOAD_UDP_CKSUM |
3344                 DEV_TX_OFFLOAD_TCP_CKSUM |
3345                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3346                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3347                 DEV_TX_OFFLOAD_TCP_TSO |
3348                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3349                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3350                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3351                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3352                 DEV_TX_OFFLOAD_MULTI_SEGS |
3353                 dev_info->tx_queue_offload_capa;
3354         dev_info->dev_capa =
3355                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3356                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3357
3358         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3359                                                 sizeof(uint32_t);
3360         dev_info->reta_size = pf->hash_lut_size;
3361         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3362
3363         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3364                 .rx_thresh = {
3365                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3366                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3367                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3368                 },
3369                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3370                 .rx_drop_en = 0,
3371                 .offloads = 0,
3372         };
3373
3374         dev_info->default_txconf = (struct rte_eth_txconf) {
3375                 .tx_thresh = {
3376                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3377                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3378                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3379                 },
3380                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3381                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3382                 .offloads = 0,
3383         };
3384
3385         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3386                 .nb_max = I40E_MAX_RING_DESC,
3387                 .nb_min = I40E_MIN_RING_DESC,
3388                 .nb_align = I40E_ALIGN_RING_DESC,
3389         };
3390
3391         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3392                 .nb_max = I40E_MAX_RING_DESC,
3393                 .nb_min = I40E_MIN_RING_DESC,
3394                 .nb_align = I40E_ALIGN_RING_DESC,
3395                 .nb_seg_max = I40E_TX_MAX_SEG,
3396                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3397         };
3398
3399         if (pf->flags & I40E_FLAG_VMDQ) {
3400                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3401                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3402                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3403                                                 pf->max_nb_vmdq_vsi;
3404                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3405                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3406                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3407         }
3408
3409         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3410                 /* For XL710 */
3411                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3412                 dev_info->default_rxportconf.nb_queues = 2;
3413                 dev_info->default_txportconf.nb_queues = 2;
3414                 if (dev->data->nb_rx_queues == 1)
3415                         dev_info->default_rxportconf.ring_size = 2048;
3416                 else
3417                         dev_info->default_rxportconf.ring_size = 1024;
3418                 if (dev->data->nb_tx_queues == 1)
3419                         dev_info->default_txportconf.ring_size = 1024;
3420                 else
3421                         dev_info->default_txportconf.ring_size = 512;
3422
3423         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3424                 /* For XXV710 */
3425                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3426                 dev_info->default_rxportconf.nb_queues = 1;
3427                 dev_info->default_txportconf.nb_queues = 1;
3428                 dev_info->default_rxportconf.ring_size = 256;
3429                 dev_info->default_txportconf.ring_size = 256;
3430         } else {
3431                 /* For X710 */
3432                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3433                 dev_info->default_rxportconf.nb_queues = 1;
3434                 dev_info->default_txportconf.nb_queues = 1;
3435                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3436                         dev_info->default_rxportconf.ring_size = 512;
3437                         dev_info->default_txportconf.ring_size = 256;
3438                 } else {
3439                         dev_info->default_rxportconf.ring_size = 256;
3440                         dev_info->default_txportconf.ring_size = 256;
3441                 }
3442         }
3443         dev_info->default_rxportconf.burst_size = 32;
3444         dev_info->default_txportconf.burst_size = 32;
3445 }
3446
3447 static int
3448 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3449 {
3450         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3451         struct i40e_vsi *vsi = pf->main_vsi;
3452         PMD_INIT_FUNC_TRACE();
3453
3454         if (on)
3455                 return i40e_vsi_add_vlan(vsi, vlan_id);
3456         else
3457                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3458 }
3459
3460 static int
3461 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3462                                 enum rte_vlan_type vlan_type,
3463                                 uint16_t tpid, int qinq)
3464 {
3465         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3466         uint64_t reg_r = 0;
3467         uint64_t reg_w = 0;
3468         uint16_t reg_id = 3;
3469         int ret;
3470
3471         if (qinq) {
3472                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3473                         reg_id = 2;
3474         }
3475
3476         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3477                                           &reg_r, NULL);
3478         if (ret != I40E_SUCCESS) {
3479                 PMD_DRV_LOG(ERR,
3480                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3481                            reg_id);
3482                 return -EIO;
3483         }
3484         PMD_DRV_LOG(DEBUG,
3485                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3486                     reg_id, reg_r);
3487
3488         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3489         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3490         if (reg_r == reg_w) {
3491                 PMD_DRV_LOG(DEBUG, "No need to write");
3492                 return 0;
3493         }
3494
3495         ret = i40e_aq_debug_write_global_register(hw,
3496                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3497                                            reg_w, NULL);
3498         if (ret != I40E_SUCCESS) {
3499                 PMD_DRV_LOG(ERR,
3500                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3501                             reg_id);
3502                 return -EIO;
3503         }
3504         PMD_DRV_LOG(DEBUG,
3505                     "Global register 0x%08x is changed with value 0x%08x",
3506                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3507
3508         return 0;
3509 }
3510
3511 static int
3512 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3513                    enum rte_vlan_type vlan_type,
3514                    uint16_t tpid)
3515 {
3516         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3517         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3518         int qinq = dev->data->dev_conf.rxmode.offloads &
3519                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3520         int ret = 0;
3521
3522         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3523              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3524             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3525                 PMD_DRV_LOG(ERR,
3526                             "Unsupported vlan type.");
3527                 return -EINVAL;
3528         }
3529
3530         if (pf->support_multi_driver) {
3531                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3532                 return -ENOTSUP;
3533         }
3534
3535         /* 802.1ad frames ability is added in NVM API 1.7*/
3536         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3537                 if (qinq) {
3538                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3539                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3540                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3541                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3542                 } else {
3543                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3544                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3545                 }
3546                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3547                 if (ret != I40E_SUCCESS) {
3548                         PMD_DRV_LOG(ERR,
3549                                     "Set switch config failed aq_err: %d",
3550                                     hw->aq.asq_last_status);
3551                         ret = -EIO;
3552                 }
3553         } else
3554                 /* If NVM API < 1.7, keep the register setting */
3555                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3556                                                       tpid, qinq);
3557
3558         return ret;
3559 }
3560
3561 static int
3562 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3563 {
3564         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3565         struct i40e_vsi *vsi = pf->main_vsi;
3566         struct rte_eth_rxmode *rxmode;
3567
3568         rxmode = &dev->data->dev_conf.rxmode;
3569         if (mask & ETH_VLAN_FILTER_MASK) {
3570                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3571                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3572                 else
3573                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3574         }
3575
3576         if (mask & ETH_VLAN_STRIP_MASK) {
3577                 /* Enable or disable VLAN stripping */
3578                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3579                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3580                 else
3581                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3582         }
3583
3584         if (mask & ETH_VLAN_EXTEND_MASK) {
3585                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3586                         i40e_vsi_config_double_vlan(vsi, TRUE);
3587                         /* Set global registers with default ethertype. */
3588                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3589                                            ETHER_TYPE_VLAN);
3590                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3591                                            ETHER_TYPE_VLAN);
3592                 }
3593                 else
3594                         i40e_vsi_config_double_vlan(vsi, FALSE);
3595         }
3596
3597         return 0;
3598 }
3599
3600 static void
3601 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3602                           __rte_unused uint16_t queue,
3603                           __rte_unused int on)
3604 {
3605         PMD_INIT_FUNC_TRACE();
3606 }
3607
3608 static int
3609 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3610 {
3611         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3612         struct i40e_vsi *vsi = pf->main_vsi;
3613         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3614         struct i40e_vsi_vlan_pvid_info info;
3615
3616         memset(&info, 0, sizeof(info));
3617         info.on = on;
3618         if (info.on)
3619                 info.config.pvid = pvid;
3620         else {
3621                 info.config.reject.tagged =
3622                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3623                 info.config.reject.untagged =
3624                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3625         }
3626
3627         return i40e_vsi_vlan_pvid_set(vsi, &info);
3628 }
3629
3630 static int
3631 i40e_dev_led_on(struct rte_eth_dev *dev)
3632 {
3633         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3634         uint32_t mode = i40e_led_get(hw);
3635
3636         if (mode == 0)
3637                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3638
3639         return 0;
3640 }
3641
3642 static int
3643 i40e_dev_led_off(struct rte_eth_dev *dev)
3644 {
3645         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3646         uint32_t mode = i40e_led_get(hw);
3647
3648         if (mode != 0)
3649                 i40e_led_set(hw, 0, false);
3650
3651         return 0;
3652 }
3653
3654 static int
3655 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3656 {
3657         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3658         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3659
3660         fc_conf->pause_time = pf->fc_conf.pause_time;
3661
3662         /* read out from register, in case they are modified by other port */
3663         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3664                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3665         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3666                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3667
3668         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3669         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3670
3671          /* Return current mode according to actual setting*/
3672         switch (hw->fc.current_mode) {
3673         case I40E_FC_FULL:
3674                 fc_conf->mode = RTE_FC_FULL;
3675                 break;
3676         case I40E_FC_TX_PAUSE:
3677                 fc_conf->mode = RTE_FC_TX_PAUSE;
3678                 break;
3679         case I40E_FC_RX_PAUSE:
3680                 fc_conf->mode = RTE_FC_RX_PAUSE;
3681                 break;
3682         case I40E_FC_NONE:
3683         default:
3684                 fc_conf->mode = RTE_FC_NONE;
3685         };
3686
3687         return 0;
3688 }
3689
3690 static int
3691 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3692 {
3693         uint32_t mflcn_reg, fctrl_reg, reg;
3694         uint32_t max_high_water;
3695         uint8_t i, aq_failure;
3696         int err;
3697         struct i40e_hw *hw;
3698         struct i40e_pf *pf;
3699         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3700                 [RTE_FC_NONE] = I40E_FC_NONE,
3701                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3702                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3703                 [RTE_FC_FULL] = I40E_FC_FULL
3704         };
3705
3706         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3707
3708         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3709         if ((fc_conf->high_water > max_high_water) ||
3710                         (fc_conf->high_water < fc_conf->low_water)) {
3711                 PMD_INIT_LOG(ERR,
3712                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3713                         max_high_water);
3714                 return -EINVAL;
3715         }
3716
3717         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3718         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3719         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3720
3721         pf->fc_conf.pause_time = fc_conf->pause_time;
3722         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3723         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3724
3725         PMD_INIT_FUNC_TRACE();
3726
3727         /* All the link flow control related enable/disable register
3728          * configuration is handle by the F/W
3729          */
3730         err = i40e_set_fc(hw, &aq_failure, true);
3731         if (err < 0)
3732                 return -ENOSYS;
3733
3734         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3735                 /* Configure flow control refresh threshold,
3736                  * the value for stat_tx_pause_refresh_timer[8]
3737                  * is used for global pause operation.
3738                  */
3739
3740                 I40E_WRITE_REG(hw,
3741                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3742                                pf->fc_conf.pause_time);
3743
3744                 /* configure the timer value included in transmitted pause
3745                  * frame,
3746                  * the value for stat_tx_pause_quanta[8] is used for global
3747                  * pause operation
3748                  */
3749                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3750                                pf->fc_conf.pause_time);
3751
3752                 fctrl_reg = I40E_READ_REG(hw,
3753                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3754
3755                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3756                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3757                 else
3758                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3759
3760                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3761                                fctrl_reg);
3762         } else {
3763                 /* Configure pause time (2 TCs per register) */
3764                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3765                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3766                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3767
3768                 /* Configure flow control refresh threshold value */
3769                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3770                                pf->fc_conf.pause_time / 2);
3771
3772                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3773
3774                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3775                  *depending on configuration
3776                  */
3777                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3778                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3779                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3780                 } else {
3781                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3782                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3783                 }
3784
3785                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3786         }
3787
3788         if (!pf->support_multi_driver) {
3789                 /* config water marker both based on the packets and bytes */
3790                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3791                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3792                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3793                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3794                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3795                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3796                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3797                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3798                                   << I40E_KILOSHIFT);
3799                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3800                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3801                                    << I40E_KILOSHIFT);
3802         } else {
3803                 PMD_DRV_LOG(ERR,
3804                             "Water marker configuration is not supported.");
3805         }
3806
3807         I40E_WRITE_FLUSH(hw);
3808
3809         return 0;
3810 }
3811
3812 static int
3813 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3814                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3815 {
3816         PMD_INIT_FUNC_TRACE();
3817
3818         return -ENOSYS;
3819 }
3820
3821 /* Add a MAC address, and update filters */
3822 static int
3823 i40e_macaddr_add(struct rte_eth_dev *dev,
3824                  struct ether_addr *mac_addr,
3825                  __rte_unused uint32_t index,
3826                  uint32_t pool)
3827 {
3828         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3829         struct i40e_mac_filter_info mac_filter;
3830         struct i40e_vsi *vsi;
3831         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3832         int ret;
3833
3834         /* If VMDQ not enabled or configured, return */
3835         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3836                           !pf->nb_cfg_vmdq_vsi)) {
3837                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3838                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3839                         pool);
3840                 return -ENOTSUP;
3841         }
3842
3843         if (pool > pf->nb_cfg_vmdq_vsi) {
3844                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3845                                 pool, pf->nb_cfg_vmdq_vsi);
3846                 return -EINVAL;
3847         }
3848
3849         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3850         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3851                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3852         else
3853                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3854
3855         if (pool == 0)
3856                 vsi = pf->main_vsi;
3857         else
3858                 vsi = pf->vmdq[pool - 1].vsi;
3859
3860         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3861         if (ret != I40E_SUCCESS) {
3862                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3863                 return -ENODEV;
3864         }
3865         return 0;
3866 }
3867
3868 /* Remove a MAC address, and update filters */
3869 static void
3870 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3871 {
3872         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3873         struct i40e_vsi *vsi;
3874         struct rte_eth_dev_data *data = dev->data;
3875         struct ether_addr *macaddr;
3876         int ret;
3877         uint32_t i;
3878         uint64_t pool_sel;
3879
3880         macaddr = &(data->mac_addrs[index]);
3881
3882         pool_sel = dev->data->mac_pool_sel[index];
3883
3884         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3885                 if (pool_sel & (1ULL << i)) {
3886                         if (i == 0)
3887                                 vsi = pf->main_vsi;
3888                         else {
3889                                 /* No VMDQ pool enabled or configured */
3890                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3891                                         (i > pf->nb_cfg_vmdq_vsi)) {
3892                                         PMD_DRV_LOG(ERR,
3893                                                 "No VMDQ pool enabled/configured");
3894                                         return;
3895                                 }
3896                                 vsi = pf->vmdq[i - 1].vsi;
3897                         }
3898                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3899
3900                         if (ret) {
3901                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3902                                 return;
3903                         }
3904                 }
3905         }
3906 }
3907
3908 /* Set perfect match or hash match of MAC and VLAN for a VF */
3909 static int
3910 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3911                  struct rte_eth_mac_filter *filter,
3912                  bool add)
3913 {
3914         struct i40e_hw *hw;
3915         struct i40e_mac_filter_info mac_filter;
3916         struct ether_addr old_mac;
3917         struct ether_addr *new_mac;
3918         struct i40e_pf_vf *vf = NULL;
3919         uint16_t vf_id;
3920         int ret;
3921
3922         if (pf == NULL) {
3923                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3924                 return -EINVAL;
3925         }
3926         hw = I40E_PF_TO_HW(pf);
3927
3928         if (filter == NULL) {
3929                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3930                 return -EINVAL;
3931         }
3932
3933         new_mac = &filter->mac_addr;
3934
3935         if (is_zero_ether_addr(new_mac)) {
3936                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3937                 return -EINVAL;
3938         }
3939
3940         vf_id = filter->dst_id;
3941
3942         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3943                 PMD_DRV_LOG(ERR, "Invalid argument.");
3944                 return -EINVAL;
3945         }
3946         vf = &pf->vfs[vf_id];
3947
3948         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3949                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3950                 return -EINVAL;
3951         }
3952
3953         if (add) {
3954                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3955                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3956                                 ETHER_ADDR_LEN);
3957                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3958                                  ETHER_ADDR_LEN);
3959
3960                 mac_filter.filter_type = filter->filter_type;
3961                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3962                 if (ret != I40E_SUCCESS) {
3963                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3964                         return -1;
3965                 }
3966                 ether_addr_copy(new_mac, &pf->dev_addr);
3967         } else {
3968                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3969                                 ETHER_ADDR_LEN);
3970                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3971                 if (ret != I40E_SUCCESS) {
3972                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3973                         return -1;
3974                 }
3975
3976                 /* Clear device address as it has been removed */
3977                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3978                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3979         }
3980
3981         return 0;
3982 }
3983
3984 /* MAC filter handle */
3985 static int
3986 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3987                 void *arg)
3988 {
3989         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3990         struct rte_eth_mac_filter *filter;
3991         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3992         int ret = I40E_NOT_SUPPORTED;
3993
3994         filter = (struct rte_eth_mac_filter *)(arg);
3995
3996         switch (filter_op) {
3997         case RTE_ETH_FILTER_NOP:
3998                 ret = I40E_SUCCESS;
3999                 break;
4000         case RTE_ETH_FILTER_ADD:
4001                 i40e_pf_disable_irq0(hw);
4002                 if (filter->is_vf)
4003                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4004                 i40e_pf_enable_irq0(hw);
4005                 break;
4006         case RTE_ETH_FILTER_DELETE:
4007                 i40e_pf_disable_irq0(hw);
4008                 if (filter->is_vf)
4009                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4010                 i40e_pf_enable_irq0(hw);
4011                 break;
4012         default:
4013                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4014                 ret = I40E_ERR_PARAM;
4015                 break;
4016         }
4017
4018         return ret;
4019 }
4020
4021 static int
4022 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4023 {
4024         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4025         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4026         uint32_t reg;
4027         int ret;
4028
4029         if (!lut)
4030                 return -EINVAL;
4031
4032         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4033                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4034                                           lut, lut_size);
4035                 if (ret) {
4036                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4037                         return ret;
4038                 }
4039         } else {
4040                 uint32_t *lut_dw = (uint32_t *)lut;
4041                 uint16_t i, lut_size_dw = lut_size / 4;
4042
4043                 if (vsi->type == I40E_VSI_SRIOV) {
4044                         for (i = 0; i <= lut_size_dw; i++) {
4045                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4046                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4047                         }
4048                 } else {
4049                         for (i = 0; i < lut_size_dw; i++)
4050                                 lut_dw[i] = I40E_READ_REG(hw,
4051                                                           I40E_PFQF_HLUT(i));
4052                 }
4053         }
4054
4055         return 0;
4056 }
4057
4058 int
4059 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4060 {
4061         struct i40e_pf *pf;
4062         struct i40e_hw *hw;
4063         int ret;
4064
4065         if (!vsi || !lut)
4066                 return -EINVAL;
4067
4068         pf = I40E_VSI_TO_PF(vsi);
4069         hw = I40E_VSI_TO_HW(vsi);
4070
4071         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4072                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4073                                           lut, lut_size);
4074                 if (ret) {
4075                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4076                         return ret;
4077                 }
4078         } else {
4079                 uint32_t *lut_dw = (uint32_t *)lut;
4080                 uint16_t i, lut_size_dw = lut_size / 4;
4081
4082                 if (vsi->type == I40E_VSI_SRIOV) {
4083                         for (i = 0; i < lut_size_dw; i++)
4084                                 I40E_WRITE_REG(
4085                                         hw,
4086                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4087                                         lut_dw[i]);
4088                 } else {
4089                         for (i = 0; i < lut_size_dw; i++)
4090                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4091                                                lut_dw[i]);
4092                 }
4093                 I40E_WRITE_FLUSH(hw);
4094         }
4095
4096         return 0;
4097 }
4098
4099 static int
4100 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4101                          struct rte_eth_rss_reta_entry64 *reta_conf,
4102                          uint16_t reta_size)
4103 {
4104         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4105         uint16_t i, lut_size = pf->hash_lut_size;
4106         uint16_t idx, shift;
4107         uint8_t *lut;
4108         int ret;
4109
4110         if (reta_size != lut_size ||
4111                 reta_size > ETH_RSS_RETA_SIZE_512) {
4112                 PMD_DRV_LOG(ERR,
4113                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4114                         reta_size, lut_size);
4115                 return -EINVAL;
4116         }
4117
4118         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4119         if (!lut) {
4120                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4121                 return -ENOMEM;
4122         }
4123         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4124         if (ret)
4125                 goto out;
4126         for (i = 0; i < reta_size; i++) {
4127                 idx = i / RTE_RETA_GROUP_SIZE;
4128                 shift = i % RTE_RETA_GROUP_SIZE;
4129                 if (reta_conf[idx].mask & (1ULL << shift))
4130                         lut[i] = reta_conf[idx].reta[shift];
4131         }
4132         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4133
4134 out:
4135         rte_free(lut);
4136
4137         return ret;
4138 }
4139
4140 static int
4141 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4142                         struct rte_eth_rss_reta_entry64 *reta_conf,
4143                         uint16_t reta_size)
4144 {
4145         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4146         uint16_t i, lut_size = pf->hash_lut_size;
4147         uint16_t idx, shift;
4148         uint8_t *lut;
4149         int ret;
4150
4151         if (reta_size != lut_size ||
4152                 reta_size > ETH_RSS_RETA_SIZE_512) {
4153                 PMD_DRV_LOG(ERR,
4154                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4155                         reta_size, lut_size);
4156                 return -EINVAL;
4157         }
4158
4159         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4160         if (!lut) {
4161                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4162                 return -ENOMEM;
4163         }
4164
4165         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4166         if (ret)
4167                 goto out;
4168         for (i = 0; i < reta_size; i++) {
4169                 idx = i / RTE_RETA_GROUP_SIZE;
4170                 shift = i % RTE_RETA_GROUP_SIZE;
4171                 if (reta_conf[idx].mask & (1ULL << shift))
4172                         reta_conf[idx].reta[shift] = lut[i];
4173         }
4174
4175 out:
4176         rte_free(lut);
4177
4178         return ret;
4179 }
4180
4181 /**
4182  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4183  * @hw:   pointer to the HW structure
4184  * @mem:  pointer to mem struct to fill out
4185  * @size: size of memory requested
4186  * @alignment: what to align the allocation to
4187  **/
4188 enum i40e_status_code
4189 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4190                         struct i40e_dma_mem *mem,
4191                         u64 size,
4192                         u32 alignment)
4193 {
4194         const struct rte_memzone *mz = NULL;
4195         char z_name[RTE_MEMZONE_NAMESIZE];
4196
4197         if (!mem)
4198                 return I40E_ERR_PARAM;
4199
4200         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4201         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4202                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4203         if (!mz)
4204                 return I40E_ERR_NO_MEMORY;
4205
4206         mem->size = size;
4207         mem->va = mz->addr;
4208         mem->pa = mz->iova;
4209         mem->zone = (const void *)mz;
4210         PMD_DRV_LOG(DEBUG,
4211                 "memzone %s allocated with physical address: %"PRIu64,
4212                 mz->name, mem->pa);
4213
4214         return I40E_SUCCESS;
4215 }
4216
4217 /**
4218  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4219  * @hw:   pointer to the HW structure
4220  * @mem:  ptr to mem struct to free
4221  **/
4222 enum i40e_status_code
4223 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4224                     struct i40e_dma_mem *mem)
4225 {
4226         if (!mem)
4227                 return I40E_ERR_PARAM;
4228
4229         PMD_DRV_LOG(DEBUG,
4230                 "memzone %s to be freed with physical address: %"PRIu64,
4231                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4232         rte_memzone_free((const struct rte_memzone *)mem->zone);
4233         mem->zone = NULL;
4234         mem->va = NULL;
4235         mem->pa = (u64)0;
4236
4237         return I40E_SUCCESS;
4238 }
4239
4240 /**
4241  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4242  * @hw:   pointer to the HW structure
4243  * @mem:  pointer to mem struct to fill out
4244  * @size: size of memory requested
4245  **/
4246 enum i40e_status_code
4247 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4248                          struct i40e_virt_mem *mem,
4249                          u32 size)
4250 {
4251         if (!mem)
4252                 return I40E_ERR_PARAM;
4253
4254         mem->size = size;
4255         mem->va = rte_zmalloc("i40e", size, 0);
4256
4257         if (mem->va)
4258                 return I40E_SUCCESS;
4259         else
4260                 return I40E_ERR_NO_MEMORY;
4261 }
4262
4263 /**
4264  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4265  * @hw:   pointer to the HW structure
4266  * @mem:  pointer to mem struct to free
4267  **/
4268 enum i40e_status_code
4269 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4270                      struct i40e_virt_mem *mem)
4271 {
4272         if (!mem)
4273                 return I40E_ERR_PARAM;
4274
4275         rte_free(mem->va);
4276         mem->va = NULL;
4277
4278         return I40E_SUCCESS;
4279 }
4280
4281 void
4282 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4283 {
4284         rte_spinlock_init(&sp->spinlock);
4285 }
4286
4287 void
4288 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4289 {
4290         rte_spinlock_lock(&sp->spinlock);
4291 }
4292
4293 void
4294 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4295 {
4296         rte_spinlock_unlock(&sp->spinlock);
4297 }
4298
4299 void
4300 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4301 {
4302         return;
4303 }
4304
4305 /**
4306  * Get the hardware capabilities, which will be parsed
4307  * and saved into struct i40e_hw.
4308  */
4309 static int
4310 i40e_get_cap(struct i40e_hw *hw)
4311 {
4312         struct i40e_aqc_list_capabilities_element_resp *buf;
4313         uint16_t len, size = 0;
4314         int ret;
4315
4316         /* Calculate a huge enough buff for saving response data temporarily */
4317         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4318                                                 I40E_MAX_CAP_ELE_NUM;
4319         buf = rte_zmalloc("i40e", len, 0);
4320         if (!buf) {
4321                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4322                 return I40E_ERR_NO_MEMORY;
4323         }
4324
4325         /* Get, parse the capabilities and save it to hw */
4326         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4327                         i40e_aqc_opc_list_func_capabilities, NULL);
4328         if (ret != I40E_SUCCESS)
4329                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4330
4331         /* Free the temporary buffer after being used */
4332         rte_free(buf);
4333
4334         return ret;
4335 }
4336
4337 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4338 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
4339
4340 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4341                 const char *value,
4342                 void *opaque)
4343 {
4344         struct i40e_pf *pf;
4345         unsigned long num;
4346         char *end;
4347
4348         pf = (struct i40e_pf *)opaque;
4349         RTE_SET_USED(key);
4350
4351         errno = 0;
4352         num = strtoul(value, &end, 0);
4353         if (errno != 0 || end == value || *end != 0) {
4354                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4355                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4356                 return -(EINVAL);
4357         }
4358
4359         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4360                 pf->vf_nb_qp_max = (uint16_t)num;
4361         else
4362                 /* here return 0 to make next valid same argument work */
4363                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4364                             "power of 2 and equal or less than 16 !, Now it is "
4365                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4366
4367         return 0;
4368 }
4369
4370 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4371 {
4372         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4373         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4374         struct rte_kvargs *kvlist;
4375
4376         /* set default queue number per VF as 4 */
4377         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4378
4379         if (dev->device->devargs == NULL)
4380                 return 0;
4381
4382         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4383         if (kvlist == NULL)
4384                 return -(EINVAL);
4385
4386         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4387                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4388                             "the first invalid or last valid one is used !",
4389                             QUEUE_NUM_PER_VF_ARG);
4390
4391         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4392                            i40e_pf_parse_vf_queue_number_handler, pf);
4393
4394         rte_kvargs_free(kvlist);
4395
4396         return 0;
4397 }
4398
4399 static int
4400 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4401 {
4402         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4403         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4404         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4405         uint16_t qp_count = 0, vsi_count = 0;
4406
4407         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4408                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4409                 return -EINVAL;
4410         }
4411
4412         i40e_pf_config_vf_rxq_number(dev);
4413
4414         /* Add the parameter init for LFC */
4415         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4416         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4417         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4418
4419         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4420         pf->max_num_vsi = hw->func_caps.num_vsis;
4421         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4422         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4423
4424         /* FDir queue/VSI allocation */
4425         pf->fdir_qp_offset = 0;
4426         if (hw->func_caps.fd) {
4427                 pf->flags |= I40E_FLAG_FDIR;
4428                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4429         } else {
4430                 pf->fdir_nb_qps = 0;
4431         }
4432         qp_count += pf->fdir_nb_qps;
4433         vsi_count += 1;
4434
4435         /* LAN queue/VSI allocation */
4436         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4437         if (!hw->func_caps.rss) {
4438                 pf->lan_nb_qps = 1;
4439         } else {
4440                 pf->flags |= I40E_FLAG_RSS;
4441                 if (hw->mac.type == I40E_MAC_X722)
4442                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4443                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4444         }
4445         qp_count += pf->lan_nb_qps;
4446         vsi_count += 1;
4447
4448         /* VF queue/VSI allocation */
4449         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4450         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4451                 pf->flags |= I40E_FLAG_SRIOV;
4452                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4453                 pf->vf_num = pci_dev->max_vfs;
4454                 PMD_DRV_LOG(DEBUG,
4455                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4456                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4457         } else {
4458                 pf->vf_nb_qps = 0;
4459                 pf->vf_num = 0;
4460         }
4461         qp_count += pf->vf_nb_qps * pf->vf_num;
4462         vsi_count += pf->vf_num;
4463
4464         /* VMDq queue/VSI allocation */
4465         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4466         pf->vmdq_nb_qps = 0;
4467         pf->max_nb_vmdq_vsi = 0;
4468         if (hw->func_caps.vmdq) {
4469                 if (qp_count < hw->func_caps.num_tx_qp &&
4470                         vsi_count < hw->func_caps.num_vsis) {
4471                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4472                                 qp_count) / pf->vmdq_nb_qp_max;
4473
4474                         /* Limit the maximum number of VMDq vsi to the maximum
4475                          * ethdev can support
4476                          */
4477                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4478                                 hw->func_caps.num_vsis - vsi_count);
4479                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4480                                 ETH_64_POOLS);
4481                         if (pf->max_nb_vmdq_vsi) {
4482                                 pf->flags |= I40E_FLAG_VMDQ;
4483                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4484                                 PMD_DRV_LOG(DEBUG,
4485                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4486                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4487                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4488                         } else {
4489                                 PMD_DRV_LOG(INFO,
4490                                         "No enough queues left for VMDq");
4491                         }
4492                 } else {
4493                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4494                 }
4495         }
4496         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4497         vsi_count += pf->max_nb_vmdq_vsi;
4498
4499         if (hw->func_caps.dcb)
4500                 pf->flags |= I40E_FLAG_DCB;
4501
4502         if (qp_count > hw->func_caps.num_tx_qp) {
4503                 PMD_DRV_LOG(ERR,
4504                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4505                         qp_count, hw->func_caps.num_tx_qp);
4506                 return -EINVAL;
4507         }
4508         if (vsi_count > hw->func_caps.num_vsis) {
4509                 PMD_DRV_LOG(ERR,
4510                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4511                         vsi_count, hw->func_caps.num_vsis);
4512                 return -EINVAL;
4513         }
4514
4515         return 0;
4516 }
4517
4518 static int
4519 i40e_pf_get_switch_config(struct i40e_pf *pf)
4520 {
4521         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4522         struct i40e_aqc_get_switch_config_resp *switch_config;
4523         struct i40e_aqc_switch_config_element_resp *element;
4524         uint16_t start_seid = 0, num_reported;
4525         int ret;
4526
4527         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4528                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4529         if (!switch_config) {
4530                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4531                 return -ENOMEM;
4532         }
4533
4534         /* Get the switch configurations */
4535         ret = i40e_aq_get_switch_config(hw, switch_config,
4536                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4537         if (ret != I40E_SUCCESS) {
4538                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4539                 goto fail;
4540         }
4541         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4542         if (num_reported != 1) { /* The number should be 1 */
4543                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4544                 goto fail;
4545         }
4546
4547         /* Parse the switch configuration elements */
4548         element = &(switch_config->element[0]);
4549         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4550                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4551                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4552         } else
4553                 PMD_DRV_LOG(INFO, "Unknown element type");
4554
4555 fail:
4556         rte_free(switch_config);
4557
4558         return ret;
4559 }
4560
4561 static int
4562 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4563                         uint32_t num)
4564 {
4565         struct pool_entry *entry;
4566
4567         if (pool == NULL || num == 0)
4568                 return -EINVAL;
4569
4570         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4571         if (entry == NULL) {
4572                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4573                 return -ENOMEM;
4574         }
4575
4576         /* queue heap initialize */
4577         pool->num_free = num;
4578         pool->num_alloc = 0;
4579         pool->base = base;
4580         LIST_INIT(&pool->alloc_list);
4581         LIST_INIT(&pool->free_list);
4582
4583         /* Initialize element  */
4584         entry->base = 0;
4585         entry->len = num;
4586
4587         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4588         return 0;
4589 }
4590
4591 static void
4592 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4593 {
4594         struct pool_entry *entry, *next_entry;
4595
4596         if (pool == NULL)
4597                 return;
4598
4599         for (entry = LIST_FIRST(&pool->alloc_list);
4600                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4601                         entry = next_entry) {
4602                 LIST_REMOVE(entry, next);
4603                 rte_free(entry);
4604         }
4605
4606         for (entry = LIST_FIRST(&pool->free_list);
4607                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4608                         entry = next_entry) {
4609                 LIST_REMOVE(entry, next);
4610                 rte_free(entry);
4611         }
4612
4613         pool->num_free = 0;
4614         pool->num_alloc = 0;
4615         pool->base = 0;
4616         LIST_INIT(&pool->alloc_list);
4617         LIST_INIT(&pool->free_list);
4618 }
4619
4620 static int
4621 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4622                        uint32_t base)
4623 {
4624         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4625         uint32_t pool_offset;
4626         int insert;
4627
4628         if (pool == NULL) {
4629                 PMD_DRV_LOG(ERR, "Invalid parameter");
4630                 return -EINVAL;
4631         }
4632
4633         pool_offset = base - pool->base;
4634         /* Lookup in alloc list */
4635         LIST_FOREACH(entry, &pool->alloc_list, next) {
4636                 if (entry->base == pool_offset) {
4637                         valid_entry = entry;
4638                         LIST_REMOVE(entry, next);
4639                         break;
4640                 }
4641         }
4642
4643         /* Not find, return */
4644         if (valid_entry == NULL) {
4645                 PMD_DRV_LOG(ERR, "Failed to find entry");
4646                 return -EINVAL;
4647         }
4648
4649         /**
4650          * Found it, move it to free list  and try to merge.
4651          * In order to make merge easier, always sort it by qbase.
4652          * Find adjacent prev and last entries.
4653          */
4654         prev = next = NULL;
4655         LIST_FOREACH(entry, &pool->free_list, next) {
4656                 if (entry->base > valid_entry->base) {
4657                         next = entry;
4658                         break;
4659                 }
4660                 prev = entry;
4661         }
4662
4663         insert = 0;
4664         /* Try to merge with next one*/
4665         if (next != NULL) {
4666                 /* Merge with next one */
4667                 if (valid_entry->base + valid_entry->len == next->base) {
4668                         next->base = valid_entry->base;
4669                         next->len += valid_entry->len;
4670                         rte_free(valid_entry);
4671                         valid_entry = next;
4672                         insert = 1;
4673                 }
4674         }
4675
4676         if (prev != NULL) {
4677                 /* Merge with previous one */
4678                 if (prev->base + prev->len == valid_entry->base) {
4679                         prev->len += valid_entry->len;
4680                         /* If it merge with next one, remove next node */
4681                         if (insert == 1) {
4682                                 LIST_REMOVE(valid_entry, next);
4683                                 rte_free(valid_entry);
4684                         } else {
4685                                 rte_free(valid_entry);
4686                                 insert = 1;
4687                         }
4688                 }
4689         }
4690
4691         /* Not find any entry to merge, insert */
4692         if (insert == 0) {
4693                 if (prev != NULL)
4694                         LIST_INSERT_AFTER(prev, valid_entry, next);
4695                 else if (next != NULL)
4696                         LIST_INSERT_BEFORE(next, valid_entry, next);
4697                 else /* It's empty list, insert to head */
4698                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4699         }
4700
4701         pool->num_free += valid_entry->len;
4702         pool->num_alloc -= valid_entry->len;
4703
4704         return 0;
4705 }
4706
4707 static int
4708 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4709                        uint16_t num)
4710 {
4711         struct pool_entry *entry, *valid_entry;
4712
4713         if (pool == NULL || num == 0) {
4714                 PMD_DRV_LOG(ERR, "Invalid parameter");
4715                 return -EINVAL;
4716         }
4717
4718         if (pool->num_free < num) {
4719                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4720                             num, pool->num_free);
4721                 return -ENOMEM;
4722         }
4723
4724         valid_entry = NULL;
4725         /* Lookup  in free list and find most fit one */
4726         LIST_FOREACH(entry, &pool->free_list, next) {
4727                 if (entry->len >= num) {
4728                         /* Find best one */
4729                         if (entry->len == num) {
4730                                 valid_entry = entry;
4731                                 break;
4732                         }
4733                         if (valid_entry == NULL || valid_entry->len > entry->len)
4734                                 valid_entry = entry;
4735                 }
4736         }
4737
4738         /* Not find one to satisfy the request, return */
4739         if (valid_entry == NULL) {
4740                 PMD_DRV_LOG(ERR, "No valid entry found");
4741                 return -ENOMEM;
4742         }
4743         /**
4744          * The entry have equal queue number as requested,
4745          * remove it from alloc_list.
4746          */
4747         if (valid_entry->len == num) {
4748                 LIST_REMOVE(valid_entry, next);
4749         } else {
4750                 /**
4751                  * The entry have more numbers than requested,
4752                  * create a new entry for alloc_list and minus its
4753                  * queue base and number in free_list.
4754                  */
4755                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4756                 if (entry == NULL) {
4757                         PMD_DRV_LOG(ERR,
4758                                 "Failed to allocate memory for resource pool");
4759                         return -ENOMEM;
4760                 }
4761                 entry->base = valid_entry->base;
4762                 entry->len = num;
4763                 valid_entry->base += num;
4764                 valid_entry->len -= num;
4765                 valid_entry = entry;
4766         }
4767
4768         /* Insert it into alloc list, not sorted */
4769         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4770
4771         pool->num_free -= valid_entry->len;
4772         pool->num_alloc += valid_entry->len;
4773
4774         return valid_entry->base + pool->base;
4775 }
4776
4777 /**
4778  * bitmap_is_subset - Check whether src2 is subset of src1
4779  **/
4780 static inline int
4781 bitmap_is_subset(uint8_t src1, uint8_t src2)
4782 {
4783         return !((src1 ^ src2) & src2);
4784 }
4785
4786 static enum i40e_status_code
4787 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4788 {
4789         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4790
4791         /* If DCB is not supported, only default TC is supported */
4792         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4793                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4794                 return I40E_NOT_SUPPORTED;
4795         }
4796
4797         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4798                 PMD_DRV_LOG(ERR,
4799                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4800                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4801                 return I40E_NOT_SUPPORTED;
4802         }
4803         return I40E_SUCCESS;
4804 }
4805
4806 int
4807 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4808                                 struct i40e_vsi_vlan_pvid_info *info)
4809 {
4810         struct i40e_hw *hw;
4811         struct i40e_vsi_context ctxt;
4812         uint8_t vlan_flags = 0;
4813         int ret;
4814
4815         if (vsi == NULL || info == NULL) {
4816                 PMD_DRV_LOG(ERR, "invalid parameters");
4817                 return I40E_ERR_PARAM;
4818         }
4819
4820         if (info->on) {
4821                 vsi->info.pvid = info->config.pvid;
4822                 /**
4823                  * If insert pvid is enabled, only tagged pkts are
4824                  * allowed to be sent out.
4825                  */
4826                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4827                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4828         } else {
4829                 vsi->info.pvid = 0;
4830                 if (info->config.reject.tagged == 0)
4831                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4832
4833                 if (info->config.reject.untagged == 0)
4834                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4835         }
4836         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4837                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4838         vsi->info.port_vlan_flags |= vlan_flags;
4839         vsi->info.valid_sections =
4840                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4841         memset(&ctxt, 0, sizeof(ctxt));
4842         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4843         ctxt.seid = vsi->seid;
4844
4845         hw = I40E_VSI_TO_HW(vsi);
4846         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4847         if (ret != I40E_SUCCESS)
4848                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4849
4850         return ret;
4851 }
4852
4853 static int
4854 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4855 {
4856         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4857         int i, ret;
4858         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4859
4860         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4861         if (ret != I40E_SUCCESS)
4862                 return ret;
4863
4864         if (!vsi->seid) {
4865                 PMD_DRV_LOG(ERR, "seid not valid");
4866                 return -EINVAL;
4867         }
4868
4869         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4870         tc_bw_data.tc_valid_bits = enabled_tcmap;
4871         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4872                 tc_bw_data.tc_bw_credits[i] =
4873                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4874
4875         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4876         if (ret != I40E_SUCCESS) {
4877                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4878                 return ret;
4879         }
4880
4881         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4882                                         sizeof(vsi->info.qs_handle));
4883         return I40E_SUCCESS;
4884 }
4885
4886 static enum i40e_status_code
4887 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4888                                  struct i40e_aqc_vsi_properties_data *info,
4889                                  uint8_t enabled_tcmap)
4890 {
4891         enum i40e_status_code ret;
4892         int i, total_tc = 0;
4893         uint16_t qpnum_per_tc, bsf, qp_idx;
4894
4895         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4896         if (ret != I40E_SUCCESS)
4897                 return ret;
4898
4899         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4900                 if (enabled_tcmap & (1 << i))
4901                         total_tc++;
4902         if (total_tc == 0)
4903                 total_tc = 1;
4904         vsi->enabled_tc = enabled_tcmap;
4905
4906         /* Number of queues per enabled TC */
4907         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4908         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4909         bsf = rte_bsf32(qpnum_per_tc);
4910
4911         /* Adjust the queue number to actual queues that can be applied */
4912         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4913                 vsi->nb_qps = qpnum_per_tc * total_tc;
4914
4915         /**
4916          * Configure TC and queue mapping parameters, for enabled TC,
4917          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4918          * default queue will serve it.
4919          */
4920         qp_idx = 0;
4921         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4922                 if (vsi->enabled_tc & (1 << i)) {
4923                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4924                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4925                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4926                         qp_idx += qpnum_per_tc;
4927                 } else
4928                         info->tc_mapping[i] = 0;
4929         }
4930
4931         /* Associate queue number with VSI */
4932         if (vsi->type == I40E_VSI_SRIOV) {
4933                 info->mapping_flags |=
4934                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4935                 for (i = 0; i < vsi->nb_qps; i++)
4936                         info->queue_mapping[i] =
4937                                 rte_cpu_to_le_16(vsi->base_queue + i);
4938         } else {
4939                 info->mapping_flags |=
4940                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4941                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4942         }
4943         info->valid_sections |=
4944                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4945
4946         return I40E_SUCCESS;
4947 }
4948
4949 static int
4950 i40e_veb_release(struct i40e_veb *veb)
4951 {
4952         struct i40e_vsi *vsi;
4953         struct i40e_hw *hw;
4954
4955         if (veb == NULL)
4956                 return -EINVAL;
4957
4958         if (!TAILQ_EMPTY(&veb->head)) {
4959                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4960                 return -EACCES;
4961         }
4962         /* associate_vsi field is NULL for floating VEB */
4963         if (veb->associate_vsi != NULL) {
4964                 vsi = veb->associate_vsi;
4965                 hw = I40E_VSI_TO_HW(vsi);
4966
4967                 vsi->uplink_seid = veb->uplink_seid;
4968                 vsi->veb = NULL;
4969         } else {
4970                 veb->associate_pf->main_vsi->floating_veb = NULL;
4971                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4972         }
4973
4974         i40e_aq_delete_element(hw, veb->seid, NULL);
4975         rte_free(veb);
4976         return I40E_SUCCESS;
4977 }
4978
4979 /* Setup a veb */
4980 static struct i40e_veb *
4981 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4982 {
4983         struct i40e_veb *veb;
4984         int ret;
4985         struct i40e_hw *hw;
4986
4987         if (pf == NULL) {
4988                 PMD_DRV_LOG(ERR,
4989                             "veb setup failed, associated PF shouldn't null");
4990                 return NULL;
4991         }
4992         hw = I40E_PF_TO_HW(pf);
4993
4994         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4995         if (!veb) {
4996                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4997                 goto fail;
4998         }
4999
5000         veb->associate_vsi = vsi;
5001         veb->associate_pf = pf;
5002         TAILQ_INIT(&veb->head);
5003         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5004
5005         /* create floating veb if vsi is NULL */
5006         if (vsi != NULL) {
5007                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5008                                       I40E_DEFAULT_TCMAP, false,
5009                                       &veb->seid, false, NULL);
5010         } else {
5011                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5012                                       true, &veb->seid, false, NULL);
5013         }
5014
5015         if (ret != I40E_SUCCESS) {
5016                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5017                             hw->aq.asq_last_status);
5018                 goto fail;
5019         }
5020         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5021
5022         /* get statistics index */
5023         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5024                                 &veb->stats_idx, NULL, NULL, NULL);
5025         if (ret != I40E_SUCCESS) {
5026                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5027                             hw->aq.asq_last_status);
5028                 goto fail;
5029         }
5030         /* Get VEB bandwidth, to be implemented */
5031         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5032         if (vsi)
5033                 vsi->uplink_seid = veb->seid;
5034
5035         return veb;
5036 fail:
5037         rte_free(veb);
5038         return NULL;
5039 }
5040
5041 int
5042 i40e_vsi_release(struct i40e_vsi *vsi)
5043 {
5044         struct i40e_pf *pf;
5045         struct i40e_hw *hw;
5046         struct i40e_vsi_list *vsi_list;
5047         void *temp;
5048         int ret;
5049         struct i40e_mac_filter *f;
5050         uint16_t user_param;
5051
5052         if (!vsi)
5053                 return I40E_SUCCESS;
5054
5055         if (!vsi->adapter)
5056                 return -EFAULT;
5057
5058         user_param = vsi->user_param;
5059
5060         pf = I40E_VSI_TO_PF(vsi);
5061         hw = I40E_VSI_TO_HW(vsi);
5062
5063         /* VSI has child to attach, release child first */
5064         if (vsi->veb) {
5065                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5066                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5067                                 return -1;
5068                 }
5069                 i40e_veb_release(vsi->veb);
5070         }
5071
5072         if (vsi->floating_veb) {
5073                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5074                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5075                                 return -1;
5076                 }
5077         }
5078
5079         /* Remove all macvlan filters of the VSI */
5080         i40e_vsi_remove_all_macvlan_filter(vsi);
5081         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5082                 rte_free(f);
5083
5084         if (vsi->type != I40E_VSI_MAIN &&
5085             ((vsi->type != I40E_VSI_SRIOV) ||
5086             !pf->floating_veb_list[user_param])) {
5087                 /* Remove vsi from parent's sibling list */
5088                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5089                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5090                         return I40E_ERR_PARAM;
5091                 }
5092                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5093                                 &vsi->sib_vsi_list, list);
5094
5095                 /* Remove all switch element of the VSI */
5096                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5097                 if (ret != I40E_SUCCESS)
5098                         PMD_DRV_LOG(ERR, "Failed to delete element");
5099         }
5100
5101         if ((vsi->type == I40E_VSI_SRIOV) &&
5102             pf->floating_veb_list[user_param]) {
5103                 /* Remove vsi from parent's sibling list */
5104                 if (vsi->parent_vsi == NULL ||
5105                     vsi->parent_vsi->floating_veb == NULL) {
5106                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5107                         return I40E_ERR_PARAM;
5108                 }
5109                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5110                              &vsi->sib_vsi_list, list);
5111
5112                 /* Remove all switch element of the VSI */
5113                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5114                 if (ret != I40E_SUCCESS)
5115                         PMD_DRV_LOG(ERR, "Failed to delete element");
5116         }
5117
5118         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5119
5120         if (vsi->type != I40E_VSI_SRIOV)
5121                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5122         rte_free(vsi);
5123
5124         return I40E_SUCCESS;
5125 }
5126
5127 static int
5128 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5129 {
5130         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5131         struct i40e_aqc_remove_macvlan_element_data def_filter;
5132         struct i40e_mac_filter_info filter;
5133         int ret;
5134
5135         if (vsi->type != I40E_VSI_MAIN)
5136                 return I40E_ERR_CONFIG;
5137         memset(&def_filter, 0, sizeof(def_filter));
5138         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5139                                         ETH_ADDR_LEN);
5140         def_filter.vlan_tag = 0;
5141         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5142                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5143         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5144         if (ret != I40E_SUCCESS) {
5145                 struct i40e_mac_filter *f;
5146                 struct ether_addr *mac;
5147
5148                 PMD_DRV_LOG(DEBUG,
5149                             "Cannot remove the default macvlan filter");
5150                 /* It needs to add the permanent mac into mac list */
5151                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5152                 if (f == NULL) {
5153                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5154                         return I40E_ERR_NO_MEMORY;
5155                 }
5156                 mac = &f->mac_info.mac_addr;
5157                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5158                                 ETH_ADDR_LEN);
5159                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5160                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5161                 vsi->mac_num++;
5162
5163                 return ret;
5164         }
5165         rte_memcpy(&filter.mac_addr,
5166                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5167         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5168         return i40e_vsi_add_mac(vsi, &filter);
5169 }
5170
5171 /*
5172  * i40e_vsi_get_bw_config - Query VSI BW Information
5173  * @vsi: the VSI to be queried
5174  *
5175  * Returns 0 on success, negative value on failure
5176  */
5177 static enum i40e_status_code
5178 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5179 {
5180         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5181         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5182         struct i40e_hw *hw = &vsi->adapter->hw;
5183         i40e_status ret;
5184         int i;
5185         uint32_t bw_max;
5186
5187         memset(&bw_config, 0, sizeof(bw_config));
5188         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5189         if (ret != I40E_SUCCESS) {
5190                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5191                             hw->aq.asq_last_status);
5192                 return ret;
5193         }
5194
5195         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5196         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5197                                         &ets_sla_config, NULL);
5198         if (ret != I40E_SUCCESS) {
5199                 PMD_DRV_LOG(ERR,
5200                         "VSI failed to get TC bandwdith configuration %u",
5201                         hw->aq.asq_last_status);
5202                 return ret;
5203         }
5204
5205         /* store and print out BW info */
5206         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5207         vsi->bw_info.bw_max = bw_config.max_bw;
5208         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5209         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5210         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5211                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5212                      I40E_16_BIT_WIDTH);
5213         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5214                 vsi->bw_info.bw_ets_share_credits[i] =
5215                                 ets_sla_config.share_credits[i];
5216                 vsi->bw_info.bw_ets_credits[i] =
5217                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5218                 /* 4 bits per TC, 4th bit is reserved */
5219                 vsi->bw_info.bw_ets_max[i] =
5220                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5221                                   RTE_LEN2MASK(3, uint8_t));
5222                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5223                             vsi->bw_info.bw_ets_share_credits[i]);
5224                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5225                             vsi->bw_info.bw_ets_credits[i]);
5226                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5227                             vsi->bw_info.bw_ets_max[i]);
5228         }
5229
5230         return I40E_SUCCESS;
5231 }
5232
5233 /* i40e_enable_pf_lb
5234  * @pf: pointer to the pf structure
5235  *
5236  * allow loopback on pf
5237  */
5238 static inline void
5239 i40e_enable_pf_lb(struct i40e_pf *pf)
5240 {
5241         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5242         struct i40e_vsi_context ctxt;
5243         int ret;
5244
5245         /* Use the FW API if FW >= v5.0 */
5246         if (hw->aq.fw_maj_ver < 5) {
5247                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5248                 return;
5249         }
5250
5251         memset(&ctxt, 0, sizeof(ctxt));
5252         ctxt.seid = pf->main_vsi_seid;
5253         ctxt.pf_num = hw->pf_id;
5254         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5255         if (ret) {
5256                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5257                             ret, hw->aq.asq_last_status);
5258                 return;
5259         }
5260         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5261         ctxt.info.valid_sections =
5262                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5263         ctxt.info.switch_id |=
5264                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5265
5266         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5267         if (ret)
5268                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5269                             hw->aq.asq_last_status);
5270 }
5271
5272 /* Setup a VSI */
5273 struct i40e_vsi *
5274 i40e_vsi_setup(struct i40e_pf *pf,
5275                enum i40e_vsi_type type,
5276                struct i40e_vsi *uplink_vsi,
5277                uint16_t user_param)
5278 {
5279         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5280         struct i40e_vsi *vsi;
5281         struct i40e_mac_filter_info filter;
5282         int ret;
5283         struct i40e_vsi_context ctxt;
5284         struct ether_addr broadcast =
5285                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5286
5287         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5288             uplink_vsi == NULL) {
5289                 PMD_DRV_LOG(ERR,
5290                         "VSI setup failed, VSI link shouldn't be NULL");
5291                 return NULL;
5292         }
5293
5294         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5295                 PMD_DRV_LOG(ERR,
5296                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5297                 return NULL;
5298         }
5299
5300         /* two situations
5301          * 1.type is not MAIN and uplink vsi is not NULL
5302          * If uplink vsi didn't setup VEB, create one first under veb field
5303          * 2.type is SRIOV and the uplink is NULL
5304          * If floating VEB is NULL, create one veb under floating veb field
5305          */
5306
5307         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5308             uplink_vsi->veb == NULL) {
5309                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5310
5311                 if (uplink_vsi->veb == NULL) {
5312                         PMD_DRV_LOG(ERR, "VEB setup failed");
5313                         return NULL;
5314                 }
5315                 /* set ALLOWLOOPBACk on pf, when veb is created */
5316                 i40e_enable_pf_lb(pf);
5317         }
5318
5319         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5320             pf->main_vsi->floating_veb == NULL) {
5321                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5322
5323                 if (pf->main_vsi->floating_veb == NULL) {
5324                         PMD_DRV_LOG(ERR, "VEB setup failed");
5325                         return NULL;
5326                 }
5327         }
5328
5329         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5330         if (!vsi) {
5331                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5332                 return NULL;
5333         }
5334         TAILQ_INIT(&vsi->mac_list);
5335         vsi->type = type;
5336         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5337         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5338         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5339         vsi->user_param = user_param;
5340         vsi->vlan_anti_spoof_on = 0;
5341         vsi->vlan_filter_on = 0;
5342         /* Allocate queues */
5343         switch (vsi->type) {
5344         case I40E_VSI_MAIN  :
5345                 vsi->nb_qps = pf->lan_nb_qps;
5346                 break;
5347         case I40E_VSI_SRIOV :
5348                 vsi->nb_qps = pf->vf_nb_qps;
5349                 break;
5350         case I40E_VSI_VMDQ2:
5351                 vsi->nb_qps = pf->vmdq_nb_qps;
5352                 break;
5353         case I40E_VSI_FDIR:
5354                 vsi->nb_qps = pf->fdir_nb_qps;
5355                 break;
5356         default:
5357                 goto fail_mem;
5358         }
5359         /*
5360          * The filter status descriptor is reported in rx queue 0,
5361          * while the tx queue for fdir filter programming has no
5362          * such constraints, can be non-zero queues.
5363          * To simplify it, choose FDIR vsi use queue 0 pair.
5364          * To make sure it will use queue 0 pair, queue allocation
5365          * need be done before this function is called
5366          */
5367         if (type != I40E_VSI_FDIR) {
5368                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5369                         if (ret < 0) {
5370                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5371                                                 vsi->seid, ret);
5372                                 goto fail_mem;
5373                         }
5374                         vsi->base_queue = ret;
5375         } else
5376                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5377
5378         /* VF has MSIX interrupt in VF range, don't allocate here */
5379         if (type == I40E_VSI_MAIN) {
5380                 if (pf->support_multi_driver) {
5381                         /* If support multi-driver, need to use INT0 instead of
5382                          * allocating from msix pool. The Msix pool is init from
5383                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5384                          * to 1 without calling i40e_res_pool_alloc.
5385                          */
5386                         vsi->msix_intr = 0;
5387                         vsi->nb_msix = 1;
5388                 } else {
5389                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5390                                                   RTE_MIN(vsi->nb_qps,
5391                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5392                         if (ret < 0) {
5393                                 PMD_DRV_LOG(ERR,
5394                                             "VSI MAIN %d get heap failed %d",
5395                                             vsi->seid, ret);
5396                                 goto fail_queue_alloc;
5397                         }
5398                         vsi->msix_intr = ret;
5399                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5400                                                RTE_MAX_RXTX_INTR_VEC_ID);
5401                 }
5402         } else if (type != I40E_VSI_SRIOV) {
5403                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5404                 if (ret < 0) {
5405                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5406                         goto fail_queue_alloc;
5407                 }
5408                 vsi->msix_intr = ret;
5409                 vsi->nb_msix = 1;
5410         } else {
5411                 vsi->msix_intr = 0;
5412                 vsi->nb_msix = 0;
5413         }
5414
5415         /* Add VSI */
5416         if (type == I40E_VSI_MAIN) {
5417                 /* For main VSI, no need to add since it's default one */
5418                 vsi->uplink_seid = pf->mac_seid;
5419                 vsi->seid = pf->main_vsi_seid;
5420                 /* Bind queues with specific MSIX interrupt */
5421                 /**
5422                  * Needs 2 interrupt at least, one for misc cause which will
5423                  * enabled from OS side, Another for queues binding the
5424                  * interrupt from device side only.
5425                  */
5426
5427                 /* Get default VSI parameters from hardware */
5428                 memset(&ctxt, 0, sizeof(ctxt));
5429                 ctxt.seid = vsi->seid;
5430                 ctxt.pf_num = hw->pf_id;
5431                 ctxt.uplink_seid = vsi->uplink_seid;
5432                 ctxt.vf_num = 0;
5433                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5434                 if (ret != I40E_SUCCESS) {
5435                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5436                         goto fail_msix_alloc;
5437                 }
5438                 rte_memcpy(&vsi->info, &ctxt.info,
5439                         sizeof(struct i40e_aqc_vsi_properties_data));
5440                 vsi->vsi_id = ctxt.vsi_number;
5441                 vsi->info.valid_sections = 0;
5442
5443                 /* Configure tc, enabled TC0 only */
5444                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5445                         I40E_SUCCESS) {
5446                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5447                         goto fail_msix_alloc;
5448                 }
5449
5450                 /* TC, queue mapping */
5451                 memset(&ctxt, 0, sizeof(ctxt));
5452                 vsi->info.valid_sections |=
5453                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5454                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5455                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5456                 rte_memcpy(&ctxt.info, &vsi->info,
5457                         sizeof(struct i40e_aqc_vsi_properties_data));
5458                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5459                                                 I40E_DEFAULT_TCMAP);
5460                 if (ret != I40E_SUCCESS) {
5461                         PMD_DRV_LOG(ERR,
5462                                 "Failed to configure TC queue mapping");
5463                         goto fail_msix_alloc;
5464                 }
5465                 ctxt.seid = vsi->seid;
5466                 ctxt.pf_num = hw->pf_id;
5467                 ctxt.uplink_seid = vsi->uplink_seid;
5468                 ctxt.vf_num = 0;
5469
5470                 /* Update VSI parameters */
5471                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5472                 if (ret != I40E_SUCCESS) {
5473                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5474                         goto fail_msix_alloc;
5475                 }
5476
5477                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5478                                                 sizeof(vsi->info.tc_mapping));
5479                 rte_memcpy(&vsi->info.queue_mapping,
5480                                 &ctxt.info.queue_mapping,
5481                         sizeof(vsi->info.queue_mapping));
5482                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5483                 vsi->info.valid_sections = 0;
5484
5485                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5486                                 ETH_ADDR_LEN);
5487
5488                 /**
5489                  * Updating default filter settings are necessary to prevent
5490                  * reception of tagged packets.
5491                  * Some old firmware configurations load a default macvlan
5492                  * filter which accepts both tagged and untagged packets.
5493                  * The updating is to use a normal filter instead if needed.
5494                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5495                  * The firmware with correct configurations load the default
5496                  * macvlan filter which is expected and cannot be removed.
5497                  */
5498                 i40e_update_default_filter_setting(vsi);
5499                 i40e_config_qinq(hw, vsi);
5500         } else if (type == I40E_VSI_SRIOV) {
5501                 memset(&ctxt, 0, sizeof(ctxt));
5502                 /**
5503                  * For other VSI, the uplink_seid equals to uplink VSI's
5504                  * uplink_seid since they share same VEB
5505                  */
5506                 if (uplink_vsi == NULL)
5507                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5508                 else
5509                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5510                 ctxt.pf_num = hw->pf_id;
5511                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5512                 ctxt.uplink_seid = vsi->uplink_seid;
5513                 ctxt.connection_type = 0x1;
5514                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5515
5516                 /* Use the VEB configuration if FW >= v5.0 */
5517                 if (hw->aq.fw_maj_ver >= 5) {
5518                         /* Configure switch ID */
5519                         ctxt.info.valid_sections |=
5520                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5521                         ctxt.info.switch_id =
5522                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5523                 }
5524
5525                 /* Configure port/vlan */
5526                 ctxt.info.valid_sections |=
5527                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5528                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5529                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5530                                                 hw->func_caps.enabled_tcmap);
5531                 if (ret != I40E_SUCCESS) {
5532                         PMD_DRV_LOG(ERR,
5533                                 "Failed to configure TC queue mapping");
5534                         goto fail_msix_alloc;
5535                 }
5536
5537                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5538                 ctxt.info.valid_sections |=
5539                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5540                 /**
5541                  * Since VSI is not created yet, only configure parameter,
5542                  * will add vsi below.
5543                  */
5544
5545                 i40e_config_qinq(hw, vsi);
5546         } else if (type == I40E_VSI_VMDQ2) {
5547                 memset(&ctxt, 0, sizeof(ctxt));
5548                 /*
5549                  * For other VSI, the uplink_seid equals to uplink VSI's
5550                  * uplink_seid since they share same VEB
5551                  */
5552                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5553                 ctxt.pf_num = hw->pf_id;
5554                 ctxt.vf_num = 0;
5555                 ctxt.uplink_seid = vsi->uplink_seid;
5556                 ctxt.connection_type = 0x1;
5557                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5558
5559                 ctxt.info.valid_sections |=
5560                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5561                 /* user_param carries flag to enable loop back */
5562                 if (user_param) {
5563                         ctxt.info.switch_id =
5564                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5565                         ctxt.info.switch_id |=
5566                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5567                 }
5568
5569                 /* Configure port/vlan */
5570                 ctxt.info.valid_sections |=
5571                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5572                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5573                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5574                                                 I40E_DEFAULT_TCMAP);
5575                 if (ret != I40E_SUCCESS) {
5576                         PMD_DRV_LOG(ERR,
5577                                 "Failed to configure TC queue mapping");
5578                         goto fail_msix_alloc;
5579                 }
5580                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5581                 ctxt.info.valid_sections |=
5582                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5583         } else if (type == I40E_VSI_FDIR) {
5584                 memset(&ctxt, 0, sizeof(ctxt));
5585                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5586                 ctxt.pf_num = hw->pf_id;
5587                 ctxt.vf_num = 0;
5588                 ctxt.uplink_seid = vsi->uplink_seid;
5589                 ctxt.connection_type = 0x1;     /* regular data port */
5590                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5591                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5592                                                 I40E_DEFAULT_TCMAP);
5593                 if (ret != I40E_SUCCESS) {
5594                         PMD_DRV_LOG(ERR,
5595                                 "Failed to configure TC queue mapping.");
5596                         goto fail_msix_alloc;
5597                 }
5598                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5599                 ctxt.info.valid_sections |=
5600                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5601         } else {
5602                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5603                 goto fail_msix_alloc;
5604         }
5605
5606         if (vsi->type != I40E_VSI_MAIN) {
5607                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5608                 if (ret != I40E_SUCCESS) {
5609                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5610                                     hw->aq.asq_last_status);
5611                         goto fail_msix_alloc;
5612                 }
5613                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5614                 vsi->info.valid_sections = 0;
5615                 vsi->seid = ctxt.seid;
5616                 vsi->vsi_id = ctxt.vsi_number;
5617                 vsi->sib_vsi_list.vsi = vsi;
5618                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5619                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5620                                           &vsi->sib_vsi_list, list);
5621                 } else {
5622                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5623                                           &vsi->sib_vsi_list, list);
5624                 }
5625         }
5626
5627         /* MAC/VLAN configuration */
5628         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5629         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5630
5631         ret = i40e_vsi_add_mac(vsi, &filter);
5632         if (ret != I40E_SUCCESS) {
5633                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5634                 goto fail_msix_alloc;
5635         }
5636
5637         /* Get VSI BW information */
5638         i40e_vsi_get_bw_config(vsi);
5639         return vsi;
5640 fail_msix_alloc:
5641         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5642 fail_queue_alloc:
5643         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5644 fail_mem:
5645         rte_free(vsi);
5646         return NULL;
5647 }
5648
5649 /* Configure vlan filter on or off */
5650 int
5651 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5652 {
5653         int i, num;
5654         struct i40e_mac_filter *f;
5655         void *temp;
5656         struct i40e_mac_filter_info *mac_filter;
5657         enum rte_mac_filter_type desired_filter;
5658         int ret = I40E_SUCCESS;
5659
5660         if (on) {
5661                 /* Filter to match MAC and VLAN */
5662                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5663         } else {
5664                 /* Filter to match only MAC */
5665                 desired_filter = RTE_MAC_PERFECT_MATCH;
5666         }
5667
5668         num = vsi->mac_num;
5669
5670         mac_filter = rte_zmalloc("mac_filter_info_data",
5671                                  num * sizeof(*mac_filter), 0);
5672         if (mac_filter == NULL) {
5673                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5674                 return I40E_ERR_NO_MEMORY;
5675         }
5676
5677         i = 0;
5678
5679         /* Remove all existing mac */
5680         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5681                 mac_filter[i] = f->mac_info;
5682                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5683                 if (ret) {
5684                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5685                                     on ? "enable" : "disable");
5686                         goto DONE;
5687                 }
5688                 i++;
5689         }
5690
5691         /* Override with new filter */
5692         for (i = 0; i < num; i++) {
5693                 mac_filter[i].filter_type = desired_filter;
5694                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5695                 if (ret) {
5696                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5697                                     on ? "enable" : "disable");
5698                         goto DONE;
5699                 }
5700         }
5701
5702 DONE:
5703         rte_free(mac_filter);
5704         return ret;
5705 }
5706
5707 /* Configure vlan stripping on or off */
5708 int
5709 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5710 {
5711         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5712         struct i40e_vsi_context ctxt;
5713         uint8_t vlan_flags;
5714         int ret = I40E_SUCCESS;
5715
5716         /* Check if it has been already on or off */
5717         if (vsi->info.valid_sections &
5718                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5719                 if (on) {
5720                         if ((vsi->info.port_vlan_flags &
5721                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5722                                 return 0; /* already on */
5723                 } else {
5724                         if ((vsi->info.port_vlan_flags &
5725                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5726                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5727                                 return 0; /* already off */
5728                 }
5729         }
5730
5731         if (on)
5732                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5733         else
5734                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5735         vsi->info.valid_sections =
5736                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5737         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5738         vsi->info.port_vlan_flags |= vlan_flags;
5739         ctxt.seid = vsi->seid;
5740         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5741         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5742         if (ret)
5743                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5744                             on ? "enable" : "disable");
5745
5746         return ret;
5747 }
5748
5749 static int
5750 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5751 {
5752         struct rte_eth_dev_data *data = dev->data;
5753         int ret;
5754         int mask = 0;
5755
5756         /* Apply vlan offload setting */
5757         mask = ETH_VLAN_STRIP_MASK |
5758                ETH_VLAN_FILTER_MASK |
5759                ETH_VLAN_EXTEND_MASK;
5760         ret = i40e_vlan_offload_set(dev, mask);
5761         if (ret) {
5762                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5763                 return ret;
5764         }
5765
5766         /* Apply pvid setting */
5767         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5768                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5769         if (ret)
5770                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5771
5772         return ret;
5773 }
5774
5775 static int
5776 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5777 {
5778         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5779
5780         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5781 }
5782
5783 static int
5784 i40e_update_flow_control(struct i40e_hw *hw)
5785 {
5786 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5787         struct i40e_link_status link_status;
5788         uint32_t rxfc = 0, txfc = 0, reg;
5789         uint8_t an_info;
5790         int ret;
5791
5792         memset(&link_status, 0, sizeof(link_status));
5793         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5794         if (ret != I40E_SUCCESS) {
5795                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5796                 goto write_reg; /* Disable flow control */
5797         }
5798
5799         an_info = hw->phy.link_info.an_info;
5800         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5801                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5802                 ret = I40E_ERR_NOT_READY;
5803                 goto write_reg; /* Disable flow control */
5804         }
5805         /**
5806          * If link auto negotiation is enabled, flow control needs to
5807          * be configured according to it
5808          */
5809         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5810         case I40E_LINK_PAUSE_RXTX:
5811                 rxfc = 1;
5812                 txfc = 1;
5813                 hw->fc.current_mode = I40E_FC_FULL;
5814                 break;
5815         case I40E_AQ_LINK_PAUSE_RX:
5816                 rxfc = 1;
5817                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5818                 break;
5819         case I40E_AQ_LINK_PAUSE_TX:
5820                 txfc = 1;
5821                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5822                 break;
5823         default:
5824                 hw->fc.current_mode = I40E_FC_NONE;
5825                 break;
5826         }
5827
5828 write_reg:
5829         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5830                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5831         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5832         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5833         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5834         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5835
5836         return ret;
5837 }
5838
5839 /* PF setup */
5840 static int
5841 i40e_pf_setup(struct i40e_pf *pf)
5842 {
5843         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5844         struct i40e_filter_control_settings settings;
5845         struct i40e_vsi *vsi;
5846         int ret;
5847
5848         /* Clear all stats counters */
5849         pf->offset_loaded = FALSE;
5850         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5851         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5852         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5853         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5854
5855         ret = i40e_pf_get_switch_config(pf);
5856         if (ret != I40E_SUCCESS) {
5857                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5858                 return ret;
5859         }
5860
5861         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
5862         if (ret)
5863                 PMD_INIT_LOG(WARNING,
5864                         "failed to allocate switch domain for device %d", ret);
5865
5866         if (pf->flags & I40E_FLAG_FDIR) {
5867                 /* make queue allocated first, let FDIR use queue pair 0*/
5868                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5869                 if (ret != I40E_FDIR_QUEUE_ID) {
5870                         PMD_DRV_LOG(ERR,
5871                                 "queue allocation fails for FDIR: ret =%d",
5872                                 ret);
5873                         pf->flags &= ~I40E_FLAG_FDIR;
5874                 }
5875         }
5876         /*  main VSI setup */
5877         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5878         if (!vsi) {
5879                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5880                 return I40E_ERR_NOT_READY;
5881         }
5882         pf->main_vsi = vsi;
5883
5884         /* Configure filter control */
5885         memset(&settings, 0, sizeof(settings));
5886         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5887                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5888         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5889                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5890         else {
5891                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5892                         hw->func_caps.rss_table_size);
5893                 return I40E_ERR_PARAM;
5894         }
5895         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5896                 hw->func_caps.rss_table_size);
5897         pf->hash_lut_size = hw->func_caps.rss_table_size;
5898
5899         /* Enable ethtype and macvlan filters */
5900         settings.enable_ethtype = TRUE;
5901         settings.enable_macvlan = TRUE;
5902         ret = i40e_set_filter_control(hw, &settings);
5903         if (ret)
5904                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5905                                                                 ret);
5906
5907         /* Update flow control according to the auto negotiation */
5908         i40e_update_flow_control(hw);
5909
5910         return I40E_SUCCESS;
5911 }
5912
5913 int
5914 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5915 {
5916         uint32_t reg;
5917         uint16_t j;
5918
5919         /**
5920          * Set or clear TX Queue Disable flags,
5921          * which is required by hardware.
5922          */
5923         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5924         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5925
5926         /* Wait until the request is finished */
5927         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5928                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5929                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5930                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5931                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5932                                                         & 0x1))) {
5933                         break;
5934                 }
5935         }
5936         if (on) {
5937                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5938                         return I40E_SUCCESS; /* already on, skip next steps */
5939
5940                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5941                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5942         } else {
5943                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5944                         return I40E_SUCCESS; /* already off, skip next steps */
5945                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5946         }
5947         /* Write the register */
5948         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5949         /* Check the result */
5950         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5951                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5952                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5953                 if (on) {
5954                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5955                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5956                                 break;
5957                 } else {
5958                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5959                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5960                                 break;
5961                 }
5962         }
5963         /* Check if it is timeout */
5964         if (j >= I40E_CHK_Q_ENA_COUNT) {
5965                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5966                             (on ? "enable" : "disable"), q_idx);
5967                 return I40E_ERR_TIMEOUT;
5968         }
5969
5970         return I40E_SUCCESS;
5971 }
5972
5973 /* Swith on or off the tx queues */
5974 static int
5975 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5976 {
5977         struct rte_eth_dev_data *dev_data = pf->dev_data;
5978         struct i40e_tx_queue *txq;
5979         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5980         uint16_t i;
5981         int ret;
5982
5983         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5984                 txq = dev_data->tx_queues[i];
5985                 /* Don't operate the queue if not configured or
5986                  * if starting only per queue */
5987                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5988                         continue;
5989                 if (on)
5990                         ret = i40e_dev_tx_queue_start(dev, i);
5991                 else
5992                         ret = i40e_dev_tx_queue_stop(dev, i);
5993                 if ( ret != I40E_SUCCESS)
5994                         return ret;
5995         }
5996
5997         return I40E_SUCCESS;
5998 }
5999
6000 int
6001 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6002 {
6003         uint32_t reg;
6004         uint16_t j;
6005
6006         /* Wait until the request is finished */
6007         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6008                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6009                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6010                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6011                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6012                         break;
6013         }
6014
6015         if (on) {
6016                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6017                         return I40E_SUCCESS; /* Already on, skip next steps */
6018                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6019         } else {
6020                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6021                         return I40E_SUCCESS; /* Already off, skip next steps */
6022                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6023         }
6024
6025         /* Write the register */
6026         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6027         /* Check the result */
6028         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6029                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6030                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6031                 if (on) {
6032                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6033                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6034                                 break;
6035                 } else {
6036                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6037                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6038                                 break;
6039                 }
6040         }
6041
6042         /* Check if it is timeout */
6043         if (j >= I40E_CHK_Q_ENA_COUNT) {
6044                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6045                             (on ? "enable" : "disable"), q_idx);
6046                 return I40E_ERR_TIMEOUT;
6047         }
6048
6049         return I40E_SUCCESS;
6050 }
6051 /* Switch on or off the rx queues */
6052 static int
6053 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6054 {
6055         struct rte_eth_dev_data *dev_data = pf->dev_data;
6056         struct i40e_rx_queue *rxq;
6057         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6058         uint16_t i;
6059         int ret;
6060
6061         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6062                 rxq = dev_data->rx_queues[i];
6063                 /* Don't operate the queue if not configured or
6064                  * if starting only per queue */
6065                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6066                         continue;
6067                 if (on)
6068                         ret = i40e_dev_rx_queue_start(dev, i);
6069                 else
6070                         ret = i40e_dev_rx_queue_stop(dev, i);
6071                 if (ret != I40E_SUCCESS)
6072                         return ret;
6073         }
6074
6075         return I40E_SUCCESS;
6076 }
6077
6078 /* Switch on or off all the rx/tx queues */
6079 int
6080 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6081 {
6082         int ret;
6083
6084         if (on) {
6085                 /* enable rx queues before enabling tx queues */
6086                 ret = i40e_dev_switch_rx_queues(pf, on);
6087                 if (ret) {
6088                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6089                         return ret;
6090                 }
6091                 ret = i40e_dev_switch_tx_queues(pf, on);
6092         } else {
6093                 /* Stop tx queues before stopping rx queues */
6094                 ret = i40e_dev_switch_tx_queues(pf, on);
6095                 if (ret) {
6096                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6097                         return ret;
6098                 }
6099                 ret = i40e_dev_switch_rx_queues(pf, on);
6100         }
6101
6102         return ret;
6103 }
6104
6105 /* Initialize VSI for TX */
6106 static int
6107 i40e_dev_tx_init(struct i40e_pf *pf)
6108 {
6109         struct rte_eth_dev_data *data = pf->dev_data;
6110         uint16_t i;
6111         uint32_t ret = I40E_SUCCESS;
6112         struct i40e_tx_queue *txq;
6113
6114         for (i = 0; i < data->nb_tx_queues; i++) {
6115                 txq = data->tx_queues[i];
6116                 if (!txq || !txq->q_set)
6117                         continue;
6118                 ret = i40e_tx_queue_init(txq);
6119                 if (ret != I40E_SUCCESS)
6120                         break;
6121         }
6122         if (ret == I40E_SUCCESS)
6123                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6124                                      ->eth_dev);
6125
6126         return ret;
6127 }
6128
6129 /* Initialize VSI for RX */
6130 static int
6131 i40e_dev_rx_init(struct i40e_pf *pf)
6132 {
6133         struct rte_eth_dev_data *data = pf->dev_data;
6134         int ret = I40E_SUCCESS;
6135         uint16_t i;
6136         struct i40e_rx_queue *rxq;
6137
6138         i40e_pf_config_mq_rx(pf);
6139         for (i = 0; i < data->nb_rx_queues; i++) {
6140                 rxq = data->rx_queues[i];
6141                 if (!rxq || !rxq->q_set)
6142                         continue;
6143
6144                 ret = i40e_rx_queue_init(rxq);
6145                 if (ret != I40E_SUCCESS) {
6146                         PMD_DRV_LOG(ERR,
6147                                 "Failed to do RX queue initialization");
6148                         break;
6149                 }
6150         }
6151         if (ret == I40E_SUCCESS)
6152                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6153                                      ->eth_dev);
6154
6155         return ret;
6156 }
6157
6158 static int
6159 i40e_dev_rxtx_init(struct i40e_pf *pf)
6160 {
6161         int err;
6162
6163         err = i40e_dev_tx_init(pf);
6164         if (err) {
6165                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6166                 return err;
6167         }
6168         err = i40e_dev_rx_init(pf);
6169         if (err) {
6170                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6171                 return err;
6172         }
6173
6174         return err;
6175 }
6176
6177 static int
6178 i40e_vmdq_setup(struct rte_eth_dev *dev)
6179 {
6180         struct rte_eth_conf *conf = &dev->data->dev_conf;
6181         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6182         int i, err, conf_vsis, j, loop;
6183         struct i40e_vsi *vsi;
6184         struct i40e_vmdq_info *vmdq_info;
6185         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6186         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6187
6188         /*
6189          * Disable interrupt to avoid message from VF. Furthermore, it will
6190          * avoid race condition in VSI creation/destroy.
6191          */
6192         i40e_pf_disable_irq0(hw);
6193
6194         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6195                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6196                 return -ENOTSUP;
6197         }
6198
6199         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6200         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6201                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6202                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6203                         pf->max_nb_vmdq_vsi);
6204                 return -ENOTSUP;
6205         }
6206
6207         if (pf->vmdq != NULL) {
6208                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6209                 return 0;
6210         }
6211
6212         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6213                                 sizeof(*vmdq_info) * conf_vsis, 0);
6214
6215         if (pf->vmdq == NULL) {
6216                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6217                 return -ENOMEM;
6218         }
6219
6220         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6221
6222         /* Create VMDQ VSI */
6223         for (i = 0; i < conf_vsis; i++) {
6224                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6225                                 vmdq_conf->enable_loop_back);
6226                 if (vsi == NULL) {
6227                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6228                         err = -1;
6229                         goto err_vsi_setup;
6230                 }
6231                 vmdq_info = &pf->vmdq[i];
6232                 vmdq_info->pf = pf;
6233                 vmdq_info->vsi = vsi;
6234         }
6235         pf->nb_cfg_vmdq_vsi = conf_vsis;
6236
6237         /* Configure Vlan */
6238         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6239         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6240                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6241                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6242                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6243                                         vmdq_conf->pool_map[i].vlan_id, j);
6244
6245                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6246                                                 vmdq_conf->pool_map[i].vlan_id);
6247                                 if (err) {
6248                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6249                                         err = -1;
6250                                         goto err_vsi_setup;
6251                                 }
6252                         }
6253                 }
6254         }
6255
6256         i40e_pf_enable_irq0(hw);
6257
6258         return 0;
6259
6260 err_vsi_setup:
6261         for (i = 0; i < conf_vsis; i++)
6262                 if (pf->vmdq[i].vsi == NULL)
6263                         break;
6264                 else
6265                         i40e_vsi_release(pf->vmdq[i].vsi);
6266
6267         rte_free(pf->vmdq);
6268         pf->vmdq = NULL;
6269         i40e_pf_enable_irq0(hw);
6270         return err;
6271 }
6272
6273 static void
6274 i40e_stat_update_32(struct i40e_hw *hw,
6275                    uint32_t reg,
6276                    bool offset_loaded,
6277                    uint64_t *offset,
6278                    uint64_t *stat)
6279 {
6280         uint64_t new_data;
6281
6282         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6283         if (!offset_loaded)
6284                 *offset = new_data;
6285
6286         if (new_data >= *offset)
6287                 *stat = (uint64_t)(new_data - *offset);
6288         else
6289                 *stat = (uint64_t)((new_data +
6290                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6291 }
6292
6293 static void
6294 i40e_stat_update_48(struct i40e_hw *hw,
6295                    uint32_t hireg,
6296                    uint32_t loreg,
6297                    bool offset_loaded,
6298                    uint64_t *offset,
6299                    uint64_t *stat)
6300 {
6301         uint64_t new_data;
6302
6303         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6304         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6305                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6306
6307         if (!offset_loaded)
6308                 *offset = new_data;
6309
6310         if (new_data >= *offset)
6311                 *stat = new_data - *offset;
6312         else
6313                 *stat = (uint64_t)((new_data +
6314                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6315
6316         *stat &= I40E_48_BIT_MASK;
6317 }
6318
6319 /* Disable IRQ0 */
6320 void
6321 i40e_pf_disable_irq0(struct i40e_hw *hw)
6322 {
6323         /* Disable all interrupt types */
6324         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6325                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6326         I40E_WRITE_FLUSH(hw);
6327 }
6328
6329 /* Enable IRQ0 */
6330 void
6331 i40e_pf_enable_irq0(struct i40e_hw *hw)
6332 {
6333         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6334                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6335                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6336                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6337         I40E_WRITE_FLUSH(hw);
6338 }
6339
6340 static void
6341 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6342 {
6343         /* read pending request and disable first */
6344         i40e_pf_disable_irq0(hw);
6345         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6346         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6347                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6348
6349         if (no_queue)
6350                 /* Link no queues with irq0 */
6351                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6352                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6353 }
6354
6355 static void
6356 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6357 {
6358         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6359         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6360         int i;
6361         uint16_t abs_vf_id;
6362         uint32_t index, offset, val;
6363
6364         if (!pf->vfs)
6365                 return;
6366         /**
6367          * Try to find which VF trigger a reset, use absolute VF id to access
6368          * since the reg is global register.
6369          */
6370         for (i = 0; i < pf->vf_num; i++) {
6371                 abs_vf_id = hw->func_caps.vf_base_id + i;
6372                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6373                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6374                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6375                 /* VFR event occurred */
6376                 if (val & (0x1 << offset)) {
6377                         int ret;
6378
6379                         /* Clear the event first */
6380                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6381                                                         (0x1 << offset));
6382                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6383                         /**
6384                          * Only notify a VF reset event occurred,
6385                          * don't trigger another SW reset
6386                          */
6387                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6388                         if (ret != I40E_SUCCESS)
6389                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6390                 }
6391         }
6392 }
6393
6394 static void
6395 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6396 {
6397         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6398         int i;
6399
6400         for (i = 0; i < pf->vf_num; i++)
6401                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6402 }
6403
6404 static void
6405 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6406 {
6407         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6408         struct i40e_arq_event_info info;
6409         uint16_t pending, opcode;
6410         int ret;
6411
6412         info.buf_len = I40E_AQ_BUF_SZ;
6413         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6414         if (!info.msg_buf) {
6415                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6416                 return;
6417         }
6418
6419         pending = 1;
6420         while (pending) {
6421                 ret = i40e_clean_arq_element(hw, &info, &pending);
6422
6423                 if (ret != I40E_SUCCESS) {
6424                         PMD_DRV_LOG(INFO,
6425                                 "Failed to read msg from AdminQ, aq_err: %u",
6426                                 hw->aq.asq_last_status);
6427                         break;
6428                 }
6429                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6430
6431                 switch (opcode) {
6432                 case i40e_aqc_opc_send_msg_to_pf:
6433                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6434                         i40e_pf_host_handle_vf_msg(dev,
6435                                         rte_le_to_cpu_16(info.desc.retval),
6436                                         rte_le_to_cpu_32(info.desc.cookie_high),
6437                                         rte_le_to_cpu_32(info.desc.cookie_low),
6438                                         info.msg_buf,
6439                                         info.msg_len);
6440                         break;
6441                 case i40e_aqc_opc_get_link_status:
6442                         ret = i40e_dev_link_update(dev, 0);
6443                         if (!ret)
6444                                 _rte_eth_dev_callback_process(dev,
6445                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6446                         break;
6447                 default:
6448                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6449                                     opcode);
6450                         break;
6451                 }
6452         }
6453         rte_free(info.msg_buf);
6454 }
6455
6456 /**
6457  * Interrupt handler triggered by NIC  for handling
6458  * specific interrupt.
6459  *
6460  * @param handle
6461  *  Pointer to interrupt handle.
6462  * @param param
6463  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6464  *
6465  * @return
6466  *  void
6467  */
6468 static void
6469 i40e_dev_interrupt_handler(void *param)
6470 {
6471         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6472         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6473         uint32_t icr0;
6474
6475         /* Disable interrupt */
6476         i40e_pf_disable_irq0(hw);
6477
6478         /* read out interrupt causes */
6479         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6480
6481         /* No interrupt event indicated */
6482         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6483                 PMD_DRV_LOG(INFO, "No interrupt event");
6484                 goto done;
6485         }
6486         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6487                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6488         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6489                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6490         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6491                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6492         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6493                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6494         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6495                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6496         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6497                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6498         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6499                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6500
6501         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6502                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6503                 i40e_dev_handle_vfr_event(dev);
6504         }
6505         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6506                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6507                 i40e_dev_handle_aq_msg(dev);
6508         }
6509
6510 done:
6511         /* Enable interrupt */
6512         i40e_pf_enable_irq0(hw);
6513         rte_intr_enable(dev->intr_handle);
6514 }
6515
6516 int
6517 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6518                          struct i40e_macvlan_filter *filter,
6519                          int total)
6520 {
6521         int ele_num, ele_buff_size;
6522         int num, actual_num, i;
6523         uint16_t flags;
6524         int ret = I40E_SUCCESS;
6525         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6526         struct i40e_aqc_add_macvlan_element_data *req_list;
6527
6528         if (filter == NULL  || total == 0)
6529                 return I40E_ERR_PARAM;
6530         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6531         ele_buff_size = hw->aq.asq_buf_size;
6532
6533         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6534         if (req_list == NULL) {
6535                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6536                 return I40E_ERR_NO_MEMORY;
6537         }
6538
6539         num = 0;
6540         do {
6541                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6542                 memset(req_list, 0, ele_buff_size);
6543
6544                 for (i = 0; i < actual_num; i++) {
6545                         rte_memcpy(req_list[i].mac_addr,
6546                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6547                         req_list[i].vlan_tag =
6548                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6549
6550                         switch (filter[num + i].filter_type) {
6551                         case RTE_MAC_PERFECT_MATCH:
6552                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6553                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6554                                 break;
6555                         case RTE_MACVLAN_PERFECT_MATCH:
6556                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6557                                 break;
6558                         case RTE_MAC_HASH_MATCH:
6559                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6560                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6561                                 break;
6562                         case RTE_MACVLAN_HASH_MATCH:
6563                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6564                                 break;
6565                         default:
6566                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6567                                 ret = I40E_ERR_PARAM;
6568                                 goto DONE;
6569                         }
6570
6571                         req_list[i].queue_number = 0;
6572
6573                         req_list[i].flags = rte_cpu_to_le_16(flags);
6574                 }
6575
6576                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6577                                                 actual_num, NULL);
6578                 if (ret != I40E_SUCCESS) {
6579                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6580                         goto DONE;
6581                 }
6582                 num += actual_num;
6583         } while (num < total);
6584
6585 DONE:
6586         rte_free(req_list);
6587         return ret;
6588 }
6589
6590 int
6591 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6592                             struct i40e_macvlan_filter *filter,
6593                             int total)
6594 {
6595         int ele_num, ele_buff_size;
6596         int num, actual_num, i;
6597         uint16_t flags;
6598         int ret = I40E_SUCCESS;
6599         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6600         struct i40e_aqc_remove_macvlan_element_data *req_list;
6601
6602         if (filter == NULL  || total == 0)
6603                 return I40E_ERR_PARAM;
6604
6605         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6606         ele_buff_size = hw->aq.asq_buf_size;
6607
6608         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6609         if (req_list == NULL) {
6610                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6611                 return I40E_ERR_NO_MEMORY;
6612         }
6613
6614         num = 0;
6615         do {
6616                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6617                 memset(req_list, 0, ele_buff_size);
6618
6619                 for (i = 0; i < actual_num; i++) {
6620                         rte_memcpy(req_list[i].mac_addr,
6621                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6622                         req_list[i].vlan_tag =
6623                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6624
6625                         switch (filter[num + i].filter_type) {
6626                         case RTE_MAC_PERFECT_MATCH:
6627                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6628                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6629                                 break;
6630                         case RTE_MACVLAN_PERFECT_MATCH:
6631                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6632                                 break;
6633                         case RTE_MAC_HASH_MATCH:
6634                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6635                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6636                                 break;
6637                         case RTE_MACVLAN_HASH_MATCH:
6638                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6639                                 break;
6640                         default:
6641                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6642                                 ret = I40E_ERR_PARAM;
6643                                 goto DONE;
6644                         }
6645                         req_list[i].flags = rte_cpu_to_le_16(flags);
6646                 }
6647
6648                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6649                                                 actual_num, NULL);
6650                 if (ret != I40E_SUCCESS) {
6651                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6652                         goto DONE;
6653                 }
6654                 num += actual_num;
6655         } while (num < total);
6656
6657 DONE:
6658         rte_free(req_list);
6659         return ret;
6660 }
6661
6662 /* Find out specific MAC filter */
6663 static struct i40e_mac_filter *
6664 i40e_find_mac_filter(struct i40e_vsi *vsi,
6665                          struct ether_addr *macaddr)
6666 {
6667         struct i40e_mac_filter *f;
6668
6669         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6670                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6671                         return f;
6672         }
6673
6674         return NULL;
6675 }
6676
6677 static bool
6678 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6679                          uint16_t vlan_id)
6680 {
6681         uint32_t vid_idx, vid_bit;
6682
6683         if (vlan_id > ETH_VLAN_ID_MAX)
6684                 return 0;
6685
6686         vid_idx = I40E_VFTA_IDX(vlan_id);
6687         vid_bit = I40E_VFTA_BIT(vlan_id);
6688
6689         if (vsi->vfta[vid_idx] & vid_bit)
6690                 return 1;
6691         else
6692                 return 0;
6693 }
6694
6695 static void
6696 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6697                        uint16_t vlan_id, bool on)
6698 {
6699         uint32_t vid_idx, vid_bit;
6700
6701         vid_idx = I40E_VFTA_IDX(vlan_id);
6702         vid_bit = I40E_VFTA_BIT(vlan_id);
6703
6704         if (on)
6705                 vsi->vfta[vid_idx] |= vid_bit;
6706         else
6707                 vsi->vfta[vid_idx] &= ~vid_bit;
6708 }
6709
6710 void
6711 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6712                      uint16_t vlan_id, bool on)
6713 {
6714         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6715         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6716         int ret;
6717
6718         if (vlan_id > ETH_VLAN_ID_MAX)
6719                 return;
6720
6721         i40e_store_vlan_filter(vsi, vlan_id, on);
6722
6723         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6724                 return;
6725
6726         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6727
6728         if (on) {
6729                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6730                                        &vlan_data, 1, NULL);
6731                 if (ret != I40E_SUCCESS)
6732                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6733         } else {
6734                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6735                                           &vlan_data, 1, NULL);
6736                 if (ret != I40E_SUCCESS)
6737                         PMD_DRV_LOG(ERR,
6738                                     "Failed to remove vlan filter");
6739         }
6740 }
6741
6742 /**
6743  * Find all vlan options for specific mac addr,
6744  * return with actual vlan found.
6745  */
6746 int
6747 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6748                            struct i40e_macvlan_filter *mv_f,
6749                            int num, struct ether_addr *addr)
6750 {
6751         int i;
6752         uint32_t j, k;
6753
6754         /**
6755          * Not to use i40e_find_vlan_filter to decrease the loop time,
6756          * although the code looks complex.
6757           */
6758         if (num < vsi->vlan_num)
6759                 return I40E_ERR_PARAM;
6760
6761         i = 0;
6762         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6763                 if (vsi->vfta[j]) {
6764                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6765                                 if (vsi->vfta[j] & (1 << k)) {
6766                                         if (i > num - 1) {
6767                                                 PMD_DRV_LOG(ERR,
6768                                                         "vlan number doesn't match");
6769                                                 return I40E_ERR_PARAM;
6770                                         }
6771                                         rte_memcpy(&mv_f[i].macaddr,
6772                                                         addr, ETH_ADDR_LEN);
6773                                         mv_f[i].vlan_id =
6774                                                 j * I40E_UINT32_BIT_SIZE + k;
6775                                         i++;
6776                                 }
6777                         }
6778                 }
6779         }
6780         return I40E_SUCCESS;
6781 }
6782
6783 static inline int
6784 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6785                            struct i40e_macvlan_filter *mv_f,
6786                            int num,
6787                            uint16_t vlan)
6788 {
6789         int i = 0;
6790         struct i40e_mac_filter *f;
6791
6792         if (num < vsi->mac_num)
6793                 return I40E_ERR_PARAM;
6794
6795         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6796                 if (i > num - 1) {
6797                         PMD_DRV_LOG(ERR, "buffer number not match");
6798                         return I40E_ERR_PARAM;
6799                 }
6800                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6801                                 ETH_ADDR_LEN);
6802                 mv_f[i].vlan_id = vlan;
6803                 mv_f[i].filter_type = f->mac_info.filter_type;
6804                 i++;
6805         }
6806
6807         return I40E_SUCCESS;
6808 }
6809
6810 static int
6811 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6812 {
6813         int i, j, num;
6814         struct i40e_mac_filter *f;
6815         struct i40e_macvlan_filter *mv_f;
6816         int ret = I40E_SUCCESS;
6817
6818         if (vsi == NULL || vsi->mac_num == 0)
6819                 return I40E_ERR_PARAM;
6820
6821         /* Case that no vlan is set */
6822         if (vsi->vlan_num == 0)
6823                 num = vsi->mac_num;
6824         else
6825                 num = vsi->mac_num * vsi->vlan_num;
6826
6827         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6828         if (mv_f == NULL) {
6829                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6830                 return I40E_ERR_NO_MEMORY;
6831         }
6832
6833         i = 0;
6834         if (vsi->vlan_num == 0) {
6835                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6836                         rte_memcpy(&mv_f[i].macaddr,
6837                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6838                         mv_f[i].filter_type = f->mac_info.filter_type;
6839                         mv_f[i].vlan_id = 0;
6840                         i++;
6841                 }
6842         } else {
6843                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6844                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6845                                         vsi->vlan_num, &f->mac_info.mac_addr);
6846                         if (ret != I40E_SUCCESS)
6847                                 goto DONE;
6848                         for (j = i; j < i + vsi->vlan_num; j++)
6849                                 mv_f[j].filter_type = f->mac_info.filter_type;
6850                         i += vsi->vlan_num;
6851                 }
6852         }
6853
6854         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6855 DONE:
6856         rte_free(mv_f);
6857
6858         return ret;
6859 }
6860
6861 int
6862 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6863 {
6864         struct i40e_macvlan_filter *mv_f;
6865         int mac_num;
6866         int ret = I40E_SUCCESS;
6867
6868         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6869                 return I40E_ERR_PARAM;
6870
6871         /* If it's already set, just return */
6872         if (i40e_find_vlan_filter(vsi,vlan))
6873                 return I40E_SUCCESS;
6874
6875         mac_num = vsi->mac_num;
6876
6877         if (mac_num == 0) {
6878                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6879                 return I40E_ERR_PARAM;
6880         }
6881
6882         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6883
6884         if (mv_f == NULL) {
6885                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6886                 return I40E_ERR_NO_MEMORY;
6887         }
6888
6889         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6890
6891         if (ret != I40E_SUCCESS)
6892                 goto DONE;
6893
6894         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6895
6896         if (ret != I40E_SUCCESS)
6897                 goto DONE;
6898
6899         i40e_set_vlan_filter(vsi, vlan, 1);
6900
6901         vsi->vlan_num++;
6902         ret = I40E_SUCCESS;
6903 DONE:
6904         rte_free(mv_f);
6905         return ret;
6906 }
6907
6908 int
6909 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6910 {
6911         struct i40e_macvlan_filter *mv_f;
6912         int mac_num;
6913         int ret = I40E_SUCCESS;
6914
6915         /**
6916          * Vlan 0 is the generic filter for untagged packets
6917          * and can't be removed.
6918          */
6919         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6920                 return I40E_ERR_PARAM;
6921
6922         /* If can't find it, just return */
6923         if (!i40e_find_vlan_filter(vsi, vlan))
6924                 return I40E_ERR_PARAM;
6925
6926         mac_num = vsi->mac_num;
6927
6928         if (mac_num == 0) {
6929                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6930                 return I40E_ERR_PARAM;
6931         }
6932
6933         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6934
6935         if (mv_f == NULL) {
6936                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6937                 return I40E_ERR_NO_MEMORY;
6938         }
6939
6940         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6941
6942         if (ret != I40E_SUCCESS)
6943                 goto DONE;
6944
6945         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6946
6947         if (ret != I40E_SUCCESS)
6948                 goto DONE;
6949
6950         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6951         if (vsi->vlan_num == 1) {
6952                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6953                 if (ret != I40E_SUCCESS)
6954                         goto DONE;
6955
6956                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6957                 if (ret != I40E_SUCCESS)
6958                         goto DONE;
6959         }
6960
6961         i40e_set_vlan_filter(vsi, vlan, 0);
6962
6963         vsi->vlan_num--;
6964         ret = I40E_SUCCESS;
6965 DONE:
6966         rte_free(mv_f);
6967         return ret;
6968 }
6969
6970 int
6971 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6972 {
6973         struct i40e_mac_filter *f;
6974         struct i40e_macvlan_filter *mv_f;
6975         int i, vlan_num = 0;
6976         int ret = I40E_SUCCESS;
6977
6978         /* If it's add and we've config it, return */
6979         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6980         if (f != NULL)
6981                 return I40E_SUCCESS;
6982         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6983                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6984
6985                 /**
6986                  * If vlan_num is 0, that's the first time to add mac,
6987                  * set mask for vlan_id 0.
6988                  */
6989                 if (vsi->vlan_num == 0) {
6990                         i40e_set_vlan_filter(vsi, 0, 1);
6991                         vsi->vlan_num = 1;
6992                 }
6993                 vlan_num = vsi->vlan_num;
6994         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6995                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6996                 vlan_num = 1;
6997
6998         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6999         if (mv_f == NULL) {
7000                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7001                 return I40E_ERR_NO_MEMORY;
7002         }
7003
7004         for (i = 0; i < vlan_num; i++) {
7005                 mv_f[i].filter_type = mac_filter->filter_type;
7006                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7007                                 ETH_ADDR_LEN);
7008         }
7009
7010         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7011                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7012                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7013                                         &mac_filter->mac_addr);
7014                 if (ret != I40E_SUCCESS)
7015                         goto DONE;
7016         }
7017
7018         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7019         if (ret != I40E_SUCCESS)
7020                 goto DONE;
7021
7022         /* Add the mac addr into mac list */
7023         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7024         if (f == NULL) {
7025                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7026                 ret = I40E_ERR_NO_MEMORY;
7027                 goto DONE;
7028         }
7029         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7030                         ETH_ADDR_LEN);
7031         f->mac_info.filter_type = mac_filter->filter_type;
7032         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7033         vsi->mac_num++;
7034
7035         ret = I40E_SUCCESS;
7036 DONE:
7037         rte_free(mv_f);
7038
7039         return ret;
7040 }
7041
7042 int
7043 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7044 {
7045         struct i40e_mac_filter *f;
7046         struct i40e_macvlan_filter *mv_f;
7047         int i, vlan_num;
7048         enum rte_mac_filter_type filter_type;
7049         int ret = I40E_SUCCESS;
7050
7051         /* Can't find it, return an error */
7052         f = i40e_find_mac_filter(vsi, addr);
7053         if (f == NULL)
7054                 return I40E_ERR_PARAM;
7055
7056         vlan_num = vsi->vlan_num;
7057         filter_type = f->mac_info.filter_type;
7058         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7059                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7060                 if (vlan_num == 0) {
7061                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7062                         return I40E_ERR_PARAM;
7063                 }
7064         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7065                         filter_type == RTE_MAC_HASH_MATCH)
7066                 vlan_num = 1;
7067
7068         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7069         if (mv_f == NULL) {
7070                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7071                 return I40E_ERR_NO_MEMORY;
7072         }
7073
7074         for (i = 0; i < vlan_num; i++) {
7075                 mv_f[i].filter_type = filter_type;
7076                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7077                                 ETH_ADDR_LEN);
7078         }
7079         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7080                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7081                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7082                 if (ret != I40E_SUCCESS)
7083                         goto DONE;
7084         }
7085
7086         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7087         if (ret != I40E_SUCCESS)
7088                 goto DONE;
7089
7090         /* Remove the mac addr into mac list */
7091         TAILQ_REMOVE(&vsi->mac_list, f, next);
7092         rte_free(f);
7093         vsi->mac_num--;
7094
7095         ret = I40E_SUCCESS;
7096 DONE:
7097         rte_free(mv_f);
7098         return ret;
7099 }
7100
7101 /* Configure hash enable flags for RSS */
7102 uint64_t
7103 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7104 {
7105         uint64_t hena = 0;
7106         int i;
7107
7108         if (!flags)
7109                 return hena;
7110
7111         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7112                 if (flags & (1ULL << i))
7113                         hena |= adapter->pctypes_tbl[i];
7114         }
7115
7116         return hena;
7117 }
7118
7119 /* Parse the hash enable flags */
7120 uint64_t
7121 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7122 {
7123         uint64_t rss_hf = 0;
7124
7125         if (!flags)
7126                 return rss_hf;
7127         int i;
7128
7129         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7130                 if (flags & adapter->pctypes_tbl[i])
7131                         rss_hf |= (1ULL << i);
7132         }
7133         return rss_hf;
7134 }
7135
7136 /* Disable RSS */
7137 static void
7138 i40e_pf_disable_rss(struct i40e_pf *pf)
7139 {
7140         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7141
7142         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7143         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7144         I40E_WRITE_FLUSH(hw);
7145 }
7146
7147 int
7148 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7149 {
7150         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7151         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7152         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7153                            I40E_VFQF_HKEY_MAX_INDEX :
7154                            I40E_PFQF_HKEY_MAX_INDEX;
7155         int ret = 0;
7156
7157         if (!key || key_len == 0) {
7158                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7159                 return 0;
7160         } else if (key_len != (key_idx + 1) *
7161                 sizeof(uint32_t)) {
7162                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7163                 return -EINVAL;
7164         }
7165
7166         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7167                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7168                         (struct i40e_aqc_get_set_rss_key_data *)key;
7169
7170                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7171                 if (ret)
7172                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7173         } else {
7174                 uint32_t *hash_key = (uint32_t *)key;
7175                 uint16_t i;
7176
7177                 if (vsi->type == I40E_VSI_SRIOV) {
7178                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7179                                 I40E_WRITE_REG(
7180                                         hw,
7181                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7182                                         hash_key[i]);
7183
7184                 } else {
7185                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7186                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7187                                                hash_key[i]);
7188                 }
7189                 I40E_WRITE_FLUSH(hw);
7190         }
7191
7192         return ret;
7193 }
7194
7195 static int
7196 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7197 {
7198         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7199         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7200         uint32_t reg;
7201         int ret;
7202
7203         if (!key || !key_len)
7204                 return -EINVAL;
7205
7206         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7207                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7208                         (struct i40e_aqc_get_set_rss_key_data *)key);
7209                 if (ret) {
7210                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7211                         return ret;
7212                 }
7213         } else {
7214                 uint32_t *key_dw = (uint32_t *)key;
7215                 uint16_t i;
7216
7217                 if (vsi->type == I40E_VSI_SRIOV) {
7218                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7219                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7220                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7221                         }
7222                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7223                                    sizeof(uint32_t);
7224                 } else {
7225                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7226                                 reg = I40E_PFQF_HKEY(i);
7227                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7228                         }
7229                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7230                                    sizeof(uint32_t);
7231                 }
7232         }
7233         return 0;
7234 }
7235
7236 static int
7237 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7238 {
7239         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7240         uint64_t hena;
7241         int ret;
7242
7243         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7244                                rss_conf->rss_key_len);
7245         if (ret)
7246                 return ret;
7247
7248         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7249         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7250         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7251         I40E_WRITE_FLUSH(hw);
7252
7253         return 0;
7254 }
7255
7256 static int
7257 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7258                          struct rte_eth_rss_conf *rss_conf)
7259 {
7260         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7261         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7262         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7263         uint64_t hena;
7264
7265         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7266         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7267
7268         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7269                 if (rss_hf != 0) /* Enable RSS */
7270                         return -EINVAL;
7271                 return 0; /* Nothing to do */
7272         }
7273         /* RSS enabled */
7274         if (rss_hf == 0) /* Disable RSS */
7275                 return -EINVAL;
7276
7277         return i40e_hw_rss_hash_set(pf, rss_conf);
7278 }
7279
7280 static int
7281 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7282                            struct rte_eth_rss_conf *rss_conf)
7283 {
7284         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7285         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7286         uint64_t hena;
7287
7288         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7289                          &rss_conf->rss_key_len);
7290
7291         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7292         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7293         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7294
7295         return 0;
7296 }
7297
7298 static int
7299 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7300 {
7301         switch (filter_type) {
7302         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7303                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7304                 break;
7305         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7306                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7307                 break;
7308         case RTE_TUNNEL_FILTER_IMAC_TENID:
7309                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7310                 break;
7311         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7312                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7313                 break;
7314         case ETH_TUNNEL_FILTER_IMAC:
7315                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7316                 break;
7317         case ETH_TUNNEL_FILTER_OIP:
7318                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7319                 break;
7320         case ETH_TUNNEL_FILTER_IIP:
7321                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7322                 break;
7323         default:
7324                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7325                 return -EINVAL;
7326         }
7327
7328         return 0;
7329 }
7330
7331 /* Convert tunnel filter structure */
7332 static int
7333 i40e_tunnel_filter_convert(
7334         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7335         struct i40e_tunnel_filter *tunnel_filter)
7336 {
7337         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7338                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7339         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7340                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7341         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7342         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7343              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7344             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7345                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7346         else
7347                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7348         tunnel_filter->input.flags = cld_filter->element.flags;
7349         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7350         tunnel_filter->queue = cld_filter->element.queue_number;
7351         rte_memcpy(tunnel_filter->input.general_fields,
7352                    cld_filter->general_fields,
7353                    sizeof(cld_filter->general_fields));
7354
7355         return 0;
7356 }
7357
7358 /* Check if there exists the tunnel filter */
7359 struct i40e_tunnel_filter *
7360 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7361                              const struct i40e_tunnel_filter_input *input)
7362 {
7363         int ret;
7364
7365         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7366         if (ret < 0)
7367                 return NULL;
7368
7369         return tunnel_rule->hash_map[ret];
7370 }
7371
7372 /* Add a tunnel filter into the SW list */
7373 static int
7374 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7375                              struct i40e_tunnel_filter *tunnel_filter)
7376 {
7377         struct i40e_tunnel_rule *rule = &pf->tunnel;
7378         int ret;
7379
7380         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7381         if (ret < 0) {
7382                 PMD_DRV_LOG(ERR,
7383                             "Failed to insert tunnel filter to hash table %d!",
7384                             ret);
7385                 return ret;
7386         }
7387         rule->hash_map[ret] = tunnel_filter;
7388
7389         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7390
7391         return 0;
7392 }
7393
7394 /* Delete a tunnel filter from the SW list */
7395 int
7396 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7397                           struct i40e_tunnel_filter_input *input)
7398 {
7399         struct i40e_tunnel_rule *rule = &pf->tunnel;
7400         struct i40e_tunnel_filter *tunnel_filter;
7401         int ret;
7402
7403         ret = rte_hash_del_key(rule->hash_table, input);
7404         if (ret < 0) {
7405                 PMD_DRV_LOG(ERR,
7406                             "Failed to delete tunnel filter to hash table %d!",
7407                             ret);
7408                 return ret;
7409         }
7410         tunnel_filter = rule->hash_map[ret];
7411         rule->hash_map[ret] = NULL;
7412
7413         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7414         rte_free(tunnel_filter);
7415
7416         return 0;
7417 }
7418
7419 int
7420 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7421                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7422                         uint8_t add)
7423 {
7424         uint16_t ip_type;
7425         uint32_t ipv4_addr, ipv4_addr_le;
7426         uint8_t i, tun_type = 0;
7427         /* internal varialbe to convert ipv6 byte order */
7428         uint32_t convert_ipv6[4];
7429         int val, ret = 0;
7430         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7431         struct i40e_vsi *vsi = pf->main_vsi;
7432         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7433         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7434         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7435         struct i40e_tunnel_filter *tunnel, *node;
7436         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7437
7438         cld_filter = rte_zmalloc("tunnel_filter",
7439                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7440         0);
7441
7442         if (NULL == cld_filter) {
7443                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7444                 return -ENOMEM;
7445         }
7446         pfilter = cld_filter;
7447
7448         ether_addr_copy(&tunnel_filter->outer_mac,
7449                         (struct ether_addr *)&pfilter->element.outer_mac);
7450         ether_addr_copy(&tunnel_filter->inner_mac,
7451                         (struct ether_addr *)&pfilter->element.inner_mac);
7452
7453         pfilter->element.inner_vlan =
7454                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7455         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7456                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7457                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7458                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7459                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7460                                 &ipv4_addr_le,
7461                                 sizeof(pfilter->element.ipaddr.v4.data));
7462         } else {
7463                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7464                 for (i = 0; i < 4; i++) {
7465                         convert_ipv6[i] =
7466                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7467                 }
7468                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7469                            &convert_ipv6,
7470                            sizeof(pfilter->element.ipaddr.v6.data));
7471         }
7472
7473         /* check tunneled type */
7474         switch (tunnel_filter->tunnel_type) {
7475         case RTE_TUNNEL_TYPE_VXLAN:
7476                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7477                 break;
7478         case RTE_TUNNEL_TYPE_NVGRE:
7479                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7480                 break;
7481         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7482                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7483                 break;
7484         default:
7485                 /* Other tunnel types is not supported. */
7486                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7487                 rte_free(cld_filter);
7488                 return -EINVAL;
7489         }
7490
7491         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7492                                        &pfilter->element.flags);
7493         if (val < 0) {
7494                 rte_free(cld_filter);
7495                 return -EINVAL;
7496         }
7497
7498         pfilter->element.flags |= rte_cpu_to_le_16(
7499                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7500                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7501         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7502         pfilter->element.queue_number =
7503                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7504
7505         /* Check if there is the filter in SW list */
7506         memset(&check_filter, 0, sizeof(check_filter));
7507         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7508         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7509         if (add && node) {
7510                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7511                 rte_free(cld_filter);
7512                 return -EINVAL;
7513         }
7514
7515         if (!add && !node) {
7516                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7517                 rte_free(cld_filter);
7518                 return -EINVAL;
7519         }
7520
7521         if (add) {
7522                 ret = i40e_aq_add_cloud_filters(hw,
7523                                         vsi->seid, &cld_filter->element, 1);
7524                 if (ret < 0) {
7525                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7526                         rte_free(cld_filter);
7527                         return -ENOTSUP;
7528                 }
7529                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7530                 if (tunnel == NULL) {
7531                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7532                         rte_free(cld_filter);
7533                         return -ENOMEM;
7534                 }
7535
7536                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7537                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7538                 if (ret < 0)
7539                         rte_free(tunnel);
7540         } else {
7541                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7542                                                    &cld_filter->element, 1);
7543                 if (ret < 0) {
7544                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7545                         rte_free(cld_filter);
7546                         return -ENOTSUP;
7547                 }
7548                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7549         }
7550
7551         rte_free(cld_filter);
7552         return ret;
7553 }
7554
7555 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7556 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7557 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7558 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7559 #define I40E_TR_GRE_KEY_MASK                    0x400
7560 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7561 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7562
7563 static enum
7564 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7565 {
7566         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7567         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7568         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7569         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7570         enum i40e_status_code status = I40E_SUCCESS;
7571
7572         if (pf->support_multi_driver) {
7573                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7574                 return I40E_NOT_SUPPORTED;
7575         }
7576
7577         memset(&filter_replace, 0,
7578                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7579         memset(&filter_replace_buf, 0,
7580                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7581
7582         /* create L1 filter */
7583         filter_replace.old_filter_type =
7584                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7585         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7586         filter_replace.tr_bit = 0;
7587
7588         /* Prepare the buffer, 3 entries */
7589         filter_replace_buf.data[0] =
7590                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7591         filter_replace_buf.data[0] |=
7592                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7593         filter_replace_buf.data[2] = 0xFF;
7594         filter_replace_buf.data[3] = 0xFF;
7595         filter_replace_buf.data[4] =
7596                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7597         filter_replace_buf.data[4] |=
7598                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7599         filter_replace_buf.data[7] = 0xF0;
7600         filter_replace_buf.data[8]
7601                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7602         filter_replace_buf.data[8] |=
7603                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7604         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7605                 I40E_TR_GENEVE_KEY_MASK |
7606                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7607         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7608                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7609                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7610
7611         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7612                                                &filter_replace_buf);
7613         if (!status && (filter_replace.old_filter_type !=
7614                         filter_replace.new_filter_type))
7615                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7616                             " original: 0x%x, new: 0x%x",
7617                             dev->device->name,
7618                             filter_replace.old_filter_type,
7619                             filter_replace.new_filter_type);
7620
7621         return status;
7622 }
7623
7624 static enum
7625 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7626 {
7627         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7628         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7629         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7630         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7631         enum i40e_status_code status = I40E_SUCCESS;
7632
7633         if (pf->support_multi_driver) {
7634                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7635                 return I40E_NOT_SUPPORTED;
7636         }
7637
7638         /* For MPLSoUDP */
7639         memset(&filter_replace, 0,
7640                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7641         memset(&filter_replace_buf, 0,
7642                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7643         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7644                 I40E_AQC_MIRROR_CLOUD_FILTER;
7645         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7646         filter_replace.new_filter_type =
7647                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7648         /* Prepare the buffer, 2 entries */
7649         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7650         filter_replace_buf.data[0] |=
7651                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7652         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7653         filter_replace_buf.data[4] |=
7654                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7655         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7656                                                &filter_replace_buf);
7657         if (status < 0)
7658                 return status;
7659         if (filter_replace.old_filter_type !=
7660             filter_replace.new_filter_type)
7661                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7662                             " original: 0x%x, new: 0x%x",
7663                             dev->device->name,
7664                             filter_replace.old_filter_type,
7665                             filter_replace.new_filter_type);
7666
7667         /* For MPLSoGRE */
7668         memset(&filter_replace, 0,
7669                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7670         memset(&filter_replace_buf, 0,
7671                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7672
7673         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7674                 I40E_AQC_MIRROR_CLOUD_FILTER;
7675         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7676         filter_replace.new_filter_type =
7677                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7678         /* Prepare the buffer, 2 entries */
7679         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7680         filter_replace_buf.data[0] |=
7681                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7682         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7683         filter_replace_buf.data[4] |=
7684                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7685
7686         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7687                                                &filter_replace_buf);
7688         if (!status && (filter_replace.old_filter_type !=
7689                         filter_replace.new_filter_type))
7690                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7691                             " original: 0x%x, new: 0x%x",
7692                             dev->device->name,
7693                             filter_replace.old_filter_type,
7694                             filter_replace.new_filter_type);
7695
7696         return status;
7697 }
7698
7699 static enum i40e_status_code
7700 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7701 {
7702         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7703         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7704         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7705         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7706         enum i40e_status_code status = I40E_SUCCESS;
7707
7708         if (pf->support_multi_driver) {
7709                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7710                 return I40E_NOT_SUPPORTED;
7711         }
7712
7713         /* For GTP-C */
7714         memset(&filter_replace, 0,
7715                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7716         memset(&filter_replace_buf, 0,
7717                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7718         /* create L1 filter */
7719         filter_replace.old_filter_type =
7720                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7721         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7722         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7723                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7724         /* Prepare the buffer, 2 entries */
7725         filter_replace_buf.data[0] =
7726                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7727         filter_replace_buf.data[0] |=
7728                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7729         filter_replace_buf.data[2] = 0xFF;
7730         filter_replace_buf.data[3] = 0xFF;
7731         filter_replace_buf.data[4] =
7732                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7733         filter_replace_buf.data[4] |=
7734                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7735         filter_replace_buf.data[6] = 0xFF;
7736         filter_replace_buf.data[7] = 0xFF;
7737         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7738                                                &filter_replace_buf);
7739         if (status < 0)
7740                 return status;
7741         if (filter_replace.old_filter_type !=
7742             filter_replace.new_filter_type)
7743                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7744                             " original: 0x%x, new: 0x%x",
7745                             dev->device->name,
7746                             filter_replace.old_filter_type,
7747                             filter_replace.new_filter_type);
7748
7749         /* for GTP-U */
7750         memset(&filter_replace, 0,
7751                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7752         memset(&filter_replace_buf, 0,
7753                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7754         /* create L1 filter */
7755         filter_replace.old_filter_type =
7756                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7757         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7758         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7759                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7760         /* Prepare the buffer, 2 entries */
7761         filter_replace_buf.data[0] =
7762                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7763         filter_replace_buf.data[0] |=
7764                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7765         filter_replace_buf.data[2] = 0xFF;
7766         filter_replace_buf.data[3] = 0xFF;
7767         filter_replace_buf.data[4] =
7768                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7769         filter_replace_buf.data[4] |=
7770                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7771         filter_replace_buf.data[6] = 0xFF;
7772         filter_replace_buf.data[7] = 0xFF;
7773
7774         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7775                                                &filter_replace_buf);
7776         if (!status && (filter_replace.old_filter_type !=
7777                         filter_replace.new_filter_type))
7778                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7779                             " original: 0x%x, new: 0x%x",
7780                             dev->device->name,
7781                             filter_replace.old_filter_type,
7782                             filter_replace.new_filter_type);
7783
7784         return status;
7785 }
7786
7787 static enum
7788 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7789 {
7790         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7791         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7792         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7793         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7794         enum i40e_status_code status = I40E_SUCCESS;
7795
7796         if (pf->support_multi_driver) {
7797                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7798                 return I40E_NOT_SUPPORTED;
7799         }
7800
7801         /* for GTP-C */
7802         memset(&filter_replace, 0,
7803                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7804         memset(&filter_replace_buf, 0,
7805                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7806         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7807         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7808         filter_replace.new_filter_type =
7809                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7810         /* Prepare the buffer, 2 entries */
7811         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7812         filter_replace_buf.data[0] |=
7813                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7814         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7815         filter_replace_buf.data[4] |=
7816                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7817         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7818                                                &filter_replace_buf);
7819         if (status < 0)
7820                 return status;
7821         if (filter_replace.old_filter_type !=
7822             filter_replace.new_filter_type)
7823                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7824                             " original: 0x%x, new: 0x%x",
7825                             dev->device->name,
7826                             filter_replace.old_filter_type,
7827                             filter_replace.new_filter_type);
7828
7829         /* for GTP-U */
7830         memset(&filter_replace, 0,
7831                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7832         memset(&filter_replace_buf, 0,
7833                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7834         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7835         filter_replace.old_filter_type =
7836                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7837         filter_replace.new_filter_type =
7838                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7839         /* Prepare the buffer, 2 entries */
7840         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7841         filter_replace_buf.data[0] |=
7842                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7843         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7844         filter_replace_buf.data[4] |=
7845                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7846
7847         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7848                                                &filter_replace_buf);
7849         if (!status && (filter_replace.old_filter_type !=
7850                         filter_replace.new_filter_type))
7851                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7852                             " original: 0x%x, new: 0x%x",
7853                             dev->device->name,
7854                             filter_replace.old_filter_type,
7855                             filter_replace.new_filter_type);
7856
7857         return status;
7858 }
7859
7860 int
7861 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7862                       struct i40e_tunnel_filter_conf *tunnel_filter,
7863                       uint8_t add)
7864 {
7865         uint16_t ip_type;
7866         uint32_t ipv4_addr, ipv4_addr_le;
7867         uint8_t i, tun_type = 0;
7868         /* internal variable to convert ipv6 byte order */
7869         uint32_t convert_ipv6[4];
7870         int val, ret = 0;
7871         struct i40e_pf_vf *vf = NULL;
7872         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7873         struct i40e_vsi *vsi;
7874         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7875         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7876         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7877         struct i40e_tunnel_filter *tunnel, *node;
7878         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7879         uint32_t teid_le;
7880         bool big_buffer = 0;
7881
7882         cld_filter = rte_zmalloc("tunnel_filter",
7883                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7884                          0);
7885
7886         if (cld_filter == NULL) {
7887                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7888                 return -ENOMEM;
7889         }
7890         pfilter = cld_filter;
7891
7892         ether_addr_copy(&tunnel_filter->outer_mac,
7893                         (struct ether_addr *)&pfilter->element.outer_mac);
7894         ether_addr_copy(&tunnel_filter->inner_mac,
7895                         (struct ether_addr *)&pfilter->element.inner_mac);
7896
7897         pfilter->element.inner_vlan =
7898                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7899         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7900                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7901                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7902                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7903                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7904                                 &ipv4_addr_le,
7905                                 sizeof(pfilter->element.ipaddr.v4.data));
7906         } else {
7907                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7908                 for (i = 0; i < 4; i++) {
7909                         convert_ipv6[i] =
7910                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7911                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7912                 }
7913                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7914                            &convert_ipv6,
7915                            sizeof(pfilter->element.ipaddr.v6.data));
7916         }
7917
7918         /* check tunneled type */
7919         switch (tunnel_filter->tunnel_type) {
7920         case I40E_TUNNEL_TYPE_VXLAN:
7921                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7922                 break;
7923         case I40E_TUNNEL_TYPE_NVGRE:
7924                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7925                 break;
7926         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7927                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7928                 break;
7929         case I40E_TUNNEL_TYPE_MPLSoUDP:
7930                 if (!pf->mpls_replace_flag) {
7931                         i40e_replace_mpls_l1_filter(pf);
7932                         i40e_replace_mpls_cloud_filter(pf);
7933                         pf->mpls_replace_flag = 1;
7934                 }
7935                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7936                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7937                         teid_le >> 4;
7938                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7939                         (teid_le & 0xF) << 12;
7940                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7941                         0x40;
7942                 big_buffer = 1;
7943                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7944                 break;
7945         case I40E_TUNNEL_TYPE_MPLSoGRE:
7946                 if (!pf->mpls_replace_flag) {
7947                         i40e_replace_mpls_l1_filter(pf);
7948                         i40e_replace_mpls_cloud_filter(pf);
7949                         pf->mpls_replace_flag = 1;
7950                 }
7951                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7952                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7953                         teid_le >> 4;
7954                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7955                         (teid_le & 0xF) << 12;
7956                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7957                         0x0;
7958                 big_buffer = 1;
7959                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7960                 break;
7961         case I40E_TUNNEL_TYPE_GTPC:
7962                 if (!pf->gtp_replace_flag) {
7963                         i40e_replace_gtp_l1_filter(pf);
7964                         i40e_replace_gtp_cloud_filter(pf);
7965                         pf->gtp_replace_flag = 1;
7966                 }
7967                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7968                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7969                         (teid_le >> 16) & 0xFFFF;
7970                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7971                         teid_le & 0xFFFF;
7972                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7973                         0x0;
7974                 big_buffer = 1;
7975                 break;
7976         case I40E_TUNNEL_TYPE_GTPU:
7977                 if (!pf->gtp_replace_flag) {
7978                         i40e_replace_gtp_l1_filter(pf);
7979                         i40e_replace_gtp_cloud_filter(pf);
7980                         pf->gtp_replace_flag = 1;
7981                 }
7982                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7983                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7984                         (teid_le >> 16) & 0xFFFF;
7985                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7986                         teid_le & 0xFFFF;
7987                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7988                         0x0;
7989                 big_buffer = 1;
7990                 break;
7991         case I40E_TUNNEL_TYPE_QINQ:
7992                 if (!pf->qinq_replace_flag) {
7993                         ret = i40e_cloud_filter_qinq_create(pf);
7994                         if (ret < 0)
7995                                 PMD_DRV_LOG(DEBUG,
7996                                             "QinQ tunnel filter already created.");
7997                         pf->qinq_replace_flag = 1;
7998                 }
7999                 /*      Add in the General fields the values of
8000                  *      the Outer and Inner VLAN
8001                  *      Big Buffer should be set, see changes in
8002                  *      i40e_aq_add_cloud_filters
8003                  */
8004                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8005                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8006                 big_buffer = 1;
8007                 break;
8008         default:
8009                 /* Other tunnel types is not supported. */
8010                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8011                 rte_free(cld_filter);
8012                 return -EINVAL;
8013         }
8014
8015         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8016                 pfilter->element.flags =
8017                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8018         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8019                 pfilter->element.flags =
8020                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8021         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8022                 pfilter->element.flags =
8023                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8024         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8025                 pfilter->element.flags =
8026                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8027         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8028                 pfilter->element.flags |=
8029                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8030         else {
8031                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8032                                                 &pfilter->element.flags);
8033                 if (val < 0) {
8034                         rte_free(cld_filter);
8035                         return -EINVAL;
8036                 }
8037         }
8038
8039         pfilter->element.flags |= rte_cpu_to_le_16(
8040                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8041                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8042         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8043         pfilter->element.queue_number =
8044                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8045
8046         if (!tunnel_filter->is_to_vf)
8047                 vsi = pf->main_vsi;
8048         else {
8049                 if (tunnel_filter->vf_id >= pf->vf_num) {
8050                         PMD_DRV_LOG(ERR, "Invalid argument.");
8051                         rte_free(cld_filter);
8052                         return -EINVAL;
8053                 }
8054                 vf = &pf->vfs[tunnel_filter->vf_id];
8055                 vsi = vf->vsi;
8056         }
8057
8058         /* Check if there is the filter in SW list */
8059         memset(&check_filter, 0, sizeof(check_filter));
8060         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8061         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8062         check_filter.vf_id = tunnel_filter->vf_id;
8063         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8064         if (add && node) {
8065                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8066                 rte_free(cld_filter);
8067                 return -EINVAL;
8068         }
8069
8070         if (!add && !node) {
8071                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8072                 rte_free(cld_filter);
8073                 return -EINVAL;
8074         }
8075
8076         if (add) {
8077                 if (big_buffer)
8078                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
8079                                                    vsi->seid, cld_filter, 1);
8080                 else
8081                         ret = i40e_aq_add_cloud_filters(hw,
8082                                         vsi->seid, &cld_filter->element, 1);
8083                 if (ret < 0) {
8084                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8085                         rte_free(cld_filter);
8086                         return -ENOTSUP;
8087                 }
8088                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8089                 if (tunnel == NULL) {
8090                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8091                         rte_free(cld_filter);
8092                         return -ENOMEM;
8093                 }
8094
8095                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8096                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8097                 if (ret < 0)
8098                         rte_free(tunnel);
8099         } else {
8100                 if (big_buffer)
8101                         ret = i40e_aq_remove_cloud_filters_big_buffer(
8102                                 hw, vsi->seid, cld_filter, 1);
8103                 else
8104                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
8105                                                    &cld_filter->element, 1);
8106                 if (ret < 0) {
8107                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8108                         rte_free(cld_filter);
8109                         return -ENOTSUP;
8110                 }
8111                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8112         }
8113
8114         rte_free(cld_filter);
8115         return ret;
8116 }
8117
8118 static int
8119 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8120 {
8121         uint8_t i;
8122
8123         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8124                 if (pf->vxlan_ports[i] == port)
8125                         return i;
8126         }
8127
8128         return -1;
8129 }
8130
8131 static int
8132 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8133 {
8134         int  idx, ret;
8135         uint8_t filter_idx;
8136         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8137
8138         idx = i40e_get_vxlan_port_idx(pf, port);
8139
8140         /* Check if port already exists */
8141         if (idx >= 0) {
8142                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8143                 return -EINVAL;
8144         }
8145
8146         /* Now check if there is space to add the new port */
8147         idx = i40e_get_vxlan_port_idx(pf, 0);
8148         if (idx < 0) {
8149                 PMD_DRV_LOG(ERR,
8150                         "Maximum number of UDP ports reached, not adding port %d",
8151                         port);
8152                 return -ENOSPC;
8153         }
8154
8155         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8156                                         &filter_idx, NULL);
8157         if (ret < 0) {
8158                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8159                 return -1;
8160         }
8161
8162         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8163                          port,  filter_idx);
8164
8165         /* New port: add it and mark its index in the bitmap */
8166         pf->vxlan_ports[idx] = port;
8167         pf->vxlan_bitmap |= (1 << idx);
8168
8169         if (!(pf->flags & I40E_FLAG_VXLAN))
8170                 pf->flags |= I40E_FLAG_VXLAN;
8171
8172         return 0;
8173 }
8174
8175 static int
8176 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8177 {
8178         int idx;
8179         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8180
8181         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8182                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8183                 return -EINVAL;
8184         }
8185
8186         idx = i40e_get_vxlan_port_idx(pf, port);
8187
8188         if (idx < 0) {
8189                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8190                 return -EINVAL;
8191         }
8192
8193         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8194                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8195                 return -1;
8196         }
8197
8198         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8199                         port, idx);
8200
8201         pf->vxlan_ports[idx] = 0;
8202         pf->vxlan_bitmap &= ~(1 << idx);
8203
8204         if (!pf->vxlan_bitmap)
8205                 pf->flags &= ~I40E_FLAG_VXLAN;
8206
8207         return 0;
8208 }
8209
8210 /* Add UDP tunneling port */
8211 static int
8212 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8213                              struct rte_eth_udp_tunnel *udp_tunnel)
8214 {
8215         int ret = 0;
8216         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8217
8218         if (udp_tunnel == NULL)
8219                 return -EINVAL;
8220
8221         switch (udp_tunnel->prot_type) {
8222         case RTE_TUNNEL_TYPE_VXLAN:
8223                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8224                 break;
8225
8226         case RTE_TUNNEL_TYPE_GENEVE:
8227         case RTE_TUNNEL_TYPE_TEREDO:
8228                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8229                 ret = -1;
8230                 break;
8231
8232         default:
8233                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8234                 ret = -1;
8235                 break;
8236         }
8237
8238         return ret;
8239 }
8240
8241 /* Remove UDP tunneling port */
8242 static int
8243 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8244                              struct rte_eth_udp_tunnel *udp_tunnel)
8245 {
8246         int ret = 0;
8247         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8248
8249         if (udp_tunnel == NULL)
8250                 return -EINVAL;
8251
8252         switch (udp_tunnel->prot_type) {
8253         case RTE_TUNNEL_TYPE_VXLAN:
8254                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8255                 break;
8256         case RTE_TUNNEL_TYPE_GENEVE:
8257         case RTE_TUNNEL_TYPE_TEREDO:
8258                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8259                 ret = -1;
8260                 break;
8261         default:
8262                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8263                 ret = -1;
8264                 break;
8265         }
8266
8267         return ret;
8268 }
8269
8270 /* Calculate the maximum number of contiguous PF queues that are configured */
8271 static int
8272 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8273 {
8274         struct rte_eth_dev_data *data = pf->dev_data;
8275         int i, num;
8276         struct i40e_rx_queue *rxq;
8277
8278         num = 0;
8279         for (i = 0; i < pf->lan_nb_qps; i++) {
8280                 rxq = data->rx_queues[i];
8281                 if (rxq && rxq->q_set)
8282                         num++;
8283                 else
8284                         break;
8285         }
8286
8287         return num;
8288 }
8289
8290 /* Configure RSS */
8291 static int
8292 i40e_pf_config_rss(struct i40e_pf *pf)
8293 {
8294         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8295         struct rte_eth_rss_conf rss_conf;
8296         uint32_t i, lut = 0;
8297         uint16_t j, num;
8298
8299         /*
8300          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8301          * It's necessary to calculate the actual PF queues that are configured.
8302          */
8303         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8304                 num = i40e_pf_calc_configured_queues_num(pf);
8305         else
8306                 num = pf->dev_data->nb_rx_queues;
8307
8308         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8309         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8310                         num);
8311
8312         if (num == 0) {
8313                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8314                 return -ENOTSUP;
8315         }
8316
8317         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8318                 if (j == num)
8319                         j = 0;
8320                 lut = (lut << 8) | (j & ((0x1 <<
8321                         hw->func_caps.rss_table_entry_width) - 1));
8322                 if ((i & 3) == 3)
8323                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8324         }
8325
8326         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8327         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8328                 i40e_pf_disable_rss(pf);
8329                 return 0;
8330         }
8331         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8332                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8333                 /* Random default keys */
8334                 static uint32_t rss_key_default[] = {0x6b793944,
8335                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8336                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8337                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8338
8339                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8340                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8341                                                         sizeof(uint32_t);
8342         }
8343
8344         return i40e_hw_rss_hash_set(pf, &rss_conf);
8345 }
8346
8347 static int
8348 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8349                                struct rte_eth_tunnel_filter_conf *filter)
8350 {
8351         if (pf == NULL || filter == NULL) {
8352                 PMD_DRV_LOG(ERR, "Invalid parameter");
8353                 return -EINVAL;
8354         }
8355
8356         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8357                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8358                 return -EINVAL;
8359         }
8360
8361         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8362                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8363                 return -EINVAL;
8364         }
8365
8366         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8367                 (is_zero_ether_addr(&filter->outer_mac))) {
8368                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8369                 return -EINVAL;
8370         }
8371
8372         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8373                 (is_zero_ether_addr(&filter->inner_mac))) {
8374                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8375                 return -EINVAL;
8376         }
8377
8378         return 0;
8379 }
8380
8381 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8382 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8383 static int
8384 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8385 {
8386         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8387         uint32_t val, reg;
8388         int ret = -EINVAL;
8389
8390         if (pf->support_multi_driver) {
8391                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8392                 return -ENOTSUP;
8393         }
8394
8395         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8396         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8397
8398         if (len == 3) {
8399                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8400         } else if (len == 4) {
8401                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8402         } else {
8403                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8404                 return ret;
8405         }
8406
8407         if (reg != val) {
8408                 ret = i40e_aq_debug_write_global_register(hw,
8409                                                    I40E_GL_PRS_FVBM(2),
8410                                                    reg, NULL);
8411                 if (ret != 0)
8412                         return ret;
8413                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8414                             "with value 0x%08x",
8415                             I40E_GL_PRS_FVBM(2), reg);
8416         } else {
8417                 ret = 0;
8418         }
8419         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8420                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8421
8422         return ret;
8423 }
8424
8425 static int
8426 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8427 {
8428         int ret = -EINVAL;
8429
8430         if (!hw || !cfg)
8431                 return -EINVAL;
8432
8433         switch (cfg->cfg_type) {
8434         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8435                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8436                 break;
8437         default:
8438                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8439                 break;
8440         }
8441
8442         return ret;
8443 }
8444
8445 static int
8446 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8447                                enum rte_filter_op filter_op,
8448                                void *arg)
8449 {
8450         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8451         int ret = I40E_ERR_PARAM;
8452
8453         switch (filter_op) {
8454         case RTE_ETH_FILTER_SET:
8455                 ret = i40e_dev_global_config_set(hw,
8456                         (struct rte_eth_global_cfg *)arg);
8457                 break;
8458         default:
8459                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8460                 break;
8461         }
8462
8463         return ret;
8464 }
8465
8466 static int
8467 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8468                           enum rte_filter_op filter_op,
8469                           void *arg)
8470 {
8471         struct rte_eth_tunnel_filter_conf *filter;
8472         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8473         int ret = I40E_SUCCESS;
8474
8475         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8476
8477         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8478                 return I40E_ERR_PARAM;
8479
8480         switch (filter_op) {
8481         case RTE_ETH_FILTER_NOP:
8482                 if (!(pf->flags & I40E_FLAG_VXLAN))
8483                         ret = I40E_NOT_SUPPORTED;
8484                 break;
8485         case RTE_ETH_FILTER_ADD:
8486                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8487                 break;
8488         case RTE_ETH_FILTER_DELETE:
8489                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8490                 break;
8491         default:
8492                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8493                 ret = I40E_ERR_PARAM;
8494                 break;
8495         }
8496
8497         return ret;
8498 }
8499
8500 static int
8501 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8502 {
8503         int ret = 0;
8504         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8505
8506         /* RSS setup */
8507         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8508                 ret = i40e_pf_config_rss(pf);
8509         else
8510                 i40e_pf_disable_rss(pf);
8511
8512         return ret;
8513 }
8514
8515 /* Get the symmetric hash enable configurations per port */
8516 static void
8517 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8518 {
8519         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8520
8521         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8522 }
8523
8524 /* Set the symmetric hash enable configurations per port */
8525 static void
8526 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8527 {
8528         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8529
8530         if (enable > 0) {
8531                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8532                         PMD_DRV_LOG(INFO,
8533                                 "Symmetric hash has already been enabled");
8534                         return;
8535                 }
8536                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8537         } else {
8538                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8539                         PMD_DRV_LOG(INFO,
8540                                 "Symmetric hash has already been disabled");
8541                         return;
8542                 }
8543                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8544         }
8545         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8546         I40E_WRITE_FLUSH(hw);
8547 }
8548
8549 /*
8550  * Get global configurations of hash function type and symmetric hash enable
8551  * per flow type (pctype). Note that global configuration means it affects all
8552  * the ports on the same NIC.
8553  */
8554 static int
8555 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8556                                    struct rte_eth_hash_global_conf *g_cfg)
8557 {
8558         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8559         uint32_t reg;
8560         uint16_t i, j;
8561
8562         memset(g_cfg, 0, sizeof(*g_cfg));
8563         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8564         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8565                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8566         else
8567                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8568         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8569                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8570
8571         /*
8572          * As i40e supports less than 64 flow types, only first 64 bits need to
8573          * be checked.
8574          */
8575         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8576                 g_cfg->valid_bit_mask[i] = 0ULL;
8577                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8578         }
8579
8580         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8581
8582         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8583                 if (!adapter->pctypes_tbl[i])
8584                         continue;
8585                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8586                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8587                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8588                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8589                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8590                                         g_cfg->sym_hash_enable_mask[0] |=
8591                                                                 (1ULL << i);
8592                                 }
8593                         }
8594                 }
8595         }
8596
8597         return 0;
8598 }
8599
8600 static int
8601 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8602                               const struct rte_eth_hash_global_conf *g_cfg)
8603 {
8604         uint32_t i;
8605         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8606
8607         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8608                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8609                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8610                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8611                                                 g_cfg->hash_func);
8612                 return -EINVAL;
8613         }
8614
8615         /*
8616          * As i40e supports less than 64 flow types, only first 64 bits need to
8617          * be checked.
8618          */
8619         mask0 = g_cfg->valid_bit_mask[0];
8620         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8621                 if (i == 0) {
8622                         /* Check if any unsupported flow type configured */
8623                         if ((mask0 | i40e_mask) ^ i40e_mask)
8624                                 goto mask_err;
8625                 } else {
8626                         if (g_cfg->valid_bit_mask[i])
8627                                 goto mask_err;
8628                 }
8629         }
8630
8631         return 0;
8632
8633 mask_err:
8634         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8635
8636         return -EINVAL;
8637 }
8638
8639 /*
8640  * Set global configurations of hash function type and symmetric hash enable
8641  * per flow type (pctype). Note any modifying global configuration will affect
8642  * all the ports on the same NIC.
8643  */
8644 static int
8645 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8646                                    struct rte_eth_hash_global_conf *g_cfg)
8647 {
8648         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8649         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8650         int ret;
8651         uint16_t i, j;
8652         uint32_t reg;
8653         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8654
8655         if (pf->support_multi_driver) {
8656                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8657                 return -ENOTSUP;
8658         }
8659
8660         /* Check the input parameters */
8661         ret = i40e_hash_global_config_check(adapter, g_cfg);
8662         if (ret < 0)
8663                 return ret;
8664
8665         /*
8666          * As i40e supports less than 64 flow types, only first 64 bits need to
8667          * be configured.
8668          */
8669         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8670                 if (mask0 & (1UL << i)) {
8671                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8672                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8673
8674                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8675                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8676                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8677                                         i40e_write_global_rx_ctl(hw,
8678                                                           I40E_GLQF_HSYM(j),
8679                                                           reg);
8680                         }
8681                 }
8682         }
8683
8684         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8685         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8686                 /* Toeplitz */
8687                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8688                         PMD_DRV_LOG(DEBUG,
8689                                 "Hash function already set to Toeplitz");
8690                         goto out;
8691                 }
8692                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8693         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8694                 /* Simple XOR */
8695                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8696                         PMD_DRV_LOG(DEBUG,
8697                                 "Hash function already set to Simple XOR");
8698                         goto out;
8699                 }
8700                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8701         } else
8702                 /* Use the default, and keep it as it is */
8703                 goto out;
8704
8705         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8706
8707 out:
8708         I40E_WRITE_FLUSH(hw);
8709
8710         return 0;
8711 }
8712
8713 /**
8714  * Valid input sets for hash and flow director filters per PCTYPE
8715  */
8716 static uint64_t
8717 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8718                 enum rte_filter_type filter)
8719 {
8720         uint64_t valid;
8721
8722         static const uint64_t valid_hash_inset_table[] = {
8723                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8724                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8725                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8726                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8727                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8728                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8729                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8730                         I40E_INSET_FLEX_PAYLOAD,
8731                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8732                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8733                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8734                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8735                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8736                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8737                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8738                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8739                         I40E_INSET_FLEX_PAYLOAD,
8740                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8741                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8742                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8743                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8744                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8745                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8746                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8747                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8748                         I40E_INSET_FLEX_PAYLOAD,
8749                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8750                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8751                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8752                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8753                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8754                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8755                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8756                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8757                         I40E_INSET_FLEX_PAYLOAD,
8758                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8759                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8760                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8761                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8762                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8763                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8764                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8765                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8766                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8767                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8768                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8769                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8770                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8771                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8772                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8773                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8774                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8775                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8776                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8777                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8778                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8779                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8780                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8781                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8782                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8783                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8784                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8785                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8786                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8787                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8788                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8789                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8790                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8791                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8792                         I40E_INSET_FLEX_PAYLOAD,
8793                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8794                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8795                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8796                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8797                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8798                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8799                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8800                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8801                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8802                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8803                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8804                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8805                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8806                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8807                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8808                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8809                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8810                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8811                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8812                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8813                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8814                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8815                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8816                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8817                         I40E_INSET_FLEX_PAYLOAD,
8818                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8819                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8820                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8821                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8822                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8823                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8824                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8825                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8826                         I40E_INSET_FLEX_PAYLOAD,
8827                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8828                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8829                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8830                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8831                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8832                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8833                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8834                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8835                         I40E_INSET_FLEX_PAYLOAD,
8836                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8837                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8838                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8839                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8840                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8841                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8842                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8843                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8844                         I40E_INSET_FLEX_PAYLOAD,
8845                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8846                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8847                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8848                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8849                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8850                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8851                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8852                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8853                         I40E_INSET_FLEX_PAYLOAD,
8854                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8855                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8856                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8857                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8858                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8859                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8860                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8861                         I40E_INSET_FLEX_PAYLOAD,
8862                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8863                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8864                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8865                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8866                         I40E_INSET_FLEX_PAYLOAD,
8867         };
8868
8869         /**
8870          * Flow director supports only fields defined in
8871          * union rte_eth_fdir_flow.
8872          */
8873         static const uint64_t valid_fdir_inset_table[] = {
8874                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8875                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8876                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8877                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8878                 I40E_INSET_IPV4_TTL,
8879                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8880                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8881                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8882                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8883                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8884                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8885                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8886                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8887                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8888                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8889                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8890                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8891                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8892                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8893                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8894                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8895                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8896                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8897                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8898                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8899                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8900                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8901                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8902                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8903                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8904                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8905                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8906                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8907                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8908                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8909                 I40E_INSET_SCTP_VT,
8910                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8911                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8912                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8913                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8914                 I40E_INSET_IPV4_TTL,
8915                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8916                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8917                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8918                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8919                 I40E_INSET_IPV6_HOP_LIMIT,
8920                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8921                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8922                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8923                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8924                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8925                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8926                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8927                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8928                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8929                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8930                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8931                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8932                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8933                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8934                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8935                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8936                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8937                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8938                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8939                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8940                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8941                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8942                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8943                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8944                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8945                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8946                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8947                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8948                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8949                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8950                 I40E_INSET_SCTP_VT,
8951                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8952                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8953                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8954                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8955                 I40E_INSET_IPV6_HOP_LIMIT,
8956                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8957                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8958                 I40E_INSET_LAST_ETHER_TYPE,
8959         };
8960
8961         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8962                 return 0;
8963         if (filter == RTE_ETH_FILTER_HASH)
8964                 valid = valid_hash_inset_table[pctype];
8965         else
8966                 valid = valid_fdir_inset_table[pctype];
8967
8968         return valid;
8969 }
8970
8971 /**
8972  * Validate if the input set is allowed for a specific PCTYPE
8973  */
8974 int
8975 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8976                 enum rte_filter_type filter, uint64_t inset)
8977 {
8978         uint64_t valid;
8979
8980         valid = i40e_get_valid_input_set(pctype, filter);
8981         if (inset & (~valid))
8982                 return -EINVAL;
8983
8984         return 0;
8985 }
8986
8987 /* default input set fields combination per pctype */
8988 uint64_t
8989 i40e_get_default_input_set(uint16_t pctype)
8990 {
8991         static const uint64_t default_inset_table[] = {
8992                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8993                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8994                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8995                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8996                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8997                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8998                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8999                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9000                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9001                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9002                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9003                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9004                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9005                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9006                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9007                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9008                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9009                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9010                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9011                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9012                         I40E_INSET_SCTP_VT,
9013                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9014                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9015                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9016                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9017                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9018                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9019                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9020                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9021                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9022                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9023                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9024                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9025                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9026                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9027                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9028                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9029                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9030                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9031                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9032                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9033                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9034                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9035                         I40E_INSET_SCTP_VT,
9036                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9037                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9038                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9039                         I40E_INSET_LAST_ETHER_TYPE,
9040         };
9041
9042         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9043                 return 0;
9044
9045         return default_inset_table[pctype];
9046 }
9047
9048 /**
9049  * Parse the input set from index to logical bit masks
9050  */
9051 static int
9052 i40e_parse_input_set(uint64_t *inset,
9053                      enum i40e_filter_pctype pctype,
9054                      enum rte_eth_input_set_field *field,
9055                      uint16_t size)
9056 {
9057         uint16_t i, j;
9058         int ret = -EINVAL;
9059
9060         static const struct {
9061                 enum rte_eth_input_set_field field;
9062                 uint64_t inset;
9063         } inset_convert_table[] = {
9064                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9065                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9066                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9067                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9068                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9069                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9070                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9071                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9072                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9073                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9074                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9075                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9076                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9077                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9078                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9079                         I40E_INSET_IPV6_NEXT_HDR},
9080                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9081                         I40E_INSET_IPV6_HOP_LIMIT},
9082                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9083                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9084                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9085                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9086                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9087                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9088                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9089                         I40E_INSET_SCTP_VT},
9090                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9091                         I40E_INSET_TUNNEL_DMAC},
9092                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9093                         I40E_INSET_VLAN_TUNNEL},
9094                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9095                         I40E_INSET_TUNNEL_ID},
9096                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9097                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9098                         I40E_INSET_FLEX_PAYLOAD_W1},
9099                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9100                         I40E_INSET_FLEX_PAYLOAD_W2},
9101                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9102                         I40E_INSET_FLEX_PAYLOAD_W3},
9103                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9104                         I40E_INSET_FLEX_PAYLOAD_W4},
9105                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9106                         I40E_INSET_FLEX_PAYLOAD_W5},
9107                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9108                         I40E_INSET_FLEX_PAYLOAD_W6},
9109                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9110                         I40E_INSET_FLEX_PAYLOAD_W7},
9111                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9112                         I40E_INSET_FLEX_PAYLOAD_W8},
9113         };
9114
9115         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9116                 return ret;
9117
9118         /* Only one item allowed for default or all */
9119         if (size == 1) {
9120                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9121                         *inset = i40e_get_default_input_set(pctype);
9122                         return 0;
9123                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9124                         *inset = I40E_INSET_NONE;
9125                         return 0;
9126                 }
9127         }
9128
9129         for (i = 0, *inset = 0; i < size; i++) {
9130                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9131                         if (field[i] == inset_convert_table[j].field) {
9132                                 *inset |= inset_convert_table[j].inset;
9133                                 break;
9134                         }
9135                 }
9136
9137                 /* It contains unsupported input set, return immediately */
9138                 if (j == RTE_DIM(inset_convert_table))
9139                         return ret;
9140         }
9141
9142         return 0;
9143 }
9144
9145 /**
9146  * Translate the input set from bit masks to register aware bit masks
9147  * and vice versa
9148  */
9149 uint64_t
9150 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9151 {
9152         uint64_t val = 0;
9153         uint16_t i;
9154
9155         struct inset_map {
9156                 uint64_t inset;
9157                 uint64_t inset_reg;
9158         };
9159
9160         static const struct inset_map inset_map_common[] = {
9161                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9162                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9163                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9164                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9165                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9166                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9167                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9168                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9169                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9170                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9171                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9172                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9173                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9174                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9175                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9176                 {I40E_INSET_TUNNEL_DMAC,
9177                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9178                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9179                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9180                 {I40E_INSET_TUNNEL_SRC_PORT,
9181                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9182                 {I40E_INSET_TUNNEL_DST_PORT,
9183                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9184                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9185                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9186                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9187                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9188                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9189                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9190                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9191                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9192                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9193         };
9194
9195     /* some different registers map in x722*/
9196         static const struct inset_map inset_map_diff_x722[] = {
9197                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9198                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9199                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9200                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9201         };
9202
9203         static const struct inset_map inset_map_diff_not_x722[] = {
9204                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9205                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9206                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9207                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9208         };
9209
9210         if (input == 0)
9211                 return val;
9212
9213         /* Translate input set to register aware inset */
9214         if (type == I40E_MAC_X722) {
9215                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9216                         if (input & inset_map_diff_x722[i].inset)
9217                                 val |= inset_map_diff_x722[i].inset_reg;
9218                 }
9219         } else {
9220                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9221                         if (input & inset_map_diff_not_x722[i].inset)
9222                                 val |= inset_map_diff_not_x722[i].inset_reg;
9223                 }
9224         }
9225
9226         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9227                 if (input & inset_map_common[i].inset)
9228                         val |= inset_map_common[i].inset_reg;
9229         }
9230
9231         return val;
9232 }
9233
9234 int
9235 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9236 {
9237         uint8_t i, idx = 0;
9238         uint64_t inset_need_mask = inset;
9239
9240         static const struct {
9241                 uint64_t inset;
9242                 uint32_t mask;
9243         } inset_mask_map[] = {
9244                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9245                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9246                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9247                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9248                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9249                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9250                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9251                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9252         };
9253
9254         if (!inset || !mask || !nb_elem)
9255                 return 0;
9256
9257         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9258                 /* Clear the inset bit, if no MASK is required,
9259                  * for example proto + ttl
9260                  */
9261                 if ((inset & inset_mask_map[i].inset) ==
9262                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9263                         inset_need_mask &= ~inset_mask_map[i].inset;
9264                 if (!inset_need_mask)
9265                         return 0;
9266         }
9267         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9268                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9269                     inset_mask_map[i].inset) {
9270                         if (idx >= nb_elem) {
9271                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9272                                 return -EINVAL;
9273                         }
9274                         mask[idx] = inset_mask_map[i].mask;
9275                         idx++;
9276                 }
9277         }
9278
9279         return idx;
9280 }
9281
9282 void
9283 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9284 {
9285         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9286
9287         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9288         if (reg != val)
9289                 i40e_write_rx_ctl(hw, addr, val);
9290         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9291                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9292 }
9293
9294 void
9295 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9296 {
9297         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9298         struct rte_eth_dev *dev;
9299
9300         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9301         if (reg != val) {
9302                 i40e_write_rx_ctl(hw, addr, val);
9303                 PMD_DRV_LOG(WARNING,
9304                             "i40e device %s changed global register [0x%08x]."
9305                             " original: 0x%08x, new: 0x%08x",
9306                             dev->device->name, addr, reg,
9307                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9308         }
9309 }
9310
9311 static void
9312 i40e_filter_input_set_init(struct i40e_pf *pf)
9313 {
9314         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9315         enum i40e_filter_pctype pctype;
9316         uint64_t input_set, inset_reg;
9317         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9318         int num, i;
9319         uint16_t flow_type;
9320
9321         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9322              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9323                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9324
9325                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9326                         continue;
9327
9328                 input_set = i40e_get_default_input_set(pctype);
9329
9330                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9331                                                    I40E_INSET_MASK_NUM_REG);
9332                 if (num < 0)
9333                         return;
9334                 if (pf->support_multi_driver && num > 0) {
9335                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9336                         return;
9337                 }
9338                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9339                                         input_set);
9340
9341                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9342                                       (uint32_t)(inset_reg & UINT32_MAX));
9343                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9344                                      (uint32_t)((inset_reg >>
9345                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9346                 if (!pf->support_multi_driver) {
9347                         i40e_check_write_global_reg(hw,
9348                                             I40E_GLQF_HASH_INSET(0, pctype),
9349                                             (uint32_t)(inset_reg & UINT32_MAX));
9350                         i40e_check_write_global_reg(hw,
9351                                              I40E_GLQF_HASH_INSET(1, pctype),
9352                                              (uint32_t)((inset_reg >>
9353                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9354
9355                         for (i = 0; i < num; i++) {
9356                                 i40e_check_write_global_reg(hw,
9357                                                     I40E_GLQF_FD_MSK(i, pctype),
9358                                                     mask_reg[i]);
9359                                 i40e_check_write_global_reg(hw,
9360                                                   I40E_GLQF_HASH_MSK(i, pctype),
9361                                                   mask_reg[i]);
9362                         }
9363                         /*clear unused mask registers of the pctype */
9364                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9365                                 i40e_check_write_global_reg(hw,
9366                                                     I40E_GLQF_FD_MSK(i, pctype),
9367                                                     0);
9368                                 i40e_check_write_global_reg(hw,
9369                                                   I40E_GLQF_HASH_MSK(i, pctype),
9370                                                   0);
9371                         }
9372                 } else {
9373                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9374                 }
9375                 I40E_WRITE_FLUSH(hw);
9376
9377                 /* store the default input set */
9378                 if (!pf->support_multi_driver)
9379                         pf->hash_input_set[pctype] = input_set;
9380                 pf->fdir.input_set[pctype] = input_set;
9381         }
9382 }
9383
9384 int
9385 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9386                          struct rte_eth_input_set_conf *conf)
9387 {
9388         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9389         enum i40e_filter_pctype pctype;
9390         uint64_t input_set, inset_reg = 0;
9391         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9392         int ret, i, num;
9393
9394         if (!conf) {
9395                 PMD_DRV_LOG(ERR, "Invalid pointer");
9396                 return -EFAULT;
9397         }
9398         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9399             conf->op != RTE_ETH_INPUT_SET_ADD) {
9400                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9401                 return -EINVAL;
9402         }
9403
9404         if (pf->support_multi_driver) {
9405                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9406                 return -ENOTSUP;
9407         }
9408
9409         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9410         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9411                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9412                 return -EINVAL;
9413         }
9414
9415         if (hw->mac.type == I40E_MAC_X722) {
9416                 /* get translated pctype value in fd pctype register */
9417                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9418                         I40E_GLQF_FD_PCTYPES((int)pctype));
9419         }
9420
9421         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9422                                    conf->inset_size);
9423         if (ret) {
9424                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9425                 return -EINVAL;
9426         }
9427
9428         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9429                 /* get inset value in register */
9430                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9431                 inset_reg <<= I40E_32_BIT_WIDTH;
9432                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9433                 input_set |= pf->hash_input_set[pctype];
9434         }
9435         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9436                                            I40E_INSET_MASK_NUM_REG);
9437         if (num < 0)
9438                 return -EINVAL;
9439
9440         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9441
9442         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9443                                     (uint32_t)(inset_reg & UINT32_MAX));
9444         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9445                                     (uint32_t)((inset_reg >>
9446                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9447
9448         for (i = 0; i < num; i++)
9449                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9450                                             mask_reg[i]);
9451         /*clear unused mask registers of the pctype */
9452         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9453                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9454                                             0);
9455         I40E_WRITE_FLUSH(hw);
9456
9457         pf->hash_input_set[pctype] = input_set;
9458         return 0;
9459 }
9460
9461 int
9462 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9463                          struct rte_eth_input_set_conf *conf)
9464 {
9465         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9466         enum i40e_filter_pctype pctype;
9467         uint64_t input_set, inset_reg = 0;
9468         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9469         int ret, i, num;
9470
9471         if (!hw || !conf) {
9472                 PMD_DRV_LOG(ERR, "Invalid pointer");
9473                 return -EFAULT;
9474         }
9475         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9476             conf->op != RTE_ETH_INPUT_SET_ADD) {
9477                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9478                 return -EINVAL;
9479         }
9480
9481         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9482
9483         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9484                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9485                 return -EINVAL;
9486         }
9487
9488         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9489                                    conf->inset_size);
9490         if (ret) {
9491                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9492                 return -EINVAL;
9493         }
9494
9495         /* get inset value in register */
9496         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9497         inset_reg <<= I40E_32_BIT_WIDTH;
9498         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9499
9500         /* Can not change the inset reg for flex payload for fdir,
9501          * it is done by writing I40E_PRTQF_FD_FLXINSET
9502          * in i40e_set_flex_mask_on_pctype.
9503          */
9504         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9505                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9506         else
9507                 input_set |= pf->fdir.input_set[pctype];
9508         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9509                                            I40E_INSET_MASK_NUM_REG);
9510         if (num < 0)
9511                 return -EINVAL;
9512         if (pf->support_multi_driver && num > 0) {
9513                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9514                 return -ENOTSUP;
9515         }
9516
9517         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9518
9519         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9520                               (uint32_t)(inset_reg & UINT32_MAX));
9521         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9522                              (uint32_t)((inset_reg >>
9523                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9524
9525         if (!pf->support_multi_driver) {
9526                 for (i = 0; i < num; i++)
9527                         i40e_check_write_global_reg(hw,
9528                                                     I40E_GLQF_FD_MSK(i, pctype),
9529                                                     mask_reg[i]);
9530                 /*clear unused mask registers of the pctype */
9531                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9532                         i40e_check_write_global_reg(hw,
9533                                                     I40E_GLQF_FD_MSK(i, pctype),
9534                                                     0);
9535         } else {
9536                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9537         }
9538         I40E_WRITE_FLUSH(hw);
9539
9540         pf->fdir.input_set[pctype] = input_set;
9541         return 0;
9542 }
9543
9544 static int
9545 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9546 {
9547         int ret = 0;
9548
9549         if (!hw || !info) {
9550                 PMD_DRV_LOG(ERR, "Invalid pointer");
9551                 return -EFAULT;
9552         }
9553
9554         switch (info->info_type) {
9555         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9556                 i40e_get_symmetric_hash_enable_per_port(hw,
9557                                         &(info->info.enable));
9558                 break;
9559         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9560                 ret = i40e_get_hash_filter_global_config(hw,
9561                                 &(info->info.global_conf));
9562                 break;
9563         default:
9564                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9565                                                         info->info_type);
9566                 ret = -EINVAL;
9567                 break;
9568         }
9569
9570         return ret;
9571 }
9572
9573 static int
9574 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9575 {
9576         int ret = 0;
9577
9578         if (!hw || !info) {
9579                 PMD_DRV_LOG(ERR, "Invalid pointer");
9580                 return -EFAULT;
9581         }
9582
9583         switch (info->info_type) {
9584         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9585                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9586                 break;
9587         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9588                 ret = i40e_set_hash_filter_global_config(hw,
9589                                 &(info->info.global_conf));
9590                 break;
9591         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9592                 ret = i40e_hash_filter_inset_select(hw,
9593                                                &(info->info.input_set_conf));
9594                 break;
9595
9596         default:
9597                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9598                                                         info->info_type);
9599                 ret = -EINVAL;
9600                 break;
9601         }
9602
9603         return ret;
9604 }
9605
9606 /* Operations for hash function */
9607 static int
9608 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9609                       enum rte_filter_op filter_op,
9610                       void *arg)
9611 {
9612         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9613         int ret = 0;
9614
9615         switch (filter_op) {
9616         case RTE_ETH_FILTER_NOP:
9617                 break;
9618         case RTE_ETH_FILTER_GET:
9619                 ret = i40e_hash_filter_get(hw,
9620                         (struct rte_eth_hash_filter_info *)arg);
9621                 break;
9622         case RTE_ETH_FILTER_SET:
9623                 ret = i40e_hash_filter_set(hw,
9624                         (struct rte_eth_hash_filter_info *)arg);
9625                 break;
9626         default:
9627                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9628                                                                 filter_op);
9629                 ret = -ENOTSUP;
9630                 break;
9631         }
9632
9633         return ret;
9634 }
9635
9636 /* Convert ethertype filter structure */
9637 static int
9638 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9639                               struct i40e_ethertype_filter *filter)
9640 {
9641         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9642         filter->input.ether_type = input->ether_type;
9643         filter->flags = input->flags;
9644         filter->queue = input->queue;
9645
9646         return 0;
9647 }
9648
9649 /* Check if there exists the ehtertype filter */
9650 struct i40e_ethertype_filter *
9651 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9652                                 const struct i40e_ethertype_filter_input *input)
9653 {
9654         int ret;
9655
9656         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9657         if (ret < 0)
9658                 return NULL;
9659
9660         return ethertype_rule->hash_map[ret];
9661 }
9662
9663 /* Add ethertype filter in SW list */
9664 static int
9665 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9666                                 struct i40e_ethertype_filter *filter)
9667 {
9668         struct i40e_ethertype_rule *rule = &pf->ethertype;
9669         int ret;
9670
9671         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9672         if (ret < 0) {
9673                 PMD_DRV_LOG(ERR,
9674                             "Failed to insert ethertype filter"
9675                             " to hash table %d!",
9676                             ret);
9677                 return ret;
9678         }
9679         rule->hash_map[ret] = filter;
9680
9681         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9682
9683         return 0;
9684 }
9685
9686 /* Delete ethertype filter in SW list */
9687 int
9688 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9689                              struct i40e_ethertype_filter_input *input)
9690 {
9691         struct i40e_ethertype_rule *rule = &pf->ethertype;
9692         struct i40e_ethertype_filter *filter;
9693         int ret;
9694
9695         ret = rte_hash_del_key(rule->hash_table, input);
9696         if (ret < 0) {
9697                 PMD_DRV_LOG(ERR,
9698                             "Failed to delete ethertype filter"
9699                             " to hash table %d!",
9700                             ret);
9701                 return ret;
9702         }
9703         filter = rule->hash_map[ret];
9704         rule->hash_map[ret] = NULL;
9705
9706         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9707         rte_free(filter);
9708
9709         return 0;
9710 }
9711
9712 /*
9713  * Configure ethertype filter, which can director packet by filtering
9714  * with mac address and ether_type or only ether_type
9715  */
9716 int
9717 i40e_ethertype_filter_set(struct i40e_pf *pf,
9718                         struct rte_eth_ethertype_filter *filter,
9719                         bool add)
9720 {
9721         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9722         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9723         struct i40e_ethertype_filter *ethertype_filter, *node;
9724         struct i40e_ethertype_filter check_filter;
9725         struct i40e_control_filter_stats stats;
9726         uint16_t flags = 0;
9727         int ret;
9728
9729         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9730                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9731                 return -EINVAL;
9732         }
9733         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9734                 filter->ether_type == ETHER_TYPE_IPv6) {
9735                 PMD_DRV_LOG(ERR,
9736                         "unsupported ether_type(0x%04x) in control packet filter.",
9737                         filter->ether_type);
9738                 return -EINVAL;
9739         }
9740         if (filter->ether_type == ETHER_TYPE_VLAN)
9741                 PMD_DRV_LOG(WARNING,
9742                         "filter vlan ether_type in first tag is not supported.");
9743
9744         /* Check if there is the filter in SW list */
9745         memset(&check_filter, 0, sizeof(check_filter));
9746         i40e_ethertype_filter_convert(filter, &check_filter);
9747         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9748                                                &check_filter.input);
9749         if (add && node) {
9750                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9751                 return -EINVAL;
9752         }
9753
9754         if (!add && !node) {
9755                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9756                 return -EINVAL;
9757         }
9758
9759         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9760                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9761         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9762                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9763         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9764
9765         memset(&stats, 0, sizeof(stats));
9766         ret = i40e_aq_add_rem_control_packet_filter(hw,
9767                         filter->mac_addr.addr_bytes,
9768                         filter->ether_type, flags,
9769                         pf->main_vsi->seid,
9770                         filter->queue, add, &stats, NULL);
9771
9772         PMD_DRV_LOG(INFO,
9773                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9774                 ret, stats.mac_etype_used, stats.etype_used,
9775                 stats.mac_etype_free, stats.etype_free);
9776         if (ret < 0)
9777                 return -ENOSYS;
9778
9779         /* Add or delete a filter in SW list */
9780         if (add) {
9781                 ethertype_filter = rte_zmalloc("ethertype_filter",
9782                                        sizeof(*ethertype_filter), 0);
9783                 if (ethertype_filter == NULL) {
9784                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9785                         return -ENOMEM;
9786                 }
9787
9788                 rte_memcpy(ethertype_filter, &check_filter,
9789                            sizeof(check_filter));
9790                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9791                 if (ret < 0)
9792                         rte_free(ethertype_filter);
9793         } else {
9794                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9795         }
9796
9797         return ret;
9798 }
9799
9800 /*
9801  * Handle operations for ethertype filter.
9802  */
9803 static int
9804 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9805                                 enum rte_filter_op filter_op,
9806                                 void *arg)
9807 {
9808         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9809         int ret = 0;
9810
9811         if (filter_op == RTE_ETH_FILTER_NOP)
9812                 return ret;
9813
9814         if (arg == NULL) {
9815                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9816                             filter_op);
9817                 return -EINVAL;
9818         }
9819
9820         switch (filter_op) {
9821         case RTE_ETH_FILTER_ADD:
9822                 ret = i40e_ethertype_filter_set(pf,
9823                         (struct rte_eth_ethertype_filter *)arg,
9824                         TRUE);
9825                 break;
9826         case RTE_ETH_FILTER_DELETE:
9827                 ret = i40e_ethertype_filter_set(pf,
9828                         (struct rte_eth_ethertype_filter *)arg,
9829                         FALSE);
9830                 break;
9831         default:
9832                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9833                 ret = -ENOSYS;
9834                 break;
9835         }
9836         return ret;
9837 }
9838
9839 static int
9840 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9841                      enum rte_filter_type filter_type,
9842                      enum rte_filter_op filter_op,
9843                      void *arg)
9844 {
9845         int ret = 0;
9846
9847         if (dev == NULL)
9848                 return -EINVAL;
9849
9850         switch (filter_type) {
9851         case RTE_ETH_FILTER_NONE:
9852                 /* For global configuration */
9853                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9854                 break;
9855         case RTE_ETH_FILTER_HASH:
9856                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9857                 break;
9858         case RTE_ETH_FILTER_MACVLAN:
9859                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9860                 break;
9861         case RTE_ETH_FILTER_ETHERTYPE:
9862                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9863                 break;
9864         case RTE_ETH_FILTER_TUNNEL:
9865                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9866                 break;
9867         case RTE_ETH_FILTER_FDIR:
9868                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9869                 break;
9870         case RTE_ETH_FILTER_GENERIC:
9871                 if (filter_op != RTE_ETH_FILTER_GET)
9872                         return -EINVAL;
9873                 *(const void **)arg = &i40e_flow_ops;
9874                 break;
9875         default:
9876                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9877                                                         filter_type);
9878                 ret = -EINVAL;
9879                 break;
9880         }
9881
9882         return ret;
9883 }
9884
9885 /*
9886  * Check and enable Extended Tag.
9887  * Enabling Extended Tag is important for 40G performance.
9888  */
9889 static void
9890 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9891 {
9892         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9893         uint32_t buf = 0;
9894         int ret;
9895
9896         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9897                                       PCI_DEV_CAP_REG);
9898         if (ret < 0) {
9899                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9900                             PCI_DEV_CAP_REG);
9901                 return;
9902         }
9903         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9904                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9905                 return;
9906         }
9907
9908         buf = 0;
9909         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9910                                       PCI_DEV_CTRL_REG);
9911         if (ret < 0) {
9912                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9913                             PCI_DEV_CTRL_REG);
9914                 return;
9915         }
9916         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9917                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9918                 return;
9919         }
9920         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9921         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9922                                        PCI_DEV_CTRL_REG);
9923         if (ret < 0) {
9924                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9925                             PCI_DEV_CTRL_REG);
9926                 return;
9927         }
9928 }
9929
9930 /*
9931  * As some registers wouldn't be reset unless a global hardware reset,
9932  * hardware initialization is needed to put those registers into an
9933  * expected initial state.
9934  */
9935 static void
9936 i40e_hw_init(struct rte_eth_dev *dev)
9937 {
9938         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9939
9940         i40e_enable_extended_tag(dev);
9941
9942         /* clear the PF Queue Filter control register */
9943         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9944
9945         /* Disable symmetric hash per port */
9946         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9947 }
9948
9949 /*
9950  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9951  * however this function will return only one highest pctype index,
9952  * which is not quite correct. This is known problem of i40e driver
9953  * and needs to be fixed later.
9954  */
9955 enum i40e_filter_pctype
9956 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9957 {
9958         int i;
9959         uint64_t pctype_mask;
9960
9961         if (flow_type < I40E_FLOW_TYPE_MAX) {
9962                 pctype_mask = adapter->pctypes_tbl[flow_type];
9963                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9964                         if (pctype_mask & (1ULL << i))
9965                                 return (enum i40e_filter_pctype)i;
9966                 }
9967         }
9968         return I40E_FILTER_PCTYPE_INVALID;
9969 }
9970
9971 uint16_t
9972 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9973                         enum i40e_filter_pctype pctype)
9974 {
9975         uint16_t flowtype;
9976         uint64_t pctype_mask = 1ULL << pctype;
9977
9978         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9979              flowtype++) {
9980                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9981                         return flowtype;
9982         }
9983
9984         return RTE_ETH_FLOW_UNKNOWN;
9985 }
9986
9987 /*
9988  * On X710, performance number is far from the expectation on recent firmware
9989  * versions; on XL710, performance number is also far from the expectation on
9990  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9991  * mode is enabled and port MAC address is equal to the packet destination MAC
9992  * address. The fix for this issue may not be integrated in the following
9993  * firmware version. So the workaround in software driver is needed. It needs
9994  * to modify the initial values of 3 internal only registers for both X710 and
9995  * XL710. Note that the values for X710 or XL710 could be different, and the
9996  * workaround can be removed when it is fixed in firmware in the future.
9997  */
9998
9999 /* For both X710 and XL710 */
10000 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10001 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10002 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10003
10004 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10005 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10006
10007 /* For X722 */
10008 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10009 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10010
10011 /* For X710 */
10012 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10013 /* For XL710 */
10014 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10015 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10016
10017 /*
10018  * GL_SWR_PM_UP_THR:
10019  * The value is not impacted from the link speed, its value is set according
10020  * to the total number of ports for a better pipe-monitor configuration.
10021  */
10022 static bool
10023 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10024 {
10025 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10026                 .device_id = (dev),   \
10027                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10028
10029 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10030                 .device_id = (dev),   \
10031                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10032
10033         static const struct {
10034                 uint16_t device_id;
10035                 uint32_t val;
10036         } swr_pm_table[] = {
10037                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10038                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10039                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10040                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10041
10042                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10043                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10044                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10045                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10046                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10047                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10048                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10049         };
10050         uint32_t i;
10051
10052         if (value == NULL) {
10053                 PMD_DRV_LOG(ERR, "value is NULL");
10054                 return false;
10055         }
10056
10057         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10058                 if (hw->device_id == swr_pm_table[i].device_id) {
10059                         *value = swr_pm_table[i].val;
10060
10061                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10062                                     "value - 0x%08x",
10063                                     hw->device_id, *value);
10064                         return true;
10065                 }
10066         }
10067
10068         return false;
10069 }
10070
10071 static int
10072 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10073 {
10074         enum i40e_status_code status;
10075         struct i40e_aq_get_phy_abilities_resp phy_ab;
10076         int ret = -ENOTSUP;
10077         int retries = 0;
10078
10079         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10080                                               NULL);
10081
10082         while (status) {
10083                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10084                         status);
10085                 retries++;
10086                 rte_delay_us(100000);
10087                 if  (retries < 5)
10088                         status = i40e_aq_get_phy_capabilities(hw, false,
10089                                         true, &phy_ab, NULL);
10090                 else
10091                         return ret;
10092         }
10093         return 0;
10094 }
10095
10096 static void
10097 i40e_configure_registers(struct i40e_hw *hw)
10098 {
10099         static struct {
10100                 uint32_t addr;
10101                 uint64_t val;
10102         } reg_table[] = {
10103                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10104                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10105                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10106         };
10107         uint64_t reg;
10108         uint32_t i;
10109         int ret;
10110
10111         for (i = 0; i < RTE_DIM(reg_table); i++) {
10112                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10113                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10114                                 reg_table[i].val =
10115                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10116                         else /* For X710/XL710/XXV710 */
10117                                 if (hw->aq.fw_maj_ver < 6)
10118                                         reg_table[i].val =
10119                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10120                                 else
10121                                         reg_table[i].val =
10122                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10123                 }
10124
10125                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10126                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10127                                 reg_table[i].val =
10128                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10129                         else /* For X710/XL710/XXV710 */
10130                                 reg_table[i].val =
10131                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10132                 }
10133
10134                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10135                         uint32_t cfg_val;
10136
10137                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10138                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10139                                             "GL_SWR_PM_UP_THR value fixup",
10140                                             hw->device_id);
10141                                 continue;
10142                         }
10143
10144                         reg_table[i].val = cfg_val;
10145                 }
10146
10147                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10148                                                         &reg, NULL);
10149                 if (ret < 0) {
10150                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10151                                                         reg_table[i].addr);
10152                         break;
10153                 }
10154                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10155                                                 reg_table[i].addr, reg);
10156                 if (reg == reg_table[i].val)
10157                         continue;
10158
10159                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10160                                                 reg_table[i].val, NULL);
10161                 if (ret < 0) {
10162                         PMD_DRV_LOG(ERR,
10163                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10164                                 reg_table[i].val, reg_table[i].addr);
10165                         break;
10166                 }
10167                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10168                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10169         }
10170 }
10171
10172 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10173 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10174 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10175 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10176 static int
10177 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10178 {
10179         uint32_t reg;
10180         int ret;
10181
10182         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10183                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10184                 return -EINVAL;
10185         }
10186
10187         /* Configure for double VLAN RX stripping */
10188         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10189         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10190                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10191                 ret = i40e_aq_debug_write_register(hw,
10192                                                    I40E_VSI_TSR(vsi->vsi_id),
10193                                                    reg, NULL);
10194                 if (ret < 0) {
10195                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10196                                     vsi->vsi_id);
10197                         return I40E_ERR_CONFIG;
10198                 }
10199         }
10200
10201         /* Configure for double VLAN TX insertion */
10202         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10203         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10204                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10205                 ret = i40e_aq_debug_write_register(hw,
10206                                                    I40E_VSI_L2TAGSTXVALID(
10207                                                    vsi->vsi_id), reg, NULL);
10208                 if (ret < 0) {
10209                         PMD_DRV_LOG(ERR,
10210                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10211                                 vsi->vsi_id);
10212                         return I40E_ERR_CONFIG;
10213                 }
10214         }
10215
10216         return 0;
10217 }
10218
10219 /**
10220  * i40e_aq_add_mirror_rule
10221  * @hw: pointer to the hardware structure
10222  * @seid: VEB seid to add mirror rule to
10223  * @dst_id: destination vsi seid
10224  * @entries: Buffer which contains the entities to be mirrored
10225  * @count: number of entities contained in the buffer
10226  * @rule_id:the rule_id of the rule to be added
10227  *
10228  * Add a mirror rule for a given veb.
10229  *
10230  **/
10231 static enum i40e_status_code
10232 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10233                         uint16_t seid, uint16_t dst_id,
10234                         uint16_t rule_type, uint16_t *entries,
10235                         uint16_t count, uint16_t *rule_id)
10236 {
10237         struct i40e_aq_desc desc;
10238         struct i40e_aqc_add_delete_mirror_rule cmd;
10239         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10240                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10241                 &desc.params.raw;
10242         uint16_t buff_len;
10243         enum i40e_status_code status;
10244
10245         i40e_fill_default_direct_cmd_desc(&desc,
10246                                           i40e_aqc_opc_add_mirror_rule);
10247         memset(&cmd, 0, sizeof(cmd));
10248
10249         buff_len = sizeof(uint16_t) * count;
10250         desc.datalen = rte_cpu_to_le_16(buff_len);
10251         if (buff_len > 0)
10252                 desc.flags |= rte_cpu_to_le_16(
10253                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10254         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10255                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10256         cmd.num_entries = rte_cpu_to_le_16(count);
10257         cmd.seid = rte_cpu_to_le_16(seid);
10258         cmd.destination = rte_cpu_to_le_16(dst_id);
10259
10260         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10261         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10262         PMD_DRV_LOG(INFO,
10263                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10264                 hw->aq.asq_last_status, resp->rule_id,
10265                 resp->mirror_rules_used, resp->mirror_rules_free);
10266         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10267
10268         return status;
10269 }
10270
10271 /**
10272  * i40e_aq_del_mirror_rule
10273  * @hw: pointer to the hardware structure
10274  * @seid: VEB seid to add mirror rule to
10275  * @entries: Buffer which contains the entities to be mirrored
10276  * @count: number of entities contained in the buffer
10277  * @rule_id:the rule_id of the rule to be delete
10278  *
10279  * Delete a mirror rule for a given veb.
10280  *
10281  **/
10282 static enum i40e_status_code
10283 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10284                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10285                 uint16_t count, uint16_t rule_id)
10286 {
10287         struct i40e_aq_desc desc;
10288         struct i40e_aqc_add_delete_mirror_rule cmd;
10289         uint16_t buff_len = 0;
10290         enum i40e_status_code status;
10291         void *buff = NULL;
10292
10293         i40e_fill_default_direct_cmd_desc(&desc,
10294                                           i40e_aqc_opc_delete_mirror_rule);
10295         memset(&cmd, 0, sizeof(cmd));
10296         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10297                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10298                                                           I40E_AQ_FLAG_RD));
10299                 cmd.num_entries = count;
10300                 buff_len = sizeof(uint16_t) * count;
10301                 desc.datalen = rte_cpu_to_le_16(buff_len);
10302                 buff = (void *)entries;
10303         } else
10304                 /* rule id is filled in destination field for deleting mirror rule */
10305                 cmd.destination = rte_cpu_to_le_16(rule_id);
10306
10307         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10308                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10309         cmd.seid = rte_cpu_to_le_16(seid);
10310
10311         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10312         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10313
10314         return status;
10315 }
10316
10317 /**
10318  * i40e_mirror_rule_set
10319  * @dev: pointer to the hardware structure
10320  * @mirror_conf: mirror rule info
10321  * @sw_id: mirror rule's sw_id
10322  * @on: enable/disable
10323  *
10324  * set a mirror rule.
10325  *
10326  **/
10327 static int
10328 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10329                         struct rte_eth_mirror_conf *mirror_conf,
10330                         uint8_t sw_id, uint8_t on)
10331 {
10332         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10333         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10334         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10335         struct i40e_mirror_rule *parent = NULL;
10336         uint16_t seid, dst_seid, rule_id;
10337         uint16_t i, j = 0;
10338         int ret;
10339
10340         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10341
10342         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10343                 PMD_DRV_LOG(ERR,
10344                         "mirror rule can not be configured without veb or vfs.");
10345                 return -ENOSYS;
10346         }
10347         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10348                 PMD_DRV_LOG(ERR, "mirror table is full.");
10349                 return -ENOSPC;
10350         }
10351         if (mirror_conf->dst_pool > pf->vf_num) {
10352                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10353                                  mirror_conf->dst_pool);
10354                 return -EINVAL;
10355         }
10356
10357         seid = pf->main_vsi->veb->seid;
10358
10359         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10360                 if (sw_id <= it->index) {
10361                         mirr_rule = it;
10362                         break;
10363                 }
10364                 parent = it;
10365         }
10366         if (mirr_rule && sw_id == mirr_rule->index) {
10367                 if (on) {
10368                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10369                         return -EEXIST;
10370                 } else {
10371                         ret = i40e_aq_del_mirror_rule(hw, seid,
10372                                         mirr_rule->rule_type,
10373                                         mirr_rule->entries,
10374                                         mirr_rule->num_entries, mirr_rule->id);
10375                         if (ret < 0) {
10376                                 PMD_DRV_LOG(ERR,
10377                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10378                                         ret, hw->aq.asq_last_status);
10379                                 return -ENOSYS;
10380                         }
10381                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10382                         rte_free(mirr_rule);
10383                         pf->nb_mirror_rule--;
10384                         return 0;
10385                 }
10386         } else if (!on) {
10387                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10388                 return -ENOENT;
10389         }
10390
10391         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10392                                 sizeof(struct i40e_mirror_rule) , 0);
10393         if (!mirr_rule) {
10394                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10395                 return I40E_ERR_NO_MEMORY;
10396         }
10397         switch (mirror_conf->rule_type) {
10398         case ETH_MIRROR_VLAN:
10399                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10400                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10401                                 mirr_rule->entries[j] =
10402                                         mirror_conf->vlan.vlan_id[i];
10403                                 j++;
10404                         }
10405                 }
10406                 if (j == 0) {
10407                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10408                         rte_free(mirr_rule);
10409                         return -EINVAL;
10410                 }
10411                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10412                 break;
10413         case ETH_MIRROR_VIRTUAL_POOL_UP:
10414         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10415                 /* check if the specified pool bit is out of range */
10416                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10417                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10418                         rte_free(mirr_rule);
10419                         return -EINVAL;
10420                 }
10421                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10422                         if (mirror_conf->pool_mask & (1ULL << i)) {
10423                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10424                                 j++;
10425                         }
10426                 }
10427                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10428                         /* add pf vsi to entries */
10429                         mirr_rule->entries[j] = pf->main_vsi_seid;
10430                         j++;
10431                 }
10432                 if (j == 0) {
10433                         PMD_DRV_LOG(ERR, "pool is not specified.");
10434                         rte_free(mirr_rule);
10435                         return -EINVAL;
10436                 }
10437                 /* egress and ingress in aq commands means from switch but not port */
10438                 mirr_rule->rule_type =
10439                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10440                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10441                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10442                 break;
10443         case ETH_MIRROR_UPLINK_PORT:
10444                 /* egress and ingress in aq commands means from switch but not port*/
10445                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10446                 break;
10447         case ETH_MIRROR_DOWNLINK_PORT:
10448                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10449                 break;
10450         default:
10451                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10452                         mirror_conf->rule_type);
10453                 rte_free(mirr_rule);
10454                 return -EINVAL;
10455         }
10456
10457         /* If the dst_pool is equal to vf_num, consider it as PF */
10458         if (mirror_conf->dst_pool == pf->vf_num)
10459                 dst_seid = pf->main_vsi_seid;
10460         else
10461                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10462
10463         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10464                                       mirr_rule->rule_type, mirr_rule->entries,
10465                                       j, &rule_id);
10466         if (ret < 0) {
10467                 PMD_DRV_LOG(ERR,
10468                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10469                         ret, hw->aq.asq_last_status);
10470                 rte_free(mirr_rule);
10471                 return -ENOSYS;
10472         }
10473
10474         mirr_rule->index = sw_id;
10475         mirr_rule->num_entries = j;
10476         mirr_rule->id = rule_id;
10477         mirr_rule->dst_vsi_seid = dst_seid;
10478
10479         if (parent)
10480                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10481         else
10482                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10483
10484         pf->nb_mirror_rule++;
10485         return 0;
10486 }
10487
10488 /**
10489  * i40e_mirror_rule_reset
10490  * @dev: pointer to the device
10491  * @sw_id: mirror rule's sw_id
10492  *
10493  * reset a mirror rule.
10494  *
10495  **/
10496 static int
10497 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10498 {
10499         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10500         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10501         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10502         uint16_t seid;
10503         int ret;
10504
10505         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10506
10507         seid = pf->main_vsi->veb->seid;
10508
10509         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10510                 if (sw_id == it->index) {
10511                         mirr_rule = it;
10512                         break;
10513                 }
10514         }
10515         if (mirr_rule) {
10516                 ret = i40e_aq_del_mirror_rule(hw, seid,
10517                                 mirr_rule->rule_type,
10518                                 mirr_rule->entries,
10519                                 mirr_rule->num_entries, mirr_rule->id);
10520                 if (ret < 0) {
10521                         PMD_DRV_LOG(ERR,
10522                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10523                                 ret, hw->aq.asq_last_status);
10524                         return -ENOSYS;
10525                 }
10526                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10527                 rte_free(mirr_rule);
10528                 pf->nb_mirror_rule--;
10529         } else {
10530                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10531                 return -ENOENT;
10532         }
10533         return 0;
10534 }
10535
10536 static uint64_t
10537 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10538 {
10539         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10540         uint64_t systim_cycles;
10541
10542         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10543         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10544                         << 32;
10545
10546         return systim_cycles;
10547 }
10548
10549 static uint64_t
10550 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10551 {
10552         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10553         uint64_t rx_tstamp;
10554
10555         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10556         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10557                         << 32;
10558
10559         return rx_tstamp;
10560 }
10561
10562 static uint64_t
10563 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10564 {
10565         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10566         uint64_t tx_tstamp;
10567
10568         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10569         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10570                         << 32;
10571
10572         return tx_tstamp;
10573 }
10574
10575 static void
10576 i40e_start_timecounters(struct rte_eth_dev *dev)
10577 {
10578         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10579         struct i40e_adapter *adapter =
10580                         (struct i40e_adapter *)dev->data->dev_private;
10581         struct rte_eth_link link;
10582         uint32_t tsync_inc_l;
10583         uint32_t tsync_inc_h;
10584
10585         /* Get current link speed. */
10586         i40e_dev_link_update(dev, 1);
10587         rte_eth_linkstatus_get(dev, &link);
10588
10589         switch (link.link_speed) {
10590         case ETH_SPEED_NUM_40G:
10591                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10592                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10593                 break;
10594         case ETH_SPEED_NUM_10G:
10595                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10596                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10597                 break;
10598         case ETH_SPEED_NUM_1G:
10599                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10600                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10601                 break;
10602         default:
10603                 tsync_inc_l = 0x0;
10604                 tsync_inc_h = 0x0;
10605         }
10606
10607         /* Set the timesync increment value. */
10608         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10609         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10610
10611         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10612         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10613         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10614
10615         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10616         adapter->systime_tc.cc_shift = 0;
10617         adapter->systime_tc.nsec_mask = 0;
10618
10619         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10620         adapter->rx_tstamp_tc.cc_shift = 0;
10621         adapter->rx_tstamp_tc.nsec_mask = 0;
10622
10623         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10624         adapter->tx_tstamp_tc.cc_shift = 0;
10625         adapter->tx_tstamp_tc.nsec_mask = 0;
10626 }
10627
10628 static int
10629 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10630 {
10631         struct i40e_adapter *adapter =
10632                         (struct i40e_adapter *)dev->data->dev_private;
10633
10634         adapter->systime_tc.nsec += delta;
10635         adapter->rx_tstamp_tc.nsec += delta;
10636         adapter->tx_tstamp_tc.nsec += delta;
10637
10638         return 0;
10639 }
10640
10641 static int
10642 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10643 {
10644         uint64_t ns;
10645         struct i40e_adapter *adapter =
10646                         (struct i40e_adapter *)dev->data->dev_private;
10647
10648         ns = rte_timespec_to_ns(ts);
10649
10650         /* Set the timecounters to a new value. */
10651         adapter->systime_tc.nsec = ns;
10652         adapter->rx_tstamp_tc.nsec = ns;
10653         adapter->tx_tstamp_tc.nsec = ns;
10654
10655         return 0;
10656 }
10657
10658 static int
10659 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10660 {
10661         uint64_t ns, systime_cycles;
10662         struct i40e_adapter *adapter =
10663                         (struct i40e_adapter *)dev->data->dev_private;
10664
10665         systime_cycles = i40e_read_systime_cyclecounter(dev);
10666         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10667         *ts = rte_ns_to_timespec(ns);
10668
10669         return 0;
10670 }
10671
10672 static int
10673 i40e_timesync_enable(struct rte_eth_dev *dev)
10674 {
10675         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10676         uint32_t tsync_ctl_l;
10677         uint32_t tsync_ctl_h;
10678
10679         /* Stop the timesync system time. */
10680         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10681         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10682         /* Reset the timesync system time value. */
10683         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10684         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10685
10686         i40e_start_timecounters(dev);
10687
10688         /* Clear timesync registers. */
10689         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10690         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10691         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10692         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10693         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10694         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10695
10696         /* Enable timestamping of PTP packets. */
10697         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10698         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10699
10700         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10701         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10702         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10703
10704         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10705         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10706
10707         return 0;
10708 }
10709
10710 static int
10711 i40e_timesync_disable(struct rte_eth_dev *dev)
10712 {
10713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10714         uint32_t tsync_ctl_l;
10715         uint32_t tsync_ctl_h;
10716
10717         /* Disable timestamping of transmitted PTP packets. */
10718         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10719         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10720
10721         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10722         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10723
10724         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10725         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10726
10727         /* Reset the timesync increment value. */
10728         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10729         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10730
10731         return 0;
10732 }
10733
10734 static int
10735 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10736                                 struct timespec *timestamp, uint32_t flags)
10737 {
10738         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10739         struct i40e_adapter *adapter =
10740                 (struct i40e_adapter *)dev->data->dev_private;
10741
10742         uint32_t sync_status;
10743         uint32_t index = flags & 0x03;
10744         uint64_t rx_tstamp_cycles;
10745         uint64_t ns;
10746
10747         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10748         if ((sync_status & (1 << index)) == 0)
10749                 return -EINVAL;
10750
10751         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10752         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10753         *timestamp = rte_ns_to_timespec(ns);
10754
10755         return 0;
10756 }
10757
10758 static int
10759 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10760                                 struct timespec *timestamp)
10761 {
10762         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10763         struct i40e_adapter *adapter =
10764                 (struct i40e_adapter *)dev->data->dev_private;
10765
10766         uint32_t sync_status;
10767         uint64_t tx_tstamp_cycles;
10768         uint64_t ns;
10769
10770         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10771         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10772                 return -EINVAL;
10773
10774         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10775         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10776         *timestamp = rte_ns_to_timespec(ns);
10777
10778         return 0;
10779 }
10780
10781 /*
10782  * i40e_parse_dcb_configure - parse dcb configure from user
10783  * @dev: the device being configured
10784  * @dcb_cfg: pointer of the result of parse
10785  * @*tc_map: bit map of enabled traffic classes
10786  *
10787  * Returns 0 on success, negative value on failure
10788  */
10789 static int
10790 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10791                          struct i40e_dcbx_config *dcb_cfg,
10792                          uint8_t *tc_map)
10793 {
10794         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10795         uint8_t i, tc_bw, bw_lf;
10796
10797         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10798
10799         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10800         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10801                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10802                 return -EINVAL;
10803         }
10804
10805         /* assume each tc has the same bw */
10806         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10807         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10808                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10809         /* to ensure the sum of tcbw is equal to 100 */
10810         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10811         for (i = 0; i < bw_lf; i++)
10812                 dcb_cfg->etscfg.tcbwtable[i]++;
10813
10814         /* assume each tc has the same Transmission Selection Algorithm */
10815         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10816                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10817
10818         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10819                 dcb_cfg->etscfg.prioritytable[i] =
10820                                 dcb_rx_conf->dcb_tc[i];
10821
10822         /* FW needs one App to configure HW */
10823         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10824         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10825         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10826         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10827
10828         if (dcb_rx_conf->nb_tcs == 0)
10829                 *tc_map = 1; /* tc0 only */
10830         else
10831                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10832
10833         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10834                 dcb_cfg->pfc.willing = 0;
10835                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10836                 dcb_cfg->pfc.pfcenable = *tc_map;
10837         }
10838         return 0;
10839 }
10840
10841
10842 static enum i40e_status_code
10843 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10844                               struct i40e_aqc_vsi_properties_data *info,
10845                               uint8_t enabled_tcmap)
10846 {
10847         enum i40e_status_code ret;
10848         int i, total_tc = 0;
10849         uint16_t qpnum_per_tc, bsf, qp_idx;
10850         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10851         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10852         uint16_t used_queues;
10853
10854         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10855         if (ret != I40E_SUCCESS)
10856                 return ret;
10857
10858         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10859                 if (enabled_tcmap & (1 << i))
10860                         total_tc++;
10861         }
10862         if (total_tc == 0)
10863                 total_tc = 1;
10864         vsi->enabled_tc = enabled_tcmap;
10865
10866         /* different VSI has different queues assigned */
10867         if (vsi->type == I40E_VSI_MAIN)
10868                 used_queues = dev_data->nb_rx_queues -
10869                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10870         else if (vsi->type == I40E_VSI_VMDQ2)
10871                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10872         else {
10873                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10874                 return I40E_ERR_NO_AVAILABLE_VSI;
10875         }
10876
10877         qpnum_per_tc = used_queues / total_tc;
10878         /* Number of queues per enabled TC */
10879         if (qpnum_per_tc == 0) {
10880                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10881                 return I40E_ERR_INVALID_QP_ID;
10882         }
10883         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10884                                 I40E_MAX_Q_PER_TC);
10885         bsf = rte_bsf32(qpnum_per_tc);
10886
10887         /**
10888          * Configure TC and queue mapping parameters, for enabled TC,
10889          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10890          * default queue will serve it.
10891          */
10892         qp_idx = 0;
10893         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10894                 if (vsi->enabled_tc & (1 << i)) {
10895                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10896                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10897                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10898                         qp_idx += qpnum_per_tc;
10899                 } else
10900                         info->tc_mapping[i] = 0;
10901         }
10902
10903         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10904         if (vsi->type == I40E_VSI_SRIOV) {
10905                 info->mapping_flags |=
10906                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10907                 for (i = 0; i < vsi->nb_qps; i++)
10908                         info->queue_mapping[i] =
10909                                 rte_cpu_to_le_16(vsi->base_queue + i);
10910         } else {
10911                 info->mapping_flags |=
10912                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10913                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10914         }
10915         info->valid_sections |=
10916                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10917
10918         return I40E_SUCCESS;
10919 }
10920
10921 /*
10922  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10923  * @veb: VEB to be configured
10924  * @tc_map: enabled TC bitmap
10925  *
10926  * Returns 0 on success, negative value on failure
10927  */
10928 static enum i40e_status_code
10929 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10930 {
10931         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10932         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10933         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10934         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10935         enum i40e_status_code ret = I40E_SUCCESS;
10936         int i;
10937         uint32_t bw_max;
10938
10939         /* Check if enabled_tc is same as existing or new TCs */
10940         if (veb->enabled_tc == tc_map)
10941                 return ret;
10942
10943         /* configure tc bandwidth */
10944         memset(&veb_bw, 0, sizeof(veb_bw));
10945         veb_bw.tc_valid_bits = tc_map;
10946         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10947         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10948                 if (tc_map & BIT_ULL(i))
10949                         veb_bw.tc_bw_share_credits[i] = 1;
10950         }
10951         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10952                                                    &veb_bw, NULL);
10953         if (ret) {
10954                 PMD_INIT_LOG(ERR,
10955                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10956                         hw->aq.asq_last_status);
10957                 return ret;
10958         }
10959
10960         memset(&ets_query, 0, sizeof(ets_query));
10961         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10962                                                    &ets_query, NULL);
10963         if (ret != I40E_SUCCESS) {
10964                 PMD_DRV_LOG(ERR,
10965                         "Failed to get switch_comp ETS configuration %u",
10966                         hw->aq.asq_last_status);
10967                 return ret;
10968         }
10969         memset(&bw_query, 0, sizeof(bw_query));
10970         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10971                                                   &bw_query, NULL);
10972         if (ret != I40E_SUCCESS) {
10973                 PMD_DRV_LOG(ERR,
10974                         "Failed to get switch_comp bandwidth configuration %u",
10975                         hw->aq.asq_last_status);
10976                 return ret;
10977         }
10978
10979         /* store and print out BW info */
10980         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10981         veb->bw_info.bw_max = ets_query.tc_bw_max;
10982         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10983         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10984         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10985                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10986                      I40E_16_BIT_WIDTH);
10987         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10988                 veb->bw_info.bw_ets_share_credits[i] =
10989                                 bw_query.tc_bw_share_credits[i];
10990                 veb->bw_info.bw_ets_credits[i] =
10991                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10992                 /* 4 bits per TC, 4th bit is reserved */
10993                 veb->bw_info.bw_ets_max[i] =
10994                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10995                                   RTE_LEN2MASK(3, uint8_t));
10996                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10997                             veb->bw_info.bw_ets_share_credits[i]);
10998                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10999                             veb->bw_info.bw_ets_credits[i]);
11000                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11001                             veb->bw_info.bw_ets_max[i]);
11002         }
11003
11004         veb->enabled_tc = tc_map;
11005
11006         return ret;
11007 }
11008
11009
11010 /*
11011  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11012  * @vsi: VSI to be configured
11013  * @tc_map: enabled TC bitmap
11014  *
11015  * Returns 0 on success, negative value on failure
11016  */
11017 static enum i40e_status_code
11018 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11019 {
11020         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11021         struct i40e_vsi_context ctxt;
11022         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11023         enum i40e_status_code ret = I40E_SUCCESS;
11024         int i;
11025
11026         /* Check if enabled_tc is same as existing or new TCs */
11027         if (vsi->enabled_tc == tc_map)
11028                 return ret;
11029
11030         /* configure tc bandwidth */
11031         memset(&bw_data, 0, sizeof(bw_data));
11032         bw_data.tc_valid_bits = tc_map;
11033         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11034         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11035                 if (tc_map & BIT_ULL(i))
11036                         bw_data.tc_bw_credits[i] = 1;
11037         }
11038         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11039         if (ret) {
11040                 PMD_INIT_LOG(ERR,
11041                         "AQ command Config VSI BW allocation per TC failed = %d",
11042                         hw->aq.asq_last_status);
11043                 goto out;
11044         }
11045         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11046                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11047
11048         /* Update Queue Pairs Mapping for currently enabled UPs */
11049         ctxt.seid = vsi->seid;
11050         ctxt.pf_num = hw->pf_id;
11051         ctxt.vf_num = 0;
11052         ctxt.uplink_seid = vsi->uplink_seid;
11053         ctxt.info = vsi->info;
11054         i40e_get_cap(hw);
11055         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11056         if (ret)
11057                 goto out;
11058
11059         /* Update the VSI after updating the VSI queue-mapping information */
11060         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11061         if (ret) {
11062                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11063                         hw->aq.asq_last_status);
11064                 goto out;
11065         }
11066         /* update the local VSI info with updated queue map */
11067         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11068                                         sizeof(vsi->info.tc_mapping));
11069         rte_memcpy(&vsi->info.queue_mapping,
11070                         &ctxt.info.queue_mapping,
11071                 sizeof(vsi->info.queue_mapping));
11072         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11073         vsi->info.valid_sections = 0;
11074
11075         /* query and update current VSI BW information */
11076         ret = i40e_vsi_get_bw_config(vsi);
11077         if (ret) {
11078                 PMD_INIT_LOG(ERR,
11079                          "Failed updating vsi bw info, err %s aq_err %s",
11080                          i40e_stat_str(hw, ret),
11081                          i40e_aq_str(hw, hw->aq.asq_last_status));
11082                 goto out;
11083         }
11084
11085         vsi->enabled_tc = tc_map;
11086
11087 out:
11088         return ret;
11089 }
11090
11091 /*
11092  * i40e_dcb_hw_configure - program the dcb setting to hw
11093  * @pf: pf the configuration is taken on
11094  * @new_cfg: new configuration
11095  * @tc_map: enabled TC bitmap
11096  *
11097  * Returns 0 on success, negative value on failure
11098  */
11099 static enum i40e_status_code
11100 i40e_dcb_hw_configure(struct i40e_pf *pf,
11101                       struct i40e_dcbx_config *new_cfg,
11102                       uint8_t tc_map)
11103 {
11104         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11105         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11106         struct i40e_vsi *main_vsi = pf->main_vsi;
11107         struct i40e_vsi_list *vsi_list;
11108         enum i40e_status_code ret;
11109         int i;
11110         uint32_t val;
11111
11112         /* Use the FW API if FW > v4.4*/
11113         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11114               (hw->aq.fw_maj_ver >= 5))) {
11115                 PMD_INIT_LOG(ERR,
11116                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11117                 return I40E_ERR_FIRMWARE_API_VERSION;
11118         }
11119
11120         /* Check if need reconfiguration */
11121         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11122                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11123                 return I40E_SUCCESS;
11124         }
11125
11126         /* Copy the new config to the current config */
11127         *old_cfg = *new_cfg;
11128         old_cfg->etsrec = old_cfg->etscfg;
11129         ret = i40e_set_dcb_config(hw);
11130         if (ret) {
11131                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11132                          i40e_stat_str(hw, ret),
11133                          i40e_aq_str(hw, hw->aq.asq_last_status));
11134                 return ret;
11135         }
11136         /* set receive Arbiter to RR mode and ETS scheme by default */
11137         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11138                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11139                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11140                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11141                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11142                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11143                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11144                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11145                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11146                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11147                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11148                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11149                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11150         }
11151         /* get local mib to check whether it is configured correctly */
11152         /* IEEE mode */
11153         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11154         /* Get Local DCB Config */
11155         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11156                                      &hw->local_dcbx_config);
11157
11158         /* if Veb is created, need to update TC of it at first */
11159         if (main_vsi->veb) {
11160                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11161                 if (ret)
11162                         PMD_INIT_LOG(WARNING,
11163                                  "Failed configuring TC for VEB seid=%d",
11164                                  main_vsi->veb->seid);
11165         }
11166         /* Update each VSI */
11167         i40e_vsi_config_tc(main_vsi, tc_map);
11168         if (main_vsi->veb) {
11169                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11170                         /* Beside main VSI and VMDQ VSIs, only enable default
11171                          * TC for other VSIs
11172                          */
11173                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11174                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11175                                                          tc_map);
11176                         else
11177                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11178                                                          I40E_DEFAULT_TCMAP);
11179                         if (ret)
11180                                 PMD_INIT_LOG(WARNING,
11181                                         "Failed configuring TC for VSI seid=%d",
11182                                         vsi_list->vsi->seid);
11183                         /* continue */
11184                 }
11185         }
11186         return I40E_SUCCESS;
11187 }
11188
11189 /*
11190  * i40e_dcb_init_configure - initial dcb config
11191  * @dev: device being configured
11192  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11193  *
11194  * Returns 0 on success, negative value on failure
11195  */
11196 int
11197 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11198 {
11199         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11200         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11201         int i, ret = 0;
11202
11203         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11204                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11205                 return -ENOTSUP;
11206         }
11207
11208         /* DCB initialization:
11209          * Update DCB configuration from the Firmware and configure
11210          * LLDP MIB change event.
11211          */
11212         if (sw_dcb == TRUE) {
11213                 ret = i40e_init_dcb(hw);
11214                 /* If lldp agent is stopped, the return value from
11215                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11216                  * adminq status. Otherwise, it should return success.
11217                  */
11218                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11219                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11220                         memset(&hw->local_dcbx_config, 0,
11221                                 sizeof(struct i40e_dcbx_config));
11222                         /* set dcb default configuration */
11223                         hw->local_dcbx_config.etscfg.willing = 0;
11224                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11225                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11226                         hw->local_dcbx_config.etscfg.tsatable[0] =
11227                                                 I40E_IEEE_TSA_ETS;
11228                         /* all UPs mapping to TC0 */
11229                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11230                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11231                         hw->local_dcbx_config.etsrec =
11232                                 hw->local_dcbx_config.etscfg;
11233                         hw->local_dcbx_config.pfc.willing = 0;
11234                         hw->local_dcbx_config.pfc.pfccap =
11235                                                 I40E_MAX_TRAFFIC_CLASS;
11236                         /* FW needs one App to configure HW */
11237                         hw->local_dcbx_config.numapps = 1;
11238                         hw->local_dcbx_config.app[0].selector =
11239                                                 I40E_APP_SEL_ETHTYPE;
11240                         hw->local_dcbx_config.app[0].priority = 3;
11241                         hw->local_dcbx_config.app[0].protocolid =
11242                                                 I40E_APP_PROTOID_FCOE;
11243                         ret = i40e_set_dcb_config(hw);
11244                         if (ret) {
11245                                 PMD_INIT_LOG(ERR,
11246                                         "default dcb config fails. err = %d, aq_err = %d.",
11247                                         ret, hw->aq.asq_last_status);
11248                                 return -ENOSYS;
11249                         }
11250                 } else {
11251                         PMD_INIT_LOG(ERR,
11252                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11253                                 ret, hw->aq.asq_last_status);
11254                         return -ENOTSUP;
11255                 }
11256         } else {
11257                 ret = i40e_aq_start_lldp(hw, NULL);
11258                 if (ret != I40E_SUCCESS)
11259                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11260
11261                 ret = i40e_init_dcb(hw);
11262                 if (!ret) {
11263                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11264                                 PMD_INIT_LOG(ERR,
11265                                         "HW doesn't support DCBX offload.");
11266                                 return -ENOTSUP;
11267                         }
11268                 } else {
11269                         PMD_INIT_LOG(ERR,
11270                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11271                                 ret, hw->aq.asq_last_status);
11272                         return -ENOTSUP;
11273                 }
11274         }
11275         return 0;
11276 }
11277
11278 /*
11279  * i40e_dcb_setup - setup dcb related config
11280  * @dev: device being configured
11281  *
11282  * Returns 0 on success, negative value on failure
11283  */
11284 static int
11285 i40e_dcb_setup(struct rte_eth_dev *dev)
11286 {
11287         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11288         struct i40e_dcbx_config dcb_cfg;
11289         uint8_t tc_map = 0;
11290         int ret = 0;
11291
11292         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11293                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11294                 return -ENOTSUP;
11295         }
11296
11297         if (pf->vf_num != 0)
11298                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11299
11300         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11301         if (ret) {
11302                 PMD_INIT_LOG(ERR, "invalid dcb config");
11303                 return -EINVAL;
11304         }
11305         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11306         if (ret) {
11307                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11308                 return -ENOSYS;
11309         }
11310
11311         return 0;
11312 }
11313
11314 static int
11315 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11316                       struct rte_eth_dcb_info *dcb_info)
11317 {
11318         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11319         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11320         struct i40e_vsi *vsi = pf->main_vsi;
11321         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11322         uint16_t bsf, tc_mapping;
11323         int i, j = 0;
11324
11325         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11326                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11327         else
11328                 dcb_info->nb_tcs = 1;
11329         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11330                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11331         for (i = 0; i < dcb_info->nb_tcs; i++)
11332                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11333
11334         /* get queue mapping if vmdq is disabled */
11335         if (!pf->nb_cfg_vmdq_vsi) {
11336                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11337                         if (!(vsi->enabled_tc & (1 << i)))
11338                                 continue;
11339                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11340                         dcb_info->tc_queue.tc_rxq[j][i].base =
11341                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11342                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11343                         dcb_info->tc_queue.tc_txq[j][i].base =
11344                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11345                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11346                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11347                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11348                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11349                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11350                 }
11351                 return 0;
11352         }
11353
11354         /* get queue mapping if vmdq is enabled */
11355         do {
11356                 vsi = pf->vmdq[j].vsi;
11357                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11358                         if (!(vsi->enabled_tc & (1 << i)))
11359                                 continue;
11360                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11361                         dcb_info->tc_queue.tc_rxq[j][i].base =
11362                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11363                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11364                         dcb_info->tc_queue.tc_txq[j][i].base =
11365                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11366                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11367                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11368                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11369                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11370                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11371                 }
11372                 j++;
11373         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11374         return 0;
11375 }
11376
11377 static int
11378 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11379 {
11380         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11381         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11382         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11383         uint16_t msix_intr;
11384
11385         msix_intr = intr_handle->intr_vec[queue_id];
11386         if (msix_intr == I40E_MISC_VEC_ID)
11387                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11388                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11389                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11390                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11391         else
11392                 I40E_WRITE_REG(hw,
11393                                I40E_PFINT_DYN_CTLN(msix_intr -
11394                                                    I40E_RX_VEC_START),
11395                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11396                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11397                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11398
11399         I40E_WRITE_FLUSH(hw);
11400         rte_intr_enable(&pci_dev->intr_handle);
11401
11402         return 0;
11403 }
11404
11405 static int
11406 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11407 {
11408         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11409         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11410         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11411         uint16_t msix_intr;
11412
11413         msix_intr = intr_handle->intr_vec[queue_id];
11414         if (msix_intr == I40E_MISC_VEC_ID)
11415                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11416                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11417         else
11418                 I40E_WRITE_REG(hw,
11419                                I40E_PFINT_DYN_CTLN(msix_intr -
11420                                                    I40E_RX_VEC_START),
11421                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11422         I40E_WRITE_FLUSH(hw);
11423
11424         return 0;
11425 }
11426
11427 static int i40e_get_regs(struct rte_eth_dev *dev,
11428                          struct rte_dev_reg_info *regs)
11429 {
11430         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11431         uint32_t *ptr_data = regs->data;
11432         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11433         const struct i40e_reg_info *reg_info;
11434
11435         if (ptr_data == NULL) {
11436                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11437                 regs->width = sizeof(uint32_t);
11438                 return 0;
11439         }
11440
11441         /* The first few registers have to be read using AQ operations */
11442         reg_idx = 0;
11443         while (i40e_regs_adminq[reg_idx].name) {
11444                 reg_info = &i40e_regs_adminq[reg_idx++];
11445                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11446                         for (arr_idx2 = 0;
11447                                         arr_idx2 <= reg_info->count2;
11448                                         arr_idx2++) {
11449                                 reg_offset = arr_idx * reg_info->stride1 +
11450                                         arr_idx2 * reg_info->stride2;
11451                                 reg_offset += reg_info->base_addr;
11452                                 ptr_data[reg_offset >> 2] =
11453                                         i40e_read_rx_ctl(hw, reg_offset);
11454                         }
11455         }
11456
11457         /* The remaining registers can be read using primitives */
11458         reg_idx = 0;
11459         while (i40e_regs_others[reg_idx].name) {
11460                 reg_info = &i40e_regs_others[reg_idx++];
11461                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11462                         for (arr_idx2 = 0;
11463                                         arr_idx2 <= reg_info->count2;
11464                                         arr_idx2++) {
11465                                 reg_offset = arr_idx * reg_info->stride1 +
11466                                         arr_idx2 * reg_info->stride2;
11467                                 reg_offset += reg_info->base_addr;
11468                                 ptr_data[reg_offset >> 2] =
11469                                         I40E_READ_REG(hw, reg_offset);
11470                         }
11471         }
11472
11473         return 0;
11474 }
11475
11476 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11477 {
11478         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11479
11480         /* Convert word count to byte count */
11481         return hw->nvm.sr_size << 1;
11482 }
11483
11484 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11485                            struct rte_dev_eeprom_info *eeprom)
11486 {
11487         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11488         uint16_t *data = eeprom->data;
11489         uint16_t offset, length, cnt_words;
11490         int ret_code;
11491
11492         offset = eeprom->offset >> 1;
11493         length = eeprom->length >> 1;
11494         cnt_words = length;
11495
11496         if (offset > hw->nvm.sr_size ||
11497                 offset + length > hw->nvm.sr_size) {
11498                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11499                 return -EINVAL;
11500         }
11501
11502         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11503
11504         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11505         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11506                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11507                 return -EIO;
11508         }
11509
11510         return 0;
11511 }
11512
11513 static int i40e_get_module_info(struct rte_eth_dev *dev,
11514                                 struct rte_eth_dev_module_info *modinfo)
11515 {
11516         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11517         uint32_t sff8472_comp = 0;
11518         uint32_t sff8472_swap = 0;
11519         uint32_t sff8636_rev = 0;
11520         i40e_status status;
11521         uint32_t type = 0;
11522
11523         /* Check if firmware supports reading module EEPROM. */
11524         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11525                 PMD_DRV_LOG(ERR,
11526                             "Module EEPROM memory read not supported. "
11527                             "Please update the NVM image.\n");
11528                 return -EINVAL;
11529         }
11530
11531         status = i40e_update_link_info(hw);
11532         if (status)
11533                 return -EIO;
11534
11535         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11536                 PMD_DRV_LOG(ERR,
11537                             "Cannot read module EEPROM memory. "
11538                             "No module connected.\n");
11539                 return -EINVAL;
11540         }
11541
11542         type = hw->phy.link_info.module_type[0];
11543
11544         switch (type) {
11545         case I40E_MODULE_TYPE_SFP:
11546                 status = i40e_aq_get_phy_register(hw,
11547                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11548                                 I40E_I2C_EEPROM_DEV_ADDR,
11549                                 I40E_MODULE_SFF_8472_COMP,
11550                                 &sff8472_comp, NULL);
11551                 if (status)
11552                         return -EIO;
11553
11554                 status = i40e_aq_get_phy_register(hw,
11555                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11556                                 I40E_I2C_EEPROM_DEV_ADDR,
11557                                 I40E_MODULE_SFF_8472_SWAP,
11558                                 &sff8472_swap, NULL);
11559                 if (status)
11560                         return -EIO;
11561
11562                 /* Check if the module requires address swap to access
11563                  * the other EEPROM memory page.
11564                  */
11565                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11566                         PMD_DRV_LOG(WARNING,
11567                                     "Module address swap to access "
11568                                     "page 0xA2 is not supported.\n");
11569                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11570                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11571                 } else if (sff8472_comp == 0x00) {
11572                         /* Module is not SFF-8472 compliant */
11573                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11574                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11575                 } else {
11576                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11577                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11578                 }
11579                 break;
11580         case I40E_MODULE_TYPE_QSFP_PLUS:
11581                 /* Read from memory page 0. */
11582                 status = i40e_aq_get_phy_register(hw,
11583                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11584                                 0,
11585                                 I40E_MODULE_REVISION_ADDR,
11586                                 &sff8636_rev, NULL);
11587                 if (status)
11588                         return -EIO;
11589                 /* Determine revision compliance byte */
11590                 if (sff8636_rev > 0x02) {
11591                         /* Module is SFF-8636 compliant */
11592                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11593                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11594                 } else {
11595                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11596                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11597                 }
11598                 break;
11599         case I40E_MODULE_TYPE_QSFP28:
11600                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11601                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11602                 break;
11603         default:
11604                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11605                 return -EINVAL;
11606         }
11607         return 0;
11608 }
11609
11610 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11611                                   struct rte_dev_eeprom_info *info)
11612 {
11613         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11614         bool is_sfp = false;
11615         i40e_status status;
11616         uint8_t *data = info->data;
11617         uint32_t value = 0;
11618         uint32_t i;
11619
11620         if (!info || !info->length || !data)
11621                 return -EINVAL;
11622
11623         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11624                 is_sfp = true;
11625
11626         for (i = 0; i < info->length; i++) {
11627                 u32 offset = i + info->offset;
11628                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11629
11630                 /* Check if we need to access the other memory page */
11631                 if (is_sfp) {
11632                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11633                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11634                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11635                         }
11636                 } else {
11637                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11638                                 /* Compute memory page number and offset. */
11639                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11640                                 addr++;
11641                         }
11642                 }
11643                 status = i40e_aq_get_phy_register(hw,
11644                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11645                                 addr, offset, &value, NULL);
11646                 if (status)
11647                         return -EIO;
11648                 data[i] = (uint8_t)value;
11649         }
11650         return 0;
11651 }
11652
11653 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11654                                      struct ether_addr *mac_addr)
11655 {
11656         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11657         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11658         struct i40e_vsi *vsi = pf->main_vsi;
11659         struct i40e_mac_filter_info mac_filter;
11660         struct i40e_mac_filter *f;
11661         int ret;
11662
11663         if (!is_valid_assigned_ether_addr(mac_addr)) {
11664                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11665                 return -EINVAL;
11666         }
11667
11668         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11669                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11670                         break;
11671         }
11672
11673         if (f == NULL) {
11674                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11675                 return -EIO;
11676         }
11677
11678         mac_filter = f->mac_info;
11679         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11680         if (ret != I40E_SUCCESS) {
11681                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11682                 return -EIO;
11683         }
11684         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11685         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11686         if (ret != I40E_SUCCESS) {
11687                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11688                 return -EIO;
11689         }
11690         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11691
11692         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11693                                         mac_addr->addr_bytes, NULL);
11694         if (ret != I40E_SUCCESS) {
11695                 PMD_DRV_LOG(ERR, "Failed to change mac");
11696                 return -EIO;
11697         }
11698
11699         return 0;
11700 }
11701
11702 static int
11703 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11704 {
11705         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11706         struct rte_eth_dev_data *dev_data = pf->dev_data;
11707         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11708         int ret = 0;
11709
11710         /* check if mtu is within the allowed range */
11711         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11712                 return -EINVAL;
11713
11714         /* mtu setting is forbidden if port is start */
11715         if (dev_data->dev_started) {
11716                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11717                             dev_data->port_id);
11718                 return -EBUSY;
11719         }
11720
11721         if (frame_size > ETHER_MAX_LEN)
11722                 dev_data->dev_conf.rxmode.offloads |=
11723                         DEV_RX_OFFLOAD_JUMBO_FRAME;
11724         else
11725                 dev_data->dev_conf.rxmode.offloads &=
11726                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11727
11728         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11729
11730         return ret;
11731 }
11732
11733 /* Restore ethertype filter */
11734 static void
11735 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11736 {
11737         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11738         struct i40e_ethertype_filter_list
11739                 *ethertype_list = &pf->ethertype.ethertype_list;
11740         struct i40e_ethertype_filter *f;
11741         struct i40e_control_filter_stats stats;
11742         uint16_t flags;
11743
11744         TAILQ_FOREACH(f, ethertype_list, rules) {
11745                 flags = 0;
11746                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11747                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11748                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11749                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11750                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11751
11752                 memset(&stats, 0, sizeof(stats));
11753                 i40e_aq_add_rem_control_packet_filter(hw,
11754                                             f->input.mac_addr.addr_bytes,
11755                                             f->input.ether_type,
11756                                             flags, pf->main_vsi->seid,
11757                                             f->queue, 1, &stats, NULL);
11758         }
11759         PMD_DRV_LOG(INFO, "Ethertype filter:"
11760                     " mac_etype_used = %u, etype_used = %u,"
11761                     " mac_etype_free = %u, etype_free = %u",
11762                     stats.mac_etype_used, stats.etype_used,
11763                     stats.mac_etype_free, stats.etype_free);
11764 }
11765
11766 /* Restore tunnel filter */
11767 static void
11768 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11769 {
11770         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11771         struct i40e_vsi *vsi;
11772         struct i40e_pf_vf *vf;
11773         struct i40e_tunnel_filter_list
11774                 *tunnel_list = &pf->tunnel.tunnel_list;
11775         struct i40e_tunnel_filter *f;
11776         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11777         bool big_buffer = 0;
11778
11779         TAILQ_FOREACH(f, tunnel_list, rules) {
11780                 if (!f->is_to_vf)
11781                         vsi = pf->main_vsi;
11782                 else {
11783                         vf = &pf->vfs[f->vf_id];
11784                         vsi = vf->vsi;
11785                 }
11786                 memset(&cld_filter, 0, sizeof(cld_filter));
11787                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11788                         (struct ether_addr *)&cld_filter.element.outer_mac);
11789                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11790                         (struct ether_addr *)&cld_filter.element.inner_mac);
11791                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11792                 cld_filter.element.flags = f->input.flags;
11793                 cld_filter.element.tenant_id = f->input.tenant_id;
11794                 cld_filter.element.queue_number = f->queue;
11795                 rte_memcpy(cld_filter.general_fields,
11796                            f->input.general_fields,
11797                            sizeof(f->input.general_fields));
11798
11799                 if (((f->input.flags &
11800                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11801                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11802                     ((f->input.flags &
11803                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11804                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11805                     ((f->input.flags &
11806                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11807                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11808                         big_buffer = 1;
11809
11810                 if (big_buffer)
11811                         i40e_aq_add_cloud_filters_big_buffer(hw,
11812                                              vsi->seid, &cld_filter, 1);
11813                 else
11814                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11815                                                   &cld_filter.element, 1);
11816         }
11817 }
11818
11819 /* Restore rss filter */
11820 static inline void
11821 i40e_rss_filter_restore(struct i40e_pf *pf)
11822 {
11823         struct i40e_rte_flow_rss_conf *conf =
11824                                         &pf->rss_info;
11825         if (conf->conf.queue_num)
11826                 i40e_config_rss_filter(pf, conf, TRUE);
11827 }
11828
11829 static void
11830 i40e_filter_restore(struct i40e_pf *pf)
11831 {
11832         i40e_ethertype_filter_restore(pf);
11833         i40e_tunnel_filter_restore(pf);
11834         i40e_fdir_filter_restore(pf);
11835         i40e_rss_filter_restore(pf);
11836 }
11837
11838 static bool
11839 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11840 {
11841         if (strcmp(dev->device->driver->name, drv->driver.name))
11842                 return false;
11843
11844         return true;
11845 }
11846
11847 bool
11848 is_i40e_supported(struct rte_eth_dev *dev)
11849 {
11850         return is_device_supported(dev, &rte_i40e_pmd);
11851 }
11852
11853 struct i40e_customized_pctype*
11854 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11855 {
11856         int i;
11857
11858         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11859                 if (pf->customized_pctype[i].index == index)
11860                         return &pf->customized_pctype[i];
11861         }
11862         return NULL;
11863 }
11864
11865 static int
11866 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11867                               uint32_t pkg_size, uint32_t proto_num,
11868                               struct rte_pmd_i40e_proto_info *proto,
11869                               enum rte_pmd_i40e_package_op op)
11870 {
11871         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11872         uint32_t pctype_num;
11873         struct rte_pmd_i40e_ptype_info *pctype;
11874         uint32_t buff_size;
11875         struct i40e_customized_pctype *new_pctype = NULL;
11876         uint8_t proto_id;
11877         uint8_t pctype_value;
11878         char name[64];
11879         uint32_t i, j, n;
11880         int ret;
11881
11882         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11883             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11884                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11885                 return -1;
11886         }
11887
11888         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11889                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11890                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11891         if (ret) {
11892                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11893                 return -1;
11894         }
11895         if (!pctype_num) {
11896                 PMD_DRV_LOG(INFO, "No new pctype added");
11897                 return -1;
11898         }
11899
11900         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11901         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11902         if (!pctype) {
11903                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11904                 return -1;
11905         }
11906         /* get information about new pctype list */
11907         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11908                                         (uint8_t *)pctype, buff_size,
11909                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11910         if (ret) {
11911                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11912                 rte_free(pctype);
11913                 return -1;
11914         }
11915
11916         /* Update customized pctype. */
11917         for (i = 0; i < pctype_num; i++) {
11918                 pctype_value = pctype[i].ptype_id;
11919                 memset(name, 0, sizeof(name));
11920                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11921                         proto_id = pctype[i].protocols[j];
11922                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11923                                 continue;
11924                         for (n = 0; n < proto_num; n++) {
11925                                 if (proto[n].proto_id != proto_id)
11926                                         continue;
11927                                 strcat(name, proto[n].name);
11928                                 strcat(name, "_");
11929                                 break;
11930                         }
11931                 }
11932                 name[strlen(name) - 1] = '\0';
11933                 if (!strcmp(name, "GTPC"))
11934                         new_pctype =
11935                                 i40e_find_customized_pctype(pf,
11936                                                       I40E_CUSTOMIZED_GTPC);
11937                 else if (!strcmp(name, "GTPU_IPV4"))
11938                         new_pctype =
11939                                 i40e_find_customized_pctype(pf,
11940                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11941                 else if (!strcmp(name, "GTPU_IPV6"))
11942                         new_pctype =
11943                                 i40e_find_customized_pctype(pf,
11944                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11945                 else if (!strcmp(name, "GTPU"))
11946                         new_pctype =
11947                                 i40e_find_customized_pctype(pf,
11948                                                       I40E_CUSTOMIZED_GTPU);
11949                 if (new_pctype) {
11950                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11951                                 new_pctype->pctype = pctype_value;
11952                                 new_pctype->valid = true;
11953                         } else {
11954                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11955                                 new_pctype->valid = false;
11956                         }
11957                 }
11958         }
11959
11960         rte_free(pctype);
11961         return 0;
11962 }
11963
11964 static int
11965 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11966                              uint32_t pkg_size, uint32_t proto_num,
11967                              struct rte_pmd_i40e_proto_info *proto,
11968                              enum rte_pmd_i40e_package_op op)
11969 {
11970         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11971         uint16_t port_id = dev->data->port_id;
11972         uint32_t ptype_num;
11973         struct rte_pmd_i40e_ptype_info *ptype;
11974         uint32_t buff_size;
11975         uint8_t proto_id;
11976         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11977         uint32_t i, j, n;
11978         bool in_tunnel;
11979         int ret;
11980
11981         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11982             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11983                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11984                 return -1;
11985         }
11986
11987         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11988                 rte_pmd_i40e_ptype_mapping_reset(port_id);
11989                 return 0;
11990         }
11991
11992         /* get information about new ptype num */
11993         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11994                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11995                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11996         if (ret) {
11997                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11998                 return ret;
11999         }
12000         if (!ptype_num) {
12001                 PMD_DRV_LOG(INFO, "No new ptype added");
12002                 return -1;
12003         }
12004
12005         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12006         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12007         if (!ptype) {
12008                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12009                 return -1;
12010         }
12011
12012         /* get information about new ptype list */
12013         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12014                                         (uint8_t *)ptype, buff_size,
12015                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12016         if (ret) {
12017                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12018                 rte_free(ptype);
12019                 return ret;
12020         }
12021
12022         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12023         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12024         if (!ptype_mapping) {
12025                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12026                 rte_free(ptype);
12027                 return -1;
12028         }
12029
12030         /* Update ptype mapping table. */
12031         for (i = 0; i < ptype_num; i++) {
12032                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12033                 ptype_mapping[i].sw_ptype = 0;
12034                 in_tunnel = false;
12035                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12036                         proto_id = ptype[i].protocols[j];
12037                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12038                                 continue;
12039                         for (n = 0; n < proto_num; n++) {
12040                                 if (proto[n].proto_id != proto_id)
12041                                         continue;
12042                                 memset(name, 0, sizeof(name));
12043                                 strcpy(name, proto[n].name);
12044                                 if (!strncasecmp(name, "PPPOE", 5))
12045                                         ptype_mapping[i].sw_ptype |=
12046                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12047                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12048                                          !in_tunnel) {
12049                                         ptype_mapping[i].sw_ptype |=
12050                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12051                                         ptype_mapping[i].sw_ptype |=
12052                                                 RTE_PTYPE_L4_FRAG;
12053                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12054                                            in_tunnel) {
12055                                         ptype_mapping[i].sw_ptype |=
12056                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12057                                         ptype_mapping[i].sw_ptype |=
12058                                                 RTE_PTYPE_INNER_L4_FRAG;
12059                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12060                                         ptype_mapping[i].sw_ptype |=
12061                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12062                                         in_tunnel = true;
12063                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12064                                            !in_tunnel)
12065                                         ptype_mapping[i].sw_ptype |=
12066                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12067                                 else if (!strncasecmp(name, "IPV4", 4) &&
12068                                          in_tunnel)
12069                                         ptype_mapping[i].sw_ptype |=
12070                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12071                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12072                                          !in_tunnel) {
12073                                         ptype_mapping[i].sw_ptype |=
12074                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12075                                         ptype_mapping[i].sw_ptype |=
12076                                                 RTE_PTYPE_L4_FRAG;
12077                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12078                                            in_tunnel) {
12079                                         ptype_mapping[i].sw_ptype |=
12080                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12081                                         ptype_mapping[i].sw_ptype |=
12082                                                 RTE_PTYPE_INNER_L4_FRAG;
12083                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12084                                         ptype_mapping[i].sw_ptype |=
12085                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12086                                         in_tunnel = true;
12087                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12088                                            !in_tunnel)
12089                                         ptype_mapping[i].sw_ptype |=
12090                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12091                                 else if (!strncasecmp(name, "IPV6", 4) &&
12092                                          in_tunnel)
12093                                         ptype_mapping[i].sw_ptype |=
12094                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12095                                 else if (!strncasecmp(name, "UDP", 3) &&
12096                                          !in_tunnel)
12097                                         ptype_mapping[i].sw_ptype |=
12098                                                 RTE_PTYPE_L4_UDP;
12099                                 else if (!strncasecmp(name, "UDP", 3) &&
12100                                          in_tunnel)
12101                                         ptype_mapping[i].sw_ptype |=
12102                                                 RTE_PTYPE_INNER_L4_UDP;
12103                                 else if (!strncasecmp(name, "TCP", 3) &&
12104                                          !in_tunnel)
12105                                         ptype_mapping[i].sw_ptype |=
12106                                                 RTE_PTYPE_L4_TCP;
12107                                 else if (!strncasecmp(name, "TCP", 3) &&
12108                                          in_tunnel)
12109                                         ptype_mapping[i].sw_ptype |=
12110                                                 RTE_PTYPE_INNER_L4_TCP;
12111                                 else if (!strncasecmp(name, "SCTP", 4) &&
12112                                          !in_tunnel)
12113                                         ptype_mapping[i].sw_ptype |=
12114                                                 RTE_PTYPE_L4_SCTP;
12115                                 else if (!strncasecmp(name, "SCTP", 4) &&
12116                                          in_tunnel)
12117                                         ptype_mapping[i].sw_ptype |=
12118                                                 RTE_PTYPE_INNER_L4_SCTP;
12119                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12120                                           !strncasecmp(name, "ICMPV6", 6)) &&
12121                                          !in_tunnel)
12122                                         ptype_mapping[i].sw_ptype |=
12123                                                 RTE_PTYPE_L4_ICMP;
12124                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12125                                           !strncasecmp(name, "ICMPV6", 6)) &&
12126                                          in_tunnel)
12127                                         ptype_mapping[i].sw_ptype |=
12128                                                 RTE_PTYPE_INNER_L4_ICMP;
12129                                 else if (!strncasecmp(name, "GTPC", 4)) {
12130                                         ptype_mapping[i].sw_ptype |=
12131                                                 RTE_PTYPE_TUNNEL_GTPC;
12132                                         in_tunnel = true;
12133                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12134                                         ptype_mapping[i].sw_ptype |=
12135                                                 RTE_PTYPE_TUNNEL_GTPU;
12136                                         in_tunnel = true;
12137                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12138                                         ptype_mapping[i].sw_ptype |=
12139                                                 RTE_PTYPE_TUNNEL_GRENAT;
12140                                         in_tunnel = true;
12141                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12142                                            !strncasecmp(name, "L2TPV2", 6)) {
12143                                         ptype_mapping[i].sw_ptype |=
12144                                                 RTE_PTYPE_TUNNEL_L2TP;
12145                                         in_tunnel = true;
12146                                 }
12147
12148                                 break;
12149                         }
12150                 }
12151         }
12152
12153         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12154                                                 ptype_num, 0);
12155         if (ret)
12156                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12157
12158         rte_free(ptype_mapping);
12159         rte_free(ptype);
12160         return ret;
12161 }
12162
12163 void
12164 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12165                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12166 {
12167         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12168         uint32_t proto_num;
12169         struct rte_pmd_i40e_proto_info *proto;
12170         uint32_t buff_size;
12171         uint32_t i;
12172         int ret;
12173
12174         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12175             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12176                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12177                 return;
12178         }
12179
12180         /* get information about protocol number */
12181         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12182                                        (uint8_t *)&proto_num, sizeof(proto_num),
12183                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12184         if (ret) {
12185                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12186                 return;
12187         }
12188         if (!proto_num) {
12189                 PMD_DRV_LOG(INFO, "No new protocol added");
12190                 return;
12191         }
12192
12193         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12194         proto = rte_zmalloc("new_proto", buff_size, 0);
12195         if (!proto) {
12196                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12197                 return;
12198         }
12199
12200         /* get information about protocol list */
12201         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12202                                         (uint8_t *)proto, buff_size,
12203                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12204         if (ret) {
12205                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12206                 rte_free(proto);
12207                 return;
12208         }
12209
12210         /* Check if GTP is supported. */
12211         for (i = 0; i < proto_num; i++) {
12212                 if (!strncmp(proto[i].name, "GTP", 3)) {
12213                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12214                                 pf->gtp_support = true;
12215                         else
12216                                 pf->gtp_support = false;
12217                         break;
12218                 }
12219         }
12220
12221         /* Update customized pctype info */
12222         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12223                                             proto_num, proto, op);
12224         if (ret)
12225                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12226
12227         /* Update customized ptype info */
12228         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12229                                            proto_num, proto, op);
12230         if (ret)
12231                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12232
12233         rte_free(proto);
12234 }
12235
12236 /* Create a QinQ cloud filter
12237  *
12238  * The Fortville NIC has limited resources for tunnel filters,
12239  * so we can only reuse existing filters.
12240  *
12241  * In step 1 we define which Field Vector fields can be used for
12242  * filter types.
12243  * As we do not have the inner tag defined as a field,
12244  * we have to define it first, by reusing one of L1 entries.
12245  *
12246  * In step 2 we are replacing one of existing filter types with
12247  * a new one for QinQ.
12248  * As we reusing L1 and replacing L2, some of the default filter
12249  * types will disappear,which depends on L1 and L2 entries we reuse.
12250  *
12251  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12252  *
12253  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12254  *              later when we define the cloud filter.
12255  *      a.      Valid_flags.replace_cloud = 0
12256  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12257  *      c.      New_filter = 0x10
12258  *      d.      TR bit = 0xff (optional, not used here)
12259  *      e.      Buffer – 2 entries:
12260  *              i.      Byte 0 = 8 (outer vlan FV index).
12261  *                      Byte 1 = 0 (rsv)
12262  *                      Byte 2-3 = 0x0fff
12263  *              ii.     Byte 0 = 37 (inner vlan FV index).
12264  *                      Byte 1 =0 (rsv)
12265  *                      Byte 2-3 = 0x0fff
12266  *
12267  * Step 2:
12268  * 2.   Create cloud filter using two L1 filters entries: stag and
12269  *              new filter(outer vlan+ inner vlan)
12270  *      a.      Valid_flags.replace_cloud = 1
12271  *      b.      Old_filter = 1 (instead of outer IP)
12272  *      c.      New_filter = 0x10
12273  *      d.      Buffer – 2 entries:
12274  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12275  *                      Byte 1-3 = 0 (rsv)
12276  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12277  *                      Byte 9-11 = 0 (rsv)
12278  */
12279 static int
12280 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12281 {
12282         int ret = -ENOTSUP;
12283         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12284         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12285         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12286         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12287
12288         if (pf->support_multi_driver) {
12289                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12290                 return ret;
12291         }
12292
12293         /* Init */
12294         memset(&filter_replace, 0,
12295                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12296         memset(&filter_replace_buf, 0,
12297                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12298
12299         /* create L1 filter */
12300         filter_replace.old_filter_type =
12301                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12302         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12303         filter_replace.tr_bit = 0;
12304
12305         /* Prepare the buffer, 2 entries */
12306         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12307         filter_replace_buf.data[0] |=
12308                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12309         /* Field Vector 12b mask */
12310         filter_replace_buf.data[2] = 0xff;
12311         filter_replace_buf.data[3] = 0x0f;
12312         filter_replace_buf.data[4] =
12313                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12314         filter_replace_buf.data[4] |=
12315                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12316         /* Field Vector 12b mask */
12317         filter_replace_buf.data[6] = 0xff;
12318         filter_replace_buf.data[7] = 0x0f;
12319         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12320                         &filter_replace_buf);
12321         if (ret != I40E_SUCCESS)
12322                 return ret;
12323
12324         if (filter_replace.old_filter_type !=
12325             filter_replace.new_filter_type)
12326                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12327                             " original: 0x%x, new: 0x%x",
12328                             dev->device->name,
12329                             filter_replace.old_filter_type,
12330                             filter_replace.new_filter_type);
12331
12332         /* Apply the second L2 cloud filter */
12333         memset(&filter_replace, 0,
12334                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12335         memset(&filter_replace_buf, 0,
12336                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12337
12338         /* create L2 filter, input for L2 filter will be L1 filter  */
12339         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12340         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12341         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12342
12343         /* Prepare the buffer, 2 entries */
12344         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12345         filter_replace_buf.data[0] |=
12346                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12347         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12348         filter_replace_buf.data[4] |=
12349                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12350         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12351                         &filter_replace_buf);
12352         if (!ret && (filter_replace.old_filter_type !=
12353                      filter_replace.new_filter_type))
12354                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12355                             " original: 0x%x, new: 0x%x",
12356                             dev->device->name,
12357                             filter_replace.old_filter_type,
12358                             filter_replace.new_filter_type);
12359
12360         return ret;
12361 }
12362
12363 int
12364 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12365                    const struct rte_flow_action_rss *in)
12366 {
12367         if (in->key_len > RTE_DIM(out->key) ||
12368             in->queue_num > RTE_DIM(out->queue))
12369                 return -EINVAL;
12370         out->conf = (struct rte_flow_action_rss){
12371                 .func = in->func,
12372                 .level = in->level,
12373                 .types = in->types,
12374                 .key_len = in->key_len,
12375                 .queue_num = in->queue_num,
12376                 .key = memcpy(out->key, in->key, in->key_len),
12377                 .queue = memcpy(out->queue, in->queue,
12378                                 sizeof(*in->queue) * in->queue_num),
12379         };
12380         return 0;
12381 }
12382
12383 int
12384 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12385                      const struct rte_flow_action_rss *with)
12386 {
12387         return (comp->func == with->func &&
12388                 comp->level == with->level &&
12389                 comp->types == with->types &&
12390                 comp->key_len == with->key_len &&
12391                 comp->queue_num == with->queue_num &&
12392                 !memcmp(comp->key, with->key, with->key_len) &&
12393                 !memcmp(comp->queue, with->queue,
12394                         sizeof(*with->queue) * with->queue_num));
12395 }
12396
12397 int
12398 i40e_config_rss_filter(struct i40e_pf *pf,
12399                 struct i40e_rte_flow_rss_conf *conf, bool add)
12400 {
12401         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12402         uint32_t i, lut = 0;
12403         uint16_t j, num;
12404         struct rte_eth_rss_conf rss_conf = {
12405                 .rss_key = conf->conf.key_len ?
12406                         (void *)(uintptr_t)conf->conf.key : NULL,
12407                 .rss_key_len = conf->conf.key_len,
12408                 .rss_hf = conf->conf.types,
12409         };
12410         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12411
12412         if (!add) {
12413                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12414                         i40e_pf_disable_rss(pf);
12415                         memset(rss_info, 0,
12416                                 sizeof(struct i40e_rte_flow_rss_conf));
12417                         return 0;
12418                 }
12419                 return -EINVAL;
12420         }
12421
12422         if (rss_info->conf.queue_num)
12423                 return -EINVAL;
12424
12425         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12426          * It's necessary to calculate the actual PF queues that are configured.
12427          */
12428         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12429                 num = i40e_pf_calc_configured_queues_num(pf);
12430         else
12431                 num = pf->dev_data->nb_rx_queues;
12432
12433         num = RTE_MIN(num, conf->conf.queue_num);
12434         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12435                         num);
12436
12437         if (num == 0) {
12438                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12439                 return -ENOTSUP;
12440         }
12441
12442         /* Fill in redirection table */
12443         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12444                 if (j == num)
12445                         j = 0;
12446                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12447                         hw->func_caps.rss_table_entry_width) - 1));
12448                 if ((i & 3) == 3)
12449                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12450         }
12451
12452         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12453                 i40e_pf_disable_rss(pf);
12454                 return 0;
12455         }
12456         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12457                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12458                 /* Random default keys */
12459                 static uint32_t rss_key_default[] = {0x6b793944,
12460                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12461                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12462                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12463
12464                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12465                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12466                                                         sizeof(uint32_t);
12467         }
12468
12469         i40e_hw_rss_hash_set(pf, &rss_conf);
12470
12471         if (i40e_rss_conf_init(rss_info, &conf->conf))
12472                 return -EINVAL;
12473
12474         return 0;
12475 }
12476
12477 RTE_INIT(i40e_init_log)
12478 {
12479         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12480         if (i40e_logtype_init >= 0)
12481                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12482         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12483         if (i40e_logtype_driver >= 0)
12484                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12485 }
12486
12487 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12488                               QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12489                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");