drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64
  65 /* Maximun number of MAC addresses */
  66 #define I40E_NUM_MACADDR_MAX       64
  67 #define I40E_CLEAR_PXE_WAIT_MS     200
  68
  69 /* Maximun number of capability elements */
  70 #define I40E_MAX_CAP_ELE_NUM       128
  71
  72 /* Wait count and inteval */
  73 #define I40E_CHK_Q_ENA_COUNT       1000
  74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  75
  76 /* Maximun number of VSI */
  77 #define I40E_MAX_NUM_VSIS          (384UL)
  78
  79 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  80
  81 /* Flow control default timer */
  82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  83
  84 /* Flow control default high water */
  85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  86
  87 /* Flow control default low water */
  88 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Receive Average Packet Size in Byte*/
 100 #define I40E_PACKET_AVERAGE_SIZE 128
 101
 102 /* Mask of PF interrupt causes */
 103 #define I40E_PFINT_ICR0_ENA_MASK ( \
 104                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 105                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 106                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 107                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 108                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 110                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 114
 115 #define I40E_FLOW_TYPES ( \
 116         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 127
 128 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 129 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 130 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 131 #define I40E_PRTTSYN_TSYNENA  0x80000000
 132 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 133
 134 #define I40E_MAX_PERCENT            100
 135 #define I40E_DEFAULT_DCB_APP_NUM    1
 136 #define I40E_DEFAULT_DCB_APP_PRIO   3
 137
 138 #define I40E_PRTQF_FD_INSET(_i, _j)  (0x00250000 + ((_i) * 64 + (_j) * 32))
 139 #define I40E_GLQF_FD_MSK(_i, _j)     (0x00267200 + ((_i) * 4 + (_j) * 8))
 140 #define I40E_GLQF_FD_MSK_FIELD       0x0000FFFF
 141 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))
 142 #define I40E_GLQF_HASH_MSK(_i, _j)   (0x00267A00 + ((_i) * 4 + (_j) * 8))
 143 #define I40E_GLQF_HASH_MSK_FIELD      0x0000FFFF
 144
 145 #define I40E_INSET_NONE            0x00000000000000000ULL
 146
 147 /* bit0 ~ bit 7 */
 148 #define I40E_INSET_DMAC            0x0000000000000001ULL
 149 #define I40E_INSET_SMAC            0x0000000000000002ULL
 150 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 151 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 152 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 153
 154 /* bit 8 ~ bit 15 */
 155 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 156 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 157 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 158 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 159 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 160 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 161 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 162
 163 /* bit 16 ~ bit 31 */
 164 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 165 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 166 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 167 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 168 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 169 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 170 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 171 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 172
 173 /* bit 32 ~ bit 47, tunnel fields */
 174 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 175 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 176 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 177 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 178 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 179 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 180
 181 /* bit 48 ~ bit 55 */
 182 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 183
 184 /* bit 56 ~ bit 63, Flex Payload */
 185 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 191 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 192 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 193 #define I40E_INSET_FLEX_PAYLOAD \
 194         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 195         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W3 | \
 196         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 197         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 198
 199 /**
 200  * Below are values for writing un-exposed registers suggested
 201  * by silicon experts
 202  */
 203 /* Destination MAC address */
 204 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 205 /* Source MAC address */
 206 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 207 /* VLAN tag in the outer L2 header */
 208 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000000800000ULL
 209 /* VLAN tag in the inner L2 header */
 210 #define I40E_REG_INSET_L2_INNER_VLAN             0x0000000001000000ULL
 211 /* Source IPv4 address */
 212 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 213 /* Destination IPv4 address */
 214 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 215 /* IPv4 Type of Service (TOS) */
 216 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 217 /* IPv4 Protocol */
 218 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 219 /* Source IPv6 address */
 220 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 221 /* Destination IPv6 address */
 222 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 223 /* IPv6 Traffic Class (TC) */
 224 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 225 /* IPv6 Next Header */
 226 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 227 /* Source L4 port */
 228 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 229 /* Destination L4 port */
 230 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 231 /* SCTP verification tag */
 232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 235 /* Source port of tunneling UDP */
 236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 237 /* Destination port of tunneling UDP */
 238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 239 /* UDP Tunneling ID, NVGRE/GRE key */
 240 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 241 /* Last ether type */
 242 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 243 /* Tunneling outer destination IPv4 address */
 244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 245 /* Tunneling outer destination IPv6 address */
 246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 247 /* 1st word of flex payload */
 248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 249 /* 2nd word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 251 /* 3rd word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 253 /* 4th word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 255 /* 5th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 257 /* 6th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 259 /* 7th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 261 /* 8th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 263
 264 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 265
 266 #define I40E_TRANSLATE_INSET 0
 267 #define I40E_TRANSLATE_REG   1
 268
 269 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 270 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 271 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 272 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 273
 274 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 275 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 276 static int i40e_dev_configure(struct rte_eth_dev *dev);
 277 static int i40e_dev_start(struct rte_eth_dev *dev);
 278 static void i40e_dev_stop(struct rte_eth_dev *dev);
 279 static void i40e_dev_close(struct rte_eth_dev *dev);
 280 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 281 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 282 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 283 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 284 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 285 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 286 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 287                                struct rte_eth_stats *stats);
 288 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 289                                struct rte_eth_xstats *xstats, unsigned n);
 290 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 291 static void i40e_dev_xstats_reset(struct rte_eth_dev *dev);
 292 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 293                                             uint16_t queue_id,
 294                                             uint8_t stat_idx,
 295                                             uint8_t is_rx);
 296 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 297                               struct rte_eth_dev_info *dev_info);
 298 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 299                                 uint16_t vlan_id,
 300                                 int on);
 301 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 302 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 303 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 304                                       uint16_t queue,
 305                                       int on);
 306 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 307 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 308 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 309 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 310                               struct rte_eth_fc_conf *fc_conf);
 311 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 312                               struct rte_eth_fc_conf *fc_conf);
 313 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 314                                        struct rte_eth_pfc_conf *pfc_conf);
 315 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 316                           struct ether_addr *mac_addr,
 317                           uint32_t index,
 318                           uint32_t pool);
 319 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 320 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 321                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 322                                     uint16_t reta_size);
 323 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 324                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 325                                    uint16_t reta_size);
 326
 327 static int i40e_get_cap(struct i40e_hw *hw);
 328 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 329 static int i40e_pf_setup(struct i40e_pf *pf);
 330 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 331 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 332 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 333 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 334 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 335                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 336 static void i40e_stat_update_48(struct i40e_hw *hw,
 337                                uint32_t hireg,
 338                                uint32_t loreg,
 339                                bool offset_loaded,
 340                                uint64_t *offset,
 341                                uint64_t *stat);
 342 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 343 static void i40e_dev_interrupt_handler(
 344                 __rte_unused struct rte_intr_handle *handle, void *param);
 345 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 346                                 uint32_t base, uint32_t num);
 347 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 348 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 349                         uint32_t base);
 350 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 351                         uint16_t num);
 352 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 353 static int i40e_veb_release(struct i40e_veb *veb);
 354 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 355                                                 struct i40e_vsi *vsi);
 356 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 357 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 358 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 359                                              struct i40e_macvlan_filter *mv_f,
 360                                              int num,
 361                                              struct ether_addr *addr);
 362 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 363                                              struct i40e_macvlan_filter *mv_f,
 364                                              int num,
 365                                              uint16_t vlan);
 366 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 367 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 368                                     struct rte_eth_rss_conf *rss_conf);
 369 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 370                                       struct rte_eth_rss_conf *rss_conf);
 371 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 372                                 struct rte_eth_udp_tunnel *udp_tunnel);
 373 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 374                                 struct rte_eth_udp_tunnel *udp_tunnel);
 375 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 376                         struct rte_eth_ethertype_filter *filter,
 377                         bool add);
 378 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 379                                 enum rte_filter_op filter_op,
 380                                 void *arg);
 381 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 382                                 enum rte_filter_type filter_type,
 383                                 enum rte_filter_op filter_op,
 384                                 void *arg);
 385 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 386                                   struct rte_eth_dcb_info *dcb_info);
 387 static void i40e_configure_registers(struct i40e_hw *hw);
 388 static void i40e_hw_init(struct i40e_hw *hw);
 389 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 390 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 391                         struct rte_eth_mirror_conf *mirror_conf,
 392                         uint8_t sw_id, uint8_t on);
 393 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 394
 395 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 396 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 397 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 398                                            struct timespec *timestamp,
 399                                            uint32_t flags);
 400 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 401                                            struct timespec *timestamp);
 402 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 403 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 404                                          uint16_t queue_id);
 405 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 406                                           uint16_t queue_id);
 407
 408 static const struct rte_pci_id pci_id_i40e_map[] = {
 409 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 410 #include "rte_pci_dev_ids.h"
 411 { .vendor_id = 0, /* sentinel */ },
 412 };
 413
 414 static const struct eth_dev_ops i40e_eth_dev_ops = {
 415         .dev_configure                = i40e_dev_configure,
 416         .dev_start                    = i40e_dev_start,
 417         .dev_stop                     = i40e_dev_stop,
 418         .dev_close                    = i40e_dev_close,
 419         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 420         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 421         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 422         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 423         .dev_set_link_up              = i40e_dev_set_link_up,
 424         .dev_set_link_down            = i40e_dev_set_link_down,
 425         .link_update                  = i40e_dev_link_update,
 426         .stats_get                    = i40e_dev_stats_get,
 427         .xstats_get                   = i40e_dev_xstats_get,
 428         .stats_reset                  = i40e_dev_stats_reset,
 429         .xstats_reset                 = i40e_dev_xstats_reset,
 430         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 431         .dev_infos_get                = i40e_dev_info_get,
 432         .vlan_filter_set              = i40e_vlan_filter_set,
 433         .vlan_tpid_set                = i40e_vlan_tpid_set,
 434         .vlan_offload_set             = i40e_vlan_offload_set,
 435         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 436         .vlan_pvid_set                = i40e_vlan_pvid_set,
 437         .rx_queue_start               = i40e_dev_rx_queue_start,
 438         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 439         .tx_queue_start               = i40e_dev_tx_queue_start,
 440         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 441         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 442         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 443         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 444         .rx_queue_release             = i40e_dev_rx_queue_release,
 445         .rx_queue_count               = i40e_dev_rx_queue_count,
 446         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 447         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 448         .tx_queue_release             = i40e_dev_tx_queue_release,
 449         .dev_led_on                   = i40e_dev_led_on,
 450         .dev_led_off                  = i40e_dev_led_off,
 451         .flow_ctrl_get                = i40e_flow_ctrl_get,
 452         .flow_ctrl_set                = i40e_flow_ctrl_set,
 453         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 454         .mac_addr_add                 = i40e_macaddr_add,
 455         .mac_addr_remove              = i40e_macaddr_remove,
 456         .reta_update                  = i40e_dev_rss_reta_update,
 457         .reta_query                   = i40e_dev_rss_reta_query,
 458         .rss_hash_update              = i40e_dev_rss_hash_update,
 459         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 460         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 461         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 462         .filter_ctrl                  = i40e_dev_filter_ctrl,
 463         .rxq_info_get                 = i40e_rxq_info_get,
 464         .txq_info_get                 = i40e_txq_info_get,
 465         .mirror_rule_set              = i40e_mirror_rule_set,
 466         .mirror_rule_reset            = i40e_mirror_rule_reset,
 467         .timesync_enable              = i40e_timesync_enable,
 468         .timesync_disable             = i40e_timesync_disable,
 469         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 470         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 471         .get_dcb_info                 = i40e_dev_get_dcb_info,
 472 };
 473
 474 /* store statistics names and its offset in stats structure */
 475 struct rte_i40e_xstats_name_off {
 476         char name[RTE_ETH_XSTATS_NAME_SIZE];
 477         unsigned offset;
 478 };
 479
 480 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 481         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 482         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 483         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 484         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 485         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 486                 rx_unknown_protocol)},
 487         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 488         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 489         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 490         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 491 };
 492
 493 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 494         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 495                 tx_dropped_link_down)},
 496         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 497         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 498                 illegal_bytes)},
 499         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 500         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 501                 mac_local_faults)},
 502         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 503                 mac_remote_faults)},
 504         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 505                 rx_length_errors)},
 506         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 507         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 508         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 509         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 510         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 511         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 512                 rx_size_127)},
 513         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 514                 rx_size_255)},
 515         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 516                 rx_size_511)},
 517         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 518                 rx_size_1023)},
 519         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 520                 rx_size_1522)},
 521         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 522                 rx_size_big)},
 523         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 524                 rx_undersize)},
 525         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 526                 rx_oversize)},
 527         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 528                 mac_short_packet_dropped)},
 529         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 530                 rx_fragments)},
 531         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 532         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 533         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 534                 tx_size_127)},
 535         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 536                 tx_size_255)},
 537         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 538                 tx_size_511)},
 539         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 540                 tx_size_1023)},
 541         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 542                 tx_size_1522)},
 543         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 544                 tx_size_big)},
 545         {"rx_flow_director_atr_match_packets",
 546                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 547         {"rx_flow_director_sb_match_packets",
 548                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 549         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 550                 tx_lpi_status)},
 551         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 552                 rx_lpi_status)},
 553         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 554                 tx_lpi_count)},
 555         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 556                 rx_lpi_count)},
 557 };
 558
 559 /* Q Stats: 5 stats are exposed for each queue, implemented in xstats_get() */
 560 #define I40E_NB_HW_PORT_Q_STATS (8 * 5)
 561
 562 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 563                 sizeof(rte_i40e_stats_strings[0]))
 564 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 565                 sizeof(rte_i40e_hw_port_strings[0]))
 566 #define I40E_NB_XSTATS (I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + \
 567                 I40E_NB_HW_PORT_Q_STATS)
 568
 569 static struct eth_driver rte_i40e_pmd = {
 570         .pci_drv = {
 571                 .name = "rte_i40e_pmd",
 572                 .id_table = pci_id_i40e_map,
 573                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 574                         RTE_PCI_DRV_DETACHABLE,
 575         },
 576         .eth_dev_init = eth_i40e_dev_init,
 577         .eth_dev_uninit = eth_i40e_dev_uninit,
 578         .dev_private_size = sizeof(struct i40e_adapter),
 579 };
 580
 581 static inline int
 582 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 583                                      struct rte_eth_link *link)
 584 {
 585         struct rte_eth_link *dst = link;
 586         struct rte_eth_link *src = &(dev->data->dev_link);
 587
 588         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 589                                         *(uint64_t *)src) == 0)
 590                 return -1;
 591
 592         return 0;
 593 }
 594
 595 static inline int
 596 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 597                                       struct rte_eth_link *link)
 598 {
 599         struct rte_eth_link *dst = &(dev->data->dev_link);
 600         struct rte_eth_link *src = link;
 601
 602         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 603                                         *(uint64_t *)src) == 0)
 604                 return -1;
 605
 606         return 0;
 607 }
 608
 609 /*
 610  * Driver initialization routine.
 611  * Invoked once at EAL init time.
 612  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 613  */
 614 static int
 615 rte_i40e_pmd_init(const char *name __rte_unused,
 616                   const char *params __rte_unused)
 617 {
 618         PMD_INIT_FUNC_TRACE();
 619         rte_eth_driver_register(&rte_i40e_pmd);
 620
 621         return 0;
 622 }
 623
 624 static struct rte_driver rte_i40e_driver = {
 625         .type = PMD_PDEV,
 626         .init = rte_i40e_pmd_init,
 627 };
 628
 629 PMD_REGISTER_DRIVER(rte_i40e_driver);
 630
 631 /*
 632  * Initialize registers for flexible payload, which should be set by NVM.
 633  * This should be removed from code once it is fixed in NVM.
 634  */
 635 #ifndef I40E_GLQF_ORT
 636 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 637 #endif
 638 #ifndef I40E_GLQF_PIT
 639 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 640 #endif
 641
 642 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 643 {
 644         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 645         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 646         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 647         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 648         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 649         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 650         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 651         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 652         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 653         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 654
 655         /* GLQF_PIT Registers */
 656         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 657         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 658 }
 659
 660 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 661
 662 /*
 663  * Add a ethertype filter to drop all flow control frames transmitted
 664  * from VSIs.
 665 */
 666 static void
 667 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 668 {
 669         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 670         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 671                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 672                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 673         int ret;
 674
 675         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 676                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 677                                 pf->main_vsi_seid, 0,
 678                                 TRUE, NULL, NULL);
 679         if (ret)
 680                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 681                                   " frames from VSIs.");
 682 }
 683
 684 static int
 685 eth_i40e_dev_init(struct rte_eth_dev *dev)
 686 {
 687         struct rte_pci_device *pci_dev;
 688         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 689         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 690         struct i40e_vsi *vsi;
 691         int ret;
 692         uint32_t len;
 693         uint8_t aq_fail = 0;
 694
 695         PMD_INIT_FUNC_TRACE();
 696
 697         dev->dev_ops = &i40e_eth_dev_ops;
 698         dev->rx_pkt_burst = i40e_recv_pkts;
 699         dev->tx_pkt_burst = i40e_xmit_pkts;
 700
 701         /* for secondary processes, we don't initialise any further as primary
 702          * has already done this work. Only check we don't need a different
 703          * RX function */
 704         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 705                 i40e_set_rx_function(dev);
 706                 i40e_set_tx_function(dev);
 707                 return 0;
 708         }
 709         pci_dev = dev->pci_dev;
 710
 711         rte_eth_copy_pci_info(dev, pci_dev);
 712
 713         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 714         pf->adapter->eth_dev = dev;
 715         pf->dev_data = dev->data;
 716
 717         hw->back = I40E_PF_TO_ADAPTER(pf);
 718         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 719         if (!hw->hw_addr) {
 720                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 721                              "as address is NULL");
 722                 return -ENODEV;
 723         }
 724
 725         hw->vendor_id = pci_dev->id.vendor_id;
 726         hw->device_id = pci_dev->id.device_id;
 727         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 728         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 729         hw->bus.device = pci_dev->addr.devid;
 730         hw->bus.func = pci_dev->addr.function;
 731         hw->adapter_stopped = 0;
 732
 733         /* Make sure all is clean before doing PF reset */
 734         i40e_clear_hw(hw);
 735
 736         /* Initialize the hardware */
 737         i40e_hw_init(hw);
 738
 739         /* Reset here to make sure all is clean for each PF */
 740         ret = i40e_pf_reset(hw);
 741         if (ret) {
 742                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 743                 return ret;
 744         }
 745
 746         /* Initialize the shared code (base driver) */
 747         ret = i40e_init_shared_code(hw);
 748         if (ret) {
 749                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 750                 return ret;
 751         }
 752
 753         /*
 754          * To work around the NVM issue,initialize registers
 755          * for flexible payload by software.
 756          * It should be removed once issues are fixed in NVM.
 757          */
 758         i40e_flex_payload_reg_init(hw);
 759
 760         /* Initialize the parameters for adminq */
 761         i40e_init_adminq_parameter(hw);
 762         ret = i40e_init_adminq(hw);
 763         if (ret != I40E_SUCCESS) {
 764                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 765                 return -EIO;
 766         }
 767         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 768                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 769                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 770                      ((hw->nvm.version >> 12) & 0xf),
 771                      ((hw->nvm.version >> 4) & 0xff),
 772                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 773
 774         /* Clear PXE mode */
 775         i40e_clear_pxe_mode(hw);
 776
 777         /*
 778          * On X710, performance number is far from the expectation on recent
 779          * firmware versions. The fix for this issue may not be integrated in
 780          * the following firmware version. So the workaround in software driver
 781          * is needed. It needs to modify the initial values of 3 internal only
 782          * registers. Note that the workaround can be removed when it is fixed
 783          * in firmware in the future.
 784          */
 785         i40e_configure_registers(hw);
 786
 787         /* Get hw capabilities */
 788         ret = i40e_get_cap(hw);
 789         if (ret != I40E_SUCCESS) {
 790                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 791                 goto err_get_capabilities;
 792         }
 793
 794         /* Initialize parameters for PF */
 795         ret = i40e_pf_parameter_init(dev);
 796         if (ret != 0) {
 797                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 798                 goto err_parameter_init;
 799         }
 800
 801         /* Initialize the queue management */
 802         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 803         if (ret < 0) {
 804                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 805                 goto err_qp_pool_init;
 806         }
 807         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 808                                 hw->func_caps.num_msix_vectors - 1);
 809         if (ret < 0) {
 810                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 811                 goto err_msix_pool_init;
 812         }
 813
 814         /* Initialize lan hmc */
 815         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 816                                 hw->func_caps.num_rx_qp, 0, 0);
 817         if (ret != I40E_SUCCESS) {
 818                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 819                 goto err_init_lan_hmc;
 820         }
 821
 822         /* Configure lan hmc */
 823         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 824         if (ret != I40E_SUCCESS) {
 825                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 826                 goto err_configure_lan_hmc;
 827         }
 828
 829         /* Get and check the mac address */
 830         i40e_get_mac_addr(hw, hw->mac.addr);
 831         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 832                 PMD_INIT_LOG(ERR, "mac address is not valid");
 833                 ret = -EIO;
 834                 goto err_get_mac_addr;
 835         }
 836         /* Copy the permanent MAC address */
 837         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 838                         (struct ether_addr *) hw->mac.perm_addr);
 839
 840         /* Disable flow control */
 841         hw->fc.requested_mode = I40E_FC_NONE;
 842         i40e_set_fc(hw, &aq_fail, TRUE);
 843
 844         /* PF setup, which includes VSI setup */
 845         ret = i40e_pf_setup(pf);
 846         if (ret) {
 847                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 848                 goto err_setup_pf_switch;
 849         }
 850
 851         vsi = pf->main_vsi;
 852
 853         /* Disable double vlan by default */
 854         i40e_vsi_config_double_vlan(vsi, FALSE);
 855
 856         if (!vsi->max_macaddrs)
 857                 len = ETHER_ADDR_LEN;
 858         else
 859                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 860
 861         /* Should be after VSI initialized */
 862         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 863         if (!dev->data->mac_addrs) {
 864                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 865                                         "for storing mac address");
 866                 goto err_mac_alloc;
 867         }
 868         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 869                                         &dev->data->mac_addrs[0]);
 870
 871         /* initialize pf host driver to setup SRIOV resource if applicable */
 872         i40e_pf_host_init(dev);
 873
 874         /* register callback func to eal lib */
 875         rte_intr_callback_register(&(pci_dev->intr_handle),
 876                 i40e_dev_interrupt_handler, (void *)dev);
 877
 878         /* configure and enable device interrupt */
 879         i40e_pf_config_irq0(hw, TRUE);
 880         i40e_pf_enable_irq0(hw);
 881
 882         /* enable uio intr after callback register */
 883         rte_intr_enable(&(pci_dev->intr_handle));
 884         /*
 885          * Add an ethertype filter to drop all flow control frames transmitted
 886          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 887          * frames to wire.
 888          */
 889         i40e_add_tx_flow_control_drop_filter(pf);
 890
 891         /* initialize mirror rule list */
 892         TAILQ_INIT(&pf->mirror_list);
 893
 894         /* Init dcb to sw mode by default */
 895         ret = i40e_dcb_init_configure(dev, TRUE);
 896         if (ret != I40E_SUCCESS) {
 897                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 898                 pf->flags &= ~I40E_FLAG_DCB;
 899         }
 900
 901         return 0;
 902
 903 err_mac_alloc:
 904         i40e_vsi_release(pf->main_vsi);
 905 err_setup_pf_switch:
 906 err_get_mac_addr:
 907 err_configure_lan_hmc:
 908         (void)i40e_shutdown_lan_hmc(hw);
 909 err_init_lan_hmc:
 910         i40e_res_pool_destroy(&pf->msix_pool);
 911 err_msix_pool_init:
 912         i40e_res_pool_destroy(&pf->qp_pool);
 913 err_qp_pool_init:
 914 err_parameter_init:
 915 err_get_capabilities:
 916         (void)i40e_shutdown_adminq(hw);
 917
 918         return ret;
 919 }
 920
 921 static int
 922 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 923 {
 924         struct rte_pci_device *pci_dev;
 925         struct i40e_hw *hw;
 926         struct i40e_filter_control_settings settings;
 927         int ret;
 928         uint8_t aq_fail = 0;
 929
 930         PMD_INIT_FUNC_TRACE();
 931
 932         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 933                 return 0;
 934
 935         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 936         pci_dev = dev->pci_dev;
 937
 938         if (hw->adapter_stopped == 0)
 939                 i40e_dev_close(dev);
 940
 941         dev->dev_ops = NULL;
 942         dev->rx_pkt_burst = NULL;
 943         dev->tx_pkt_burst = NULL;
 944
 945         /* Disable LLDP */
 946         ret = i40e_aq_stop_lldp(hw, true, NULL);
 947         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 948                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 949
 950         /* Clear PXE mode */
 951         i40e_clear_pxe_mode(hw);
 952
 953         /* Unconfigure filter control */
 954         memset(&settings, 0, sizeof(settings));
 955         ret = i40e_set_filter_control(hw, &settings);
 956         if (ret)
 957                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 958                                         ret);
 959
 960         /* Disable flow control */
 961         hw->fc.requested_mode = I40E_FC_NONE;
 962         i40e_set_fc(hw, &aq_fail, TRUE);
 963
 964         /* uninitialize pf host driver */
 965         i40e_pf_host_uninit(dev);
 966
 967         rte_free(dev->data->mac_addrs);
 968         dev->data->mac_addrs = NULL;
 969
 970         /* disable uio intr before callback unregister */
 971         rte_intr_disable(&(pci_dev->intr_handle));
 972
 973         /* register callback func to eal lib */
 974         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 975                 i40e_dev_interrupt_handler, (void *)dev);
 976
 977         return 0;
 978 }
 979
 980 static int
 981 i40e_dev_configure(struct rte_eth_dev *dev)
 982 {
 983         struct i40e_adapter *ad =
 984                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 985         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 986         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 987         int i, ret;
 988
 989         /* Initialize to TRUE. If any of Rx queues doesn't meet the
 990          * bulk allocation or vector Rx preconditions we will reset it.
 991          */
 992         ad->rx_bulk_alloc_allowed = true;
 993         ad->rx_vec_allowed = true;
 994         ad->tx_simple_allowed = true;
 995         ad->tx_vec_allowed = true;
 996
 997         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 998                 ret = i40e_fdir_setup(pf);
 999                 if (ret != I40E_SUCCESS) {
1000                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1001                         return -ENOTSUP;
1002                 }
1003                 ret = i40e_fdir_configure(dev);
1004                 if (ret < 0) {
1005                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1006                         goto err;
1007                 }
1008         } else
1009                 i40e_fdir_teardown(pf);
1010
1011         ret = i40e_dev_init_vlan(dev);
1012         if (ret < 0)
1013                 goto err;
1014
1015         /* VMDQ setup.
1016          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1017          *  RSS setting have different requirements.
1018          *  General PMD driver call sequence are NIC init, configure,
1019          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1020          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1021          *  applicable. So, VMDQ setting has to be done before
1022          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1023          *  For RSS setting, it will try to calculate actual configured RX queue
1024          *  number, which will be available after rx_queue_setup(). dev_start()
1025          *  function is good to place RSS setup.
1026          */
1027         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1028                 ret = i40e_vmdq_setup(dev);
1029                 if (ret)
1030                         goto err;
1031         }
1032
1033         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1034                 ret = i40e_dcb_setup(dev);
1035                 if (ret) {
1036                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1037                         goto err_dcb;
1038                 }
1039         }
1040
1041         return 0;
1042
1043 err_dcb:
1044         /* need to release vmdq resource if exists */
1045         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1046                 i40e_vsi_release(pf->vmdq[i].vsi);
1047                 pf->vmdq[i].vsi = NULL;
1048         }
1049         rte_free(pf->vmdq);
1050         pf->vmdq = NULL;
1051 err:
1052         /* need to release fdir resource if exists */
1053         i40e_fdir_teardown(pf);
1054         return ret;
1055 }
1056
1057 void
1058 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1059 {
1060         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1061         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1062         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1063         uint16_t msix_vect = vsi->msix_intr;
1064         uint16_t i;
1065
1066         for (i = 0; i < vsi->nb_qps; i++) {
1067                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1068                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1069                 rte_wmb();
1070         }
1071
1072         if (vsi->type != I40E_VSI_SRIOV) {
1073                 if (!rte_intr_allow_others(intr_handle)) {
1074                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1075                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1076                         I40E_WRITE_REG(hw,
1077                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1078                                        0);
1079                 } else {
1080                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1081                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1082                         I40E_WRITE_REG(hw,
1083                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1084                                                        msix_vect - 1), 0);
1085                 }
1086         } else {
1087                 uint32_t reg;
1088                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1089                         vsi->user_param + (msix_vect - 1);
1090
1091                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1092                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1093         }
1094         I40E_WRITE_FLUSH(hw);
1095 }
1096
1097 static void
1098 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1099                        int base_queue, int nb_queue)
1100 {
1101         int i;
1102         uint32_t val;
1103         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1104
1105         /* Bind all RX queues to allocated MSIX interrupt */
1106         for (i = 0; i < nb_queue; i++) {
1107                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1108                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1109                         ((base_queue + i + 1) <<
1110                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1111                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1112                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1113
1114                 if (i == nb_queue - 1)
1115                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1116                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1117         }
1118
1119         /* Write first RX queue to Link list register as the head element */
1120         if (vsi->type != I40E_VSI_SRIOV) {
1121                 uint16_t interval =
1122                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1123
1124                 if (msix_vect == I40E_MISC_VEC_ID) {
1125                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1126                                        (base_queue <<
1127                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1128                                        (0x0 <<
1129                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1130                         I40E_WRITE_REG(hw,
1131                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1132                                        interval);
1133                 } else {
1134                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1135                                        (base_queue <<
1136                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1137                                        (0x0 <<
1138                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1139                         I40E_WRITE_REG(hw,
1140                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1141                                                        msix_vect - 1),
1142                                        interval);
1143                 }
1144         } else {
1145                 uint32_t reg;
1146
1147                 if (msix_vect == I40E_MISC_VEC_ID) {
1148                         I40E_WRITE_REG(hw,
1149                                        I40E_VPINT_LNKLST0(vsi->user_param),
1150                                        (base_queue <<
1151                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1152                                        (0x0 <<
1153                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1154                 } else {
1155                         /* num_msix_vectors_vf needs to minus irq0 */
1156                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1157                                 vsi->user_param + (msix_vect - 1);
1158
1159                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1160                                        (base_queue <<
1161                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1162                                        (0x0 <<
1163                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1164                 }
1165         }
1166
1167         I40E_WRITE_FLUSH(hw);
1168 }
1169
1170 void
1171 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1172 {
1173         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1174         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1175         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1176         uint16_t msix_vect = vsi->msix_intr;
1177         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1178         uint16_t queue_idx = 0;
1179         int record = 0;
1180         uint32_t val;
1181         int i;
1182
1183         for (i = 0; i < vsi->nb_qps; i++) {
1184                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1185                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1186         }
1187
1188         /* INTENA flag is not auto-cleared for interrupt */
1189         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1190         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1191                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1192                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1193         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1194
1195         /* VF bind interrupt */
1196         if (vsi->type == I40E_VSI_SRIOV) {
1197                 __vsi_queues_bind_intr(vsi, msix_vect,
1198                                        vsi->base_queue, vsi->nb_qps);
1199                 return;
1200         }
1201
1202         /* PF & VMDq bind interrupt */
1203         if (rte_intr_dp_is_en(intr_handle)) {
1204                 if (vsi->type == I40E_VSI_MAIN) {
1205                         queue_idx = 0;
1206                         record = 1;
1207                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1208                         struct i40e_vsi *main_vsi =
1209                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1210                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1211                         record = 1;
1212                 }
1213         }
1214
1215         for (i = 0; i < vsi->nb_used_qps; i++) {
1216                 if (nb_msix <= 1) {
1217                         if (!rte_intr_allow_others(intr_handle))
1218                                 /* allow to share MISC_VEC_ID */
1219                                 msix_vect = I40E_MISC_VEC_ID;
1220
1221                         /* no enough msix_vect, map all to one */
1222                         __vsi_queues_bind_intr(vsi, msix_vect,
1223                                                vsi->base_queue + i,
1224                                                vsi->nb_used_qps - i);
1225                         for (; !!record && i < vsi->nb_used_qps; i++)
1226                                 intr_handle->intr_vec[queue_idx + i] =
1227                                         msix_vect;
1228                         break;
1229                 }
1230                 /* 1:1 queue/msix_vect mapping */
1231                 __vsi_queues_bind_intr(vsi, msix_vect,
1232                                        vsi->base_queue + i, 1);
1233                 if (!!record)
1234                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1235
1236                 msix_vect++;
1237                 nb_msix--;
1238         }
1239 }
1240
1241 static void
1242 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1243 {
1244         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1245         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1246         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1247         uint16_t interval = i40e_calc_itr_interval(\
1248                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1249         uint16_t msix_intr, i;
1250
1251         if (rte_intr_allow_others(intr_handle))
1252                 for (i = 0; i < vsi->nb_msix; i++) {
1253                         msix_intr = vsi->msix_intr + i;
1254                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1255                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1256                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1257                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1258                                 (interval <<
1259                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1260                 }
1261         else
1262                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1263                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1264                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1265                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1266                                (interval <<
1267                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1268
1269         I40E_WRITE_FLUSH(hw);
1270 }
1271
1272 static void
1273 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1274 {
1275         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1276         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1277         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1278         uint16_t msix_intr, i;
1279
1280         if (rte_intr_allow_others(intr_handle))
1281                 for (i = 0; i < vsi->nb_msix; i++) {
1282                         msix_intr = vsi->msix_intr + i;
1283                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1284                                        0);
1285                 }
1286         else
1287                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1288
1289         I40E_WRITE_FLUSH(hw);
1290 }
1291
1292 static inline uint8_t
1293 i40e_parse_link_speed(uint16_t eth_link_speed)
1294 {
1295         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1296
1297         switch (eth_link_speed) {
1298         case ETH_LINK_SPEED_40G:
1299                 link_speed = I40E_LINK_SPEED_40GB;
1300                 break;
1301         case ETH_LINK_SPEED_20G:
1302                 link_speed = I40E_LINK_SPEED_20GB;
1303                 break;
1304         case ETH_LINK_SPEED_10G:
1305                 link_speed = I40E_LINK_SPEED_10GB;
1306                 break;
1307         case ETH_LINK_SPEED_1000:
1308                 link_speed = I40E_LINK_SPEED_1GB;
1309                 break;
1310         case ETH_LINK_SPEED_100:
1311                 link_speed = I40E_LINK_SPEED_100MB;
1312                 break;
1313         }
1314
1315         return link_speed;
1316 }
1317
1318 static int
1319 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
1320 {
1321         enum i40e_status_code status;
1322         struct i40e_aq_get_phy_abilities_resp phy_ab;
1323         struct i40e_aq_set_phy_config phy_conf;
1324         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1325                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1326                         I40E_AQ_PHY_FLAG_LOW_POWER;
1327         const uint8_t advt = I40E_LINK_SPEED_40GB |
1328                         I40E_LINK_SPEED_10GB |
1329                         I40E_LINK_SPEED_1GB |
1330                         I40E_LINK_SPEED_100MB;
1331         int ret = -ENOTSUP;
1332
1333         /* Skip it on 40G interfaces, as a workaround for the link issue */
1334         if (i40e_is_40G_device(hw->device_id))
1335                 return I40E_SUCCESS;
1336
1337         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1338                                               NULL);
1339         if (status)
1340                 return ret;
1341
1342         memset(&phy_conf, 0, sizeof(phy_conf));
1343
1344         /* bits 0-2 use the values from get_phy_abilities_resp */
1345         abilities &= ~mask;
1346         abilities |= phy_ab.abilities & mask;
1347
1348         /* update ablities and speed */
1349         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1350                 phy_conf.link_speed = advt;
1351         else
1352                 phy_conf.link_speed = force_speed;
1353
1354         phy_conf.abilities = abilities;
1355
1356         /* use get_phy_abilities_resp value for the rest */
1357         phy_conf.phy_type = phy_ab.phy_type;
1358         phy_conf.eee_capability = phy_ab.eee_capability;
1359         phy_conf.eeer = phy_ab.eeer_val;
1360         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1361
1362         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1363                     phy_ab.abilities, phy_ab.link_speed);
1364         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1365                     phy_conf.abilities, phy_conf.link_speed);
1366
1367         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1368         if (status)
1369                 return ret;
1370
1371         return I40E_SUCCESS;
1372 }
1373
1374 static int
1375 i40e_apply_link_speed(struct rte_eth_dev *dev)
1376 {
1377         uint8_t speed;
1378         uint8_t abilities = 0;
1379         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1380         struct rte_eth_conf *conf = &dev->data->dev_conf;
1381
1382         speed = i40e_parse_link_speed(conf->link_speed);
1383         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1384         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1385                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1386         else
1387                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1388
1389         return i40e_phy_conf_link(hw, abilities, speed);
1390 }
1391
1392 static int
1393 i40e_dev_start(struct rte_eth_dev *dev)
1394 {
1395         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1396         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397         struct i40e_vsi *main_vsi = pf->main_vsi;
1398         int ret, i;
1399         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1400         uint32_t intr_vector = 0;
1401
1402         hw->adapter_stopped = 0;
1403
1404         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1405                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1406                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1407                              dev->data->dev_conf.link_duplex,
1408                              dev->data->port_id);
1409                 return -EINVAL;
1410         }
1411
1412         rte_intr_disable(intr_handle);
1413
1414         if ((rte_intr_cap_multiple(intr_handle) ||
1415              !RTE_ETH_DEV_SRIOV(dev).active) &&
1416             dev->data->dev_conf.intr_conf.rxq != 0) {
1417                 intr_vector = dev->data->nb_rx_queues;
1418                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1419                         return -1;
1420         }
1421
1422         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1423                 intr_handle->intr_vec =
1424                         rte_zmalloc("intr_vec",
1425                                     dev->data->nb_rx_queues * sizeof(int),
1426                                     0);
1427                 if (!intr_handle->intr_vec) {
1428                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1429                                      " intr_vec\n", dev->data->nb_rx_queues);
1430                         return -ENOMEM;
1431                 }
1432         }
1433
1434         /* Initialize VSI */
1435         ret = i40e_dev_rxtx_init(pf);
1436         if (ret != I40E_SUCCESS) {
1437                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1438                 goto err_up;
1439         }
1440
1441         /* Map queues with MSIX interrupt */
1442         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1443                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1444         i40e_vsi_queues_bind_intr(main_vsi);
1445         i40e_vsi_enable_queues_intr(main_vsi);
1446
1447         /* Map VMDQ VSI queues with MSIX interrupt */
1448         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1449                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1450                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1451                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1452         }
1453
1454         /* enable FDIR MSIX interrupt */
1455         if (pf->fdir.fdir_vsi) {
1456                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1457                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1458         }
1459
1460         /* Enable all queues which have been configured */
1461         ret = i40e_dev_switch_queues(pf, TRUE);
1462         if (ret != I40E_SUCCESS) {
1463                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1464                 goto err_up;
1465         }
1466
1467         /* Enable receiving broadcast packets */
1468         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1469         if (ret != I40E_SUCCESS)
1470                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1471
1472         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1473                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1474                                                 true, NULL);
1475                 if (ret != I40E_SUCCESS)
1476                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1477         }
1478
1479         /* Apply link configure */
1480         ret = i40e_apply_link_speed(dev);
1481         if (I40E_SUCCESS != ret) {
1482                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1483                 goto err_up;
1484         }
1485
1486         if (!rte_intr_allow_others(intr_handle)) {
1487                 rte_intr_callback_unregister(intr_handle,
1488                                              i40e_dev_interrupt_handler,
1489                                              (void *)dev);
1490                 /* configure and enable device interrupt */
1491                 i40e_pf_config_irq0(hw, FALSE);
1492                 i40e_pf_enable_irq0(hw);
1493
1494                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1495                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1496                                      " no intr multiplex\n");
1497         }
1498
1499         /* enable uio intr after callback register */
1500         rte_intr_enable(intr_handle);
1501
1502         return I40E_SUCCESS;
1503
1504 err_up:
1505         i40e_dev_switch_queues(pf, FALSE);
1506         i40e_dev_clear_queues(dev);
1507
1508         return ret;
1509 }
1510
1511 static void
1512 i40e_dev_stop(struct rte_eth_dev *dev)
1513 {
1514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1515         struct i40e_vsi *main_vsi = pf->main_vsi;
1516         struct i40e_mirror_rule *p_mirror;
1517         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1518         int i;
1519
1520         /* Disable all queues */
1521         i40e_dev_switch_queues(pf, FALSE);
1522
1523         /* un-map queues with interrupt registers */
1524         i40e_vsi_disable_queues_intr(main_vsi);
1525         i40e_vsi_queues_unbind_intr(main_vsi);
1526
1527         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1528                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1529                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1530         }
1531
1532         if (pf->fdir.fdir_vsi) {
1533                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1534                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1535         }
1536         /* Clear all queues and release memory */
1537         i40e_dev_clear_queues(dev);
1538
1539         /* Set link down */
1540         i40e_dev_set_link_down(dev);
1541
1542         /* Remove all mirror rules */
1543         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1544                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1545                 rte_free(p_mirror);
1546         }
1547         pf->nb_mirror_rule = 0;
1548
1549         if (!rte_intr_allow_others(intr_handle))
1550                 /* resume to the default handler */
1551                 rte_intr_callback_register(intr_handle,
1552                                            i40e_dev_interrupt_handler,
1553                                            (void *)dev);
1554
1555         /* Clean datapath event and queue/vec mapping */
1556         rte_intr_efd_disable(intr_handle);
1557         if (intr_handle->intr_vec) {
1558                 rte_free(intr_handle->intr_vec);
1559                 intr_handle->intr_vec = NULL;
1560         }
1561 }
1562
1563 static void
1564 i40e_dev_close(struct rte_eth_dev *dev)
1565 {
1566         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1567         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1568         uint32_t reg;
1569         int i;
1570
1571         PMD_INIT_FUNC_TRACE();
1572
1573         i40e_dev_stop(dev);
1574         hw->adapter_stopped = 1;
1575         i40e_dev_free_queues(dev);
1576
1577         /* Disable interrupt */
1578         i40e_pf_disable_irq0(hw);
1579         rte_intr_disable(&(dev->pci_dev->intr_handle));
1580
1581         /* shutdown and destroy the HMC */
1582         i40e_shutdown_lan_hmc(hw);
1583
1584         /* release all the existing VSIs and VEBs */
1585         i40e_fdir_teardown(pf);
1586         i40e_vsi_release(pf->main_vsi);
1587
1588         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1589                 i40e_vsi_release(pf->vmdq[i].vsi);
1590                 pf->vmdq[i].vsi = NULL;
1591         }
1592
1593         rte_free(pf->vmdq);
1594         pf->vmdq = NULL;
1595
1596         /* shutdown the adminq */
1597         i40e_aq_queue_shutdown(hw, true);
1598         i40e_shutdown_adminq(hw);
1599
1600         i40e_res_pool_destroy(&pf->qp_pool);
1601         i40e_res_pool_destroy(&pf->msix_pool);
1602
1603         /* force a PF reset to clean anything leftover */
1604         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1605         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1606                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1607         I40E_WRITE_FLUSH(hw);
1608 }
1609
1610 static void
1611 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1612 {
1613         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1614         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1615         struct i40e_vsi *vsi = pf->main_vsi;
1616         int status;
1617
1618         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1619                                                         true, NULL);
1620         if (status != I40E_SUCCESS)
1621                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1622
1623         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1624                                                         TRUE, NULL);
1625         if (status != I40E_SUCCESS)
1626                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1627
1628 }
1629
1630 static void
1631 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1632 {
1633         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1634         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1635         struct i40e_vsi *vsi = pf->main_vsi;
1636         int status;
1637
1638         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1639                                                         false, NULL);
1640         if (status != I40E_SUCCESS)
1641                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1642
1643         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1644                                                         false, NULL);
1645         if (status != I40E_SUCCESS)
1646                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1647 }
1648
1649 static void
1650 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1651 {
1652         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1653         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654         struct i40e_vsi *vsi = pf->main_vsi;
1655         int ret;
1656
1657         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1658         if (ret != I40E_SUCCESS)
1659                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1660 }
1661
1662 static void
1663 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1664 {
1665         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1666         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1667         struct i40e_vsi *vsi = pf->main_vsi;
1668         int ret;
1669
1670         if (dev->data->promiscuous == 1)
1671                 return; /* must remain in all_multicast mode */
1672
1673         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1674                                 vsi->seid, FALSE, NULL);
1675         if (ret != I40E_SUCCESS)
1676                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1677 }
1678
1679 /*
1680  * Set device link up.
1681  */
1682 static int
1683 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1684 {
1685         /* re-apply link speed setting */
1686         return i40e_apply_link_speed(dev);
1687 }
1688
1689 /*
1690  * Set device link down.
1691  */
1692 static int
1693 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1694 {
1695         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1696         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1697         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1698
1699         return i40e_phy_conf_link(hw, abilities, speed);
1700 }
1701
1702 int
1703 i40e_dev_link_update(struct rte_eth_dev *dev,
1704                      int wait_to_complete)
1705 {
1706 #define CHECK_INTERVAL 100  /* 100ms */
1707 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1708         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709         struct i40e_link_status link_status;
1710         struct rte_eth_link link, old;
1711         int status;
1712         unsigned rep_cnt = MAX_REPEAT_TIME;
1713
1714         memset(&link, 0, sizeof(link));
1715         memset(&old, 0, sizeof(old));
1716         memset(&link_status, 0, sizeof(link_status));
1717         rte_i40e_dev_atomic_read_link_status(dev, &old);
1718
1719         do {
1720                 /* Get link status information from hardware */
1721                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1722                 if (status != I40E_SUCCESS) {
1723                         link.link_speed = ETH_LINK_SPEED_100;
1724                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1725                         PMD_DRV_LOG(ERR, "Failed to get link info");
1726                         goto out;
1727                 }
1728
1729                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1730                 if (!wait_to_complete)
1731                         break;
1732
1733                 rte_delay_ms(CHECK_INTERVAL);
1734         } while (!link.link_status && rep_cnt--);
1735
1736         if (!link.link_status)
1737                 goto out;
1738
1739         /* i40e uses full duplex only */
1740         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1741
1742         /* Parse the link status */
1743         switch (link_status.link_speed) {
1744         case I40E_LINK_SPEED_100MB:
1745                 link.link_speed = ETH_LINK_SPEED_100;
1746                 break;
1747         case I40E_LINK_SPEED_1GB:
1748                 link.link_speed = ETH_LINK_SPEED_1000;
1749                 break;
1750         case I40E_LINK_SPEED_10GB:
1751                 link.link_speed = ETH_LINK_SPEED_10G;
1752                 break;
1753         case I40E_LINK_SPEED_20GB:
1754                 link.link_speed = ETH_LINK_SPEED_20G;
1755                 break;
1756         case I40E_LINK_SPEED_40GB:
1757                 link.link_speed = ETH_LINK_SPEED_40G;
1758                 break;
1759         default:
1760                 link.link_speed = ETH_LINK_SPEED_100;
1761                 break;
1762         }
1763
1764 out:
1765         rte_i40e_dev_atomic_write_link_status(dev, &link);
1766         if (link.link_status == old.link_status)
1767                 return -1;
1768
1769         return 0;
1770 }
1771
1772 /* Get all the statistics of a VSI */
1773 void
1774 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1775 {
1776         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1777         struct i40e_eth_stats *nes = &vsi->eth_stats;
1778         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1779         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1780
1781         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1782                             vsi->offset_loaded, &oes->rx_bytes,
1783                             &nes->rx_bytes);
1784         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1785                             vsi->offset_loaded, &oes->rx_unicast,
1786                             &nes->rx_unicast);
1787         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1788                             vsi->offset_loaded, &oes->rx_multicast,
1789                             &nes->rx_multicast);
1790         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1791                             vsi->offset_loaded, &oes->rx_broadcast,
1792                             &nes->rx_broadcast);
1793         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1794                             &oes->rx_discards, &nes->rx_discards);
1795         /* GLV_REPC not supported */
1796         /* GLV_RMPC not supported */
1797         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1798                             &oes->rx_unknown_protocol,
1799                             &nes->rx_unknown_protocol);
1800         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1801                             vsi->offset_loaded, &oes->tx_bytes,
1802                             &nes->tx_bytes);
1803         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1804                             vsi->offset_loaded, &oes->tx_unicast,
1805                             &nes->tx_unicast);
1806         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1807                             vsi->offset_loaded, &oes->tx_multicast,
1808                             &nes->tx_multicast);
1809         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1810                             vsi->offset_loaded,  &oes->tx_broadcast,
1811                             &nes->tx_broadcast);
1812         /* GLV_TDPC not supported */
1813         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1814                             &oes->tx_errors, &nes->tx_errors);
1815         vsi->offset_loaded = true;
1816
1817         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1818                     vsi->vsi_id);
1819         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1820         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1821         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1822         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1823         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1824         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1825                     nes->rx_unknown_protocol);
1826         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1827         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1828         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1829         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1830         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1831         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1832         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1833                     vsi->vsi_id);
1834 }
1835
1836 static void
1837 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1838 {
1839         unsigned int i;
1840         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1841         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1842         /* Get statistics of struct i40e_eth_stats */
1843         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1844                             I40E_GLPRT_GORCL(hw->port),
1845                             pf->offset_loaded, &os->eth.rx_bytes,
1846                             &ns->eth.rx_bytes);
1847         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1848                             I40E_GLPRT_UPRCL(hw->port),
1849                             pf->offset_loaded, &os->eth.rx_unicast,
1850                             &ns->eth.rx_unicast);
1851         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1852                             I40E_GLPRT_MPRCL(hw->port),
1853                             pf->offset_loaded, &os->eth.rx_multicast,
1854                             &ns->eth.rx_multicast);
1855         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1856                             I40E_GLPRT_BPRCL(hw->port),
1857                             pf->offset_loaded, &os->eth.rx_broadcast,
1858                             &ns->eth.rx_broadcast);
1859         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1860                             pf->offset_loaded, &os->eth.rx_discards,
1861                             &ns->eth.rx_discards);
1862         /* GLPRT_REPC not supported */
1863         /* GLPRT_RMPC not supported */
1864         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1865                             pf->offset_loaded,
1866                             &os->eth.rx_unknown_protocol,
1867                             &ns->eth.rx_unknown_protocol);
1868         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1869                             I40E_GLPRT_GOTCL(hw->port),
1870                             pf->offset_loaded, &os->eth.tx_bytes,
1871                             &ns->eth.tx_bytes);
1872         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1873                             I40E_GLPRT_UPTCL(hw->port),
1874                             pf->offset_loaded, &os->eth.tx_unicast,
1875                             &ns->eth.tx_unicast);
1876         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1877                             I40E_GLPRT_MPTCL(hw->port),
1878                             pf->offset_loaded, &os->eth.tx_multicast,
1879                             &ns->eth.tx_multicast);
1880         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1881                             I40E_GLPRT_BPTCL(hw->port),
1882                             pf->offset_loaded, &os->eth.tx_broadcast,
1883                             &ns->eth.tx_broadcast);
1884         /* GLPRT_TEPC not supported */
1885
1886         /* additional port specific stats */
1887         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1888                             pf->offset_loaded, &os->tx_dropped_link_down,
1889                             &ns->tx_dropped_link_down);
1890         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1891                             pf->offset_loaded, &os->crc_errors,
1892                             &ns->crc_errors);
1893         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1894                             pf->offset_loaded, &os->illegal_bytes,
1895                             &ns->illegal_bytes);
1896         /* GLPRT_ERRBC not supported */
1897         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1898                             pf->offset_loaded, &os->mac_local_faults,
1899                             &ns->mac_local_faults);
1900         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1901                             pf->offset_loaded, &os->mac_remote_faults,
1902                             &ns->mac_remote_faults);
1903         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1904                             pf->offset_loaded, &os->rx_length_errors,
1905                             &ns->rx_length_errors);
1906         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1907                             pf->offset_loaded, &os->link_xon_rx,
1908                             &ns->link_xon_rx);
1909         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1910                             pf->offset_loaded, &os->link_xoff_rx,
1911                             &ns->link_xoff_rx);
1912         for (i = 0; i < 8; i++) {
1913                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1914                                     pf->offset_loaded,
1915                                     &os->priority_xon_rx[i],
1916                                     &ns->priority_xon_rx[i]);
1917                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1918                                     pf->offset_loaded,
1919                                     &os->priority_xoff_rx[i],
1920                                     &ns->priority_xoff_rx[i]);
1921         }
1922         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1923                             pf->offset_loaded, &os->link_xon_tx,
1924                             &ns->link_xon_tx);
1925         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1926                             pf->offset_loaded, &os->link_xoff_tx,
1927                             &ns->link_xoff_tx);
1928         for (i = 0; i < 8; i++) {
1929                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1930                                     pf->offset_loaded,
1931                                     &os->priority_xon_tx[i],
1932                                     &ns->priority_xon_tx[i]);
1933                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1934                                     pf->offset_loaded,
1935                                     &os->priority_xoff_tx[i],
1936                                     &ns->priority_xoff_tx[i]);
1937                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1938                                     pf->offset_loaded,
1939                                     &os->priority_xon_2_xoff[i],
1940                                     &ns->priority_xon_2_xoff[i]);
1941         }
1942         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1943                             I40E_GLPRT_PRC64L(hw->port),
1944                             pf->offset_loaded, &os->rx_size_64,
1945                             &ns->rx_size_64);
1946         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1947                             I40E_GLPRT_PRC127L(hw->port),
1948                             pf->offset_loaded, &os->rx_size_127,
1949                             &ns->rx_size_127);
1950         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1951                             I40E_GLPRT_PRC255L(hw->port),
1952                             pf->offset_loaded, &os->rx_size_255,
1953                             &ns->rx_size_255);
1954         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1955                             I40E_GLPRT_PRC511L(hw->port),
1956                             pf->offset_loaded, &os->rx_size_511,
1957                             &ns->rx_size_511);
1958         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1959                             I40E_GLPRT_PRC1023L(hw->port),
1960                             pf->offset_loaded, &os->rx_size_1023,
1961                             &ns->rx_size_1023);
1962         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1963                             I40E_GLPRT_PRC1522L(hw->port),
1964                             pf->offset_loaded, &os->rx_size_1522,
1965                             &ns->rx_size_1522);
1966         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1967                             I40E_GLPRT_PRC9522L(hw->port),
1968                             pf->offset_loaded, &os->rx_size_big,
1969                             &ns->rx_size_big);
1970         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1971                             pf->offset_loaded, &os->rx_undersize,
1972                             &ns->rx_undersize);
1973         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1974                             pf->offset_loaded, &os->rx_fragments,
1975                             &ns->rx_fragments);
1976         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1977                             pf->offset_loaded, &os->rx_oversize,
1978                             &ns->rx_oversize);
1979         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1980                             pf->offset_loaded, &os->rx_jabber,
1981                             &ns->rx_jabber);
1982         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1983                             I40E_GLPRT_PTC64L(hw->port),
1984                             pf->offset_loaded, &os->tx_size_64,
1985                             &ns->tx_size_64);
1986         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1987                             I40E_GLPRT_PTC127L(hw->port),
1988                             pf->offset_loaded, &os->tx_size_127,
1989                             &ns->tx_size_127);
1990         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1991                             I40E_GLPRT_PTC255L(hw->port),
1992                             pf->offset_loaded, &os->tx_size_255,
1993                             &ns->tx_size_255);
1994         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1995                             I40E_GLPRT_PTC511L(hw->port),
1996                             pf->offset_loaded, &os->tx_size_511,
1997                             &ns->tx_size_511);
1998         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1999                             I40E_GLPRT_PTC1023L(hw->port),
2000                             pf->offset_loaded, &os->tx_size_1023,
2001                             &ns->tx_size_1023);
2002         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2003                             I40E_GLPRT_PTC1522L(hw->port),
2004                             pf->offset_loaded, &os->tx_size_1522,
2005                             &ns->tx_size_1522);
2006         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2007                             I40E_GLPRT_PTC9522L(hw->port),
2008                             pf->offset_loaded, &os->tx_size_big,
2009                             &ns->tx_size_big);
2010         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2011                            pf->offset_loaded,
2012                            &os->fd_sb_match, &ns->fd_sb_match);
2013         /* GLPRT_MSPDC not supported */
2014         /* GLPRT_XEC not supported */
2015
2016         pf->offset_loaded = true;
2017
2018         if (pf->main_vsi)
2019                 i40e_update_vsi_stats(pf->main_vsi);
2020 }
2021
2022 /* Get all statistics of a port */
2023 static void
2024 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2025 {
2026         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2027         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2029         unsigned i;
2030
2031         /* call read registers - updates values, now write them to struct */
2032         i40e_read_stats_registers(pf, hw);
2033
2034         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2035                         pf->main_vsi->eth_stats.rx_multicast +
2036                         pf->main_vsi->eth_stats.rx_broadcast -
2037                         pf->main_vsi->eth_stats.rx_discards;
2038         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2039                         pf->main_vsi->eth_stats.tx_multicast +
2040                         pf->main_vsi->eth_stats.tx_broadcast;
2041         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
2042         stats->obytes   = pf->main_vsi->eth_stats.tx_bytes;
2043         stats->oerrors  = ns->eth.tx_errors +
2044                         pf->main_vsi->eth_stats.tx_errors;
2045         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2046         stats->fdirmatch = ns->fd_sb_match;
2047
2048         /* Rx Errors */
2049         stats->ibadcrc  = ns->crc_errors;
2050         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
2051                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2052         stats->imissed  = ns->eth.rx_discards +
2053                         pf->main_vsi->eth_stats.rx_discards;
2054         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
2055
2056         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2057         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2058         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2059         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2060         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2061         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2062         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2063                     ns->eth.rx_unknown_protocol);
2064         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2065         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2066         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2067         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2068         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2069         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2070
2071         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2072                     ns->tx_dropped_link_down);
2073         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2074         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2075                     ns->illegal_bytes);
2076         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2077         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2078                     ns->mac_local_faults);
2079         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2080                     ns->mac_remote_faults);
2081         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2082                     ns->rx_length_errors);
2083         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2084         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2085         for (i = 0; i < 8; i++) {
2086                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2087                                 i, ns->priority_xon_rx[i]);
2088                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2089                                 i, ns->priority_xoff_rx[i]);
2090         }
2091         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2092         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2093         for (i = 0; i < 8; i++) {
2094                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2095                                 i, ns->priority_xon_tx[i]);
2096                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2097                                 i, ns->priority_xoff_tx[i]);
2098                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2099                                 i, ns->priority_xon_2_xoff[i]);
2100         }
2101         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2102         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2103         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2104         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2105         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2106         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2107         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2108         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2109         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2110         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2111         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2112         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2113         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2114         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2115         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2116         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2117         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2118         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2119         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2120                         ns->mac_short_packet_dropped);
2121         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2122                     ns->checksum_error);
2123         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2124         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2125 }
2126
2127 static void
2128 i40e_dev_xstats_reset(struct rte_eth_dev *dev)
2129 {
2130         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2131         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2132         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2133
2134         /* The hw registers are cleared on read */
2135         pf->offset_loaded = false;
2136         i40e_read_stats_registers(pf, hw);
2137
2138         /* reset software counters */
2139         memset(hw_stats, 0, sizeof(*hw_stats));
2140 }
2141
2142 static int
2143 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2144                     unsigned n)
2145 {
2146         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2147         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148         unsigned i, count = 0;
2149         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2150
2151         if (n < I40E_NB_XSTATS)
2152                 return I40E_NB_XSTATS;
2153
2154         i40e_read_stats_registers(pf, hw);
2155
2156         /* Reset */
2157         if (xstats == NULL)
2158                 return 0;
2159
2160         /* Get stats from i40e_eth_stats struct */
2161         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2162                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2163                          "%s", rte_i40e_stats_strings[i].name);
2164                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2165                         rte_i40e_stats_strings[i].offset);
2166                 count++;
2167         }
2168
2169         /* Get individiual stats from i40e_hw_port struct */
2170         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2171                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2172                          "%s", rte_i40e_hw_port_strings[i].name);
2173                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2174                                 rte_i40e_hw_port_strings[i].offset);
2175                 count++;
2176         }
2177
2178         /* Get per-queue stats from i40e_hw_port struct */
2179         for (i = 0; i < 8; i++) {
2180                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2181                          "rx_q%u_xon_priority_packets", i);
2182                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2183                                 offsetof(struct i40e_hw_port_stats,
2184                                          priority_xon_rx[i]));
2185                 count++;
2186
2187                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2188                          "rx_q%u_xoff_priority_packets", i);
2189                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2190                                 offsetof(struct i40e_hw_port_stats,
2191                                          priority_xoff_rx[i]));
2192                 count++;
2193
2194                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2195                          "tx_q%u_xon_priority_packets", i);
2196                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2197                                 offsetof(struct i40e_hw_port_stats,
2198                                          priority_xon_tx[i]));
2199                 count++;
2200
2201                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2202                          "tx_q%u_xoff_priority_packets", i);
2203                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2204                                 offsetof(struct i40e_hw_port_stats,
2205                                          priority_xoff_tx[i]));
2206                 count++;
2207
2208                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2209                          "xx_q%u_xon_to_xoff_priority_packets", i);
2210                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2211                                 offsetof(struct i40e_hw_port_stats,
2212                                          priority_xon_2_xoff[i]));
2213                 count++;
2214         }
2215
2216         return I40E_NB_XSTATS;
2217 }
2218
2219 /* Reset the statistics */
2220 static void
2221 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2222 {
2223         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2224
2225         /* It results in reloading the start point of each counter */
2226         pf->offset_loaded = false;
2227 }
2228
2229 static int
2230 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2231                                  __rte_unused uint16_t queue_id,
2232                                  __rte_unused uint8_t stat_idx,
2233                                  __rte_unused uint8_t is_rx)
2234 {
2235         PMD_INIT_FUNC_TRACE();
2236
2237         return -ENOSYS;
2238 }
2239
2240 static void
2241 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2242 {
2243         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2244         struct i40e_vsi *vsi = pf->main_vsi;
2245
2246         dev_info->max_rx_queues = vsi->nb_qps;
2247         dev_info->max_tx_queues = vsi->nb_qps;
2248         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2249         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2250         dev_info->max_mac_addrs = vsi->max_macaddrs;
2251         dev_info->max_vfs = dev->pci_dev->max_vfs;
2252         dev_info->rx_offload_capa =
2253                 DEV_RX_OFFLOAD_VLAN_STRIP |
2254                 DEV_RX_OFFLOAD_QINQ_STRIP |
2255                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2256                 DEV_RX_OFFLOAD_UDP_CKSUM |
2257                 DEV_RX_OFFLOAD_TCP_CKSUM;
2258         dev_info->tx_offload_capa =
2259                 DEV_TX_OFFLOAD_VLAN_INSERT |
2260                 DEV_TX_OFFLOAD_QINQ_INSERT |
2261                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2262                 DEV_TX_OFFLOAD_UDP_CKSUM |
2263                 DEV_TX_OFFLOAD_TCP_CKSUM |
2264                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2265                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2266                 DEV_TX_OFFLOAD_TCP_TSO;
2267         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2268                                                 sizeof(uint32_t);
2269         dev_info->reta_size = pf->hash_lut_size;
2270         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2271
2272         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2273                 .rx_thresh = {
2274                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2275                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2276                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2277                 },
2278                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2279                 .rx_drop_en = 0,
2280         };
2281
2282         dev_info->default_txconf = (struct rte_eth_txconf) {
2283                 .tx_thresh = {
2284                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2285                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2286                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2287                 },
2288                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2289                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2290                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2291                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2292         };
2293
2294         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2295                 .nb_max = I40E_MAX_RING_DESC,
2296                 .nb_min = I40E_MIN_RING_DESC,
2297                 .nb_align = I40E_ALIGN_RING_DESC,
2298         };
2299
2300         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2301                 .nb_max = I40E_MAX_RING_DESC,
2302                 .nb_min = I40E_MIN_RING_DESC,
2303                 .nb_align = I40E_ALIGN_RING_DESC,
2304         };
2305
2306         if (pf->flags & I40E_FLAG_VMDQ) {
2307                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2308                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2309                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2310                                                 pf->max_nb_vmdq_vsi;
2311                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2312                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2313                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2314         }
2315 }
2316
2317 static int
2318 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2319 {
2320         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2321         struct i40e_vsi *vsi = pf->main_vsi;
2322         PMD_INIT_FUNC_TRACE();
2323
2324         if (on)
2325                 return i40e_vsi_add_vlan(vsi, vlan_id);
2326         else
2327                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2328 }
2329
2330 static void
2331 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2332                    __rte_unused uint16_t tpid)
2333 {
2334         PMD_INIT_FUNC_TRACE();
2335 }
2336
2337 static void
2338 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2339 {
2340         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2341         struct i40e_vsi *vsi = pf->main_vsi;
2342
2343         if (mask & ETH_VLAN_STRIP_MASK) {
2344                 /* Enable or disable VLAN stripping */
2345                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2346                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2347                 else
2348                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2349         }
2350
2351         if (mask & ETH_VLAN_EXTEND_MASK) {
2352                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2353                         i40e_vsi_config_double_vlan(vsi, TRUE);
2354                 else
2355                         i40e_vsi_config_double_vlan(vsi, FALSE);
2356         }
2357 }
2358
2359 static void
2360 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2361                           __rte_unused uint16_t queue,
2362                           __rte_unused int on)
2363 {
2364         PMD_INIT_FUNC_TRACE();
2365 }
2366
2367 static int
2368 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2369 {
2370         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2371         struct i40e_vsi *vsi = pf->main_vsi;
2372         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2373         struct i40e_vsi_vlan_pvid_info info;
2374
2375         memset(&info, 0, sizeof(info));
2376         info.on = on;
2377         if (info.on)
2378                 info.config.pvid = pvid;
2379         else {
2380                 info.config.reject.tagged =
2381                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2382                 info.config.reject.untagged =
2383                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2384         }
2385
2386         return i40e_vsi_vlan_pvid_set(vsi, &info);
2387 }
2388
2389 static int
2390 i40e_dev_led_on(struct rte_eth_dev *dev)
2391 {
2392         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2393         uint32_t mode = i40e_led_get(hw);
2394
2395         if (mode == 0)
2396                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2397
2398         return 0;
2399 }
2400
2401 static int
2402 i40e_dev_led_off(struct rte_eth_dev *dev)
2403 {
2404         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2405         uint32_t mode = i40e_led_get(hw);
2406
2407         if (mode != 0)
2408                 i40e_led_set(hw, 0, false);
2409
2410         return 0;
2411 }
2412
2413 static int
2414 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2415 {
2416         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2417         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2418
2419         fc_conf->pause_time = pf->fc_conf.pause_time;
2420         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2421         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2422
2423          /* Return current mode according to actual setting*/
2424         switch (hw->fc.current_mode) {
2425         case I40E_FC_FULL:
2426                 fc_conf->mode = RTE_FC_FULL;
2427                 break;
2428         case I40E_FC_TX_PAUSE:
2429                 fc_conf->mode = RTE_FC_TX_PAUSE;
2430                 break;
2431         case I40E_FC_RX_PAUSE:
2432                 fc_conf->mode = RTE_FC_RX_PAUSE;
2433                 break;
2434         case I40E_FC_NONE:
2435         default:
2436                 fc_conf->mode = RTE_FC_NONE;
2437         };
2438
2439         return 0;
2440 }
2441
2442 static int
2443 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2444 {
2445         uint32_t mflcn_reg, fctrl_reg, reg;
2446         uint32_t max_high_water;
2447         uint8_t i, aq_failure;
2448         int err;
2449         struct i40e_hw *hw;
2450         struct i40e_pf *pf;
2451         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2452                 [RTE_FC_NONE] = I40E_FC_NONE,
2453                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2454                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2455                 [RTE_FC_FULL] = I40E_FC_FULL
2456         };
2457
2458         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2459
2460         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2461         if ((fc_conf->high_water > max_high_water) ||
2462                         (fc_conf->high_water < fc_conf->low_water)) {
2463                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2464                         "High_water must <= %d.", max_high_water);
2465                 return -EINVAL;
2466         }
2467
2468         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2470         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2471
2472         pf->fc_conf.pause_time = fc_conf->pause_time;
2473         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2474         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2475
2476         PMD_INIT_FUNC_TRACE();
2477
2478         /* All the link flow control related enable/disable register
2479          * configuration is handle by the F/W
2480          */
2481         err = i40e_set_fc(hw, &aq_failure, true);
2482         if (err < 0)
2483                 return -ENOSYS;
2484
2485         if (i40e_is_40G_device(hw->device_id)) {
2486                 /* Configure flow control refresh threshold,
2487                  * the value for stat_tx_pause_refresh_timer[8]
2488                  * is used for global pause operation.
2489                  */
2490
2491                 I40E_WRITE_REG(hw,
2492                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2493                                pf->fc_conf.pause_time);
2494
2495                 /* configure the timer value included in transmitted pause
2496                  * frame,
2497                  * the value for stat_tx_pause_quanta[8] is used for global
2498                  * pause operation
2499                  */
2500                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2501                                pf->fc_conf.pause_time);
2502
2503                 fctrl_reg = I40E_READ_REG(hw,
2504                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2505
2506                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2507                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2508                 else
2509                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2510
2511                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2512                                fctrl_reg);
2513         } else {
2514                 /* Configure pause time (2 TCs per register) */
2515                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2516                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2517                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2518
2519                 /* Configure flow control refresh threshold value */
2520                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2521                                pf->fc_conf.pause_time / 2);
2522
2523                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2524
2525                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2526                  *depending on configuration
2527                  */
2528                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2529                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2530                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2531                 } else {
2532                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2533                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2534                 }
2535
2536                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2537         }
2538
2539         /* config the water marker both based on the packets and bytes */
2540         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2541                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2542                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2543         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2544                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2545                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2546         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2547                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2548                        << I40E_KILOSHIFT);
2549         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2550                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2551                        << I40E_KILOSHIFT);
2552
2553         I40E_WRITE_FLUSH(hw);
2554
2555         return 0;
2556 }
2557
2558 static int
2559 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2560                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2561 {
2562         PMD_INIT_FUNC_TRACE();
2563
2564         return -ENOSYS;
2565 }
2566
2567 /* Add a MAC address, and update filters */
2568 static void
2569 i40e_macaddr_add(struct rte_eth_dev *dev,
2570                  struct ether_addr *mac_addr,
2571                  __rte_unused uint32_t index,
2572                  uint32_t pool)
2573 {
2574         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2575         struct i40e_mac_filter_info mac_filter;
2576         struct i40e_vsi *vsi;
2577         int ret;
2578
2579         /* If VMDQ not enabled or configured, return */
2580         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2581                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2582                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2583                         pool);
2584                 return;
2585         }
2586
2587         if (pool > pf->nb_cfg_vmdq_vsi) {
2588                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2589                                 pool, pf->nb_cfg_vmdq_vsi);
2590                 return;
2591         }
2592
2593         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2594         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2595
2596         if (pool == 0)
2597                 vsi = pf->main_vsi;
2598         else
2599                 vsi = pf->vmdq[pool - 1].vsi;
2600
2601         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2602         if (ret != I40E_SUCCESS) {
2603                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2604                 return;
2605         }
2606 }
2607
2608 /* Remove a MAC address, and update filters */
2609 static void
2610 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2611 {
2612         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2613         struct i40e_vsi *vsi;
2614         struct rte_eth_dev_data *data = dev->data;
2615         struct ether_addr *macaddr;
2616         int ret;
2617         uint32_t i;
2618         uint64_t pool_sel;
2619
2620         macaddr = &(data->mac_addrs[index]);
2621
2622         pool_sel = dev->data->mac_pool_sel[index];
2623
2624         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2625                 if (pool_sel & (1ULL << i)) {
2626                         if (i == 0)
2627                                 vsi = pf->main_vsi;
2628                         else {
2629                                 /* No VMDQ pool enabled or configured */
2630                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2631                                         (i > pf->nb_cfg_vmdq_vsi)) {
2632                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2633                                                         "/configured");
2634                                         return;
2635                                 }
2636                                 vsi = pf->vmdq[i - 1].vsi;
2637                         }
2638                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2639
2640                         if (ret) {
2641                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2642                                 return;
2643                         }
2644                 }
2645         }
2646 }
2647
2648 /* Set perfect match or hash match of MAC and VLAN for a VF */
2649 static int
2650 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2651                  struct rte_eth_mac_filter *filter,
2652                  bool add)
2653 {
2654         struct i40e_hw *hw;
2655         struct i40e_mac_filter_info mac_filter;
2656         struct ether_addr old_mac;
2657         struct ether_addr *new_mac;
2658         struct i40e_pf_vf *vf = NULL;
2659         uint16_t vf_id;
2660         int ret;
2661
2662         if (pf == NULL) {
2663                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2664                 return -EINVAL;
2665         }
2666         hw = I40E_PF_TO_HW(pf);
2667
2668         if (filter == NULL) {
2669                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2670                 return -EINVAL;
2671         }
2672
2673         new_mac = &filter->mac_addr;
2674
2675         if (is_zero_ether_addr(new_mac)) {
2676                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2677                 return -EINVAL;
2678         }
2679
2680         vf_id = filter->dst_id;
2681
2682         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2683                 PMD_DRV_LOG(ERR, "Invalid argument.");
2684                 return -EINVAL;
2685         }
2686         vf = &pf->vfs[vf_id];
2687
2688         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2689                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2690                 return -EINVAL;
2691         }
2692
2693         if (add) {
2694                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2695                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2696                                 ETHER_ADDR_LEN);
2697                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2698                                  ETHER_ADDR_LEN);
2699
2700                 mac_filter.filter_type = filter->filter_type;
2701                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2702                 if (ret != I40E_SUCCESS) {
2703                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2704                         return -1;
2705                 }
2706                 ether_addr_copy(new_mac, &pf->dev_addr);
2707         } else {
2708                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2709                                 ETHER_ADDR_LEN);
2710                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2711                 if (ret != I40E_SUCCESS) {
2712                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2713                         return -1;
2714                 }
2715
2716                 /* Clear device address as it has been removed */
2717                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2718                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2719         }
2720
2721         return 0;
2722 }
2723
2724 /* MAC filter handle */
2725 static int
2726 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2727                 void *arg)
2728 {
2729         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2730         struct rte_eth_mac_filter *filter;
2731         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2732         int ret = I40E_NOT_SUPPORTED;
2733
2734         filter = (struct rte_eth_mac_filter *)(arg);
2735
2736         switch (filter_op) {
2737         case RTE_ETH_FILTER_NOP:
2738                 ret = I40E_SUCCESS;
2739                 break;
2740         case RTE_ETH_FILTER_ADD:
2741                 i40e_pf_disable_irq0(hw);
2742                 if (filter->is_vf)
2743                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2744                 i40e_pf_enable_irq0(hw);
2745                 break;
2746         case RTE_ETH_FILTER_DELETE:
2747                 i40e_pf_disable_irq0(hw);
2748                 if (filter->is_vf)
2749                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2750                 i40e_pf_enable_irq0(hw);
2751                 break;
2752         default:
2753                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2754                 ret = I40E_ERR_PARAM;
2755                 break;
2756         }
2757
2758         return ret;
2759 }
2760
2761 static int
2762 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2763 {
2764         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2765         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2766         int ret;
2767
2768         if (!lut)
2769                 return -EINVAL;
2770
2771         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2772                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2773                                           lut, lut_size);
2774                 if (ret) {
2775                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2776                         return ret;
2777                 }
2778         } else {
2779                 uint32_t *lut_dw = (uint32_t *)lut;
2780                 uint16_t i, lut_size_dw = lut_size / 4;
2781
2782                 for (i = 0; i < lut_size_dw; i++)
2783                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2784         }
2785
2786         return 0;
2787 }
2788
2789 static int
2790 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2791 {
2792         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2793         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2794         int ret;
2795
2796         if (!vsi || !lut)
2797                 return -EINVAL;
2798
2799         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2800                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2801                                           lut, lut_size);
2802                 if (ret) {
2803                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2804                         return ret;
2805                 }
2806         } else {
2807                 uint32_t *lut_dw = (uint32_t *)lut;
2808                 uint16_t i, lut_size_dw = lut_size / 4;
2809
2810                 for (i = 0; i < lut_size_dw; i++)
2811                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2812                 I40E_WRITE_FLUSH(hw);
2813         }
2814
2815         return 0;
2816 }
2817
2818 static int
2819 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2820                          struct rte_eth_rss_reta_entry64 *reta_conf,
2821                          uint16_t reta_size)
2822 {
2823         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2824         uint16_t i, lut_size = pf->hash_lut_size;
2825         uint16_t idx, shift;
2826         uint8_t *lut;
2827         int ret;
2828
2829         if (reta_size != lut_size ||
2830                 reta_size > ETH_RSS_RETA_SIZE_512) {
2831                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2832                         "(%d) doesn't match the number hardware can supported "
2833                                         "(%d)\n", reta_size, lut_size);
2834                 return -EINVAL;
2835         }
2836
2837         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2838         if (!lut) {
2839                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2840                 return -ENOMEM;
2841         }
2842         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2843         if (ret)
2844                 goto out;
2845         for (i = 0; i < reta_size; i++) {
2846                 idx = i / RTE_RETA_GROUP_SIZE;
2847                 shift = i % RTE_RETA_GROUP_SIZE;
2848                 if (reta_conf[idx].mask & (1ULL << shift))
2849                         lut[i] = reta_conf[idx].reta[shift];
2850         }
2851         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2852
2853 out:
2854         rte_free(lut);
2855
2856         return ret;
2857 }
2858
2859 static int
2860 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2861                         struct rte_eth_rss_reta_entry64 *reta_conf,
2862                         uint16_t reta_size)
2863 {
2864         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2865         uint16_t i, lut_size = pf->hash_lut_size;
2866         uint16_t idx, shift;
2867         uint8_t *lut;
2868         int ret;
2869
2870         if (reta_size != lut_size ||
2871                 reta_size > ETH_RSS_RETA_SIZE_512) {
2872                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2873                         "(%d) doesn't match the number hardware can supported "
2874                                         "(%d)\n", reta_size, lut_size);
2875                 return -EINVAL;
2876         }
2877
2878         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2879         if (!lut) {
2880                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2881                 return -ENOMEM;
2882         }
2883
2884         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2885         if (ret)
2886                 goto out;
2887         for (i = 0; i < reta_size; i++) {
2888                 idx = i / RTE_RETA_GROUP_SIZE;
2889                 shift = i % RTE_RETA_GROUP_SIZE;
2890                 if (reta_conf[idx].mask & (1ULL << shift))
2891                         reta_conf[idx].reta[shift] = lut[i];
2892         }
2893
2894 out:
2895         rte_free(lut);
2896
2897         return ret;
2898 }
2899
2900 /**
2901  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2902  * @hw:   pointer to the HW structure
2903  * @mem:  pointer to mem struct to fill out
2904  * @size: size of memory requested
2905  * @alignment: what to align the allocation to
2906  **/
2907 enum i40e_status_code
2908 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2909                         struct i40e_dma_mem *mem,
2910                         u64 size,
2911                         u32 alignment)
2912 {
2913         static uint64_t id = 0;
2914         const struct rte_memzone *mz = NULL;
2915         char z_name[RTE_MEMZONE_NAMESIZE];
2916
2917         if (!mem)
2918                 return I40E_ERR_PARAM;
2919
2920         id++;
2921         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2922 #ifdef RTE_LIBRTE_XEN_DOM0
2923         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2924                                          alignment, RTE_PGSIZE_2M);
2925 #else
2926         mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2927                                          alignment);
2928 #endif
2929         if (!mz)
2930                 return I40E_ERR_NO_MEMORY;
2931
2932         mem->id = id;
2933         mem->size = size;
2934         mem->va = mz->addr;
2935 #ifdef RTE_LIBRTE_XEN_DOM0
2936         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2937 #else
2938         mem->pa = mz->phys_addr;
2939 #endif
2940
2941         return I40E_SUCCESS;
2942 }
2943
2944 /**
2945  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2946  * @hw:   pointer to the HW structure
2947  * @mem:  ptr to mem struct to free
2948  **/
2949 enum i40e_status_code
2950 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2951                     struct i40e_dma_mem *mem)
2952 {
2953         if (!mem || !mem->va)
2954                 return I40E_ERR_PARAM;
2955
2956         mem->va = NULL;
2957         mem->pa = (u64)0;
2958
2959         return I40E_SUCCESS;
2960 }
2961
2962 /**
2963  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2964  * @hw:   pointer to the HW structure
2965  * @mem:  pointer to mem struct to fill out
2966  * @size: size of memory requested
2967  **/
2968 enum i40e_status_code
2969 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2970                          struct i40e_virt_mem *mem,
2971                          u32 size)
2972 {
2973         if (!mem)
2974                 return I40E_ERR_PARAM;
2975
2976         mem->size = size;
2977         mem->va = rte_zmalloc("i40e", size, 0);
2978
2979         if (mem->va)
2980                 return I40E_SUCCESS;
2981         else
2982                 return I40E_ERR_NO_MEMORY;
2983 }
2984
2985 /**
2986  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2987  * @hw:   pointer to the HW structure
2988  * @mem:  pointer to mem struct to free
2989  **/
2990 enum i40e_status_code
2991 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2992                      struct i40e_virt_mem *mem)
2993 {
2994         if (!mem)
2995                 return I40E_ERR_PARAM;
2996
2997         rte_free(mem->va);
2998         mem->va = NULL;
2999
3000         return I40E_SUCCESS;
3001 }
3002
3003 void
3004 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3005 {
3006         rte_spinlock_init(&sp->spinlock);
3007 }
3008
3009 void
3010 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3011 {
3012         rte_spinlock_lock(&sp->spinlock);
3013 }
3014
3015 void
3016 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3017 {
3018         rte_spinlock_unlock(&sp->spinlock);
3019 }
3020
3021 void
3022 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3023 {
3024         return;
3025 }
3026
3027 /**
3028  * Get the hardware capabilities, which will be parsed
3029  * and saved into struct i40e_hw.
3030  */
3031 static int
3032 i40e_get_cap(struct i40e_hw *hw)
3033 {
3034         struct i40e_aqc_list_capabilities_element_resp *buf;
3035         uint16_t len, size = 0;
3036         int ret;
3037
3038         /* Calculate a huge enough buff for saving response data temporarily */
3039         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3040                                                 I40E_MAX_CAP_ELE_NUM;
3041         buf = rte_zmalloc("i40e", len, 0);
3042         if (!buf) {
3043                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3044                 return I40E_ERR_NO_MEMORY;
3045         }
3046
3047         /* Get, parse the capabilities and save it to hw */
3048         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3049                         i40e_aqc_opc_list_func_capabilities, NULL);
3050         if (ret != I40E_SUCCESS)
3051                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3052
3053         /* Free the temporary buffer after being used */
3054         rte_free(buf);
3055
3056         return ret;
3057 }
3058
3059 static int
3060 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3061 {
3062         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3063         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3064         uint16_t qp_count = 0, vsi_count = 0;
3065
3066         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3067                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3068                 return -EINVAL;
3069         }
3070         /* Add the parameter init for LFC */
3071         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3072         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3073         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3074
3075         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3076         pf->max_num_vsi = hw->func_caps.num_vsis;
3077         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3078         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3079         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3080
3081         /* FDir queue/VSI allocation */
3082         pf->fdir_qp_offset = 0;
3083         if (hw->func_caps.fd) {
3084                 pf->flags |= I40E_FLAG_FDIR;
3085                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3086         } else {
3087                 pf->fdir_nb_qps = 0;
3088         }
3089         qp_count += pf->fdir_nb_qps;
3090         vsi_count += 1;
3091
3092         /* LAN queue/VSI allocation */
3093         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3094         if (!hw->func_caps.rss) {
3095                 pf->lan_nb_qps = 1;
3096         } else {
3097                 pf->flags |= I40E_FLAG_RSS;
3098                 if (hw->mac.type == I40E_MAC_X722)
3099                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3100                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3101         }
3102         qp_count += pf->lan_nb_qps;
3103         vsi_count += 1;
3104
3105         /* VF queue/VSI allocation */
3106         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3107         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3108                 pf->flags |= I40E_FLAG_SRIOV;
3109                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3110                 pf->vf_num = dev->pci_dev->max_vfs;
3111                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3112                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3113                             pf->vf_nb_qps * pf->vf_num);
3114         } else {
3115                 pf->vf_nb_qps = 0;
3116                 pf->vf_num = 0;
3117         }
3118         qp_count += pf->vf_nb_qps * pf->vf_num;
3119         vsi_count += pf->vf_num;
3120
3121         /* VMDq queue/VSI allocation */
3122         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3123         if (hw->func_caps.vmdq) {
3124                 pf->flags |= I40E_FLAG_VMDQ;
3125                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3126                 pf->max_nb_vmdq_vsi = 1;
3127                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues per VMDQ VSI, "
3128                             "in total %u queues", pf->max_nb_vmdq_vsi,
3129                             pf->vmdq_nb_qps,
3130                             pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3131         } else {
3132                 pf->vmdq_nb_qps = 0;
3133                 pf->max_nb_vmdq_vsi = 0;
3134         }
3135         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3136         vsi_count += pf->max_nb_vmdq_vsi;
3137
3138         if (hw->func_caps.dcb)
3139                 pf->flags |= I40E_FLAG_DCB;
3140
3141         if (qp_count > hw->func_caps.num_tx_qp) {
3142                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3143                             "the hardware maximum %u", qp_count,
3144                             hw->func_caps.num_tx_qp);
3145                 return -EINVAL;
3146         }
3147         if (vsi_count > hw->func_caps.num_vsis) {
3148                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3149                             "the hardware maximum %u", vsi_count,
3150                             hw->func_caps.num_vsis);
3151                 return -EINVAL;
3152         }
3153
3154         return 0;
3155 }
3156
3157 static int
3158 i40e_pf_get_switch_config(struct i40e_pf *pf)
3159 {
3160         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3161         struct i40e_aqc_get_switch_config_resp *switch_config;
3162         struct i40e_aqc_switch_config_element_resp *element;
3163         uint16_t start_seid = 0, num_reported;
3164         int ret;
3165
3166         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3167                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3168         if (!switch_config) {
3169                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3170                 return -ENOMEM;
3171         }
3172
3173         /* Get the switch configurations */
3174         ret = i40e_aq_get_switch_config(hw, switch_config,
3175                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3176         if (ret != I40E_SUCCESS) {
3177                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3178                 goto fail;
3179         }
3180         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3181         if (num_reported != 1) { /* The number should be 1 */
3182                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3183                 goto fail;
3184         }
3185
3186         /* Parse the switch configuration elements */
3187         element = &(switch_config->element[0]);
3188         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3189                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3190                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3191         } else
3192                 PMD_DRV_LOG(INFO, "Unknown element type");
3193
3194 fail:
3195         rte_free(switch_config);
3196
3197         return ret;
3198 }
3199
3200 static int
3201 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3202                         uint32_t num)
3203 {
3204         struct pool_entry *entry;
3205
3206         if (pool == NULL || num == 0)
3207                 return -EINVAL;
3208
3209         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3210         if (entry == NULL) {
3211                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3212                 return -ENOMEM;
3213         }
3214
3215         /* queue heap initialize */
3216         pool->num_free = num;
3217         pool->num_alloc = 0;
3218         pool->base = base;
3219         LIST_INIT(&pool->alloc_list);
3220         LIST_INIT(&pool->free_list);
3221
3222         /* Initialize element  */
3223         entry->base = 0;
3224         entry->len = num;
3225
3226         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3227         return 0;
3228 }
3229
3230 static void
3231 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3232 {
3233         struct pool_entry *entry;
3234
3235         if (pool == NULL)
3236                 return;
3237
3238         LIST_FOREACH(entry, &pool->alloc_list, next) {
3239                 LIST_REMOVE(entry, next);
3240                 rte_free(entry);
3241         }
3242
3243         LIST_FOREACH(entry, &pool->free_list, next) {
3244                 LIST_REMOVE(entry, next);
3245                 rte_free(entry);
3246         }
3247
3248         pool->num_free = 0;
3249         pool->num_alloc = 0;
3250         pool->base = 0;
3251         LIST_INIT(&pool->alloc_list);
3252         LIST_INIT(&pool->free_list);
3253 }
3254
3255 static int
3256 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3257                        uint32_t base)
3258 {
3259         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3260         uint32_t pool_offset;
3261         int insert;
3262
3263         if (pool == NULL) {
3264                 PMD_DRV_LOG(ERR, "Invalid parameter");
3265                 return -EINVAL;
3266         }
3267
3268         pool_offset = base - pool->base;
3269         /* Lookup in alloc list */
3270         LIST_FOREACH(entry, &pool->alloc_list, next) {
3271                 if (entry->base == pool_offset) {
3272                         valid_entry = entry;
3273                         LIST_REMOVE(entry, next);
3274                         break;
3275                 }
3276         }
3277
3278         /* Not find, return */
3279         if (valid_entry == NULL) {
3280                 PMD_DRV_LOG(ERR, "Failed to find entry");
3281                 return -EINVAL;
3282         }
3283
3284         /**
3285          * Found it, move it to free list  and try to merge.
3286          * In order to make merge easier, always sort it by qbase.
3287          * Find adjacent prev and last entries.
3288          */
3289         prev = next = NULL;
3290         LIST_FOREACH(entry, &pool->free_list, next) {
3291                 if (entry->base > valid_entry->base) {
3292                         next = entry;
3293                         break;
3294                 }
3295                 prev = entry;
3296         }
3297
3298         insert = 0;
3299         /* Try to merge with next one*/
3300         if (next != NULL) {
3301                 /* Merge with next one */
3302                 if (valid_entry->base + valid_entry->len == next->base) {
3303                         next->base = valid_entry->base;
3304                         next->len += valid_entry->len;
3305                         rte_free(valid_entry);
3306                         valid_entry = next;
3307                         insert = 1;
3308                 }
3309         }
3310
3311         if (prev != NULL) {
3312                 /* Merge with previous one */
3313                 if (prev->base + prev->len == valid_entry->base) {
3314                         prev->len += valid_entry->len;
3315                         /* If it merge with next one, remove next node */
3316                         if (insert == 1) {
3317                                 LIST_REMOVE(valid_entry, next);
3318                                 rte_free(valid_entry);
3319                         } else {
3320                                 rte_free(valid_entry);
3321                                 insert = 1;
3322                         }
3323                 }
3324         }
3325
3326         /* Not find any entry to merge, insert */
3327         if (insert == 0) {
3328                 if (prev != NULL)
3329                         LIST_INSERT_AFTER(prev, valid_entry, next);
3330                 else if (next != NULL)
3331                         LIST_INSERT_BEFORE(next, valid_entry, next);
3332                 else /* It's empty list, insert to head */
3333                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3334         }
3335
3336         pool->num_free += valid_entry->len;
3337         pool->num_alloc -= valid_entry->len;
3338
3339         return 0;
3340 }
3341
3342 static int
3343 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3344                        uint16_t num)
3345 {
3346         struct pool_entry *entry, *valid_entry;
3347
3348         if (pool == NULL || num == 0) {
3349                 PMD_DRV_LOG(ERR, "Invalid parameter");
3350                 return -EINVAL;
3351         }
3352
3353         if (pool->num_free < num) {
3354                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3355                             num, pool->num_free);
3356                 return -ENOMEM;
3357         }
3358
3359         valid_entry = NULL;
3360         /* Lookup  in free list and find most fit one */
3361         LIST_FOREACH(entry, &pool->free_list, next) {
3362                 if (entry->len >= num) {
3363                         /* Find best one */
3364                         if (entry->len == num) {
3365                                 valid_entry = entry;
3366                                 break;
3367                         }
3368                         if (valid_entry == NULL || valid_entry->len > entry->len)
3369                                 valid_entry = entry;
3370                 }
3371         }
3372
3373         /* Not find one to satisfy the request, return */
3374         if (valid_entry == NULL) {
3375                 PMD_DRV_LOG(ERR, "No valid entry found");
3376                 return -ENOMEM;
3377         }
3378         /**
3379          * The entry have equal queue number as requested,
3380          * remove it from alloc_list.
3381          */
3382         if (valid_entry->len == num) {
3383                 LIST_REMOVE(valid_entry, next);
3384         } else {
3385                 /**
3386                  * The entry have more numbers than requested,
3387                  * create a new entry for alloc_list and minus its
3388                  * queue base and number in free_list.
3389                  */
3390                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3391                 if (entry == NULL) {
3392                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3393                                     "resource pool");
3394                         return -ENOMEM;
3395                 }
3396                 entry->base = valid_entry->base;
3397                 entry->len = num;
3398                 valid_entry->base += num;
3399                 valid_entry->len -= num;
3400                 valid_entry = entry;
3401         }
3402
3403         /* Insert it into alloc list, not sorted */
3404         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3405
3406         pool->num_free -= valid_entry->len;
3407         pool->num_alloc += valid_entry->len;
3408
3409         return (valid_entry->base + pool->base);
3410 }
3411
3412 /**
3413  * bitmap_is_subset - Check whether src2 is subset of src1
3414  **/
3415 static inline int
3416 bitmap_is_subset(uint8_t src1, uint8_t src2)
3417 {
3418         return !((src1 ^ src2) & src2);
3419 }
3420
3421 static enum i40e_status_code
3422 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3423 {
3424         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3425
3426         /* If DCB is not supported, only default TC is supported */
3427         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3428                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3429                 return I40E_NOT_SUPPORTED;
3430         }
3431
3432         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3433                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3434                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3435                             enabled_tcmap);
3436                 return I40E_NOT_SUPPORTED;
3437         }
3438         return I40E_SUCCESS;
3439 }
3440
3441 int
3442 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3443                                 struct i40e_vsi_vlan_pvid_info *info)
3444 {
3445         struct i40e_hw *hw;
3446         struct i40e_vsi_context ctxt;
3447         uint8_t vlan_flags = 0;
3448         int ret;
3449
3450         if (vsi == NULL || info == NULL) {
3451                 PMD_DRV_LOG(ERR, "invalid parameters");
3452                 return I40E_ERR_PARAM;
3453         }
3454
3455         if (info->on) {
3456                 vsi->info.pvid = info->config.pvid;
3457                 /**
3458                  * If insert pvid is enabled, only tagged pkts are
3459                  * allowed to be sent out.
3460                  */
3461                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3462                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3463         } else {
3464                 vsi->info.pvid = 0;
3465                 if (info->config.reject.tagged == 0)
3466                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3467
3468                 if (info->config.reject.untagged == 0)
3469                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3470         }
3471         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3472                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3473         vsi->info.port_vlan_flags |= vlan_flags;
3474         vsi->info.valid_sections =
3475                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3476         memset(&ctxt, 0, sizeof(ctxt));
3477         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3478         ctxt.seid = vsi->seid;
3479
3480         hw = I40E_VSI_TO_HW(vsi);
3481         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3482         if (ret != I40E_SUCCESS)
3483                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3484
3485         return ret;
3486 }
3487
3488 static int
3489 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3490 {
3491         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3492         int i, ret;
3493         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3494
3495         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3496         if (ret != I40E_SUCCESS)
3497                 return ret;
3498
3499         if (!vsi->seid) {
3500                 PMD_DRV_LOG(ERR, "seid not valid");
3501                 return -EINVAL;
3502         }
3503
3504         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3505         tc_bw_data.tc_valid_bits = enabled_tcmap;
3506         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3507                 tc_bw_data.tc_bw_credits[i] =
3508                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3509
3510         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3511         if (ret != I40E_SUCCESS) {
3512                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3513                 return ret;
3514         }
3515
3516         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3517                                         sizeof(vsi->info.qs_handle));
3518         return I40E_SUCCESS;
3519 }
3520
3521 static enum i40e_status_code
3522 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3523                                  struct i40e_aqc_vsi_properties_data *info,
3524                                  uint8_t enabled_tcmap)
3525 {
3526         enum i40e_status_code ret;
3527         int i, total_tc = 0;
3528         uint16_t qpnum_per_tc, bsf, qp_idx;
3529
3530         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3531         if (ret != I40E_SUCCESS)
3532                 return ret;
3533
3534         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3535                 if (enabled_tcmap & (1 << i))
3536                         total_tc++;
3537         vsi->enabled_tc = enabled_tcmap;
3538
3539         /* Number of queues per enabled TC */
3540         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3541         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3542         bsf = rte_bsf32(qpnum_per_tc);
3543
3544         /* Adjust the queue number to actual queues that can be applied */
3545         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3546                 vsi->nb_qps = qpnum_per_tc * total_tc;
3547
3548         /**
3549          * Configure TC and queue mapping parameters, for enabled TC,
3550          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3551          * default queue will serve it.
3552          */
3553         qp_idx = 0;
3554         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3555                 if (vsi->enabled_tc & (1 << i)) {
3556                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3557                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3558                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3559                         qp_idx += qpnum_per_tc;
3560                 } else
3561                         info->tc_mapping[i] = 0;
3562         }
3563
3564         /* Associate queue number with VSI */
3565         if (vsi->type == I40E_VSI_SRIOV) {
3566                 info->mapping_flags |=
3567                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3568                 for (i = 0; i < vsi->nb_qps; i++)
3569                         info->queue_mapping[i] =
3570                                 rte_cpu_to_le_16(vsi->base_queue + i);
3571         } else {
3572                 info->mapping_flags |=
3573                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3574                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3575         }
3576         info->valid_sections |=
3577                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3578
3579         return I40E_SUCCESS;
3580 }
3581
3582 static int
3583 i40e_veb_release(struct i40e_veb *veb)
3584 {
3585         struct i40e_vsi *vsi;
3586         struct i40e_hw *hw;
3587
3588         if (veb == NULL || veb->associate_vsi == NULL)
3589                 return -EINVAL;
3590
3591         if (!TAILQ_EMPTY(&veb->head)) {
3592                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3593                 return -EACCES;
3594         }
3595
3596         vsi = veb->associate_vsi;
3597         hw = I40E_VSI_TO_HW(vsi);
3598
3599         vsi->uplink_seid = veb->uplink_seid;
3600         i40e_aq_delete_element(hw, veb->seid, NULL);
3601         rte_free(veb);
3602         vsi->veb = NULL;
3603         return I40E_SUCCESS;
3604 }
3605
3606 /* Setup a veb */
3607 static struct i40e_veb *
3608 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3609 {
3610         struct i40e_veb *veb;
3611         int ret;
3612         struct i40e_hw *hw;
3613
3614         if (NULL == pf || vsi == NULL) {
3615                 PMD_DRV_LOG(ERR, "veb setup failed, "
3616                             "associated VSI shouldn't null");
3617                 return NULL;
3618         }
3619         hw = I40E_PF_TO_HW(pf);
3620
3621         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3622         if (!veb) {
3623                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3624                 goto fail;
3625         }
3626
3627         veb->associate_vsi = vsi;
3628         TAILQ_INIT(&veb->head);
3629         veb->uplink_seid = vsi->uplink_seid;
3630
3631         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3632                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3633
3634         if (ret != I40E_SUCCESS) {
3635                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3636                             hw->aq.asq_last_status);
3637                 goto fail;
3638         }
3639
3640         /* get statistics index */
3641         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3642                                 &veb->stats_idx, NULL, NULL, NULL);
3643         if (ret != I40E_SUCCESS) {
3644                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3645                             hw->aq.asq_last_status);
3646                 goto fail;
3647         }
3648
3649         /* Get VEB bandwidth, to be implemented */
3650         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3651         vsi->uplink_seid = veb->seid;
3652
3653         return veb;
3654 fail:
3655         rte_free(veb);
3656         return NULL;
3657 }
3658
3659 int
3660 i40e_vsi_release(struct i40e_vsi *vsi)
3661 {
3662         struct i40e_pf *pf;
3663         struct i40e_hw *hw;
3664         struct i40e_vsi_list *vsi_list;
3665         int ret;
3666         struct i40e_mac_filter *f;
3667
3668         if (!vsi)
3669                 return I40E_SUCCESS;
3670
3671         pf = I40E_VSI_TO_PF(vsi);
3672         hw = I40E_VSI_TO_HW(vsi);
3673
3674         /* VSI has child to attach, release child first */
3675         if (vsi->veb) {
3676                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3677                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3678                                 return -1;
3679                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3680                 }
3681                 i40e_veb_release(vsi->veb);
3682         }
3683
3684         /* Remove all macvlan filters of the VSI */
3685         i40e_vsi_remove_all_macvlan_filter(vsi);
3686         TAILQ_FOREACH(f, &vsi->mac_list, next)
3687                 rte_free(f);
3688
3689         if (vsi->type != I40E_VSI_MAIN) {
3690                 /* Remove vsi from parent's sibling list */
3691                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3692                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3693                         return I40E_ERR_PARAM;
3694                 }
3695                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3696                                 &vsi->sib_vsi_list, list);
3697
3698                 /* Remove all switch element of the VSI */
3699                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3700                 if (ret != I40E_SUCCESS)
3701                         PMD_DRV_LOG(ERR, "Failed to delete element");
3702         }
3703         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3704
3705         if (vsi->type != I40E_VSI_SRIOV)
3706                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3707         rte_free(vsi);
3708
3709         return I40E_SUCCESS;
3710 }
3711
3712 static int
3713 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3714 {
3715         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3716         struct i40e_aqc_remove_macvlan_element_data def_filter;
3717         struct i40e_mac_filter_info filter;
3718         int ret;
3719
3720         if (vsi->type != I40E_VSI_MAIN)
3721                 return I40E_ERR_CONFIG;
3722         memset(&def_filter, 0, sizeof(def_filter));
3723         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3724                                         ETH_ADDR_LEN);
3725         def_filter.vlan_tag = 0;
3726         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3727                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3728         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3729         if (ret != I40E_SUCCESS) {
3730                 struct i40e_mac_filter *f;
3731                 struct ether_addr *mac;
3732
3733                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3734                             "macvlan filter");
3735                 /* It needs to add the permanent mac into mac list */
3736                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3737                 if (f == NULL) {
3738                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3739                         return I40E_ERR_NO_MEMORY;
3740                 }
3741                 mac = &f->mac_info.mac_addr;
3742                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3743                                 ETH_ADDR_LEN);
3744                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3745                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3746                 vsi->mac_num++;
3747
3748                 return ret;
3749         }
3750         (void)rte_memcpy(&filter.mac_addr,
3751                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3752         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3753         return i40e_vsi_add_mac(vsi, &filter);
3754 }
3755
3756 static int
3757 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3758 {
3759         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3760         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3761         struct i40e_hw *hw = &vsi->adapter->hw;
3762         i40e_status ret;
3763         int i;
3764
3765         memset(&bw_config, 0, sizeof(bw_config));
3766         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3767         if (ret != I40E_SUCCESS) {
3768                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3769                             hw->aq.asq_last_status);
3770                 return ret;
3771         }
3772
3773         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3774         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3775                                         &ets_sla_config, NULL);
3776         if (ret != I40E_SUCCESS) {
3777                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3778                             "configuration %u", hw->aq.asq_last_status);
3779                 return ret;
3780         }
3781
3782         /* Not store the info yet, just print out */
3783         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3784         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3785         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3786                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3787                             ets_sla_config.share_credits[i]);
3788                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3789                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3790                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3791                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3792                             (i * 4));
3793         }
3794
3795         return 0;
3796 }
3797
3798 /* Setup a VSI */
3799 struct i40e_vsi *
3800 i40e_vsi_setup(struct i40e_pf *pf,
3801                enum i40e_vsi_type type,
3802                struct i40e_vsi *uplink_vsi,
3803                uint16_t user_param)
3804 {
3805         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3806         struct i40e_vsi *vsi;
3807         struct i40e_mac_filter_info filter;
3808         int ret;
3809         struct i40e_vsi_context ctxt;
3810         struct ether_addr broadcast =
3811                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3812
3813         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3814                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3815                             "VSI link shouldn't be NULL");
3816                 return NULL;
3817         }
3818
3819         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3820                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3821                             "uplink VSI should be NULL");
3822                 return NULL;
3823         }
3824
3825         /* If uplink vsi didn't setup VEB, create one first */
3826         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3827                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3828
3829                 if (NULL == uplink_vsi->veb) {
3830                         PMD_DRV_LOG(ERR, "VEB setup failed");
3831                         return NULL;
3832                 }
3833         }
3834
3835         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3836         if (!vsi) {
3837                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3838                 return NULL;
3839         }
3840         TAILQ_INIT(&vsi->mac_list);
3841         vsi->type = type;
3842         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3843         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3844         vsi->parent_vsi = uplink_vsi;
3845         vsi->user_param = user_param;
3846         /* Allocate queues */
3847         switch (vsi->type) {
3848         case I40E_VSI_MAIN  :
3849                 vsi->nb_qps = pf->lan_nb_qps;
3850                 break;
3851         case I40E_VSI_SRIOV :
3852                 vsi->nb_qps = pf->vf_nb_qps;
3853                 break;
3854         case I40E_VSI_VMDQ2:
3855                 vsi->nb_qps = pf->vmdq_nb_qps;
3856                 break;
3857         case I40E_VSI_FDIR:
3858                 vsi->nb_qps = pf->fdir_nb_qps;
3859                 break;
3860         default:
3861                 goto fail_mem;
3862         }
3863         /*
3864          * The filter status descriptor is reported in rx queue 0,
3865          * while the tx queue for fdir filter programming has no
3866          * such constraints, can be non-zero queues.
3867          * To simplify it, choose FDIR vsi use queue 0 pair.
3868          * To make sure it will use queue 0 pair, queue allocation
3869          * need be done before this function is called
3870          */
3871         if (type != I40E_VSI_FDIR) {
3872                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3873                         if (ret < 0) {
3874                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3875                                                 vsi->seid, ret);
3876                                 goto fail_mem;
3877                         }
3878                         vsi->base_queue = ret;
3879         } else
3880                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3881
3882         /* VF has MSIX interrupt in VF range, don't allocate here */
3883         if (type == I40E_VSI_MAIN) {
3884                 ret = i40e_res_pool_alloc(&pf->msix_pool,
3885                                           RTE_MIN(vsi->nb_qps,
3886                                                   RTE_MAX_RXTX_INTR_VEC_ID));
3887                 if (ret < 0) {
3888                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
3889                                     vsi->seid, ret);
3890                         goto fail_queue_alloc;
3891                 }
3892                 vsi->msix_intr = ret;
3893                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
3894         } else if (type != I40E_VSI_SRIOV) {
3895                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3896                 if (ret < 0) {
3897                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3898                         goto fail_queue_alloc;
3899                 }
3900                 vsi->msix_intr = ret;
3901                 vsi->nb_msix = 1;
3902         } else {
3903                 vsi->msix_intr = 0;
3904                 vsi->nb_msix = 0;
3905         }
3906
3907         /* Add VSI */
3908         if (type == I40E_VSI_MAIN) {
3909                 /* For main VSI, no need to add since it's default one */
3910                 vsi->uplink_seid = pf->mac_seid;
3911                 vsi->seid = pf->main_vsi_seid;
3912                 /* Bind queues with specific MSIX interrupt */
3913                 /**
3914                  * Needs 2 interrupt at least, one for misc cause which will
3915                  * enabled from OS side, Another for queues binding the
3916                  * interrupt from device side only.
3917                  */
3918
3919                 /* Get default VSI parameters from hardware */
3920                 memset(&ctxt, 0, sizeof(ctxt));
3921                 ctxt.seid = vsi->seid;
3922                 ctxt.pf_num = hw->pf_id;
3923                 ctxt.uplink_seid = vsi->uplink_seid;
3924                 ctxt.vf_num = 0;
3925                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3926                 if (ret != I40E_SUCCESS) {
3927                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3928                         goto fail_msix_alloc;
3929                 }
3930                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3931                         sizeof(struct i40e_aqc_vsi_properties_data));
3932                 vsi->vsi_id = ctxt.vsi_number;
3933                 vsi->info.valid_sections = 0;
3934
3935                 /* Configure tc, enabled TC0 only */
3936                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3937                         I40E_SUCCESS) {
3938                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3939                         goto fail_msix_alloc;
3940                 }
3941
3942                 /* TC, queue mapping */
3943                 memset(&ctxt, 0, sizeof(ctxt));
3944                 vsi->info.valid_sections |=
3945                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3946                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3947                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3948                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3949                         sizeof(struct i40e_aqc_vsi_properties_data));
3950                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3951                                                 I40E_DEFAULT_TCMAP);
3952                 if (ret != I40E_SUCCESS) {
3953                         PMD_DRV_LOG(ERR, "Failed to configure "
3954                                     "TC queue mapping");
3955                         goto fail_msix_alloc;
3956                 }
3957                 ctxt.seid = vsi->seid;
3958                 ctxt.pf_num = hw->pf_id;
3959                 ctxt.uplink_seid = vsi->uplink_seid;
3960                 ctxt.vf_num = 0;
3961
3962                 /* Update VSI parameters */
3963                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3964                 if (ret != I40E_SUCCESS) {
3965                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3966                         goto fail_msix_alloc;
3967                 }
3968
3969                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3970                                                 sizeof(vsi->info.tc_mapping));
3971                 (void)rte_memcpy(&vsi->info.queue_mapping,
3972                                 &ctxt.info.queue_mapping,
3973                         sizeof(vsi->info.queue_mapping));
3974                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3975                 vsi->info.valid_sections = 0;
3976
3977                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3978                                 ETH_ADDR_LEN);
3979
3980                 /**
3981                  * Updating default filter settings are necessary to prevent
3982                  * reception of tagged packets.
3983                  * Some old firmware configurations load a default macvlan
3984                  * filter which accepts both tagged and untagged packets.
3985                  * The updating is to use a normal filter instead if needed.
3986                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3987                  * The firmware with correct configurations load the default
3988                  * macvlan filter which is expected and cannot be removed.
3989                  */
3990                 i40e_update_default_filter_setting(vsi);
3991                 i40e_config_qinq(hw, vsi);
3992         } else if (type == I40E_VSI_SRIOV) {
3993                 memset(&ctxt, 0, sizeof(ctxt));
3994                 /**
3995                  * For other VSI, the uplink_seid equals to uplink VSI's
3996                  * uplink_seid since they share same VEB
3997                  */
3998                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3999                 ctxt.pf_num = hw->pf_id;
4000                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4001                 ctxt.uplink_seid = vsi->uplink_seid;
4002                 ctxt.connection_type = 0x1;
4003                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4004
4005                 /**
4006                  * Do not configure switch ID to enable VEB switch by
4007                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
4008                  * if the source mac address of packet sent from VF is not
4009                  * listed in the VEB's mac table, the VEB will switch the
4010                  * packet back to the VF. Need to enable it when HW issue
4011                  * is fixed.
4012                  */
4013
4014                 /* Configure port/vlan */
4015                 ctxt.info.valid_sections |=
4016                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4017                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4018                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4019                                                 I40E_DEFAULT_TCMAP);
4020                 if (ret != I40E_SUCCESS) {
4021                         PMD_DRV_LOG(ERR, "Failed to configure "
4022                                     "TC queue mapping");
4023                         goto fail_msix_alloc;
4024                 }
4025                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4026                 ctxt.info.valid_sections |=
4027                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4028                 /**
4029                  * Since VSI is not created yet, only configure parameter,
4030                  * will add vsi below.
4031                  */
4032
4033                 i40e_config_qinq(hw, vsi);
4034         } else if (type == I40E_VSI_VMDQ2) {
4035                 memset(&ctxt, 0, sizeof(ctxt));
4036                 /*
4037                  * For other VSI, the uplink_seid equals to uplink VSI's
4038                  * uplink_seid since they share same VEB
4039                  */
4040                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4041                 ctxt.pf_num = hw->pf_id;
4042                 ctxt.vf_num = 0;
4043                 ctxt.uplink_seid = vsi->uplink_seid;
4044                 ctxt.connection_type = 0x1;
4045                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4046
4047                 ctxt.info.valid_sections |=
4048                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4049                 /* user_param carries flag to enable loop back */
4050                 if (user_param) {
4051                         ctxt.info.switch_id =
4052                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4053                         ctxt.info.switch_id |=
4054                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4055                 }
4056
4057                 /* Configure port/vlan */
4058                 ctxt.info.valid_sections |=
4059                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4060                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4061                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4062                                                 I40E_DEFAULT_TCMAP);
4063                 if (ret != I40E_SUCCESS) {
4064                         PMD_DRV_LOG(ERR, "Failed to configure "
4065                                         "TC queue mapping");
4066                         goto fail_msix_alloc;
4067                 }
4068                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4069                 ctxt.info.valid_sections |=
4070                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4071         } else if (type == I40E_VSI_FDIR) {
4072                 memset(&ctxt, 0, sizeof(ctxt));
4073                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4074                 ctxt.pf_num = hw->pf_id;
4075                 ctxt.vf_num = 0;
4076                 ctxt.uplink_seid = vsi->uplink_seid;
4077                 ctxt.connection_type = 0x1;     /* regular data port */
4078                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4079                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4080                                                 I40E_DEFAULT_TCMAP);
4081                 if (ret != I40E_SUCCESS) {
4082                         PMD_DRV_LOG(ERR, "Failed to configure "
4083                                         "TC queue mapping.");
4084                         goto fail_msix_alloc;
4085                 }
4086                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4087                 ctxt.info.valid_sections |=
4088                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4089         } else {
4090                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4091                 goto fail_msix_alloc;
4092         }
4093
4094         if (vsi->type != I40E_VSI_MAIN) {
4095                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4096                 if (ret != I40E_SUCCESS) {
4097                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4098                                     hw->aq.asq_last_status);
4099                         goto fail_msix_alloc;
4100                 }
4101                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4102                 vsi->info.valid_sections = 0;
4103                 vsi->seid = ctxt.seid;
4104                 vsi->vsi_id = ctxt.vsi_number;
4105                 vsi->sib_vsi_list.vsi = vsi;
4106                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4107                                 &vsi->sib_vsi_list, list);
4108         }
4109
4110         /* MAC/VLAN configuration */
4111         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4112         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4113
4114         ret = i40e_vsi_add_mac(vsi, &filter);
4115         if (ret != I40E_SUCCESS) {
4116                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4117                 goto fail_msix_alloc;
4118         }
4119
4120         /* Get VSI BW information */
4121         i40e_vsi_dump_bw_config(vsi);
4122         return vsi;
4123 fail_msix_alloc:
4124         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4125 fail_queue_alloc:
4126         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4127 fail_mem:
4128         rte_free(vsi);
4129         return NULL;
4130 }
4131
4132 /* Configure vlan stripping on or off */
4133 int
4134 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4135 {
4136         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4137         struct i40e_vsi_context ctxt;
4138         uint8_t vlan_flags;
4139         int ret = I40E_SUCCESS;
4140
4141         /* Check if it has been already on or off */
4142         if (vsi->info.valid_sections &
4143                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4144                 if (on) {
4145                         if ((vsi->info.port_vlan_flags &
4146                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4147                                 return 0; /* already on */
4148                 } else {
4149                         if ((vsi->info.port_vlan_flags &
4150                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4151                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4152                                 return 0; /* already off */
4153                 }
4154         }
4155
4156         if (on)
4157                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4158         else
4159                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4160         vsi->info.valid_sections =
4161                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4162         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4163         vsi->info.port_vlan_flags |= vlan_flags;
4164         ctxt.seid = vsi->seid;
4165         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4166         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4167         if (ret)
4168                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4169                             on ? "enable" : "disable");
4170
4171         return ret;
4172 }
4173
4174 static int
4175 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4176 {
4177         struct rte_eth_dev_data *data = dev->data;
4178         int ret;
4179
4180         /* Apply vlan offload setting */
4181         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
4182
4183         /* Apply double-vlan setting, not implemented yet */
4184
4185         /* Apply pvid setting */
4186         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4187                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4188         if (ret)
4189                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4190
4191         return ret;
4192 }
4193
4194 static int
4195 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4196 {
4197         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4198
4199         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4200 }
4201
4202 static int
4203 i40e_update_flow_control(struct i40e_hw *hw)
4204 {
4205 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4206         struct i40e_link_status link_status;
4207         uint32_t rxfc = 0, txfc = 0, reg;
4208         uint8_t an_info;
4209         int ret;
4210
4211         memset(&link_status, 0, sizeof(link_status));
4212         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4213         if (ret != I40E_SUCCESS) {
4214                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4215                 goto write_reg; /* Disable flow control */
4216         }
4217
4218         an_info = hw->phy.link_info.an_info;
4219         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4220                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4221                 ret = I40E_ERR_NOT_READY;
4222                 goto write_reg; /* Disable flow control */
4223         }
4224         /**
4225          * If link auto negotiation is enabled, flow control needs to
4226          * be configured according to it
4227          */
4228         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4229         case I40E_LINK_PAUSE_RXTX:
4230                 rxfc = 1;
4231                 txfc = 1;
4232                 hw->fc.current_mode = I40E_FC_FULL;
4233                 break;
4234         case I40E_AQ_LINK_PAUSE_RX:
4235                 rxfc = 1;
4236                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4237                 break;
4238         case I40E_AQ_LINK_PAUSE_TX:
4239                 txfc = 1;
4240                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4241                 break;
4242         default:
4243                 hw->fc.current_mode = I40E_FC_NONE;
4244                 break;
4245         }
4246
4247 write_reg:
4248         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4249                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4250         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4251         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4252         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4253         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4254
4255         return ret;
4256 }
4257
4258 /* PF setup */
4259 static int
4260 i40e_pf_setup(struct i40e_pf *pf)
4261 {
4262         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4263         struct i40e_filter_control_settings settings;
4264         struct i40e_vsi *vsi;
4265         int ret;
4266
4267         /* Clear all stats counters */
4268         pf->offset_loaded = FALSE;
4269         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4270         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4271
4272         ret = i40e_pf_get_switch_config(pf);
4273         if (ret != I40E_SUCCESS) {
4274                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4275                 return ret;
4276         }
4277         if (pf->flags & I40E_FLAG_FDIR) {
4278                 /* make queue allocated first, let FDIR use queue pair 0*/
4279                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4280                 if (ret != I40E_FDIR_QUEUE_ID) {
4281                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4282                                     " ret =%d", ret);
4283                         pf->flags &= ~I40E_FLAG_FDIR;
4284                 }
4285         }
4286         /*  main VSI setup */
4287         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4288         if (!vsi) {
4289                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4290                 return I40E_ERR_NOT_READY;
4291         }
4292         pf->main_vsi = vsi;
4293
4294         /* Configure filter control */
4295         memset(&settings, 0, sizeof(settings));
4296         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4297                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4298         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4299                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4300         else {
4301                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4302                                                 hw->func_caps.rss_table_size);
4303                 return I40E_ERR_PARAM;
4304         }
4305         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4306                         "size: %u\n", hw->func_caps.rss_table_size);
4307         pf->hash_lut_size = hw->func_caps.rss_table_size;
4308
4309         /* Enable ethtype and macvlan filters */
4310         settings.enable_ethtype = TRUE;
4311         settings.enable_macvlan = TRUE;
4312         ret = i40e_set_filter_control(hw, &settings);
4313         if (ret)
4314                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4315                                                                 ret);
4316
4317         /* Update flow control according to the auto negotiation */
4318         i40e_update_flow_control(hw);
4319
4320         return I40E_SUCCESS;
4321 }
4322
4323 int
4324 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4325 {
4326         uint32_t reg;
4327         uint16_t j;
4328
4329         /**
4330          * Set or clear TX Queue Disable flags,
4331          * which is required by hardware.
4332          */
4333         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4334         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4335
4336         /* Wait until the request is finished */
4337         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4338                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4339                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4340                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4341                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4342                                                         & 0x1))) {
4343                         break;
4344                 }
4345         }
4346         if (on) {
4347                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4348                         return I40E_SUCCESS; /* already on, skip next steps */
4349
4350                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4351                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4352         } else {
4353                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4354                         return I40E_SUCCESS; /* already off, skip next steps */
4355                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4356         }
4357         /* Write the register */
4358         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4359         /* Check the result */
4360         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4361                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4362                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4363                 if (on) {
4364                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4365                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4366                                 break;
4367                 } else {
4368                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4369                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4370                                 break;
4371                 }
4372         }
4373         /* Check if it is timeout */
4374         if (j >= I40E_CHK_Q_ENA_COUNT) {
4375                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4376                             (on ? "enable" : "disable"), q_idx);
4377                 return I40E_ERR_TIMEOUT;
4378         }
4379
4380         return I40E_SUCCESS;
4381 }
4382
4383 /* Swith on or off the tx queues */
4384 static int
4385 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4386 {
4387         struct rte_eth_dev_data *dev_data = pf->dev_data;
4388         struct i40e_tx_queue *txq;
4389         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4390         uint16_t i;
4391         int ret;
4392
4393         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4394                 txq = dev_data->tx_queues[i];
4395                 /* Don't operate the queue if not configured or
4396                  * if starting only per queue */
4397                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4398                         continue;
4399                 if (on)
4400                         ret = i40e_dev_tx_queue_start(dev, i);
4401                 else
4402                         ret = i40e_dev_tx_queue_stop(dev, i);
4403                 if ( ret != I40E_SUCCESS)
4404                         return ret;
4405         }
4406
4407         return I40E_SUCCESS;
4408 }
4409
4410 int
4411 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4412 {
4413         uint32_t reg;
4414         uint16_t j;
4415
4416         /* Wait until the request is finished */
4417         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4418                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4419                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4420                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4421                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4422                         break;
4423         }
4424
4425         if (on) {
4426                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4427                         return I40E_SUCCESS; /* Already on, skip next steps */
4428                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4429         } else {
4430                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4431                         return I40E_SUCCESS; /* Already off, skip next steps */
4432                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4433         }
4434
4435         /* Write the register */
4436         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4437         /* Check the result */
4438         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4439                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4440                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4441                 if (on) {
4442                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4443                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4444                                 break;
4445                 } else {
4446                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4447                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4448                                 break;
4449                 }
4450         }
4451
4452         /* Check if it is timeout */
4453         if (j >= I40E_CHK_Q_ENA_COUNT) {
4454                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4455                             (on ? "enable" : "disable"), q_idx);
4456                 return I40E_ERR_TIMEOUT;
4457         }
4458
4459         return I40E_SUCCESS;
4460 }
4461 /* Switch on or off the rx queues */
4462 static int
4463 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4464 {
4465         struct rte_eth_dev_data *dev_data = pf->dev_data;
4466         struct i40e_rx_queue *rxq;
4467         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4468         uint16_t i;
4469         int ret;
4470
4471         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4472                 rxq = dev_data->rx_queues[i];
4473                 /* Don't operate the queue if not configured or
4474                  * if starting only per queue */
4475                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4476                         continue;
4477                 if (on)
4478                         ret = i40e_dev_rx_queue_start(dev, i);
4479                 else
4480                         ret = i40e_dev_rx_queue_stop(dev, i);
4481                 if (ret != I40E_SUCCESS)
4482                         return ret;
4483         }
4484
4485         return I40E_SUCCESS;
4486 }
4487
4488 /* Switch on or off all the rx/tx queues */
4489 int
4490 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4491 {
4492         int ret;
4493
4494         if (on) {
4495                 /* enable rx queues before enabling tx queues */
4496                 ret = i40e_dev_switch_rx_queues(pf, on);
4497                 if (ret) {
4498                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4499                         return ret;
4500                 }
4501                 ret = i40e_dev_switch_tx_queues(pf, on);
4502         } else {
4503                 /* Stop tx queues before stopping rx queues */
4504                 ret = i40e_dev_switch_tx_queues(pf, on);
4505                 if (ret) {
4506                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4507                         return ret;
4508                 }
4509                 ret = i40e_dev_switch_rx_queues(pf, on);
4510         }
4511
4512         return ret;
4513 }
4514
4515 /* Initialize VSI for TX */
4516 static int
4517 i40e_dev_tx_init(struct i40e_pf *pf)
4518 {
4519         struct rte_eth_dev_data *data = pf->dev_data;
4520         uint16_t i;
4521         uint32_t ret = I40E_SUCCESS;
4522         struct i40e_tx_queue *txq;
4523
4524         for (i = 0; i < data->nb_tx_queues; i++) {
4525                 txq = data->tx_queues[i];
4526                 if (!txq || !txq->q_set)
4527                         continue;
4528                 ret = i40e_tx_queue_init(txq);
4529                 if (ret != I40E_SUCCESS)
4530                         break;
4531         }
4532         if (ret == I40E_SUCCESS)
4533                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4534                                      ->eth_dev);
4535
4536         return ret;
4537 }
4538
4539 /* Initialize VSI for RX */
4540 static int
4541 i40e_dev_rx_init(struct i40e_pf *pf)
4542 {
4543         struct rte_eth_dev_data *data = pf->dev_data;
4544         int ret = I40E_SUCCESS;
4545         uint16_t i;
4546         struct i40e_rx_queue *rxq;
4547
4548         i40e_pf_config_mq_rx(pf);
4549         for (i = 0; i < data->nb_rx_queues; i++) {
4550                 rxq = data->rx_queues[i];
4551                 if (!rxq || !rxq->q_set)
4552                         continue;
4553
4554                 ret = i40e_rx_queue_init(rxq);
4555                 if (ret != I40E_SUCCESS) {
4556                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4557                                     "initialization");
4558                         break;
4559                 }
4560         }
4561         if (ret == I40E_SUCCESS)
4562                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4563                                      ->eth_dev);
4564
4565         return ret;
4566 }
4567
4568 static int
4569 i40e_dev_rxtx_init(struct i40e_pf *pf)
4570 {
4571         int err;
4572
4573         err = i40e_dev_tx_init(pf);
4574         if (err) {
4575                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4576                 return err;
4577         }
4578         err = i40e_dev_rx_init(pf);
4579         if (err) {
4580                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4581                 return err;
4582         }
4583
4584         return err;
4585 }
4586
4587 static int
4588 i40e_vmdq_setup(struct rte_eth_dev *dev)
4589 {
4590         struct rte_eth_conf *conf = &dev->data->dev_conf;
4591         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4592         int i, err, conf_vsis, j, loop;
4593         struct i40e_vsi *vsi;
4594         struct i40e_vmdq_info *vmdq_info;
4595         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4596         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4597
4598         /*
4599          * Disable interrupt to avoid message from VF. Furthermore, it will
4600          * avoid race condition in VSI creation/destroy.
4601          */
4602         i40e_pf_disable_irq0(hw);
4603
4604         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4605                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4606                 return -ENOTSUP;
4607         }
4608
4609         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4610         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4611                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4612                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4613                         pf->max_nb_vmdq_vsi);
4614                 return -ENOTSUP;
4615         }
4616
4617         if (pf->vmdq != NULL) {
4618                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4619                 return 0;
4620         }
4621
4622         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4623                                 sizeof(*vmdq_info) * conf_vsis, 0);
4624
4625         if (pf->vmdq == NULL) {
4626                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4627                 return -ENOMEM;
4628         }
4629
4630         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4631
4632         /* Create VMDQ VSI */
4633         for (i = 0; i < conf_vsis; i++) {
4634                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4635                                 vmdq_conf->enable_loop_back);
4636                 if (vsi == NULL) {
4637                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4638                         err = -1;
4639                         goto err_vsi_setup;
4640                 }
4641                 vmdq_info = &pf->vmdq[i];
4642                 vmdq_info->pf = pf;
4643                 vmdq_info->vsi = vsi;
4644         }
4645         pf->nb_cfg_vmdq_vsi = conf_vsis;
4646
4647         /* Configure Vlan */
4648         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4649         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4650                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4651                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4652                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4653                                         vmdq_conf->pool_map[i].vlan_id, j);
4654
4655                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4656                                                 vmdq_conf->pool_map[i].vlan_id);
4657                                 if (err) {
4658                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4659                                         err = -1;
4660                                         goto err_vsi_setup;
4661                                 }
4662                         }
4663                 }
4664         }
4665
4666         i40e_pf_enable_irq0(hw);
4667
4668         return 0;
4669
4670 err_vsi_setup:
4671         for (i = 0; i < conf_vsis; i++)
4672                 if (pf->vmdq[i].vsi == NULL)
4673                         break;
4674                 else
4675                         i40e_vsi_release(pf->vmdq[i].vsi);
4676
4677         rte_free(pf->vmdq);
4678         pf->vmdq = NULL;
4679         i40e_pf_enable_irq0(hw);
4680         return err;
4681 }
4682
4683 static void
4684 i40e_stat_update_32(struct i40e_hw *hw,
4685                    uint32_t reg,
4686                    bool offset_loaded,
4687                    uint64_t *offset,
4688                    uint64_t *stat)
4689 {
4690         uint64_t new_data;
4691
4692         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4693         if (!offset_loaded)
4694                 *offset = new_data;
4695
4696         if (new_data >= *offset)
4697                 *stat = (uint64_t)(new_data - *offset);
4698         else
4699                 *stat = (uint64_t)((new_data +
4700                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4701 }
4702
4703 static void
4704 i40e_stat_update_48(struct i40e_hw *hw,
4705                    uint32_t hireg,
4706                    uint32_t loreg,
4707                    bool offset_loaded,
4708                    uint64_t *offset,
4709                    uint64_t *stat)
4710 {
4711         uint64_t new_data;
4712
4713         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4714         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4715                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4716
4717         if (!offset_loaded)
4718                 *offset = new_data;
4719
4720         if (new_data >= *offset)
4721                 *stat = new_data - *offset;
4722         else
4723                 *stat = (uint64_t)((new_data +
4724                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4725
4726         *stat &= I40E_48_BIT_MASK;
4727 }
4728
4729 /* Disable IRQ0 */
4730 void
4731 i40e_pf_disable_irq0(struct i40e_hw *hw)
4732 {
4733         /* Disable all interrupt types */
4734         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4735         I40E_WRITE_FLUSH(hw);
4736 }
4737
4738 /* Enable IRQ0 */
4739 void
4740 i40e_pf_enable_irq0(struct i40e_hw *hw)
4741 {
4742         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4743                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4744                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4745                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4746         I40E_WRITE_FLUSH(hw);
4747 }
4748
4749 static void
4750 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4751 {
4752         /* read pending request and disable first */
4753         i40e_pf_disable_irq0(hw);
4754         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4755         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4756                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4757
4758         if (no_queue)
4759                 /* Link no queues with irq0 */
4760                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4761                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4762 }
4763
4764 static void
4765 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4766 {
4767         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4768         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4769         int i;
4770         uint16_t abs_vf_id;
4771         uint32_t index, offset, val;
4772
4773         if (!pf->vfs)
4774                 return;
4775         /**
4776          * Try to find which VF trigger a reset, use absolute VF id to access
4777          * since the reg is global register.
4778          */
4779         for (i = 0; i < pf->vf_num; i++) {
4780                 abs_vf_id = hw->func_caps.vf_base_id + i;
4781                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4782                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4783                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4784                 /* VFR event occured */
4785                 if (val & (0x1 << offset)) {
4786                         int ret;
4787
4788                         /* Clear the event first */
4789                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4790                                                         (0x1 << offset));
4791                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4792                         /**
4793                          * Only notify a VF reset event occured,
4794                          * don't trigger another SW reset
4795                          */
4796                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4797                         if (ret != I40E_SUCCESS)
4798                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4799                 }
4800         }
4801 }
4802
4803 static void
4804 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4805 {
4806         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4807         struct i40e_arq_event_info info;
4808         uint16_t pending, opcode;
4809         int ret;
4810
4811         info.buf_len = I40E_AQ_BUF_SZ;
4812         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4813         if (!info.msg_buf) {
4814                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4815                 return;
4816         }
4817
4818         pending = 1;
4819         while (pending) {
4820                 ret = i40e_clean_arq_element(hw, &info, &pending);
4821
4822                 if (ret != I40E_SUCCESS) {
4823                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4824                                     "aq_err: %u", hw->aq.asq_last_status);
4825                         break;
4826                 }
4827                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4828
4829                 switch (opcode) {
4830                 case i40e_aqc_opc_send_msg_to_pf:
4831                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4832                         i40e_pf_host_handle_vf_msg(dev,
4833                                         rte_le_to_cpu_16(info.desc.retval),
4834                                         rte_le_to_cpu_32(info.desc.cookie_high),
4835                                         rte_le_to_cpu_32(info.desc.cookie_low),
4836                                         info.msg_buf,
4837                                         info.msg_len);
4838                         break;
4839                 default:
4840                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4841                                     opcode);
4842                         break;
4843                 }
4844         }
4845         rte_free(info.msg_buf);
4846 }
4847
4848 /*
4849  * Interrupt handler is registered as the alarm callback for handling LSC
4850  * interrupt in a definite of time, in order to wait the NIC into a stable
4851  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4852  * no need for link down interrupt.
4853  */
4854 static void
4855 i40e_dev_interrupt_delayed_handler(void *param)
4856 {
4857         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4858         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4859         uint32_t icr0;
4860
4861         /* read interrupt causes again */
4862         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4863
4864 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4865         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4866                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4867         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4868                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4869         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4870                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4871         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4872                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4873         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4874                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4875                                                                 "state\n");
4876         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4877                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4878         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4879                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4880 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4881
4882         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4883                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4884                 i40e_dev_handle_vfr_event(dev);
4885         }
4886         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4887                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4888                 i40e_dev_handle_aq_msg(dev);
4889         }
4890
4891         /* handle the link up interrupt in an alarm callback */
4892         i40e_dev_link_update(dev, 0);
4893         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4894
4895         i40e_pf_enable_irq0(hw);
4896         rte_intr_enable(&(dev->pci_dev->intr_handle));
4897 }
4898
4899 /**
4900  * Interrupt handler triggered by NIC  for handling
4901  * specific interrupt.
4902  *
4903  * @param handle
4904  *  Pointer to interrupt handle.
4905  * @param param
4906  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4907  *
4908  * @return
4909  *  void
4910  */
4911 static void
4912 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4913                            void *param)
4914 {
4915         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4916         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4917         uint32_t icr0;
4918
4919         /* Disable interrupt */
4920         i40e_pf_disable_irq0(hw);
4921
4922         /* read out interrupt causes */
4923         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4924
4925         /* No interrupt event indicated */
4926         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4927                 PMD_DRV_LOG(INFO, "No interrupt event");
4928                 goto done;
4929         }
4930 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4931         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4932                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4933         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4934                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4935         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4936                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4937         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4938                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4939         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4940                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4941         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4942                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4943         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4944                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4945 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4946
4947         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4948                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4949                 i40e_dev_handle_vfr_event(dev);
4950         }
4951         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4952                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4953                 i40e_dev_handle_aq_msg(dev);
4954         }
4955
4956         /* Link Status Change interrupt */
4957         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4958 #define I40E_US_PER_SECOND 1000000
4959                 struct rte_eth_link link;
4960
4961                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4962                 memset(&link, 0, sizeof(link));
4963                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4964                 i40e_dev_link_update(dev, 0);
4965
4966                 /*
4967                  * For link up interrupt, it needs to wait 1 second to let the
4968                  * hardware be a stable state. Otherwise several consecutive
4969                  * interrupts can be observed.
4970                  * For link down interrupt, no need to wait.
4971                  */
4972                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4973                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4974                         return;
4975                 else
4976                         _rte_eth_dev_callback_process(dev,
4977                                 RTE_ETH_EVENT_INTR_LSC);
4978         }
4979
4980 done:
4981         /* Enable interrupt */
4982         i40e_pf_enable_irq0(hw);
4983         rte_intr_enable(&(dev->pci_dev->intr_handle));
4984 }
4985
4986 static int
4987 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4988                          struct i40e_macvlan_filter *filter,
4989                          int total)
4990 {
4991         int ele_num, ele_buff_size;
4992         int num, actual_num, i;
4993         uint16_t flags;
4994         int ret = I40E_SUCCESS;
4995         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4996         struct i40e_aqc_add_macvlan_element_data *req_list;
4997
4998         if (filter == NULL  || total == 0)
4999                 return I40E_ERR_PARAM;
5000         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5001         ele_buff_size = hw->aq.asq_buf_size;
5002
5003         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5004         if (req_list == NULL) {
5005                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5006                 return I40E_ERR_NO_MEMORY;
5007         }
5008
5009         num = 0;
5010         do {
5011                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5012                 memset(req_list, 0, ele_buff_size);
5013
5014                 for (i = 0; i < actual_num; i++) {
5015                         (void)rte_memcpy(req_list[i].mac_addr,
5016                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5017                         req_list[i].vlan_tag =
5018                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5019
5020                         switch (filter[num + i].filter_type) {
5021                         case RTE_MAC_PERFECT_MATCH:
5022                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5023                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5024                                 break;
5025                         case RTE_MACVLAN_PERFECT_MATCH:
5026                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5027                                 break;
5028                         case RTE_MAC_HASH_MATCH:
5029                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5030                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5031                                 break;
5032                         case RTE_MACVLAN_HASH_MATCH:
5033                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5034                                 break;
5035                         default:
5036                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5037                                 ret = I40E_ERR_PARAM;
5038                                 goto DONE;
5039                         }
5040
5041                         req_list[i].queue_number = 0;
5042
5043                         req_list[i].flags = rte_cpu_to_le_16(flags);
5044                 }
5045
5046                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5047                                                 actual_num, NULL);
5048                 if (ret != I40E_SUCCESS) {
5049                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5050                         goto DONE;
5051                 }
5052                 num += actual_num;
5053         } while (num < total);
5054
5055 DONE:
5056         rte_free(req_list);
5057         return ret;
5058 }
5059
5060 static int
5061 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5062                             struct i40e_macvlan_filter *filter,
5063                             int total)
5064 {
5065         int ele_num, ele_buff_size;
5066         int num, actual_num, i;
5067         uint16_t flags;
5068         int ret = I40E_SUCCESS;
5069         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5070         struct i40e_aqc_remove_macvlan_element_data *req_list;
5071
5072         if (filter == NULL  || total == 0)
5073                 return I40E_ERR_PARAM;
5074
5075         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5076         ele_buff_size = hw->aq.asq_buf_size;
5077
5078         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5079         if (req_list == NULL) {
5080                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5081                 return I40E_ERR_NO_MEMORY;
5082         }
5083
5084         num = 0;
5085         do {
5086                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5087                 memset(req_list, 0, ele_buff_size);
5088
5089                 for (i = 0; i < actual_num; i++) {
5090                         (void)rte_memcpy(req_list[i].mac_addr,
5091                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5092                         req_list[i].vlan_tag =
5093                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5094
5095                         switch (filter[num + i].filter_type) {
5096                         case RTE_MAC_PERFECT_MATCH:
5097                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5098                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5099                                 break;
5100                         case RTE_MACVLAN_PERFECT_MATCH:
5101                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5102                                 break;
5103                         case RTE_MAC_HASH_MATCH:
5104                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5105                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5106                                 break;
5107                         case RTE_MACVLAN_HASH_MATCH:
5108                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5109                                 break;
5110                         default:
5111                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5112                                 ret = I40E_ERR_PARAM;
5113                                 goto DONE;
5114                         }
5115                         req_list[i].flags = rte_cpu_to_le_16(flags);
5116                 }
5117
5118                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5119                                                 actual_num, NULL);
5120                 if (ret != I40E_SUCCESS) {
5121                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5122                         goto DONE;
5123                 }
5124                 num += actual_num;
5125         } while (num < total);
5126
5127 DONE:
5128         rte_free(req_list);
5129         return ret;
5130 }
5131
5132 /* Find out specific MAC filter */
5133 static struct i40e_mac_filter *
5134 i40e_find_mac_filter(struct i40e_vsi *vsi,
5135                          struct ether_addr *macaddr)
5136 {
5137         struct i40e_mac_filter *f;
5138
5139         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5140                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5141                         return f;
5142         }
5143
5144         return NULL;
5145 }
5146
5147 static bool
5148 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5149                          uint16_t vlan_id)
5150 {
5151         uint32_t vid_idx, vid_bit;
5152
5153         if (vlan_id > ETH_VLAN_ID_MAX)
5154                 return 0;
5155
5156         vid_idx = I40E_VFTA_IDX(vlan_id);
5157         vid_bit = I40E_VFTA_BIT(vlan_id);
5158
5159         if (vsi->vfta[vid_idx] & vid_bit)
5160                 return 1;
5161         else
5162                 return 0;
5163 }
5164
5165 static void
5166 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5167                          uint16_t vlan_id, bool on)
5168 {
5169         uint32_t vid_idx, vid_bit;
5170
5171         if (vlan_id > ETH_VLAN_ID_MAX)
5172                 return;
5173
5174         vid_idx = I40E_VFTA_IDX(vlan_id);
5175         vid_bit = I40E_VFTA_BIT(vlan_id);
5176
5177         if (on)
5178                 vsi->vfta[vid_idx] |= vid_bit;
5179         else
5180                 vsi->vfta[vid_idx] &= ~vid_bit;
5181 }
5182
5183 /**
5184  * Find all vlan options for specific mac addr,
5185  * return with actual vlan found.
5186  */
5187 static inline int
5188 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5189                            struct i40e_macvlan_filter *mv_f,
5190                            int num, struct ether_addr *addr)
5191 {
5192         int i;
5193         uint32_t j, k;
5194
5195         /**
5196          * Not to use i40e_find_vlan_filter to decrease the loop time,
5197          * although the code looks complex.
5198           */
5199         if (num < vsi->vlan_num)
5200                 return I40E_ERR_PARAM;
5201
5202         i = 0;
5203         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5204                 if (vsi->vfta[j]) {
5205                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5206                                 if (vsi->vfta[j] & (1 << k)) {
5207                                         if (i > num - 1) {
5208                                                 PMD_DRV_LOG(ERR, "vlan number "
5209                                                             "not match");
5210                                                 return I40E_ERR_PARAM;
5211                                         }
5212                                         (void)rte_memcpy(&mv_f[i].macaddr,
5213                                                         addr, ETH_ADDR_LEN);
5214                                         mv_f[i].vlan_id =
5215                                                 j * I40E_UINT32_BIT_SIZE + k;
5216                                         i++;
5217                                 }
5218                         }
5219                 }
5220         }
5221         return I40E_SUCCESS;
5222 }
5223
5224 static inline int
5225 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5226                            struct i40e_macvlan_filter *mv_f,
5227                            int num,
5228                            uint16_t vlan)
5229 {
5230         int i = 0;
5231         struct i40e_mac_filter *f;
5232
5233         if (num < vsi->mac_num)
5234                 return I40E_ERR_PARAM;
5235
5236         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5237                 if (i > num - 1) {
5238                         PMD_DRV_LOG(ERR, "buffer number not match");
5239                         return I40E_ERR_PARAM;
5240                 }
5241                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5242                                 ETH_ADDR_LEN);
5243                 mv_f[i].vlan_id = vlan;
5244                 mv_f[i].filter_type = f->mac_info.filter_type;
5245                 i++;
5246         }
5247
5248         return I40E_SUCCESS;
5249 }
5250
5251 static int
5252 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5253 {
5254         int i, num;
5255         struct i40e_mac_filter *f;
5256         struct i40e_macvlan_filter *mv_f;
5257         int ret = I40E_SUCCESS;
5258
5259         if (vsi == NULL || vsi->mac_num == 0)
5260                 return I40E_ERR_PARAM;
5261
5262         /* Case that no vlan is set */
5263         if (vsi->vlan_num == 0)
5264                 num = vsi->mac_num;
5265         else
5266                 num = vsi->mac_num * vsi->vlan_num;
5267
5268         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5269         if (mv_f == NULL) {
5270                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5271                 return I40E_ERR_NO_MEMORY;
5272         }
5273
5274         i = 0;
5275         if (vsi->vlan_num == 0) {
5276                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5277                         (void)rte_memcpy(&mv_f[i].macaddr,
5278                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5279                         mv_f[i].vlan_id = 0;
5280                         i++;
5281                 }
5282         } else {
5283                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5284                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5285                                         vsi->vlan_num, &f->mac_info.mac_addr);
5286                         if (ret != I40E_SUCCESS)
5287                                 goto DONE;
5288                         i += vsi->vlan_num;
5289                 }
5290         }
5291
5292         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5293 DONE:
5294         rte_free(mv_f);
5295
5296         return ret;
5297 }
5298
5299 int
5300 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5301 {
5302         struct i40e_macvlan_filter *mv_f;
5303         int mac_num;
5304         int ret = I40E_SUCCESS;
5305
5306         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5307                 return I40E_ERR_PARAM;
5308
5309         /* If it's already set, just return */
5310         if (i40e_find_vlan_filter(vsi,vlan))
5311                 return I40E_SUCCESS;
5312
5313         mac_num = vsi->mac_num;
5314
5315         if (mac_num == 0) {
5316                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5317                 return I40E_ERR_PARAM;
5318         }
5319
5320         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5321
5322         if (mv_f == NULL) {
5323                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5324                 return I40E_ERR_NO_MEMORY;
5325         }
5326
5327         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5328
5329         if (ret != I40E_SUCCESS)
5330                 goto DONE;
5331
5332         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5333
5334         if (ret != I40E_SUCCESS)
5335                 goto DONE;
5336
5337         i40e_set_vlan_filter(vsi, vlan, 1);
5338
5339         vsi->vlan_num++;
5340         ret = I40E_SUCCESS;
5341 DONE:
5342         rte_free(mv_f);
5343         return ret;
5344 }
5345
5346 int
5347 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5348 {
5349         struct i40e_macvlan_filter *mv_f;
5350         int mac_num;
5351         int ret = I40E_SUCCESS;
5352
5353         /**
5354          * Vlan 0 is the generic filter for untagged packets
5355          * and can't be removed.
5356          */
5357         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5358                 return I40E_ERR_PARAM;
5359
5360         /* If can't find it, just return */
5361         if (!i40e_find_vlan_filter(vsi, vlan))
5362                 return I40E_ERR_PARAM;
5363
5364         mac_num = vsi->mac_num;
5365
5366         if (mac_num == 0) {
5367                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5368                 return I40E_ERR_PARAM;
5369         }
5370
5371         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5372
5373         if (mv_f == NULL) {
5374                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5375                 return I40E_ERR_NO_MEMORY;
5376         }
5377
5378         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5379
5380         if (ret != I40E_SUCCESS)
5381                 goto DONE;
5382
5383         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5384
5385         if (ret != I40E_SUCCESS)
5386                 goto DONE;
5387
5388         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5389         if (vsi->vlan_num == 1) {
5390                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5391                 if (ret != I40E_SUCCESS)
5392                         goto DONE;
5393
5394                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5395                 if (ret != I40E_SUCCESS)
5396                         goto DONE;
5397         }
5398
5399         i40e_set_vlan_filter(vsi, vlan, 0);
5400
5401         vsi->vlan_num--;
5402         ret = I40E_SUCCESS;
5403 DONE:
5404         rte_free(mv_f);
5405         return ret;
5406 }
5407
5408 int
5409 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5410 {
5411         struct i40e_mac_filter *f;
5412         struct i40e_macvlan_filter *mv_f;
5413         int i, vlan_num = 0;
5414         int ret = I40E_SUCCESS;
5415
5416         /* If it's add and we've config it, return */
5417         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5418         if (f != NULL)
5419                 return I40E_SUCCESS;
5420         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5421                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5422
5423                 /**
5424                  * If vlan_num is 0, that's the first time to add mac,
5425                  * set mask for vlan_id 0.
5426                  */
5427                 if (vsi->vlan_num == 0) {
5428                         i40e_set_vlan_filter(vsi, 0, 1);
5429                         vsi->vlan_num = 1;
5430                 }
5431                 vlan_num = vsi->vlan_num;
5432         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5433                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5434                 vlan_num = 1;
5435
5436         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5437         if (mv_f == NULL) {
5438                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5439                 return I40E_ERR_NO_MEMORY;
5440         }
5441
5442         for (i = 0; i < vlan_num; i++) {
5443                 mv_f[i].filter_type = mac_filter->filter_type;
5444                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5445                                 ETH_ADDR_LEN);
5446         }
5447
5448         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5449                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5450                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5451                                         &mac_filter->mac_addr);
5452                 if (ret != I40E_SUCCESS)
5453                         goto DONE;
5454         }
5455
5456         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5457         if (ret != I40E_SUCCESS)
5458                 goto DONE;
5459
5460         /* Add the mac addr into mac list */
5461         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5462         if (f == NULL) {
5463                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5464                 ret = I40E_ERR_NO_MEMORY;
5465                 goto DONE;
5466         }
5467         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5468                         ETH_ADDR_LEN);
5469         f->mac_info.filter_type = mac_filter->filter_type;
5470         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5471         vsi->mac_num++;
5472
5473         ret = I40E_SUCCESS;
5474 DONE:
5475         rte_free(mv_f);
5476
5477         return ret;
5478 }
5479
5480 int
5481 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5482 {
5483         struct i40e_mac_filter *f;
5484         struct i40e_macvlan_filter *mv_f;
5485         int i, vlan_num;
5486         enum rte_mac_filter_type filter_type;
5487         int ret = I40E_SUCCESS;
5488
5489         /* Can't find it, return an error */
5490         f = i40e_find_mac_filter(vsi, addr);
5491         if (f == NULL)
5492                 return I40E_ERR_PARAM;
5493
5494         vlan_num = vsi->vlan_num;
5495         filter_type = f->mac_info.filter_type;
5496         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5497                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5498                 if (vlan_num == 0) {
5499                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5500                         return I40E_ERR_PARAM;
5501                 }
5502         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5503                         filter_type == RTE_MAC_HASH_MATCH)
5504                 vlan_num = 1;
5505
5506         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5507         if (mv_f == NULL) {
5508                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5509                 return I40E_ERR_NO_MEMORY;
5510         }
5511
5512         for (i = 0; i < vlan_num; i++) {
5513                 mv_f[i].filter_type = filter_type;
5514                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5515                                 ETH_ADDR_LEN);
5516         }
5517         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5518                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5519                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5520                 if (ret != I40E_SUCCESS)
5521                         goto DONE;
5522         }
5523
5524         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5525         if (ret != I40E_SUCCESS)
5526                 goto DONE;
5527
5528         /* Remove the mac addr into mac list */
5529         TAILQ_REMOVE(&vsi->mac_list, f, next);
5530         rte_free(f);
5531         vsi->mac_num--;
5532
5533         ret = I40E_SUCCESS;
5534 DONE:
5535         rte_free(mv_f);
5536         return ret;
5537 }
5538
5539 /* Configure hash enable flags for RSS */
5540 uint64_t
5541 i40e_config_hena(uint64_t flags)
5542 {
5543         uint64_t hena = 0;
5544
5545         if (!flags)
5546                 return hena;
5547
5548         if (flags & ETH_RSS_FRAG_IPV4)
5549                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5550         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5551                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5552         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5553                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5554         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5555                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5556         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5557                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5558         if (flags & ETH_RSS_FRAG_IPV6)
5559                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5560         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5561                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5562         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5563                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5564         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5565                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5566         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5567                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5568         if (flags & ETH_RSS_L2_PAYLOAD)
5569                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5570
5571         return hena;
5572 }
5573
5574 /* Parse the hash enable flags */
5575 uint64_t
5576 i40e_parse_hena(uint64_t flags)
5577 {
5578         uint64_t rss_hf = 0;
5579
5580         if (!flags)
5581                 return rss_hf;
5582         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5583                 rss_hf |= ETH_RSS_FRAG_IPV4;
5584         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5585                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5586         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5587                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5588         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5589                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5590         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5591                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5592         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5593                 rss_hf |= ETH_RSS_FRAG_IPV6;
5594         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5595                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5596         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5597                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5598         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5599                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5600         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5601                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5602         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5603                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5604
5605         return rss_hf;
5606 }
5607
5608 /* Disable RSS */
5609 static void
5610 i40e_pf_disable_rss(struct i40e_pf *pf)
5611 {
5612         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5613         uint64_t hena;
5614
5615         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5616         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5617         hena &= ~I40E_RSS_HENA_ALL;
5618         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5619         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5620         I40E_WRITE_FLUSH(hw);
5621 }
5622
5623 static int
5624 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5625 {
5626         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5627         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5628         int ret = 0;
5629
5630         if (!key || key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) *
5631                 sizeof(uint32_t)))
5632                 return -EINVAL;
5633
5634         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5635                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5636                         (struct i40e_aqc_get_set_rss_key_data *)key;
5637
5638                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5639                 if (ret)
5640                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5641                                      "via AQ");
5642         } else {
5643                 uint32_t *hash_key = (uint32_t *)key;
5644                 uint16_t i;
5645
5646                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5647                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5648                 I40E_WRITE_FLUSH(hw);
5649         }
5650
5651         return ret;
5652 }
5653
5654 static int
5655 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5656 {
5657         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5658         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5659         int ret;
5660
5661         if (!key || !key_len)
5662                 return -EINVAL;
5663
5664         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5665                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5666                         (struct i40e_aqc_get_set_rss_key_data *)key);
5667                 if (ret) {
5668                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5669                         return ret;
5670                 }
5671         } else {
5672                 uint32_t *key_dw = (uint32_t *)key;
5673                 uint16_t i;
5674
5675                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5676                         key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5677         }
5678         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5679
5680         return 0;
5681 }
5682
5683 static int
5684 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5685 {
5686         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5687         uint64_t rss_hf;
5688         uint64_t hena;
5689         int ret;
5690
5691         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5692                                rss_conf->rss_key_len);
5693         if (ret)
5694                 return ret;
5695
5696         rss_hf = rss_conf->rss_hf;
5697         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5698         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5699         hena &= ~I40E_RSS_HENA_ALL;
5700         hena |= i40e_config_hena(rss_hf);
5701         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5702         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5703         I40E_WRITE_FLUSH(hw);
5704
5705         return 0;
5706 }
5707
5708 static int
5709 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5710                          struct rte_eth_rss_conf *rss_conf)
5711 {
5712         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5714         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5715         uint64_t hena;
5716
5717         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5718         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5719         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5720                 if (rss_hf != 0) /* Enable RSS */
5721                         return -EINVAL;
5722                 return 0; /* Nothing to do */
5723         }
5724         /* RSS enabled */
5725         if (rss_hf == 0) /* Disable RSS */
5726                 return -EINVAL;
5727
5728         return i40e_hw_rss_hash_set(pf, rss_conf);
5729 }
5730
5731 static int
5732 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5733                            struct rte_eth_rss_conf *rss_conf)
5734 {
5735         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5736         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5737         uint64_t hena;
5738
5739         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5740                          &rss_conf->rss_key_len);
5741
5742         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5743         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5744         rss_conf->rss_hf = i40e_parse_hena(hena);
5745
5746         return 0;
5747 }
5748
5749 static int
5750 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5751 {
5752         switch (filter_type) {
5753         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5754                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5755                 break;
5756         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5757                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5758                 break;
5759         case RTE_TUNNEL_FILTER_IMAC_TENID:
5760                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5761                 break;
5762         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5763                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5764                 break;
5765         case ETH_TUNNEL_FILTER_IMAC:
5766                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5767                 break;
5768         default:
5769                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5770                 return -EINVAL;
5771         }
5772
5773         return 0;
5774 }
5775
5776 static int
5777 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5778                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5779                         uint8_t add)
5780 {
5781         uint16_t ip_type;
5782         uint8_t tun_type = 0;
5783         int val, ret = 0;
5784         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5785         struct i40e_vsi *vsi = pf->main_vsi;
5786         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5787         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5788
5789         cld_filter = rte_zmalloc("tunnel_filter",
5790                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5791                 0);
5792
5793         if (NULL == cld_filter) {
5794                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5795                 return -EINVAL;
5796         }
5797         pfilter = cld_filter;
5798
5799         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5800                         sizeof(struct ether_addr));
5801         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5802                         sizeof(struct ether_addr));
5803
5804         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5805         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5806                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5807                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5808                                 &tunnel_filter->ip_addr,
5809                                 sizeof(pfilter->ipaddr.v4.data));
5810         } else {
5811                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5812                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5813                                 &tunnel_filter->ip_addr,
5814                                 sizeof(pfilter->ipaddr.v6.data));
5815         }
5816
5817         /* check tunneled type */
5818         switch (tunnel_filter->tunnel_type) {
5819         case RTE_TUNNEL_TYPE_VXLAN:
5820                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5821                 break;
5822         case RTE_TUNNEL_TYPE_NVGRE:
5823                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5824                 break;
5825         default:
5826                 /* Other tunnel types is not supported. */
5827                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5828                 rte_free(cld_filter);
5829                 return -EINVAL;
5830         }
5831
5832         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5833                                                 &pfilter->flags);
5834         if (val < 0) {
5835                 rte_free(cld_filter);
5836                 return -EINVAL;
5837         }
5838
5839         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5840                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5841         pfilter->tenant_id = tunnel_filter->tenant_id;
5842         pfilter->queue_number = tunnel_filter->queue_id;
5843
5844         if (add)
5845                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5846         else
5847                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5848                                                 cld_filter, 1);
5849
5850         rte_free(cld_filter);
5851         return ret;
5852 }
5853
5854 static int
5855 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5856 {
5857         uint8_t i;
5858
5859         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5860                 if (pf->vxlan_ports[i] == port)
5861                         return i;
5862         }
5863
5864         return -1;
5865 }
5866
5867 static int
5868 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5869 {
5870         int  idx, ret;
5871         uint8_t filter_idx;
5872         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5873
5874         idx = i40e_get_vxlan_port_idx(pf, port);
5875
5876         /* Check if port already exists */
5877         if (idx >= 0) {
5878                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5879                 return -EINVAL;
5880         }
5881
5882         /* Now check if there is space to add the new port */
5883         idx = i40e_get_vxlan_port_idx(pf, 0);
5884         if (idx < 0) {
5885                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5886                         "not adding port %d", port);
5887                 return -ENOSPC;
5888         }
5889
5890         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5891                                         &filter_idx, NULL);
5892         if (ret < 0) {
5893                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5894                 return -1;
5895         }
5896
5897         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5898                          port,  filter_idx);
5899
5900         /* New port: add it and mark its index in the bitmap */
5901         pf->vxlan_ports[idx] = port;
5902         pf->vxlan_bitmap |= (1 << idx);
5903
5904         if (!(pf->flags & I40E_FLAG_VXLAN))
5905                 pf->flags |= I40E_FLAG_VXLAN;
5906
5907         return 0;
5908 }
5909
5910 static int
5911 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5912 {
5913         int idx;
5914         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5915
5916         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5917                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5918                 return -EINVAL;
5919         }
5920
5921         idx = i40e_get_vxlan_port_idx(pf, port);
5922
5923         if (idx < 0) {
5924                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5925                 return -EINVAL;
5926         }
5927
5928         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5929                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5930                 return -1;
5931         }
5932
5933         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5934                         port, idx);
5935
5936         pf->vxlan_ports[idx] = 0;
5937         pf->vxlan_bitmap &= ~(1 << idx);
5938
5939         if (!pf->vxlan_bitmap)
5940                 pf->flags &= ~I40E_FLAG_VXLAN;
5941
5942         return 0;
5943 }
5944
5945 /* Add UDP tunneling port */
5946 static int
5947 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5948                         struct rte_eth_udp_tunnel *udp_tunnel)
5949 {
5950         int ret = 0;
5951         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5952
5953         if (udp_tunnel == NULL)
5954                 return -EINVAL;
5955
5956         switch (udp_tunnel->prot_type) {
5957         case RTE_TUNNEL_TYPE_VXLAN:
5958                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5959                 break;
5960
5961         case RTE_TUNNEL_TYPE_GENEVE:
5962         case RTE_TUNNEL_TYPE_TEREDO:
5963                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5964                 ret = -1;
5965                 break;
5966
5967         default:
5968                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5969                 ret = -1;
5970                 break;
5971         }
5972
5973         return ret;
5974 }
5975
5976 /* Remove UDP tunneling port */
5977 static int
5978 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5979                         struct rte_eth_udp_tunnel *udp_tunnel)
5980 {
5981         int ret = 0;
5982         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5983
5984         if (udp_tunnel == NULL)
5985                 return -EINVAL;
5986
5987         switch (udp_tunnel->prot_type) {
5988         case RTE_TUNNEL_TYPE_VXLAN:
5989                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5990                 break;
5991         case RTE_TUNNEL_TYPE_GENEVE:
5992         case RTE_TUNNEL_TYPE_TEREDO:
5993                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5994                 ret = -1;
5995                 break;
5996         default:
5997                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5998                 ret = -1;
5999                 break;
6000         }
6001
6002         return ret;
6003 }
6004
6005 /* Calculate the maximum number of contiguous PF queues that are configured */
6006 static int
6007 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6008 {
6009         struct rte_eth_dev_data *data = pf->dev_data;
6010         int i, num;
6011         struct i40e_rx_queue *rxq;
6012
6013         num = 0;
6014         for (i = 0; i < pf->lan_nb_qps; i++) {
6015                 rxq = data->rx_queues[i];
6016                 if (rxq && rxq->q_set)
6017                         num++;
6018                 else
6019                         break;
6020         }
6021
6022         return num;
6023 }
6024
6025 /* Configure RSS */
6026 static int
6027 i40e_pf_config_rss(struct i40e_pf *pf)
6028 {
6029         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6030         struct rte_eth_rss_conf rss_conf;
6031         uint32_t i, lut = 0;
6032         uint16_t j, num;
6033
6034         /*
6035          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6036          * It's necessary to calulate the actual PF queues that are configured.
6037          */
6038         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6039                 num = i40e_pf_calc_configured_queues_num(pf);
6040         else
6041                 num = pf->dev_data->nb_rx_queues;
6042
6043         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6044         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6045                         num);
6046
6047         if (num == 0) {
6048                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6049                 return -ENOTSUP;
6050         }
6051
6052         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6053                 if (j == num)
6054                         j = 0;
6055                 lut = (lut << 8) | (j & ((0x1 <<
6056                         hw->func_caps.rss_table_entry_width) - 1));
6057                 if ((i & 3) == 3)
6058                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6059         }
6060
6061         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6062         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6063                 i40e_pf_disable_rss(pf);
6064                 return 0;
6065         }
6066         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6067                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6068                 /* Random default keys */
6069                 static uint32_t rss_key_default[] = {0x6b793944,
6070                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6071                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6072                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6073
6074                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6075                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6076                                                         sizeof(uint32_t);
6077         }
6078
6079         return i40e_hw_rss_hash_set(pf, &rss_conf);
6080 }
6081
6082 static int
6083 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6084                                struct rte_eth_tunnel_filter_conf *filter)
6085 {
6086         if (pf == NULL || filter == NULL) {
6087                 PMD_DRV_LOG(ERR, "Invalid parameter");
6088                 return -EINVAL;
6089         }
6090
6091         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6092                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6093                 return -EINVAL;
6094         }
6095
6096         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6097                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6098                 return -EINVAL;
6099         }
6100
6101         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6102                 (is_zero_ether_addr(filter->outer_mac))) {
6103                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6104                 return -EINVAL;
6105         }
6106
6107         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6108                 (is_zero_ether_addr(filter->inner_mac))) {
6109                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6110                 return -EINVAL;
6111         }
6112
6113         return 0;
6114 }
6115
6116 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6117 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6118 static int
6119 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6120 {
6121         uint32_t val, reg;
6122         int ret = -EINVAL;
6123
6124         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6125         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6126
6127         if (len == 3) {
6128                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6129         } else if (len == 4) {
6130                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6131         } else {
6132                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6133                 return ret;
6134         }
6135
6136         if (reg != val) {
6137                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6138                                                    reg, NULL);
6139                 if (ret != 0)
6140                         return ret;
6141         } else {
6142                 ret = 0;
6143         }
6144         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6145                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6146
6147         return ret;
6148 }
6149
6150 static int
6151 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6152 {
6153         int ret = -EINVAL;
6154
6155         if (!hw || !cfg)
6156                 return -EINVAL;
6157
6158         switch (cfg->cfg_type) {
6159         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6160                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6161                 break;
6162         default:
6163                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6164                 break;
6165         }
6166
6167         return ret;
6168 }
6169
6170 static int
6171 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6172                                enum rte_filter_op filter_op,
6173                                void *arg)
6174 {
6175         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6176         int ret = I40E_ERR_PARAM;
6177
6178         switch (filter_op) {
6179         case RTE_ETH_FILTER_SET:
6180                 ret = i40e_dev_global_config_set(hw,
6181                         (struct rte_eth_global_cfg *)arg);
6182                 break;
6183         default:
6184                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6185                 break;
6186         }
6187
6188         return ret;
6189 }
6190
6191 static int
6192 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6193                           enum rte_filter_op filter_op,
6194                           void *arg)
6195 {
6196         struct rte_eth_tunnel_filter_conf *filter;
6197         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6198         int ret = I40E_SUCCESS;
6199
6200         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6201
6202         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6203                 return I40E_ERR_PARAM;
6204
6205         switch (filter_op) {
6206         case RTE_ETH_FILTER_NOP:
6207                 if (!(pf->flags & I40E_FLAG_VXLAN))
6208                         ret = I40E_NOT_SUPPORTED;
6209                 break;
6210         case RTE_ETH_FILTER_ADD:
6211                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6212                 break;
6213         case RTE_ETH_FILTER_DELETE:
6214                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6215                 break;
6216         default:
6217                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6218                 ret = I40E_ERR_PARAM;
6219                 break;
6220         }
6221
6222         return ret;
6223 }
6224
6225 static int
6226 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6227 {
6228         int ret = 0;
6229         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6230
6231         /* RSS setup */
6232         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6233                 ret = i40e_pf_config_rss(pf);
6234         else
6235                 i40e_pf_disable_rss(pf);
6236
6237         return ret;
6238 }
6239
6240 /* Get the symmetric hash enable configurations per port */
6241 static void
6242 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6243 {
6244         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6245
6246         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6247 }
6248
6249 /* Set the symmetric hash enable configurations per port */
6250 static void
6251 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6252 {
6253         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6254
6255         if (enable > 0) {
6256                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6257                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6258                                                         "been enabled");
6259                         return;
6260                 }
6261                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6262         } else {
6263                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6264                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6265                                                         "been disabled");
6266                         return;
6267                 }
6268                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6269         }
6270         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
6271         I40E_WRITE_FLUSH(hw);
6272 }
6273
6274 /*
6275  * Get global configurations of hash function type and symmetric hash enable
6276  * per flow type (pctype). Note that global configuration means it affects all
6277  * the ports on the same NIC.
6278  */
6279 static int
6280 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6281                                    struct rte_eth_hash_global_conf *g_cfg)
6282 {
6283         uint32_t reg, mask = I40E_FLOW_TYPES;
6284         uint16_t i;
6285         enum i40e_filter_pctype pctype;
6286
6287         memset(g_cfg, 0, sizeof(*g_cfg));
6288         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6289         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6290                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6291         else
6292                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6293         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6294                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6295
6296         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6297                 if (!(mask & (1UL << i)))
6298                         continue;
6299                 mask &= ~(1UL << i);
6300                 /* Bit set indicats the coresponding flow type is supported */
6301                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6302                 pctype = i40e_flowtype_to_pctype(i);
6303                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
6304                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6305                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6306         }
6307
6308         return 0;
6309 }
6310
6311 static int
6312 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6313 {
6314         uint32_t i;
6315         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6316
6317         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6318                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6319                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6320                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6321                                                 g_cfg->hash_func);
6322                 return -EINVAL;
6323         }
6324
6325         /*
6326          * As i40e supports less than 32 flow types, only first 32 bits need to
6327          * be checked.
6328          */
6329         mask0 = g_cfg->valid_bit_mask[0];
6330         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6331                 if (i == 0) {
6332                         /* Check if any unsupported flow type configured */
6333                         if ((mask0 | i40e_mask) ^ i40e_mask)
6334                                 goto mask_err;
6335                 } else {
6336                         if (g_cfg->valid_bit_mask[i])
6337                                 goto mask_err;
6338                 }
6339         }
6340
6341         return 0;
6342
6343 mask_err:
6344         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6345
6346         return -EINVAL;
6347 }
6348
6349 /*
6350  * Set global configurations of hash function type and symmetric hash enable
6351  * per flow type (pctype). Note any modifying global configuration will affect
6352  * all the ports on the same NIC.
6353  */
6354 static int
6355 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6356                                    struct rte_eth_hash_global_conf *g_cfg)
6357 {
6358         int ret;
6359         uint16_t i;
6360         uint32_t reg;
6361         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6362         enum i40e_filter_pctype pctype;
6363
6364         /* Check the input parameters */
6365         ret = i40e_hash_global_config_check(g_cfg);
6366         if (ret < 0)
6367                 return ret;
6368
6369         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6370                 if (!(mask0 & (1UL << i)))
6371                         continue;
6372                 mask0 &= ~(1UL << i);
6373                 pctype = i40e_flowtype_to_pctype(i);
6374                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6375                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6376                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
6377         }
6378
6379         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6380         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6381                 /* Toeplitz */
6382                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6383                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6384                                                                 "Toeplitz");
6385                         goto out;
6386                 }
6387                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6388         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6389                 /* Simple XOR */
6390                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6391                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6392                                                         "Simple XOR");
6393                         goto out;
6394                 }
6395                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6396         } else
6397                 /* Use the default, and keep it as it is */
6398                 goto out;
6399
6400         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6401
6402 out:
6403         I40E_WRITE_FLUSH(hw);
6404
6405         return 0;
6406 }
6407
6408 /**
6409  * Valid input sets for hash and flow director filters per PCTYPE
6410  */
6411 static uint64_t
6412 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6413                 enum rte_filter_type filter)
6414 {
6415         uint64_t valid;
6416
6417         static const uint64_t valid_hash_inset_table[] = {
6418                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6419                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6420                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6421                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6422                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6423                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6424                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6425                         I40E_INSET_FLEX_PAYLOAD,
6426                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6427                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6428                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6429                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6430                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6431                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6432                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6433                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6434                         I40E_INSET_FLEX_PAYLOAD,
6435                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6436                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6437                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6438                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6439                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6440                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6441                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6442                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6443                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6444                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6445                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6446                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6447                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6448                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6449                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6450                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6451                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6452                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6453                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6454                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6455                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6456                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6457                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6458                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6459                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6460                         I40E_INSET_FLEX_PAYLOAD,
6461                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6462                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6463                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6464                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6465                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6466                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6467                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6468                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6469                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6470                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6471                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6472                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6473                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6474                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6475                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6476                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6477                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6478                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6479                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6480                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6481                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6482                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6483                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6484                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6485                         I40E_INSET_FLEX_PAYLOAD,
6486                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6487                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6488                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6489                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6490                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6491                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6492                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6493                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6494                         I40E_INSET_FLEX_PAYLOAD,
6495                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6496                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6497                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6498                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6499                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6500                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6501                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6502                         I40E_INSET_FLEX_PAYLOAD,
6503                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6504                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6505                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6506                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6507                         I40E_INSET_FLEX_PAYLOAD,
6508         };
6509
6510         /**
6511          * Flow director supports only fields defined in
6512          * union rte_eth_fdir_flow.
6513          */
6514         static const uint64_t valid_fdir_inset_table[] = {
6515                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6516                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6517                 I40E_INSET_FLEX_PAYLOAD,
6518                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6519                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6520                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6521                 I40E_INSET_FLEX_PAYLOAD,
6522                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6523                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6524                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6525                 I40E_INSET_FLEX_PAYLOAD,
6526                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6527                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6528                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6529                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6530                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6531                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6532                 I40E_INSET_FLEX_PAYLOAD,
6533                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6534                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6535                 I40E_INSET_FLEX_PAYLOAD,
6536                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6537                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6538                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6539                 I40E_INSET_FLEX_PAYLOAD,
6540                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6541                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6542                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6543                 I40E_INSET_FLEX_PAYLOAD,
6544                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6545                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6546                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6547                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6548                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6549                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6550                 I40E_INSET_FLEX_PAYLOAD,
6551                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6552                 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6553         };
6554
6555         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6556                 return 0;
6557         if (filter == RTE_ETH_FILTER_HASH)
6558                 valid = valid_hash_inset_table[pctype];
6559         else
6560                 valid = valid_fdir_inset_table[pctype];
6561
6562         return valid;
6563 }
6564
6565 /**
6566  * Validate if the input set is allowed for a specific PCTYPE
6567  */
6568 static int
6569 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6570                 enum rte_filter_type filter, uint64_t inset)
6571 {
6572         uint64_t valid;
6573
6574         valid = i40e_get_valid_input_set(pctype, filter);
6575         if (inset & (~valid))
6576                 return -EINVAL;
6577
6578         return 0;
6579 }
6580
6581 /* default input set fields combination per pctype */
6582 static uint64_t
6583 i40e_get_default_input_set(uint16_t pctype)
6584 {
6585         static const uint64_t default_inset_table[] = {
6586                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6587                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6588                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6589                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6590                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6591                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6592                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6593                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6594                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6595                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6596                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6597                         I40E_INSET_SCTP_VT,
6598                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6599                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6600                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6601                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6602                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6603                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6604                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6605                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6606                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6607                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6608                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6609                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6610                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6611                         I40E_INSET_SCTP_VT,
6612                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6613                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6614                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6615                         I40E_INSET_LAST_ETHER_TYPE,
6616         };
6617
6618         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6619                 return 0;
6620
6621         return default_inset_table[pctype];
6622 }
6623
6624 /**
6625  * Parse the input set from index to logical bit masks
6626  */
6627 static int
6628 i40e_parse_input_set(uint64_t *inset,
6629                      enum i40e_filter_pctype pctype,
6630                      enum rte_eth_input_set_field *field,
6631                      uint16_t size)
6632 {
6633         uint16_t i, j;
6634         int ret = -EINVAL;
6635
6636         static const struct {
6637                 enum rte_eth_input_set_field field;
6638                 uint64_t inset;
6639         } inset_convert_table[] = {
6640                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6641                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6642                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6643                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6644                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6645                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6646                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6647                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6648                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6649                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6650                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6651                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6652                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6653                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6654                         I40E_INSET_IPV6_NEXT_HDR},
6655                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6656                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6657                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6658                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6659                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6660                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6661                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6662                         I40E_INSET_SCTP_VT},
6663                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6664                         I40E_INSET_TUNNEL_DMAC},
6665                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6666                         I40E_INSET_VLAN_TUNNEL},
6667                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6668                         I40E_INSET_TUNNEL_ID},
6669                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6670                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6671                         I40E_INSET_FLEX_PAYLOAD_W1},
6672                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6673                         I40E_INSET_FLEX_PAYLOAD_W2},
6674                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6675                         I40E_INSET_FLEX_PAYLOAD_W3},
6676                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6677                         I40E_INSET_FLEX_PAYLOAD_W4},
6678                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6679                         I40E_INSET_FLEX_PAYLOAD_W5},
6680                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6681                         I40E_INSET_FLEX_PAYLOAD_W6},
6682                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6683                         I40E_INSET_FLEX_PAYLOAD_W7},
6684                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6685                         I40E_INSET_FLEX_PAYLOAD_W8},
6686         };
6687
6688         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6689                 return ret;
6690
6691         /* Only one item allowed for default or all */
6692         if (size == 1) {
6693                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6694                         *inset = i40e_get_default_input_set(pctype);
6695                         return 0;
6696                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6697                         *inset = I40E_INSET_NONE;
6698                         return 0;
6699                 }
6700         }
6701
6702         for (i = 0, *inset = 0; i < size; i++) {
6703                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6704                         if (field[i] == inset_convert_table[j].field) {
6705                                 *inset |= inset_convert_table[j].inset;
6706                                 break;
6707                         }
6708                 }
6709
6710                 /* It contains unsupported input set, return immediately */
6711                 if (j == RTE_DIM(inset_convert_table))
6712                         return ret;
6713         }
6714
6715         return 0;
6716 }
6717
6718 /**
6719  * Translate the input set from bit masks to register aware bit masks
6720  * and vice versa
6721  */
6722 static uint64_t
6723 i40e_translate_input_set_reg(uint64_t input)
6724 {
6725         uint64_t val = 0;
6726         uint16_t i;
6727
6728         static const struct {
6729                 uint64_t inset;
6730                 uint64_t inset_reg;
6731         } inset_map[] = {
6732                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6733                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6734                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6735                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6736                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6737                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6738                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6739                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6740                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6741                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6742                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6743                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6744                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6745                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6746                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6747                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6748                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6749                 {I40E_INSET_TUNNEL_DMAC,
6750                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6751                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6752                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6753                 {I40E_INSET_TUNNEL_SRC_PORT,
6754                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6755                 {I40E_INSET_TUNNEL_DST_PORT,
6756                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6757                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6758                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6759                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6760                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6761                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6762                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6763                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6764                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6765                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6766         };
6767
6768         if (input == 0)
6769                 return val;
6770
6771         /* Translate input set to register aware inset */
6772         for (i = 0; i < RTE_DIM(inset_map); i++) {
6773                 if (input & inset_map[i].inset)
6774                         val |= inset_map[i].inset_reg;
6775         }
6776
6777         return val;
6778 }
6779
6780 static uint8_t
6781 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6782 {
6783         uint8_t i, idx = 0;
6784
6785         static const struct {
6786                 uint64_t inset;
6787                 uint32_t mask;
6788         } inset_mask_map[] = {
6789                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6790                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6791                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6792                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6793         };
6794
6795         if (!inset || !mask || !nb_elem)
6796                 return 0;
6797
6798         if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6799                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6800                         mask[i] = 0;
6801                 return I40E_INSET_MASK_NUM_REG;
6802         }
6803
6804         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6805                 if (idx >= nb_elem)
6806                         break;
6807                 if (inset & inset_mask_map[i].inset) {
6808                         mask[idx] = inset_mask_map[i].mask;
6809                         idx++;
6810                 }
6811         }
6812
6813         return idx;
6814 }
6815
6816 static uint64_t
6817 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
6818                             enum i40e_filter_pctype pctype)
6819 {
6820         uint64_t reg = 0;
6821
6822         if (filter == RTE_ETH_FILTER_HASH) {
6823                 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
6824                 reg <<= I40E_32_BIT_WIDTH;
6825                 reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
6826         } else if (filter == RTE_ETH_FILTER_FDIR) {
6827                 reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
6828                 reg <<= I40E_32_BIT_WIDTH;
6829                 reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
6830         }
6831
6832         return reg;
6833 }
6834
6835 static void
6836 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
6837 {
6838         uint32_t reg = I40E_READ_REG(hw, addr);
6839
6840         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
6841         if (reg != val)
6842                 I40E_WRITE_REG(hw, addr, val);
6843         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
6844                     (uint32_t)I40E_READ_REG(hw, addr));
6845 }
6846
6847 static int
6848 i40e_set_hash_inset_mask(struct i40e_hw *hw,
6849                          enum i40e_filter_pctype pctype,
6850                          enum rte_filter_input_set_op op,
6851                          uint32_t *mask_reg,
6852                          uint8_t num)
6853 {
6854         uint32_t reg;
6855         uint8_t i;
6856
6857         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6858                 return -EINVAL;
6859
6860         if (op == RTE_ETH_INPUT_SET_SELECT) {
6861                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6862                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6863                                              0);
6864                         if (i >= num)
6865                                 continue;
6866                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6867                                              mask_reg[i]);
6868                 }
6869         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6870                 uint8_t j, count = 0;
6871
6872                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6873                         reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
6874                         if (reg & I40E_GLQF_HASH_MSK_FIELD)
6875                                 count++;
6876                 }
6877                 if (count + num > I40E_INSET_MASK_NUM_REG)
6878                         return -EINVAL;
6879
6880                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6881                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6882                                              mask_reg[j]);
6883         }
6884
6885         return 0;
6886 }
6887
6888 static int
6889 i40e_set_fd_inset_mask(struct i40e_hw *hw,
6890                        enum i40e_filter_pctype pctype,
6891                        enum rte_filter_input_set_op op,
6892                        uint32_t *mask_reg,
6893                        uint8_t num)
6894 {
6895         uint32_t reg;
6896         uint8_t i;
6897
6898         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6899                 return -EINVAL;
6900
6901         if (op == RTE_ETH_INPUT_SET_SELECT) {
6902                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6903                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6904                                              0);
6905                         if (i >= num)
6906                                 continue;
6907                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6908                                              mask_reg[i]);
6909                 }
6910         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6911                 uint8_t j, count = 0;
6912
6913                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6914                         reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
6915                         if (reg & I40E_GLQF_FD_MSK_FIELD)
6916                                 count++;
6917                 }
6918                 if (count + num > I40E_INSET_MASK_NUM_REG)
6919                         return -EINVAL;
6920
6921                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6922                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6923                                              mask_reg[j]);
6924         }
6925
6926         return 0;
6927 }
6928
6929 int
6930 i40e_filter_inset_select(struct i40e_hw *hw,
6931                          struct rte_eth_input_set_conf *conf,
6932                          enum rte_filter_type filter)
6933 {
6934         enum i40e_filter_pctype pctype;
6935         uint64_t inset_reg = 0, input_set;
6936         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
6937         uint8_t num;
6938         int ret;
6939
6940         if (!hw || !conf) {
6941                 PMD_DRV_LOG(ERR, "Invalid pointer");
6942                 return -EFAULT;
6943         }
6944
6945         pctype = i40e_flowtype_to_pctype(conf->flow_type);
6946         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
6947                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
6948                             conf->flow_type);
6949                 return -EINVAL;
6950         }
6951         if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
6952                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6953                 return -EINVAL;
6954         }
6955
6956         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
6957                                    conf->inset_size);
6958         if (ret) {
6959                 PMD_DRV_LOG(ERR, "Failed to parse input set");
6960                 return -EINVAL;
6961         }
6962         if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
6963                 PMD_DRV_LOG(ERR, "Invalid input set");
6964                 return -EINVAL;
6965         }
6966
6967         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
6968                 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
6969         } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
6970                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
6971                 return -EINVAL;
6972         }
6973         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
6974                                            I40E_INSET_MASK_NUM_REG);
6975         inset_reg |= i40e_translate_input_set_reg(input_set);
6976
6977         if (filter == RTE_ETH_FILTER_HASH) {
6978                 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
6979                                                num);
6980                 if (ret)
6981                         return -EINVAL;
6982
6983                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
6984                                       (uint32_t)(inset_reg & UINT32_MAX));
6985                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
6986                                      (uint32_t)((inset_reg >>
6987                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
6988         } else if (filter == RTE_ETH_FILTER_FDIR) {
6989                 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
6990                                              num);
6991                 if (ret)
6992                         return -EINVAL;
6993
6994                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
6995                                       (uint32_t)(inset_reg & UINT32_MAX));
6996                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
6997                                      (uint32_t)((inset_reg >>
6998                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
6999         } else {
7000                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7001                 return -EINVAL;
7002         }
7003         I40E_WRITE_FLUSH(hw);
7004
7005         return 0;
7006 }
7007
7008 static int
7009 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7010 {
7011         int ret = 0;
7012
7013         if (!hw || !info) {
7014                 PMD_DRV_LOG(ERR, "Invalid pointer");
7015                 return -EFAULT;
7016         }
7017
7018         switch (info->info_type) {
7019         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7020                 i40e_get_symmetric_hash_enable_per_port(hw,
7021                                         &(info->info.enable));
7022                 break;
7023         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7024                 ret = i40e_get_hash_filter_global_config(hw,
7025                                 &(info->info.global_conf));
7026                 break;
7027         default:
7028                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7029                                                         info->info_type);
7030                 ret = -EINVAL;
7031                 break;
7032         }
7033
7034         return ret;
7035 }
7036
7037 static int
7038 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7039 {
7040         int ret = 0;
7041
7042         if (!hw || !info) {
7043                 PMD_DRV_LOG(ERR, "Invalid pointer");
7044                 return -EFAULT;
7045         }
7046
7047         switch (info->info_type) {
7048         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7049                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7050                 break;
7051         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7052                 ret = i40e_set_hash_filter_global_config(hw,
7053                                 &(info->info.global_conf));
7054                 break;
7055         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7056                 ret = i40e_filter_inset_select(hw,
7057                                                &(info->info.input_set_conf),
7058                                                RTE_ETH_FILTER_HASH);
7059                 break;
7060
7061         default:
7062                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7063                                                         info->info_type);
7064                 ret = -EINVAL;
7065                 break;
7066         }
7067
7068         return ret;
7069 }
7070
7071 /* Operations for hash function */
7072 static int
7073 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7074                       enum rte_filter_op filter_op,
7075                       void *arg)
7076 {
7077         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7078         int ret = 0;
7079
7080         switch (filter_op) {
7081         case RTE_ETH_FILTER_NOP:
7082                 break;
7083         case RTE_ETH_FILTER_GET:
7084                 ret = i40e_hash_filter_get(hw,
7085                         (struct rte_eth_hash_filter_info *)arg);
7086                 break;
7087         case RTE_ETH_FILTER_SET:
7088                 ret = i40e_hash_filter_set(hw,
7089                         (struct rte_eth_hash_filter_info *)arg);
7090                 break;
7091         default:
7092                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7093                                                                 filter_op);
7094                 ret = -ENOTSUP;
7095                 break;
7096         }
7097
7098         return ret;
7099 }
7100
7101 /*
7102  * Configure ethertype filter, which can director packet by filtering
7103  * with mac address and ether_type or only ether_type
7104  */
7105 static int
7106 i40e_ethertype_filter_set(struct i40e_pf *pf,
7107                         struct rte_eth_ethertype_filter *filter,
7108                         bool add)
7109 {
7110         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7111         struct i40e_control_filter_stats stats;
7112         uint16_t flags = 0;
7113         int ret;
7114
7115         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7116                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7117                 return -EINVAL;
7118         }
7119         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7120                 filter->ether_type == ETHER_TYPE_IPv6) {
7121                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7122                         " control packet filter.", filter->ether_type);
7123                 return -EINVAL;
7124         }
7125         if (filter->ether_type == ETHER_TYPE_VLAN)
7126                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7127                         " not supported.");
7128
7129         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7130                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7131         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7132                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7133         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7134
7135         memset(&stats, 0, sizeof(stats));
7136         ret = i40e_aq_add_rem_control_packet_filter(hw,
7137                         filter->mac_addr.addr_bytes,
7138                         filter->ether_type, flags,
7139                         pf->main_vsi->seid,
7140                         filter->queue, add, &stats, NULL);
7141
7142         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7143                          " mac_etype_used = %u, etype_used = %u,"
7144                          " mac_etype_free = %u, etype_free = %u\n",
7145                          ret, stats.mac_etype_used, stats.etype_used,
7146                          stats.mac_etype_free, stats.etype_free);
7147         if (ret < 0)
7148                 return -ENOSYS;
7149         return 0;
7150 }
7151
7152 /*
7153  * Handle operations for ethertype filter.
7154  */
7155 static int
7156 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7157                                 enum rte_filter_op filter_op,
7158                                 void *arg)
7159 {
7160         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7161         int ret = 0;
7162
7163         if (filter_op == RTE_ETH_FILTER_NOP)
7164                 return ret;
7165
7166         if (arg == NULL) {
7167                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7168                             filter_op);
7169                 return -EINVAL;
7170         }
7171
7172         switch (filter_op) {
7173         case RTE_ETH_FILTER_ADD:
7174                 ret = i40e_ethertype_filter_set(pf,
7175                         (struct rte_eth_ethertype_filter *)arg,
7176                         TRUE);
7177                 break;
7178         case RTE_ETH_FILTER_DELETE:
7179                 ret = i40e_ethertype_filter_set(pf,
7180                         (struct rte_eth_ethertype_filter *)arg,
7181                         FALSE);
7182                 break;
7183         default:
7184                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7185                 ret = -ENOSYS;
7186                 break;
7187         }
7188         return ret;
7189 }
7190
7191 static int
7192 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7193                      enum rte_filter_type filter_type,
7194                      enum rte_filter_op filter_op,
7195                      void *arg)
7196 {
7197         int ret = 0;
7198
7199         if (dev == NULL)
7200                 return -EINVAL;
7201
7202         switch (filter_type) {
7203         case RTE_ETH_FILTER_NONE:
7204                 /* For global configuration */
7205                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7206                 break;
7207         case RTE_ETH_FILTER_HASH:
7208                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7209                 break;
7210         case RTE_ETH_FILTER_MACVLAN:
7211                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7212                 break;
7213         case RTE_ETH_FILTER_ETHERTYPE:
7214                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7215                 break;
7216         case RTE_ETH_FILTER_TUNNEL:
7217                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7218                 break;
7219         case RTE_ETH_FILTER_FDIR:
7220                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7221                 break;
7222         default:
7223                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7224                                                         filter_type);
7225                 ret = -EINVAL;
7226                 break;
7227         }
7228
7229         return ret;
7230 }
7231
7232 /*
7233  * As some registers wouldn't be reset unless a global hardware reset,
7234  * hardware initialization is needed to put those registers into an
7235  * expected initial state.
7236  */
7237 static void
7238 i40e_hw_init(struct i40e_hw *hw)
7239 {
7240         /* clear the PF Queue Filter control register */
7241         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
7242
7243         /* Disable symmetric hash per port */
7244         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7245 }
7246
7247 enum i40e_filter_pctype
7248 i40e_flowtype_to_pctype(uint16_t flow_type)
7249 {
7250         static const enum i40e_filter_pctype pctype_table[] = {
7251                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7252                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7253                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7254                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7255                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7256                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7257                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7258                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7259                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7260                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7261                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7262                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7263                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7264                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7265                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7266                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7267                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7268                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7269                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7270         };
7271
7272         return pctype_table[flow_type];
7273 }
7274
7275 uint16_t
7276 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7277 {
7278         static const uint16_t flowtype_table[] = {
7279                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7280                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7281                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7282                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7283                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7284                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7285                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7286                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7287                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7288                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7289                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7290                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7291                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7292                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7293                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7294                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7295                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7296                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7297                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7298         };
7299
7300         return flowtype_table[pctype];
7301 }
7302
7303 /*
7304  * On X710, performance number is far from the expectation on recent firmware
7305  * versions; on XL710, performance number is also far from the expectation on
7306  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7307  * mode is enabled and port MAC address is equal to the packet destination MAC
7308  * address. The fix for this issue may not be integrated in the following
7309  * firmware version. So the workaround in software driver is needed. It needs
7310  * to modify the initial values of 3 internal only registers for both X710 and
7311  * XL710. Note that the values for X710 or XL710 could be different, and the
7312  * workaround can be removed when it is fixed in firmware in the future.
7313  */
7314
7315 /* For both X710 and XL710 */
7316 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7317 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7318
7319 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7320 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7321
7322 /* For X710 */
7323 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7324 /* For XL710 */
7325 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7326 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7327
7328 static void
7329 i40e_configure_registers(struct i40e_hw *hw)
7330 {
7331         static struct {
7332                 uint32_t addr;
7333                 uint64_t val;
7334         } reg_table[] = {
7335                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7336                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7337                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7338         };
7339         uint64_t reg;
7340         uint32_t i;
7341         int ret;
7342
7343         for (i = 0; i < RTE_DIM(reg_table); i++) {
7344                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7345                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7346                                 reg_table[i].val =
7347                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7348                         else /* For X710 */
7349                                 reg_table[i].val =
7350                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7351                 }
7352
7353                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7354                                                         &reg, NULL);
7355                 if (ret < 0) {
7356                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7357                                                         reg_table[i].addr);
7358                         break;
7359                 }
7360                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7361                                                 reg_table[i].addr, reg);
7362                 if (reg == reg_table[i].val)
7363                         continue;
7364
7365                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7366                                                 reg_table[i].val, NULL);
7367                 if (ret < 0) {
7368                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7369                                 "address of 0x%"PRIx32, reg_table[i].val,
7370                                                         reg_table[i].addr);
7371                         break;
7372                 }
7373                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7374                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7375         }
7376 }
7377
7378 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7379 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7380 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7381 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7382 static int
7383 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7384 {
7385         uint32_t reg;
7386         int ret;
7387
7388         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7389                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7390                 return -EINVAL;
7391         }
7392
7393         /* Configure for double VLAN RX stripping */
7394         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7395         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7396                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7397                 ret = i40e_aq_debug_write_register(hw,
7398                                                    I40E_VSI_TSR(vsi->vsi_id),
7399                                                    reg, NULL);
7400                 if (ret < 0) {
7401                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7402                                     vsi->vsi_id);
7403                         return I40E_ERR_CONFIG;
7404                 }
7405         }
7406
7407         /* Configure for double VLAN TX insertion */
7408         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7409         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7410                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7411                 ret = i40e_aq_debug_write_register(hw,
7412                                                    I40E_VSI_L2TAGSTXVALID(
7413                                                    vsi->vsi_id), reg, NULL);
7414                 if (ret < 0) {
7415                         PMD_DRV_LOG(ERR, "Failed to update "
7416                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7417                         return I40E_ERR_CONFIG;
7418                 }
7419         }
7420
7421         return 0;
7422 }
7423
7424 /**
7425  * i40e_aq_add_mirror_rule
7426  * @hw: pointer to the hardware structure
7427  * @seid: VEB seid to add mirror rule to
7428  * @dst_id: destination vsi seid
7429  * @entries: Buffer which contains the entities to be mirrored
7430  * @count: number of entities contained in the buffer
7431  * @rule_id:the rule_id of the rule to be added
7432  *
7433  * Add a mirror rule for a given veb.
7434  *
7435  **/
7436 static enum i40e_status_code
7437 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7438                         uint16_t seid, uint16_t dst_id,
7439                         uint16_t rule_type, uint16_t *entries,
7440                         uint16_t count, uint16_t *rule_id)
7441 {
7442         struct i40e_aq_desc desc;
7443         struct i40e_aqc_add_delete_mirror_rule cmd;
7444         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7445                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7446                 &desc.params.raw;
7447         uint16_t buff_len;
7448         enum i40e_status_code status;
7449
7450         i40e_fill_default_direct_cmd_desc(&desc,
7451                                           i40e_aqc_opc_add_mirror_rule);
7452         memset(&cmd, 0, sizeof(cmd));
7453
7454         buff_len = sizeof(uint16_t) * count;
7455         desc.datalen = rte_cpu_to_le_16(buff_len);
7456         if (buff_len > 0)
7457                 desc.flags |= rte_cpu_to_le_16(
7458                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7459         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7460                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7461         cmd.num_entries = rte_cpu_to_le_16(count);
7462         cmd.seid = rte_cpu_to_le_16(seid);
7463         cmd.destination = rte_cpu_to_le_16(dst_id);
7464
7465         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7466         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7467         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7468                          "rule_id = %u"
7469                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7470                          hw->aq.asq_last_status, resp->rule_id,
7471                          resp->mirror_rules_used, resp->mirror_rules_free);
7472         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7473
7474         return status;
7475 }
7476
7477 /**
7478  * i40e_aq_del_mirror_rule
7479  * @hw: pointer to the hardware structure
7480  * @seid: VEB seid to add mirror rule to
7481  * @entries: Buffer which contains the entities to be mirrored
7482  * @count: number of entities contained in the buffer
7483  * @rule_id:the rule_id of the rule to be delete
7484  *
7485  * Delete a mirror rule for a given veb.
7486  *
7487  **/
7488 static enum i40e_status_code
7489 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7490                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7491                 uint16_t count, uint16_t rule_id)
7492 {
7493         struct i40e_aq_desc desc;
7494         struct i40e_aqc_add_delete_mirror_rule cmd;
7495         uint16_t buff_len = 0;
7496         enum i40e_status_code status;
7497         void *buff = NULL;
7498
7499         i40e_fill_default_direct_cmd_desc(&desc,
7500                                           i40e_aqc_opc_delete_mirror_rule);
7501         memset(&cmd, 0, sizeof(cmd));
7502         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7503                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7504                                                           I40E_AQ_FLAG_RD));
7505                 cmd.num_entries = count;
7506                 buff_len = sizeof(uint16_t) * count;
7507                 desc.datalen = rte_cpu_to_le_16(buff_len);
7508                 buff = (void *)entries;
7509         } else
7510                 /* rule id is filled in destination field for deleting mirror rule */
7511                 cmd.destination = rte_cpu_to_le_16(rule_id);
7512
7513         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7514                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7515         cmd.seid = rte_cpu_to_le_16(seid);
7516
7517         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7518         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7519
7520         return status;
7521 }
7522
7523 /**
7524  * i40e_mirror_rule_set
7525  * @dev: pointer to the hardware structure
7526  * @mirror_conf: mirror rule info
7527  * @sw_id: mirror rule's sw_id
7528  * @on: enable/disable
7529  *
7530  * set a mirror rule.
7531  *
7532  **/
7533 static int
7534 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7535                         struct rte_eth_mirror_conf *mirror_conf,
7536                         uint8_t sw_id, uint8_t on)
7537 {
7538         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7539         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7540         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7541         struct i40e_mirror_rule *parent = NULL;
7542         uint16_t seid, dst_seid, rule_id;
7543         uint16_t i, j = 0;
7544         int ret;
7545
7546         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7547
7548         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7549                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7550                         " without veb or vfs.");
7551                 return -ENOSYS;
7552         }
7553         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7554                 PMD_DRV_LOG(ERR, "mirror table is full.");
7555                 return -ENOSPC;
7556         }
7557         if (mirror_conf->dst_pool > pf->vf_num) {
7558                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7559                                  mirror_conf->dst_pool);
7560                 return -EINVAL;
7561         }
7562
7563         seid = pf->main_vsi->veb->seid;
7564
7565         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7566                 if (sw_id <= it->index) {
7567                         mirr_rule = it;
7568                         break;
7569                 }
7570                 parent = it;
7571         }
7572         if (mirr_rule && sw_id == mirr_rule->index) {
7573                 if (on) {
7574                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7575                         return -EEXIST;
7576                 } else {
7577                         ret = i40e_aq_del_mirror_rule(hw, seid,
7578                                         mirr_rule->rule_type,
7579                                         mirr_rule->entries,
7580                                         mirr_rule->num_entries, mirr_rule->id);
7581                         if (ret < 0) {
7582                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7583                                                    " ret = %d, aq_err = %d.",
7584                                                    ret, hw->aq.asq_last_status);
7585                                 return -ENOSYS;
7586                         }
7587                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7588                         rte_free(mirr_rule);
7589                         pf->nb_mirror_rule--;
7590                         return 0;
7591                 }
7592         } else if (!on) {
7593                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7594                 return -ENOENT;
7595         }
7596
7597         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7598                                 sizeof(struct i40e_mirror_rule) , 0);
7599         if (!mirr_rule) {
7600                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7601                 return I40E_ERR_NO_MEMORY;
7602         }
7603         switch (mirror_conf->rule_type) {
7604         case ETH_MIRROR_VLAN:
7605                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7606                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7607                                 mirr_rule->entries[j] =
7608                                         mirror_conf->vlan.vlan_id[i];
7609                                 j++;
7610                         }
7611                 }
7612                 if (j == 0) {
7613                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7614                         rte_free(mirr_rule);
7615                         return -EINVAL;
7616                 }
7617                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7618                 break;
7619         case ETH_MIRROR_VIRTUAL_POOL_UP:
7620         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7621                 /* check if the specified pool bit is out of range */
7622                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7623                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7624                         rte_free(mirr_rule);
7625                         return -EINVAL;
7626                 }
7627                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7628                         if (mirror_conf->pool_mask & (1ULL << i)) {
7629                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7630                                 j++;
7631                         }
7632                 }
7633                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7634                         /* add pf vsi to entries */
7635                         mirr_rule->entries[j] = pf->main_vsi_seid;
7636                         j++;
7637                 }
7638                 if (j == 0) {
7639                         PMD_DRV_LOG(ERR, "pool is not specified.");
7640                         rte_free(mirr_rule);
7641                         return -EINVAL;
7642                 }
7643                 /* egress and ingress in aq commands means from switch but not port */
7644                 mirr_rule->rule_type =
7645                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7646                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7647                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7648                 break;
7649         case ETH_MIRROR_UPLINK_PORT:
7650                 /* egress and ingress in aq commands means from switch but not port*/
7651                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7652                 break;
7653         case ETH_MIRROR_DOWNLINK_PORT:
7654                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7655                 break;
7656         default:
7657                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7658                         mirror_conf->rule_type);
7659                 rte_free(mirr_rule);
7660                 return -EINVAL;
7661         }
7662
7663         /* If the dst_pool is equal to vf_num, consider it as PF */
7664         if (mirror_conf->dst_pool == pf->vf_num)
7665                 dst_seid = pf->main_vsi_seid;
7666         else
7667                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7668
7669         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7670                                       mirr_rule->rule_type, mirr_rule->entries,
7671                                       j, &rule_id);
7672         if (ret < 0) {
7673                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7674                                    " ret = %d, aq_err = %d.",
7675                                    ret, hw->aq.asq_last_status);
7676                 rte_free(mirr_rule);
7677                 return -ENOSYS;
7678         }
7679
7680         mirr_rule->index = sw_id;
7681         mirr_rule->num_entries = j;
7682         mirr_rule->id = rule_id;
7683         mirr_rule->dst_vsi_seid = dst_seid;
7684
7685         if (parent)
7686                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7687         else
7688                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7689
7690         pf->nb_mirror_rule++;
7691         return 0;
7692 }
7693
7694 /**
7695  * i40e_mirror_rule_reset
7696  * @dev: pointer to the device
7697  * @sw_id: mirror rule's sw_id
7698  *
7699  * reset a mirror rule.
7700  *
7701  **/
7702 static int
7703 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7704 {
7705         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7706         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7707         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7708         uint16_t seid;
7709         int ret;
7710
7711         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7712
7713         seid = pf->main_vsi->veb->seid;
7714
7715         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7716                 if (sw_id == it->index) {
7717                         mirr_rule = it;
7718                         break;
7719                 }
7720         }
7721         if (mirr_rule) {
7722                 ret = i40e_aq_del_mirror_rule(hw, seid,
7723                                 mirr_rule->rule_type,
7724                                 mirr_rule->entries,
7725                                 mirr_rule->num_entries, mirr_rule->id);
7726                 if (ret < 0) {
7727                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7728                                            " status = %d, aq_err = %d.",
7729                                            ret, hw->aq.asq_last_status);
7730                         return -ENOSYS;
7731                 }
7732                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7733                 rte_free(mirr_rule);
7734                 pf->nb_mirror_rule--;
7735         } else {
7736                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7737                 return -ENOENT;
7738         }
7739         return 0;
7740 }
7741
7742 static int
7743 i40e_timesync_enable(struct rte_eth_dev *dev)
7744 {
7745         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7746         struct rte_eth_link *link = &dev->data->dev_link;
7747         uint32_t tsync_ctl_l;
7748         uint32_t tsync_ctl_h;
7749         uint32_t tsync_inc_l;
7750         uint32_t tsync_inc_h;
7751
7752         switch (link->link_speed) {
7753         case ETH_LINK_SPEED_40G:
7754                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
7755                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
7756                 break;
7757         case ETH_LINK_SPEED_10G:
7758                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
7759                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
7760                 break;
7761         case ETH_LINK_SPEED_1000:
7762                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
7763                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
7764                 break;
7765         default:
7766                 tsync_inc_l = 0x0;
7767                 tsync_inc_h = 0x0;
7768         }
7769
7770         /* Clear timesync registers. */
7771         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7772         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7773         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
7774         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
7775         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
7776         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
7777         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7778
7779         /* Set the timesync increment value. */
7780         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
7781         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
7782
7783         /* Enable timestamping of PTP packets. */
7784         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7785         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
7786
7787         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7788         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
7789         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
7790
7791         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7792         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7793
7794         return 0;
7795 }
7796
7797 static int
7798 i40e_timesync_disable(struct rte_eth_dev *dev)
7799 {
7800         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7801         uint32_t tsync_ctl_l;
7802         uint32_t tsync_ctl_h;
7803
7804         /* Disable timestamping of transmitted PTP packets. */
7805         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7806         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
7807
7808         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7809         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
7810
7811         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7812         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7813
7814         /* Set the timesync increment value. */
7815         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7816         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7817
7818         return 0;
7819 }
7820
7821 static int
7822 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7823                                 struct timespec *timestamp, uint32_t flags)
7824 {
7825         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7826         uint32_t sync_status;
7827         uint32_t rx_stmpl;
7828         uint32_t rx_stmph;
7829         uint32_t index = flags & 0x03;
7830
7831         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
7832         if ((sync_status & (1 << index)) == 0)
7833                 return -EINVAL;
7834
7835         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7836         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
7837
7838         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
7839         timestamp->tv_nsec = 0;
7840
7841         return  0;
7842 }
7843
7844 static int
7845 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7846                                 struct timespec *timestamp)
7847 {
7848         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7849         uint32_t sync_status;
7850         uint32_t tx_stmpl;
7851         uint32_t tx_stmph;
7852
7853         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7854         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
7855                 return -EINVAL;
7856
7857         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
7858         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7859
7860         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
7861         timestamp->tv_nsec = 0;
7862
7863         return  0;
7864 }
7865
7866 /*
7867  * i40e_parse_dcb_configure - parse dcb configure from user
7868  * @dev: the device being configured
7869  * @dcb_cfg: pointer of the result of parse
7870  * @*tc_map: bit map of enabled traffic classes
7871  *
7872  * Returns 0 on success, negative value on failure
7873  */
7874 static int
7875 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
7876                          struct i40e_dcbx_config *dcb_cfg,
7877                          uint8_t *tc_map)
7878 {
7879         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
7880         uint8_t i, tc_bw, bw_lf;
7881
7882         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
7883
7884         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7885         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
7886                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
7887                 return -EINVAL;
7888         }
7889
7890         /* assume each tc has the same bw */
7891         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
7892         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7893                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
7894         /* to ensure the sum of tcbw is equal to 100 */
7895         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
7896         for (i = 0; i < bw_lf; i++)
7897                 dcb_cfg->etscfg.tcbwtable[i]++;
7898
7899         /* assume each tc has the same Transmission Selection Algorithm */
7900         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7901                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
7902
7903         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
7904                 dcb_cfg->etscfg.prioritytable[i] =
7905                                 dcb_rx_conf->dcb_tc[i];
7906
7907         /* FW needs one App to configure HW */
7908         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
7909         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
7910         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
7911         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
7912
7913         if (dcb_rx_conf->nb_tcs == 0)
7914                 *tc_map = 1; /* tc0 only */
7915         else
7916                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
7917
7918         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
7919                 dcb_cfg->pfc.willing = 0;
7920                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
7921                 dcb_cfg->pfc.pfcenable = *tc_map;
7922         }
7923         return 0;
7924 }
7925
7926 /*
7927  * i40e_vsi_get_bw_info - Query VSI BW Information
7928  * @vsi: the VSI being queried
7929  *
7930  * Returns 0 on success, negative value on failure
7931  */
7932 static enum i40e_status_code
7933 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
7934 {
7935         struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
7936         struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
7937         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7938         enum i40e_status_code ret;
7939         int i;
7940         uint32_t tc_bw_max;
7941
7942         /* Get the VSI level BW configuration */
7943         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
7944         if (ret) {
7945                 PMD_INIT_LOG(ERR,
7946                          "couldn't get PF vsi bw config, err %s aq_err %s\n",
7947                          i40e_stat_str(hw, ret),
7948                          i40e_aq_str(hw, hw->aq.asq_last_status));
7949                 return ret;
7950         }
7951
7952         /* Get the VSI level BW configuration per TC */
7953         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
7954                                                   NULL);
7955         if (ret) {
7956                 PMD_INIT_LOG(ERR,
7957                          "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
7958                          i40e_stat_str(hw, ret),
7959                          i40e_aq_str(hw, hw->aq.asq_last_status));
7960                 return ret;
7961         }
7962
7963         if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
7964                 PMD_INIT_LOG(WARNING,
7965                          "Enabled TCs mismatch from querying VSI BW info"
7966                          " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
7967                          bw_ets_config.tc_valid_bits);
7968                 /* Still continuing */
7969         }
7970
7971         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
7972         vsi->bw_info.bw_max_quanta = bw_config.max_bw;
7973         tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
7974                     (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
7975         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7976                 vsi->bw_info.bw_ets_share_credits[i] =
7977                                 bw_ets_config.share_credits[i];
7978                 vsi->bw_info.bw_ets_limit_credits[i] =
7979                                 rte_le_to_cpu_16(bw_ets_config.credits[i]);
7980                 /* 3 bits out of 4 for each TC */
7981                 vsi->bw_info.bw_ets_max_quanta[i] =
7982                         (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
7983                 PMD_INIT_LOG(DEBUG,
7984                          "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
7985                          __func__, vsi->seid, i, bw_config.qs_handles[i]);
7986         }
7987
7988         return ret;
7989 }
7990
7991 static enum i40e_status_code
7992 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
7993                               struct i40e_aqc_vsi_properties_data *info,
7994                               uint8_t enabled_tcmap)
7995 {
7996         enum i40e_status_code ret;
7997         int i, total_tc = 0;
7998         uint16_t qpnum_per_tc, bsf, qp_idx;
7999         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8000
8001         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8002         if (ret != I40E_SUCCESS)
8003                 return ret;
8004
8005         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8006                 if (enabled_tcmap & (1 << i))
8007                         total_tc++;
8008         }
8009         if (total_tc == 0)
8010                 total_tc = 1;
8011         vsi->enabled_tc = enabled_tcmap;
8012
8013         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
8014         /* Number of queues per enabled TC */
8015         if (qpnum_per_tc == 0) {
8016                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8017                 return I40E_ERR_INVALID_QP_ID;
8018         }
8019         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8020                                 I40E_MAX_Q_PER_TC);
8021         bsf = rte_bsf32(qpnum_per_tc);
8022
8023         /**
8024          * Configure TC and queue mapping parameters, for enabled TC,
8025          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8026          * default queue will serve it.
8027          */
8028         qp_idx = 0;
8029         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8030                 if (vsi->enabled_tc & (1 << i)) {
8031                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8032                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8033                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8034                         qp_idx += qpnum_per_tc;
8035                 } else
8036                         info->tc_mapping[i] = 0;
8037         }
8038
8039         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8040         if (vsi->type == I40E_VSI_SRIOV) {
8041                 info->mapping_flags |=
8042                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8043                 for (i = 0; i < vsi->nb_qps; i++)
8044                         info->queue_mapping[i] =
8045                                 rte_cpu_to_le_16(vsi->base_queue + i);
8046         } else {
8047                 info->mapping_flags |=
8048                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8049                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8050         }
8051         info->valid_sections |=
8052                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8053
8054         return I40E_SUCCESS;
8055 }
8056
8057 /*
8058  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8059  * @vsi: VSI to be configured
8060  * @tc_map: enabled TC bitmap
8061  *
8062  * Returns 0 on success, negative value on failure
8063  */
8064 static enum i40e_status_code
8065 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
8066 {
8067         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8068         struct i40e_vsi_context ctxt;
8069         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8070         enum i40e_status_code ret = I40E_SUCCESS;
8071         int i;
8072
8073         /* Check if enabled_tc is same as existing or new TCs */
8074         if (vsi->enabled_tc == tc_map)
8075                 return ret;
8076
8077         /* configure tc bandwidth */
8078         memset(&bw_data, 0, sizeof(bw_data));
8079         bw_data.tc_valid_bits = tc_map;
8080         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8081         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8082                 if (tc_map & BIT_ULL(i))
8083                         bw_data.tc_bw_credits[i] = 1;
8084         }
8085         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8086         if (ret) {
8087                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8088                         " per TC failed = %d",
8089                         hw->aq.asq_last_status);
8090                 goto out;
8091         }
8092         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8093                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8094
8095         /* Update Queue Pairs Mapping for currently enabled UPs */
8096         ctxt.seid = vsi->seid;
8097         ctxt.pf_num = hw->pf_id;
8098         ctxt.vf_num = 0;
8099         ctxt.uplink_seid = vsi->uplink_seid;
8100         ctxt.info = vsi->info;
8101         i40e_get_cap(hw);
8102         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8103         if (ret)
8104                 goto out;
8105
8106         /* Update the VSI after updating the VSI queue-mapping information */
8107         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8108         if (ret) {
8109                 PMD_INIT_LOG(ERR, "Failed to configure "
8110                             "TC queue mapping = %d",
8111                             hw->aq.asq_last_status);
8112                 goto out;
8113         }
8114         /* update the local VSI info with updated queue map */
8115         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8116                                         sizeof(vsi->info.tc_mapping));
8117         (void)rte_memcpy(&vsi->info.queue_mapping,
8118                         &ctxt.info.queue_mapping,
8119                 sizeof(vsi->info.queue_mapping));
8120         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8121         vsi->info.valid_sections = 0;
8122
8123         /* Update current VSI BW information */
8124         ret = i40e_vsi_get_bw_info(vsi);
8125         if (ret) {
8126                 PMD_INIT_LOG(ERR,
8127                          "Failed updating vsi bw info, err %s aq_err %s",
8128                          i40e_stat_str(hw, ret),
8129                          i40e_aq_str(hw, hw->aq.asq_last_status));
8130                 goto out;
8131         }
8132
8133         vsi->enabled_tc = tc_map;
8134
8135 out:
8136         return ret;
8137 }
8138
8139 /*
8140  * i40e_dcb_hw_configure - program the dcb setting to hw
8141  * @pf: pf the configuration is taken on
8142  * @new_cfg: new configuration
8143  * @tc_map: enabled TC bitmap
8144  *
8145  * Returns 0 on success, negative value on failure
8146  */
8147 static enum i40e_status_code
8148 i40e_dcb_hw_configure(struct i40e_pf *pf,
8149                       struct i40e_dcbx_config *new_cfg,
8150                       uint8_t tc_map)
8151 {
8152         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8153         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8154         struct i40e_vsi *main_vsi = pf->main_vsi;
8155         struct i40e_vsi_list *vsi_list;
8156         enum i40e_status_code ret;
8157         int i;
8158         uint32_t val;
8159
8160         /* Use the FW API if FW > v4.4*/
8161         if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
8162                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8163                                   " to configure DCB");
8164                 return I40E_ERR_FIRMWARE_API_VERSION;
8165         }
8166
8167         /* Check if need reconfiguration */
8168         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8169                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8170                 return I40E_SUCCESS;
8171         }
8172
8173         /* Copy the new config to the current config */
8174         *old_cfg = *new_cfg;
8175         old_cfg->etsrec = old_cfg->etscfg;
8176         ret = i40e_set_dcb_config(hw);
8177         if (ret) {
8178                 PMD_INIT_LOG(ERR,
8179                          "Set DCB Config failed, err %s aq_err %s\n",
8180                          i40e_stat_str(hw, ret),
8181                          i40e_aq_str(hw, hw->aq.asq_last_status));
8182                 return ret;
8183         }
8184         /* set receive Arbiter to RR mode and ETS scheme by default */
8185         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8186                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8187                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8188                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8189                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8190                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8191                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8192                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8193                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8194                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8195                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8196                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8197                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8198         }
8199         /* get local mib to check whether it is configured correctly */
8200         /* IEEE mode */
8201         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8202         /* Get Local DCB Config */
8203         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8204                                      &hw->local_dcbx_config);
8205
8206         /* Update each VSI */
8207         i40e_vsi_config_tc(main_vsi, tc_map);
8208         if (main_vsi->veb) {
8209                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8210                         /* Beside main VSI, only enable default
8211                          * TC for other VSIs
8212                          */
8213                         ret = i40e_vsi_config_tc(vsi_list->vsi,
8214                                                 I40E_DEFAULT_TCMAP);
8215                         if (ret)
8216                                 PMD_INIT_LOG(WARNING,
8217                                          "Failed configuring TC for VSI seid=%d\n",
8218                                          vsi_list->vsi->seid);
8219                         /* continue */
8220                 }
8221         }
8222         return I40E_SUCCESS;
8223 }
8224
8225 /*
8226  * i40e_dcb_init_configure - initial dcb config
8227  * @dev: device being configured
8228  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8229  *
8230  * Returns 0 on success, negative value on failure
8231  */
8232 static int
8233 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8234 {
8235         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8236         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8237         int ret = 0;
8238
8239         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8240                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8241                 return -ENOTSUP;
8242         }
8243
8244         /* DCB initialization:
8245          * Update DCB configuration from the Firmware and configure
8246          * LLDP MIB change event.
8247          */
8248         if (sw_dcb == TRUE) {
8249                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8250                 if (ret != I40E_SUCCESS)
8251                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8252
8253                 ret = i40e_init_dcb(hw);
8254                 /* if sw_dcb, lldp agent is stopped, the return from
8255                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8256                  * adminq status.
8257                  */
8258                 if (ret != I40E_SUCCESS &&
8259                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8260                         memset(&hw->local_dcbx_config, 0,
8261                                 sizeof(struct i40e_dcbx_config));
8262                         /* set dcb default configuration */
8263                         hw->local_dcbx_config.etscfg.willing = 0;
8264                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8265                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8266                         hw->local_dcbx_config.etscfg.tsatable[0] =
8267                                                 I40E_IEEE_TSA_ETS;
8268                         hw->local_dcbx_config.etsrec =
8269                                 hw->local_dcbx_config.etscfg;
8270                         hw->local_dcbx_config.pfc.willing = 0;
8271                         hw->local_dcbx_config.pfc.pfccap =
8272                                                 I40E_MAX_TRAFFIC_CLASS;
8273                         /* FW needs one App to configure HW */
8274                         hw->local_dcbx_config.numapps = 1;
8275                         hw->local_dcbx_config.app[0].selector =
8276                                                 I40E_APP_SEL_ETHTYPE;
8277                         hw->local_dcbx_config.app[0].priority = 3;
8278                         hw->local_dcbx_config.app[0].protocolid =
8279                                                 I40E_APP_PROTOID_FCOE;
8280                         ret = i40e_set_dcb_config(hw);
8281                         if (ret) {
8282                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8283                                         " err = %d, aq_err = %d.", ret,
8284                                           hw->aq.asq_last_status);
8285                                 return -ENOSYS;
8286                         }
8287                 } else {
8288                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8289                                           " aq_err = %d.", ret,
8290                                           hw->aq.asq_last_status);
8291                         return -ENOTSUP;
8292                 }
8293         } else {
8294                 ret = i40e_aq_start_lldp(hw, NULL);
8295                 if (ret != I40E_SUCCESS)
8296                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8297
8298                 ret = i40e_init_dcb(hw);
8299                 if (!ret) {
8300                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8301                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8302                                                   " DCBX offload.");
8303                                 return -ENOTSUP;
8304                         }
8305                 } else {
8306                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8307                                           " aq_err = %d.", ret,
8308                                           hw->aq.asq_last_status);
8309                         return -ENOTSUP;
8310                 }
8311         }
8312         return 0;
8313 }
8314
8315 /*
8316  * i40e_dcb_setup - setup dcb related config
8317  * @dev: device being configured
8318  *
8319  * Returns 0 on success, negative value on failure
8320  */
8321 static int
8322 i40e_dcb_setup(struct rte_eth_dev *dev)
8323 {
8324         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8325         struct i40e_dcbx_config dcb_cfg;
8326         uint8_t tc_map = 0;
8327         int ret = 0;
8328
8329         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8330                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8331                 return -ENOTSUP;
8332         }
8333
8334         if (pf->vf_num != 0 ||
8335             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8336                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8337
8338         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8339         if (ret) {
8340                 PMD_INIT_LOG(ERR, "invalid dcb config");
8341                 return -EINVAL;
8342         }
8343         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8344         if (ret) {
8345                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8346                 return -ENOSYS;
8347         }
8348
8349         return 0;
8350 }
8351
8352 static int
8353 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8354                       struct rte_eth_dcb_info *dcb_info)
8355 {
8356         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8357         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8358         struct i40e_vsi *vsi = pf->main_vsi;
8359         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8360         uint16_t bsf, tc_mapping;
8361         int i;
8362
8363         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8364                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8365         else
8366                 dcb_info->nb_tcs = 1;
8367         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8368                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8369         for (i = 0; i < dcb_info->nb_tcs; i++)
8370                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8371
8372         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8373                 if (vsi->enabled_tc & (1 << i)) {
8374                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8375                         /* only main vsi support multi TCs */
8376                         dcb_info->tc_queue.tc_rxq[0][i].base =
8377                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8378                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8379                         dcb_info->tc_queue.tc_txq[0][i].base =
8380                                 dcb_info->tc_queue.tc_rxq[0][i].base;
8381                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8382                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8383                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8384                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8385                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
8386                 }
8387         }
8388
8389         return 0;
8390 }
8391
8392 static int
8393 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8394 {
8395         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8396         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8397         uint16_t interval =
8398                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8399         uint16_t msix_intr;
8400
8401         msix_intr = intr_handle->intr_vec[queue_id];
8402         if (msix_intr == I40E_MISC_VEC_ID)
8403                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8404                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8405                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8406                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8407                                (interval <<
8408                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8409         else
8410                 I40E_WRITE_REG(hw,
8411                                I40E_PFINT_DYN_CTLN(msix_intr -
8412                                                    I40E_RX_VEC_START),
8413                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8414                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8415                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8416                                (interval <<
8417                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8418
8419         I40E_WRITE_FLUSH(hw);
8420         rte_intr_enable(&dev->pci_dev->intr_handle);
8421
8422         return 0;
8423 }
8424
8425 static int
8426 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8427 {
8428         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8429         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8430         uint16_t msix_intr;
8431
8432         msix_intr = intr_handle->intr_vec[queue_id];
8433         if (msix_intr == I40E_MISC_VEC_ID)
8434                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8435         else
8436                 I40E_WRITE_REG(hw,
8437                                I40E_PFINT_DYN_CTLN(msix_intr -
8438                                                    I40E_RX_VEC_START),
8439                                0);
8440         I40E_WRITE_FLUSH(hw);
8441
8442         return 0;
8443 }