drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_eth_ctrl.h>
  28 #include <rte_tailq.h>
  29 #include <rte_hash_crc.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  48
  49 #define I40E_CLEAR_PXE_WAIT_MS     200
  50
  51 /* Maximun number of capability elements */
  52 #define I40E_MAX_CAP_ELE_NUM       128
  53
  54 /* Wait count and interval */
  55 #define I40E_CHK_Q_ENA_COUNT       1000
  56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  57
  58 /* Maximun number of VSI */
  59 #define I40E_MAX_NUM_VSIS          (384UL)
  60
  61 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  62
  63 /* Flow control default timer */
  64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  65
  66 /* Flow control enable fwd bit */
  67 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  68
  69 /* Receive Packet Buffer size */
  70 #define I40E_RXPBSIZE (968 * 1024)
  71
  72 /* Kilobytes shift */
  73 #define I40E_KILOSHIFT 10
  74
  75 /* Flow control default high water */
  76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Flow control default low water */
  79 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  80
  81 /* Receive Average Packet Size in Byte*/
  82 #define I40E_PACKET_AVERAGE_SIZE 128
  83
  84 /* Mask of PF interrupt causes */
  85 #define I40E_PFINT_ICR0_ENA_MASK ( \
  86                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  87                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  90                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 /* Additional timesync values. */
 110 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 111 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 112 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 113 #define I40E_PRTTSYN_TSYNENA     0x80000000
 114 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 115 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 116
 117 /**
 118  * Below are values for writing un-exposed registers suggested
 119  * by silicon experts
 120  */
 121 /* Destination MAC address */
 122 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 123 /* Source MAC address */
 124 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 126 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 128 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 129 /* Single VLAN tag in the inner L2 header */
 130 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 131 /* Source IPv4 address */
 132 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 133 /* Destination IPv4 address */
 134 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 135 /* Source IPv4 address for X722 */
 136 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 137 /* Destination IPv4 address for X722 */
 138 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 139 /* IPv4 Protocol for X722 */
 140 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 141 /* IPv4 Time to Live for X722 */
 142 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 143 /* IPv4 Type of Service (TOS) */
 144 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 145 /* IPv4 Protocol */
 146 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 147 /* IPv4 Time to Live */
 148 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 149 /* Source IPv6 address */
 150 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 151 /* Destination IPv6 address */
 152 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 153 /* IPv6 Traffic Class (TC) */
 154 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 155 /* IPv6 Next Header */
 156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 157 /* IPv6 Hop Limit */
 158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 159 /* Source L4 port */
 160 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 161 /* Destination L4 port */
 162 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 163 /* SCTP verification tag */
 164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 167 /* Source port of tunneling UDP */
 168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 169 /* Destination port of tunneling UDP */
 170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 171 /* UDP Tunneling ID, NVGRE/GRE key */
 172 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 173 /* Last ether type */
 174 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 175 /* Tunneling outer destination IPv4 address */
 176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 177 /* Tunneling outer destination IPv6 address */
 178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 179 /* 1st word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 181 /* 2nd word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 183 /* 3rd word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 185 /* 4th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 187 /* 5th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 189 /* 6th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 191 /* 7th word of flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 193 /* 8th word of flex payload */
 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 195 /* all 8 words flex payload */
 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 197 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 198
 199 #define I40E_TRANSLATE_INSET 0
 200 #define I40E_TRANSLATE_REG   1
 201
 202 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 203 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 204 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 205 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 207 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 208
 209 /* PCI offset for querying capability */
 210 #define PCI_DEV_CAP_REG            0xA4
 211 /* PCI offset for enabling/disabling Extended Tag */
 212 #define PCI_DEV_CTRL_REG           0xA8
 213 /* Bit mask of Extended Tag capability */
 214 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 215 /* Bit shift of Extended Tag enable/disable */
 216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 217 /* Bit mask of Extended Tag enable/disable */
 218 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 219
 220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 222 static int i40e_dev_configure(struct rte_eth_dev *dev);
 223 static int i40e_dev_start(struct rte_eth_dev *dev);
 224 static void i40e_dev_stop(struct rte_eth_dev *dev);
 225 static void i40e_dev_close(struct rte_eth_dev *dev);
 226 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 227 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 228 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 229 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 230 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 234                                struct rte_eth_stats *stats);
 235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 236                                struct rte_eth_xstat *xstats, unsigned n);
 237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 238                                      struct rte_eth_xstat_name *xstats_names,
 239                                      unsigned limit);
 240 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 241 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 242                                             uint16_t queue_id,
 243                                             uint8_t stat_idx,
 244                                             uint8_t is_rx);
 245 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 246                                 char *fw_version, size_t fw_size);
 247 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 248                               struct rte_eth_dev_info *dev_info);
 249 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 250                                 uint16_t vlan_id,
 251                                 int on);
 252 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 253                               enum rte_vlan_type vlan_type,
 254                               uint16_t tpid);
 255 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 256 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 257                                       uint16_t queue,
 258                                       int on);
 259 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 260 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 261 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 262 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 263                               struct rte_eth_fc_conf *fc_conf);
 264 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 265                               struct rte_eth_fc_conf *fc_conf);
 266 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 267                                        struct rte_eth_pfc_conf *pfc_conf);
 268 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 269                             struct ether_addr *mac_addr,
 270                             uint32_t index,
 271                             uint32_t pool);
 272 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 273 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 274                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 275                                     uint16_t reta_size);
 276 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 277                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 278                                    uint16_t reta_size);
 279
 280 static int i40e_get_cap(struct i40e_hw *hw);
 281 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 282 static int i40e_pf_setup(struct i40e_pf *pf);
 283 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 284 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 285 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 286 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 287                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 288 static void i40e_stat_update_48(struct i40e_hw *hw,
 289                                uint32_t hireg,
 290                                uint32_t loreg,
 291                                bool offset_loaded,
 292                                uint64_t *offset,
 293                                uint64_t *stat);
 294 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 295 static void i40e_dev_interrupt_handler(void *param);
 296 static void i40e_dev_alarm_handler(void *param);
 297 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 298                                 uint32_t base, uint32_t num);
 299 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 300 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 301                         uint32_t base);
 302 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 303                         uint16_t num);
 304 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 305 static int i40e_veb_release(struct i40e_veb *veb);
 306 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 307                                                 struct i40e_vsi *vsi);
 308 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 309 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 310 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 311                                              struct i40e_macvlan_filter *mv_f,
 312                                              int num,
 313                                              uint16_t vlan);
 314 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 315 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 316                                     struct rte_eth_rss_conf *rss_conf);
 317 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 318                                       struct rte_eth_rss_conf *rss_conf);
 319 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 320                                         struct rte_eth_udp_tunnel *udp_tunnel);
 321 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 322                                         struct rte_eth_udp_tunnel *udp_tunnel);
 323 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 324 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 328                                 enum rte_filter_type filter_type,
 329                                 enum rte_filter_op filter_op,
 330                                 void *arg);
 331 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 332                                   struct rte_eth_dcb_info *dcb_info);
 333 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 334 static void i40e_configure_registers(struct i40e_hw *hw);
 335 static void i40e_hw_init(struct rte_eth_dev *dev);
 336 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 337 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 338                                                      uint16_t seid,
 339                                                      uint16_t rule_type,
 340                                                      uint16_t *entries,
 341                                                      uint16_t count,
 342                                                      uint16_t rule_id);
 343 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 344                         struct rte_eth_mirror_conf *mirror_conf,
 345                         uint8_t sw_id, uint8_t on);
 346 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 347
 348 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 349 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 350 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 351                                            struct timespec *timestamp,
 352                                            uint32_t flags);
 353 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 354                                            struct timespec *timestamp);
 355 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 356
 357 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 358
 359 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 360                                    struct timespec *timestamp);
 361 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 362                                     const struct timespec *timestamp);
 363
 364 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 365                                          uint16_t queue_id);
 366 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 367                                           uint16_t queue_id);
 368
 369 static int i40e_get_regs(struct rte_eth_dev *dev,
 370                          struct rte_dev_reg_info *regs);
 371
 372 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 373
 374 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 375                            struct rte_dev_eeprom_info *eeprom);
 376
 377 static int i40e_get_module_info(struct rte_eth_dev *dev,
 378                                 struct rte_eth_dev_module_info *modinfo);
 379 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 380                                   struct rte_dev_eeprom_info *info);
 381
 382 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 383                                       struct ether_addr *mac_addr);
 384
 385 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 386
 387 static int i40e_ethertype_filter_convert(
 388         const struct rte_eth_ethertype_filter *input,
 389         struct i40e_ethertype_filter *filter);
 390 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 391                                    struct i40e_ethertype_filter *filter);
 392
 393 static int i40e_tunnel_filter_convert(
 394         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 395         struct i40e_tunnel_filter *tunnel_filter);
 396 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 397                                 struct i40e_tunnel_filter *tunnel_filter);
 398 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 399
 400 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 401 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 402 static void i40e_filter_restore(struct i40e_pf *pf);
 403 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 404
 405 int i40e_logtype_init;
 406 int i40e_logtype_driver;
 407
 408 static const char *const valid_keys[] = {
 409         ETH_I40E_FLOATING_VEB_ARG,
 410         ETH_I40E_FLOATING_VEB_LIST_ARG,
 411         ETH_I40E_SUPPORT_MULTI_DRIVER,
 412         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 413         ETH_I40E_USE_LATEST_VEC,
 414         NULL};
 415
 416 static const struct rte_pci_id pci_id_i40e_map[] = {
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 437         { .vendor_id = 0, /* sentinel */ },
 438 };
 439
 440 static const struct eth_dev_ops i40e_eth_dev_ops = {
 441         .dev_configure                = i40e_dev_configure,
 442         .dev_start                    = i40e_dev_start,
 443         .dev_stop                     = i40e_dev_stop,
 444         .dev_close                    = i40e_dev_close,
 445         .dev_reset                    = i40e_dev_reset,
 446         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 447         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 448         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 449         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 450         .dev_set_link_up              = i40e_dev_set_link_up,
 451         .dev_set_link_down            = i40e_dev_set_link_down,
 452         .link_update                  = i40e_dev_link_update,
 453         .stats_get                    = i40e_dev_stats_get,
 454         .xstats_get                   = i40e_dev_xstats_get,
 455         .xstats_get_names             = i40e_dev_xstats_get_names,
 456         .stats_reset                  = i40e_dev_stats_reset,
 457         .xstats_reset                 = i40e_dev_stats_reset,
 458         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 459         .fw_version_get               = i40e_fw_version_get,
 460         .dev_infos_get                = i40e_dev_info_get,
 461         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 462         .vlan_filter_set              = i40e_vlan_filter_set,
 463         .vlan_tpid_set                = i40e_vlan_tpid_set,
 464         .vlan_offload_set             = i40e_vlan_offload_set,
 465         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 466         .vlan_pvid_set                = i40e_vlan_pvid_set,
 467         .rx_queue_start               = i40e_dev_rx_queue_start,
 468         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 469         .tx_queue_start               = i40e_dev_tx_queue_start,
 470         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 471         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 472         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 473         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 474         .rx_queue_release             = i40e_dev_rx_queue_release,
 475         .rx_queue_count               = i40e_dev_rx_queue_count,
 476         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 477         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 478         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 479         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 480         .tx_queue_release             = i40e_dev_tx_queue_release,
 481         .dev_led_on                   = i40e_dev_led_on,
 482         .dev_led_off                  = i40e_dev_led_off,
 483         .flow_ctrl_get                = i40e_flow_ctrl_get,
 484         .flow_ctrl_set                = i40e_flow_ctrl_set,
 485         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 486         .mac_addr_add                 = i40e_macaddr_add,
 487         .mac_addr_remove              = i40e_macaddr_remove,
 488         .reta_update                  = i40e_dev_rss_reta_update,
 489         .reta_query                   = i40e_dev_rss_reta_query,
 490         .rss_hash_update              = i40e_dev_rss_hash_update,
 491         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 492         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 493         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 494         .filter_ctrl                  = i40e_dev_filter_ctrl,
 495         .rxq_info_get                 = i40e_rxq_info_get,
 496         .txq_info_get                 = i40e_txq_info_get,
 497         .mirror_rule_set              = i40e_mirror_rule_set,
 498         .mirror_rule_reset            = i40e_mirror_rule_reset,
 499         .timesync_enable              = i40e_timesync_enable,
 500         .timesync_disable             = i40e_timesync_disable,
 501         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 502         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 503         .get_dcb_info                 = i40e_dev_get_dcb_info,
 504         .timesync_adjust_time         = i40e_timesync_adjust_time,
 505         .timesync_read_time           = i40e_timesync_read_time,
 506         .timesync_write_time          = i40e_timesync_write_time,
 507         .get_reg                      = i40e_get_regs,
 508         .get_eeprom_length            = i40e_get_eeprom_length,
 509         .get_eeprom                   = i40e_get_eeprom,
 510         .get_module_info              = i40e_get_module_info,
 511         .get_module_eeprom            = i40e_get_module_eeprom,
 512         .mac_addr_set                 = i40e_set_default_mac_addr,
 513         .mtu_set                      = i40e_dev_mtu_set,
 514         .tm_ops_get                   = i40e_tm_ops_get,
 515 };
 516
 517 /* store statistics names and its offset in stats structure */
 518 struct rte_i40e_xstats_name_off {
 519         char name[RTE_ETH_XSTATS_NAME_SIZE];
 520         unsigned offset;
 521 };
 522
 523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 524         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 525         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 526         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 527         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 528         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 529                 rx_unknown_protocol)},
 530         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 531         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 532         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 533         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 534 };
 535
 536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 537                 sizeof(rte_i40e_stats_strings[0]))
 538
 539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 540         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 541                 tx_dropped_link_down)},
 542         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 543         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 544                 illegal_bytes)},
 545         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 546         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 547                 mac_local_faults)},
 548         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_remote_faults)},
 550         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 551                 rx_length_errors)},
 552         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 553         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 554         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 555         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 556         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 557         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 558                 rx_size_127)},
 559         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_255)},
 561         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_511)},
 563         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_1023)},
 565         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1522)},
 567         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_big)},
 569         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 570                 rx_undersize)},
 571         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_oversize)},
 573         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 574                 mac_short_packet_dropped)},
 575         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_fragments)},
 577         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 578         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 579         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 580                 tx_size_127)},
 581         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_255)},
 583         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_511)},
 585         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_1023)},
 587         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1522)},
 589         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_big)},
 591         {"rx_flow_director_atr_match_packets",
 592                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 593         {"rx_flow_director_sb_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 595         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 596                 tx_lpi_status)},
 597         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 rx_lpi_status)},
 599         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 600                 tx_lpi_count)},
 601         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 rx_lpi_count)},
 603 };
 604
 605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 606                 sizeof(rte_i40e_hw_port_strings[0]))
 607
 608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 609         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xon_rx)},
 611         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xoff_rx)},
 613 };
 614
 615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 616                 sizeof(rte_i40e_rxq_prio_strings[0]))
 617
 618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 619         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xon_tx)},
 621         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xoff_tx)},
 623         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xon_2_xoff)},
 625 };
 626
 627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 628                 sizeof(rte_i40e_txq_prio_strings[0]))
 629
 630 static int
 631 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 632         struct rte_pci_device *pci_dev)
 633 {
 634         char name[RTE_ETH_NAME_MAX_LEN];
 635         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 636         int i, retval;
 637
 638         if (pci_dev->device.devargs) {
 639                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 640                                 &eth_da);
 641                 if (retval)
 642                         return retval;
 643         }
 644
 645         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 646                 sizeof(struct i40e_adapter),
 647                 eth_dev_pci_specific_init, pci_dev,
 648                 eth_i40e_dev_init, NULL);
 649
 650         if (retval || eth_da.nb_representor_ports < 1)
 651                 return retval;
 652
 653         /* probe VF representor ports */
 654         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 655                 pci_dev->device.name);
 656
 657         if (pf_ethdev == NULL)
 658                 return -ENODEV;
 659
 660         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 661                 struct i40e_vf_representor representor = {
 662                         .vf_id = eth_da.representor_ports[i],
 663                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 664                                 pf_ethdev->data->dev_private)->switch_domain_id,
 665                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 666                                 pf_ethdev->data->dev_private)
 667                 };
 668
 669                 /* representor port net_bdf_port */
 670                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 671                         pci_dev->device.name, eth_da.representor_ports[i]);
 672
 673                 retval = rte_eth_dev_create(&pci_dev->device, name,
 674                         sizeof(struct i40e_vf_representor), NULL, NULL,
 675                         i40e_vf_representor_init, &representor);
 676
 677                 if (retval)
 678                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 679                                 "representor %s.", name);
 680         }
 681
 682         return 0;
 683 }
 684
 685 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 686 {
 687         struct rte_eth_dev *ethdev;
 688
 689         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 690         if (!ethdev)
 691                 return -ENODEV;
 692
 693
 694         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 695                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 696         else
 697                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 698 }
 699
 700 static struct rte_pci_driver rte_i40e_pmd = {
 701         .id_table = pci_id_i40e_map,
 702         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 703                      RTE_PCI_DRV_IOVA_AS_VA,
 704         .probe = eth_i40e_pci_probe,
 705         .remove = eth_i40e_pci_remove,
 706 };
 707
 708 static inline void
 709 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 710                          uint32_t reg_val)
 711 {
 712         uint32_t ori_reg_val;
 713         struct rte_eth_dev *dev;
 714
 715         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 716         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 717         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 718         if (ori_reg_val != reg_val)
 719                 PMD_DRV_LOG(WARNING,
 720                             "i40e device %s changed global register [0x%08x]."
 721                             " original: 0x%08x, new: 0x%08x",
 722                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 723 }
 724
 725 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 726 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 727 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 728
 729 #ifndef I40E_GLQF_ORT
 730 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 731 #endif
 732 #ifndef I40E_GLQF_PIT
 733 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 734 #endif
 735 #ifndef I40E_GLQF_L3_MAP
 736 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 737 #endif
 738
 739 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 740 {
 741         /*
 742          * Initialize registers for parsing packet type of QinQ
 743          * This should be removed from code once proper
 744          * configuration API is added to avoid configuration conflicts
 745          * between ports of the same device.
 746          */
 747         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 748         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 749 }
 750
 751 static inline void i40e_config_automask(struct i40e_pf *pf)
 752 {
 753         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 754         uint32_t val;
 755
 756         /* INTENA flag is not auto-cleared for interrupt */
 757         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 758         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 759                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 760
 761         /* If support multi-driver, PF will use INT0. */
 762         if (!pf->support_multi_driver)
 763                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 764
 765         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 766 }
 767
 768 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 769
 770 /*
 771  * Add a ethertype filter to drop all flow control frames transmitted
 772  * from VSIs.
 773 */
 774 static void
 775 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 776 {
 777         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 778         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 779                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 780                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 781         int ret;
 782
 783         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 784                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 785                                 pf->main_vsi_seid, 0,
 786                                 TRUE, NULL, NULL);
 787         if (ret)
 788                 PMD_INIT_LOG(ERR,
 789                         "Failed to add filter to drop flow control frames from VSIs.");
 790 }
 791
 792 static int
 793 floating_veb_list_handler(__rte_unused const char *key,
 794                           const char *floating_veb_value,
 795                           void *opaque)
 796 {
 797         int idx = 0;
 798         unsigned int count = 0;
 799         char *end = NULL;
 800         int min, max;
 801         bool *vf_floating_veb = opaque;
 802
 803         while (isblank(*floating_veb_value))
 804                 floating_veb_value++;
 805
 806         /* Reset floating VEB configuration for VFs */
 807         for (idx = 0; idx < I40E_MAX_VF; idx++)
 808                 vf_floating_veb[idx] = false;
 809
 810         min = I40E_MAX_VF;
 811         do {
 812                 while (isblank(*floating_veb_value))
 813                         floating_veb_value++;
 814                 if (*floating_veb_value == '\0')
 815                         return -1;
 816                 errno = 0;
 817                 idx = strtoul(floating_veb_value, &end, 10);
 818                 if (errno || end == NULL)
 819                         return -1;
 820                 while (isblank(*end))
 821                         end++;
 822                 if (*end == '-') {
 823                         min = idx;
 824                 } else if ((*end == ';') || (*end == '\0')) {
 825                         max = idx;
 826                         if (min == I40E_MAX_VF)
 827                                 min = idx;
 828                         if (max >= I40E_MAX_VF)
 829                                 max = I40E_MAX_VF - 1;
 830                         for (idx = min; idx <= max; idx++) {
 831                                 vf_floating_veb[idx] = true;
 832                                 count++;
 833                         }
 834                         min = I40E_MAX_VF;
 835                 } else {
 836                         return -1;
 837                 }
 838                 floating_veb_value = end + 1;
 839         } while (*end != '\0');
 840
 841         if (count == 0)
 842                 return -1;
 843
 844         return 0;
 845 }
 846
 847 static void
 848 config_vf_floating_veb(struct rte_devargs *devargs,
 849                        uint16_t floating_veb,
 850                        bool *vf_floating_veb)
 851 {
 852         struct rte_kvargs *kvlist;
 853         int i;
 854         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 855
 856         if (!floating_veb)
 857                 return;
 858         /* All the VFs attach to the floating VEB by default
 859          * when the floating VEB is enabled.
 860          */
 861         for (i = 0; i < I40E_MAX_VF; i++)
 862                 vf_floating_veb[i] = true;
 863
 864         if (devargs == NULL)
 865                 return;
 866
 867         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 868         if (kvlist == NULL)
 869                 return;
 870
 871         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 872                 rte_kvargs_free(kvlist);
 873                 return;
 874         }
 875         /* When the floating_veb_list parameter exists, all the VFs
 876          * will attach to the legacy VEB firstly, then configure VFs
 877          * to the floating VEB according to the floating_veb_list.
 878          */
 879         if (rte_kvargs_process(kvlist, floating_veb_list,
 880                                floating_veb_list_handler,
 881                                vf_floating_veb) < 0) {
 882                 rte_kvargs_free(kvlist);
 883                 return;
 884         }
 885         rte_kvargs_free(kvlist);
 886 }
 887
 888 static int
 889 i40e_check_floating_handler(__rte_unused const char *key,
 890                             const char *value,
 891                             __rte_unused void *opaque)
 892 {
 893         if (strcmp(value, "1"))
 894                 return -1;
 895
 896         return 0;
 897 }
 898
 899 static int
 900 is_floating_veb_supported(struct rte_devargs *devargs)
 901 {
 902         struct rte_kvargs *kvlist;
 903         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 904
 905         if (devargs == NULL)
 906                 return 0;
 907
 908         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 909         if (kvlist == NULL)
 910                 return 0;
 911
 912         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 913                 rte_kvargs_free(kvlist);
 914                 return 0;
 915         }
 916         /* Floating VEB is enabled when there's key-value:
 917          * enable_floating_veb=1
 918          */
 919         if (rte_kvargs_process(kvlist, floating_veb_key,
 920                                i40e_check_floating_handler, NULL) < 0) {
 921                 rte_kvargs_free(kvlist);
 922                 return 0;
 923         }
 924         rte_kvargs_free(kvlist);
 925
 926         return 1;
 927 }
 928
 929 static void
 930 config_floating_veb(struct rte_eth_dev *dev)
 931 {
 932         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 933         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 934         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 935
 936         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 937
 938         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 939                 pf->floating_veb =
 940                         is_floating_veb_supported(pci_dev->device.devargs);
 941                 config_vf_floating_veb(pci_dev->device.devargs,
 942                                        pf->floating_veb,
 943                                        pf->floating_veb_list);
 944         } else {
 945                 pf->floating_veb = false;
 946         }
 947 }
 948
 949 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 950 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 951
 952 static int
 953 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 954 {
 955         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 956         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 957         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 958         int ret;
 959
 960         struct rte_hash_parameters ethertype_hash_params = {
 961                 .name = ethertype_hash_name,
 962                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 963                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 964                 .hash_func = rte_hash_crc,
 965                 .hash_func_init_val = 0,
 966                 .socket_id = rte_socket_id(),
 967         };
 968
 969         /* Initialize ethertype filter rule list and hash */
 970         TAILQ_INIT(&ethertype_rule->ethertype_list);
 971         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 972                  "ethertype_%s", dev->device->name);
 973         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 974         if (!ethertype_rule->hash_table) {
 975                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 976                 return -EINVAL;
 977         }
 978         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 979                                        sizeof(struct i40e_ethertype_filter *) *
 980                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 981                                        0);
 982         if (!ethertype_rule->hash_map) {
 983                 PMD_INIT_LOG(ERR,
 984                              "Failed to allocate memory for ethertype hash map!");
 985                 ret = -ENOMEM;
 986                 goto err_ethertype_hash_map_alloc;
 987         }
 988
 989         return 0;
 990
 991 err_ethertype_hash_map_alloc:
 992         rte_hash_free(ethertype_rule->hash_table);
 993
 994         return ret;
 995 }
 996
 997 static int
 998 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 999 {
1000         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1001         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1002         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1003         int ret;
1004
1005         struct rte_hash_parameters tunnel_hash_params = {
1006                 .name = tunnel_hash_name,
1007                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1008                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1009                 .hash_func = rte_hash_crc,
1010                 .hash_func_init_val = 0,
1011                 .socket_id = rte_socket_id(),
1012         };
1013
1014         /* Initialize tunnel filter rule list and hash */
1015         TAILQ_INIT(&tunnel_rule->tunnel_list);
1016         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1017                  "tunnel_%s", dev->device->name);
1018         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1019         if (!tunnel_rule->hash_table) {
1020                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1021                 return -EINVAL;
1022         }
1023         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1024                                     sizeof(struct i40e_tunnel_filter *) *
1025                                     I40E_MAX_TUNNEL_FILTER_NUM,
1026                                     0);
1027         if (!tunnel_rule->hash_map) {
1028                 PMD_INIT_LOG(ERR,
1029                              "Failed to allocate memory for tunnel hash map!");
1030                 ret = -ENOMEM;
1031                 goto err_tunnel_hash_map_alloc;
1032         }
1033
1034         return 0;
1035
1036 err_tunnel_hash_map_alloc:
1037         rte_hash_free(tunnel_rule->hash_table);
1038
1039         return ret;
1040 }
1041
1042 static int
1043 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1044 {
1045         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1046         struct i40e_fdir_info *fdir_info = &pf->fdir;
1047         char fdir_hash_name[RTE_HASH_NAMESIZE];
1048         int ret;
1049
1050         struct rte_hash_parameters fdir_hash_params = {
1051                 .name = fdir_hash_name,
1052                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1053                 .key_len = sizeof(struct i40e_fdir_input),
1054                 .hash_func = rte_hash_crc,
1055                 .hash_func_init_val = 0,
1056                 .socket_id = rte_socket_id(),
1057         };
1058
1059         /* Initialize flow director filter rule list and hash */
1060         TAILQ_INIT(&fdir_info->fdir_list);
1061         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1062                  "fdir_%s", dev->device->name);
1063         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1064         if (!fdir_info->hash_table) {
1065                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1066                 return -EINVAL;
1067         }
1068         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1069                                           sizeof(struct i40e_fdir_filter *) *
1070                                           I40E_MAX_FDIR_FILTER_NUM,
1071                                           0);
1072         if (!fdir_info->hash_map) {
1073                 PMD_INIT_LOG(ERR,
1074                              "Failed to allocate memory for fdir hash map!");
1075                 ret = -ENOMEM;
1076                 goto err_fdir_hash_map_alloc;
1077         }
1078         return 0;
1079
1080 err_fdir_hash_map_alloc:
1081         rte_hash_free(fdir_info->hash_table);
1082
1083         return ret;
1084 }
1085
1086 static void
1087 i40e_init_customized_info(struct i40e_pf *pf)
1088 {
1089         int i;
1090
1091         /* Initialize customized pctype */
1092         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1093                 pf->customized_pctype[i].index = i;
1094                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1095                 pf->customized_pctype[i].valid = false;
1096         }
1097
1098         pf->gtp_support = false;
1099 }
1100
1101 void
1102 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1103 {
1104         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1105         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1106         struct i40e_queue_regions *info = &pf->queue_region;
1107         uint16_t i;
1108
1109         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1110                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1111
1112         memset(info, 0, sizeof(struct i40e_queue_regions));
1113 }
1114
1115 static int
1116 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1117                                const char *value,
1118                                void *opaque)
1119 {
1120         struct i40e_pf *pf;
1121         unsigned long support_multi_driver;
1122         char *end;
1123
1124         pf = (struct i40e_pf *)opaque;
1125
1126         errno = 0;
1127         support_multi_driver = strtoul(value, &end, 10);
1128         if (errno != 0 || end == value || *end != 0) {
1129                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1130                 return -(EINVAL);
1131         }
1132
1133         if (support_multi_driver == 1 || support_multi_driver == 0)
1134                 pf->support_multi_driver = (bool)support_multi_driver;
1135         else
1136                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1137                             "enable global configuration by default."
1138                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1139         return 0;
1140 }
1141
1142 static int
1143 i40e_support_multi_driver(struct rte_eth_dev *dev)
1144 {
1145         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1146         struct rte_kvargs *kvlist;
1147         int kvargs_count;
1148
1149         /* Enable global configuration by default */
1150         pf->support_multi_driver = false;
1151
1152         if (!dev->device->devargs)
1153                 return 0;
1154
1155         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1156         if (!kvlist)
1157                 return -EINVAL;
1158
1159         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1160         if (!kvargs_count) {
1161                 rte_kvargs_free(kvlist);
1162                 return 0;
1163         }
1164
1165         if (kvargs_count > 1)
1166                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1167                             "the first invalid or last valid one is used !",
1168                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1169
1170         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1171                                i40e_parse_multi_drv_handler, pf) < 0) {
1172                 rte_kvargs_free(kvlist);
1173                 return -EINVAL;
1174         }
1175
1176         rte_kvargs_free(kvlist);
1177         return 0;
1178 }
1179
1180 static int
1181 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1182                                     uint32_t reg_addr, uint64_t reg_val,
1183                                     struct i40e_asq_cmd_details *cmd_details)
1184 {
1185         uint64_t ori_reg_val;
1186         struct rte_eth_dev *dev;
1187         int ret;
1188
1189         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1190         if (ret != I40E_SUCCESS) {
1191                 PMD_DRV_LOG(ERR,
1192                             "Fail to debug read from 0x%08x",
1193                             reg_addr);
1194                 return -EIO;
1195         }
1196         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1197
1198         if (ori_reg_val != reg_val)
1199                 PMD_DRV_LOG(WARNING,
1200                             "i40e device %s changed global register [0x%08x]."
1201                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1202                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1203
1204         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1205 }
1206
1207 static int
1208 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1209                                 const char *value,
1210                                 void *opaque)
1211 {
1212         struct i40e_adapter *ad;
1213         int use_latest_vec;
1214
1215         ad = (struct i40e_adapter *)opaque;
1216
1217         use_latest_vec = atoi(value);
1218
1219         if (use_latest_vec != 0 && use_latest_vec != 1)
1220                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1221
1222         ad->use_latest_vec = (uint8_t)use_latest_vec;
1223
1224         return 0;
1225 }
1226
1227 static int
1228 i40e_use_latest_vec(struct rte_eth_dev *dev)
1229 {
1230         struct i40e_adapter *ad =
1231                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1232         struct rte_kvargs *kvlist;
1233         int kvargs_count;
1234
1235         ad->use_latest_vec = false;
1236
1237         if (!dev->device->devargs)
1238                 return 0;
1239
1240         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1241         if (!kvlist)
1242                 return -EINVAL;
1243
1244         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1245         if (!kvargs_count) {
1246                 rte_kvargs_free(kvlist);
1247                 return 0;
1248         }
1249
1250         if (kvargs_count > 1)
1251                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1252                             "the first invalid or last valid one is used !",
1253                             ETH_I40E_USE_LATEST_VEC);
1254
1255         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1256                                 i40e_parse_latest_vec_handler, ad) < 0) {
1257                 rte_kvargs_free(kvlist);
1258                 return -EINVAL;
1259         }
1260
1261         rte_kvargs_free(kvlist);
1262         return 0;
1263 }
1264
1265 #define I40E_ALARM_INTERVAL 50000 /* us */
1266
1267 static int
1268 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1269 {
1270         struct rte_pci_device *pci_dev;
1271         struct rte_intr_handle *intr_handle;
1272         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1273         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274         struct i40e_vsi *vsi;
1275         int ret;
1276         uint32_t len, val;
1277         uint8_t aq_fail = 0;
1278
1279         PMD_INIT_FUNC_TRACE();
1280
1281         dev->dev_ops = &i40e_eth_dev_ops;
1282         dev->rx_pkt_burst = i40e_recv_pkts;
1283         dev->tx_pkt_burst = i40e_xmit_pkts;
1284         dev->tx_pkt_prepare = i40e_prep_pkts;
1285
1286         /* for secondary processes, we don't initialise any further as primary
1287          * has already done this work. Only check we don't need a different
1288          * RX function */
1289         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1290                 i40e_set_rx_function(dev);
1291                 i40e_set_tx_function(dev);
1292                 return 0;
1293         }
1294         i40e_set_default_ptype_table(dev);
1295         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1296         intr_handle = &pci_dev->intr_handle;
1297
1298         rte_eth_copy_pci_info(dev, pci_dev);
1299
1300         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1301         pf->adapter->eth_dev = dev;
1302         pf->dev_data = dev->data;
1303
1304         hw->back = I40E_PF_TO_ADAPTER(pf);
1305         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1306         if (!hw->hw_addr) {
1307                 PMD_INIT_LOG(ERR,
1308                         "Hardware is not available, as address is NULL");
1309                 return -ENODEV;
1310         }
1311
1312         hw->vendor_id = pci_dev->id.vendor_id;
1313         hw->device_id = pci_dev->id.device_id;
1314         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1315         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1316         hw->bus.device = pci_dev->addr.devid;
1317         hw->bus.func = pci_dev->addr.function;
1318         hw->adapter_stopped = 0;
1319         hw->adapter_closed = 0;
1320
1321         /*
1322          * Switch Tag value should not be identical to either the First Tag
1323          * or Second Tag values. So set something other than common Ethertype
1324          * for internal switching.
1325          */
1326         hw->switch_tag = 0xffff;
1327
1328         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1329         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1330                 PMD_INIT_LOG(ERR, "\nERROR: "
1331                         "Firmware recovery mode detected. Limiting functionality.\n"
1332                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1333                         "User Guide for details on firmware recovery mode.");
1334                 return -EIO;
1335         }
1336
1337         /* Check if need to support multi-driver */
1338         i40e_support_multi_driver(dev);
1339         /* Check if users want the latest supported vec path */
1340         i40e_use_latest_vec(dev);
1341
1342         /* Make sure all is clean before doing PF reset */
1343         i40e_clear_hw(hw);
1344
1345         /* Reset here to make sure all is clean for each PF */
1346         ret = i40e_pf_reset(hw);
1347         if (ret) {
1348                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1349                 return ret;
1350         }
1351
1352         /* Initialize the shared code (base driver) */
1353         ret = i40e_init_shared_code(hw);
1354         if (ret) {
1355                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1356                 return ret;
1357         }
1358
1359         /* Initialize the parameters for adminq */
1360         i40e_init_adminq_parameter(hw);
1361         ret = i40e_init_adminq(hw);
1362         if (ret != I40E_SUCCESS) {
1363                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1364                 return -EIO;
1365         }
1366         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1367                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1368                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1369                      ((hw->nvm.version >> 12) & 0xf),
1370                      ((hw->nvm.version >> 4) & 0xff),
1371                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1372
1373         /* Initialize the hardware */
1374         i40e_hw_init(dev);
1375
1376         i40e_config_automask(pf);
1377
1378         i40e_set_default_pctype_table(dev);
1379
1380         /*
1381          * To work around the NVM issue, initialize registers
1382          * for packet type of QinQ by software.
1383          * It should be removed once issues are fixed in NVM.
1384          */
1385         if (!pf->support_multi_driver)
1386                 i40e_GLQF_reg_init(hw);
1387
1388         /* Initialize the input set for filters (hash and fd) to default value */
1389         i40e_filter_input_set_init(pf);
1390
1391         /* initialise the L3_MAP register */
1392         if (!pf->support_multi_driver) {
1393                 ret = i40e_aq_debug_write_global_register(hw,
1394                                                    I40E_GLQF_L3_MAP(40),
1395                                                    0x00000028,  NULL);
1396                 if (ret)
1397                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1398                                      ret);
1399                 PMD_INIT_LOG(DEBUG,
1400                              "Global register 0x%08x is changed with 0x28",
1401                              I40E_GLQF_L3_MAP(40));
1402         }
1403
1404         /* Need the special FW version to support floating VEB */
1405         config_floating_veb(dev);
1406         /* Clear PXE mode */
1407         i40e_clear_pxe_mode(hw);
1408         i40e_dev_sync_phy_type(hw);
1409
1410         /*
1411          * On X710, performance number is far from the expectation on recent
1412          * firmware versions. The fix for this issue may not be integrated in
1413          * the following firmware version. So the workaround in software driver
1414          * is needed. It needs to modify the initial values of 3 internal only
1415          * registers. Note that the workaround can be removed when it is fixed
1416          * in firmware in the future.
1417          */
1418         i40e_configure_registers(hw);
1419
1420         /* Get hw capabilities */
1421         ret = i40e_get_cap(hw);
1422         if (ret != I40E_SUCCESS) {
1423                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1424                 goto err_get_capabilities;
1425         }
1426
1427         /* Initialize parameters for PF */
1428         ret = i40e_pf_parameter_init(dev);
1429         if (ret != 0) {
1430                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1431                 goto err_parameter_init;
1432         }
1433
1434         /* Initialize the queue management */
1435         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1436         if (ret < 0) {
1437                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1438                 goto err_qp_pool_init;
1439         }
1440         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1441                                 hw->func_caps.num_msix_vectors - 1);
1442         if (ret < 0) {
1443                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1444                 goto err_msix_pool_init;
1445         }
1446
1447         /* Initialize lan hmc */
1448         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1449                                 hw->func_caps.num_rx_qp, 0, 0);
1450         if (ret != I40E_SUCCESS) {
1451                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1452                 goto err_init_lan_hmc;
1453         }
1454
1455         /* Configure lan hmc */
1456         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1457         if (ret != I40E_SUCCESS) {
1458                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1459                 goto err_configure_lan_hmc;
1460         }
1461
1462         /* Get and check the mac address */
1463         i40e_get_mac_addr(hw, hw->mac.addr);
1464         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1465                 PMD_INIT_LOG(ERR, "mac address is not valid");
1466                 ret = -EIO;
1467                 goto err_get_mac_addr;
1468         }
1469         /* Copy the permanent MAC address */
1470         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1471                         (struct ether_addr *) hw->mac.perm_addr);
1472
1473         /* Disable flow control */
1474         hw->fc.requested_mode = I40E_FC_NONE;
1475         i40e_set_fc(hw, &aq_fail, TRUE);
1476
1477         /* Set the global registers with default ether type value */
1478         if (!pf->support_multi_driver) {
1479                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1480                                          ETHER_TYPE_VLAN);
1481                 if (ret != I40E_SUCCESS) {
1482                         PMD_INIT_LOG(ERR,
1483                                      "Failed to set the default outer "
1484                                      "VLAN ether type");
1485                         goto err_setup_pf_switch;
1486                 }
1487         }
1488
1489         /* PF setup, which includes VSI setup */
1490         ret = i40e_pf_setup(pf);
1491         if (ret) {
1492                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1493                 goto err_setup_pf_switch;
1494         }
1495
1496         /* reset all stats of the device, including pf and main vsi */
1497         i40e_dev_stats_reset(dev);
1498
1499         vsi = pf->main_vsi;
1500
1501         /* Disable double vlan by default */
1502         i40e_vsi_config_double_vlan(vsi, FALSE);
1503
1504         /* Disable S-TAG identification when floating_veb is disabled */
1505         if (!pf->floating_veb) {
1506                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1507                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1508                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1509                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1510                 }
1511         }
1512
1513         if (!vsi->max_macaddrs)
1514                 len = ETHER_ADDR_LEN;
1515         else
1516                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1517
1518         /* Should be after VSI initialized */
1519         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1520         if (!dev->data->mac_addrs) {
1521                 PMD_INIT_LOG(ERR,
1522                         "Failed to allocated memory for storing mac address");
1523                 goto err_mac_alloc;
1524         }
1525         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1526                                         &dev->data->mac_addrs[0]);
1527
1528         /* Init dcb to sw mode by default */
1529         ret = i40e_dcb_init_configure(dev, TRUE);
1530         if (ret != I40E_SUCCESS) {
1531                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1532                 pf->flags &= ~I40E_FLAG_DCB;
1533         }
1534         /* Update HW struct after DCB configuration */
1535         i40e_get_cap(hw);
1536
1537         /* initialize pf host driver to setup SRIOV resource if applicable */
1538         i40e_pf_host_init(dev);
1539
1540         /* register callback func to eal lib */
1541         rte_intr_callback_register(intr_handle,
1542                                    i40e_dev_interrupt_handler, dev);
1543
1544         /* configure and enable device interrupt */
1545         i40e_pf_config_irq0(hw, TRUE);
1546         i40e_pf_enable_irq0(hw);
1547
1548         /* enable uio intr after callback register */
1549         rte_intr_enable(intr_handle);
1550
1551         /* By default disable flexible payload in global configuration */
1552         if (!pf->support_multi_driver)
1553                 i40e_flex_payload_reg_set_default(hw);
1554
1555         /*
1556          * Add an ethertype filter to drop all flow control frames transmitted
1557          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1558          * frames to wire.
1559          */
1560         i40e_add_tx_flow_control_drop_filter(pf);
1561
1562         /* Set the max frame size to 0x2600 by default,
1563          * in case other drivers changed the default value.
1564          */
1565         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1566
1567         /* initialize mirror rule list */
1568         TAILQ_INIT(&pf->mirror_list);
1569
1570         /* initialize Traffic Manager configuration */
1571         i40e_tm_conf_init(dev);
1572
1573         /* Initialize customized information */
1574         i40e_init_customized_info(pf);
1575
1576         ret = i40e_init_ethtype_filter_list(dev);
1577         if (ret < 0)
1578                 goto err_init_ethtype_filter_list;
1579         ret = i40e_init_tunnel_filter_list(dev);
1580         if (ret < 0)
1581                 goto err_init_tunnel_filter_list;
1582         ret = i40e_init_fdir_filter_list(dev);
1583         if (ret < 0)
1584                 goto err_init_fdir_filter_list;
1585
1586         /* initialize queue region configuration */
1587         i40e_init_queue_region_conf(dev);
1588
1589         /* initialize rss configuration from rte_flow */
1590         memset(&pf->rss_info, 0,
1591                 sizeof(struct i40e_rte_flow_rss_conf));
1592
1593         return 0;
1594
1595 err_init_fdir_filter_list:
1596         rte_free(pf->tunnel.hash_table);
1597         rte_free(pf->tunnel.hash_map);
1598 err_init_tunnel_filter_list:
1599         rte_free(pf->ethertype.hash_table);
1600         rte_free(pf->ethertype.hash_map);
1601 err_init_ethtype_filter_list:
1602         rte_free(dev->data->mac_addrs);
1603 err_mac_alloc:
1604         i40e_vsi_release(pf->main_vsi);
1605 err_setup_pf_switch:
1606 err_get_mac_addr:
1607 err_configure_lan_hmc:
1608         (void)i40e_shutdown_lan_hmc(hw);
1609 err_init_lan_hmc:
1610         i40e_res_pool_destroy(&pf->msix_pool);
1611 err_msix_pool_init:
1612         i40e_res_pool_destroy(&pf->qp_pool);
1613 err_qp_pool_init:
1614 err_parameter_init:
1615 err_get_capabilities:
1616         (void)i40e_shutdown_adminq(hw);
1617
1618         return ret;
1619 }
1620
1621 static void
1622 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1623 {
1624         struct i40e_ethertype_filter *p_ethertype;
1625         struct i40e_ethertype_rule *ethertype_rule;
1626
1627         ethertype_rule = &pf->ethertype;
1628         /* Remove all ethertype filter rules and hash */
1629         if (ethertype_rule->hash_map)
1630                 rte_free(ethertype_rule->hash_map);
1631         if (ethertype_rule->hash_table)
1632                 rte_hash_free(ethertype_rule->hash_table);
1633
1634         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1635                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1636                              p_ethertype, rules);
1637                 rte_free(p_ethertype);
1638         }
1639 }
1640
1641 static void
1642 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1643 {
1644         struct i40e_tunnel_filter *p_tunnel;
1645         struct i40e_tunnel_rule *tunnel_rule;
1646
1647         tunnel_rule = &pf->tunnel;
1648         /* Remove all tunnel director rules and hash */
1649         if (tunnel_rule->hash_map)
1650                 rte_free(tunnel_rule->hash_map);
1651         if (tunnel_rule->hash_table)
1652                 rte_hash_free(tunnel_rule->hash_table);
1653
1654         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1655                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1656                 rte_free(p_tunnel);
1657         }
1658 }
1659
1660 static void
1661 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1662 {
1663         struct i40e_fdir_filter *p_fdir;
1664         struct i40e_fdir_info *fdir_info;
1665
1666         fdir_info = &pf->fdir;
1667         /* Remove all flow director rules and hash */
1668         if (fdir_info->hash_map)
1669                 rte_free(fdir_info->hash_map);
1670         if (fdir_info->hash_table)
1671                 rte_hash_free(fdir_info->hash_table);
1672
1673         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1674                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1675                 rte_free(p_fdir);
1676         }
1677 }
1678
1679 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1680 {
1681         /*
1682          * Disable by default flexible payload
1683          * for corresponding L2/L3/L4 layers.
1684          */
1685         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1686         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1687         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1688 }
1689
1690 static int
1691 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1692 {
1693         struct i40e_pf *pf;
1694         struct rte_pci_device *pci_dev;
1695         struct rte_intr_handle *intr_handle;
1696         struct i40e_hw *hw;
1697         struct i40e_filter_control_settings settings;
1698         struct rte_flow *p_flow;
1699         int ret;
1700         uint8_t aq_fail = 0;
1701         int retries = 0;
1702
1703         PMD_INIT_FUNC_TRACE();
1704
1705         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1706                 return 0;
1707
1708         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1709         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1710         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1711         intr_handle = &pci_dev->intr_handle;
1712
1713         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1714         if (ret)
1715                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1716
1717         if (hw->adapter_closed == 0)
1718                 i40e_dev_close(dev);
1719
1720         dev->dev_ops = NULL;
1721         dev->rx_pkt_burst = NULL;
1722         dev->tx_pkt_burst = NULL;
1723
1724         /* Clear PXE mode */
1725         i40e_clear_pxe_mode(hw);
1726
1727         /* Unconfigure filter control */
1728         memset(&settings, 0, sizeof(settings));
1729         ret = i40e_set_filter_control(hw, &settings);
1730         if (ret)
1731                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1732                                         ret);
1733
1734         /* Disable flow control */
1735         hw->fc.requested_mode = I40E_FC_NONE;
1736         i40e_set_fc(hw, &aq_fail, TRUE);
1737
1738         /* uninitialize pf host driver */
1739         i40e_pf_host_uninit(dev);
1740
1741         /* disable uio intr before callback unregister */
1742         rte_intr_disable(intr_handle);
1743
1744         /* unregister callback func to eal lib */
1745         do {
1746                 ret = rte_intr_callback_unregister(intr_handle,
1747                                 i40e_dev_interrupt_handler, dev);
1748                 if (ret >= 0) {
1749                         break;
1750                 } else if (ret != -EAGAIN) {
1751                         PMD_INIT_LOG(ERR,
1752                                  "intr callback unregister failed: %d",
1753                                  ret);
1754                         return ret;
1755                 }
1756                 i40e_msec_delay(500);
1757         } while (retries++ < 5);
1758
1759         i40e_rm_ethtype_filter_list(pf);
1760         i40e_rm_tunnel_filter_list(pf);
1761         i40e_rm_fdir_filter_list(pf);
1762
1763         /* Remove all flows */
1764         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1765                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1766                 rte_free(p_flow);
1767         }
1768
1769         /* Remove all Traffic Manager configuration */
1770         i40e_tm_conf_uninit(dev);
1771
1772         return 0;
1773 }
1774
1775 static int
1776 i40e_dev_configure(struct rte_eth_dev *dev)
1777 {
1778         struct i40e_adapter *ad =
1779                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1780         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1782         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1783         int i, ret;
1784
1785         ret = i40e_dev_sync_phy_type(hw);
1786         if (ret)
1787                 return ret;
1788
1789         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1790          * bulk allocation or vector Rx preconditions we will reset it.
1791          */
1792         ad->rx_bulk_alloc_allowed = true;
1793         ad->rx_vec_allowed = true;
1794         ad->tx_simple_allowed = true;
1795         ad->tx_vec_allowed = true;
1796
1797         /* Only legacy filter API needs the following fdir config. So when the
1798          * legacy filter API is deprecated, the following codes should also be
1799          * removed.
1800          */
1801         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1802                 ret = i40e_fdir_setup(pf);
1803                 if (ret != I40E_SUCCESS) {
1804                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1805                         return -ENOTSUP;
1806                 }
1807                 ret = i40e_fdir_configure(dev);
1808                 if (ret < 0) {
1809                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1810                         goto err;
1811                 }
1812         } else
1813                 i40e_fdir_teardown(pf);
1814
1815         ret = i40e_dev_init_vlan(dev);
1816         if (ret < 0)
1817                 goto err;
1818
1819         /* VMDQ setup.
1820          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1821          *  RSS setting have different requirements.
1822          *  General PMD driver call sequence are NIC init, configure,
1823          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1824          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1825          *  applicable. So, VMDQ setting has to be done before
1826          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1827          *  For RSS setting, it will try to calculate actual configured RX queue
1828          *  number, which will be available after rx_queue_setup(). dev_start()
1829          *  function is good to place RSS setup.
1830          */
1831         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1832                 ret = i40e_vmdq_setup(dev);
1833                 if (ret)
1834                         goto err;
1835         }
1836
1837         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1838                 ret = i40e_dcb_setup(dev);
1839                 if (ret) {
1840                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1841                         goto err_dcb;
1842                 }
1843         }
1844
1845         TAILQ_INIT(&pf->flow_list);
1846
1847         return 0;
1848
1849 err_dcb:
1850         /* need to release vmdq resource if exists */
1851         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1852                 i40e_vsi_release(pf->vmdq[i].vsi);
1853                 pf->vmdq[i].vsi = NULL;
1854         }
1855         rte_free(pf->vmdq);
1856         pf->vmdq = NULL;
1857 err:
1858         /* Need to release fdir resource if exists.
1859          * Only legacy filter API needs the following fdir config. So when the
1860          * legacy filter API is deprecated, the following code should also be
1861          * removed.
1862          */
1863         i40e_fdir_teardown(pf);
1864         return ret;
1865 }
1866
1867 void
1868 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1869 {
1870         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1871         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1872         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1873         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1874         uint16_t msix_vect = vsi->msix_intr;
1875         uint16_t i;
1876
1877         for (i = 0; i < vsi->nb_qps; i++) {
1878                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1879                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1880                 rte_wmb();
1881         }
1882
1883         if (vsi->type != I40E_VSI_SRIOV) {
1884                 if (!rte_intr_allow_others(intr_handle)) {
1885                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1886                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1887                         I40E_WRITE_REG(hw,
1888                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1889                                        0);
1890                 } else {
1891                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1892                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1893                         I40E_WRITE_REG(hw,
1894                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1895                                                        msix_vect - 1), 0);
1896                 }
1897         } else {
1898                 uint32_t reg;
1899                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1900                         vsi->user_param + (msix_vect - 1);
1901
1902                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1903                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1904         }
1905         I40E_WRITE_FLUSH(hw);
1906 }
1907
1908 static void
1909 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1910                        int base_queue, int nb_queue,
1911                        uint16_t itr_idx)
1912 {
1913         int i;
1914         uint32_t val;
1915         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1916         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1917
1918         /* Bind all RX queues to allocated MSIX interrupt */
1919         for (i = 0; i < nb_queue; i++) {
1920                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1921                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1922                         ((base_queue + i + 1) <<
1923                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1924                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1925                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1926
1927                 if (i == nb_queue - 1)
1928                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1929                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1930         }
1931
1932         /* Write first RX queue to Link list register as the head element */
1933         if (vsi->type != I40E_VSI_SRIOV) {
1934                 uint16_t interval =
1935                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1936
1937                 if (msix_vect == I40E_MISC_VEC_ID) {
1938                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1939                                        (base_queue <<
1940                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1941                                        (0x0 <<
1942                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1943                         I40E_WRITE_REG(hw,
1944                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1945                                        interval);
1946                 } else {
1947                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1948                                        (base_queue <<
1949                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1950                                        (0x0 <<
1951                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1952                         I40E_WRITE_REG(hw,
1953                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1954                                                        msix_vect - 1),
1955                                        interval);
1956                 }
1957         } else {
1958                 uint32_t reg;
1959
1960                 if (msix_vect == I40E_MISC_VEC_ID) {
1961                         I40E_WRITE_REG(hw,
1962                                        I40E_VPINT_LNKLST0(vsi->user_param),
1963                                        (base_queue <<
1964                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1965                                        (0x0 <<
1966                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1967                 } else {
1968                         /* num_msix_vectors_vf needs to minus irq0 */
1969                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1970                                 vsi->user_param + (msix_vect - 1);
1971
1972                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1973                                        (base_queue <<
1974                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1975                                        (0x0 <<
1976                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1977                 }
1978         }
1979
1980         I40E_WRITE_FLUSH(hw);
1981 }
1982
1983 void
1984 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1985 {
1986         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1987         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1988         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1989         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1990         uint16_t msix_vect = vsi->msix_intr;
1991         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1992         uint16_t queue_idx = 0;
1993         int record = 0;
1994         int i;
1995
1996         for (i = 0; i < vsi->nb_qps; i++) {
1997                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1998                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1999         }
2000
2001         /* VF bind interrupt */
2002         if (vsi->type == I40E_VSI_SRIOV) {
2003                 __vsi_queues_bind_intr(vsi, msix_vect,
2004                                        vsi->base_queue, vsi->nb_qps,
2005                                        itr_idx);
2006                 return;
2007         }
2008
2009         /* PF & VMDq bind interrupt */
2010         if (rte_intr_dp_is_en(intr_handle)) {
2011                 if (vsi->type == I40E_VSI_MAIN) {
2012                         queue_idx = 0;
2013                         record = 1;
2014                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2015                         struct i40e_vsi *main_vsi =
2016                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2017                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2018                         record = 1;
2019                 }
2020         }
2021
2022         for (i = 0; i < vsi->nb_used_qps; i++) {
2023                 if (nb_msix <= 1) {
2024                         if (!rte_intr_allow_others(intr_handle))
2025                                 /* allow to share MISC_VEC_ID */
2026                                 msix_vect = I40E_MISC_VEC_ID;
2027
2028                         /* no enough msix_vect, map all to one */
2029                         __vsi_queues_bind_intr(vsi, msix_vect,
2030                                                vsi->base_queue + i,
2031                                                vsi->nb_used_qps - i,
2032                                                itr_idx);
2033                         for (; !!record && i < vsi->nb_used_qps; i++)
2034                                 intr_handle->intr_vec[queue_idx + i] =
2035                                         msix_vect;
2036                         break;
2037                 }
2038                 /* 1:1 queue/msix_vect mapping */
2039                 __vsi_queues_bind_intr(vsi, msix_vect,
2040                                        vsi->base_queue + i, 1,
2041                                        itr_idx);
2042                 if (!!record)
2043                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2044
2045                 msix_vect++;
2046                 nb_msix--;
2047         }
2048 }
2049
2050 static void
2051 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2052 {
2053         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2054         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2055         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2056         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2057         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2058         uint16_t msix_intr, i;
2059
2060         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2061                 for (i = 0; i < vsi->nb_msix; i++) {
2062                         msix_intr = vsi->msix_intr + i;
2063                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2064                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2065                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2066                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2067                 }
2068         else
2069                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2070                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2071                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2072                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2073
2074         I40E_WRITE_FLUSH(hw);
2075 }
2076
2077 static void
2078 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2079 {
2080         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2081         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2082         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2083         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2084         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2085         uint16_t msix_intr, i;
2086
2087         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2088                 for (i = 0; i < vsi->nb_msix; i++) {
2089                         msix_intr = vsi->msix_intr + i;
2090                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2091                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2092                 }
2093         else
2094                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2095                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2096
2097         I40E_WRITE_FLUSH(hw);
2098 }
2099
2100 static inline uint8_t
2101 i40e_parse_link_speeds(uint16_t link_speeds)
2102 {
2103         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2104
2105         if (link_speeds & ETH_LINK_SPEED_40G)
2106                 link_speed |= I40E_LINK_SPEED_40GB;
2107         if (link_speeds & ETH_LINK_SPEED_25G)
2108                 link_speed |= I40E_LINK_SPEED_25GB;
2109         if (link_speeds & ETH_LINK_SPEED_20G)
2110                 link_speed |= I40E_LINK_SPEED_20GB;
2111         if (link_speeds & ETH_LINK_SPEED_10G)
2112                 link_speed |= I40E_LINK_SPEED_10GB;
2113         if (link_speeds & ETH_LINK_SPEED_1G)
2114                 link_speed |= I40E_LINK_SPEED_1GB;
2115         if (link_speeds & ETH_LINK_SPEED_100M)
2116                 link_speed |= I40E_LINK_SPEED_100MB;
2117
2118         return link_speed;
2119 }
2120
2121 static int
2122 i40e_phy_conf_link(struct i40e_hw *hw,
2123                    uint8_t abilities,
2124                    uint8_t force_speed,
2125                    bool is_up)
2126 {
2127         enum i40e_status_code status;
2128         struct i40e_aq_get_phy_abilities_resp phy_ab;
2129         struct i40e_aq_set_phy_config phy_conf;
2130         enum i40e_aq_phy_type cnt;
2131         uint8_t avail_speed;
2132         uint32_t phy_type_mask = 0;
2133
2134         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2135                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2136                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2137                         I40E_AQ_PHY_FLAG_LOW_POWER;
2138         int ret = -ENOTSUP;
2139
2140         /* To get phy capabilities of available speeds. */
2141         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2142                                               NULL);
2143         if (status) {
2144                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2145                                 status);
2146                 return ret;
2147         }
2148         avail_speed = phy_ab.link_speed;
2149
2150         /* To get the current phy config. */
2151         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2152                                               NULL);
2153         if (status) {
2154                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2155                                 status);
2156                 return ret;
2157         }
2158
2159         /* If link needs to go up and it is in autoneg mode the speed is OK,
2160          * no need to set up again.
2161          */
2162         if (is_up && phy_ab.phy_type != 0 &&
2163                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2164                      phy_ab.link_speed != 0)
2165                 return I40E_SUCCESS;
2166
2167         memset(&phy_conf, 0, sizeof(phy_conf));
2168
2169         /* bits 0-2 use the values from get_phy_abilities_resp */
2170         abilities &= ~mask;
2171         abilities |= phy_ab.abilities & mask;
2172
2173         phy_conf.abilities = abilities;
2174
2175         /* If link needs to go up, but the force speed is not supported,
2176          * Warn users and config the default available speeds.
2177          */
2178         if (is_up && !(force_speed & avail_speed)) {
2179                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2180                 phy_conf.link_speed = avail_speed;
2181         } else {
2182                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2183         }
2184
2185         /* PHY type mask needs to include each type except PHY type extension */
2186         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2187                 phy_type_mask |= 1 << cnt;
2188
2189         /* use get_phy_abilities_resp value for the rest */
2190         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2191         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2192                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2193                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2194         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2195         phy_conf.eee_capability = phy_ab.eee_capability;
2196         phy_conf.eeer = phy_ab.eeer_val;
2197         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2198
2199         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2200                     phy_ab.abilities, phy_ab.link_speed);
2201         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2202                     phy_conf.abilities, phy_conf.link_speed);
2203
2204         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2205         if (status)
2206                 return ret;
2207
2208         return I40E_SUCCESS;
2209 }
2210
2211 static int
2212 i40e_apply_link_speed(struct rte_eth_dev *dev)
2213 {
2214         uint8_t speed;
2215         uint8_t abilities = 0;
2216         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2217         struct rte_eth_conf *conf = &dev->data->dev_conf;
2218
2219         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2220                 conf->link_speeds = ETH_LINK_SPEED_40G |
2221                                     ETH_LINK_SPEED_25G |
2222                                     ETH_LINK_SPEED_20G |
2223                                     ETH_LINK_SPEED_10G |
2224                                     ETH_LINK_SPEED_1G |
2225                                     ETH_LINK_SPEED_100M;
2226         }
2227         speed = i40e_parse_link_speeds(conf->link_speeds);
2228         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2229                      I40E_AQ_PHY_AN_ENABLED |
2230                      I40E_AQ_PHY_LINK_ENABLED;
2231
2232         return i40e_phy_conf_link(hw, abilities, speed, true);
2233 }
2234
2235 static int
2236 i40e_dev_start(struct rte_eth_dev *dev)
2237 {
2238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2239         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240         struct i40e_vsi *main_vsi = pf->main_vsi;
2241         int ret, i;
2242         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2243         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2244         uint32_t intr_vector = 0;
2245         struct i40e_vsi *vsi;
2246
2247         hw->adapter_stopped = 0;
2248
2249         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2250                 PMD_INIT_LOG(ERR,
2251                 "Invalid link_speeds for port %u, autonegotiation disabled",
2252                               dev->data->port_id);
2253                 return -EINVAL;
2254         }
2255
2256         rte_intr_disable(intr_handle);
2257
2258         if ((rte_intr_cap_multiple(intr_handle) ||
2259              !RTE_ETH_DEV_SRIOV(dev).active) &&
2260             dev->data->dev_conf.intr_conf.rxq != 0) {
2261                 intr_vector = dev->data->nb_rx_queues;
2262                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2263                 if (ret)
2264                         return ret;
2265         }
2266
2267         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2268                 intr_handle->intr_vec =
2269                         rte_zmalloc("intr_vec",
2270                                     dev->data->nb_rx_queues * sizeof(int),
2271                                     0);
2272                 if (!intr_handle->intr_vec) {
2273                         PMD_INIT_LOG(ERR,
2274                                 "Failed to allocate %d rx_queues intr_vec",
2275                                 dev->data->nb_rx_queues);
2276                         return -ENOMEM;
2277                 }
2278         }
2279
2280         /* Initialize VSI */
2281         ret = i40e_dev_rxtx_init(pf);
2282         if (ret != I40E_SUCCESS) {
2283                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2284                 goto err_up;
2285         }
2286
2287         /* Map queues with MSIX interrupt */
2288         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2289                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2290         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2291         i40e_vsi_enable_queues_intr(main_vsi);
2292
2293         /* Map VMDQ VSI queues with MSIX interrupt */
2294         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2295                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2296                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2297                                           I40E_ITR_INDEX_DEFAULT);
2298                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2299         }
2300
2301         /* enable FDIR MSIX interrupt */
2302         if (pf->fdir.fdir_vsi) {
2303                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2304                                           I40E_ITR_INDEX_NONE);
2305                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2306         }
2307
2308         /* Enable all queues which have been configured */
2309         ret = i40e_dev_switch_queues(pf, TRUE);
2310         if (ret != I40E_SUCCESS) {
2311                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2312                 goto err_up;
2313         }
2314
2315         /* Enable receiving broadcast packets */
2316         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2317         if (ret != I40E_SUCCESS)
2318                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2319
2320         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2321                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2322                                                 true, NULL);
2323                 if (ret != I40E_SUCCESS)
2324                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2325         }
2326
2327         /* Enable the VLAN promiscuous mode. */
2328         if (pf->vfs) {
2329                 for (i = 0; i < pf->vf_num; i++) {
2330                         vsi = pf->vfs[i].vsi;
2331                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2332                                                      true, NULL);
2333                 }
2334         }
2335
2336         /* Enable mac loopback mode */
2337         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2338             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2339                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2340                 if (ret != I40E_SUCCESS) {
2341                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2342                         goto err_up;
2343                 }
2344         }
2345
2346         /* Apply link configure */
2347         ret = i40e_apply_link_speed(dev);
2348         if (I40E_SUCCESS != ret) {
2349                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2350                 goto err_up;
2351         }
2352
2353         if (!rte_intr_allow_others(intr_handle)) {
2354                 rte_intr_callback_unregister(intr_handle,
2355                                              i40e_dev_interrupt_handler,
2356                                              (void *)dev);
2357                 /* configure and enable device interrupt */
2358                 i40e_pf_config_irq0(hw, FALSE);
2359                 i40e_pf_enable_irq0(hw);
2360
2361                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2362                         PMD_INIT_LOG(INFO,
2363                                 "lsc won't enable because of no intr multiplex");
2364         } else {
2365                 ret = i40e_aq_set_phy_int_mask(hw,
2366                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2367                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2368                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2369                 if (ret != I40E_SUCCESS)
2370                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2371
2372                 /* Call get_link_info aq commond to enable/disable LSE */
2373                 i40e_dev_link_update(dev, 0);
2374         }
2375
2376         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2377                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2378                                   i40e_dev_alarm_handler, dev);
2379         } else {
2380                 /* enable uio intr after callback register */
2381                 rte_intr_enable(intr_handle);
2382         }
2383
2384         i40e_filter_restore(pf);
2385
2386         if (pf->tm_conf.root && !pf->tm_conf.committed)
2387                 PMD_DRV_LOG(WARNING,
2388                             "please call hierarchy_commit() "
2389                             "before starting the port");
2390
2391         return I40E_SUCCESS;
2392
2393 err_up:
2394         i40e_dev_switch_queues(pf, FALSE);
2395         i40e_dev_clear_queues(dev);
2396
2397         return ret;
2398 }
2399
2400 static void
2401 i40e_dev_stop(struct rte_eth_dev *dev)
2402 {
2403         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2404         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2405         struct i40e_vsi *main_vsi = pf->main_vsi;
2406         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2407         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2408         int i;
2409
2410         if (hw->adapter_stopped == 1)
2411                 return;
2412
2413         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2414                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2415                 rte_intr_enable(intr_handle);
2416         }
2417
2418         /* Disable all queues */
2419         i40e_dev_switch_queues(pf, FALSE);
2420
2421         /* un-map queues with interrupt registers */
2422         i40e_vsi_disable_queues_intr(main_vsi);
2423         i40e_vsi_queues_unbind_intr(main_vsi);
2424
2425         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2426                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2427                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2428         }
2429
2430         if (pf->fdir.fdir_vsi) {
2431                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2432                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2433         }
2434         /* Clear all queues and release memory */
2435         i40e_dev_clear_queues(dev);
2436
2437         /* Set link down */
2438         i40e_dev_set_link_down(dev);
2439
2440         if (!rte_intr_allow_others(intr_handle))
2441                 /* resume to the default handler */
2442                 rte_intr_callback_register(intr_handle,
2443                                            i40e_dev_interrupt_handler,
2444                                            (void *)dev);
2445
2446         /* Clean datapath event and queue/vec mapping */
2447         rte_intr_efd_disable(intr_handle);
2448         if (intr_handle->intr_vec) {
2449                 rte_free(intr_handle->intr_vec);
2450                 intr_handle->intr_vec = NULL;
2451         }
2452
2453         /* reset hierarchy commit */
2454         pf->tm_conf.committed = false;
2455
2456         hw->adapter_stopped = 1;
2457
2458         pf->adapter->rss_reta_updated = 0;
2459 }
2460
2461 static void
2462 i40e_dev_close(struct rte_eth_dev *dev)
2463 {
2464         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2465         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2467         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2468         struct i40e_mirror_rule *p_mirror;
2469         uint32_t reg;
2470         int i;
2471         int ret;
2472
2473         PMD_INIT_FUNC_TRACE();
2474
2475         i40e_dev_stop(dev);
2476
2477         /* Remove all mirror rules */
2478         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2479                 ret = i40e_aq_del_mirror_rule(hw,
2480                                               pf->main_vsi->veb->seid,
2481                                               p_mirror->rule_type,
2482                                               p_mirror->entries,
2483                                               p_mirror->num_entries,
2484                                               p_mirror->id);
2485                 if (ret < 0)
2486                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2487                                     "status = %d, aq_err = %d.", ret,
2488                                     hw->aq.asq_last_status);
2489
2490                 /* remove mirror software resource anyway */
2491                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2492                 rte_free(p_mirror);
2493                 pf->nb_mirror_rule--;
2494         }
2495
2496         i40e_dev_free_queues(dev);
2497
2498         /* Disable interrupt */
2499         i40e_pf_disable_irq0(hw);
2500         rte_intr_disable(intr_handle);
2501
2502         /*
2503          * Only legacy filter API needs the following fdir config. So when the
2504          * legacy filter API is deprecated, the following code should also be
2505          * removed.
2506          */
2507         i40e_fdir_teardown(pf);
2508
2509         /* shutdown and destroy the HMC */
2510         i40e_shutdown_lan_hmc(hw);
2511
2512         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2513                 i40e_vsi_release(pf->vmdq[i].vsi);
2514                 pf->vmdq[i].vsi = NULL;
2515         }
2516         rte_free(pf->vmdq);
2517         pf->vmdq = NULL;
2518
2519         /* release all the existing VSIs and VEBs */
2520         i40e_vsi_release(pf->main_vsi);
2521
2522         /* shutdown the adminq */
2523         i40e_aq_queue_shutdown(hw, true);
2524         i40e_shutdown_adminq(hw);
2525
2526         i40e_res_pool_destroy(&pf->qp_pool);
2527         i40e_res_pool_destroy(&pf->msix_pool);
2528
2529         /* Disable flexible payload in global configuration */
2530         if (!pf->support_multi_driver)
2531                 i40e_flex_payload_reg_set_default(hw);
2532
2533         /* force a PF reset to clean anything leftover */
2534         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2535         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2536                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2537         I40E_WRITE_FLUSH(hw);
2538
2539         hw->adapter_closed = 1;
2540 }
2541
2542 /*
2543  * Reset PF device only to re-initialize resources in PMD layer
2544  */
2545 static int
2546 i40e_dev_reset(struct rte_eth_dev *dev)
2547 {
2548         int ret;
2549
2550         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2551          * its VF to make them align with it. The detailed notification
2552          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2553          * To avoid unexpected behavior in VF, currently reset of PF with
2554          * SR-IOV activation is not supported. It might be supported later.
2555          */
2556         if (dev->data->sriov.active)
2557                 return -ENOTSUP;
2558
2559         ret = eth_i40e_dev_uninit(dev);
2560         if (ret)
2561                 return ret;
2562
2563         ret = eth_i40e_dev_init(dev, NULL);
2564
2565         return ret;
2566 }
2567
2568 static void
2569 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2570 {
2571         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2572         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2573         struct i40e_vsi *vsi = pf->main_vsi;
2574         int status;
2575
2576         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2577                                                      true, NULL, true);
2578         if (status != I40E_SUCCESS)
2579                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2580
2581         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2582                                                         TRUE, NULL);
2583         if (status != I40E_SUCCESS)
2584                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2585
2586 }
2587
2588 static void
2589 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2590 {
2591         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2592         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2593         struct i40e_vsi *vsi = pf->main_vsi;
2594         int status;
2595
2596         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2597                                                      false, NULL, true);
2598         if (status != I40E_SUCCESS)
2599                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2600
2601         /* must remain in all_multicast mode */
2602         if (dev->data->all_multicast == 1)
2603                 return;
2604
2605         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2606                                                         false, NULL);
2607         if (status != I40E_SUCCESS)
2608                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2609 }
2610
2611 static void
2612 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2613 {
2614         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616         struct i40e_vsi *vsi = pf->main_vsi;
2617         int ret;
2618
2619         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2620         if (ret != I40E_SUCCESS)
2621                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2622 }
2623
2624 static void
2625 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2626 {
2627         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2628         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2629         struct i40e_vsi *vsi = pf->main_vsi;
2630         int ret;
2631
2632         if (dev->data->promiscuous == 1)
2633                 return; /* must remain in all_multicast mode */
2634
2635         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2636                                 vsi->seid, FALSE, NULL);
2637         if (ret != I40E_SUCCESS)
2638                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2639 }
2640
2641 /*
2642  * Set device link up.
2643  */
2644 static int
2645 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2646 {
2647         /* re-apply link speed setting */
2648         return i40e_apply_link_speed(dev);
2649 }
2650
2651 /*
2652  * Set device link down.
2653  */
2654 static int
2655 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2656 {
2657         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2658         uint8_t abilities = 0;
2659         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2660
2661         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2662         return i40e_phy_conf_link(hw, abilities, speed, false);
2663 }
2664
2665 static __rte_always_inline void
2666 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2667 {
2668 /* Link status registers and values*/
2669 #define I40E_PRTMAC_LINKSTA             0x001E2420
2670 #define I40E_REG_LINK_UP                0x40000080
2671 #define I40E_PRTMAC_MACC                0x001E24E0
2672 #define I40E_REG_MACC_25GB              0x00020000
2673 #define I40E_REG_SPEED_MASK             0x38000000
2674 #define I40E_REG_SPEED_100MB            0x00000000
2675 #define I40E_REG_SPEED_1GB              0x08000000
2676 #define I40E_REG_SPEED_10GB             0x10000000
2677 #define I40E_REG_SPEED_20GB             0x20000000
2678 #define I40E_REG_SPEED_25_40GB          0x18000000
2679         uint32_t link_speed;
2680         uint32_t reg_val;
2681
2682         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2683         link_speed = reg_val & I40E_REG_SPEED_MASK;
2684         reg_val &= I40E_REG_LINK_UP;
2685         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2686
2687         if (unlikely(link->link_status == 0))
2688                 return;
2689
2690         /* Parse the link status */
2691         switch (link_speed) {
2692         case I40E_REG_SPEED_100MB:
2693                 link->link_speed = ETH_SPEED_NUM_100M;
2694                 break;
2695         case I40E_REG_SPEED_1GB:
2696                 link->link_speed = ETH_SPEED_NUM_1G;
2697                 break;
2698         case I40E_REG_SPEED_10GB:
2699                 link->link_speed = ETH_SPEED_NUM_10G;
2700                 break;
2701         case I40E_REG_SPEED_20GB:
2702                 link->link_speed = ETH_SPEED_NUM_20G;
2703                 break;
2704         case I40E_REG_SPEED_25_40GB:
2705                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2706
2707                 if (reg_val & I40E_REG_MACC_25GB)
2708                         link->link_speed = ETH_SPEED_NUM_25G;
2709                 else
2710                         link->link_speed = ETH_SPEED_NUM_40G;
2711
2712                 break;
2713         default:
2714                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2715                 break;
2716         }
2717 }
2718
2719 static __rte_always_inline void
2720 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2721         bool enable_lse, int wait_to_complete)
2722 {
2723 #define CHECK_INTERVAL             100  /* 100ms */
2724 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2725         uint32_t rep_cnt = MAX_REPEAT_TIME;
2726         struct i40e_link_status link_status;
2727         int status;
2728
2729         memset(&link_status, 0, sizeof(link_status));
2730
2731         do {
2732                 memset(&link_status, 0, sizeof(link_status));
2733
2734                 /* Get link status information from hardware */
2735                 status = i40e_aq_get_link_info(hw, enable_lse,
2736                                                 &link_status, NULL);
2737                 if (unlikely(status != I40E_SUCCESS)) {
2738                         link->link_speed = ETH_SPEED_NUM_100M;
2739                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2740                         PMD_DRV_LOG(ERR, "Failed to get link info");
2741                         return;
2742                 }
2743
2744                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2745                 if (!wait_to_complete || link->link_status)
2746                         break;
2747
2748                 rte_delay_ms(CHECK_INTERVAL);
2749         } while (--rep_cnt);
2750
2751         /* Parse the link status */
2752         switch (link_status.link_speed) {
2753         case I40E_LINK_SPEED_100MB:
2754                 link->link_speed = ETH_SPEED_NUM_100M;
2755                 break;
2756         case I40E_LINK_SPEED_1GB:
2757                 link->link_speed = ETH_SPEED_NUM_1G;
2758                 break;
2759         case I40E_LINK_SPEED_10GB:
2760                 link->link_speed = ETH_SPEED_NUM_10G;
2761                 break;
2762         case I40E_LINK_SPEED_20GB:
2763                 link->link_speed = ETH_SPEED_NUM_20G;
2764                 break;
2765         case I40E_LINK_SPEED_25GB:
2766                 link->link_speed = ETH_SPEED_NUM_25G;
2767                 break;
2768         case I40E_LINK_SPEED_40GB:
2769                 link->link_speed = ETH_SPEED_NUM_40G;
2770                 break;
2771         default:
2772                 link->link_speed = ETH_SPEED_NUM_100M;
2773                 break;
2774         }
2775 }
2776
2777 int
2778 i40e_dev_link_update(struct rte_eth_dev *dev,
2779                      int wait_to_complete)
2780 {
2781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782         struct rte_eth_link link;
2783         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2784         int ret;
2785
2786         memset(&link, 0, sizeof(link));
2787
2788         /* i40e uses full duplex only */
2789         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2790         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2791                         ETH_LINK_SPEED_FIXED);
2792
2793         if (!wait_to_complete && !enable_lse)
2794                 update_link_reg(hw, &link);
2795         else
2796                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2797
2798         ret = rte_eth_linkstatus_set(dev, &link);
2799         i40e_notify_all_vfs_link_status(dev);
2800
2801         return ret;
2802 }
2803
2804 /* Get all the statistics of a VSI */
2805 void
2806 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2807 {
2808         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2809         struct i40e_eth_stats *nes = &vsi->eth_stats;
2810         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2811         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2812
2813         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2814                             vsi->offset_loaded, &oes->rx_bytes,
2815                             &nes->rx_bytes);
2816         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2817                             vsi->offset_loaded, &oes->rx_unicast,
2818                             &nes->rx_unicast);
2819         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2820                             vsi->offset_loaded, &oes->rx_multicast,
2821                             &nes->rx_multicast);
2822         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2823                             vsi->offset_loaded, &oes->rx_broadcast,
2824                             &nes->rx_broadcast);
2825         /* exclude CRC bytes */
2826         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2827                 nes->rx_broadcast) * ETHER_CRC_LEN;
2828
2829         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2830                             &oes->rx_discards, &nes->rx_discards);
2831         /* GLV_REPC not supported */
2832         /* GLV_RMPC not supported */
2833         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2834                             &oes->rx_unknown_protocol,
2835                             &nes->rx_unknown_protocol);
2836         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2837                             vsi->offset_loaded, &oes->tx_bytes,
2838                             &nes->tx_bytes);
2839         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2840                             vsi->offset_loaded, &oes->tx_unicast,
2841                             &nes->tx_unicast);
2842         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2843                             vsi->offset_loaded, &oes->tx_multicast,
2844                             &nes->tx_multicast);
2845         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2846                             vsi->offset_loaded,  &oes->tx_broadcast,
2847                             &nes->tx_broadcast);
2848         /* GLV_TDPC not supported */
2849         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2850                             &oes->tx_errors, &nes->tx_errors);
2851         vsi->offset_loaded = true;
2852
2853         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2854                     vsi->vsi_id);
2855         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2856         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2857         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2858         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2859         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2860         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2861                     nes->rx_unknown_protocol);
2862         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2863         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2864         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2865         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2866         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2867         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2868         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2869                     vsi->vsi_id);
2870 }
2871
2872 static void
2873 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2874 {
2875         unsigned int i;
2876         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2877         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2878
2879         /* Get rx/tx bytes of internal transfer packets */
2880         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2881                         I40E_GLV_GORCL(hw->port),
2882                         pf->offset_loaded,
2883                         &pf->internal_stats_offset.rx_bytes,
2884                         &pf->internal_stats.rx_bytes);
2885
2886         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2887                         I40E_GLV_GOTCL(hw->port),
2888                         pf->offset_loaded,
2889                         &pf->internal_stats_offset.tx_bytes,
2890                         &pf->internal_stats.tx_bytes);
2891         /* Get total internal rx packet count */
2892         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2893                             I40E_GLV_UPRCL(hw->port),
2894                             pf->offset_loaded,
2895                             &pf->internal_stats_offset.rx_unicast,
2896                             &pf->internal_stats.rx_unicast);
2897         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2898                             I40E_GLV_MPRCL(hw->port),
2899                             pf->offset_loaded,
2900                             &pf->internal_stats_offset.rx_multicast,
2901                             &pf->internal_stats.rx_multicast);
2902         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2903                             I40E_GLV_BPRCL(hw->port),
2904                             pf->offset_loaded,
2905                             &pf->internal_stats_offset.rx_broadcast,
2906                             &pf->internal_stats.rx_broadcast);
2907         /* Get total internal tx packet count */
2908         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2909                             I40E_GLV_UPTCL(hw->port),
2910                             pf->offset_loaded,
2911                             &pf->internal_stats_offset.tx_unicast,
2912                             &pf->internal_stats.tx_unicast);
2913         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2914                             I40E_GLV_MPTCL(hw->port),
2915                             pf->offset_loaded,
2916                             &pf->internal_stats_offset.tx_multicast,
2917                             &pf->internal_stats.tx_multicast);
2918         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2919                             I40E_GLV_BPTCL(hw->port),
2920                             pf->offset_loaded,
2921                             &pf->internal_stats_offset.tx_broadcast,
2922                             &pf->internal_stats.tx_broadcast);
2923
2924         /* exclude CRC size */
2925         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2926                 pf->internal_stats.rx_multicast +
2927                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2928
2929         /* Get statistics of struct i40e_eth_stats */
2930         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2931                             I40E_GLPRT_GORCL(hw->port),
2932                             pf->offset_loaded, &os->eth.rx_bytes,
2933                             &ns->eth.rx_bytes);
2934         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2935                             I40E_GLPRT_UPRCL(hw->port),
2936                             pf->offset_loaded, &os->eth.rx_unicast,
2937                             &ns->eth.rx_unicast);
2938         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2939                             I40E_GLPRT_MPRCL(hw->port),
2940                             pf->offset_loaded, &os->eth.rx_multicast,
2941                             &ns->eth.rx_multicast);
2942         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2943                             I40E_GLPRT_BPRCL(hw->port),
2944                             pf->offset_loaded, &os->eth.rx_broadcast,
2945                             &ns->eth.rx_broadcast);
2946         /* Workaround: CRC size should not be included in byte statistics,
2947          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2948          */
2949         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2950                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2951
2952         /* exclude internal rx bytes
2953          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2954          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2955          * value.
2956          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2957          */
2958         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2959                 ns->eth.rx_bytes = 0;
2960         else
2961                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2962
2963         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2964                 ns->eth.rx_unicast = 0;
2965         else
2966                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2967
2968         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2969                 ns->eth.rx_multicast = 0;
2970         else
2971                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2972
2973         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2974                 ns->eth.rx_broadcast = 0;
2975         else
2976                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2977
2978         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2979                             pf->offset_loaded, &os->eth.rx_discards,
2980                             &ns->eth.rx_discards);
2981         /* GLPRT_REPC not supported */
2982         /* GLPRT_RMPC not supported */
2983         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2984                             pf->offset_loaded,
2985                             &os->eth.rx_unknown_protocol,
2986                             &ns->eth.rx_unknown_protocol);
2987         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2988                             I40E_GLPRT_GOTCL(hw->port),
2989                             pf->offset_loaded, &os->eth.tx_bytes,
2990                             &ns->eth.tx_bytes);
2991         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2992                             I40E_GLPRT_UPTCL(hw->port),
2993                             pf->offset_loaded, &os->eth.tx_unicast,
2994                             &ns->eth.tx_unicast);
2995         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2996                             I40E_GLPRT_MPTCL(hw->port),
2997                             pf->offset_loaded, &os->eth.tx_multicast,
2998                             &ns->eth.tx_multicast);
2999         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3000                             I40E_GLPRT_BPTCL(hw->port),
3001                             pf->offset_loaded, &os->eth.tx_broadcast,
3002                             &ns->eth.tx_broadcast);
3003         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3004                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
3005
3006         /* exclude internal tx bytes
3007          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3008          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3009          * value.
3010          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3011          */
3012         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3013                 ns->eth.tx_bytes = 0;
3014         else
3015                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3016
3017         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3018                 ns->eth.tx_unicast = 0;
3019         else
3020                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3021
3022         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3023                 ns->eth.tx_multicast = 0;
3024         else
3025                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3026
3027         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3028                 ns->eth.tx_broadcast = 0;
3029         else
3030                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3031
3032         /* GLPRT_TEPC not supported */
3033
3034         /* additional port specific stats */
3035         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3036                             pf->offset_loaded, &os->tx_dropped_link_down,
3037                             &ns->tx_dropped_link_down);
3038         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3039                             pf->offset_loaded, &os->crc_errors,
3040                             &ns->crc_errors);
3041         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3042                             pf->offset_loaded, &os->illegal_bytes,
3043                             &ns->illegal_bytes);
3044         /* GLPRT_ERRBC not supported */
3045         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3046                             pf->offset_loaded, &os->mac_local_faults,
3047                             &ns->mac_local_faults);
3048         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3049                             pf->offset_loaded, &os->mac_remote_faults,
3050                             &ns->mac_remote_faults);
3051         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3052                             pf->offset_loaded, &os->rx_length_errors,
3053                             &ns->rx_length_errors);
3054         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3055                             pf->offset_loaded, &os->link_xon_rx,
3056                             &ns->link_xon_rx);
3057         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3058                             pf->offset_loaded, &os->link_xoff_rx,
3059                             &ns->link_xoff_rx);
3060         for (i = 0; i < 8; i++) {
3061                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3062                                     pf->offset_loaded,
3063                                     &os->priority_xon_rx[i],
3064                                     &ns->priority_xon_rx[i]);
3065                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3066                                     pf->offset_loaded,
3067                                     &os->priority_xoff_rx[i],
3068                                     &ns->priority_xoff_rx[i]);
3069         }
3070         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3071                             pf->offset_loaded, &os->link_xon_tx,
3072                             &ns->link_xon_tx);
3073         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3074                             pf->offset_loaded, &os->link_xoff_tx,
3075                             &ns->link_xoff_tx);
3076         for (i = 0; i < 8; i++) {
3077                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3078                                     pf->offset_loaded,
3079                                     &os->priority_xon_tx[i],
3080                                     &ns->priority_xon_tx[i]);
3081                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3082                                     pf->offset_loaded,
3083                                     &os->priority_xoff_tx[i],
3084                                     &ns->priority_xoff_tx[i]);
3085                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3086                                     pf->offset_loaded,
3087                                     &os->priority_xon_2_xoff[i],
3088                                     &ns->priority_xon_2_xoff[i]);
3089         }
3090         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3091                             I40E_GLPRT_PRC64L(hw->port),
3092                             pf->offset_loaded, &os->rx_size_64,
3093                             &ns->rx_size_64);
3094         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3095                             I40E_GLPRT_PRC127L(hw->port),
3096                             pf->offset_loaded, &os->rx_size_127,
3097                             &ns->rx_size_127);
3098         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3099                             I40E_GLPRT_PRC255L(hw->port),
3100                             pf->offset_loaded, &os->rx_size_255,
3101                             &ns->rx_size_255);
3102         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3103                             I40E_GLPRT_PRC511L(hw->port),
3104                             pf->offset_loaded, &os->rx_size_511,
3105                             &ns->rx_size_511);
3106         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3107                             I40E_GLPRT_PRC1023L(hw->port),
3108                             pf->offset_loaded, &os->rx_size_1023,
3109                             &ns->rx_size_1023);
3110         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3111                             I40E_GLPRT_PRC1522L(hw->port),
3112                             pf->offset_loaded, &os->rx_size_1522,
3113                             &ns->rx_size_1522);
3114         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3115                             I40E_GLPRT_PRC9522L(hw->port),
3116                             pf->offset_loaded, &os->rx_size_big,
3117                             &ns->rx_size_big);
3118         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3119                             pf->offset_loaded, &os->rx_undersize,
3120                             &ns->rx_undersize);
3121         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3122                             pf->offset_loaded, &os->rx_fragments,
3123                             &ns->rx_fragments);
3124         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3125                             pf->offset_loaded, &os->rx_oversize,
3126                             &ns->rx_oversize);
3127         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3128                             pf->offset_loaded, &os->rx_jabber,
3129                             &ns->rx_jabber);
3130         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3131                             I40E_GLPRT_PTC64L(hw->port),
3132                             pf->offset_loaded, &os->tx_size_64,
3133                             &ns->tx_size_64);
3134         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3135                             I40E_GLPRT_PTC127L(hw->port),
3136                             pf->offset_loaded, &os->tx_size_127,
3137                             &ns->tx_size_127);
3138         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3139                             I40E_GLPRT_PTC255L(hw->port),
3140                             pf->offset_loaded, &os->tx_size_255,
3141                             &ns->tx_size_255);
3142         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3143                             I40E_GLPRT_PTC511L(hw->port),
3144                             pf->offset_loaded, &os->tx_size_511,
3145                             &ns->tx_size_511);
3146         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3147                             I40E_GLPRT_PTC1023L(hw->port),
3148                             pf->offset_loaded, &os->tx_size_1023,
3149                             &ns->tx_size_1023);
3150         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3151                             I40E_GLPRT_PTC1522L(hw->port),
3152                             pf->offset_loaded, &os->tx_size_1522,
3153                             &ns->tx_size_1522);
3154         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3155                             I40E_GLPRT_PTC9522L(hw->port),
3156                             pf->offset_loaded, &os->tx_size_big,
3157                             &ns->tx_size_big);
3158         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3159                            pf->offset_loaded,
3160                            &os->fd_sb_match, &ns->fd_sb_match);
3161         /* GLPRT_MSPDC not supported */
3162         /* GLPRT_XEC not supported */
3163
3164         pf->offset_loaded = true;
3165
3166         if (pf->main_vsi)
3167                 i40e_update_vsi_stats(pf->main_vsi);
3168 }
3169
3170 /* Get all statistics of a port */
3171 static int
3172 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3173 {
3174         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3175         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3176         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3177         struct i40e_vsi *vsi;
3178         unsigned i;
3179
3180         /* call read registers - updates values, now write them to struct */
3181         i40e_read_stats_registers(pf, hw);
3182
3183         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3184                         pf->main_vsi->eth_stats.rx_multicast +
3185                         pf->main_vsi->eth_stats.rx_broadcast -
3186                         pf->main_vsi->eth_stats.rx_discards;
3187         stats->opackets = ns->eth.tx_unicast +
3188                         ns->eth.tx_multicast +
3189                         ns->eth.tx_broadcast;
3190         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3191         stats->obytes   = ns->eth.tx_bytes;
3192         stats->oerrors  = ns->eth.tx_errors +
3193                         pf->main_vsi->eth_stats.tx_errors;
3194
3195         /* Rx Errors */
3196         stats->imissed  = ns->eth.rx_discards +
3197                         pf->main_vsi->eth_stats.rx_discards;
3198         stats->ierrors  = ns->crc_errors +
3199                         ns->rx_length_errors + ns->rx_undersize +
3200                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3201
3202         if (pf->vfs) {
3203                 for (i = 0; i < pf->vf_num; i++) {
3204                         vsi = pf->vfs[i].vsi;
3205                         i40e_update_vsi_stats(vsi);
3206
3207                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3208                                         vsi->eth_stats.rx_multicast +
3209                                         vsi->eth_stats.rx_broadcast -
3210                                         vsi->eth_stats.rx_discards);
3211                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3212                         stats->oerrors  += vsi->eth_stats.tx_errors;
3213                         stats->imissed  += vsi->eth_stats.rx_discards;
3214                 }
3215         }
3216
3217         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3218         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3219         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3220         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3221         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3222         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3223         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3224                     ns->eth.rx_unknown_protocol);
3225         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3226         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3227         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3228         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3229         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3230         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3231
3232         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3233                     ns->tx_dropped_link_down);
3234         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3235         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3236                     ns->illegal_bytes);
3237         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3238         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3239                     ns->mac_local_faults);
3240         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3241                     ns->mac_remote_faults);
3242         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3243                     ns->rx_length_errors);
3244         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3245         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3246         for (i = 0; i < 8; i++) {
3247                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3248                                 i, ns->priority_xon_rx[i]);
3249                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3250                                 i, ns->priority_xoff_rx[i]);
3251         }
3252         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3253         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3254         for (i = 0; i < 8; i++) {
3255                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3256                                 i, ns->priority_xon_tx[i]);
3257                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3258                                 i, ns->priority_xoff_tx[i]);
3259                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3260                                 i, ns->priority_xon_2_xoff[i]);
3261         }
3262         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3263         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3264         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3265         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3266         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3267         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3268         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3269         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3270         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3271         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3272         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3273         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3274         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3275         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3276         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3277         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3278         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3279         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3280         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3281                         ns->mac_short_packet_dropped);
3282         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3283                     ns->checksum_error);
3284         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3285         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3286         return 0;
3287 }
3288
3289 /* Reset the statistics */
3290 static void
3291 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3292 {
3293         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3294         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3295
3296         /* Mark PF and VSI stats to update the offset, aka "reset" */
3297         pf->offset_loaded = false;
3298         if (pf->main_vsi)
3299                 pf->main_vsi->offset_loaded = false;
3300
3301         /* read the stats, reading current register values into offset */
3302         i40e_read_stats_registers(pf, hw);
3303 }
3304
3305 static uint32_t
3306 i40e_xstats_calc_num(void)
3307 {
3308         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3309                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3310                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3311 }
3312
3313 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3314                                      struct rte_eth_xstat_name *xstats_names,
3315                                      __rte_unused unsigned limit)
3316 {
3317         unsigned count = 0;
3318         unsigned i, prio;
3319
3320         if (xstats_names == NULL)
3321                 return i40e_xstats_calc_num();
3322
3323         /* Note: limit checked in rte_eth_xstats_names() */
3324
3325         /* Get stats from i40e_eth_stats struct */
3326         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3327                 snprintf(xstats_names[count].name,
3328                          sizeof(xstats_names[count].name),
3329                          "%s", rte_i40e_stats_strings[i].name);
3330                 count++;
3331         }
3332
3333         /* Get individiual stats from i40e_hw_port struct */
3334         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3335                 snprintf(xstats_names[count].name,
3336                         sizeof(xstats_names[count].name),
3337                          "%s", rte_i40e_hw_port_strings[i].name);
3338                 count++;
3339         }
3340
3341         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3342                 for (prio = 0; prio < 8; prio++) {
3343                         snprintf(xstats_names[count].name,
3344                                  sizeof(xstats_names[count].name),
3345                                  "rx_priority%u_%s", prio,
3346                                  rte_i40e_rxq_prio_strings[i].name);
3347                         count++;
3348                 }
3349         }
3350
3351         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3352                 for (prio = 0; prio < 8; prio++) {
3353                         snprintf(xstats_names[count].name,
3354                                  sizeof(xstats_names[count].name),
3355                                  "tx_priority%u_%s", prio,
3356                                  rte_i40e_txq_prio_strings[i].name);
3357                         count++;
3358                 }
3359         }
3360         return count;
3361 }
3362
3363 static int
3364 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3365                     unsigned n)
3366 {
3367         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3368         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3369         unsigned i, count, prio;
3370         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3371
3372         count = i40e_xstats_calc_num();
3373         if (n < count)
3374                 return count;
3375
3376         i40e_read_stats_registers(pf, hw);
3377
3378         if (xstats == NULL)
3379                 return 0;
3380
3381         count = 0;
3382
3383         /* Get stats from i40e_eth_stats struct */
3384         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3385                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3386                         rte_i40e_stats_strings[i].offset);
3387                 xstats[count].id = count;
3388                 count++;
3389         }
3390
3391         /* Get individiual stats from i40e_hw_port struct */
3392         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3393                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3394                         rte_i40e_hw_port_strings[i].offset);
3395                 xstats[count].id = count;
3396                 count++;
3397         }
3398
3399         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3400                 for (prio = 0; prio < 8; prio++) {
3401                         xstats[count].value =
3402                                 *(uint64_t *)(((char *)hw_stats) +
3403                                 rte_i40e_rxq_prio_strings[i].offset +
3404                                 (sizeof(uint64_t) * prio));
3405                         xstats[count].id = count;
3406                         count++;
3407                 }
3408         }
3409
3410         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3411                 for (prio = 0; prio < 8; prio++) {
3412                         xstats[count].value =
3413                                 *(uint64_t *)(((char *)hw_stats) +
3414                                 rte_i40e_txq_prio_strings[i].offset +
3415                                 (sizeof(uint64_t) * prio));
3416                         xstats[count].id = count;
3417                         count++;
3418                 }
3419         }
3420
3421         return count;
3422 }
3423
3424 static int
3425 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3426                                  __rte_unused uint16_t queue_id,
3427                                  __rte_unused uint8_t stat_idx,
3428                                  __rte_unused uint8_t is_rx)
3429 {
3430         PMD_INIT_FUNC_TRACE();
3431
3432         return -ENOSYS;
3433 }
3434
3435 static int
3436 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3437 {
3438         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3439         u32 full_ver;
3440         u8 ver, patch;
3441         u16 build;
3442         int ret;
3443
3444         full_ver = hw->nvm.oem_ver;
3445         ver = (u8)(full_ver >> 24);
3446         build = (u16)((full_ver >> 8) & 0xffff);
3447         patch = (u8)(full_ver & 0xff);
3448
3449         ret = snprintf(fw_version, fw_size,
3450                  "%d.%d%d 0x%08x %d.%d.%d",
3451                  ((hw->nvm.version >> 12) & 0xf),
3452                  ((hw->nvm.version >> 4) & 0xff),
3453                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3454                  ver, build, patch);
3455
3456         ret += 1; /* add the size of '\0' */
3457         if (fw_size < (u32)ret)
3458                 return ret;
3459         else
3460                 return 0;
3461 }
3462
3463 static void
3464 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3465 {
3466         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3467         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3468         struct i40e_vsi *vsi = pf->main_vsi;
3469         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3470
3471         dev_info->max_rx_queues = vsi->nb_qps;
3472         dev_info->max_tx_queues = vsi->nb_qps;
3473         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3474         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3475         dev_info->max_mac_addrs = vsi->max_macaddrs;
3476         dev_info->max_vfs = pci_dev->max_vfs;
3477         dev_info->rx_queue_offload_capa = 0;
3478         dev_info->rx_offload_capa =
3479                 DEV_RX_OFFLOAD_VLAN_STRIP |
3480                 DEV_RX_OFFLOAD_QINQ_STRIP |
3481                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3482                 DEV_RX_OFFLOAD_UDP_CKSUM |
3483                 DEV_RX_OFFLOAD_TCP_CKSUM |
3484                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3485                 DEV_RX_OFFLOAD_KEEP_CRC |
3486                 DEV_RX_OFFLOAD_SCATTER |
3487                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3488                 DEV_RX_OFFLOAD_VLAN_FILTER |
3489                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3490
3491         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3492         dev_info->tx_offload_capa =
3493                 DEV_TX_OFFLOAD_VLAN_INSERT |
3494                 DEV_TX_OFFLOAD_QINQ_INSERT |
3495                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3496                 DEV_TX_OFFLOAD_UDP_CKSUM |
3497                 DEV_TX_OFFLOAD_TCP_CKSUM |
3498                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3499                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3500                 DEV_TX_OFFLOAD_TCP_TSO |
3501                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3502                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3503                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3504                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3505                 DEV_TX_OFFLOAD_MULTI_SEGS |
3506                 dev_info->tx_queue_offload_capa;
3507         dev_info->dev_capa =
3508                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3509                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3510
3511         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3512                                                 sizeof(uint32_t);
3513         dev_info->reta_size = pf->hash_lut_size;
3514         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3515
3516         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3517                 .rx_thresh = {
3518                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3519                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3520                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3521                 },
3522                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3523                 .rx_drop_en = 0,
3524                 .offloads = 0,
3525         };
3526
3527         dev_info->default_txconf = (struct rte_eth_txconf) {
3528                 .tx_thresh = {
3529                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3530                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3531                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3532                 },
3533                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3534                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3535                 .offloads = 0,
3536         };
3537
3538         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3539                 .nb_max = I40E_MAX_RING_DESC,
3540                 .nb_min = I40E_MIN_RING_DESC,
3541                 .nb_align = I40E_ALIGN_RING_DESC,
3542         };
3543
3544         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3545                 .nb_max = I40E_MAX_RING_DESC,
3546                 .nb_min = I40E_MIN_RING_DESC,
3547                 .nb_align = I40E_ALIGN_RING_DESC,
3548                 .nb_seg_max = I40E_TX_MAX_SEG,
3549                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3550         };
3551
3552         if (pf->flags & I40E_FLAG_VMDQ) {
3553                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3554                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3555                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3556                                                 pf->max_nb_vmdq_vsi;
3557                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3558                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3559                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3560         }
3561
3562         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3563                 /* For XL710 */
3564                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3565                 dev_info->default_rxportconf.nb_queues = 2;
3566                 dev_info->default_txportconf.nb_queues = 2;
3567                 if (dev->data->nb_rx_queues == 1)
3568                         dev_info->default_rxportconf.ring_size = 2048;
3569                 else
3570                         dev_info->default_rxportconf.ring_size = 1024;
3571                 if (dev->data->nb_tx_queues == 1)
3572                         dev_info->default_txportconf.ring_size = 1024;
3573                 else
3574                         dev_info->default_txportconf.ring_size = 512;
3575
3576         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3577                 /* For XXV710 */
3578                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3579                 dev_info->default_rxportconf.nb_queues = 1;
3580                 dev_info->default_txportconf.nb_queues = 1;
3581                 dev_info->default_rxportconf.ring_size = 256;
3582                 dev_info->default_txportconf.ring_size = 256;
3583         } else {
3584                 /* For X710 */
3585                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3586                 dev_info->default_rxportconf.nb_queues = 1;
3587                 dev_info->default_txportconf.nb_queues = 1;
3588                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3589                         dev_info->default_rxportconf.ring_size = 512;
3590                         dev_info->default_txportconf.ring_size = 256;
3591                 } else {
3592                         dev_info->default_rxportconf.ring_size = 256;
3593                         dev_info->default_txportconf.ring_size = 256;
3594                 }
3595         }
3596         dev_info->default_rxportconf.burst_size = 32;
3597         dev_info->default_txportconf.burst_size = 32;
3598 }
3599
3600 static int
3601 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3602 {
3603         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3604         struct i40e_vsi *vsi = pf->main_vsi;
3605         PMD_INIT_FUNC_TRACE();
3606
3607         if (on)
3608                 return i40e_vsi_add_vlan(vsi, vlan_id);
3609         else
3610                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3611 }
3612
3613 static int
3614 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3615                                 enum rte_vlan_type vlan_type,
3616                                 uint16_t tpid, int qinq)
3617 {
3618         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3619         uint64_t reg_r = 0;
3620         uint64_t reg_w = 0;
3621         uint16_t reg_id = 3;
3622         int ret;
3623
3624         if (qinq) {
3625                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3626                         reg_id = 2;
3627         }
3628
3629         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3630                                           &reg_r, NULL);
3631         if (ret != I40E_SUCCESS) {
3632                 PMD_DRV_LOG(ERR,
3633                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3634                            reg_id);
3635                 return -EIO;
3636         }
3637         PMD_DRV_LOG(DEBUG,
3638                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3639                     reg_id, reg_r);
3640
3641         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3642         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3643         if (reg_r == reg_w) {
3644                 PMD_DRV_LOG(DEBUG, "No need to write");
3645                 return 0;
3646         }
3647
3648         ret = i40e_aq_debug_write_global_register(hw,
3649                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3650                                            reg_w, NULL);
3651         if (ret != I40E_SUCCESS) {
3652                 PMD_DRV_LOG(ERR,
3653                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3654                             reg_id);
3655                 return -EIO;
3656         }
3657         PMD_DRV_LOG(DEBUG,
3658                     "Global register 0x%08x is changed with value 0x%08x",
3659                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3660
3661         return 0;
3662 }
3663
3664 static int
3665 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3666                    enum rte_vlan_type vlan_type,
3667                    uint16_t tpid)
3668 {
3669         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3670         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3671         int qinq = dev->data->dev_conf.rxmode.offloads &
3672                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3673         int ret = 0;
3674
3675         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3676              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3677             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3678                 PMD_DRV_LOG(ERR,
3679                             "Unsupported vlan type.");
3680                 return -EINVAL;
3681         }
3682
3683         if (pf->support_multi_driver) {
3684                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3685                 return -ENOTSUP;
3686         }
3687
3688         /* 802.1ad frames ability is added in NVM API 1.7*/
3689         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3690                 if (qinq) {
3691                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3692                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3693                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3694                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3695                 } else {
3696                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3697                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3698                 }
3699                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3700                 if (ret != I40E_SUCCESS) {
3701                         PMD_DRV_LOG(ERR,
3702                                     "Set switch config failed aq_err: %d",
3703                                     hw->aq.asq_last_status);
3704                         ret = -EIO;
3705                 }
3706         } else
3707                 /* If NVM API < 1.7, keep the register setting */
3708                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3709                                                       tpid, qinq);
3710
3711         return ret;
3712 }
3713
3714 static int
3715 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3716 {
3717         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3718         struct i40e_vsi *vsi = pf->main_vsi;
3719         struct rte_eth_rxmode *rxmode;
3720
3721         rxmode = &dev->data->dev_conf.rxmode;
3722         if (mask & ETH_VLAN_FILTER_MASK) {
3723                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3724                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3725                 else
3726                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3727         }
3728
3729         if (mask & ETH_VLAN_STRIP_MASK) {
3730                 /* Enable or disable VLAN stripping */
3731                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3732                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3733                 else
3734                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3735         }
3736
3737         if (mask & ETH_VLAN_EXTEND_MASK) {
3738                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3739                         i40e_vsi_config_double_vlan(vsi, TRUE);
3740                         /* Set global registers with default ethertype. */
3741                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3742                                            ETHER_TYPE_VLAN);
3743                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3744                                            ETHER_TYPE_VLAN);
3745                 }
3746                 else
3747                         i40e_vsi_config_double_vlan(vsi, FALSE);
3748         }
3749
3750         return 0;
3751 }
3752
3753 static void
3754 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3755                           __rte_unused uint16_t queue,
3756                           __rte_unused int on)
3757 {
3758         PMD_INIT_FUNC_TRACE();
3759 }
3760
3761 static int
3762 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3763 {
3764         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3765         struct i40e_vsi *vsi = pf->main_vsi;
3766         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3767         struct i40e_vsi_vlan_pvid_info info;
3768
3769         memset(&info, 0, sizeof(info));
3770         info.on = on;
3771         if (info.on)
3772                 info.config.pvid = pvid;
3773         else {
3774                 info.config.reject.tagged =
3775                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3776                 info.config.reject.untagged =
3777                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3778         }
3779
3780         return i40e_vsi_vlan_pvid_set(vsi, &info);
3781 }
3782
3783 static int
3784 i40e_dev_led_on(struct rte_eth_dev *dev)
3785 {
3786         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3787         uint32_t mode = i40e_led_get(hw);
3788
3789         if (mode == 0)
3790                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3791
3792         return 0;
3793 }
3794
3795 static int
3796 i40e_dev_led_off(struct rte_eth_dev *dev)
3797 {
3798         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3799         uint32_t mode = i40e_led_get(hw);
3800
3801         if (mode != 0)
3802                 i40e_led_set(hw, 0, false);
3803
3804         return 0;
3805 }
3806
3807 static int
3808 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3809 {
3810         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3811         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3812
3813         fc_conf->pause_time = pf->fc_conf.pause_time;
3814
3815         /* read out from register, in case they are modified by other port */
3816         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3817                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3818         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3819                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3820
3821         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3822         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3823
3824          /* Return current mode according to actual setting*/
3825         switch (hw->fc.current_mode) {
3826         case I40E_FC_FULL:
3827                 fc_conf->mode = RTE_FC_FULL;
3828                 break;
3829         case I40E_FC_TX_PAUSE:
3830                 fc_conf->mode = RTE_FC_TX_PAUSE;
3831                 break;
3832         case I40E_FC_RX_PAUSE:
3833                 fc_conf->mode = RTE_FC_RX_PAUSE;
3834                 break;
3835         case I40E_FC_NONE:
3836         default:
3837                 fc_conf->mode = RTE_FC_NONE;
3838         };
3839
3840         return 0;
3841 }
3842
3843 static int
3844 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3845 {
3846         uint32_t mflcn_reg, fctrl_reg, reg;
3847         uint32_t max_high_water;
3848         uint8_t i, aq_failure;
3849         int err;
3850         struct i40e_hw *hw;
3851         struct i40e_pf *pf;
3852         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3853                 [RTE_FC_NONE] = I40E_FC_NONE,
3854                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3855                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3856                 [RTE_FC_FULL] = I40E_FC_FULL
3857         };
3858
3859         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3860
3861         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3862         if ((fc_conf->high_water > max_high_water) ||
3863                         (fc_conf->high_water < fc_conf->low_water)) {
3864                 PMD_INIT_LOG(ERR,
3865                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3866                         max_high_water);
3867                 return -EINVAL;
3868         }
3869
3870         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3871         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3872         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3873
3874         pf->fc_conf.pause_time = fc_conf->pause_time;
3875         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3876         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3877
3878         PMD_INIT_FUNC_TRACE();
3879
3880         /* All the link flow control related enable/disable register
3881          * configuration is handle by the F/W
3882          */
3883         err = i40e_set_fc(hw, &aq_failure, true);
3884         if (err < 0)
3885                 return -ENOSYS;
3886
3887         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3888                 /* Configure flow control refresh threshold,
3889                  * the value for stat_tx_pause_refresh_timer[8]
3890                  * is used for global pause operation.
3891                  */
3892
3893                 I40E_WRITE_REG(hw,
3894                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3895                                pf->fc_conf.pause_time);
3896
3897                 /* configure the timer value included in transmitted pause
3898                  * frame,
3899                  * the value for stat_tx_pause_quanta[8] is used for global
3900                  * pause operation
3901                  */
3902                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3903                                pf->fc_conf.pause_time);
3904
3905                 fctrl_reg = I40E_READ_REG(hw,
3906                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3907
3908                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3909                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3910                 else
3911                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3912
3913                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3914                                fctrl_reg);
3915         } else {
3916                 /* Configure pause time (2 TCs per register) */
3917                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3918                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3919                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3920
3921                 /* Configure flow control refresh threshold value */
3922                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3923                                pf->fc_conf.pause_time / 2);
3924
3925                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3926
3927                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3928                  *depending on configuration
3929                  */
3930                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3931                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3932                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3933                 } else {
3934                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3935                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3936                 }
3937
3938                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3939         }
3940
3941         if (!pf->support_multi_driver) {
3942                 /* config water marker both based on the packets and bytes */
3943                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3944                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3945                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3946                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3947                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3948                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3949                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3950                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3951                                   << I40E_KILOSHIFT);
3952                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3953                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3954                                    << I40E_KILOSHIFT);
3955         } else {
3956                 PMD_DRV_LOG(ERR,
3957                             "Water marker configuration is not supported.");
3958         }
3959
3960         I40E_WRITE_FLUSH(hw);
3961
3962         return 0;
3963 }
3964
3965 static int
3966 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3967                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3968 {
3969         PMD_INIT_FUNC_TRACE();
3970
3971         return -ENOSYS;
3972 }
3973
3974 /* Add a MAC address, and update filters */
3975 static int
3976 i40e_macaddr_add(struct rte_eth_dev *dev,
3977                  struct ether_addr *mac_addr,
3978                  __rte_unused uint32_t index,
3979                  uint32_t pool)
3980 {
3981         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3982         struct i40e_mac_filter_info mac_filter;
3983         struct i40e_vsi *vsi;
3984         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3985         int ret;
3986
3987         /* If VMDQ not enabled or configured, return */
3988         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3989                           !pf->nb_cfg_vmdq_vsi)) {
3990                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3991                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3992                         pool);
3993                 return -ENOTSUP;
3994         }
3995
3996         if (pool > pf->nb_cfg_vmdq_vsi) {
3997                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3998                                 pool, pf->nb_cfg_vmdq_vsi);
3999                 return -EINVAL;
4000         }
4001
4002         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
4003         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4004                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4005         else
4006                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4007
4008         if (pool == 0)
4009                 vsi = pf->main_vsi;
4010         else
4011                 vsi = pf->vmdq[pool - 1].vsi;
4012
4013         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4014         if (ret != I40E_SUCCESS) {
4015                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4016                 return -ENODEV;
4017         }
4018         return 0;
4019 }
4020
4021 /* Remove a MAC address, and update filters */
4022 static void
4023 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4024 {
4025         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4026         struct i40e_vsi *vsi;
4027         struct rte_eth_dev_data *data = dev->data;
4028         struct ether_addr *macaddr;
4029         int ret;
4030         uint32_t i;
4031         uint64_t pool_sel;
4032
4033         macaddr = &(data->mac_addrs[index]);
4034
4035         pool_sel = dev->data->mac_pool_sel[index];
4036
4037         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4038                 if (pool_sel & (1ULL << i)) {
4039                         if (i == 0)
4040                                 vsi = pf->main_vsi;
4041                         else {
4042                                 /* No VMDQ pool enabled or configured */
4043                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4044                                         (i > pf->nb_cfg_vmdq_vsi)) {
4045                                         PMD_DRV_LOG(ERR,
4046                                                 "No VMDQ pool enabled/configured");
4047                                         return;
4048                                 }
4049                                 vsi = pf->vmdq[i - 1].vsi;
4050                         }
4051                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4052
4053                         if (ret) {
4054                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4055                                 return;
4056                         }
4057                 }
4058         }
4059 }
4060
4061 /* Set perfect match or hash match of MAC and VLAN for a VF */
4062 static int
4063 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4064                  struct rte_eth_mac_filter *filter,
4065                  bool add)
4066 {
4067         struct i40e_hw *hw;
4068         struct i40e_mac_filter_info mac_filter;
4069         struct ether_addr old_mac;
4070         struct ether_addr *new_mac;
4071         struct i40e_pf_vf *vf = NULL;
4072         uint16_t vf_id;
4073         int ret;
4074
4075         if (pf == NULL) {
4076                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4077                 return -EINVAL;
4078         }
4079         hw = I40E_PF_TO_HW(pf);
4080
4081         if (filter == NULL) {
4082                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4083                 return -EINVAL;
4084         }
4085
4086         new_mac = &filter->mac_addr;
4087
4088         if (is_zero_ether_addr(new_mac)) {
4089                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4090                 return -EINVAL;
4091         }
4092
4093         vf_id = filter->dst_id;
4094
4095         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4096                 PMD_DRV_LOG(ERR, "Invalid argument.");
4097                 return -EINVAL;
4098         }
4099         vf = &pf->vfs[vf_id];
4100
4101         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
4102                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4103                 return -EINVAL;
4104         }
4105
4106         if (add) {
4107                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
4108                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4109                                 ETHER_ADDR_LEN);
4110                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4111                                  ETHER_ADDR_LEN);
4112
4113                 mac_filter.filter_type = filter->filter_type;
4114                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4115                 if (ret != I40E_SUCCESS) {
4116                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4117                         return -1;
4118                 }
4119                 ether_addr_copy(new_mac, &pf->dev_addr);
4120         } else {
4121                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4122                                 ETHER_ADDR_LEN);
4123                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4124                 if (ret != I40E_SUCCESS) {
4125                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4126                         return -1;
4127                 }
4128
4129                 /* Clear device address as it has been removed */
4130                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
4131                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
4132         }
4133
4134         return 0;
4135 }
4136
4137 /* MAC filter handle */
4138 static int
4139 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4140                 void *arg)
4141 {
4142         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4143         struct rte_eth_mac_filter *filter;
4144         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4145         int ret = I40E_NOT_SUPPORTED;
4146
4147         filter = (struct rte_eth_mac_filter *)(arg);
4148
4149         switch (filter_op) {
4150         case RTE_ETH_FILTER_NOP:
4151                 ret = I40E_SUCCESS;
4152                 break;
4153         case RTE_ETH_FILTER_ADD:
4154                 i40e_pf_disable_irq0(hw);
4155                 if (filter->is_vf)
4156                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4157                 i40e_pf_enable_irq0(hw);
4158                 break;
4159         case RTE_ETH_FILTER_DELETE:
4160                 i40e_pf_disable_irq0(hw);
4161                 if (filter->is_vf)
4162                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4163                 i40e_pf_enable_irq0(hw);
4164                 break;
4165         default:
4166                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4167                 ret = I40E_ERR_PARAM;
4168                 break;
4169         }
4170
4171         return ret;
4172 }
4173
4174 static int
4175 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4176 {
4177         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4178         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4179         uint32_t reg;
4180         int ret;
4181
4182         if (!lut)
4183                 return -EINVAL;
4184
4185         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4186                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4187                                           lut, lut_size);
4188                 if (ret) {
4189                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4190                         return ret;
4191                 }
4192         } else {
4193                 uint32_t *lut_dw = (uint32_t *)lut;
4194                 uint16_t i, lut_size_dw = lut_size / 4;
4195
4196                 if (vsi->type == I40E_VSI_SRIOV) {
4197                         for (i = 0; i <= lut_size_dw; i++) {
4198                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4199                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4200                         }
4201                 } else {
4202                         for (i = 0; i < lut_size_dw; i++)
4203                                 lut_dw[i] = I40E_READ_REG(hw,
4204                                                           I40E_PFQF_HLUT(i));
4205                 }
4206         }
4207
4208         return 0;
4209 }
4210
4211 int
4212 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4213 {
4214         struct i40e_pf *pf;
4215         struct i40e_hw *hw;
4216         int ret;
4217
4218         if (!vsi || !lut)
4219                 return -EINVAL;
4220
4221         pf = I40E_VSI_TO_PF(vsi);
4222         hw = I40E_VSI_TO_HW(vsi);
4223
4224         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4225                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4226                                           lut, lut_size);
4227                 if (ret) {
4228                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4229                         return ret;
4230                 }
4231         } else {
4232                 uint32_t *lut_dw = (uint32_t *)lut;
4233                 uint16_t i, lut_size_dw = lut_size / 4;
4234
4235                 if (vsi->type == I40E_VSI_SRIOV) {
4236                         for (i = 0; i < lut_size_dw; i++)
4237                                 I40E_WRITE_REG(
4238                                         hw,
4239                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4240                                         lut_dw[i]);
4241                 } else {
4242                         for (i = 0; i < lut_size_dw; i++)
4243                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4244                                                lut_dw[i]);
4245                 }
4246                 I40E_WRITE_FLUSH(hw);
4247         }
4248
4249         return 0;
4250 }
4251
4252 static int
4253 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4254                          struct rte_eth_rss_reta_entry64 *reta_conf,
4255                          uint16_t reta_size)
4256 {
4257         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4258         uint16_t i, lut_size = pf->hash_lut_size;
4259         uint16_t idx, shift;
4260         uint8_t *lut;
4261         int ret;
4262
4263         if (reta_size != lut_size ||
4264                 reta_size > ETH_RSS_RETA_SIZE_512) {
4265                 PMD_DRV_LOG(ERR,
4266                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4267                         reta_size, lut_size);
4268                 return -EINVAL;
4269         }
4270
4271         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4272         if (!lut) {
4273                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4274                 return -ENOMEM;
4275         }
4276         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4277         if (ret)
4278                 goto out;
4279         for (i = 0; i < reta_size; i++) {
4280                 idx = i / RTE_RETA_GROUP_SIZE;
4281                 shift = i % RTE_RETA_GROUP_SIZE;
4282                 if (reta_conf[idx].mask & (1ULL << shift))
4283                         lut[i] = reta_conf[idx].reta[shift];
4284         }
4285         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4286
4287         pf->adapter->rss_reta_updated = 1;
4288
4289 out:
4290         rte_free(lut);
4291
4292         return ret;
4293 }
4294
4295 static int
4296 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4297                         struct rte_eth_rss_reta_entry64 *reta_conf,
4298                         uint16_t reta_size)
4299 {
4300         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4301         uint16_t i, lut_size = pf->hash_lut_size;
4302         uint16_t idx, shift;
4303         uint8_t *lut;
4304         int ret;
4305
4306         if (reta_size != lut_size ||
4307                 reta_size > ETH_RSS_RETA_SIZE_512) {
4308                 PMD_DRV_LOG(ERR,
4309                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4310                         reta_size, lut_size);
4311                 return -EINVAL;
4312         }
4313
4314         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4315         if (!lut) {
4316                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4317                 return -ENOMEM;
4318         }
4319
4320         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4321         if (ret)
4322                 goto out;
4323         for (i = 0; i < reta_size; i++) {
4324                 idx = i / RTE_RETA_GROUP_SIZE;
4325                 shift = i % RTE_RETA_GROUP_SIZE;
4326                 if (reta_conf[idx].mask & (1ULL << shift))
4327                         reta_conf[idx].reta[shift] = lut[i];
4328         }
4329
4330 out:
4331         rte_free(lut);
4332
4333         return ret;
4334 }
4335
4336 /**
4337  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4338  * @hw:   pointer to the HW structure
4339  * @mem:  pointer to mem struct to fill out
4340  * @size: size of memory requested
4341  * @alignment: what to align the allocation to
4342  **/
4343 enum i40e_status_code
4344 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4345                         struct i40e_dma_mem *mem,
4346                         u64 size,
4347                         u32 alignment)
4348 {
4349         const struct rte_memzone *mz = NULL;
4350         char z_name[RTE_MEMZONE_NAMESIZE];
4351
4352         if (!mem)
4353                 return I40E_ERR_PARAM;
4354
4355         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4356         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4357                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4358         if (!mz)
4359                 return I40E_ERR_NO_MEMORY;
4360
4361         mem->size = size;
4362         mem->va = mz->addr;
4363         mem->pa = mz->iova;
4364         mem->zone = (const void *)mz;
4365         PMD_DRV_LOG(DEBUG,
4366                 "memzone %s allocated with physical address: %"PRIu64,
4367                 mz->name, mem->pa);
4368
4369         return I40E_SUCCESS;
4370 }
4371
4372 /**
4373  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4374  * @hw:   pointer to the HW structure
4375  * @mem:  ptr to mem struct to free
4376  **/
4377 enum i40e_status_code
4378 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4379                     struct i40e_dma_mem *mem)
4380 {
4381         if (!mem)
4382                 return I40E_ERR_PARAM;
4383
4384         PMD_DRV_LOG(DEBUG,
4385                 "memzone %s to be freed with physical address: %"PRIu64,
4386                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4387         rte_memzone_free((const struct rte_memzone *)mem->zone);
4388         mem->zone = NULL;
4389         mem->va = NULL;
4390         mem->pa = (u64)0;
4391
4392         return I40E_SUCCESS;
4393 }
4394
4395 /**
4396  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4397  * @hw:   pointer to the HW structure
4398  * @mem:  pointer to mem struct to fill out
4399  * @size: size of memory requested
4400  **/
4401 enum i40e_status_code
4402 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4403                          struct i40e_virt_mem *mem,
4404                          u32 size)
4405 {
4406         if (!mem)
4407                 return I40E_ERR_PARAM;
4408
4409         mem->size = size;
4410         mem->va = rte_zmalloc("i40e", size, 0);
4411
4412         if (mem->va)
4413                 return I40E_SUCCESS;
4414         else
4415                 return I40E_ERR_NO_MEMORY;
4416 }
4417
4418 /**
4419  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4420  * @hw:   pointer to the HW structure
4421  * @mem:  pointer to mem struct to free
4422  **/
4423 enum i40e_status_code
4424 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4425                      struct i40e_virt_mem *mem)
4426 {
4427         if (!mem)
4428                 return I40E_ERR_PARAM;
4429
4430         rte_free(mem->va);
4431         mem->va = NULL;
4432
4433         return I40E_SUCCESS;
4434 }
4435
4436 void
4437 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4438 {
4439         rte_spinlock_init(&sp->spinlock);
4440 }
4441
4442 void
4443 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4444 {
4445         rte_spinlock_lock(&sp->spinlock);
4446 }
4447
4448 void
4449 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4450 {
4451         rte_spinlock_unlock(&sp->spinlock);
4452 }
4453
4454 void
4455 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4456 {
4457         return;
4458 }
4459
4460 /**
4461  * Get the hardware capabilities, which will be parsed
4462  * and saved into struct i40e_hw.
4463  */
4464 static int
4465 i40e_get_cap(struct i40e_hw *hw)
4466 {
4467         struct i40e_aqc_list_capabilities_element_resp *buf;
4468         uint16_t len, size = 0;
4469         int ret;
4470
4471         /* Calculate a huge enough buff for saving response data temporarily */
4472         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4473                                                 I40E_MAX_CAP_ELE_NUM;
4474         buf = rte_zmalloc("i40e", len, 0);
4475         if (!buf) {
4476                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4477                 return I40E_ERR_NO_MEMORY;
4478         }
4479
4480         /* Get, parse the capabilities and save it to hw */
4481         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4482                         i40e_aqc_opc_list_func_capabilities, NULL);
4483         if (ret != I40E_SUCCESS)
4484                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4485
4486         /* Free the temporary buffer after being used */
4487         rte_free(buf);
4488
4489         return ret;
4490 }
4491
4492 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4493
4494 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4495                 const char *value,
4496                 void *opaque)
4497 {
4498         struct i40e_pf *pf;
4499         unsigned long num;
4500         char *end;
4501
4502         pf = (struct i40e_pf *)opaque;
4503         RTE_SET_USED(key);
4504
4505         errno = 0;
4506         num = strtoul(value, &end, 0);
4507         if (errno != 0 || end == value || *end != 0) {
4508                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4509                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4510                 return -(EINVAL);
4511         }
4512
4513         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4514                 pf->vf_nb_qp_max = (uint16_t)num;
4515         else
4516                 /* here return 0 to make next valid same argument work */
4517                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4518                             "power of 2 and equal or less than 16 !, Now it is "
4519                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4520
4521         return 0;
4522 }
4523
4524 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4525 {
4526         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4527         struct rte_kvargs *kvlist;
4528         int kvargs_count;
4529
4530         /* set default queue number per VF as 4 */
4531         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4532
4533         if (dev->device->devargs == NULL)
4534                 return 0;
4535
4536         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4537         if (kvlist == NULL)
4538                 return -(EINVAL);
4539
4540         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4541         if (!kvargs_count) {
4542                 rte_kvargs_free(kvlist);
4543                 return 0;
4544         }
4545
4546         if (kvargs_count > 1)
4547                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4548                             "the first invalid or last valid one is used !",
4549                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4550
4551         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4552                            i40e_pf_parse_vf_queue_number_handler, pf);
4553
4554         rte_kvargs_free(kvlist);
4555
4556         return 0;
4557 }
4558
4559 static int
4560 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4561 {
4562         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4563         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4564         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4565         uint16_t qp_count = 0, vsi_count = 0;
4566
4567         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4568                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4569                 return -EINVAL;
4570         }
4571
4572         i40e_pf_config_vf_rxq_number(dev);
4573
4574         /* Add the parameter init for LFC */
4575         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4576         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4577         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4578
4579         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4580         pf->max_num_vsi = hw->func_caps.num_vsis;
4581         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4582         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4583
4584         /* FDir queue/VSI allocation */
4585         pf->fdir_qp_offset = 0;
4586         if (hw->func_caps.fd) {
4587                 pf->flags |= I40E_FLAG_FDIR;
4588                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4589         } else {
4590                 pf->fdir_nb_qps = 0;
4591         }
4592         qp_count += pf->fdir_nb_qps;
4593         vsi_count += 1;
4594
4595         /* LAN queue/VSI allocation */
4596         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4597         if (!hw->func_caps.rss) {
4598                 pf->lan_nb_qps = 1;
4599         } else {
4600                 pf->flags |= I40E_FLAG_RSS;
4601                 if (hw->mac.type == I40E_MAC_X722)
4602                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4603                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4604         }
4605         qp_count += pf->lan_nb_qps;
4606         vsi_count += 1;
4607
4608         /* VF queue/VSI allocation */
4609         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4610         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4611                 pf->flags |= I40E_FLAG_SRIOV;
4612                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4613                 pf->vf_num = pci_dev->max_vfs;
4614                 PMD_DRV_LOG(DEBUG,
4615                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4616                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4617         } else {
4618                 pf->vf_nb_qps = 0;
4619                 pf->vf_num = 0;
4620         }
4621         qp_count += pf->vf_nb_qps * pf->vf_num;
4622         vsi_count += pf->vf_num;
4623
4624         /* VMDq queue/VSI allocation */
4625         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4626         pf->vmdq_nb_qps = 0;
4627         pf->max_nb_vmdq_vsi = 0;
4628         if (hw->func_caps.vmdq) {
4629                 if (qp_count < hw->func_caps.num_tx_qp &&
4630                         vsi_count < hw->func_caps.num_vsis) {
4631                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4632                                 qp_count) / pf->vmdq_nb_qp_max;
4633
4634                         /* Limit the maximum number of VMDq vsi to the maximum
4635                          * ethdev can support
4636                          */
4637                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4638                                 hw->func_caps.num_vsis - vsi_count);
4639                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4640                                 ETH_64_POOLS);
4641                         if (pf->max_nb_vmdq_vsi) {
4642                                 pf->flags |= I40E_FLAG_VMDQ;
4643                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4644                                 PMD_DRV_LOG(DEBUG,
4645                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4646                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4647                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4648                         } else {
4649                                 PMD_DRV_LOG(INFO,
4650                                         "No enough queues left for VMDq");
4651                         }
4652                 } else {
4653                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4654                 }
4655         }
4656         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4657         vsi_count += pf->max_nb_vmdq_vsi;
4658
4659         if (hw->func_caps.dcb)
4660                 pf->flags |= I40E_FLAG_DCB;
4661
4662         if (qp_count > hw->func_caps.num_tx_qp) {
4663                 PMD_DRV_LOG(ERR,
4664                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4665                         qp_count, hw->func_caps.num_tx_qp);
4666                 return -EINVAL;
4667         }
4668         if (vsi_count > hw->func_caps.num_vsis) {
4669                 PMD_DRV_LOG(ERR,
4670                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4671                         vsi_count, hw->func_caps.num_vsis);
4672                 return -EINVAL;
4673         }
4674
4675         return 0;
4676 }
4677
4678 static int
4679 i40e_pf_get_switch_config(struct i40e_pf *pf)
4680 {
4681         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4682         struct i40e_aqc_get_switch_config_resp *switch_config;
4683         struct i40e_aqc_switch_config_element_resp *element;
4684         uint16_t start_seid = 0, num_reported;
4685         int ret;
4686
4687         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4688                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4689         if (!switch_config) {
4690                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4691                 return -ENOMEM;
4692         }
4693
4694         /* Get the switch configurations */
4695         ret = i40e_aq_get_switch_config(hw, switch_config,
4696                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4697         if (ret != I40E_SUCCESS) {
4698                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4699                 goto fail;
4700         }
4701         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4702         if (num_reported != 1) { /* The number should be 1 */
4703                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4704                 goto fail;
4705         }
4706
4707         /* Parse the switch configuration elements */
4708         element = &(switch_config->element[0]);
4709         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4710                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4711                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4712         } else
4713                 PMD_DRV_LOG(INFO, "Unknown element type");
4714
4715 fail:
4716         rte_free(switch_config);
4717
4718         return ret;
4719 }
4720
4721 static int
4722 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4723                         uint32_t num)
4724 {
4725         struct pool_entry *entry;
4726
4727         if (pool == NULL || num == 0)
4728                 return -EINVAL;
4729
4730         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4731         if (entry == NULL) {
4732                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4733                 return -ENOMEM;
4734         }
4735
4736         /* queue heap initialize */
4737         pool->num_free = num;
4738         pool->num_alloc = 0;
4739         pool->base = base;
4740         LIST_INIT(&pool->alloc_list);
4741         LIST_INIT(&pool->free_list);
4742
4743         /* Initialize element  */
4744         entry->base = 0;
4745         entry->len = num;
4746
4747         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4748         return 0;
4749 }
4750
4751 static void
4752 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4753 {
4754         struct pool_entry *entry, *next_entry;
4755
4756         if (pool == NULL)
4757                 return;
4758
4759         for (entry = LIST_FIRST(&pool->alloc_list);
4760                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4761                         entry = next_entry) {
4762                 LIST_REMOVE(entry, next);
4763                 rte_free(entry);
4764         }
4765
4766         for (entry = LIST_FIRST(&pool->free_list);
4767                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4768                         entry = next_entry) {
4769                 LIST_REMOVE(entry, next);
4770                 rte_free(entry);
4771         }
4772
4773         pool->num_free = 0;
4774         pool->num_alloc = 0;
4775         pool->base = 0;
4776         LIST_INIT(&pool->alloc_list);
4777         LIST_INIT(&pool->free_list);
4778 }
4779
4780 static int
4781 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4782                        uint32_t base)
4783 {
4784         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4785         uint32_t pool_offset;
4786         int insert;
4787
4788         if (pool == NULL) {
4789                 PMD_DRV_LOG(ERR, "Invalid parameter");
4790                 return -EINVAL;
4791         }
4792
4793         pool_offset = base - pool->base;
4794         /* Lookup in alloc list */
4795         LIST_FOREACH(entry, &pool->alloc_list, next) {
4796                 if (entry->base == pool_offset) {
4797                         valid_entry = entry;
4798                         LIST_REMOVE(entry, next);
4799                         break;
4800                 }
4801         }
4802
4803         /* Not find, return */
4804         if (valid_entry == NULL) {
4805                 PMD_DRV_LOG(ERR, "Failed to find entry");
4806                 return -EINVAL;
4807         }
4808
4809         /**
4810          * Found it, move it to free list  and try to merge.
4811          * In order to make merge easier, always sort it by qbase.
4812          * Find adjacent prev and last entries.
4813          */
4814         prev = next = NULL;
4815         LIST_FOREACH(entry, &pool->free_list, next) {
4816                 if (entry->base > valid_entry->base) {
4817                         next = entry;
4818                         break;
4819                 }
4820                 prev = entry;
4821         }
4822
4823         insert = 0;
4824         /* Try to merge with next one*/
4825         if (next != NULL) {
4826                 /* Merge with next one */
4827                 if (valid_entry->base + valid_entry->len == next->base) {
4828                         next->base = valid_entry->base;
4829                         next->len += valid_entry->len;
4830                         rte_free(valid_entry);
4831                         valid_entry = next;
4832                         insert = 1;
4833                 }
4834         }
4835
4836         if (prev != NULL) {
4837                 /* Merge with previous one */
4838                 if (prev->base + prev->len == valid_entry->base) {
4839                         prev->len += valid_entry->len;
4840                         /* If it merge with next one, remove next node */
4841                         if (insert == 1) {
4842                                 LIST_REMOVE(valid_entry, next);
4843                                 rte_free(valid_entry);
4844                         } else {
4845                                 rte_free(valid_entry);
4846                                 insert = 1;
4847                         }
4848                 }
4849         }
4850
4851         /* Not find any entry to merge, insert */
4852         if (insert == 0) {
4853                 if (prev != NULL)
4854                         LIST_INSERT_AFTER(prev, valid_entry, next);
4855                 else if (next != NULL)
4856                         LIST_INSERT_BEFORE(next, valid_entry, next);
4857                 else /* It's empty list, insert to head */
4858                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4859         }
4860
4861         pool->num_free += valid_entry->len;
4862         pool->num_alloc -= valid_entry->len;
4863
4864         return 0;
4865 }
4866
4867 static int
4868 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4869                        uint16_t num)
4870 {
4871         struct pool_entry *entry, *valid_entry;
4872
4873         if (pool == NULL || num == 0) {
4874                 PMD_DRV_LOG(ERR, "Invalid parameter");
4875                 return -EINVAL;
4876         }
4877
4878         if (pool->num_free < num) {
4879                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4880                             num, pool->num_free);
4881                 return -ENOMEM;
4882         }
4883
4884         valid_entry = NULL;
4885         /* Lookup  in free list and find most fit one */
4886         LIST_FOREACH(entry, &pool->free_list, next) {
4887                 if (entry->len >= num) {
4888                         /* Find best one */
4889                         if (entry->len == num) {
4890                                 valid_entry = entry;
4891                                 break;
4892                         }
4893                         if (valid_entry == NULL || valid_entry->len > entry->len)
4894                                 valid_entry = entry;
4895                 }
4896         }
4897
4898         /* Not find one to satisfy the request, return */
4899         if (valid_entry == NULL) {
4900                 PMD_DRV_LOG(ERR, "No valid entry found");
4901                 return -ENOMEM;
4902         }
4903         /**
4904          * The entry have equal queue number as requested,
4905          * remove it from alloc_list.
4906          */
4907         if (valid_entry->len == num) {
4908                 LIST_REMOVE(valid_entry, next);
4909         } else {
4910                 /**
4911                  * The entry have more numbers than requested,
4912                  * create a new entry for alloc_list and minus its
4913                  * queue base and number in free_list.
4914                  */
4915                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4916                 if (entry == NULL) {
4917                         PMD_DRV_LOG(ERR,
4918                                 "Failed to allocate memory for resource pool");
4919                         return -ENOMEM;
4920                 }
4921                 entry->base = valid_entry->base;
4922                 entry->len = num;
4923                 valid_entry->base += num;
4924                 valid_entry->len -= num;
4925                 valid_entry = entry;
4926         }
4927
4928         /* Insert it into alloc list, not sorted */
4929         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4930
4931         pool->num_free -= valid_entry->len;
4932         pool->num_alloc += valid_entry->len;
4933
4934         return valid_entry->base + pool->base;
4935 }
4936
4937 /**
4938  * bitmap_is_subset - Check whether src2 is subset of src1
4939  **/
4940 static inline int
4941 bitmap_is_subset(uint8_t src1, uint8_t src2)
4942 {
4943         return !((src1 ^ src2) & src2);
4944 }
4945
4946 static enum i40e_status_code
4947 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4948 {
4949         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4950
4951         /* If DCB is not supported, only default TC is supported */
4952         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4953                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4954                 return I40E_NOT_SUPPORTED;
4955         }
4956
4957         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4958                 PMD_DRV_LOG(ERR,
4959                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4960                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4961                 return I40E_NOT_SUPPORTED;
4962         }
4963         return I40E_SUCCESS;
4964 }
4965
4966 int
4967 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4968                                 struct i40e_vsi_vlan_pvid_info *info)
4969 {
4970         struct i40e_hw *hw;
4971         struct i40e_vsi_context ctxt;
4972         uint8_t vlan_flags = 0;
4973         int ret;
4974
4975         if (vsi == NULL || info == NULL) {
4976                 PMD_DRV_LOG(ERR, "invalid parameters");
4977                 return I40E_ERR_PARAM;
4978         }
4979
4980         if (info->on) {
4981                 vsi->info.pvid = info->config.pvid;
4982                 /**
4983                  * If insert pvid is enabled, only tagged pkts are
4984                  * allowed to be sent out.
4985                  */
4986                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4987                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4988         } else {
4989                 vsi->info.pvid = 0;
4990                 if (info->config.reject.tagged == 0)
4991                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4992
4993                 if (info->config.reject.untagged == 0)
4994                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4995         }
4996         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4997                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4998         vsi->info.port_vlan_flags |= vlan_flags;
4999         vsi->info.valid_sections =
5000                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5001         memset(&ctxt, 0, sizeof(ctxt));
5002         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5003         ctxt.seid = vsi->seid;
5004
5005         hw = I40E_VSI_TO_HW(vsi);
5006         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5007         if (ret != I40E_SUCCESS)
5008                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5009
5010         return ret;
5011 }
5012
5013 static int
5014 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5015 {
5016         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5017         int i, ret;
5018         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5019
5020         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5021         if (ret != I40E_SUCCESS)
5022                 return ret;
5023
5024         if (!vsi->seid) {
5025                 PMD_DRV_LOG(ERR, "seid not valid");
5026                 return -EINVAL;
5027         }
5028
5029         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5030         tc_bw_data.tc_valid_bits = enabled_tcmap;
5031         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5032                 tc_bw_data.tc_bw_credits[i] =
5033                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5034
5035         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5036         if (ret != I40E_SUCCESS) {
5037                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5038                 return ret;
5039         }
5040
5041         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5042                                         sizeof(vsi->info.qs_handle));
5043         return I40E_SUCCESS;
5044 }
5045
5046 static enum i40e_status_code
5047 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5048                                  struct i40e_aqc_vsi_properties_data *info,
5049                                  uint8_t enabled_tcmap)
5050 {
5051         enum i40e_status_code ret;
5052         int i, total_tc = 0;
5053         uint16_t qpnum_per_tc, bsf, qp_idx;
5054
5055         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5056         if (ret != I40E_SUCCESS)
5057                 return ret;
5058
5059         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5060                 if (enabled_tcmap & (1 << i))
5061                         total_tc++;
5062         if (total_tc == 0)
5063                 total_tc = 1;
5064         vsi->enabled_tc = enabled_tcmap;
5065
5066         /* Number of queues per enabled TC */
5067         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5068         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5069         bsf = rte_bsf32(qpnum_per_tc);
5070
5071         /* Adjust the queue number to actual queues that can be applied */
5072         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5073                 vsi->nb_qps = qpnum_per_tc * total_tc;
5074
5075         /**
5076          * Configure TC and queue mapping parameters, for enabled TC,
5077          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5078          * default queue will serve it.
5079          */
5080         qp_idx = 0;
5081         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5082                 if (vsi->enabled_tc & (1 << i)) {
5083                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5084                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5085                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5086                         qp_idx += qpnum_per_tc;
5087                 } else
5088                         info->tc_mapping[i] = 0;
5089         }
5090
5091         /* Associate queue number with VSI */
5092         if (vsi->type == I40E_VSI_SRIOV) {
5093                 info->mapping_flags |=
5094                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5095                 for (i = 0; i < vsi->nb_qps; i++)
5096                         info->queue_mapping[i] =
5097                                 rte_cpu_to_le_16(vsi->base_queue + i);
5098         } else {
5099                 info->mapping_flags |=
5100                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5101                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5102         }
5103         info->valid_sections |=
5104                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5105
5106         return I40E_SUCCESS;
5107 }
5108
5109 static int
5110 i40e_veb_release(struct i40e_veb *veb)
5111 {
5112         struct i40e_vsi *vsi;
5113         struct i40e_hw *hw;
5114
5115         if (veb == NULL)
5116                 return -EINVAL;
5117
5118         if (!TAILQ_EMPTY(&veb->head)) {
5119                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5120                 return -EACCES;
5121         }
5122         /* associate_vsi field is NULL for floating VEB */
5123         if (veb->associate_vsi != NULL) {
5124                 vsi = veb->associate_vsi;
5125                 hw = I40E_VSI_TO_HW(vsi);
5126
5127                 vsi->uplink_seid = veb->uplink_seid;
5128                 vsi->veb = NULL;
5129         } else {
5130                 veb->associate_pf->main_vsi->floating_veb = NULL;
5131                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5132         }
5133
5134         i40e_aq_delete_element(hw, veb->seid, NULL);
5135         rte_free(veb);
5136         return I40E_SUCCESS;
5137 }
5138
5139 /* Setup a veb */
5140 static struct i40e_veb *
5141 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5142 {
5143         struct i40e_veb *veb;
5144         int ret;
5145         struct i40e_hw *hw;
5146
5147         if (pf == NULL) {
5148                 PMD_DRV_LOG(ERR,
5149                             "veb setup failed, associated PF shouldn't null");
5150                 return NULL;
5151         }
5152         hw = I40E_PF_TO_HW(pf);
5153
5154         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5155         if (!veb) {
5156                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5157                 goto fail;
5158         }
5159
5160         veb->associate_vsi = vsi;
5161         veb->associate_pf = pf;
5162         TAILQ_INIT(&veb->head);
5163         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5164
5165         /* create floating veb if vsi is NULL */
5166         if (vsi != NULL) {
5167                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5168                                       I40E_DEFAULT_TCMAP, false,
5169                                       &veb->seid, false, NULL);
5170         } else {
5171                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5172                                       true, &veb->seid, false, NULL);
5173         }
5174
5175         if (ret != I40E_SUCCESS) {
5176                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5177                             hw->aq.asq_last_status);
5178                 goto fail;
5179         }
5180         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5181
5182         /* get statistics index */
5183         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5184                                 &veb->stats_idx, NULL, NULL, NULL);
5185         if (ret != I40E_SUCCESS) {
5186                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5187                             hw->aq.asq_last_status);
5188                 goto fail;
5189         }
5190         /* Get VEB bandwidth, to be implemented */
5191         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5192         if (vsi)
5193                 vsi->uplink_seid = veb->seid;
5194
5195         return veb;
5196 fail:
5197         rte_free(veb);
5198         return NULL;
5199 }
5200
5201 int
5202 i40e_vsi_release(struct i40e_vsi *vsi)
5203 {
5204         struct i40e_pf *pf;
5205         struct i40e_hw *hw;
5206         struct i40e_vsi_list *vsi_list;
5207         void *temp;
5208         int ret;
5209         struct i40e_mac_filter *f;
5210         uint16_t user_param;
5211
5212         if (!vsi)
5213                 return I40E_SUCCESS;
5214
5215         if (!vsi->adapter)
5216                 return -EFAULT;
5217
5218         user_param = vsi->user_param;
5219
5220         pf = I40E_VSI_TO_PF(vsi);
5221         hw = I40E_VSI_TO_HW(vsi);
5222
5223         /* VSI has child to attach, release child first */
5224         if (vsi->veb) {
5225                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5226                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5227                                 return -1;
5228                 }
5229                 i40e_veb_release(vsi->veb);
5230         }
5231
5232         if (vsi->floating_veb) {
5233                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5234                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5235                                 return -1;
5236                 }
5237         }
5238
5239         /* Remove all macvlan filters of the VSI */
5240         i40e_vsi_remove_all_macvlan_filter(vsi);
5241         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5242                 rte_free(f);
5243
5244         if (vsi->type != I40E_VSI_MAIN &&
5245             ((vsi->type != I40E_VSI_SRIOV) ||
5246             !pf->floating_veb_list[user_param])) {
5247                 /* Remove vsi from parent's sibling list */
5248                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5249                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5250                         return I40E_ERR_PARAM;
5251                 }
5252                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5253                                 &vsi->sib_vsi_list, list);
5254
5255                 /* Remove all switch element of the VSI */
5256                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5257                 if (ret != I40E_SUCCESS)
5258                         PMD_DRV_LOG(ERR, "Failed to delete element");
5259         }
5260
5261         if ((vsi->type == I40E_VSI_SRIOV) &&
5262             pf->floating_veb_list[user_param]) {
5263                 /* Remove vsi from parent's sibling list */
5264                 if (vsi->parent_vsi == NULL ||
5265                     vsi->parent_vsi->floating_veb == NULL) {
5266                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5267                         return I40E_ERR_PARAM;
5268                 }
5269                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5270                              &vsi->sib_vsi_list, list);
5271
5272                 /* Remove all switch element of the VSI */
5273                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5274                 if (ret != I40E_SUCCESS)
5275                         PMD_DRV_LOG(ERR, "Failed to delete element");
5276         }
5277
5278         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5279
5280         if (vsi->type != I40E_VSI_SRIOV)
5281                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5282         rte_free(vsi);
5283
5284         return I40E_SUCCESS;
5285 }
5286
5287 static int
5288 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5289 {
5290         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5291         struct i40e_aqc_remove_macvlan_element_data def_filter;
5292         struct i40e_mac_filter_info filter;
5293         int ret;
5294
5295         if (vsi->type != I40E_VSI_MAIN)
5296                 return I40E_ERR_CONFIG;
5297         memset(&def_filter, 0, sizeof(def_filter));
5298         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5299                                         ETH_ADDR_LEN);
5300         def_filter.vlan_tag = 0;
5301         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5302                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5303         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5304         if (ret != I40E_SUCCESS) {
5305                 struct i40e_mac_filter *f;
5306                 struct ether_addr *mac;
5307
5308                 PMD_DRV_LOG(DEBUG,
5309                             "Cannot remove the default macvlan filter");
5310                 /* It needs to add the permanent mac into mac list */
5311                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5312                 if (f == NULL) {
5313                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5314                         return I40E_ERR_NO_MEMORY;
5315                 }
5316                 mac = &f->mac_info.mac_addr;
5317                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5318                                 ETH_ADDR_LEN);
5319                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5320                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5321                 vsi->mac_num++;
5322
5323                 return ret;
5324         }
5325         rte_memcpy(&filter.mac_addr,
5326                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5327         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5328         return i40e_vsi_add_mac(vsi, &filter);
5329 }
5330
5331 /*
5332  * i40e_vsi_get_bw_config - Query VSI BW Information
5333  * @vsi: the VSI to be queried
5334  *
5335  * Returns 0 on success, negative value on failure
5336  */
5337 static enum i40e_status_code
5338 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5339 {
5340         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5341         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5342         struct i40e_hw *hw = &vsi->adapter->hw;
5343         i40e_status ret;
5344         int i;
5345         uint32_t bw_max;
5346
5347         memset(&bw_config, 0, sizeof(bw_config));
5348         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5349         if (ret != I40E_SUCCESS) {
5350                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5351                             hw->aq.asq_last_status);
5352                 return ret;
5353         }
5354
5355         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5356         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5357                                         &ets_sla_config, NULL);
5358         if (ret != I40E_SUCCESS) {
5359                 PMD_DRV_LOG(ERR,
5360                         "VSI failed to get TC bandwdith configuration %u",
5361                         hw->aq.asq_last_status);
5362                 return ret;
5363         }
5364
5365         /* store and print out BW info */
5366         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5367         vsi->bw_info.bw_max = bw_config.max_bw;
5368         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5369         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5370         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5371                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5372                      I40E_16_BIT_WIDTH);
5373         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5374                 vsi->bw_info.bw_ets_share_credits[i] =
5375                                 ets_sla_config.share_credits[i];
5376                 vsi->bw_info.bw_ets_credits[i] =
5377                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5378                 /* 4 bits per TC, 4th bit is reserved */
5379                 vsi->bw_info.bw_ets_max[i] =
5380                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5381                                   RTE_LEN2MASK(3, uint8_t));
5382                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5383                             vsi->bw_info.bw_ets_share_credits[i]);
5384                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5385                             vsi->bw_info.bw_ets_credits[i]);
5386                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5387                             vsi->bw_info.bw_ets_max[i]);
5388         }
5389
5390         return I40E_SUCCESS;
5391 }
5392
5393 /* i40e_enable_pf_lb
5394  * @pf: pointer to the pf structure
5395  *
5396  * allow loopback on pf
5397  */
5398 static inline void
5399 i40e_enable_pf_lb(struct i40e_pf *pf)
5400 {
5401         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5402         struct i40e_vsi_context ctxt;
5403         int ret;
5404
5405         /* Use the FW API if FW >= v5.0 */
5406         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5407                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5408                 return;
5409         }
5410
5411         memset(&ctxt, 0, sizeof(ctxt));
5412         ctxt.seid = pf->main_vsi_seid;
5413         ctxt.pf_num = hw->pf_id;
5414         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5415         if (ret) {
5416                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5417                             ret, hw->aq.asq_last_status);
5418                 return;
5419         }
5420         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5421         ctxt.info.valid_sections =
5422                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5423         ctxt.info.switch_id |=
5424                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5425
5426         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5427         if (ret)
5428                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5429                             hw->aq.asq_last_status);
5430 }
5431
5432 /* Setup a VSI */
5433 struct i40e_vsi *
5434 i40e_vsi_setup(struct i40e_pf *pf,
5435                enum i40e_vsi_type type,
5436                struct i40e_vsi *uplink_vsi,
5437                uint16_t user_param)
5438 {
5439         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5440         struct i40e_vsi *vsi;
5441         struct i40e_mac_filter_info filter;
5442         int ret;
5443         struct i40e_vsi_context ctxt;
5444         struct ether_addr broadcast =
5445                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5446
5447         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5448             uplink_vsi == NULL) {
5449                 PMD_DRV_LOG(ERR,
5450                         "VSI setup failed, VSI link shouldn't be NULL");
5451                 return NULL;
5452         }
5453
5454         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5455                 PMD_DRV_LOG(ERR,
5456                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5457                 return NULL;
5458         }
5459
5460         /* two situations
5461          * 1.type is not MAIN and uplink vsi is not NULL
5462          * If uplink vsi didn't setup VEB, create one first under veb field
5463          * 2.type is SRIOV and the uplink is NULL
5464          * If floating VEB is NULL, create one veb under floating veb field
5465          */
5466
5467         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5468             uplink_vsi->veb == NULL) {
5469                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5470
5471                 if (uplink_vsi->veb == NULL) {
5472                         PMD_DRV_LOG(ERR, "VEB setup failed");
5473                         return NULL;
5474                 }
5475                 /* set ALLOWLOOPBACk on pf, when veb is created */
5476                 i40e_enable_pf_lb(pf);
5477         }
5478
5479         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5480             pf->main_vsi->floating_veb == NULL) {
5481                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5482
5483                 if (pf->main_vsi->floating_veb == NULL) {
5484                         PMD_DRV_LOG(ERR, "VEB setup failed");
5485                         return NULL;
5486                 }
5487         }
5488
5489         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5490         if (!vsi) {
5491                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5492                 return NULL;
5493         }
5494         TAILQ_INIT(&vsi->mac_list);
5495         vsi->type = type;
5496         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5497         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5498         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5499         vsi->user_param = user_param;
5500         vsi->vlan_anti_spoof_on = 0;
5501         vsi->vlan_filter_on = 0;
5502         /* Allocate queues */
5503         switch (vsi->type) {
5504         case I40E_VSI_MAIN  :
5505                 vsi->nb_qps = pf->lan_nb_qps;
5506                 break;
5507         case I40E_VSI_SRIOV :
5508                 vsi->nb_qps = pf->vf_nb_qps;
5509                 break;
5510         case I40E_VSI_VMDQ2:
5511                 vsi->nb_qps = pf->vmdq_nb_qps;
5512                 break;
5513         case I40E_VSI_FDIR:
5514                 vsi->nb_qps = pf->fdir_nb_qps;
5515                 break;
5516         default:
5517                 goto fail_mem;
5518         }
5519         /*
5520          * The filter status descriptor is reported in rx queue 0,
5521          * while the tx queue for fdir filter programming has no
5522          * such constraints, can be non-zero queues.
5523          * To simplify it, choose FDIR vsi use queue 0 pair.
5524          * To make sure it will use queue 0 pair, queue allocation
5525          * need be done before this function is called
5526          */
5527         if (type != I40E_VSI_FDIR) {
5528                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5529                         if (ret < 0) {
5530                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5531                                                 vsi->seid, ret);
5532                                 goto fail_mem;
5533                         }
5534                         vsi->base_queue = ret;
5535         } else
5536                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5537
5538         /* VF has MSIX interrupt in VF range, don't allocate here */
5539         if (type == I40E_VSI_MAIN) {
5540                 if (pf->support_multi_driver) {
5541                         /* If support multi-driver, need to use INT0 instead of
5542                          * allocating from msix pool. The Msix pool is init from
5543                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5544                          * to 1 without calling i40e_res_pool_alloc.
5545                          */
5546                         vsi->msix_intr = 0;
5547                         vsi->nb_msix = 1;
5548                 } else {
5549                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5550                                                   RTE_MIN(vsi->nb_qps,
5551                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5552                         if (ret < 0) {
5553                                 PMD_DRV_LOG(ERR,
5554                                             "VSI MAIN %d get heap failed %d",
5555                                             vsi->seid, ret);
5556                                 goto fail_queue_alloc;
5557                         }
5558                         vsi->msix_intr = ret;
5559                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5560                                                RTE_MAX_RXTX_INTR_VEC_ID);
5561                 }
5562         } else if (type != I40E_VSI_SRIOV) {
5563                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5564                 if (ret < 0) {
5565                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5566                         goto fail_queue_alloc;
5567                 }
5568                 vsi->msix_intr = ret;
5569                 vsi->nb_msix = 1;
5570         } else {
5571                 vsi->msix_intr = 0;
5572                 vsi->nb_msix = 0;
5573         }
5574
5575         /* Add VSI */
5576         if (type == I40E_VSI_MAIN) {
5577                 /* For main VSI, no need to add since it's default one */
5578                 vsi->uplink_seid = pf->mac_seid;
5579                 vsi->seid = pf->main_vsi_seid;
5580                 /* Bind queues with specific MSIX interrupt */
5581                 /**
5582                  * Needs 2 interrupt at least, one for misc cause which will
5583                  * enabled from OS side, Another for queues binding the
5584                  * interrupt from device side only.
5585                  */
5586
5587                 /* Get default VSI parameters from hardware */
5588                 memset(&ctxt, 0, sizeof(ctxt));
5589                 ctxt.seid = vsi->seid;
5590                 ctxt.pf_num = hw->pf_id;
5591                 ctxt.uplink_seid = vsi->uplink_seid;
5592                 ctxt.vf_num = 0;
5593                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5594                 if (ret != I40E_SUCCESS) {
5595                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5596                         goto fail_msix_alloc;
5597                 }
5598                 rte_memcpy(&vsi->info, &ctxt.info,
5599                         sizeof(struct i40e_aqc_vsi_properties_data));
5600                 vsi->vsi_id = ctxt.vsi_number;
5601                 vsi->info.valid_sections = 0;
5602
5603                 /* Configure tc, enabled TC0 only */
5604                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5605                         I40E_SUCCESS) {
5606                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5607                         goto fail_msix_alloc;
5608                 }
5609
5610                 /* TC, queue mapping */
5611                 memset(&ctxt, 0, sizeof(ctxt));
5612                 vsi->info.valid_sections |=
5613                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5614                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5615                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5616                 rte_memcpy(&ctxt.info, &vsi->info,
5617                         sizeof(struct i40e_aqc_vsi_properties_data));
5618                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5619                                                 I40E_DEFAULT_TCMAP);
5620                 if (ret != I40E_SUCCESS) {
5621                         PMD_DRV_LOG(ERR,
5622                                 "Failed to configure TC queue mapping");
5623                         goto fail_msix_alloc;
5624                 }
5625                 ctxt.seid = vsi->seid;
5626                 ctxt.pf_num = hw->pf_id;
5627                 ctxt.uplink_seid = vsi->uplink_seid;
5628                 ctxt.vf_num = 0;
5629
5630                 /* Update VSI parameters */
5631                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5632                 if (ret != I40E_SUCCESS) {
5633                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5634                         goto fail_msix_alloc;
5635                 }
5636
5637                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5638                                                 sizeof(vsi->info.tc_mapping));
5639                 rte_memcpy(&vsi->info.queue_mapping,
5640                                 &ctxt.info.queue_mapping,
5641                         sizeof(vsi->info.queue_mapping));
5642                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5643                 vsi->info.valid_sections = 0;
5644
5645                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5646                                 ETH_ADDR_LEN);
5647
5648                 /**
5649                  * Updating default filter settings are necessary to prevent
5650                  * reception of tagged packets.
5651                  * Some old firmware configurations load a default macvlan
5652                  * filter which accepts both tagged and untagged packets.
5653                  * The updating is to use a normal filter instead if needed.
5654                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5655                  * The firmware with correct configurations load the default
5656                  * macvlan filter which is expected and cannot be removed.
5657                  */
5658                 i40e_update_default_filter_setting(vsi);
5659                 i40e_config_qinq(hw, vsi);
5660         } else if (type == I40E_VSI_SRIOV) {
5661                 memset(&ctxt, 0, sizeof(ctxt));
5662                 /**
5663                  * For other VSI, the uplink_seid equals to uplink VSI's
5664                  * uplink_seid since they share same VEB
5665                  */
5666                 if (uplink_vsi == NULL)
5667                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5668                 else
5669                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5670                 ctxt.pf_num = hw->pf_id;
5671                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5672                 ctxt.uplink_seid = vsi->uplink_seid;
5673                 ctxt.connection_type = 0x1;
5674                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5675
5676                 /* Use the VEB configuration if FW >= v5.0 */
5677                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5678                         /* Configure switch ID */
5679                         ctxt.info.valid_sections |=
5680                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5681                         ctxt.info.switch_id =
5682                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5683                 }
5684
5685                 /* Configure port/vlan */
5686                 ctxt.info.valid_sections |=
5687                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5688                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5689                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5690                                                 hw->func_caps.enabled_tcmap);
5691                 if (ret != I40E_SUCCESS) {
5692                         PMD_DRV_LOG(ERR,
5693                                 "Failed to configure TC queue mapping");
5694                         goto fail_msix_alloc;
5695                 }
5696
5697                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5698                 ctxt.info.valid_sections |=
5699                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5700                 /**
5701                  * Since VSI is not created yet, only configure parameter,
5702                  * will add vsi below.
5703                  */
5704
5705                 i40e_config_qinq(hw, vsi);
5706         } else if (type == I40E_VSI_VMDQ2) {
5707                 memset(&ctxt, 0, sizeof(ctxt));
5708                 /*
5709                  * For other VSI, the uplink_seid equals to uplink VSI's
5710                  * uplink_seid since they share same VEB
5711                  */
5712                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5713                 ctxt.pf_num = hw->pf_id;
5714                 ctxt.vf_num = 0;
5715                 ctxt.uplink_seid = vsi->uplink_seid;
5716                 ctxt.connection_type = 0x1;
5717                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5718
5719                 ctxt.info.valid_sections |=
5720                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5721                 /* user_param carries flag to enable loop back */
5722                 if (user_param) {
5723                         ctxt.info.switch_id =
5724                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5725                         ctxt.info.switch_id |=
5726                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5727                 }
5728
5729                 /* Configure port/vlan */
5730                 ctxt.info.valid_sections |=
5731                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5732                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5733                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5734                                                 I40E_DEFAULT_TCMAP);
5735                 if (ret != I40E_SUCCESS) {
5736                         PMD_DRV_LOG(ERR,
5737                                 "Failed to configure TC queue mapping");
5738                         goto fail_msix_alloc;
5739                 }
5740                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5741                 ctxt.info.valid_sections |=
5742                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5743         } else if (type == I40E_VSI_FDIR) {
5744                 memset(&ctxt, 0, sizeof(ctxt));
5745                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5746                 ctxt.pf_num = hw->pf_id;
5747                 ctxt.vf_num = 0;
5748                 ctxt.uplink_seid = vsi->uplink_seid;
5749                 ctxt.connection_type = 0x1;     /* regular data port */
5750                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5751                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5752                                                 I40E_DEFAULT_TCMAP);
5753                 if (ret != I40E_SUCCESS) {
5754                         PMD_DRV_LOG(ERR,
5755                                 "Failed to configure TC queue mapping.");
5756                         goto fail_msix_alloc;
5757                 }
5758                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5759                 ctxt.info.valid_sections |=
5760                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5761         } else {
5762                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5763                 goto fail_msix_alloc;
5764         }
5765
5766         if (vsi->type != I40E_VSI_MAIN) {
5767                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5768                 if (ret != I40E_SUCCESS) {
5769                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5770                                     hw->aq.asq_last_status);
5771                         goto fail_msix_alloc;
5772                 }
5773                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5774                 vsi->info.valid_sections = 0;
5775                 vsi->seid = ctxt.seid;
5776                 vsi->vsi_id = ctxt.vsi_number;
5777                 vsi->sib_vsi_list.vsi = vsi;
5778                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5779                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5780                                           &vsi->sib_vsi_list, list);
5781                 } else {
5782                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5783                                           &vsi->sib_vsi_list, list);
5784                 }
5785         }
5786
5787         /* MAC/VLAN configuration */
5788         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5789         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5790
5791         ret = i40e_vsi_add_mac(vsi, &filter);
5792         if (ret != I40E_SUCCESS) {
5793                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5794                 goto fail_msix_alloc;
5795         }
5796
5797         /* Get VSI BW information */
5798         i40e_vsi_get_bw_config(vsi);
5799         return vsi;
5800 fail_msix_alloc:
5801         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5802 fail_queue_alloc:
5803         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5804 fail_mem:
5805         rte_free(vsi);
5806         return NULL;
5807 }
5808
5809 /* Configure vlan filter on or off */
5810 int
5811 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5812 {
5813         int i, num;
5814         struct i40e_mac_filter *f;
5815         void *temp;
5816         struct i40e_mac_filter_info *mac_filter;
5817         enum rte_mac_filter_type desired_filter;
5818         int ret = I40E_SUCCESS;
5819
5820         if (on) {
5821                 /* Filter to match MAC and VLAN */
5822                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5823         } else {
5824                 /* Filter to match only MAC */
5825                 desired_filter = RTE_MAC_PERFECT_MATCH;
5826         }
5827
5828         num = vsi->mac_num;
5829
5830         mac_filter = rte_zmalloc("mac_filter_info_data",
5831                                  num * sizeof(*mac_filter), 0);
5832         if (mac_filter == NULL) {
5833                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5834                 return I40E_ERR_NO_MEMORY;
5835         }
5836
5837         i = 0;
5838
5839         /* Remove all existing mac */
5840         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5841                 mac_filter[i] = f->mac_info;
5842                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5843                 if (ret) {
5844                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5845                                     on ? "enable" : "disable");
5846                         goto DONE;
5847                 }
5848                 i++;
5849         }
5850
5851         /* Override with new filter */
5852         for (i = 0; i < num; i++) {
5853                 mac_filter[i].filter_type = desired_filter;
5854                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5855                 if (ret) {
5856                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5857                                     on ? "enable" : "disable");
5858                         goto DONE;
5859                 }
5860         }
5861
5862 DONE:
5863         rte_free(mac_filter);
5864         return ret;
5865 }
5866
5867 /* Configure vlan stripping on or off */
5868 int
5869 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5870 {
5871         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5872         struct i40e_vsi_context ctxt;
5873         uint8_t vlan_flags;
5874         int ret = I40E_SUCCESS;
5875
5876         /* Check if it has been already on or off */
5877         if (vsi->info.valid_sections &
5878                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5879                 if (on) {
5880                         if ((vsi->info.port_vlan_flags &
5881                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5882                                 return 0; /* already on */
5883                 } else {
5884                         if ((vsi->info.port_vlan_flags &
5885                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5886                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5887                                 return 0; /* already off */
5888                 }
5889         }
5890
5891         if (on)
5892                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5893         else
5894                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5895         vsi->info.valid_sections =
5896                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5897         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5898         vsi->info.port_vlan_flags |= vlan_flags;
5899         ctxt.seid = vsi->seid;
5900         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5901         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5902         if (ret)
5903                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5904                             on ? "enable" : "disable");
5905
5906         return ret;
5907 }
5908
5909 static int
5910 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5911 {
5912         struct rte_eth_dev_data *data = dev->data;
5913         int ret;
5914         int mask = 0;
5915
5916         /* Apply vlan offload setting */
5917         mask = ETH_VLAN_STRIP_MASK |
5918                ETH_VLAN_FILTER_MASK |
5919                ETH_VLAN_EXTEND_MASK;
5920         ret = i40e_vlan_offload_set(dev, mask);
5921         if (ret) {
5922                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5923                 return ret;
5924         }
5925
5926         /* Apply pvid setting */
5927         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5928                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5929         if (ret)
5930                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5931
5932         return ret;
5933 }
5934
5935 static int
5936 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5937 {
5938         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5939
5940         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5941 }
5942
5943 static int
5944 i40e_update_flow_control(struct i40e_hw *hw)
5945 {
5946 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5947         struct i40e_link_status link_status;
5948         uint32_t rxfc = 0, txfc = 0, reg;
5949         uint8_t an_info;
5950         int ret;
5951
5952         memset(&link_status, 0, sizeof(link_status));
5953         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5954         if (ret != I40E_SUCCESS) {
5955                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5956                 goto write_reg; /* Disable flow control */
5957         }
5958
5959         an_info = hw->phy.link_info.an_info;
5960         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5961                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5962                 ret = I40E_ERR_NOT_READY;
5963                 goto write_reg; /* Disable flow control */
5964         }
5965         /**
5966          * If link auto negotiation is enabled, flow control needs to
5967          * be configured according to it
5968          */
5969         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5970         case I40E_LINK_PAUSE_RXTX:
5971                 rxfc = 1;
5972                 txfc = 1;
5973                 hw->fc.current_mode = I40E_FC_FULL;
5974                 break;
5975         case I40E_AQ_LINK_PAUSE_RX:
5976                 rxfc = 1;
5977                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5978                 break;
5979         case I40E_AQ_LINK_PAUSE_TX:
5980                 txfc = 1;
5981                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5982                 break;
5983         default:
5984                 hw->fc.current_mode = I40E_FC_NONE;
5985                 break;
5986         }
5987
5988 write_reg:
5989         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5990                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5991         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5992         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5993         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5994         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5995
5996         return ret;
5997 }
5998
5999 /* PF setup */
6000 static int
6001 i40e_pf_setup(struct i40e_pf *pf)
6002 {
6003         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6004         struct i40e_filter_control_settings settings;
6005         struct i40e_vsi *vsi;
6006         int ret;
6007
6008         /* Clear all stats counters */
6009         pf->offset_loaded = FALSE;
6010         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6011         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6012         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6013         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6014
6015         ret = i40e_pf_get_switch_config(pf);
6016         if (ret != I40E_SUCCESS) {
6017                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6018                 return ret;
6019         }
6020
6021         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6022         if (ret)
6023                 PMD_INIT_LOG(WARNING,
6024                         "failed to allocate switch domain for device %d", ret);
6025
6026         if (pf->flags & I40E_FLAG_FDIR) {
6027                 /* make queue allocated first, let FDIR use queue pair 0*/
6028                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6029                 if (ret != I40E_FDIR_QUEUE_ID) {
6030                         PMD_DRV_LOG(ERR,
6031                                 "queue allocation fails for FDIR: ret =%d",
6032                                 ret);
6033                         pf->flags &= ~I40E_FLAG_FDIR;
6034                 }
6035         }
6036         /*  main VSI setup */
6037         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6038         if (!vsi) {
6039                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6040                 return I40E_ERR_NOT_READY;
6041         }
6042         pf->main_vsi = vsi;
6043
6044         /* Configure filter control */
6045         memset(&settings, 0, sizeof(settings));
6046         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6047                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6048         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6049                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6050         else {
6051                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6052                         hw->func_caps.rss_table_size);
6053                 return I40E_ERR_PARAM;
6054         }
6055         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6056                 hw->func_caps.rss_table_size);
6057         pf->hash_lut_size = hw->func_caps.rss_table_size;
6058
6059         /* Enable ethtype and macvlan filters */
6060         settings.enable_ethtype = TRUE;
6061         settings.enable_macvlan = TRUE;
6062         ret = i40e_set_filter_control(hw, &settings);
6063         if (ret)
6064                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6065                                                                 ret);
6066
6067         /* Update flow control according to the auto negotiation */
6068         i40e_update_flow_control(hw);
6069
6070         return I40E_SUCCESS;
6071 }
6072
6073 int
6074 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6075 {
6076         uint32_t reg;
6077         uint16_t j;
6078
6079         /**
6080          * Set or clear TX Queue Disable flags,
6081          * which is required by hardware.
6082          */
6083         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6084         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6085
6086         /* Wait until the request is finished */
6087         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6088                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6089                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6090                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6091                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6092                                                         & 0x1))) {
6093                         break;
6094                 }
6095         }
6096         if (on) {
6097                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6098                         return I40E_SUCCESS; /* already on, skip next steps */
6099
6100                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6101                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6102         } else {
6103                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6104                         return I40E_SUCCESS; /* already off, skip next steps */
6105                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6106         }
6107         /* Write the register */
6108         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6109         /* Check the result */
6110         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6111                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6112                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6113                 if (on) {
6114                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6115                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6116                                 break;
6117                 } else {
6118                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6119                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6120                                 break;
6121                 }
6122         }
6123         /* Check if it is timeout */
6124         if (j >= I40E_CHK_Q_ENA_COUNT) {
6125                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6126                             (on ? "enable" : "disable"), q_idx);
6127                 return I40E_ERR_TIMEOUT;
6128         }
6129
6130         return I40E_SUCCESS;
6131 }
6132
6133 /* Swith on or off the tx queues */
6134 static int
6135 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6136 {
6137         struct rte_eth_dev_data *dev_data = pf->dev_data;
6138         struct i40e_tx_queue *txq;
6139         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6140         uint16_t i;
6141         int ret;
6142
6143         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6144                 txq = dev_data->tx_queues[i];
6145                 /* Don't operate the queue if not configured or
6146                  * if starting only per queue */
6147                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6148                         continue;
6149                 if (on)
6150                         ret = i40e_dev_tx_queue_start(dev, i);
6151                 else
6152                         ret = i40e_dev_tx_queue_stop(dev, i);
6153                 if ( ret != I40E_SUCCESS)
6154                         return ret;
6155         }
6156
6157         return I40E_SUCCESS;
6158 }
6159
6160 int
6161 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6162 {
6163         uint32_t reg;
6164         uint16_t j;
6165
6166         /* Wait until the request is finished */
6167         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6168                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6169                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6170                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6171                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6172                         break;
6173         }
6174
6175         if (on) {
6176                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6177                         return I40E_SUCCESS; /* Already on, skip next steps */
6178                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6179         } else {
6180                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6181                         return I40E_SUCCESS; /* Already off, skip next steps */
6182                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6183         }
6184
6185         /* Write the register */
6186         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6187         /* Check the result */
6188         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6189                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6190                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6191                 if (on) {
6192                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6193                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6194                                 break;
6195                 } else {
6196                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6197                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6198                                 break;
6199                 }
6200         }
6201
6202         /* Check if it is timeout */
6203         if (j >= I40E_CHK_Q_ENA_COUNT) {
6204                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6205                             (on ? "enable" : "disable"), q_idx);
6206                 return I40E_ERR_TIMEOUT;
6207         }
6208
6209         return I40E_SUCCESS;
6210 }
6211 /* Switch on or off the rx queues */
6212 static int
6213 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6214 {
6215         struct rte_eth_dev_data *dev_data = pf->dev_data;
6216         struct i40e_rx_queue *rxq;
6217         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6218         uint16_t i;
6219         int ret;
6220
6221         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6222                 rxq = dev_data->rx_queues[i];
6223                 /* Don't operate the queue if not configured or
6224                  * if starting only per queue */
6225                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6226                         continue;
6227                 if (on)
6228                         ret = i40e_dev_rx_queue_start(dev, i);
6229                 else
6230                         ret = i40e_dev_rx_queue_stop(dev, i);
6231                 if (ret != I40E_SUCCESS)
6232                         return ret;
6233         }
6234
6235         return I40E_SUCCESS;
6236 }
6237
6238 /* Switch on or off all the rx/tx queues */
6239 int
6240 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6241 {
6242         int ret;
6243
6244         if (on) {
6245                 /* enable rx queues before enabling tx queues */
6246                 ret = i40e_dev_switch_rx_queues(pf, on);
6247                 if (ret) {
6248                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6249                         return ret;
6250                 }
6251                 ret = i40e_dev_switch_tx_queues(pf, on);
6252         } else {
6253                 /* Stop tx queues before stopping rx queues */
6254                 ret = i40e_dev_switch_tx_queues(pf, on);
6255                 if (ret) {
6256                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6257                         return ret;
6258                 }
6259                 ret = i40e_dev_switch_rx_queues(pf, on);
6260         }
6261
6262         return ret;
6263 }
6264
6265 /* Initialize VSI for TX */
6266 static int
6267 i40e_dev_tx_init(struct i40e_pf *pf)
6268 {
6269         struct rte_eth_dev_data *data = pf->dev_data;
6270         uint16_t i;
6271         uint32_t ret = I40E_SUCCESS;
6272         struct i40e_tx_queue *txq;
6273
6274         for (i = 0; i < data->nb_tx_queues; i++) {
6275                 txq = data->tx_queues[i];
6276                 if (!txq || !txq->q_set)
6277                         continue;
6278                 ret = i40e_tx_queue_init(txq);
6279                 if (ret != I40E_SUCCESS)
6280                         break;
6281         }
6282         if (ret == I40E_SUCCESS)
6283                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6284                                      ->eth_dev);
6285
6286         return ret;
6287 }
6288
6289 /* Initialize VSI for RX */
6290 static int
6291 i40e_dev_rx_init(struct i40e_pf *pf)
6292 {
6293         struct rte_eth_dev_data *data = pf->dev_data;
6294         int ret = I40E_SUCCESS;
6295         uint16_t i;
6296         struct i40e_rx_queue *rxq;
6297
6298         i40e_pf_config_mq_rx(pf);
6299         for (i = 0; i < data->nb_rx_queues; i++) {
6300                 rxq = data->rx_queues[i];
6301                 if (!rxq || !rxq->q_set)
6302                         continue;
6303
6304                 ret = i40e_rx_queue_init(rxq);
6305                 if (ret != I40E_SUCCESS) {
6306                         PMD_DRV_LOG(ERR,
6307                                 "Failed to do RX queue initialization");
6308                         break;
6309                 }
6310         }
6311         if (ret == I40E_SUCCESS)
6312                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6313                                      ->eth_dev);
6314
6315         return ret;
6316 }
6317
6318 static int
6319 i40e_dev_rxtx_init(struct i40e_pf *pf)
6320 {
6321         int err;
6322
6323         err = i40e_dev_tx_init(pf);
6324         if (err) {
6325                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6326                 return err;
6327         }
6328         err = i40e_dev_rx_init(pf);
6329         if (err) {
6330                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6331                 return err;
6332         }
6333
6334         return err;
6335 }
6336
6337 static int
6338 i40e_vmdq_setup(struct rte_eth_dev *dev)
6339 {
6340         struct rte_eth_conf *conf = &dev->data->dev_conf;
6341         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6342         int i, err, conf_vsis, j, loop;
6343         struct i40e_vsi *vsi;
6344         struct i40e_vmdq_info *vmdq_info;
6345         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6346         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6347
6348         /*
6349          * Disable interrupt to avoid message from VF. Furthermore, it will
6350          * avoid race condition in VSI creation/destroy.
6351          */
6352         i40e_pf_disable_irq0(hw);
6353
6354         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6355                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6356                 return -ENOTSUP;
6357         }
6358
6359         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6360         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6361                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6362                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6363                         pf->max_nb_vmdq_vsi);
6364                 return -ENOTSUP;
6365         }
6366
6367         if (pf->vmdq != NULL) {
6368                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6369                 return 0;
6370         }
6371
6372         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6373                                 sizeof(*vmdq_info) * conf_vsis, 0);
6374
6375         if (pf->vmdq == NULL) {
6376                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6377                 return -ENOMEM;
6378         }
6379
6380         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6381
6382         /* Create VMDQ VSI */
6383         for (i = 0; i < conf_vsis; i++) {
6384                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6385                                 vmdq_conf->enable_loop_back);
6386                 if (vsi == NULL) {
6387                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6388                         err = -1;
6389                         goto err_vsi_setup;
6390                 }
6391                 vmdq_info = &pf->vmdq[i];
6392                 vmdq_info->pf = pf;
6393                 vmdq_info->vsi = vsi;
6394         }
6395         pf->nb_cfg_vmdq_vsi = conf_vsis;
6396
6397         /* Configure Vlan */
6398         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6399         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6400                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6401                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6402                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6403                                         vmdq_conf->pool_map[i].vlan_id, j);
6404
6405                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6406                                                 vmdq_conf->pool_map[i].vlan_id);
6407                                 if (err) {
6408                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6409                                         err = -1;
6410                                         goto err_vsi_setup;
6411                                 }
6412                         }
6413                 }
6414         }
6415
6416         i40e_pf_enable_irq0(hw);
6417
6418         return 0;
6419
6420 err_vsi_setup:
6421         for (i = 0; i < conf_vsis; i++)
6422                 if (pf->vmdq[i].vsi == NULL)
6423                         break;
6424                 else
6425                         i40e_vsi_release(pf->vmdq[i].vsi);
6426
6427         rte_free(pf->vmdq);
6428         pf->vmdq = NULL;
6429         i40e_pf_enable_irq0(hw);
6430         return err;
6431 }
6432
6433 static void
6434 i40e_stat_update_32(struct i40e_hw *hw,
6435                    uint32_t reg,
6436                    bool offset_loaded,
6437                    uint64_t *offset,
6438                    uint64_t *stat)
6439 {
6440         uint64_t new_data;
6441
6442         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6443         if (!offset_loaded)
6444                 *offset = new_data;
6445
6446         if (new_data >= *offset)
6447                 *stat = (uint64_t)(new_data - *offset);
6448         else
6449                 *stat = (uint64_t)((new_data +
6450                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6451 }
6452
6453 static void
6454 i40e_stat_update_48(struct i40e_hw *hw,
6455                    uint32_t hireg,
6456                    uint32_t loreg,
6457                    bool offset_loaded,
6458                    uint64_t *offset,
6459                    uint64_t *stat)
6460 {
6461         uint64_t new_data;
6462
6463         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6464         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6465                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6466
6467         if (!offset_loaded)
6468                 *offset = new_data;
6469
6470         if (new_data >= *offset)
6471                 *stat = new_data - *offset;
6472         else
6473                 *stat = (uint64_t)((new_data +
6474                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6475
6476         *stat &= I40E_48_BIT_MASK;
6477 }
6478
6479 /* Disable IRQ0 */
6480 void
6481 i40e_pf_disable_irq0(struct i40e_hw *hw)
6482 {
6483         /* Disable all interrupt types */
6484         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6485                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6486         I40E_WRITE_FLUSH(hw);
6487 }
6488
6489 /* Enable IRQ0 */
6490 void
6491 i40e_pf_enable_irq0(struct i40e_hw *hw)
6492 {
6493         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6494                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6495                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6496                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6497         I40E_WRITE_FLUSH(hw);
6498 }
6499
6500 static void
6501 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6502 {
6503         /* read pending request and disable first */
6504         i40e_pf_disable_irq0(hw);
6505         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6506         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6507                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6508
6509         if (no_queue)
6510                 /* Link no queues with irq0 */
6511                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6512                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6513 }
6514
6515 static void
6516 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6517 {
6518         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6519         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6520         int i;
6521         uint16_t abs_vf_id;
6522         uint32_t index, offset, val;
6523
6524         if (!pf->vfs)
6525                 return;
6526         /**
6527          * Try to find which VF trigger a reset, use absolute VF id to access
6528          * since the reg is global register.
6529          */
6530         for (i = 0; i < pf->vf_num; i++) {
6531                 abs_vf_id = hw->func_caps.vf_base_id + i;
6532                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6533                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6534                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6535                 /* VFR event occurred */
6536                 if (val & (0x1 << offset)) {
6537                         int ret;
6538
6539                         /* Clear the event first */
6540                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6541                                                         (0x1 << offset));
6542                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6543                         /**
6544                          * Only notify a VF reset event occurred,
6545                          * don't trigger another SW reset
6546                          */
6547                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6548                         if (ret != I40E_SUCCESS)
6549                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6550                 }
6551         }
6552 }
6553
6554 static void
6555 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6556 {
6557         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6558         int i;
6559
6560         for (i = 0; i < pf->vf_num; i++)
6561                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6562 }
6563
6564 static void
6565 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6566 {
6567         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6568         struct i40e_arq_event_info info;
6569         uint16_t pending, opcode;
6570         int ret;
6571
6572         info.buf_len = I40E_AQ_BUF_SZ;
6573         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6574         if (!info.msg_buf) {
6575                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6576                 return;
6577         }
6578
6579         pending = 1;
6580         while (pending) {
6581                 ret = i40e_clean_arq_element(hw, &info, &pending);
6582
6583                 if (ret != I40E_SUCCESS) {
6584                         PMD_DRV_LOG(INFO,
6585                                 "Failed to read msg from AdminQ, aq_err: %u",
6586                                 hw->aq.asq_last_status);
6587                         break;
6588                 }
6589                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6590
6591                 switch (opcode) {
6592                 case i40e_aqc_opc_send_msg_to_pf:
6593                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6594                         i40e_pf_host_handle_vf_msg(dev,
6595                                         rte_le_to_cpu_16(info.desc.retval),
6596                                         rte_le_to_cpu_32(info.desc.cookie_high),
6597                                         rte_le_to_cpu_32(info.desc.cookie_low),
6598                                         info.msg_buf,
6599                                         info.msg_len);
6600                         break;
6601                 case i40e_aqc_opc_get_link_status:
6602                         ret = i40e_dev_link_update(dev, 0);
6603                         if (!ret)
6604                                 _rte_eth_dev_callback_process(dev,
6605                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6606                         break;
6607                 default:
6608                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6609                                     opcode);
6610                         break;
6611                 }
6612         }
6613         rte_free(info.msg_buf);
6614 }
6615
6616 /**
6617  * Interrupt handler triggered by NIC  for handling
6618  * specific interrupt.
6619  *
6620  * @param handle
6621  *  Pointer to interrupt handle.
6622  * @param param
6623  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6624  *
6625  * @return
6626  *  void
6627  */
6628 static void
6629 i40e_dev_interrupt_handler(void *param)
6630 {
6631         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6632         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6633         uint32_t icr0;
6634
6635         /* Disable interrupt */
6636         i40e_pf_disable_irq0(hw);
6637
6638         /* read out interrupt causes */
6639         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6640
6641         /* No interrupt event indicated */
6642         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6643                 PMD_DRV_LOG(INFO, "No interrupt event");
6644                 goto done;
6645         }
6646         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6647                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6648         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6649                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6650         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6651                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6652         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6653                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6654         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6655                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6656         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6657                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6658         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6659                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6660
6661         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6662                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6663                 i40e_dev_handle_vfr_event(dev);
6664         }
6665         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6666                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6667                 i40e_dev_handle_aq_msg(dev);
6668         }
6669
6670 done:
6671         /* Enable interrupt */
6672         i40e_pf_enable_irq0(hw);
6673 }
6674
6675 static void
6676 i40e_dev_alarm_handler(void *param)
6677 {
6678         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6679         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6680         uint32_t icr0;
6681
6682         /* Disable interrupt */
6683         i40e_pf_disable_irq0(hw);
6684
6685         /* read out interrupt causes */
6686         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6687
6688         /* No interrupt event indicated */
6689         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6690                 goto done;
6691         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6692                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6693         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6694                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6695         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6696                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6697         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6698                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6699         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6700                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6701         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6702                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6703         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6704                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6705
6706         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6707                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6708                 i40e_dev_handle_vfr_event(dev);
6709         }
6710         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6711                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6712                 i40e_dev_handle_aq_msg(dev);
6713         }
6714
6715 done:
6716         /* Enable interrupt */
6717         i40e_pf_enable_irq0(hw);
6718         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6719                           i40e_dev_alarm_handler, dev);
6720 }
6721
6722 int
6723 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6724                          struct i40e_macvlan_filter *filter,
6725                          int total)
6726 {
6727         int ele_num, ele_buff_size;
6728         int num, actual_num, i;
6729         uint16_t flags;
6730         int ret = I40E_SUCCESS;
6731         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6732         struct i40e_aqc_add_macvlan_element_data *req_list;
6733
6734         if (filter == NULL  || total == 0)
6735                 return I40E_ERR_PARAM;
6736         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6737         ele_buff_size = hw->aq.asq_buf_size;
6738
6739         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6740         if (req_list == NULL) {
6741                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6742                 return I40E_ERR_NO_MEMORY;
6743         }
6744
6745         num = 0;
6746         do {
6747                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6748                 memset(req_list, 0, ele_buff_size);
6749
6750                 for (i = 0; i < actual_num; i++) {
6751                         rte_memcpy(req_list[i].mac_addr,
6752                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6753                         req_list[i].vlan_tag =
6754                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6755
6756                         switch (filter[num + i].filter_type) {
6757                         case RTE_MAC_PERFECT_MATCH:
6758                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6759                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6760                                 break;
6761                         case RTE_MACVLAN_PERFECT_MATCH:
6762                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6763                                 break;
6764                         case RTE_MAC_HASH_MATCH:
6765                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6766                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6767                                 break;
6768                         case RTE_MACVLAN_HASH_MATCH:
6769                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6770                                 break;
6771                         default:
6772                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6773                                 ret = I40E_ERR_PARAM;
6774                                 goto DONE;
6775                         }
6776
6777                         req_list[i].queue_number = 0;
6778
6779                         req_list[i].flags = rte_cpu_to_le_16(flags);
6780                 }
6781
6782                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6783                                                 actual_num, NULL);
6784                 if (ret != I40E_SUCCESS) {
6785                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6786                         goto DONE;
6787                 }
6788                 num += actual_num;
6789         } while (num < total);
6790
6791 DONE:
6792         rte_free(req_list);
6793         return ret;
6794 }
6795
6796 int
6797 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6798                             struct i40e_macvlan_filter *filter,
6799                             int total)
6800 {
6801         int ele_num, ele_buff_size;
6802         int num, actual_num, i;
6803         uint16_t flags;
6804         int ret = I40E_SUCCESS;
6805         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6806         struct i40e_aqc_remove_macvlan_element_data *req_list;
6807
6808         if (filter == NULL  || total == 0)
6809                 return I40E_ERR_PARAM;
6810
6811         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6812         ele_buff_size = hw->aq.asq_buf_size;
6813
6814         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6815         if (req_list == NULL) {
6816                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6817                 return I40E_ERR_NO_MEMORY;
6818         }
6819
6820         num = 0;
6821         do {
6822                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6823                 memset(req_list, 0, ele_buff_size);
6824
6825                 for (i = 0; i < actual_num; i++) {
6826                         rte_memcpy(req_list[i].mac_addr,
6827                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6828                         req_list[i].vlan_tag =
6829                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6830
6831                         switch (filter[num + i].filter_type) {
6832                         case RTE_MAC_PERFECT_MATCH:
6833                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6834                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6835                                 break;
6836                         case RTE_MACVLAN_PERFECT_MATCH:
6837                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6838                                 break;
6839                         case RTE_MAC_HASH_MATCH:
6840                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6841                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6842                                 break;
6843                         case RTE_MACVLAN_HASH_MATCH:
6844                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6845                                 break;
6846                         default:
6847                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6848                                 ret = I40E_ERR_PARAM;
6849                                 goto DONE;
6850                         }
6851                         req_list[i].flags = rte_cpu_to_le_16(flags);
6852                 }
6853
6854                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6855                                                 actual_num, NULL);
6856                 if (ret != I40E_SUCCESS) {
6857                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6858                         goto DONE;
6859                 }
6860                 num += actual_num;
6861         } while (num < total);
6862
6863 DONE:
6864         rte_free(req_list);
6865         return ret;
6866 }
6867
6868 /* Find out specific MAC filter */
6869 static struct i40e_mac_filter *
6870 i40e_find_mac_filter(struct i40e_vsi *vsi,
6871                          struct ether_addr *macaddr)
6872 {
6873         struct i40e_mac_filter *f;
6874
6875         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6876                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6877                         return f;
6878         }
6879
6880         return NULL;
6881 }
6882
6883 static bool
6884 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6885                          uint16_t vlan_id)
6886 {
6887         uint32_t vid_idx, vid_bit;
6888
6889         if (vlan_id > ETH_VLAN_ID_MAX)
6890                 return 0;
6891
6892         vid_idx = I40E_VFTA_IDX(vlan_id);
6893         vid_bit = I40E_VFTA_BIT(vlan_id);
6894
6895         if (vsi->vfta[vid_idx] & vid_bit)
6896                 return 1;
6897         else
6898                 return 0;
6899 }
6900
6901 static void
6902 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6903                        uint16_t vlan_id, bool on)
6904 {
6905         uint32_t vid_idx, vid_bit;
6906
6907         vid_idx = I40E_VFTA_IDX(vlan_id);
6908         vid_bit = I40E_VFTA_BIT(vlan_id);
6909
6910         if (on)
6911                 vsi->vfta[vid_idx] |= vid_bit;
6912         else
6913                 vsi->vfta[vid_idx] &= ~vid_bit;
6914 }
6915
6916 void
6917 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6918                      uint16_t vlan_id, bool on)
6919 {
6920         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6921         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6922         int ret;
6923
6924         if (vlan_id > ETH_VLAN_ID_MAX)
6925                 return;
6926
6927         i40e_store_vlan_filter(vsi, vlan_id, on);
6928
6929         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6930                 return;
6931
6932         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6933
6934         if (on) {
6935                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6936                                        &vlan_data, 1, NULL);
6937                 if (ret != I40E_SUCCESS)
6938                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6939         } else {
6940                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6941                                           &vlan_data, 1, NULL);
6942                 if (ret != I40E_SUCCESS)
6943                         PMD_DRV_LOG(ERR,
6944                                     "Failed to remove vlan filter");
6945         }
6946 }
6947
6948 /**
6949  * Find all vlan options for specific mac addr,
6950  * return with actual vlan found.
6951  */
6952 int
6953 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6954                            struct i40e_macvlan_filter *mv_f,
6955                            int num, struct ether_addr *addr)
6956 {
6957         int i;
6958         uint32_t j, k;
6959
6960         /**
6961          * Not to use i40e_find_vlan_filter to decrease the loop time,
6962          * although the code looks complex.
6963           */
6964         if (num < vsi->vlan_num)
6965                 return I40E_ERR_PARAM;
6966
6967         i = 0;
6968         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6969                 if (vsi->vfta[j]) {
6970                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6971                                 if (vsi->vfta[j] & (1 << k)) {
6972                                         if (i > num - 1) {
6973                                                 PMD_DRV_LOG(ERR,
6974                                                         "vlan number doesn't match");
6975                                                 return I40E_ERR_PARAM;
6976                                         }
6977                                         rte_memcpy(&mv_f[i].macaddr,
6978                                                         addr, ETH_ADDR_LEN);
6979                                         mv_f[i].vlan_id =
6980                                                 j * I40E_UINT32_BIT_SIZE + k;
6981                                         i++;
6982                                 }
6983                         }
6984                 }
6985         }
6986         return I40E_SUCCESS;
6987 }
6988
6989 static inline int
6990 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6991                            struct i40e_macvlan_filter *mv_f,
6992                            int num,
6993                            uint16_t vlan)
6994 {
6995         int i = 0;
6996         struct i40e_mac_filter *f;
6997
6998         if (num < vsi->mac_num)
6999                 return I40E_ERR_PARAM;
7000
7001         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7002                 if (i > num - 1) {
7003                         PMD_DRV_LOG(ERR, "buffer number not match");
7004                         return I40E_ERR_PARAM;
7005                 }
7006                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7007                                 ETH_ADDR_LEN);
7008                 mv_f[i].vlan_id = vlan;
7009                 mv_f[i].filter_type = f->mac_info.filter_type;
7010                 i++;
7011         }
7012
7013         return I40E_SUCCESS;
7014 }
7015
7016 static int
7017 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7018 {
7019         int i, j, num;
7020         struct i40e_mac_filter *f;
7021         struct i40e_macvlan_filter *mv_f;
7022         int ret = I40E_SUCCESS;
7023
7024         if (vsi == NULL || vsi->mac_num == 0)
7025                 return I40E_ERR_PARAM;
7026
7027         /* Case that no vlan is set */
7028         if (vsi->vlan_num == 0)
7029                 num = vsi->mac_num;
7030         else
7031                 num = vsi->mac_num * vsi->vlan_num;
7032
7033         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7034         if (mv_f == NULL) {
7035                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7036                 return I40E_ERR_NO_MEMORY;
7037         }
7038
7039         i = 0;
7040         if (vsi->vlan_num == 0) {
7041                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7042                         rte_memcpy(&mv_f[i].macaddr,
7043                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7044                         mv_f[i].filter_type = f->mac_info.filter_type;
7045                         mv_f[i].vlan_id = 0;
7046                         i++;
7047                 }
7048         } else {
7049                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7050                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7051                                         vsi->vlan_num, &f->mac_info.mac_addr);
7052                         if (ret != I40E_SUCCESS)
7053                                 goto DONE;
7054                         for (j = i; j < i + vsi->vlan_num; j++)
7055                                 mv_f[j].filter_type = f->mac_info.filter_type;
7056                         i += vsi->vlan_num;
7057                 }
7058         }
7059
7060         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7061 DONE:
7062         rte_free(mv_f);
7063
7064         return ret;
7065 }
7066
7067 int
7068 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7069 {
7070         struct i40e_macvlan_filter *mv_f;
7071         int mac_num;
7072         int ret = I40E_SUCCESS;
7073
7074         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
7075                 return I40E_ERR_PARAM;
7076
7077         /* If it's already set, just return */
7078         if (i40e_find_vlan_filter(vsi,vlan))
7079                 return I40E_SUCCESS;
7080
7081         mac_num = vsi->mac_num;
7082
7083         if (mac_num == 0) {
7084                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7085                 return I40E_ERR_PARAM;
7086         }
7087
7088         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7089
7090         if (mv_f == NULL) {
7091                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7092                 return I40E_ERR_NO_MEMORY;
7093         }
7094
7095         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7096
7097         if (ret != I40E_SUCCESS)
7098                 goto DONE;
7099
7100         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7101
7102         if (ret != I40E_SUCCESS)
7103                 goto DONE;
7104
7105         i40e_set_vlan_filter(vsi, vlan, 1);
7106
7107         vsi->vlan_num++;
7108         ret = I40E_SUCCESS;
7109 DONE:
7110         rte_free(mv_f);
7111         return ret;
7112 }
7113
7114 int
7115 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7116 {
7117         struct i40e_macvlan_filter *mv_f;
7118         int mac_num;
7119         int ret = I40E_SUCCESS;
7120
7121         /**
7122          * Vlan 0 is the generic filter for untagged packets
7123          * and can't be removed.
7124          */
7125         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
7126                 return I40E_ERR_PARAM;
7127
7128         /* If can't find it, just return */
7129         if (!i40e_find_vlan_filter(vsi, vlan))
7130                 return I40E_ERR_PARAM;
7131
7132         mac_num = vsi->mac_num;
7133
7134         if (mac_num == 0) {
7135                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7136                 return I40E_ERR_PARAM;
7137         }
7138
7139         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7140
7141         if (mv_f == NULL) {
7142                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7143                 return I40E_ERR_NO_MEMORY;
7144         }
7145
7146         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7147
7148         if (ret != I40E_SUCCESS)
7149                 goto DONE;
7150
7151         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7152
7153         if (ret != I40E_SUCCESS)
7154                 goto DONE;
7155
7156         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7157         if (vsi->vlan_num == 1) {
7158                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7159                 if (ret != I40E_SUCCESS)
7160                         goto DONE;
7161
7162                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7163                 if (ret != I40E_SUCCESS)
7164                         goto DONE;
7165         }
7166
7167         i40e_set_vlan_filter(vsi, vlan, 0);
7168
7169         vsi->vlan_num--;
7170         ret = I40E_SUCCESS;
7171 DONE:
7172         rte_free(mv_f);
7173         return ret;
7174 }
7175
7176 int
7177 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7178 {
7179         struct i40e_mac_filter *f;
7180         struct i40e_macvlan_filter *mv_f;
7181         int i, vlan_num = 0;
7182         int ret = I40E_SUCCESS;
7183
7184         /* If it's add and we've config it, return */
7185         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7186         if (f != NULL)
7187                 return I40E_SUCCESS;
7188         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7189                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7190
7191                 /**
7192                  * If vlan_num is 0, that's the first time to add mac,
7193                  * set mask for vlan_id 0.
7194                  */
7195                 if (vsi->vlan_num == 0) {
7196                         i40e_set_vlan_filter(vsi, 0, 1);
7197                         vsi->vlan_num = 1;
7198                 }
7199                 vlan_num = vsi->vlan_num;
7200         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7201                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7202                 vlan_num = 1;
7203
7204         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7205         if (mv_f == NULL) {
7206                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7207                 return I40E_ERR_NO_MEMORY;
7208         }
7209
7210         for (i = 0; i < vlan_num; i++) {
7211                 mv_f[i].filter_type = mac_filter->filter_type;
7212                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7213                                 ETH_ADDR_LEN);
7214         }
7215
7216         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7217                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7218                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7219                                         &mac_filter->mac_addr);
7220                 if (ret != I40E_SUCCESS)
7221                         goto DONE;
7222         }
7223
7224         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7225         if (ret != I40E_SUCCESS)
7226                 goto DONE;
7227
7228         /* Add the mac addr into mac list */
7229         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7230         if (f == NULL) {
7231                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7232                 ret = I40E_ERR_NO_MEMORY;
7233                 goto DONE;
7234         }
7235         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7236                         ETH_ADDR_LEN);
7237         f->mac_info.filter_type = mac_filter->filter_type;
7238         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7239         vsi->mac_num++;
7240
7241         ret = I40E_SUCCESS;
7242 DONE:
7243         rte_free(mv_f);
7244
7245         return ret;
7246 }
7247
7248 int
7249 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7250 {
7251         struct i40e_mac_filter *f;
7252         struct i40e_macvlan_filter *mv_f;
7253         int i, vlan_num;
7254         enum rte_mac_filter_type filter_type;
7255         int ret = I40E_SUCCESS;
7256
7257         /* Can't find it, return an error */
7258         f = i40e_find_mac_filter(vsi, addr);
7259         if (f == NULL)
7260                 return I40E_ERR_PARAM;
7261
7262         vlan_num = vsi->vlan_num;
7263         filter_type = f->mac_info.filter_type;
7264         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7265                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7266                 if (vlan_num == 0) {
7267                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7268                         return I40E_ERR_PARAM;
7269                 }
7270         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7271                         filter_type == RTE_MAC_HASH_MATCH)
7272                 vlan_num = 1;
7273
7274         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7275         if (mv_f == NULL) {
7276                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7277                 return I40E_ERR_NO_MEMORY;
7278         }
7279
7280         for (i = 0; i < vlan_num; i++) {
7281                 mv_f[i].filter_type = filter_type;
7282                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7283                                 ETH_ADDR_LEN);
7284         }
7285         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7286                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7287                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7288                 if (ret != I40E_SUCCESS)
7289                         goto DONE;
7290         }
7291
7292         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7293         if (ret != I40E_SUCCESS)
7294                 goto DONE;
7295
7296         /* Remove the mac addr into mac list */
7297         TAILQ_REMOVE(&vsi->mac_list, f, next);
7298         rte_free(f);
7299         vsi->mac_num--;
7300
7301         ret = I40E_SUCCESS;
7302 DONE:
7303         rte_free(mv_f);
7304         return ret;
7305 }
7306
7307 /* Configure hash enable flags for RSS */
7308 uint64_t
7309 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7310 {
7311         uint64_t hena = 0;
7312         int i;
7313
7314         if (!flags)
7315                 return hena;
7316
7317         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7318                 if (flags & (1ULL << i))
7319                         hena |= adapter->pctypes_tbl[i];
7320         }
7321
7322         return hena;
7323 }
7324
7325 /* Parse the hash enable flags */
7326 uint64_t
7327 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7328 {
7329         uint64_t rss_hf = 0;
7330
7331         if (!flags)
7332                 return rss_hf;
7333         int i;
7334
7335         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7336                 if (flags & adapter->pctypes_tbl[i])
7337                         rss_hf |= (1ULL << i);
7338         }
7339         return rss_hf;
7340 }
7341
7342 /* Disable RSS */
7343 static void
7344 i40e_pf_disable_rss(struct i40e_pf *pf)
7345 {
7346         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7347
7348         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7349         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7350         I40E_WRITE_FLUSH(hw);
7351 }
7352
7353 int
7354 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7355 {
7356         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7357         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7358         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7359                            I40E_VFQF_HKEY_MAX_INDEX :
7360                            I40E_PFQF_HKEY_MAX_INDEX;
7361         int ret = 0;
7362
7363         if (!key || key_len == 0) {
7364                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7365                 return 0;
7366         } else if (key_len != (key_idx + 1) *
7367                 sizeof(uint32_t)) {
7368                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7369                 return -EINVAL;
7370         }
7371
7372         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7373                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7374                         (struct i40e_aqc_get_set_rss_key_data *)key;
7375
7376                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7377                 if (ret)
7378                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7379         } else {
7380                 uint32_t *hash_key = (uint32_t *)key;
7381                 uint16_t i;
7382
7383                 if (vsi->type == I40E_VSI_SRIOV) {
7384                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7385                                 I40E_WRITE_REG(
7386                                         hw,
7387                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7388                                         hash_key[i]);
7389
7390                 } else {
7391                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7392                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7393                                                hash_key[i]);
7394                 }
7395                 I40E_WRITE_FLUSH(hw);
7396         }
7397
7398         return ret;
7399 }
7400
7401 static int
7402 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7403 {
7404         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7405         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7406         uint32_t reg;
7407         int ret;
7408
7409         if (!key || !key_len)
7410                 return -EINVAL;
7411
7412         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7413                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7414                         (struct i40e_aqc_get_set_rss_key_data *)key);
7415                 if (ret) {
7416                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7417                         return ret;
7418                 }
7419         } else {
7420                 uint32_t *key_dw = (uint32_t *)key;
7421                 uint16_t i;
7422
7423                 if (vsi->type == I40E_VSI_SRIOV) {
7424                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7425                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7426                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7427                         }
7428                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7429                                    sizeof(uint32_t);
7430                 } else {
7431                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7432                                 reg = I40E_PFQF_HKEY(i);
7433                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7434                         }
7435                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7436                                    sizeof(uint32_t);
7437                 }
7438         }
7439         return 0;
7440 }
7441
7442 static int
7443 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7444 {
7445         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7446         uint64_t hena;
7447         int ret;
7448
7449         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7450                                rss_conf->rss_key_len);
7451         if (ret)
7452                 return ret;
7453
7454         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7455         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7456         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7457         I40E_WRITE_FLUSH(hw);
7458
7459         return 0;
7460 }
7461
7462 static int
7463 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7464                          struct rte_eth_rss_conf *rss_conf)
7465 {
7466         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7467         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7468         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7469         uint64_t hena;
7470
7471         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7472         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7473
7474         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7475                 if (rss_hf != 0) /* Enable RSS */
7476                         return -EINVAL;
7477                 return 0; /* Nothing to do */
7478         }
7479         /* RSS enabled */
7480         if (rss_hf == 0) /* Disable RSS */
7481                 return -EINVAL;
7482
7483         return i40e_hw_rss_hash_set(pf, rss_conf);
7484 }
7485
7486 static int
7487 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7488                            struct rte_eth_rss_conf *rss_conf)
7489 {
7490         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7491         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7492         uint64_t hena;
7493         int ret;
7494
7495         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7496                          &rss_conf->rss_key_len);
7497         if (ret)
7498                 return ret;
7499
7500         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7501         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7502         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7503
7504         return 0;
7505 }
7506
7507 static int
7508 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7509 {
7510         switch (filter_type) {
7511         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7512                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7513                 break;
7514         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7515                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7516                 break;
7517         case RTE_TUNNEL_FILTER_IMAC_TENID:
7518                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7519                 break;
7520         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7521                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7522                 break;
7523         case ETH_TUNNEL_FILTER_IMAC:
7524                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7525                 break;
7526         case ETH_TUNNEL_FILTER_OIP:
7527                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7528                 break;
7529         case ETH_TUNNEL_FILTER_IIP:
7530                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7531                 break;
7532         default:
7533                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7534                 return -EINVAL;
7535         }
7536
7537         return 0;
7538 }
7539
7540 /* Convert tunnel filter structure */
7541 static int
7542 i40e_tunnel_filter_convert(
7543         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7544         struct i40e_tunnel_filter *tunnel_filter)
7545 {
7546         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7547                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7548         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7549                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7550         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7551         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7552              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7553             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7554                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7555         else
7556                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7557         tunnel_filter->input.flags = cld_filter->element.flags;
7558         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7559         tunnel_filter->queue = cld_filter->element.queue_number;
7560         rte_memcpy(tunnel_filter->input.general_fields,
7561                    cld_filter->general_fields,
7562                    sizeof(cld_filter->general_fields));
7563
7564         return 0;
7565 }
7566
7567 /* Check if there exists the tunnel filter */
7568 struct i40e_tunnel_filter *
7569 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7570                              const struct i40e_tunnel_filter_input *input)
7571 {
7572         int ret;
7573
7574         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7575         if (ret < 0)
7576                 return NULL;
7577
7578         return tunnel_rule->hash_map[ret];
7579 }
7580
7581 /* Add a tunnel filter into the SW list */
7582 static int
7583 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7584                              struct i40e_tunnel_filter *tunnel_filter)
7585 {
7586         struct i40e_tunnel_rule *rule = &pf->tunnel;
7587         int ret;
7588
7589         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7590         if (ret < 0) {
7591                 PMD_DRV_LOG(ERR,
7592                             "Failed to insert tunnel filter to hash table %d!",
7593                             ret);
7594                 return ret;
7595         }
7596         rule->hash_map[ret] = tunnel_filter;
7597
7598         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7599
7600         return 0;
7601 }
7602
7603 /* Delete a tunnel filter from the SW list */
7604 int
7605 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7606                           struct i40e_tunnel_filter_input *input)
7607 {
7608         struct i40e_tunnel_rule *rule = &pf->tunnel;
7609         struct i40e_tunnel_filter *tunnel_filter;
7610         int ret;
7611
7612         ret = rte_hash_del_key(rule->hash_table, input);
7613         if (ret < 0) {
7614                 PMD_DRV_LOG(ERR,
7615                             "Failed to delete tunnel filter to hash table %d!",
7616                             ret);
7617                 return ret;
7618         }
7619         tunnel_filter = rule->hash_map[ret];
7620         rule->hash_map[ret] = NULL;
7621
7622         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7623         rte_free(tunnel_filter);
7624
7625         return 0;
7626 }
7627
7628 int
7629 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7630                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7631                         uint8_t add)
7632 {
7633         uint16_t ip_type;
7634         uint32_t ipv4_addr, ipv4_addr_le;
7635         uint8_t i, tun_type = 0;
7636         /* internal varialbe to convert ipv6 byte order */
7637         uint32_t convert_ipv6[4];
7638         int val, ret = 0;
7639         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7640         struct i40e_vsi *vsi = pf->main_vsi;
7641         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7642         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7643         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7644         struct i40e_tunnel_filter *tunnel, *node;
7645         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7646
7647         cld_filter = rte_zmalloc("tunnel_filter",
7648                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7649         0);
7650
7651         if (NULL == cld_filter) {
7652                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7653                 return -ENOMEM;
7654         }
7655         pfilter = cld_filter;
7656
7657         ether_addr_copy(&tunnel_filter->outer_mac,
7658                         (struct ether_addr *)&pfilter->element.outer_mac);
7659         ether_addr_copy(&tunnel_filter->inner_mac,
7660                         (struct ether_addr *)&pfilter->element.inner_mac);
7661
7662         pfilter->element.inner_vlan =
7663                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7664         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7665                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7666                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7667                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7668                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7669                                 &ipv4_addr_le,
7670                                 sizeof(pfilter->element.ipaddr.v4.data));
7671         } else {
7672                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7673                 for (i = 0; i < 4; i++) {
7674                         convert_ipv6[i] =
7675                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7676                 }
7677                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7678                            &convert_ipv6,
7679                            sizeof(pfilter->element.ipaddr.v6.data));
7680         }
7681
7682         /* check tunneled type */
7683         switch (tunnel_filter->tunnel_type) {
7684         case RTE_TUNNEL_TYPE_VXLAN:
7685                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7686                 break;
7687         case RTE_TUNNEL_TYPE_NVGRE:
7688                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7689                 break;
7690         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7691                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7692                 break;
7693         default:
7694                 /* Other tunnel types is not supported. */
7695                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7696                 rte_free(cld_filter);
7697                 return -EINVAL;
7698         }
7699
7700         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7701                                        &pfilter->element.flags);
7702         if (val < 0) {
7703                 rte_free(cld_filter);
7704                 return -EINVAL;
7705         }
7706
7707         pfilter->element.flags |= rte_cpu_to_le_16(
7708                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7709                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7710         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7711         pfilter->element.queue_number =
7712                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7713
7714         /* Check if there is the filter in SW list */
7715         memset(&check_filter, 0, sizeof(check_filter));
7716         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7717         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7718         if (add && node) {
7719                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7720                 rte_free(cld_filter);
7721                 return -EINVAL;
7722         }
7723
7724         if (!add && !node) {
7725                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7726                 rte_free(cld_filter);
7727                 return -EINVAL;
7728         }
7729
7730         if (add) {
7731                 ret = i40e_aq_add_cloud_filters(hw,
7732                                         vsi->seid, &cld_filter->element, 1);
7733                 if (ret < 0) {
7734                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7735                         rte_free(cld_filter);
7736                         return -ENOTSUP;
7737                 }
7738                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7739                 if (tunnel == NULL) {
7740                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7741                         rte_free(cld_filter);
7742                         return -ENOMEM;
7743                 }
7744
7745                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7746                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7747                 if (ret < 0)
7748                         rte_free(tunnel);
7749         } else {
7750                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7751                                                    &cld_filter->element, 1);
7752                 if (ret < 0) {
7753                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7754                         rte_free(cld_filter);
7755                         return -ENOTSUP;
7756                 }
7757                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7758         }
7759
7760         rte_free(cld_filter);
7761         return ret;
7762 }
7763
7764 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7765 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7766 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7767 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7768 #define I40E_TR_GRE_KEY_MASK                    0x400
7769 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7770 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7771
7772 static enum
7773 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7774 {
7775         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7776         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7777         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7778         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7779         enum i40e_status_code status = I40E_SUCCESS;
7780
7781         if (pf->support_multi_driver) {
7782                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7783                 return I40E_NOT_SUPPORTED;
7784         }
7785
7786         memset(&filter_replace, 0,
7787                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7788         memset(&filter_replace_buf, 0,
7789                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7790
7791         /* create L1 filter */
7792         filter_replace.old_filter_type =
7793                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7794         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7795         filter_replace.tr_bit = 0;
7796
7797         /* Prepare the buffer, 3 entries */
7798         filter_replace_buf.data[0] =
7799                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7800         filter_replace_buf.data[0] |=
7801                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7802         filter_replace_buf.data[2] = 0xFF;
7803         filter_replace_buf.data[3] = 0xFF;
7804         filter_replace_buf.data[4] =
7805                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7806         filter_replace_buf.data[4] |=
7807                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7808         filter_replace_buf.data[7] = 0xF0;
7809         filter_replace_buf.data[8]
7810                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7811         filter_replace_buf.data[8] |=
7812                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7813         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7814                 I40E_TR_GENEVE_KEY_MASK |
7815                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7816         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7817                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7818                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7819
7820         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7821                                                &filter_replace_buf);
7822         if (!status && (filter_replace.old_filter_type !=
7823                         filter_replace.new_filter_type))
7824                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7825                             " original: 0x%x, new: 0x%x",
7826                             dev->device->name,
7827                             filter_replace.old_filter_type,
7828                             filter_replace.new_filter_type);
7829
7830         return status;
7831 }
7832
7833 static enum
7834 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7835 {
7836         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7837         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7838         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7839         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7840         enum i40e_status_code status = I40E_SUCCESS;
7841
7842         if (pf->support_multi_driver) {
7843                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7844                 return I40E_NOT_SUPPORTED;
7845         }
7846
7847         /* For MPLSoUDP */
7848         memset(&filter_replace, 0,
7849                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7850         memset(&filter_replace_buf, 0,
7851                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7852         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7853                 I40E_AQC_MIRROR_CLOUD_FILTER;
7854         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7855         filter_replace.new_filter_type =
7856                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7857         /* Prepare the buffer, 2 entries */
7858         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7859         filter_replace_buf.data[0] |=
7860                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7861         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7862         filter_replace_buf.data[4] |=
7863                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7864         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7865                                                &filter_replace_buf);
7866         if (status < 0)
7867                 return status;
7868         if (filter_replace.old_filter_type !=
7869             filter_replace.new_filter_type)
7870                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7871                             " original: 0x%x, new: 0x%x",
7872                             dev->device->name,
7873                             filter_replace.old_filter_type,
7874                             filter_replace.new_filter_type);
7875
7876         /* For MPLSoGRE */
7877         memset(&filter_replace, 0,
7878                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7879         memset(&filter_replace_buf, 0,
7880                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7881
7882         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7883                 I40E_AQC_MIRROR_CLOUD_FILTER;
7884         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7885         filter_replace.new_filter_type =
7886                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7887         /* Prepare the buffer, 2 entries */
7888         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7889         filter_replace_buf.data[0] |=
7890                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7891         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7892         filter_replace_buf.data[4] |=
7893                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7894
7895         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7896                                                &filter_replace_buf);
7897         if (!status && (filter_replace.old_filter_type !=
7898                         filter_replace.new_filter_type))
7899                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7900                             " original: 0x%x, new: 0x%x",
7901                             dev->device->name,
7902                             filter_replace.old_filter_type,
7903                             filter_replace.new_filter_type);
7904
7905         return status;
7906 }
7907
7908 static enum i40e_status_code
7909 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7910 {
7911         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7912         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7913         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7914         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7915         enum i40e_status_code status = I40E_SUCCESS;
7916
7917         if (pf->support_multi_driver) {
7918                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7919                 return I40E_NOT_SUPPORTED;
7920         }
7921
7922         /* For GTP-C */
7923         memset(&filter_replace, 0,
7924                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7925         memset(&filter_replace_buf, 0,
7926                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7927         /* create L1 filter */
7928         filter_replace.old_filter_type =
7929                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7930         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7931         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7932                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7933         /* Prepare the buffer, 2 entries */
7934         filter_replace_buf.data[0] =
7935                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7936         filter_replace_buf.data[0] |=
7937                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7938         filter_replace_buf.data[2] = 0xFF;
7939         filter_replace_buf.data[3] = 0xFF;
7940         filter_replace_buf.data[4] =
7941                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7942         filter_replace_buf.data[4] |=
7943                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7944         filter_replace_buf.data[6] = 0xFF;
7945         filter_replace_buf.data[7] = 0xFF;
7946         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7947                                                &filter_replace_buf);
7948         if (status < 0)
7949                 return status;
7950         if (filter_replace.old_filter_type !=
7951             filter_replace.new_filter_type)
7952                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7953                             " original: 0x%x, new: 0x%x",
7954                             dev->device->name,
7955                             filter_replace.old_filter_type,
7956                             filter_replace.new_filter_type);
7957
7958         /* for GTP-U */
7959         memset(&filter_replace, 0,
7960                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7961         memset(&filter_replace_buf, 0,
7962                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7963         /* create L1 filter */
7964         filter_replace.old_filter_type =
7965                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7966         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7967         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7968                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7969         /* Prepare the buffer, 2 entries */
7970         filter_replace_buf.data[0] =
7971                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7972         filter_replace_buf.data[0] |=
7973                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7974         filter_replace_buf.data[2] = 0xFF;
7975         filter_replace_buf.data[3] = 0xFF;
7976         filter_replace_buf.data[4] =
7977                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7978         filter_replace_buf.data[4] |=
7979                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7980         filter_replace_buf.data[6] = 0xFF;
7981         filter_replace_buf.data[7] = 0xFF;
7982
7983         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7984                                                &filter_replace_buf);
7985         if (!status && (filter_replace.old_filter_type !=
7986                         filter_replace.new_filter_type))
7987                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7988                             " original: 0x%x, new: 0x%x",
7989                             dev->device->name,
7990                             filter_replace.old_filter_type,
7991                             filter_replace.new_filter_type);
7992
7993         return status;
7994 }
7995
7996 static enum
7997 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7998 {
7999         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8000         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8001         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8002         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8003         enum i40e_status_code status = I40E_SUCCESS;
8004
8005         if (pf->support_multi_driver) {
8006                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8007                 return I40E_NOT_SUPPORTED;
8008         }
8009
8010         /* for GTP-C */
8011         memset(&filter_replace, 0,
8012                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8013         memset(&filter_replace_buf, 0,
8014                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8015         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8016         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8017         filter_replace.new_filter_type =
8018                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8019         /* Prepare the buffer, 2 entries */
8020         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8021         filter_replace_buf.data[0] |=
8022                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8023         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8024         filter_replace_buf.data[4] |=
8025                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8026         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8027                                                &filter_replace_buf);
8028         if (status < 0)
8029                 return status;
8030         if (filter_replace.old_filter_type !=
8031             filter_replace.new_filter_type)
8032                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8033                             " original: 0x%x, new: 0x%x",
8034                             dev->device->name,
8035                             filter_replace.old_filter_type,
8036                             filter_replace.new_filter_type);
8037
8038         /* for GTP-U */
8039         memset(&filter_replace, 0,
8040                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8041         memset(&filter_replace_buf, 0,
8042                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8043         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8044         filter_replace.old_filter_type =
8045                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8046         filter_replace.new_filter_type =
8047                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8048         /* Prepare the buffer, 2 entries */
8049         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8050         filter_replace_buf.data[0] |=
8051                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8052         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8053         filter_replace_buf.data[4] |=
8054                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8055
8056         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8057                                                &filter_replace_buf);
8058         if (!status && (filter_replace.old_filter_type !=
8059                         filter_replace.new_filter_type))
8060                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8061                             " original: 0x%x, new: 0x%x",
8062                             dev->device->name,
8063                             filter_replace.old_filter_type,
8064                             filter_replace.new_filter_type);
8065
8066         return status;
8067 }
8068
8069 int
8070 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8071                       struct i40e_tunnel_filter_conf *tunnel_filter,
8072                       uint8_t add)
8073 {
8074         uint16_t ip_type;
8075         uint32_t ipv4_addr, ipv4_addr_le;
8076         uint8_t i, tun_type = 0;
8077         /* internal variable to convert ipv6 byte order */
8078         uint32_t convert_ipv6[4];
8079         int val, ret = 0;
8080         struct i40e_pf_vf *vf = NULL;
8081         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8082         struct i40e_vsi *vsi;
8083         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8084         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8085         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8086         struct i40e_tunnel_filter *tunnel, *node;
8087         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8088         uint32_t teid_le;
8089         bool big_buffer = 0;
8090
8091         cld_filter = rte_zmalloc("tunnel_filter",
8092                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8093                          0);
8094
8095         if (cld_filter == NULL) {
8096                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8097                 return -ENOMEM;
8098         }
8099         pfilter = cld_filter;
8100
8101         ether_addr_copy(&tunnel_filter->outer_mac,
8102                         (struct ether_addr *)&pfilter->element.outer_mac);
8103         ether_addr_copy(&tunnel_filter->inner_mac,
8104                         (struct ether_addr *)&pfilter->element.inner_mac);
8105
8106         pfilter->element.inner_vlan =
8107                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8108         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8109                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8110                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8111                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8112                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8113                                 &ipv4_addr_le,
8114                                 sizeof(pfilter->element.ipaddr.v4.data));
8115         } else {
8116                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8117                 for (i = 0; i < 4; i++) {
8118                         convert_ipv6[i] =
8119                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8120                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8121                 }
8122                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8123                            &convert_ipv6,
8124                            sizeof(pfilter->element.ipaddr.v6.data));
8125         }
8126
8127         /* check tunneled type */
8128         switch (tunnel_filter->tunnel_type) {
8129         case I40E_TUNNEL_TYPE_VXLAN:
8130                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8131                 break;
8132         case I40E_TUNNEL_TYPE_NVGRE:
8133                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8134                 break;
8135         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8136                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8137                 break;
8138         case I40E_TUNNEL_TYPE_MPLSoUDP:
8139                 if (!pf->mpls_replace_flag) {
8140                         i40e_replace_mpls_l1_filter(pf);
8141                         i40e_replace_mpls_cloud_filter(pf);
8142                         pf->mpls_replace_flag = 1;
8143                 }
8144                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8145                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8146                         teid_le >> 4;
8147                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8148                         (teid_le & 0xF) << 12;
8149                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8150                         0x40;
8151                 big_buffer = 1;
8152                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8153                 break;
8154         case I40E_TUNNEL_TYPE_MPLSoGRE:
8155                 if (!pf->mpls_replace_flag) {
8156                         i40e_replace_mpls_l1_filter(pf);
8157                         i40e_replace_mpls_cloud_filter(pf);
8158                         pf->mpls_replace_flag = 1;
8159                 }
8160                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8161                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8162                         teid_le >> 4;
8163                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8164                         (teid_le & 0xF) << 12;
8165                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8166                         0x0;
8167                 big_buffer = 1;
8168                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8169                 break;
8170         case I40E_TUNNEL_TYPE_GTPC:
8171                 if (!pf->gtp_replace_flag) {
8172                         i40e_replace_gtp_l1_filter(pf);
8173                         i40e_replace_gtp_cloud_filter(pf);
8174                         pf->gtp_replace_flag = 1;
8175                 }
8176                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8177                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8178                         (teid_le >> 16) & 0xFFFF;
8179                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8180                         teid_le & 0xFFFF;
8181                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8182                         0x0;
8183                 big_buffer = 1;
8184                 break;
8185         case I40E_TUNNEL_TYPE_GTPU:
8186                 if (!pf->gtp_replace_flag) {
8187                         i40e_replace_gtp_l1_filter(pf);
8188                         i40e_replace_gtp_cloud_filter(pf);
8189                         pf->gtp_replace_flag = 1;
8190                 }
8191                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8192                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8193                         (teid_le >> 16) & 0xFFFF;
8194                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8195                         teid_le & 0xFFFF;
8196                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8197                         0x0;
8198                 big_buffer = 1;
8199                 break;
8200         case I40E_TUNNEL_TYPE_QINQ:
8201                 if (!pf->qinq_replace_flag) {
8202                         ret = i40e_cloud_filter_qinq_create(pf);
8203                         if (ret < 0)
8204                                 PMD_DRV_LOG(DEBUG,
8205                                             "QinQ tunnel filter already created.");
8206                         pf->qinq_replace_flag = 1;
8207                 }
8208                 /*      Add in the General fields the values of
8209                  *      the Outer and Inner VLAN
8210                  *      Big Buffer should be set, see changes in
8211                  *      i40e_aq_add_cloud_filters
8212                  */
8213                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8214                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8215                 big_buffer = 1;
8216                 break;
8217         default:
8218                 /* Other tunnel types is not supported. */
8219                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8220                 rte_free(cld_filter);
8221                 return -EINVAL;
8222         }
8223
8224         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8225                 pfilter->element.flags =
8226                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8227         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8228                 pfilter->element.flags =
8229                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8230         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8231                 pfilter->element.flags =
8232                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8233         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8234                 pfilter->element.flags =
8235                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8236         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8237                 pfilter->element.flags |=
8238                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8239         else {
8240                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8241                                                 &pfilter->element.flags);
8242                 if (val < 0) {
8243                         rte_free(cld_filter);
8244                         return -EINVAL;
8245                 }
8246         }
8247
8248         pfilter->element.flags |= rte_cpu_to_le_16(
8249                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8250                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8251         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8252         pfilter->element.queue_number =
8253                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8254
8255         if (!tunnel_filter->is_to_vf)
8256                 vsi = pf->main_vsi;
8257         else {
8258                 if (tunnel_filter->vf_id >= pf->vf_num) {
8259                         PMD_DRV_LOG(ERR, "Invalid argument.");
8260                         rte_free(cld_filter);
8261                         return -EINVAL;
8262                 }
8263                 vf = &pf->vfs[tunnel_filter->vf_id];
8264                 vsi = vf->vsi;
8265         }
8266
8267         /* Check if there is the filter in SW list */
8268         memset(&check_filter, 0, sizeof(check_filter));
8269         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8270         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8271         check_filter.vf_id = tunnel_filter->vf_id;
8272         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8273         if (add && node) {
8274                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8275                 rte_free(cld_filter);
8276                 return -EINVAL;
8277         }
8278
8279         if (!add && !node) {
8280                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8281                 rte_free(cld_filter);
8282                 return -EINVAL;
8283         }
8284
8285         if (add) {
8286                 if (big_buffer)
8287                         ret = i40e_aq_add_cloud_filters_bb(hw,
8288                                                    vsi->seid, cld_filter, 1);
8289                 else
8290                         ret = i40e_aq_add_cloud_filters(hw,
8291                                         vsi->seid, &cld_filter->element, 1);
8292                 if (ret < 0) {
8293                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8294                         rte_free(cld_filter);
8295                         return -ENOTSUP;
8296                 }
8297                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8298                 if (tunnel == NULL) {
8299                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8300                         rte_free(cld_filter);
8301                         return -ENOMEM;
8302                 }
8303
8304                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8305                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8306                 if (ret < 0)
8307                         rte_free(tunnel);
8308         } else {
8309                 if (big_buffer)
8310                         ret = i40e_aq_rem_cloud_filters_bb(
8311                                 hw, vsi->seid, cld_filter, 1);
8312                 else
8313                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8314                                                 &cld_filter->element, 1);
8315                 if (ret < 0) {
8316                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8317                         rte_free(cld_filter);
8318                         return -ENOTSUP;
8319                 }
8320                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8321         }
8322
8323         rte_free(cld_filter);
8324         return ret;
8325 }
8326
8327 static int
8328 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8329 {
8330         uint8_t i;
8331
8332         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8333                 if (pf->vxlan_ports[i] == port)
8334                         return i;
8335         }
8336
8337         return -1;
8338 }
8339
8340 static int
8341 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8342 {
8343         int  idx, ret;
8344         uint8_t filter_idx;
8345         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8346
8347         idx = i40e_get_vxlan_port_idx(pf, port);
8348
8349         /* Check if port already exists */
8350         if (idx >= 0) {
8351                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8352                 return -EINVAL;
8353         }
8354
8355         /* Now check if there is space to add the new port */
8356         idx = i40e_get_vxlan_port_idx(pf, 0);
8357         if (idx < 0) {
8358                 PMD_DRV_LOG(ERR,
8359                         "Maximum number of UDP ports reached, not adding port %d",
8360                         port);
8361                 return -ENOSPC;
8362         }
8363
8364         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8365                                         &filter_idx, NULL);
8366         if (ret < 0) {
8367                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8368                 return -1;
8369         }
8370
8371         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8372                          port,  filter_idx);
8373
8374         /* New port: add it and mark its index in the bitmap */
8375         pf->vxlan_ports[idx] = port;
8376         pf->vxlan_bitmap |= (1 << idx);
8377
8378         if (!(pf->flags & I40E_FLAG_VXLAN))
8379                 pf->flags |= I40E_FLAG_VXLAN;
8380
8381         return 0;
8382 }
8383
8384 static int
8385 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8386 {
8387         int idx;
8388         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8389
8390         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8391                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8392                 return -EINVAL;
8393         }
8394
8395         idx = i40e_get_vxlan_port_idx(pf, port);
8396
8397         if (idx < 0) {
8398                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8399                 return -EINVAL;
8400         }
8401
8402         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8403                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8404                 return -1;
8405         }
8406
8407         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8408                         port, idx);
8409
8410         pf->vxlan_ports[idx] = 0;
8411         pf->vxlan_bitmap &= ~(1 << idx);
8412
8413         if (!pf->vxlan_bitmap)
8414                 pf->flags &= ~I40E_FLAG_VXLAN;
8415
8416         return 0;
8417 }
8418
8419 /* Add UDP tunneling port */
8420 static int
8421 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8422                              struct rte_eth_udp_tunnel *udp_tunnel)
8423 {
8424         int ret = 0;
8425         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8426
8427         if (udp_tunnel == NULL)
8428                 return -EINVAL;
8429
8430         switch (udp_tunnel->prot_type) {
8431         case RTE_TUNNEL_TYPE_VXLAN:
8432                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8433                 break;
8434
8435         case RTE_TUNNEL_TYPE_GENEVE:
8436         case RTE_TUNNEL_TYPE_TEREDO:
8437                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8438                 ret = -1;
8439                 break;
8440
8441         default:
8442                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8443                 ret = -1;
8444                 break;
8445         }
8446
8447         return ret;
8448 }
8449
8450 /* Remove UDP tunneling port */
8451 static int
8452 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8453                              struct rte_eth_udp_tunnel *udp_tunnel)
8454 {
8455         int ret = 0;
8456         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8457
8458         if (udp_tunnel == NULL)
8459                 return -EINVAL;
8460
8461         switch (udp_tunnel->prot_type) {
8462         case RTE_TUNNEL_TYPE_VXLAN:
8463                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8464                 break;
8465         case RTE_TUNNEL_TYPE_GENEVE:
8466         case RTE_TUNNEL_TYPE_TEREDO:
8467                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8468                 ret = -1;
8469                 break;
8470         default:
8471                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8472                 ret = -1;
8473                 break;
8474         }
8475
8476         return ret;
8477 }
8478
8479 /* Calculate the maximum number of contiguous PF queues that are configured */
8480 static int
8481 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8482 {
8483         struct rte_eth_dev_data *data = pf->dev_data;
8484         int i, num;
8485         struct i40e_rx_queue *rxq;
8486
8487         num = 0;
8488         for (i = 0; i < pf->lan_nb_qps; i++) {
8489                 rxq = data->rx_queues[i];
8490                 if (rxq && rxq->q_set)
8491                         num++;
8492                 else
8493                         break;
8494         }
8495
8496         return num;
8497 }
8498
8499 /* Configure RSS */
8500 static int
8501 i40e_pf_config_rss(struct i40e_pf *pf)
8502 {
8503         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8504         struct rte_eth_rss_conf rss_conf;
8505         uint32_t i, lut = 0;
8506         uint16_t j, num;
8507
8508         /*
8509          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8510          * It's necessary to calculate the actual PF queues that are configured.
8511          */
8512         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8513                 num = i40e_pf_calc_configured_queues_num(pf);
8514         else
8515                 num = pf->dev_data->nb_rx_queues;
8516
8517         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8518         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8519                         num);
8520
8521         if (num == 0) {
8522                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8523                 return -ENOTSUP;
8524         }
8525
8526         if (pf->adapter->rss_reta_updated == 0) {
8527                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8528                         if (j == num)
8529                                 j = 0;
8530                         lut = (lut << 8) | (j & ((0x1 <<
8531                                 hw->func_caps.rss_table_entry_width) - 1));
8532                         if ((i & 3) == 3)
8533                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8534                                                rte_bswap32(lut));
8535                 }
8536         }
8537
8538         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8539         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8540                 i40e_pf_disable_rss(pf);
8541                 return 0;
8542         }
8543         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8544                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8545                 /* Random default keys */
8546                 static uint32_t rss_key_default[] = {0x6b793944,
8547                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8548                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8549                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8550
8551                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8552                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8553                                                         sizeof(uint32_t);
8554         }
8555
8556         return i40e_hw_rss_hash_set(pf, &rss_conf);
8557 }
8558
8559 static int
8560 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8561                                struct rte_eth_tunnel_filter_conf *filter)
8562 {
8563         if (pf == NULL || filter == NULL) {
8564                 PMD_DRV_LOG(ERR, "Invalid parameter");
8565                 return -EINVAL;
8566         }
8567
8568         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8569                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8570                 return -EINVAL;
8571         }
8572
8573         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8574                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8575                 return -EINVAL;
8576         }
8577
8578         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8579                 (is_zero_ether_addr(&filter->outer_mac))) {
8580                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8581                 return -EINVAL;
8582         }
8583
8584         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8585                 (is_zero_ether_addr(&filter->inner_mac))) {
8586                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8587                 return -EINVAL;
8588         }
8589
8590         return 0;
8591 }
8592
8593 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8594 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8595 static int
8596 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8597 {
8598         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8599         uint32_t val, reg;
8600         int ret = -EINVAL;
8601
8602         if (pf->support_multi_driver) {
8603                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8604                 return -ENOTSUP;
8605         }
8606
8607         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8608         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8609
8610         if (len == 3) {
8611                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8612         } else if (len == 4) {
8613                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8614         } else {
8615                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8616                 return ret;
8617         }
8618
8619         if (reg != val) {
8620                 ret = i40e_aq_debug_write_global_register(hw,
8621                                                    I40E_GL_PRS_FVBM(2),
8622                                                    reg, NULL);
8623                 if (ret != 0)
8624                         return ret;
8625                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8626                             "with value 0x%08x",
8627                             I40E_GL_PRS_FVBM(2), reg);
8628         } else {
8629                 ret = 0;
8630         }
8631         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8632                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8633
8634         return ret;
8635 }
8636
8637 static int
8638 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8639 {
8640         int ret = -EINVAL;
8641
8642         if (!hw || !cfg)
8643                 return -EINVAL;
8644
8645         switch (cfg->cfg_type) {
8646         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8647                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8648                 break;
8649         default:
8650                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8651                 break;
8652         }
8653
8654         return ret;
8655 }
8656
8657 static int
8658 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8659                                enum rte_filter_op filter_op,
8660                                void *arg)
8661 {
8662         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8663         int ret = I40E_ERR_PARAM;
8664
8665         switch (filter_op) {
8666         case RTE_ETH_FILTER_SET:
8667                 ret = i40e_dev_global_config_set(hw,
8668                         (struct rte_eth_global_cfg *)arg);
8669                 break;
8670         default:
8671                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8672                 break;
8673         }
8674
8675         return ret;
8676 }
8677
8678 static int
8679 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8680                           enum rte_filter_op filter_op,
8681                           void *arg)
8682 {
8683         struct rte_eth_tunnel_filter_conf *filter;
8684         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8685         int ret = I40E_SUCCESS;
8686
8687         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8688
8689         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8690                 return I40E_ERR_PARAM;
8691
8692         switch (filter_op) {
8693         case RTE_ETH_FILTER_NOP:
8694                 if (!(pf->flags & I40E_FLAG_VXLAN))
8695                         ret = I40E_NOT_SUPPORTED;
8696                 break;
8697         case RTE_ETH_FILTER_ADD:
8698                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8699                 break;
8700         case RTE_ETH_FILTER_DELETE:
8701                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8702                 break;
8703         default:
8704                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8705                 ret = I40E_ERR_PARAM;
8706                 break;
8707         }
8708
8709         return ret;
8710 }
8711
8712 static int
8713 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8714 {
8715         int ret = 0;
8716         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8717
8718         /* RSS setup */
8719         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8720                 ret = i40e_pf_config_rss(pf);
8721         else
8722                 i40e_pf_disable_rss(pf);
8723
8724         return ret;
8725 }
8726
8727 /* Get the symmetric hash enable configurations per port */
8728 static void
8729 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8730 {
8731         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8732
8733         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8734 }
8735
8736 /* Set the symmetric hash enable configurations per port */
8737 static void
8738 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8739 {
8740         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8741
8742         if (enable > 0) {
8743                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8744                         PMD_DRV_LOG(INFO,
8745                                 "Symmetric hash has already been enabled");
8746                         return;
8747                 }
8748                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8749         } else {
8750                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8751                         PMD_DRV_LOG(INFO,
8752                                 "Symmetric hash has already been disabled");
8753                         return;
8754                 }
8755                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8756         }
8757         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8758         I40E_WRITE_FLUSH(hw);
8759 }
8760
8761 /*
8762  * Get global configurations of hash function type and symmetric hash enable
8763  * per flow type (pctype). Note that global configuration means it affects all
8764  * the ports on the same NIC.
8765  */
8766 static int
8767 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8768                                    struct rte_eth_hash_global_conf *g_cfg)
8769 {
8770         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8771         uint32_t reg;
8772         uint16_t i, j;
8773
8774         memset(g_cfg, 0, sizeof(*g_cfg));
8775         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8776         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8777                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8778         else
8779                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8780         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8781                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8782
8783         /*
8784          * As i40e supports less than 64 flow types, only first 64 bits need to
8785          * be checked.
8786          */
8787         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8788                 g_cfg->valid_bit_mask[i] = 0ULL;
8789                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8790         }
8791
8792         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8793
8794         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8795                 if (!adapter->pctypes_tbl[i])
8796                         continue;
8797                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8798                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8799                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8800                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8801                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8802                                         g_cfg->sym_hash_enable_mask[0] |=
8803                                                                 (1ULL << i);
8804                                 }
8805                         }
8806                 }
8807         }
8808
8809         return 0;
8810 }
8811
8812 static int
8813 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8814                               const struct rte_eth_hash_global_conf *g_cfg)
8815 {
8816         uint32_t i;
8817         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8818
8819         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8820                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8821                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8822                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8823                                                 g_cfg->hash_func);
8824                 return -EINVAL;
8825         }
8826
8827         /*
8828          * As i40e supports less than 64 flow types, only first 64 bits need to
8829          * be checked.
8830          */
8831         mask0 = g_cfg->valid_bit_mask[0];
8832         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8833                 if (i == 0) {
8834                         /* Check if any unsupported flow type configured */
8835                         if ((mask0 | i40e_mask) ^ i40e_mask)
8836                                 goto mask_err;
8837                 } else {
8838                         if (g_cfg->valid_bit_mask[i])
8839                                 goto mask_err;
8840                 }
8841         }
8842
8843         return 0;
8844
8845 mask_err:
8846         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8847
8848         return -EINVAL;
8849 }
8850
8851 /*
8852  * Set global configurations of hash function type and symmetric hash enable
8853  * per flow type (pctype). Note any modifying global configuration will affect
8854  * all the ports on the same NIC.
8855  */
8856 static int
8857 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8858                                    struct rte_eth_hash_global_conf *g_cfg)
8859 {
8860         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8861         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8862         int ret;
8863         uint16_t i, j;
8864         uint32_t reg;
8865         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8866
8867         if (pf->support_multi_driver) {
8868                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8869                 return -ENOTSUP;
8870         }
8871
8872         /* Check the input parameters */
8873         ret = i40e_hash_global_config_check(adapter, g_cfg);
8874         if (ret < 0)
8875                 return ret;
8876
8877         /*
8878          * As i40e supports less than 64 flow types, only first 64 bits need to
8879          * be configured.
8880          */
8881         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8882                 if (mask0 & (1UL << i)) {
8883                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8884                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8885
8886                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8887                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8888                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8889                                         i40e_write_global_rx_ctl(hw,
8890                                                           I40E_GLQF_HSYM(j),
8891                                                           reg);
8892                         }
8893                 }
8894         }
8895
8896         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8897         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8898                 /* Toeplitz */
8899                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8900                         PMD_DRV_LOG(DEBUG,
8901                                 "Hash function already set to Toeplitz");
8902                         goto out;
8903                 }
8904                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8905         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8906                 /* Simple XOR */
8907                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8908                         PMD_DRV_LOG(DEBUG,
8909                                 "Hash function already set to Simple XOR");
8910                         goto out;
8911                 }
8912                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8913         } else
8914                 /* Use the default, and keep it as it is */
8915                 goto out;
8916
8917         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8918
8919 out:
8920         I40E_WRITE_FLUSH(hw);
8921
8922         return 0;
8923 }
8924
8925 /**
8926  * Valid input sets for hash and flow director filters per PCTYPE
8927  */
8928 static uint64_t
8929 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8930                 enum rte_filter_type filter)
8931 {
8932         uint64_t valid;
8933
8934         static const uint64_t valid_hash_inset_table[] = {
8935                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8936                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8937                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8938                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8939                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8940                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8941                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8942                         I40E_INSET_FLEX_PAYLOAD,
8943                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8944                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8945                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8946                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8947                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8948                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8949                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8950                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8951                         I40E_INSET_FLEX_PAYLOAD,
8952                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8953                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8954                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8955                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8956                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8957                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8958                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8959                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8960                         I40E_INSET_FLEX_PAYLOAD,
8961                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8962                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8963                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8964                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8965                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8966                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8967                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8968                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8969                         I40E_INSET_FLEX_PAYLOAD,
8970                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8971                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8972                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8973                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8974                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8975                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8976                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8977                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8978                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8979                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8980                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8981                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8982                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8983                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8984                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8985                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8986                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8987                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8988                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8989                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8990                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8991                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8992                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8993                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8994                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8995                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8996                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8997                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8998                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8999                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9000                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9001                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9002                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9003                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9004                         I40E_INSET_FLEX_PAYLOAD,
9005                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9006                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9007                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9008                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9009                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9010                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9011                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9012                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9013                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9014                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9015                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9016                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9017                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9018                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9019                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9020                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9021                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9022                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9023                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9024                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9025                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9026                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9027                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9028                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9029                         I40E_INSET_FLEX_PAYLOAD,
9030                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9031                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9032                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9033                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9034                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9035                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9036                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9037                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9038                         I40E_INSET_FLEX_PAYLOAD,
9039                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9040                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9041                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9042                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9043                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9044                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9045                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9046                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9047                         I40E_INSET_FLEX_PAYLOAD,
9048                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9049                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9050                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9051                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9052                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9053                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9054                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9055                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9056                         I40E_INSET_FLEX_PAYLOAD,
9057                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9058                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9059                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9060                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9061                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9062                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9063                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9064                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9065                         I40E_INSET_FLEX_PAYLOAD,
9066                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9067                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9068                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9069                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9070                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9071                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9072                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9073                         I40E_INSET_FLEX_PAYLOAD,
9074                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9075                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9076                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9077                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9078                         I40E_INSET_FLEX_PAYLOAD,
9079         };
9080
9081         /**
9082          * Flow director supports only fields defined in
9083          * union rte_eth_fdir_flow.
9084          */
9085         static const uint64_t valid_fdir_inset_table[] = {
9086                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9087                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9088                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9089                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9090                 I40E_INSET_IPV4_TTL,
9091                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9092                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9093                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9094                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9095                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9096                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9097                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9098                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9099                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9100                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9101                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9102                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9103                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9104                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9105                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9106                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9107                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9108                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9109                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9110                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9111                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9112                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9113                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9114                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9115                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9116                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9117                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9118                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9119                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9120                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9121                 I40E_INSET_SCTP_VT,
9122                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9123                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9124                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9125                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9126                 I40E_INSET_IPV4_TTL,
9127                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9128                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9129                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9130                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9131                 I40E_INSET_IPV6_HOP_LIMIT,
9132                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9133                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9134                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9135                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9136                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9137                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9138                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9139                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9140                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9141                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9142                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9143                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9144                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9145                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9146                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9147                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9148                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9149                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9150                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9151                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9152                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9153                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9154                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9155                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9156                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9157                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9158                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9159                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9160                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9161                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9162                 I40E_INSET_SCTP_VT,
9163                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9164                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9165                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9166                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9167                 I40E_INSET_IPV6_HOP_LIMIT,
9168                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9169                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9170                 I40E_INSET_LAST_ETHER_TYPE,
9171         };
9172
9173         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9174                 return 0;
9175         if (filter == RTE_ETH_FILTER_HASH)
9176                 valid = valid_hash_inset_table[pctype];
9177         else
9178                 valid = valid_fdir_inset_table[pctype];
9179
9180         return valid;
9181 }
9182
9183 /**
9184  * Validate if the input set is allowed for a specific PCTYPE
9185  */
9186 int
9187 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9188                 enum rte_filter_type filter, uint64_t inset)
9189 {
9190         uint64_t valid;
9191
9192         valid = i40e_get_valid_input_set(pctype, filter);
9193         if (inset & (~valid))
9194                 return -EINVAL;
9195
9196         return 0;
9197 }
9198
9199 /* default input set fields combination per pctype */
9200 uint64_t
9201 i40e_get_default_input_set(uint16_t pctype)
9202 {
9203         static const uint64_t default_inset_table[] = {
9204                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9205                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9206                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9207                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9208                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9209                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9210                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9211                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9212                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9213                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9214                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9215                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9216                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9217                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9218                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9219                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9220                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9221                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9222                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9223                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9224                         I40E_INSET_SCTP_VT,
9225                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9226                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9227                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9228                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9229                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9230                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9231                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9232                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9233                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9234                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9235                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9236                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9237                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9238                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9239                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9240                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9241                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9242                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9243                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9244                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9245                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9246                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9247                         I40E_INSET_SCTP_VT,
9248                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9249                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9250                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9251                         I40E_INSET_LAST_ETHER_TYPE,
9252         };
9253
9254         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9255                 return 0;
9256
9257         return default_inset_table[pctype];
9258 }
9259
9260 /**
9261  * Parse the input set from index to logical bit masks
9262  */
9263 static int
9264 i40e_parse_input_set(uint64_t *inset,
9265                      enum i40e_filter_pctype pctype,
9266                      enum rte_eth_input_set_field *field,
9267                      uint16_t size)
9268 {
9269         uint16_t i, j;
9270         int ret = -EINVAL;
9271
9272         static const struct {
9273                 enum rte_eth_input_set_field field;
9274                 uint64_t inset;
9275         } inset_convert_table[] = {
9276                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9277                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9278                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9279                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9280                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9281                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9282                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9283                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9284                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9285                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9286                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9287                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9288                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9289                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9290                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9291                         I40E_INSET_IPV6_NEXT_HDR},
9292                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9293                         I40E_INSET_IPV6_HOP_LIMIT},
9294                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9295                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9296                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9297                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9298                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9299                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9300                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9301                         I40E_INSET_SCTP_VT},
9302                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9303                         I40E_INSET_TUNNEL_DMAC},
9304                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9305                         I40E_INSET_VLAN_TUNNEL},
9306                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9307                         I40E_INSET_TUNNEL_ID},
9308                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9309                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9310                         I40E_INSET_FLEX_PAYLOAD_W1},
9311                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9312                         I40E_INSET_FLEX_PAYLOAD_W2},
9313                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9314                         I40E_INSET_FLEX_PAYLOAD_W3},
9315                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9316                         I40E_INSET_FLEX_PAYLOAD_W4},
9317                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9318                         I40E_INSET_FLEX_PAYLOAD_W5},
9319                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9320                         I40E_INSET_FLEX_PAYLOAD_W6},
9321                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9322                         I40E_INSET_FLEX_PAYLOAD_W7},
9323                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9324                         I40E_INSET_FLEX_PAYLOAD_W8},
9325         };
9326
9327         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9328                 return ret;
9329
9330         /* Only one item allowed for default or all */
9331         if (size == 1) {
9332                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9333                         *inset = i40e_get_default_input_set(pctype);
9334                         return 0;
9335                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9336                         *inset = I40E_INSET_NONE;
9337                         return 0;
9338                 }
9339         }
9340
9341         for (i = 0, *inset = 0; i < size; i++) {
9342                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9343                         if (field[i] == inset_convert_table[j].field) {
9344                                 *inset |= inset_convert_table[j].inset;
9345                                 break;
9346                         }
9347                 }
9348
9349                 /* It contains unsupported input set, return immediately */
9350                 if (j == RTE_DIM(inset_convert_table))
9351                         return ret;
9352         }
9353
9354         return 0;
9355 }
9356
9357 /**
9358  * Translate the input set from bit masks to register aware bit masks
9359  * and vice versa
9360  */
9361 uint64_t
9362 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9363 {
9364         uint64_t val = 0;
9365         uint16_t i;
9366
9367         struct inset_map {
9368                 uint64_t inset;
9369                 uint64_t inset_reg;
9370         };
9371
9372         static const struct inset_map inset_map_common[] = {
9373                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9374                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9375                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9376                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9377                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9378                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9379                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9380                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9381                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9382                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9383                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9384                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9385                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9386                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9387                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9388                 {I40E_INSET_TUNNEL_DMAC,
9389                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9390                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9391                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9392                 {I40E_INSET_TUNNEL_SRC_PORT,
9393                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9394                 {I40E_INSET_TUNNEL_DST_PORT,
9395                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9396                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9397                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9398                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9399                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9400                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9401                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9402                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9403                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9404                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9405         };
9406
9407     /* some different registers map in x722*/
9408         static const struct inset_map inset_map_diff_x722[] = {
9409                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9410                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9411                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9412                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9413         };
9414
9415         static const struct inset_map inset_map_diff_not_x722[] = {
9416                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9417                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9418                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9419                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9420         };
9421
9422         if (input == 0)
9423                 return val;
9424
9425         /* Translate input set to register aware inset */
9426         if (type == I40E_MAC_X722) {
9427                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9428                         if (input & inset_map_diff_x722[i].inset)
9429                                 val |= inset_map_diff_x722[i].inset_reg;
9430                 }
9431         } else {
9432                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9433                         if (input & inset_map_diff_not_x722[i].inset)
9434                                 val |= inset_map_diff_not_x722[i].inset_reg;
9435                 }
9436         }
9437
9438         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9439                 if (input & inset_map_common[i].inset)
9440                         val |= inset_map_common[i].inset_reg;
9441         }
9442
9443         return val;
9444 }
9445
9446 int
9447 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9448 {
9449         uint8_t i, idx = 0;
9450         uint64_t inset_need_mask = inset;
9451
9452         static const struct {
9453                 uint64_t inset;
9454                 uint32_t mask;
9455         } inset_mask_map[] = {
9456                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9457                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9458                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9459                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9460                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9461                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9462                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9463                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9464         };
9465
9466         if (!inset || !mask || !nb_elem)
9467                 return 0;
9468
9469         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9470                 /* Clear the inset bit, if no MASK is required,
9471                  * for example proto + ttl
9472                  */
9473                 if ((inset & inset_mask_map[i].inset) ==
9474                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9475                         inset_need_mask &= ~inset_mask_map[i].inset;
9476                 if (!inset_need_mask)
9477                         return 0;
9478         }
9479         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9480                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9481                     inset_mask_map[i].inset) {
9482                         if (idx >= nb_elem) {
9483                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9484                                 return -EINVAL;
9485                         }
9486                         mask[idx] = inset_mask_map[i].mask;
9487                         idx++;
9488                 }
9489         }
9490
9491         return idx;
9492 }
9493
9494 void
9495 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9496 {
9497         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9498
9499         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9500         if (reg != val)
9501                 i40e_write_rx_ctl(hw, addr, val);
9502         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9503                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9504 }
9505
9506 void
9507 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9508 {
9509         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9510         struct rte_eth_dev *dev;
9511
9512         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9513         if (reg != val) {
9514                 i40e_write_rx_ctl(hw, addr, val);
9515                 PMD_DRV_LOG(WARNING,
9516                             "i40e device %s changed global register [0x%08x]."
9517                             " original: 0x%08x, new: 0x%08x",
9518                             dev->device->name, addr, reg,
9519                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9520         }
9521 }
9522
9523 static void
9524 i40e_filter_input_set_init(struct i40e_pf *pf)
9525 {
9526         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9527         enum i40e_filter_pctype pctype;
9528         uint64_t input_set, inset_reg;
9529         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9530         int num, i;
9531         uint16_t flow_type;
9532
9533         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9534              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9535                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9536
9537                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9538                         continue;
9539
9540                 input_set = i40e_get_default_input_set(pctype);
9541
9542                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9543                                                    I40E_INSET_MASK_NUM_REG);
9544                 if (num < 0)
9545                         return;
9546                 if (pf->support_multi_driver && num > 0) {
9547                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9548                         return;
9549                 }
9550                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9551                                         input_set);
9552
9553                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9554                                       (uint32_t)(inset_reg & UINT32_MAX));
9555                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9556                                      (uint32_t)((inset_reg >>
9557                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9558                 if (!pf->support_multi_driver) {
9559                         i40e_check_write_global_reg(hw,
9560                                             I40E_GLQF_HASH_INSET(0, pctype),
9561                                             (uint32_t)(inset_reg & UINT32_MAX));
9562                         i40e_check_write_global_reg(hw,
9563                                              I40E_GLQF_HASH_INSET(1, pctype),
9564                                              (uint32_t)((inset_reg >>
9565                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9566
9567                         for (i = 0; i < num; i++) {
9568                                 i40e_check_write_global_reg(hw,
9569                                                     I40E_GLQF_FD_MSK(i, pctype),
9570                                                     mask_reg[i]);
9571                                 i40e_check_write_global_reg(hw,
9572                                                   I40E_GLQF_HASH_MSK(i, pctype),
9573                                                   mask_reg[i]);
9574                         }
9575                         /*clear unused mask registers of the pctype */
9576                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9577                                 i40e_check_write_global_reg(hw,
9578                                                     I40E_GLQF_FD_MSK(i, pctype),
9579                                                     0);
9580                                 i40e_check_write_global_reg(hw,
9581                                                   I40E_GLQF_HASH_MSK(i, pctype),
9582                                                   0);
9583                         }
9584                 } else {
9585                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9586                 }
9587                 I40E_WRITE_FLUSH(hw);
9588
9589                 /* store the default input set */
9590                 if (!pf->support_multi_driver)
9591                         pf->hash_input_set[pctype] = input_set;
9592                 pf->fdir.input_set[pctype] = input_set;
9593         }
9594 }
9595
9596 int
9597 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9598                          struct rte_eth_input_set_conf *conf)
9599 {
9600         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9601         enum i40e_filter_pctype pctype;
9602         uint64_t input_set, inset_reg = 0;
9603         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9604         int ret, i, num;
9605
9606         if (!conf) {
9607                 PMD_DRV_LOG(ERR, "Invalid pointer");
9608                 return -EFAULT;
9609         }
9610         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9611             conf->op != RTE_ETH_INPUT_SET_ADD) {
9612                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9613                 return -EINVAL;
9614         }
9615
9616         if (pf->support_multi_driver) {
9617                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9618                 return -ENOTSUP;
9619         }
9620
9621         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9622         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9623                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9624                 return -EINVAL;
9625         }
9626
9627         if (hw->mac.type == I40E_MAC_X722) {
9628                 /* get translated pctype value in fd pctype register */
9629                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9630                         I40E_GLQF_FD_PCTYPES((int)pctype));
9631         }
9632
9633         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9634                                    conf->inset_size);
9635         if (ret) {
9636                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9637                 return -EINVAL;
9638         }
9639
9640         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9641                 /* get inset value in register */
9642                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9643                 inset_reg <<= I40E_32_BIT_WIDTH;
9644                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9645                 input_set |= pf->hash_input_set[pctype];
9646         }
9647         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9648                                            I40E_INSET_MASK_NUM_REG);
9649         if (num < 0)
9650                 return -EINVAL;
9651
9652         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9653
9654         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9655                                     (uint32_t)(inset_reg & UINT32_MAX));
9656         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9657                                     (uint32_t)((inset_reg >>
9658                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9659
9660         for (i = 0; i < num; i++)
9661                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9662                                             mask_reg[i]);
9663         /*clear unused mask registers of the pctype */
9664         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9665                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9666                                             0);
9667         I40E_WRITE_FLUSH(hw);
9668
9669         pf->hash_input_set[pctype] = input_set;
9670         return 0;
9671 }
9672
9673 int
9674 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9675                          struct rte_eth_input_set_conf *conf)
9676 {
9677         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9678         enum i40e_filter_pctype pctype;
9679         uint64_t input_set, inset_reg = 0;
9680         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9681         int ret, i, num;
9682
9683         if (!hw || !conf) {
9684                 PMD_DRV_LOG(ERR, "Invalid pointer");
9685                 return -EFAULT;
9686         }
9687         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9688             conf->op != RTE_ETH_INPUT_SET_ADD) {
9689                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9690                 return -EINVAL;
9691         }
9692
9693         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9694
9695         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9696                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9697                 return -EINVAL;
9698         }
9699
9700         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9701                                    conf->inset_size);
9702         if (ret) {
9703                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9704                 return -EINVAL;
9705         }
9706
9707         /* get inset value in register */
9708         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9709         inset_reg <<= I40E_32_BIT_WIDTH;
9710         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9711
9712         /* Can not change the inset reg for flex payload for fdir,
9713          * it is done by writing I40E_PRTQF_FD_FLXINSET
9714          * in i40e_set_flex_mask_on_pctype.
9715          */
9716         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9717                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9718         else
9719                 input_set |= pf->fdir.input_set[pctype];
9720         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9721                                            I40E_INSET_MASK_NUM_REG);
9722         if (num < 0)
9723                 return -EINVAL;
9724         if (pf->support_multi_driver && num > 0) {
9725                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9726                 return -ENOTSUP;
9727         }
9728
9729         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9730
9731         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9732                               (uint32_t)(inset_reg & UINT32_MAX));
9733         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9734                              (uint32_t)((inset_reg >>
9735                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9736
9737         if (!pf->support_multi_driver) {
9738                 for (i = 0; i < num; i++)
9739                         i40e_check_write_global_reg(hw,
9740                                                     I40E_GLQF_FD_MSK(i, pctype),
9741                                                     mask_reg[i]);
9742                 /*clear unused mask registers of the pctype */
9743                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9744                         i40e_check_write_global_reg(hw,
9745                                                     I40E_GLQF_FD_MSK(i, pctype),
9746                                                     0);
9747         } else {
9748                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9749         }
9750         I40E_WRITE_FLUSH(hw);
9751
9752         pf->fdir.input_set[pctype] = input_set;
9753         return 0;
9754 }
9755
9756 static int
9757 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9758 {
9759         int ret = 0;
9760
9761         if (!hw || !info) {
9762                 PMD_DRV_LOG(ERR, "Invalid pointer");
9763                 return -EFAULT;
9764         }
9765
9766         switch (info->info_type) {
9767         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9768                 i40e_get_symmetric_hash_enable_per_port(hw,
9769                                         &(info->info.enable));
9770                 break;
9771         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9772                 ret = i40e_get_hash_filter_global_config(hw,
9773                                 &(info->info.global_conf));
9774                 break;
9775         default:
9776                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9777                                                         info->info_type);
9778                 ret = -EINVAL;
9779                 break;
9780         }
9781
9782         return ret;
9783 }
9784
9785 static int
9786 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9787 {
9788         int ret = 0;
9789
9790         if (!hw || !info) {
9791                 PMD_DRV_LOG(ERR, "Invalid pointer");
9792                 return -EFAULT;
9793         }
9794
9795         switch (info->info_type) {
9796         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9797                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9798                 break;
9799         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9800                 ret = i40e_set_hash_filter_global_config(hw,
9801                                 &(info->info.global_conf));
9802                 break;
9803         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9804                 ret = i40e_hash_filter_inset_select(hw,
9805                                                &(info->info.input_set_conf));
9806                 break;
9807
9808         default:
9809                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9810                                                         info->info_type);
9811                 ret = -EINVAL;
9812                 break;
9813         }
9814
9815         return ret;
9816 }
9817
9818 /* Operations for hash function */
9819 static int
9820 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9821                       enum rte_filter_op filter_op,
9822                       void *arg)
9823 {
9824         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9825         int ret = 0;
9826
9827         switch (filter_op) {
9828         case RTE_ETH_FILTER_NOP:
9829                 break;
9830         case RTE_ETH_FILTER_GET:
9831                 ret = i40e_hash_filter_get(hw,
9832                         (struct rte_eth_hash_filter_info *)arg);
9833                 break;
9834         case RTE_ETH_FILTER_SET:
9835                 ret = i40e_hash_filter_set(hw,
9836                         (struct rte_eth_hash_filter_info *)arg);
9837                 break;
9838         default:
9839                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9840                                                                 filter_op);
9841                 ret = -ENOTSUP;
9842                 break;
9843         }
9844
9845         return ret;
9846 }
9847
9848 /* Convert ethertype filter structure */
9849 static int
9850 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9851                               struct i40e_ethertype_filter *filter)
9852 {
9853         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9854         filter->input.ether_type = input->ether_type;
9855         filter->flags = input->flags;
9856         filter->queue = input->queue;
9857
9858         return 0;
9859 }
9860
9861 /* Check if there exists the ehtertype filter */
9862 struct i40e_ethertype_filter *
9863 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9864                                 const struct i40e_ethertype_filter_input *input)
9865 {
9866         int ret;
9867
9868         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9869         if (ret < 0)
9870                 return NULL;
9871
9872         return ethertype_rule->hash_map[ret];
9873 }
9874
9875 /* Add ethertype filter in SW list */
9876 static int
9877 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9878                                 struct i40e_ethertype_filter *filter)
9879 {
9880         struct i40e_ethertype_rule *rule = &pf->ethertype;
9881         int ret;
9882
9883         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9884         if (ret < 0) {
9885                 PMD_DRV_LOG(ERR,
9886                             "Failed to insert ethertype filter"
9887                             " to hash table %d!",
9888                             ret);
9889                 return ret;
9890         }
9891         rule->hash_map[ret] = filter;
9892
9893         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9894
9895         return 0;
9896 }
9897
9898 /* Delete ethertype filter in SW list */
9899 int
9900 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9901                              struct i40e_ethertype_filter_input *input)
9902 {
9903         struct i40e_ethertype_rule *rule = &pf->ethertype;
9904         struct i40e_ethertype_filter *filter;
9905         int ret;
9906
9907         ret = rte_hash_del_key(rule->hash_table, input);
9908         if (ret < 0) {
9909                 PMD_DRV_LOG(ERR,
9910                             "Failed to delete ethertype filter"
9911                             " to hash table %d!",
9912                             ret);
9913                 return ret;
9914         }
9915         filter = rule->hash_map[ret];
9916         rule->hash_map[ret] = NULL;
9917
9918         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9919         rte_free(filter);
9920
9921         return 0;
9922 }
9923
9924 /*
9925  * Configure ethertype filter, which can director packet by filtering
9926  * with mac address and ether_type or only ether_type
9927  */
9928 int
9929 i40e_ethertype_filter_set(struct i40e_pf *pf,
9930                         struct rte_eth_ethertype_filter *filter,
9931                         bool add)
9932 {
9933         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9934         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9935         struct i40e_ethertype_filter *ethertype_filter, *node;
9936         struct i40e_ethertype_filter check_filter;
9937         struct i40e_control_filter_stats stats;
9938         uint16_t flags = 0;
9939         int ret;
9940
9941         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9942                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9943                 return -EINVAL;
9944         }
9945         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9946                 filter->ether_type == ETHER_TYPE_IPv6) {
9947                 PMD_DRV_LOG(ERR,
9948                         "unsupported ether_type(0x%04x) in control packet filter.",
9949                         filter->ether_type);
9950                 return -EINVAL;
9951         }
9952         if (filter->ether_type == ETHER_TYPE_VLAN)
9953                 PMD_DRV_LOG(WARNING,
9954                         "filter vlan ether_type in first tag is not supported.");
9955
9956         /* Check if there is the filter in SW list */
9957         memset(&check_filter, 0, sizeof(check_filter));
9958         i40e_ethertype_filter_convert(filter, &check_filter);
9959         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9960                                                &check_filter.input);
9961         if (add && node) {
9962                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9963                 return -EINVAL;
9964         }
9965
9966         if (!add && !node) {
9967                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9968                 return -EINVAL;
9969         }
9970
9971         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9972                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9973         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9974                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9975         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9976
9977         memset(&stats, 0, sizeof(stats));
9978         ret = i40e_aq_add_rem_control_packet_filter(hw,
9979                         filter->mac_addr.addr_bytes,
9980                         filter->ether_type, flags,
9981                         pf->main_vsi->seid,
9982                         filter->queue, add, &stats, NULL);
9983
9984         PMD_DRV_LOG(INFO,
9985                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9986                 ret, stats.mac_etype_used, stats.etype_used,
9987                 stats.mac_etype_free, stats.etype_free);
9988         if (ret < 0)
9989                 return -ENOSYS;
9990
9991         /* Add or delete a filter in SW list */
9992         if (add) {
9993                 ethertype_filter = rte_zmalloc("ethertype_filter",
9994                                        sizeof(*ethertype_filter), 0);
9995                 if (ethertype_filter == NULL) {
9996                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9997                         return -ENOMEM;
9998                 }
9999
10000                 rte_memcpy(ethertype_filter, &check_filter,
10001                            sizeof(check_filter));
10002                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10003                 if (ret < 0)
10004                         rte_free(ethertype_filter);
10005         } else {
10006                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10007         }
10008
10009         return ret;
10010 }
10011
10012 /*
10013  * Handle operations for ethertype filter.
10014  */
10015 static int
10016 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10017                                 enum rte_filter_op filter_op,
10018                                 void *arg)
10019 {
10020         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10021         int ret = 0;
10022
10023         if (filter_op == RTE_ETH_FILTER_NOP)
10024                 return ret;
10025
10026         if (arg == NULL) {
10027                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10028                             filter_op);
10029                 return -EINVAL;
10030         }
10031
10032         switch (filter_op) {
10033         case RTE_ETH_FILTER_ADD:
10034                 ret = i40e_ethertype_filter_set(pf,
10035                         (struct rte_eth_ethertype_filter *)arg,
10036                         TRUE);
10037                 break;
10038         case RTE_ETH_FILTER_DELETE:
10039                 ret = i40e_ethertype_filter_set(pf,
10040                         (struct rte_eth_ethertype_filter *)arg,
10041                         FALSE);
10042                 break;
10043         default:
10044                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10045                 ret = -ENOSYS;
10046                 break;
10047         }
10048         return ret;
10049 }
10050
10051 static int
10052 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10053                      enum rte_filter_type filter_type,
10054                      enum rte_filter_op filter_op,
10055                      void *arg)
10056 {
10057         int ret = 0;
10058
10059         if (dev == NULL)
10060                 return -EINVAL;
10061
10062         switch (filter_type) {
10063         case RTE_ETH_FILTER_NONE:
10064                 /* For global configuration */
10065                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10066                 break;
10067         case RTE_ETH_FILTER_HASH:
10068                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10069                 break;
10070         case RTE_ETH_FILTER_MACVLAN:
10071                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10072                 break;
10073         case RTE_ETH_FILTER_ETHERTYPE:
10074                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10075                 break;
10076         case RTE_ETH_FILTER_TUNNEL:
10077                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10078                 break;
10079         case RTE_ETH_FILTER_FDIR:
10080                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10081                 break;
10082         case RTE_ETH_FILTER_GENERIC:
10083                 if (filter_op != RTE_ETH_FILTER_GET)
10084                         return -EINVAL;
10085                 *(const void **)arg = &i40e_flow_ops;
10086                 break;
10087         default:
10088                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10089                                                         filter_type);
10090                 ret = -EINVAL;
10091                 break;
10092         }
10093
10094         return ret;
10095 }
10096
10097 /*
10098  * Check and enable Extended Tag.
10099  * Enabling Extended Tag is important for 40G performance.
10100  */
10101 static void
10102 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10103 {
10104         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10105         uint32_t buf = 0;
10106         int ret;
10107
10108         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10109                                       PCI_DEV_CAP_REG);
10110         if (ret < 0) {
10111                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10112                             PCI_DEV_CAP_REG);
10113                 return;
10114         }
10115         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10116                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10117                 return;
10118         }
10119
10120         buf = 0;
10121         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10122                                       PCI_DEV_CTRL_REG);
10123         if (ret < 0) {
10124                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10125                             PCI_DEV_CTRL_REG);
10126                 return;
10127         }
10128         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10129                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10130                 return;
10131         }
10132         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10133         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10134                                        PCI_DEV_CTRL_REG);
10135         if (ret < 0) {
10136                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10137                             PCI_DEV_CTRL_REG);
10138                 return;
10139         }
10140 }
10141
10142 /*
10143  * As some registers wouldn't be reset unless a global hardware reset,
10144  * hardware initialization is needed to put those registers into an
10145  * expected initial state.
10146  */
10147 static void
10148 i40e_hw_init(struct rte_eth_dev *dev)
10149 {
10150         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10151
10152         i40e_enable_extended_tag(dev);
10153
10154         /* clear the PF Queue Filter control register */
10155         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10156
10157         /* Disable symmetric hash per port */
10158         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10159 }
10160
10161 /*
10162  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10163  * however this function will return only one highest pctype index,
10164  * which is not quite correct. This is known problem of i40e driver
10165  * and needs to be fixed later.
10166  */
10167 enum i40e_filter_pctype
10168 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10169 {
10170         int i;
10171         uint64_t pctype_mask;
10172
10173         if (flow_type < I40E_FLOW_TYPE_MAX) {
10174                 pctype_mask = adapter->pctypes_tbl[flow_type];
10175                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10176                         if (pctype_mask & (1ULL << i))
10177                                 return (enum i40e_filter_pctype)i;
10178                 }
10179         }
10180         return I40E_FILTER_PCTYPE_INVALID;
10181 }
10182
10183 uint16_t
10184 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10185                         enum i40e_filter_pctype pctype)
10186 {
10187         uint16_t flowtype;
10188         uint64_t pctype_mask = 1ULL << pctype;
10189
10190         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10191              flowtype++) {
10192                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10193                         return flowtype;
10194         }
10195
10196         return RTE_ETH_FLOW_UNKNOWN;
10197 }
10198
10199 /*
10200  * On X710, performance number is far from the expectation on recent firmware
10201  * versions; on XL710, performance number is also far from the expectation on
10202  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10203  * mode is enabled and port MAC address is equal to the packet destination MAC
10204  * address. The fix for this issue may not be integrated in the following
10205  * firmware version. So the workaround in software driver is needed. It needs
10206  * to modify the initial values of 3 internal only registers for both X710 and
10207  * XL710. Note that the values for X710 or XL710 could be different, and the
10208  * workaround can be removed when it is fixed in firmware in the future.
10209  */
10210
10211 /* For both X710 and XL710 */
10212 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10213 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10214 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10215
10216 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10217 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10218
10219 /* For X722 */
10220 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10221 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10222
10223 /* For X710 */
10224 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10225 /* For XL710 */
10226 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10227 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10228
10229 /*
10230  * GL_SWR_PM_UP_THR:
10231  * The value is not impacted from the link speed, its value is set according
10232  * to the total number of ports for a better pipe-monitor configuration.
10233  */
10234 static bool
10235 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10236 {
10237 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10238                 .device_id = (dev),   \
10239                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10240
10241 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10242                 .device_id = (dev),   \
10243                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10244
10245         static const struct {
10246                 uint16_t device_id;
10247                 uint32_t val;
10248         } swr_pm_table[] = {
10249                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10250                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10251                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10252                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10253
10254                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10255                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10256                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10257                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10258                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10259                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10260                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10261         };
10262         uint32_t i;
10263
10264         if (value == NULL) {
10265                 PMD_DRV_LOG(ERR, "value is NULL");
10266                 return false;
10267         }
10268
10269         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10270                 if (hw->device_id == swr_pm_table[i].device_id) {
10271                         *value = swr_pm_table[i].val;
10272
10273                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10274                                     "value - 0x%08x",
10275                                     hw->device_id, *value);
10276                         return true;
10277                 }
10278         }
10279
10280         return false;
10281 }
10282
10283 static int
10284 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10285 {
10286         enum i40e_status_code status;
10287         struct i40e_aq_get_phy_abilities_resp phy_ab;
10288         int ret = -ENOTSUP;
10289         int retries = 0;
10290
10291         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10292                                               NULL);
10293
10294         while (status) {
10295                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10296                         status);
10297                 retries++;
10298                 rte_delay_us(100000);
10299                 if  (retries < 5)
10300                         status = i40e_aq_get_phy_capabilities(hw, false,
10301                                         true, &phy_ab, NULL);
10302                 else
10303                         return ret;
10304         }
10305         return 0;
10306 }
10307
10308 static void
10309 i40e_configure_registers(struct i40e_hw *hw)
10310 {
10311         static struct {
10312                 uint32_t addr;
10313                 uint64_t val;
10314         } reg_table[] = {
10315                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10316                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10317                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10318         };
10319         uint64_t reg;
10320         uint32_t i;
10321         int ret;
10322
10323         for (i = 0; i < RTE_DIM(reg_table); i++) {
10324                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10325                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10326                                 reg_table[i].val =
10327                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10328                         else /* For X710/XL710/XXV710 */
10329                                 if (hw->aq.fw_maj_ver < 6)
10330                                         reg_table[i].val =
10331                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10332                                 else
10333                                         reg_table[i].val =
10334                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10335                 }
10336
10337                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10338                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10339                                 reg_table[i].val =
10340                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10341                         else /* For X710/XL710/XXV710 */
10342                                 reg_table[i].val =
10343                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10344                 }
10345
10346                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10347                         uint32_t cfg_val;
10348
10349                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10350                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10351                                             "GL_SWR_PM_UP_THR value fixup",
10352                                             hw->device_id);
10353                                 continue;
10354                         }
10355
10356                         reg_table[i].val = cfg_val;
10357                 }
10358
10359                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10360                                                         &reg, NULL);
10361                 if (ret < 0) {
10362                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10363                                                         reg_table[i].addr);
10364                         break;
10365                 }
10366                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10367                                                 reg_table[i].addr, reg);
10368                 if (reg == reg_table[i].val)
10369                         continue;
10370
10371                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10372                                                 reg_table[i].val, NULL);
10373                 if (ret < 0) {
10374                         PMD_DRV_LOG(ERR,
10375                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10376                                 reg_table[i].val, reg_table[i].addr);
10377                         break;
10378                 }
10379                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10380                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10381         }
10382 }
10383
10384 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10385 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10386 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10387 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10388 static int
10389 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10390 {
10391         uint32_t reg;
10392         int ret;
10393
10394         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10395                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10396                 return -EINVAL;
10397         }
10398
10399         /* Configure for double VLAN RX stripping */
10400         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10401         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10402                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10403                 ret = i40e_aq_debug_write_register(hw,
10404                                                    I40E_VSI_TSR(vsi->vsi_id),
10405                                                    reg, NULL);
10406                 if (ret < 0) {
10407                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10408                                     vsi->vsi_id);
10409                         return I40E_ERR_CONFIG;
10410                 }
10411         }
10412
10413         /* Configure for double VLAN TX insertion */
10414         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10415         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10416                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10417                 ret = i40e_aq_debug_write_register(hw,
10418                                                    I40E_VSI_L2TAGSTXVALID(
10419                                                    vsi->vsi_id), reg, NULL);
10420                 if (ret < 0) {
10421                         PMD_DRV_LOG(ERR,
10422                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10423                                 vsi->vsi_id);
10424                         return I40E_ERR_CONFIG;
10425                 }
10426         }
10427
10428         return 0;
10429 }
10430
10431 /**
10432  * i40e_aq_add_mirror_rule
10433  * @hw: pointer to the hardware structure
10434  * @seid: VEB seid to add mirror rule to
10435  * @dst_id: destination vsi seid
10436  * @entries: Buffer which contains the entities to be mirrored
10437  * @count: number of entities contained in the buffer
10438  * @rule_id:the rule_id of the rule to be added
10439  *
10440  * Add a mirror rule for a given veb.
10441  *
10442  **/
10443 static enum i40e_status_code
10444 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10445                         uint16_t seid, uint16_t dst_id,
10446                         uint16_t rule_type, uint16_t *entries,
10447                         uint16_t count, uint16_t *rule_id)
10448 {
10449         struct i40e_aq_desc desc;
10450         struct i40e_aqc_add_delete_mirror_rule cmd;
10451         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10452                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10453                 &desc.params.raw;
10454         uint16_t buff_len;
10455         enum i40e_status_code status;
10456
10457         i40e_fill_default_direct_cmd_desc(&desc,
10458                                           i40e_aqc_opc_add_mirror_rule);
10459         memset(&cmd, 0, sizeof(cmd));
10460
10461         buff_len = sizeof(uint16_t) * count;
10462         desc.datalen = rte_cpu_to_le_16(buff_len);
10463         if (buff_len > 0)
10464                 desc.flags |= rte_cpu_to_le_16(
10465                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10466         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10467                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10468         cmd.num_entries = rte_cpu_to_le_16(count);
10469         cmd.seid = rte_cpu_to_le_16(seid);
10470         cmd.destination = rte_cpu_to_le_16(dst_id);
10471
10472         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10473         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10474         PMD_DRV_LOG(INFO,
10475                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10476                 hw->aq.asq_last_status, resp->rule_id,
10477                 resp->mirror_rules_used, resp->mirror_rules_free);
10478         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10479
10480         return status;
10481 }
10482
10483 /**
10484  * i40e_aq_del_mirror_rule
10485  * @hw: pointer to the hardware structure
10486  * @seid: VEB seid to add mirror rule to
10487  * @entries: Buffer which contains the entities to be mirrored
10488  * @count: number of entities contained in the buffer
10489  * @rule_id:the rule_id of the rule to be delete
10490  *
10491  * Delete a mirror rule for a given veb.
10492  *
10493  **/
10494 static enum i40e_status_code
10495 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10496                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10497                 uint16_t count, uint16_t rule_id)
10498 {
10499         struct i40e_aq_desc desc;
10500         struct i40e_aqc_add_delete_mirror_rule cmd;
10501         uint16_t buff_len = 0;
10502         enum i40e_status_code status;
10503         void *buff = NULL;
10504
10505         i40e_fill_default_direct_cmd_desc(&desc,
10506                                           i40e_aqc_opc_delete_mirror_rule);
10507         memset(&cmd, 0, sizeof(cmd));
10508         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10509                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10510                                                           I40E_AQ_FLAG_RD));
10511                 cmd.num_entries = count;
10512                 buff_len = sizeof(uint16_t) * count;
10513                 desc.datalen = rte_cpu_to_le_16(buff_len);
10514                 buff = (void *)entries;
10515         } else
10516                 /* rule id is filled in destination field for deleting mirror rule */
10517                 cmd.destination = rte_cpu_to_le_16(rule_id);
10518
10519         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10520                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10521         cmd.seid = rte_cpu_to_le_16(seid);
10522
10523         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10524         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10525
10526         return status;
10527 }
10528
10529 /**
10530  * i40e_mirror_rule_set
10531  * @dev: pointer to the hardware structure
10532  * @mirror_conf: mirror rule info
10533  * @sw_id: mirror rule's sw_id
10534  * @on: enable/disable
10535  *
10536  * set a mirror rule.
10537  *
10538  **/
10539 static int
10540 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10541                         struct rte_eth_mirror_conf *mirror_conf,
10542                         uint8_t sw_id, uint8_t on)
10543 {
10544         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10545         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10546         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10547         struct i40e_mirror_rule *parent = NULL;
10548         uint16_t seid, dst_seid, rule_id;
10549         uint16_t i, j = 0;
10550         int ret;
10551
10552         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10553
10554         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10555                 PMD_DRV_LOG(ERR,
10556                         "mirror rule can not be configured without veb or vfs.");
10557                 return -ENOSYS;
10558         }
10559         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10560                 PMD_DRV_LOG(ERR, "mirror table is full.");
10561                 return -ENOSPC;
10562         }
10563         if (mirror_conf->dst_pool > pf->vf_num) {
10564                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10565                                  mirror_conf->dst_pool);
10566                 return -EINVAL;
10567         }
10568
10569         seid = pf->main_vsi->veb->seid;
10570
10571         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10572                 if (sw_id <= it->index) {
10573                         mirr_rule = it;
10574                         break;
10575                 }
10576                 parent = it;
10577         }
10578         if (mirr_rule && sw_id == mirr_rule->index) {
10579                 if (on) {
10580                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10581                         return -EEXIST;
10582                 } else {
10583                         ret = i40e_aq_del_mirror_rule(hw, seid,
10584                                         mirr_rule->rule_type,
10585                                         mirr_rule->entries,
10586                                         mirr_rule->num_entries, mirr_rule->id);
10587                         if (ret < 0) {
10588                                 PMD_DRV_LOG(ERR,
10589                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10590                                         ret, hw->aq.asq_last_status);
10591                                 return -ENOSYS;
10592                         }
10593                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10594                         rte_free(mirr_rule);
10595                         pf->nb_mirror_rule--;
10596                         return 0;
10597                 }
10598         } else if (!on) {
10599                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10600                 return -ENOENT;
10601         }
10602
10603         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10604                                 sizeof(struct i40e_mirror_rule) , 0);
10605         if (!mirr_rule) {
10606                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10607                 return I40E_ERR_NO_MEMORY;
10608         }
10609         switch (mirror_conf->rule_type) {
10610         case ETH_MIRROR_VLAN:
10611                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10612                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10613                                 mirr_rule->entries[j] =
10614                                         mirror_conf->vlan.vlan_id[i];
10615                                 j++;
10616                         }
10617                 }
10618                 if (j == 0) {
10619                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10620                         rte_free(mirr_rule);
10621                         return -EINVAL;
10622                 }
10623                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10624                 break;
10625         case ETH_MIRROR_VIRTUAL_POOL_UP:
10626         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10627                 /* check if the specified pool bit is out of range */
10628                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10629                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10630                         rte_free(mirr_rule);
10631                         return -EINVAL;
10632                 }
10633                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10634                         if (mirror_conf->pool_mask & (1ULL << i)) {
10635                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10636                                 j++;
10637                         }
10638                 }
10639                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10640                         /* add pf vsi to entries */
10641                         mirr_rule->entries[j] = pf->main_vsi_seid;
10642                         j++;
10643                 }
10644                 if (j == 0) {
10645                         PMD_DRV_LOG(ERR, "pool is not specified.");
10646                         rte_free(mirr_rule);
10647                         return -EINVAL;
10648                 }
10649                 /* egress and ingress in aq commands means from switch but not port */
10650                 mirr_rule->rule_type =
10651                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10652                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10653                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10654                 break;
10655         case ETH_MIRROR_UPLINK_PORT:
10656                 /* egress and ingress in aq commands means from switch but not port*/
10657                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10658                 break;
10659         case ETH_MIRROR_DOWNLINK_PORT:
10660                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10661                 break;
10662         default:
10663                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10664                         mirror_conf->rule_type);
10665                 rte_free(mirr_rule);
10666                 return -EINVAL;
10667         }
10668
10669         /* If the dst_pool is equal to vf_num, consider it as PF */
10670         if (mirror_conf->dst_pool == pf->vf_num)
10671                 dst_seid = pf->main_vsi_seid;
10672         else
10673                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10674
10675         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10676                                       mirr_rule->rule_type, mirr_rule->entries,
10677                                       j, &rule_id);
10678         if (ret < 0) {
10679                 PMD_DRV_LOG(ERR,
10680                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10681                         ret, hw->aq.asq_last_status);
10682                 rte_free(mirr_rule);
10683                 return -ENOSYS;
10684         }
10685
10686         mirr_rule->index = sw_id;
10687         mirr_rule->num_entries = j;
10688         mirr_rule->id = rule_id;
10689         mirr_rule->dst_vsi_seid = dst_seid;
10690
10691         if (parent)
10692                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10693         else
10694                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10695
10696         pf->nb_mirror_rule++;
10697         return 0;
10698 }
10699
10700 /**
10701  * i40e_mirror_rule_reset
10702  * @dev: pointer to the device
10703  * @sw_id: mirror rule's sw_id
10704  *
10705  * reset a mirror rule.
10706  *
10707  **/
10708 static int
10709 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10710 {
10711         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10712         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10713         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10714         uint16_t seid;
10715         int ret;
10716
10717         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10718
10719         seid = pf->main_vsi->veb->seid;
10720
10721         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10722                 if (sw_id == it->index) {
10723                         mirr_rule = it;
10724                         break;
10725                 }
10726         }
10727         if (mirr_rule) {
10728                 ret = i40e_aq_del_mirror_rule(hw, seid,
10729                                 mirr_rule->rule_type,
10730                                 mirr_rule->entries,
10731                                 mirr_rule->num_entries, mirr_rule->id);
10732                 if (ret < 0) {
10733                         PMD_DRV_LOG(ERR,
10734                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10735                                 ret, hw->aq.asq_last_status);
10736                         return -ENOSYS;
10737                 }
10738                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10739                 rte_free(mirr_rule);
10740                 pf->nb_mirror_rule--;
10741         } else {
10742                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10743                 return -ENOENT;
10744         }
10745         return 0;
10746 }
10747
10748 static uint64_t
10749 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10750 {
10751         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10752         uint64_t systim_cycles;
10753
10754         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10755         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10756                         << 32;
10757
10758         return systim_cycles;
10759 }
10760
10761 static uint64_t
10762 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10763 {
10764         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10765         uint64_t rx_tstamp;
10766
10767         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10768         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10769                         << 32;
10770
10771         return rx_tstamp;
10772 }
10773
10774 static uint64_t
10775 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10776 {
10777         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10778         uint64_t tx_tstamp;
10779
10780         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10781         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10782                         << 32;
10783
10784         return tx_tstamp;
10785 }
10786
10787 static void
10788 i40e_start_timecounters(struct rte_eth_dev *dev)
10789 {
10790         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10791         struct i40e_adapter *adapter =
10792                         (struct i40e_adapter *)dev->data->dev_private;
10793         struct rte_eth_link link;
10794         uint32_t tsync_inc_l;
10795         uint32_t tsync_inc_h;
10796
10797         /* Get current link speed. */
10798         i40e_dev_link_update(dev, 1);
10799         rte_eth_linkstatus_get(dev, &link);
10800
10801         switch (link.link_speed) {
10802         case ETH_SPEED_NUM_40G:
10803                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10804                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10805                 break;
10806         case ETH_SPEED_NUM_10G:
10807                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10808                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10809                 break;
10810         case ETH_SPEED_NUM_1G:
10811                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10812                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10813                 break;
10814         default:
10815                 tsync_inc_l = 0x0;
10816                 tsync_inc_h = 0x0;
10817         }
10818
10819         /* Set the timesync increment value. */
10820         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10821         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10822
10823         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10824         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10825         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10826
10827         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10828         adapter->systime_tc.cc_shift = 0;
10829         adapter->systime_tc.nsec_mask = 0;
10830
10831         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10832         adapter->rx_tstamp_tc.cc_shift = 0;
10833         adapter->rx_tstamp_tc.nsec_mask = 0;
10834
10835         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10836         adapter->tx_tstamp_tc.cc_shift = 0;
10837         adapter->tx_tstamp_tc.nsec_mask = 0;
10838 }
10839
10840 static int
10841 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10842 {
10843         struct i40e_adapter *adapter =
10844                         (struct i40e_adapter *)dev->data->dev_private;
10845
10846         adapter->systime_tc.nsec += delta;
10847         adapter->rx_tstamp_tc.nsec += delta;
10848         adapter->tx_tstamp_tc.nsec += delta;
10849
10850         return 0;
10851 }
10852
10853 static int
10854 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10855 {
10856         uint64_t ns;
10857         struct i40e_adapter *adapter =
10858                         (struct i40e_adapter *)dev->data->dev_private;
10859
10860         ns = rte_timespec_to_ns(ts);
10861
10862         /* Set the timecounters to a new value. */
10863         adapter->systime_tc.nsec = ns;
10864         adapter->rx_tstamp_tc.nsec = ns;
10865         adapter->tx_tstamp_tc.nsec = ns;
10866
10867         return 0;
10868 }
10869
10870 static int
10871 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10872 {
10873         uint64_t ns, systime_cycles;
10874         struct i40e_adapter *adapter =
10875                         (struct i40e_adapter *)dev->data->dev_private;
10876
10877         systime_cycles = i40e_read_systime_cyclecounter(dev);
10878         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10879         *ts = rte_ns_to_timespec(ns);
10880
10881         return 0;
10882 }
10883
10884 static int
10885 i40e_timesync_enable(struct rte_eth_dev *dev)
10886 {
10887         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10888         uint32_t tsync_ctl_l;
10889         uint32_t tsync_ctl_h;
10890
10891         /* Stop the timesync system time. */
10892         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10893         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10894         /* Reset the timesync system time value. */
10895         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10896         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10897
10898         i40e_start_timecounters(dev);
10899
10900         /* Clear timesync registers. */
10901         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10902         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10903         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10904         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10905         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10906         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10907
10908         /* Enable timestamping of PTP packets. */
10909         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10910         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10911
10912         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10913         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10914         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10915
10916         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10917         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10918
10919         return 0;
10920 }
10921
10922 static int
10923 i40e_timesync_disable(struct rte_eth_dev *dev)
10924 {
10925         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10926         uint32_t tsync_ctl_l;
10927         uint32_t tsync_ctl_h;
10928
10929         /* Disable timestamping of transmitted PTP packets. */
10930         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10931         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10932
10933         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10934         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10935
10936         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10937         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10938
10939         /* Reset the timesync increment value. */
10940         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10941         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10942
10943         return 0;
10944 }
10945
10946 static int
10947 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10948                                 struct timespec *timestamp, uint32_t flags)
10949 {
10950         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10951         struct i40e_adapter *adapter =
10952                 (struct i40e_adapter *)dev->data->dev_private;
10953
10954         uint32_t sync_status;
10955         uint32_t index = flags & 0x03;
10956         uint64_t rx_tstamp_cycles;
10957         uint64_t ns;
10958
10959         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10960         if ((sync_status & (1 << index)) == 0)
10961                 return -EINVAL;
10962
10963         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10964         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10965         *timestamp = rte_ns_to_timespec(ns);
10966
10967         return 0;
10968 }
10969
10970 static int
10971 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10972                                 struct timespec *timestamp)
10973 {
10974         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10975         struct i40e_adapter *adapter =
10976                 (struct i40e_adapter *)dev->data->dev_private;
10977
10978         uint32_t sync_status;
10979         uint64_t tx_tstamp_cycles;
10980         uint64_t ns;
10981
10982         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10983         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10984                 return -EINVAL;
10985
10986         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10987         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10988         *timestamp = rte_ns_to_timespec(ns);
10989
10990         return 0;
10991 }
10992
10993 /*
10994  * i40e_parse_dcb_configure - parse dcb configure from user
10995  * @dev: the device being configured
10996  * @dcb_cfg: pointer of the result of parse
10997  * @*tc_map: bit map of enabled traffic classes
10998  *
10999  * Returns 0 on success, negative value on failure
11000  */
11001 static int
11002 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11003                          struct i40e_dcbx_config *dcb_cfg,
11004                          uint8_t *tc_map)
11005 {
11006         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11007         uint8_t i, tc_bw, bw_lf;
11008
11009         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11010
11011         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11012         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11013                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11014                 return -EINVAL;
11015         }
11016
11017         /* assume each tc has the same bw */
11018         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11019         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11020                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11021         /* to ensure the sum of tcbw is equal to 100 */
11022         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11023         for (i = 0; i < bw_lf; i++)
11024                 dcb_cfg->etscfg.tcbwtable[i]++;
11025
11026         /* assume each tc has the same Transmission Selection Algorithm */
11027         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11028                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11029
11030         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11031                 dcb_cfg->etscfg.prioritytable[i] =
11032                                 dcb_rx_conf->dcb_tc[i];
11033
11034         /* FW needs one App to configure HW */
11035         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11036         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11037         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11038         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11039
11040         if (dcb_rx_conf->nb_tcs == 0)
11041                 *tc_map = 1; /* tc0 only */
11042         else
11043                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11044
11045         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11046                 dcb_cfg->pfc.willing = 0;
11047                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11048                 dcb_cfg->pfc.pfcenable = *tc_map;
11049         }
11050         return 0;
11051 }
11052
11053
11054 static enum i40e_status_code
11055 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11056                               struct i40e_aqc_vsi_properties_data *info,
11057                               uint8_t enabled_tcmap)
11058 {
11059         enum i40e_status_code ret;
11060         int i, total_tc = 0;
11061         uint16_t qpnum_per_tc, bsf, qp_idx;
11062         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11063         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11064         uint16_t used_queues;
11065
11066         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11067         if (ret != I40E_SUCCESS)
11068                 return ret;
11069
11070         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11071                 if (enabled_tcmap & (1 << i))
11072                         total_tc++;
11073         }
11074         if (total_tc == 0)
11075                 total_tc = 1;
11076         vsi->enabled_tc = enabled_tcmap;
11077
11078         /* different VSI has different queues assigned */
11079         if (vsi->type == I40E_VSI_MAIN)
11080                 used_queues = dev_data->nb_rx_queues -
11081                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11082         else if (vsi->type == I40E_VSI_VMDQ2)
11083                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11084         else {
11085                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11086                 return I40E_ERR_NO_AVAILABLE_VSI;
11087         }
11088
11089         qpnum_per_tc = used_queues / total_tc;
11090         /* Number of queues per enabled TC */
11091         if (qpnum_per_tc == 0) {
11092                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11093                 return I40E_ERR_INVALID_QP_ID;
11094         }
11095         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11096                                 I40E_MAX_Q_PER_TC);
11097         bsf = rte_bsf32(qpnum_per_tc);
11098
11099         /**
11100          * Configure TC and queue mapping parameters, for enabled TC,
11101          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11102          * default queue will serve it.
11103          */
11104         qp_idx = 0;
11105         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11106                 if (vsi->enabled_tc & (1 << i)) {
11107                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11108                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11109                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11110                         qp_idx += qpnum_per_tc;
11111                 } else
11112                         info->tc_mapping[i] = 0;
11113         }
11114
11115         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11116         if (vsi->type == I40E_VSI_SRIOV) {
11117                 info->mapping_flags |=
11118                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11119                 for (i = 0; i < vsi->nb_qps; i++)
11120                         info->queue_mapping[i] =
11121                                 rte_cpu_to_le_16(vsi->base_queue + i);
11122         } else {
11123                 info->mapping_flags |=
11124                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11125                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11126         }
11127         info->valid_sections |=
11128                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11129
11130         return I40E_SUCCESS;
11131 }
11132
11133 /*
11134  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11135  * @veb: VEB to be configured
11136  * @tc_map: enabled TC bitmap
11137  *
11138  * Returns 0 on success, negative value on failure
11139  */
11140 static enum i40e_status_code
11141 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11142 {
11143         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11144         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11145         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11146         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11147         enum i40e_status_code ret = I40E_SUCCESS;
11148         int i;
11149         uint32_t bw_max;
11150
11151         /* Check if enabled_tc is same as existing or new TCs */
11152         if (veb->enabled_tc == tc_map)
11153                 return ret;
11154
11155         /* configure tc bandwidth */
11156         memset(&veb_bw, 0, sizeof(veb_bw));
11157         veb_bw.tc_valid_bits = tc_map;
11158         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11159         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11160                 if (tc_map & BIT_ULL(i))
11161                         veb_bw.tc_bw_share_credits[i] = 1;
11162         }
11163         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11164                                                    &veb_bw, NULL);
11165         if (ret) {
11166                 PMD_INIT_LOG(ERR,
11167                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11168                         hw->aq.asq_last_status);
11169                 return ret;
11170         }
11171
11172         memset(&ets_query, 0, sizeof(ets_query));
11173         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11174                                                    &ets_query, NULL);
11175         if (ret != I40E_SUCCESS) {
11176                 PMD_DRV_LOG(ERR,
11177                         "Failed to get switch_comp ETS configuration %u",
11178                         hw->aq.asq_last_status);
11179                 return ret;
11180         }
11181         memset(&bw_query, 0, sizeof(bw_query));
11182         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11183                                                   &bw_query, NULL);
11184         if (ret != I40E_SUCCESS) {
11185                 PMD_DRV_LOG(ERR,
11186                         "Failed to get switch_comp bandwidth configuration %u",
11187                         hw->aq.asq_last_status);
11188                 return ret;
11189         }
11190
11191         /* store and print out BW info */
11192         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11193         veb->bw_info.bw_max = ets_query.tc_bw_max;
11194         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11195         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11196         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11197                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11198                      I40E_16_BIT_WIDTH);
11199         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11200                 veb->bw_info.bw_ets_share_credits[i] =
11201                                 bw_query.tc_bw_share_credits[i];
11202                 veb->bw_info.bw_ets_credits[i] =
11203                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11204                 /* 4 bits per TC, 4th bit is reserved */
11205                 veb->bw_info.bw_ets_max[i] =
11206                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11207                                   RTE_LEN2MASK(3, uint8_t));
11208                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11209                             veb->bw_info.bw_ets_share_credits[i]);
11210                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11211                             veb->bw_info.bw_ets_credits[i]);
11212                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11213                             veb->bw_info.bw_ets_max[i]);
11214         }
11215
11216         veb->enabled_tc = tc_map;
11217
11218         return ret;
11219 }
11220
11221
11222 /*
11223  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11224  * @vsi: VSI to be configured
11225  * @tc_map: enabled TC bitmap
11226  *
11227  * Returns 0 on success, negative value on failure
11228  */
11229 static enum i40e_status_code
11230 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11231 {
11232         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11233         struct i40e_vsi_context ctxt;
11234         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11235         enum i40e_status_code ret = I40E_SUCCESS;
11236         int i;
11237
11238         /* Check if enabled_tc is same as existing or new TCs */
11239         if (vsi->enabled_tc == tc_map)
11240                 return ret;
11241
11242         /* configure tc bandwidth */
11243         memset(&bw_data, 0, sizeof(bw_data));
11244         bw_data.tc_valid_bits = tc_map;
11245         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11246         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11247                 if (tc_map & BIT_ULL(i))
11248                         bw_data.tc_bw_credits[i] = 1;
11249         }
11250         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11251         if (ret) {
11252                 PMD_INIT_LOG(ERR,
11253                         "AQ command Config VSI BW allocation per TC failed = %d",
11254                         hw->aq.asq_last_status);
11255                 goto out;
11256         }
11257         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11258                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11259
11260         /* Update Queue Pairs Mapping for currently enabled UPs */
11261         ctxt.seid = vsi->seid;
11262         ctxt.pf_num = hw->pf_id;
11263         ctxt.vf_num = 0;
11264         ctxt.uplink_seid = vsi->uplink_seid;
11265         ctxt.info = vsi->info;
11266         i40e_get_cap(hw);
11267         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11268         if (ret)
11269                 goto out;
11270
11271         /* Update the VSI after updating the VSI queue-mapping information */
11272         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11273         if (ret) {
11274                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11275                         hw->aq.asq_last_status);
11276                 goto out;
11277         }
11278         /* update the local VSI info with updated queue map */
11279         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11280                                         sizeof(vsi->info.tc_mapping));
11281         rte_memcpy(&vsi->info.queue_mapping,
11282                         &ctxt.info.queue_mapping,
11283                 sizeof(vsi->info.queue_mapping));
11284         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11285         vsi->info.valid_sections = 0;
11286
11287         /* query and update current VSI BW information */
11288         ret = i40e_vsi_get_bw_config(vsi);
11289         if (ret) {
11290                 PMD_INIT_LOG(ERR,
11291                          "Failed updating vsi bw info, err %s aq_err %s",
11292                          i40e_stat_str(hw, ret),
11293                          i40e_aq_str(hw, hw->aq.asq_last_status));
11294                 goto out;
11295         }
11296
11297         vsi->enabled_tc = tc_map;
11298
11299 out:
11300         return ret;
11301 }
11302
11303 /*
11304  * i40e_dcb_hw_configure - program the dcb setting to hw
11305  * @pf: pf the configuration is taken on
11306  * @new_cfg: new configuration
11307  * @tc_map: enabled TC bitmap
11308  *
11309  * Returns 0 on success, negative value on failure
11310  */
11311 static enum i40e_status_code
11312 i40e_dcb_hw_configure(struct i40e_pf *pf,
11313                       struct i40e_dcbx_config *new_cfg,
11314                       uint8_t tc_map)
11315 {
11316         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11317         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11318         struct i40e_vsi *main_vsi = pf->main_vsi;
11319         struct i40e_vsi_list *vsi_list;
11320         enum i40e_status_code ret;
11321         int i;
11322         uint32_t val;
11323
11324         /* Use the FW API if FW > v4.4*/
11325         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11326               (hw->aq.fw_maj_ver >= 5))) {
11327                 PMD_INIT_LOG(ERR,
11328                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11329                 return I40E_ERR_FIRMWARE_API_VERSION;
11330         }
11331
11332         /* Check if need reconfiguration */
11333         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11334                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11335                 return I40E_SUCCESS;
11336         }
11337
11338         /* Copy the new config to the current config */
11339         *old_cfg = *new_cfg;
11340         old_cfg->etsrec = old_cfg->etscfg;
11341         ret = i40e_set_dcb_config(hw);
11342         if (ret) {
11343                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11344                          i40e_stat_str(hw, ret),
11345                          i40e_aq_str(hw, hw->aq.asq_last_status));
11346                 return ret;
11347         }
11348         /* set receive Arbiter to RR mode and ETS scheme by default */
11349         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11350                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11351                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11352                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11353                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11354                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11355                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11356                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11357                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11358                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11359                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11360                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11361                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11362         }
11363         /* get local mib to check whether it is configured correctly */
11364         /* IEEE mode */
11365         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11366         /* Get Local DCB Config */
11367         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11368                                      &hw->local_dcbx_config);
11369
11370         /* if Veb is created, need to update TC of it at first */
11371         if (main_vsi->veb) {
11372                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11373                 if (ret)
11374                         PMD_INIT_LOG(WARNING,
11375                                  "Failed configuring TC for VEB seid=%d",
11376                                  main_vsi->veb->seid);
11377         }
11378         /* Update each VSI */
11379         i40e_vsi_config_tc(main_vsi, tc_map);
11380         if (main_vsi->veb) {
11381                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11382                         /* Beside main VSI and VMDQ VSIs, only enable default
11383                          * TC for other VSIs
11384                          */
11385                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11386                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11387                                                          tc_map);
11388                         else
11389                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11390                                                          I40E_DEFAULT_TCMAP);
11391                         if (ret)
11392                                 PMD_INIT_LOG(WARNING,
11393                                         "Failed configuring TC for VSI seid=%d",
11394                                         vsi_list->vsi->seid);
11395                         /* continue */
11396                 }
11397         }
11398         return I40E_SUCCESS;
11399 }
11400
11401 /*
11402  * i40e_dcb_init_configure - initial dcb config
11403  * @dev: device being configured
11404  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11405  *
11406  * Returns 0 on success, negative value on failure
11407  */
11408 int
11409 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11410 {
11411         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11412         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11413         int i, ret = 0;
11414
11415         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11416                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11417                 return -ENOTSUP;
11418         }
11419
11420         /* DCB initialization:
11421          * Update DCB configuration from the Firmware and configure
11422          * LLDP MIB change event.
11423          */
11424         if (sw_dcb == TRUE) {
11425                 /* When using NVM 6.01 or later, the RX data path does
11426                  * not hang if the FW LLDP is stopped.
11427                  */
11428                 if (((hw->nvm.version >> 12) & 0xf) >= 6 &&
11429                     ((hw->nvm.version >> 4) & 0xff) >= 1) {
11430                         ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11431                         if (ret != I40E_SUCCESS)
11432                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11433                 }
11434
11435                 ret = i40e_init_dcb(hw);
11436                 /* If lldp agent is stopped, the return value from
11437                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11438                  * adminq status. Otherwise, it should return success.
11439                  */
11440                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11441                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11442                         memset(&hw->local_dcbx_config, 0,
11443                                 sizeof(struct i40e_dcbx_config));
11444                         /* set dcb default configuration */
11445                         hw->local_dcbx_config.etscfg.willing = 0;
11446                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11447                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11448                         hw->local_dcbx_config.etscfg.tsatable[0] =
11449                                                 I40E_IEEE_TSA_ETS;
11450                         /* all UPs mapping to TC0 */
11451                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11452                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11453                         hw->local_dcbx_config.etsrec =
11454                                 hw->local_dcbx_config.etscfg;
11455                         hw->local_dcbx_config.pfc.willing = 0;
11456                         hw->local_dcbx_config.pfc.pfccap =
11457                                                 I40E_MAX_TRAFFIC_CLASS;
11458                         /* FW needs one App to configure HW */
11459                         hw->local_dcbx_config.numapps = 1;
11460                         hw->local_dcbx_config.app[0].selector =
11461                                                 I40E_APP_SEL_ETHTYPE;
11462                         hw->local_dcbx_config.app[0].priority = 3;
11463                         hw->local_dcbx_config.app[0].protocolid =
11464                                                 I40E_APP_PROTOID_FCOE;
11465                         ret = i40e_set_dcb_config(hw);
11466                         if (ret) {
11467                                 PMD_INIT_LOG(ERR,
11468                                         "default dcb config fails. err = %d, aq_err = %d.",
11469                                         ret, hw->aq.asq_last_status);
11470                                 return -ENOSYS;
11471                         }
11472                 } else {
11473                         PMD_INIT_LOG(ERR,
11474                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11475                                 ret, hw->aq.asq_last_status);
11476                         return -ENOTSUP;
11477                 }
11478         } else {
11479                 ret = i40e_aq_start_lldp(hw, NULL);
11480                 if (ret != I40E_SUCCESS)
11481                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11482
11483                 ret = i40e_init_dcb(hw);
11484                 if (!ret) {
11485                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11486                                 PMD_INIT_LOG(ERR,
11487                                         "HW doesn't support DCBX offload.");
11488                                 return -ENOTSUP;
11489                         }
11490                 } else {
11491                         PMD_INIT_LOG(ERR,
11492                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11493                                 ret, hw->aq.asq_last_status);
11494                         return -ENOTSUP;
11495                 }
11496         }
11497         return 0;
11498 }
11499
11500 /*
11501  * i40e_dcb_setup - setup dcb related config
11502  * @dev: device being configured
11503  *
11504  * Returns 0 on success, negative value on failure
11505  */
11506 static int
11507 i40e_dcb_setup(struct rte_eth_dev *dev)
11508 {
11509         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11510         struct i40e_dcbx_config dcb_cfg;
11511         uint8_t tc_map = 0;
11512         int ret = 0;
11513
11514         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11515                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11516                 return -ENOTSUP;
11517         }
11518
11519         if (pf->vf_num != 0)
11520                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11521
11522         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11523         if (ret) {
11524                 PMD_INIT_LOG(ERR, "invalid dcb config");
11525                 return -EINVAL;
11526         }
11527         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11528         if (ret) {
11529                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11530                 return -ENOSYS;
11531         }
11532
11533         return 0;
11534 }
11535
11536 static int
11537 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11538                       struct rte_eth_dcb_info *dcb_info)
11539 {
11540         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11541         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11542         struct i40e_vsi *vsi = pf->main_vsi;
11543         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11544         uint16_t bsf, tc_mapping;
11545         int i, j = 0;
11546
11547         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11548                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11549         else
11550                 dcb_info->nb_tcs = 1;
11551         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11552                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11553         for (i = 0; i < dcb_info->nb_tcs; i++)
11554                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11555
11556         /* get queue mapping if vmdq is disabled */
11557         if (!pf->nb_cfg_vmdq_vsi) {
11558                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11559                         if (!(vsi->enabled_tc & (1 << i)))
11560                                 continue;
11561                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11562                         dcb_info->tc_queue.tc_rxq[j][i].base =
11563                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11564                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11565                         dcb_info->tc_queue.tc_txq[j][i].base =
11566                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11567                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11568                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11569                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11570                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11571                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11572                 }
11573                 return 0;
11574         }
11575
11576         /* get queue mapping if vmdq is enabled */
11577         do {
11578                 vsi = pf->vmdq[j].vsi;
11579                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11580                         if (!(vsi->enabled_tc & (1 << i)))
11581                                 continue;
11582                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11583                         dcb_info->tc_queue.tc_rxq[j][i].base =
11584                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11585                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11586                         dcb_info->tc_queue.tc_txq[j][i].base =
11587                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11588                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11589                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11590                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11591                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11592                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11593                 }
11594                 j++;
11595         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11596         return 0;
11597 }
11598
11599 static int
11600 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11601 {
11602         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11603         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11604         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11605         uint16_t msix_intr;
11606
11607         msix_intr = intr_handle->intr_vec[queue_id];
11608         if (msix_intr == I40E_MISC_VEC_ID)
11609                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11610                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11611                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11612                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11613         else
11614                 I40E_WRITE_REG(hw,
11615                                I40E_PFINT_DYN_CTLN(msix_intr -
11616                                                    I40E_RX_VEC_START),
11617                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11618                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11619                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11620
11621         I40E_WRITE_FLUSH(hw);
11622         rte_intr_enable(&pci_dev->intr_handle);
11623
11624         return 0;
11625 }
11626
11627 static int
11628 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11629 {
11630         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11631         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11632         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11633         uint16_t msix_intr;
11634
11635         msix_intr = intr_handle->intr_vec[queue_id];
11636         if (msix_intr == I40E_MISC_VEC_ID)
11637                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11638                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11639         else
11640                 I40E_WRITE_REG(hw,
11641                                I40E_PFINT_DYN_CTLN(msix_intr -
11642                                                    I40E_RX_VEC_START),
11643                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11644         I40E_WRITE_FLUSH(hw);
11645
11646         return 0;
11647 }
11648
11649 /**
11650  * This function is used to check if the register is valid.
11651  * Below is the valid registers list for X722 only:
11652  * 0x2b800--0x2bb00
11653  * 0x38700--0x38a00
11654  * 0x3d800--0x3db00
11655  * 0x208e00--0x209000
11656  * 0x20be00--0x20c000
11657  * 0x263c00--0x264000
11658  * 0x265c00--0x266000
11659  */
11660 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11661 {
11662         if ((type != I40E_MAC_X722) &&
11663             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11664              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11665              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11666              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11667              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11668              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11669              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11670                 return 0;
11671         else
11672                 return 1;
11673 }
11674
11675 static int i40e_get_regs(struct rte_eth_dev *dev,
11676                          struct rte_dev_reg_info *regs)
11677 {
11678         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11679         uint32_t *ptr_data = regs->data;
11680         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11681         const struct i40e_reg_info *reg_info;
11682
11683         if (ptr_data == NULL) {
11684                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11685                 regs->width = sizeof(uint32_t);
11686                 return 0;
11687         }
11688
11689         /* The first few registers have to be read using AQ operations */
11690         reg_idx = 0;
11691         while (i40e_regs_adminq[reg_idx].name) {
11692                 reg_info = &i40e_regs_adminq[reg_idx++];
11693                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11694                         for (arr_idx2 = 0;
11695                                         arr_idx2 <= reg_info->count2;
11696                                         arr_idx2++) {
11697                                 reg_offset = arr_idx * reg_info->stride1 +
11698                                         arr_idx2 * reg_info->stride2;
11699                                 reg_offset += reg_info->base_addr;
11700                                 ptr_data[reg_offset >> 2] =
11701                                         i40e_read_rx_ctl(hw, reg_offset);
11702                         }
11703         }
11704
11705         /* The remaining registers can be read using primitives */
11706         reg_idx = 0;
11707         while (i40e_regs_others[reg_idx].name) {
11708                 reg_info = &i40e_regs_others[reg_idx++];
11709                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11710                         for (arr_idx2 = 0;
11711                                         arr_idx2 <= reg_info->count2;
11712                                         arr_idx2++) {
11713                                 reg_offset = arr_idx * reg_info->stride1 +
11714                                         arr_idx2 * reg_info->stride2;
11715                                 reg_offset += reg_info->base_addr;
11716                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11717                                         ptr_data[reg_offset >> 2] = 0;
11718                                 else
11719                                         ptr_data[reg_offset >> 2] =
11720                                                 I40E_READ_REG(hw, reg_offset);
11721                         }
11722         }
11723
11724         return 0;
11725 }
11726
11727 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11728 {
11729         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11730
11731         /* Convert word count to byte count */
11732         return hw->nvm.sr_size << 1;
11733 }
11734
11735 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11736                            struct rte_dev_eeprom_info *eeprom)
11737 {
11738         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11739         uint16_t *data = eeprom->data;
11740         uint16_t offset, length, cnt_words;
11741         int ret_code;
11742
11743         offset = eeprom->offset >> 1;
11744         length = eeprom->length >> 1;
11745         cnt_words = length;
11746
11747         if (offset > hw->nvm.sr_size ||
11748                 offset + length > hw->nvm.sr_size) {
11749                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11750                 return -EINVAL;
11751         }
11752
11753         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11754
11755         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11756         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11757                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11758                 return -EIO;
11759         }
11760
11761         return 0;
11762 }
11763
11764 static int i40e_get_module_info(struct rte_eth_dev *dev,
11765                                 struct rte_eth_dev_module_info *modinfo)
11766 {
11767         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11768         uint32_t sff8472_comp = 0;
11769         uint32_t sff8472_swap = 0;
11770         uint32_t sff8636_rev = 0;
11771         i40e_status status;
11772         uint32_t type = 0;
11773
11774         /* Check if firmware supports reading module EEPROM. */
11775         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11776                 PMD_DRV_LOG(ERR,
11777                             "Module EEPROM memory read not supported. "
11778                             "Please update the NVM image.\n");
11779                 return -EINVAL;
11780         }
11781
11782         status = i40e_update_link_info(hw);
11783         if (status)
11784                 return -EIO;
11785
11786         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11787                 PMD_DRV_LOG(ERR,
11788                             "Cannot read module EEPROM memory. "
11789                             "No module connected.\n");
11790                 return -EINVAL;
11791         }
11792
11793         type = hw->phy.link_info.module_type[0];
11794
11795         switch (type) {
11796         case I40E_MODULE_TYPE_SFP:
11797                 status = i40e_aq_get_phy_register(hw,
11798                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11799                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11800                                 I40E_MODULE_SFF_8472_COMP,
11801                                 &sff8472_comp, NULL);
11802                 if (status)
11803                         return -EIO;
11804
11805                 status = i40e_aq_get_phy_register(hw,
11806                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11807                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11808                                 I40E_MODULE_SFF_8472_SWAP,
11809                                 &sff8472_swap, NULL);
11810                 if (status)
11811                         return -EIO;
11812
11813                 /* Check if the module requires address swap to access
11814                  * the other EEPROM memory page.
11815                  */
11816                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11817                         PMD_DRV_LOG(WARNING,
11818                                     "Module address swap to access "
11819                                     "page 0xA2 is not supported.\n");
11820                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11821                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11822                 } else if (sff8472_comp == 0x00) {
11823                         /* Module is not SFF-8472 compliant */
11824                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11825                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11826                 } else {
11827                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11828                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11829                 }
11830                 break;
11831         case I40E_MODULE_TYPE_QSFP_PLUS:
11832                 /* Read from memory page 0. */
11833                 status = i40e_aq_get_phy_register(hw,
11834                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11835                                 0, 1,
11836                                 I40E_MODULE_REVISION_ADDR,
11837                                 &sff8636_rev, NULL);
11838                 if (status)
11839                         return -EIO;
11840                 /* Determine revision compliance byte */
11841                 if (sff8636_rev > 0x02) {
11842                         /* Module is SFF-8636 compliant */
11843                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11844                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11845                 } else {
11846                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11847                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11848                 }
11849                 break;
11850         case I40E_MODULE_TYPE_QSFP28:
11851                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11852                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11853                 break;
11854         default:
11855                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11856                 return -EINVAL;
11857         }
11858         return 0;
11859 }
11860
11861 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11862                                   struct rte_dev_eeprom_info *info)
11863 {
11864         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11865         bool is_sfp = false;
11866         i40e_status status;
11867         uint8_t *data = info->data;
11868         uint32_t value = 0;
11869         uint32_t i;
11870
11871         if (!info || !info->length || !data)
11872                 return -EINVAL;
11873
11874         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11875                 is_sfp = true;
11876
11877         for (i = 0; i < info->length; i++) {
11878                 u32 offset = i + info->offset;
11879                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11880
11881                 /* Check if we need to access the other memory page */
11882                 if (is_sfp) {
11883                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11884                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11885                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11886                         }
11887                 } else {
11888                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11889                                 /* Compute memory page number and offset. */
11890                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11891                                 addr++;
11892                         }
11893                 }
11894                 status = i40e_aq_get_phy_register(hw,
11895                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11896                                 addr, offset, 1, &value, NULL);
11897                 if (status)
11898                         return -EIO;
11899                 data[i] = (uint8_t)value;
11900         }
11901         return 0;
11902 }
11903
11904 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11905                                      struct ether_addr *mac_addr)
11906 {
11907         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11908         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11909         struct i40e_vsi *vsi = pf->main_vsi;
11910         struct i40e_mac_filter_info mac_filter;
11911         struct i40e_mac_filter *f;
11912         int ret;
11913
11914         if (!is_valid_assigned_ether_addr(mac_addr)) {
11915                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11916                 return -EINVAL;
11917         }
11918
11919         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11920                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11921                         break;
11922         }
11923
11924         if (f == NULL) {
11925                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11926                 return -EIO;
11927         }
11928
11929         mac_filter = f->mac_info;
11930         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11931         if (ret != I40E_SUCCESS) {
11932                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11933                 return -EIO;
11934         }
11935         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11936         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11937         if (ret != I40E_SUCCESS) {
11938                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11939                 return -EIO;
11940         }
11941         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11942
11943         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11944                                         mac_addr->addr_bytes, NULL);
11945         if (ret != I40E_SUCCESS) {
11946                 PMD_DRV_LOG(ERR, "Failed to change mac");
11947                 return -EIO;
11948         }
11949
11950         return 0;
11951 }
11952
11953 static int
11954 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11955 {
11956         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11957         struct rte_eth_dev_data *dev_data = pf->dev_data;
11958         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11959         int ret = 0;
11960
11961         /* check if mtu is within the allowed range */
11962         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11963                 return -EINVAL;
11964
11965         /* mtu setting is forbidden if port is start */
11966         if (dev_data->dev_started) {
11967                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11968                             dev_data->port_id);
11969                 return -EBUSY;
11970         }
11971
11972         if (frame_size > ETHER_MAX_LEN)
11973                 dev_data->dev_conf.rxmode.offloads |=
11974                         DEV_RX_OFFLOAD_JUMBO_FRAME;
11975         else
11976                 dev_data->dev_conf.rxmode.offloads &=
11977                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11978
11979         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11980
11981         return ret;
11982 }
11983
11984 /* Restore ethertype filter */
11985 static void
11986 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11987 {
11988         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11989         struct i40e_ethertype_filter_list
11990                 *ethertype_list = &pf->ethertype.ethertype_list;
11991         struct i40e_ethertype_filter *f;
11992         struct i40e_control_filter_stats stats;
11993         uint16_t flags;
11994
11995         TAILQ_FOREACH(f, ethertype_list, rules) {
11996                 flags = 0;
11997                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11998                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11999                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12000                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12001                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12002
12003                 memset(&stats, 0, sizeof(stats));
12004                 i40e_aq_add_rem_control_packet_filter(hw,
12005                                             f->input.mac_addr.addr_bytes,
12006                                             f->input.ether_type,
12007                                             flags, pf->main_vsi->seid,
12008                                             f->queue, 1, &stats, NULL);
12009         }
12010         PMD_DRV_LOG(INFO, "Ethertype filter:"
12011                     " mac_etype_used = %u, etype_used = %u,"
12012                     " mac_etype_free = %u, etype_free = %u",
12013                     stats.mac_etype_used, stats.etype_used,
12014                     stats.mac_etype_free, stats.etype_free);
12015 }
12016
12017 /* Restore tunnel filter */
12018 static void
12019 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12020 {
12021         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12022         struct i40e_vsi *vsi;
12023         struct i40e_pf_vf *vf;
12024         struct i40e_tunnel_filter_list
12025                 *tunnel_list = &pf->tunnel.tunnel_list;
12026         struct i40e_tunnel_filter *f;
12027         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12028         bool big_buffer = 0;
12029
12030         TAILQ_FOREACH(f, tunnel_list, rules) {
12031                 if (!f->is_to_vf)
12032                         vsi = pf->main_vsi;
12033                 else {
12034                         vf = &pf->vfs[f->vf_id];
12035                         vsi = vf->vsi;
12036                 }
12037                 memset(&cld_filter, 0, sizeof(cld_filter));
12038                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
12039                         (struct ether_addr *)&cld_filter.element.outer_mac);
12040                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
12041                         (struct ether_addr *)&cld_filter.element.inner_mac);
12042                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12043                 cld_filter.element.flags = f->input.flags;
12044                 cld_filter.element.tenant_id = f->input.tenant_id;
12045                 cld_filter.element.queue_number = f->queue;
12046                 rte_memcpy(cld_filter.general_fields,
12047                            f->input.general_fields,
12048                            sizeof(f->input.general_fields));
12049
12050                 if (((f->input.flags &
12051                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12052                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12053                     ((f->input.flags &
12054                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12055                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12056                     ((f->input.flags &
12057                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12058                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12059                         big_buffer = 1;
12060
12061                 if (big_buffer)
12062                         i40e_aq_add_cloud_filters_bb(hw,
12063                                         vsi->seid, &cld_filter, 1);
12064                 else
12065                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12066                                                   &cld_filter.element, 1);
12067         }
12068 }
12069
12070 /* Restore rss filter */
12071 static inline void
12072 i40e_rss_filter_restore(struct i40e_pf *pf)
12073 {
12074         struct i40e_rte_flow_rss_conf *conf =
12075                                         &pf->rss_info;
12076         if (conf->conf.queue_num)
12077                 i40e_config_rss_filter(pf, conf, TRUE);
12078 }
12079
12080 static void
12081 i40e_filter_restore(struct i40e_pf *pf)
12082 {
12083         i40e_ethertype_filter_restore(pf);
12084         i40e_tunnel_filter_restore(pf);
12085         i40e_fdir_filter_restore(pf);
12086         i40e_rss_filter_restore(pf);
12087 }
12088
12089 static bool
12090 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12091 {
12092         if (strcmp(dev->device->driver->name, drv->driver.name))
12093                 return false;
12094
12095         return true;
12096 }
12097
12098 bool
12099 is_i40e_supported(struct rte_eth_dev *dev)
12100 {
12101         return is_device_supported(dev, &rte_i40e_pmd);
12102 }
12103
12104 struct i40e_customized_pctype*
12105 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12106 {
12107         int i;
12108
12109         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12110                 if (pf->customized_pctype[i].index == index)
12111                         return &pf->customized_pctype[i];
12112         }
12113         return NULL;
12114 }
12115
12116 static int
12117 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12118                               uint32_t pkg_size, uint32_t proto_num,
12119                               struct rte_pmd_i40e_proto_info *proto,
12120                               enum rte_pmd_i40e_package_op op)
12121 {
12122         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12123         uint32_t pctype_num;
12124         struct rte_pmd_i40e_ptype_info *pctype;
12125         uint32_t buff_size;
12126         struct i40e_customized_pctype *new_pctype = NULL;
12127         uint8_t proto_id;
12128         uint8_t pctype_value;
12129         char name[64];
12130         uint32_t i, j, n;
12131         int ret;
12132
12133         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12134             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12135                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12136                 return -1;
12137         }
12138
12139         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12140                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12141                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12142         if (ret) {
12143                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12144                 return -1;
12145         }
12146         if (!pctype_num) {
12147                 PMD_DRV_LOG(INFO, "No new pctype added");
12148                 return -1;
12149         }
12150
12151         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12152         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12153         if (!pctype) {
12154                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12155                 return -1;
12156         }
12157         /* get information about new pctype list */
12158         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12159                                         (uint8_t *)pctype, buff_size,
12160                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12161         if (ret) {
12162                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12163                 rte_free(pctype);
12164                 return -1;
12165         }
12166
12167         /* Update customized pctype. */
12168         for (i = 0; i < pctype_num; i++) {
12169                 pctype_value = pctype[i].ptype_id;
12170                 memset(name, 0, sizeof(name));
12171                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12172                         proto_id = pctype[i].protocols[j];
12173                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12174                                 continue;
12175                         for (n = 0; n < proto_num; n++) {
12176                                 if (proto[n].proto_id != proto_id)
12177                                         continue;
12178                                 strcat(name, proto[n].name);
12179                                 strcat(name, "_");
12180                                 break;
12181                         }
12182                 }
12183                 name[strlen(name) - 1] = '\0';
12184                 if (!strcmp(name, "GTPC"))
12185                         new_pctype =
12186                                 i40e_find_customized_pctype(pf,
12187                                                       I40E_CUSTOMIZED_GTPC);
12188                 else if (!strcmp(name, "GTPU_IPV4"))
12189                         new_pctype =
12190                                 i40e_find_customized_pctype(pf,
12191                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12192                 else if (!strcmp(name, "GTPU_IPV6"))
12193                         new_pctype =
12194                                 i40e_find_customized_pctype(pf,
12195                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12196                 else if (!strcmp(name, "GTPU"))
12197                         new_pctype =
12198                                 i40e_find_customized_pctype(pf,
12199                                                       I40E_CUSTOMIZED_GTPU);
12200                 if (new_pctype) {
12201                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12202                                 new_pctype->pctype = pctype_value;
12203                                 new_pctype->valid = true;
12204                         } else {
12205                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12206                                 new_pctype->valid = false;
12207                         }
12208                 }
12209         }
12210
12211         rte_free(pctype);
12212         return 0;
12213 }
12214
12215 static int
12216 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12217                              uint32_t pkg_size, uint32_t proto_num,
12218                              struct rte_pmd_i40e_proto_info *proto,
12219                              enum rte_pmd_i40e_package_op op)
12220 {
12221         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12222         uint16_t port_id = dev->data->port_id;
12223         uint32_t ptype_num;
12224         struct rte_pmd_i40e_ptype_info *ptype;
12225         uint32_t buff_size;
12226         uint8_t proto_id;
12227         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12228         uint32_t i, j, n;
12229         bool in_tunnel;
12230         int ret;
12231
12232         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12233             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12234                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12235                 return -1;
12236         }
12237
12238         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12239                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12240                 return 0;
12241         }
12242
12243         /* get information about new ptype num */
12244         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12245                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12246                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12247         if (ret) {
12248                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12249                 return ret;
12250         }
12251         if (!ptype_num) {
12252                 PMD_DRV_LOG(INFO, "No new ptype added");
12253                 return -1;
12254         }
12255
12256         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12257         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12258         if (!ptype) {
12259                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12260                 return -1;
12261         }
12262
12263         /* get information about new ptype list */
12264         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12265                                         (uint8_t *)ptype, buff_size,
12266                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12267         if (ret) {
12268                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12269                 rte_free(ptype);
12270                 return ret;
12271         }
12272
12273         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12274         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12275         if (!ptype_mapping) {
12276                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12277                 rte_free(ptype);
12278                 return -1;
12279         }
12280
12281         /* Update ptype mapping table. */
12282         for (i = 0; i < ptype_num; i++) {
12283                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12284                 ptype_mapping[i].sw_ptype = 0;
12285                 in_tunnel = false;
12286                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12287                         proto_id = ptype[i].protocols[j];
12288                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12289                                 continue;
12290                         for (n = 0; n < proto_num; n++) {
12291                                 if (proto[n].proto_id != proto_id)
12292                                         continue;
12293                                 memset(name, 0, sizeof(name));
12294                                 strcpy(name, proto[n].name);
12295                                 if (!strncasecmp(name, "PPPOE", 5))
12296                                         ptype_mapping[i].sw_ptype |=
12297                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12298                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12299                                          !in_tunnel) {
12300                                         ptype_mapping[i].sw_ptype |=
12301                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12302                                         ptype_mapping[i].sw_ptype |=
12303                                                 RTE_PTYPE_L4_FRAG;
12304                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12305                                            in_tunnel) {
12306                                         ptype_mapping[i].sw_ptype |=
12307                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12308                                         ptype_mapping[i].sw_ptype |=
12309                                                 RTE_PTYPE_INNER_L4_FRAG;
12310                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12311                                         ptype_mapping[i].sw_ptype |=
12312                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12313                                         in_tunnel = true;
12314                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12315                                            !in_tunnel)
12316                                         ptype_mapping[i].sw_ptype |=
12317                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12318                                 else if (!strncasecmp(name, "IPV4", 4) &&
12319                                          in_tunnel)
12320                                         ptype_mapping[i].sw_ptype |=
12321                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12322                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12323                                          !in_tunnel) {
12324                                         ptype_mapping[i].sw_ptype |=
12325                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12326                                         ptype_mapping[i].sw_ptype |=
12327                                                 RTE_PTYPE_L4_FRAG;
12328                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12329                                            in_tunnel) {
12330                                         ptype_mapping[i].sw_ptype |=
12331                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12332                                         ptype_mapping[i].sw_ptype |=
12333                                                 RTE_PTYPE_INNER_L4_FRAG;
12334                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12335                                         ptype_mapping[i].sw_ptype |=
12336                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12337                                         in_tunnel = true;
12338                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12339                                            !in_tunnel)
12340                                         ptype_mapping[i].sw_ptype |=
12341                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12342                                 else if (!strncasecmp(name, "IPV6", 4) &&
12343                                          in_tunnel)
12344                                         ptype_mapping[i].sw_ptype |=
12345                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12346                                 else if (!strncasecmp(name, "UDP", 3) &&
12347                                          !in_tunnel)
12348                                         ptype_mapping[i].sw_ptype |=
12349                                                 RTE_PTYPE_L4_UDP;
12350                                 else if (!strncasecmp(name, "UDP", 3) &&
12351                                          in_tunnel)
12352                                         ptype_mapping[i].sw_ptype |=
12353                                                 RTE_PTYPE_INNER_L4_UDP;
12354                                 else if (!strncasecmp(name, "TCP", 3) &&
12355                                          !in_tunnel)
12356                                         ptype_mapping[i].sw_ptype |=
12357                                                 RTE_PTYPE_L4_TCP;
12358                                 else if (!strncasecmp(name, "TCP", 3) &&
12359                                          in_tunnel)
12360                                         ptype_mapping[i].sw_ptype |=
12361                                                 RTE_PTYPE_INNER_L4_TCP;
12362                                 else if (!strncasecmp(name, "SCTP", 4) &&
12363                                          !in_tunnel)
12364                                         ptype_mapping[i].sw_ptype |=
12365                                                 RTE_PTYPE_L4_SCTP;
12366                                 else if (!strncasecmp(name, "SCTP", 4) &&
12367                                          in_tunnel)
12368                                         ptype_mapping[i].sw_ptype |=
12369                                                 RTE_PTYPE_INNER_L4_SCTP;
12370                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12371                                           !strncasecmp(name, "ICMPV6", 6)) &&
12372                                          !in_tunnel)
12373                                         ptype_mapping[i].sw_ptype |=
12374                                                 RTE_PTYPE_L4_ICMP;
12375                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12376                                           !strncasecmp(name, "ICMPV6", 6)) &&
12377                                          in_tunnel)
12378                                         ptype_mapping[i].sw_ptype |=
12379                                                 RTE_PTYPE_INNER_L4_ICMP;
12380                                 else if (!strncasecmp(name, "GTPC", 4)) {
12381                                         ptype_mapping[i].sw_ptype |=
12382                                                 RTE_PTYPE_TUNNEL_GTPC;
12383                                         in_tunnel = true;
12384                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12385                                         ptype_mapping[i].sw_ptype |=
12386                                                 RTE_PTYPE_TUNNEL_GTPU;
12387                                         in_tunnel = true;
12388                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12389                                         ptype_mapping[i].sw_ptype |=
12390                                                 RTE_PTYPE_TUNNEL_GRENAT;
12391                                         in_tunnel = true;
12392                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12393                                            !strncasecmp(name, "L2TPV2", 6)) {
12394                                         ptype_mapping[i].sw_ptype |=
12395                                                 RTE_PTYPE_TUNNEL_L2TP;
12396                                         in_tunnel = true;
12397                                 }
12398
12399                                 break;
12400                         }
12401                 }
12402         }
12403
12404         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12405                                                 ptype_num, 0);
12406         if (ret)
12407                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12408
12409         rte_free(ptype_mapping);
12410         rte_free(ptype);
12411         return ret;
12412 }
12413
12414 void
12415 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12416                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12417 {
12418         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12419         uint32_t proto_num;
12420         struct rte_pmd_i40e_proto_info *proto;
12421         uint32_t buff_size;
12422         uint32_t i;
12423         int ret;
12424
12425         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12426             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12427                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12428                 return;
12429         }
12430
12431         /* get information about protocol number */
12432         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12433                                        (uint8_t *)&proto_num, sizeof(proto_num),
12434                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12435         if (ret) {
12436                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12437                 return;
12438         }
12439         if (!proto_num) {
12440                 PMD_DRV_LOG(INFO, "No new protocol added");
12441                 return;
12442         }
12443
12444         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12445         proto = rte_zmalloc("new_proto", buff_size, 0);
12446         if (!proto) {
12447                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12448                 return;
12449         }
12450
12451         /* get information about protocol list */
12452         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12453                                         (uint8_t *)proto, buff_size,
12454                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12455         if (ret) {
12456                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12457                 rte_free(proto);
12458                 return;
12459         }
12460
12461         /* Check if GTP is supported. */
12462         for (i = 0; i < proto_num; i++) {
12463                 if (!strncmp(proto[i].name, "GTP", 3)) {
12464                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12465                                 pf->gtp_support = true;
12466                         else
12467                                 pf->gtp_support = false;
12468                         break;
12469                 }
12470         }
12471
12472         /* Update customized pctype info */
12473         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12474                                             proto_num, proto, op);
12475         if (ret)
12476                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12477
12478         /* Update customized ptype info */
12479         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12480                                            proto_num, proto, op);
12481         if (ret)
12482                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12483
12484         rte_free(proto);
12485 }
12486
12487 /* Create a QinQ cloud filter
12488  *
12489  * The Fortville NIC has limited resources for tunnel filters,
12490  * so we can only reuse existing filters.
12491  *
12492  * In step 1 we define which Field Vector fields can be used for
12493  * filter types.
12494  * As we do not have the inner tag defined as a field,
12495  * we have to define it first, by reusing one of L1 entries.
12496  *
12497  * In step 2 we are replacing one of existing filter types with
12498  * a new one for QinQ.
12499  * As we reusing L1 and replacing L2, some of the default filter
12500  * types will disappear,which depends on L1 and L2 entries we reuse.
12501  *
12502  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12503  *
12504  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12505  *              later when we define the cloud filter.
12506  *      a.      Valid_flags.replace_cloud = 0
12507  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12508  *      c.      New_filter = 0x10
12509  *      d.      TR bit = 0xff (optional, not used here)
12510  *      e.      Buffer – 2 entries:
12511  *              i.      Byte 0 = 8 (outer vlan FV index).
12512  *                      Byte 1 = 0 (rsv)
12513  *                      Byte 2-3 = 0x0fff
12514  *              ii.     Byte 0 = 37 (inner vlan FV index).
12515  *                      Byte 1 =0 (rsv)
12516  *                      Byte 2-3 = 0x0fff
12517  *
12518  * Step 2:
12519  * 2.   Create cloud filter using two L1 filters entries: stag and
12520  *              new filter(outer vlan+ inner vlan)
12521  *      a.      Valid_flags.replace_cloud = 1
12522  *      b.      Old_filter = 1 (instead of outer IP)
12523  *      c.      New_filter = 0x10
12524  *      d.      Buffer – 2 entries:
12525  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12526  *                      Byte 1-3 = 0 (rsv)
12527  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12528  *                      Byte 9-11 = 0 (rsv)
12529  */
12530 static int
12531 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12532 {
12533         int ret = -ENOTSUP;
12534         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12535         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12536         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12537         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12538
12539         if (pf->support_multi_driver) {
12540                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12541                 return ret;
12542         }
12543
12544         /* Init */
12545         memset(&filter_replace, 0,
12546                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12547         memset(&filter_replace_buf, 0,
12548                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12549
12550         /* create L1 filter */
12551         filter_replace.old_filter_type =
12552                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12553         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12554         filter_replace.tr_bit = 0;
12555
12556         /* Prepare the buffer, 2 entries */
12557         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12558         filter_replace_buf.data[0] |=
12559                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12560         /* Field Vector 12b mask */
12561         filter_replace_buf.data[2] = 0xff;
12562         filter_replace_buf.data[3] = 0x0f;
12563         filter_replace_buf.data[4] =
12564                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12565         filter_replace_buf.data[4] |=
12566                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12567         /* Field Vector 12b mask */
12568         filter_replace_buf.data[6] = 0xff;
12569         filter_replace_buf.data[7] = 0x0f;
12570         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12571                         &filter_replace_buf);
12572         if (ret != I40E_SUCCESS)
12573                 return ret;
12574
12575         if (filter_replace.old_filter_type !=
12576             filter_replace.new_filter_type)
12577                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12578                             " original: 0x%x, new: 0x%x",
12579                             dev->device->name,
12580                             filter_replace.old_filter_type,
12581                             filter_replace.new_filter_type);
12582
12583         /* Apply the second L2 cloud filter */
12584         memset(&filter_replace, 0,
12585                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12586         memset(&filter_replace_buf, 0,
12587                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12588
12589         /* create L2 filter, input for L2 filter will be L1 filter  */
12590         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12591         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12592         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12593
12594         /* Prepare the buffer, 2 entries */
12595         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12596         filter_replace_buf.data[0] |=
12597                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12598         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12599         filter_replace_buf.data[4] |=
12600                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12601         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12602                         &filter_replace_buf);
12603         if (!ret && (filter_replace.old_filter_type !=
12604                      filter_replace.new_filter_type))
12605                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12606                             " original: 0x%x, new: 0x%x",
12607                             dev->device->name,
12608                             filter_replace.old_filter_type,
12609                             filter_replace.new_filter_type);
12610
12611         return ret;
12612 }
12613
12614 int
12615 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12616                    const struct rte_flow_action_rss *in)
12617 {
12618         if (in->key_len > RTE_DIM(out->key) ||
12619             in->queue_num > RTE_DIM(out->queue))
12620                 return -EINVAL;
12621         if (!in->key && in->key_len)
12622                 return -EINVAL;
12623         out->conf = (struct rte_flow_action_rss){
12624                 .func = in->func,
12625                 .level = in->level,
12626                 .types = in->types,
12627                 .key_len = in->key_len,
12628                 .queue_num = in->queue_num,
12629                 .queue = memcpy(out->queue, in->queue,
12630                                 sizeof(*in->queue) * in->queue_num),
12631         };
12632         if (in->key)
12633                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12634         return 0;
12635 }
12636
12637 int
12638 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12639                      const struct rte_flow_action_rss *with)
12640 {
12641         return (comp->func == with->func &&
12642                 comp->level == with->level &&
12643                 comp->types == with->types &&
12644                 comp->key_len == with->key_len &&
12645                 comp->queue_num == with->queue_num &&
12646                 !memcmp(comp->key, with->key, with->key_len) &&
12647                 !memcmp(comp->queue, with->queue,
12648                         sizeof(*with->queue) * with->queue_num));
12649 }
12650
12651 int
12652 i40e_config_rss_filter(struct i40e_pf *pf,
12653                 struct i40e_rte_flow_rss_conf *conf, bool add)
12654 {
12655         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12656         uint32_t i, lut = 0;
12657         uint16_t j, num;
12658         struct rte_eth_rss_conf rss_conf = {
12659                 .rss_key = conf->conf.key_len ?
12660                         (void *)(uintptr_t)conf->conf.key : NULL,
12661                 .rss_key_len = conf->conf.key_len,
12662                 .rss_hf = conf->conf.types,
12663         };
12664         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12665
12666         if (!add) {
12667                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12668                         i40e_pf_disable_rss(pf);
12669                         memset(rss_info, 0,
12670                                 sizeof(struct i40e_rte_flow_rss_conf));
12671                         return 0;
12672                 }
12673                 return -EINVAL;
12674         }
12675
12676         if (rss_info->conf.queue_num)
12677                 return -EINVAL;
12678
12679         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12680          * It's necessary to calculate the actual PF queues that are configured.
12681          */
12682         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12683                 num = i40e_pf_calc_configured_queues_num(pf);
12684         else
12685                 num = pf->dev_data->nb_rx_queues;
12686
12687         num = RTE_MIN(num, conf->conf.queue_num);
12688         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12689                         num);
12690
12691         if (num == 0) {
12692                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12693                 return -ENOTSUP;
12694         }
12695
12696         /* Fill in redirection table */
12697         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12698                 if (j == num)
12699                         j = 0;
12700                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12701                         hw->func_caps.rss_table_entry_width) - 1));
12702                 if ((i & 3) == 3)
12703                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12704         }
12705
12706         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12707                 i40e_pf_disable_rss(pf);
12708                 return 0;
12709         }
12710         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12711                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12712                 /* Random default keys */
12713                 static uint32_t rss_key_default[] = {0x6b793944,
12714                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12715                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12716                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12717
12718                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12719                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12720                                                         sizeof(uint32_t);
12721         }
12722
12723         i40e_hw_rss_hash_set(pf, &rss_conf);
12724
12725         if (i40e_rss_conf_init(rss_info, &conf->conf))
12726                 return -EINVAL;
12727
12728         return 0;
12729 }
12730
12731 RTE_INIT(i40e_init_log)
12732 {
12733         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12734         if (i40e_logtype_init >= 0)
12735                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12736         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12737         if (i40e_logtype_driver >= 0)
12738                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12739 }
12740
12741 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12742                               ETH_I40E_FLOATING_VEB_ARG "=1"
12743                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12744                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12745                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12746                               ETH_I40E_USE_LATEST_VEC "=0|1");