drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64
  65 /* Maximun number of MAC addresses */
  66 #define I40E_NUM_MACADDR_MAX       64
  67 #define I40E_CLEAR_PXE_WAIT_MS     200
  68
  69 /* Maximun number of capability elements */
  70 #define I40E_MAX_CAP_ELE_NUM       128
  71
  72 /* Wait count and inteval */
  73 #define I40E_CHK_Q_ENA_COUNT       1000
  74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  75
  76 /* Maximun number of VSI */
  77 #define I40E_MAX_NUM_VSIS          (384UL)
  78
  79 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  80
  81 /* Flow control default timer */
  82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  83
  84 /* Flow control default high water */
  85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  86
  87 /* Flow control default low water */
  88 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Receive Average Packet Size in Byte*/
 100 #define I40E_PACKET_AVERAGE_SIZE 128
 101
 102 /* Mask of PF interrupt causes */
 103 #define I40E_PFINT_ICR0_ENA_MASK ( \
 104                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 105                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 106                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 107                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 108                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 110                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 114
 115 #define I40E_FLOW_TYPES ( \
 116         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 127
 128 /* Additional timesync values. */
 129 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 130 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 131 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 132 #define I40E_PRTTSYN_TSYNENA     0x80000000
 133 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 134 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 135
 136 #define I40E_MAX_PERCENT            100
 137 #define I40E_DEFAULT_DCB_APP_NUM    1
 138 #define I40E_DEFAULT_DCB_APP_PRIO   3
 139
 140 #define I40E_PRTQF_FD_INSET(_i, _j)  (0x00250000 + ((_i) * 64 + (_j) * 32))
 141 #define I40E_GLQF_FD_MSK(_i, _j)     (0x00267200 + ((_i) * 4 + (_j) * 8))
 142 #define I40E_GLQF_FD_MSK_FIELD       0x0000FFFF
 143 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))
 144 #define I40E_GLQF_HASH_MSK(_i, _j)   (0x00267A00 + ((_i) * 4 + (_j) * 8))
 145 #define I40E_GLQF_HASH_MSK_FIELD      0x0000FFFF
 146
 147 #define I40E_INSET_NONE            0x00000000000000000ULL
 148
 149 /* bit0 ~ bit 7 */
 150 #define I40E_INSET_DMAC            0x0000000000000001ULL
 151 #define I40E_INSET_SMAC            0x0000000000000002ULL
 152 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 153 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 154 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 155
 156 /* bit 8 ~ bit 15 */
 157 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 158 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 159 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 160 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 161 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 162 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 163 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 164
 165 /* bit 16 ~ bit 31 */
 166 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 167 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 168 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 169 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 170 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 171 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 172 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 173 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 174
 175 /* bit 32 ~ bit 47, tunnel fields */
 176 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 177 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 178 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 179 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 180 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 181 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 182
 183 /* bit 48 ~ bit 55 */
 184 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 185
 186 /* bit 56 ~ bit 63, Flex Payload */
 187 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 191 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 192 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 193 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 194 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 195 #define I40E_INSET_FLEX_PAYLOAD \
 196         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 197         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W3 | \
 198         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 199         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 200
 201 /**
 202  * Below are values for writing un-exposed registers suggested
 203  * by silicon experts
 204  */
 205 /* Destination MAC address */
 206 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 207 /* Source MAC address */
 208 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 209 /* VLAN tag in the outer L2 header */
 210 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000000800000ULL
 211 /* VLAN tag in the inner L2 header */
 212 #define I40E_REG_INSET_L2_INNER_VLAN             0x0000000001000000ULL
 213 /* Source IPv4 address */
 214 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 215 /* Destination IPv4 address */
 216 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 217 /* IPv4 Type of Service (TOS) */
 218 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 219 /* IPv4 Protocol */
 220 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 221 /* Source IPv6 address */
 222 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 223 /* Destination IPv6 address */
 224 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 225 /* IPv6 Traffic Class (TC) */
 226 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 227 /* IPv6 Next Header */
 228 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 229 /* Source L4 port */
 230 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 231 /* Destination L4 port */
 232 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 233 /* SCTP verification tag */
 234 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 235 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 236 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 237 /* Source port of tunneling UDP */
 238 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 239 /* Destination port of tunneling UDP */
 240 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 241 /* UDP Tunneling ID, NVGRE/GRE key */
 242 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 243 /* Last ether type */
 244 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 245 /* Tunneling outer destination IPv4 address */
 246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 247 /* Tunneling outer destination IPv6 address */
 248 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 249 /* 1st word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 251 /* 2nd word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 253 /* 3rd word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 255 /* 4th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 257 /* 5th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 259 /* 6th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 261 /* 7th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 263 /* 8th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 265
 266 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 267
 268 #define I40E_TRANSLATE_INSET 0
 269 #define I40E_TRANSLATE_REG   1
 270
 271 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 272 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 273 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 274 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 275
 276 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 277 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 278 static int i40e_dev_configure(struct rte_eth_dev *dev);
 279 static int i40e_dev_start(struct rte_eth_dev *dev);
 280 static void i40e_dev_stop(struct rte_eth_dev *dev);
 281 static void i40e_dev_close(struct rte_eth_dev *dev);
 282 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 283 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 284 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 285 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 286 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 287 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 288 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 289                                struct rte_eth_stats *stats);
 290 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 291                                struct rte_eth_xstats *xstats, unsigned n);
 292 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 293 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 294                                             uint16_t queue_id,
 295                                             uint8_t stat_idx,
 296                                             uint8_t is_rx);
 297 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 298                               struct rte_eth_dev_info *dev_info);
 299 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 300                                 uint16_t vlan_id,
 301                                 int on);
 302 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 303 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 304 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 305                                       uint16_t queue,
 306                                       int on);
 307 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 308 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 309 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 310 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 311                               struct rte_eth_fc_conf *fc_conf);
 312 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 313                               struct rte_eth_fc_conf *fc_conf);
 314 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 315                                        struct rte_eth_pfc_conf *pfc_conf);
 316 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 317                           struct ether_addr *mac_addr,
 318                           uint32_t index,
 319                           uint32_t pool);
 320 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 321 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 322                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 323                                     uint16_t reta_size);
 324 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 325                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 326                                    uint16_t reta_size);
 327
 328 static int i40e_get_cap(struct i40e_hw *hw);
 329 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 330 static int i40e_pf_setup(struct i40e_pf *pf);
 331 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 332 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 333 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 334 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 335 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 336                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 337 static void i40e_stat_update_48(struct i40e_hw *hw,
 338                                uint32_t hireg,
 339                                uint32_t loreg,
 340                                bool offset_loaded,
 341                                uint64_t *offset,
 342                                uint64_t *stat);
 343 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 344 static void i40e_dev_interrupt_handler(
 345                 __rte_unused struct rte_intr_handle *handle, void *param);
 346 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 347                                 uint32_t base, uint32_t num);
 348 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 349 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 350                         uint32_t base);
 351 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 352                         uint16_t num);
 353 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 354 static int i40e_veb_release(struct i40e_veb *veb);
 355 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 356                                                 struct i40e_vsi *vsi);
 357 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 358 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 359 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 360                                              struct i40e_macvlan_filter *mv_f,
 361                                              int num,
 362                                              struct ether_addr *addr);
 363 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 364                                              struct i40e_macvlan_filter *mv_f,
 365                                              int num,
 366                                              uint16_t vlan);
 367 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 368 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 369                                     struct rte_eth_rss_conf *rss_conf);
 370 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 371                                       struct rte_eth_rss_conf *rss_conf);
 372 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 373                                 struct rte_eth_udp_tunnel *udp_tunnel);
 374 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 375                                 struct rte_eth_udp_tunnel *udp_tunnel);
 376 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 377                         struct rte_eth_ethertype_filter *filter,
 378                         bool add);
 379 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 380                                 enum rte_filter_op filter_op,
 381                                 void *arg);
 382 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 383                                 enum rte_filter_type filter_type,
 384                                 enum rte_filter_op filter_op,
 385                                 void *arg);
 386 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 387                                   struct rte_eth_dcb_info *dcb_info);
 388 static void i40e_configure_registers(struct i40e_hw *hw);
 389 static void i40e_hw_init(struct i40e_hw *hw);
 390 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 391 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 392                         struct rte_eth_mirror_conf *mirror_conf,
 393                         uint8_t sw_id, uint8_t on);
 394 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 395
 396 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 397 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 398 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 399                                            struct timespec *timestamp,
 400                                            uint32_t flags);
 401 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 402                                            struct timespec *timestamp);
 403 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 404
 405 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 406
 407 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 408                                    struct timespec *timestamp);
 409 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 410                                     const struct timespec *timestamp);
 411
 412 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 413                                          uint16_t queue_id);
 414 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 415                                           uint16_t queue_id);
 416
 417
 418 static const struct rte_pci_id pci_id_i40e_map[] = {
 419 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 420 #include "rte_pci_dev_ids.h"
 421 { .vendor_id = 0, /* sentinel */ },
 422 };
 423
 424 static const struct eth_dev_ops i40e_eth_dev_ops = {
 425         .dev_configure                = i40e_dev_configure,
 426         .dev_start                    = i40e_dev_start,
 427         .dev_stop                     = i40e_dev_stop,
 428         .dev_close                    = i40e_dev_close,
 429         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 430         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 431         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 432         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 433         .dev_set_link_up              = i40e_dev_set_link_up,
 434         .dev_set_link_down            = i40e_dev_set_link_down,
 435         .link_update                  = i40e_dev_link_update,
 436         .stats_get                    = i40e_dev_stats_get,
 437         .xstats_get                   = i40e_dev_xstats_get,
 438         .stats_reset                  = i40e_dev_stats_reset,
 439         .xstats_reset                 = i40e_dev_stats_reset,
 440         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 441         .dev_infos_get                = i40e_dev_info_get,
 442         .vlan_filter_set              = i40e_vlan_filter_set,
 443         .vlan_tpid_set                = i40e_vlan_tpid_set,
 444         .vlan_offload_set             = i40e_vlan_offload_set,
 445         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 446         .vlan_pvid_set                = i40e_vlan_pvid_set,
 447         .rx_queue_start               = i40e_dev_rx_queue_start,
 448         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 449         .tx_queue_start               = i40e_dev_tx_queue_start,
 450         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 451         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 452         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 453         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 454         .rx_queue_release             = i40e_dev_rx_queue_release,
 455         .rx_queue_count               = i40e_dev_rx_queue_count,
 456         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 457         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 458         .tx_queue_release             = i40e_dev_tx_queue_release,
 459         .dev_led_on                   = i40e_dev_led_on,
 460         .dev_led_off                  = i40e_dev_led_off,
 461         .flow_ctrl_get                = i40e_flow_ctrl_get,
 462         .flow_ctrl_set                = i40e_flow_ctrl_set,
 463         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 464         .mac_addr_add                 = i40e_macaddr_add,
 465         .mac_addr_remove              = i40e_macaddr_remove,
 466         .reta_update                  = i40e_dev_rss_reta_update,
 467         .reta_query                   = i40e_dev_rss_reta_query,
 468         .rss_hash_update              = i40e_dev_rss_hash_update,
 469         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 470         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 471         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 472         .filter_ctrl                  = i40e_dev_filter_ctrl,
 473         .rxq_info_get                 = i40e_rxq_info_get,
 474         .txq_info_get                 = i40e_txq_info_get,
 475         .mirror_rule_set              = i40e_mirror_rule_set,
 476         .mirror_rule_reset            = i40e_mirror_rule_reset,
 477         .timesync_enable              = i40e_timesync_enable,
 478         .timesync_disable             = i40e_timesync_disable,
 479         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 480         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 481         .get_dcb_info                 = i40e_dev_get_dcb_info,
 482         .timesync_adjust_time         = i40e_timesync_adjust_time,
 483         .timesync_read_time           = i40e_timesync_read_time,
 484         .timesync_write_time          = i40e_timesync_write_time,
 485 };
 486
 487 /* store statistics names and its offset in stats structure */
 488 struct rte_i40e_xstats_name_off {
 489         char name[RTE_ETH_XSTATS_NAME_SIZE];
 490         unsigned offset;
 491 };
 492
 493 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 494         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 495         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 496         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 497         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 498         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 499                 rx_unknown_protocol)},
 500         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 501         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 502         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 503         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 504 };
 505
 506 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 507                 sizeof(rte_i40e_stats_strings[0]))
 508
 509 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 510         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 511                 tx_dropped_link_down)},
 512         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 513         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 514                 illegal_bytes)},
 515         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 516         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 517                 mac_local_faults)},
 518         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 519                 mac_remote_faults)},
 520         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 521                 rx_length_errors)},
 522         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 523         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 524         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 525         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 526         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 527         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 528                 rx_size_127)},
 529         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 530                 rx_size_255)},
 531         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 532                 rx_size_511)},
 533         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 534                 rx_size_1023)},
 535         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 536                 rx_size_1522)},
 537         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 538                 rx_size_big)},
 539         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 540                 rx_undersize)},
 541         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 542                 rx_oversize)},
 543         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 544                 mac_short_packet_dropped)},
 545         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 546                 rx_fragments)},
 547         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 548         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 549         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 550                 tx_size_127)},
 551         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 552                 tx_size_255)},
 553         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 554                 tx_size_511)},
 555         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 556                 tx_size_1023)},
 557         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 558                 tx_size_1522)},
 559         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 560                 tx_size_big)},
 561         {"rx_flow_director_atr_match_packets",
 562                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 563         {"rx_flow_director_sb_match_packets",
 564                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 565         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 566                 tx_lpi_status)},
 567         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 568                 rx_lpi_status)},
 569         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 570                 tx_lpi_count)},
 571         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 572                 rx_lpi_count)},
 573 };
 574
 575 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 576                 sizeof(rte_i40e_hw_port_strings[0]))
 577
 578 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 579         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 580                 priority_xon_rx)},
 581         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 582                 priority_xoff_rx)},
 583 };
 584
 585 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 586                 sizeof(rte_i40e_rxq_prio_strings[0]))
 587
 588 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 589         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 590                 priority_xon_tx)},
 591         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 592                 priority_xoff_tx)},
 593         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 594                 priority_xon_2_xoff)},
 595 };
 596
 597 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 598                 sizeof(rte_i40e_txq_prio_strings[0]))
 599
 600 static struct eth_driver rte_i40e_pmd = {
 601         .pci_drv = {
 602                 .name = "rte_i40e_pmd",
 603                 .id_table = pci_id_i40e_map,
 604                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 605                         RTE_PCI_DRV_DETACHABLE,
 606         },
 607         .eth_dev_init = eth_i40e_dev_init,
 608         .eth_dev_uninit = eth_i40e_dev_uninit,
 609         .dev_private_size = sizeof(struct i40e_adapter),
 610 };
 611
 612 static inline int
 613 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 614                                      struct rte_eth_link *link)
 615 {
 616         struct rte_eth_link *dst = link;
 617         struct rte_eth_link *src = &(dev->data->dev_link);
 618
 619         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 620                                         *(uint64_t *)src) == 0)
 621                 return -1;
 622
 623         return 0;
 624 }
 625
 626 static inline int
 627 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 628                                       struct rte_eth_link *link)
 629 {
 630         struct rte_eth_link *dst = &(dev->data->dev_link);
 631         struct rte_eth_link *src = link;
 632
 633         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 634                                         *(uint64_t *)src) == 0)
 635                 return -1;
 636
 637         return 0;
 638 }
 639
 640 /*
 641  * Driver initialization routine.
 642  * Invoked once at EAL init time.
 643  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 644  */
 645 static int
 646 rte_i40e_pmd_init(const char *name __rte_unused,
 647                   const char *params __rte_unused)
 648 {
 649         PMD_INIT_FUNC_TRACE();
 650         rte_eth_driver_register(&rte_i40e_pmd);
 651
 652         return 0;
 653 }
 654
 655 static struct rte_driver rte_i40e_driver = {
 656         .type = PMD_PDEV,
 657         .init = rte_i40e_pmd_init,
 658 };
 659
 660 PMD_REGISTER_DRIVER(rte_i40e_driver);
 661
 662 /*
 663  * Initialize registers for flexible payload, which should be set by NVM.
 664  * This should be removed from code once it is fixed in NVM.
 665  */
 666 #ifndef I40E_GLQF_ORT
 667 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 668 #endif
 669 #ifndef I40E_GLQF_PIT
 670 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 671 #endif
 672
 673 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 674 {
 675         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 676         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 677         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 678         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 679         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 680         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 681         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 682         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 683         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 684         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 685
 686         /* GLQF_PIT Registers */
 687         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 688         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 689 }
 690
 691 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 692
 693 /*
 694  * Add a ethertype filter to drop all flow control frames transmitted
 695  * from VSIs.
 696 */
 697 static void
 698 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 699 {
 700         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 701         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 702                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 703                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 704         int ret;
 705
 706         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 707                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 708                                 pf->main_vsi_seid, 0,
 709                                 TRUE, NULL, NULL);
 710         if (ret)
 711                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 712                                   " frames from VSIs.");
 713 }
 714
 715 static int
 716 eth_i40e_dev_init(struct rte_eth_dev *dev)
 717 {
 718         struct rte_pci_device *pci_dev;
 719         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 720         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 721         struct i40e_vsi *vsi;
 722         int ret;
 723         uint32_t len;
 724         uint8_t aq_fail = 0;
 725
 726         PMD_INIT_FUNC_TRACE();
 727
 728         dev->dev_ops = &i40e_eth_dev_ops;
 729         dev->rx_pkt_burst = i40e_recv_pkts;
 730         dev->tx_pkt_burst = i40e_xmit_pkts;
 731
 732         /* for secondary processes, we don't initialise any further as primary
 733          * has already done this work. Only check we don't need a different
 734          * RX function */
 735         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 736                 i40e_set_rx_function(dev);
 737                 i40e_set_tx_function(dev);
 738                 return 0;
 739         }
 740         pci_dev = dev->pci_dev;
 741
 742         rte_eth_copy_pci_info(dev, pci_dev);
 743
 744         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 745         pf->adapter->eth_dev = dev;
 746         pf->dev_data = dev->data;
 747
 748         hw->back = I40E_PF_TO_ADAPTER(pf);
 749         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 750         if (!hw->hw_addr) {
 751                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 752                              "as address is NULL");
 753                 return -ENODEV;
 754         }
 755
 756         hw->vendor_id = pci_dev->id.vendor_id;
 757         hw->device_id = pci_dev->id.device_id;
 758         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 759         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 760         hw->bus.device = pci_dev->addr.devid;
 761         hw->bus.func = pci_dev->addr.function;
 762         hw->adapter_stopped = 0;
 763
 764         /* Make sure all is clean before doing PF reset */
 765         i40e_clear_hw(hw);
 766
 767         /* Initialize the hardware */
 768         i40e_hw_init(hw);
 769
 770         /* Reset here to make sure all is clean for each PF */
 771         ret = i40e_pf_reset(hw);
 772         if (ret) {
 773                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 774                 return ret;
 775         }
 776
 777         /* Initialize the shared code (base driver) */
 778         ret = i40e_init_shared_code(hw);
 779         if (ret) {
 780                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 781                 return ret;
 782         }
 783
 784         /*
 785          * To work around the NVM issue,initialize registers
 786          * for flexible payload by software.
 787          * It should be removed once issues are fixed in NVM.
 788          */
 789         i40e_flex_payload_reg_init(hw);
 790
 791         /* Initialize the parameters for adminq */
 792         i40e_init_adminq_parameter(hw);
 793         ret = i40e_init_adminq(hw);
 794         if (ret != I40E_SUCCESS) {
 795                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 796                 return -EIO;
 797         }
 798         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 799                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 800                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 801                      ((hw->nvm.version >> 12) & 0xf),
 802                      ((hw->nvm.version >> 4) & 0xff),
 803                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 804
 805         /* Clear PXE mode */
 806         i40e_clear_pxe_mode(hw);
 807
 808         /*
 809          * On X710, performance number is far from the expectation on recent
 810          * firmware versions. The fix for this issue may not be integrated in
 811          * the following firmware version. So the workaround in software driver
 812          * is needed. It needs to modify the initial values of 3 internal only
 813          * registers. Note that the workaround can be removed when it is fixed
 814          * in firmware in the future.
 815          */
 816         i40e_configure_registers(hw);
 817
 818         /* Get hw capabilities */
 819         ret = i40e_get_cap(hw);
 820         if (ret != I40E_SUCCESS) {
 821                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 822                 goto err_get_capabilities;
 823         }
 824
 825         /* Initialize parameters for PF */
 826         ret = i40e_pf_parameter_init(dev);
 827         if (ret != 0) {
 828                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 829                 goto err_parameter_init;
 830         }
 831
 832         /* Initialize the queue management */
 833         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 834         if (ret < 0) {
 835                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 836                 goto err_qp_pool_init;
 837         }
 838         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 839                                 hw->func_caps.num_msix_vectors - 1);
 840         if (ret < 0) {
 841                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 842                 goto err_msix_pool_init;
 843         }
 844
 845         /* Initialize lan hmc */
 846         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 847                                 hw->func_caps.num_rx_qp, 0, 0);
 848         if (ret != I40E_SUCCESS) {
 849                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 850                 goto err_init_lan_hmc;
 851         }
 852
 853         /* Configure lan hmc */
 854         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 855         if (ret != I40E_SUCCESS) {
 856                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 857                 goto err_configure_lan_hmc;
 858         }
 859
 860         /* Get and check the mac address */
 861         i40e_get_mac_addr(hw, hw->mac.addr);
 862         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 863                 PMD_INIT_LOG(ERR, "mac address is not valid");
 864                 ret = -EIO;
 865                 goto err_get_mac_addr;
 866         }
 867         /* Copy the permanent MAC address */
 868         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 869                         (struct ether_addr *) hw->mac.perm_addr);
 870
 871         /* Disable flow control */
 872         hw->fc.requested_mode = I40E_FC_NONE;
 873         i40e_set_fc(hw, &aq_fail, TRUE);
 874
 875         /* PF setup, which includes VSI setup */
 876         ret = i40e_pf_setup(pf);
 877         if (ret) {
 878                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 879                 goto err_setup_pf_switch;
 880         }
 881
 882         vsi = pf->main_vsi;
 883
 884         /* Disable double vlan by default */
 885         i40e_vsi_config_double_vlan(vsi, FALSE);
 886
 887         if (!vsi->max_macaddrs)
 888                 len = ETHER_ADDR_LEN;
 889         else
 890                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 891
 892         /* Should be after VSI initialized */
 893         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 894         if (!dev->data->mac_addrs) {
 895                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 896                                         "for storing mac address");
 897                 goto err_mac_alloc;
 898         }
 899         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 900                                         &dev->data->mac_addrs[0]);
 901
 902         /* initialize pf host driver to setup SRIOV resource if applicable */
 903         i40e_pf_host_init(dev);
 904
 905         /* register callback func to eal lib */
 906         rte_intr_callback_register(&(pci_dev->intr_handle),
 907                 i40e_dev_interrupt_handler, (void *)dev);
 908
 909         /* configure and enable device interrupt */
 910         i40e_pf_config_irq0(hw, TRUE);
 911         i40e_pf_enable_irq0(hw);
 912
 913         /* enable uio intr after callback register */
 914         rte_intr_enable(&(pci_dev->intr_handle));
 915         /*
 916          * Add an ethertype filter to drop all flow control frames transmitted
 917          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 918          * frames to wire.
 919          */
 920         i40e_add_tx_flow_control_drop_filter(pf);
 921
 922         /* initialize mirror rule list */
 923         TAILQ_INIT(&pf->mirror_list);
 924
 925         /* Init dcb to sw mode by default */
 926         ret = i40e_dcb_init_configure(dev, TRUE);
 927         if (ret != I40E_SUCCESS) {
 928                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 929                 pf->flags &= ~I40E_FLAG_DCB;
 930         }
 931
 932         return 0;
 933
 934 err_mac_alloc:
 935         i40e_vsi_release(pf->main_vsi);
 936 err_setup_pf_switch:
 937 err_get_mac_addr:
 938 err_configure_lan_hmc:
 939         (void)i40e_shutdown_lan_hmc(hw);
 940 err_init_lan_hmc:
 941         i40e_res_pool_destroy(&pf->msix_pool);
 942 err_msix_pool_init:
 943         i40e_res_pool_destroy(&pf->qp_pool);
 944 err_qp_pool_init:
 945 err_parameter_init:
 946 err_get_capabilities:
 947         (void)i40e_shutdown_adminq(hw);
 948
 949         return ret;
 950 }
 951
 952 static int
 953 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 954 {
 955         struct rte_pci_device *pci_dev;
 956         struct i40e_hw *hw;
 957         struct i40e_filter_control_settings settings;
 958         int ret;
 959         uint8_t aq_fail = 0;
 960
 961         PMD_INIT_FUNC_TRACE();
 962
 963         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 964                 return 0;
 965
 966         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 967         pci_dev = dev->pci_dev;
 968
 969         if (hw->adapter_stopped == 0)
 970                 i40e_dev_close(dev);
 971
 972         dev->dev_ops = NULL;
 973         dev->rx_pkt_burst = NULL;
 974         dev->tx_pkt_burst = NULL;
 975
 976         /* Disable LLDP */
 977         ret = i40e_aq_stop_lldp(hw, true, NULL);
 978         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 979                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 980
 981         /* Clear PXE mode */
 982         i40e_clear_pxe_mode(hw);
 983
 984         /* Unconfigure filter control */
 985         memset(&settings, 0, sizeof(settings));
 986         ret = i40e_set_filter_control(hw, &settings);
 987         if (ret)
 988                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 989                                         ret);
 990
 991         /* Disable flow control */
 992         hw->fc.requested_mode = I40E_FC_NONE;
 993         i40e_set_fc(hw, &aq_fail, TRUE);
 994
 995         /* uninitialize pf host driver */
 996         i40e_pf_host_uninit(dev);
 997
 998         rte_free(dev->data->mac_addrs);
 999         dev->data->mac_addrs = NULL;
1000
1001         /* disable uio intr before callback unregister */
1002         rte_intr_disable(&(pci_dev->intr_handle));
1003
1004         /* register callback func to eal lib */
1005         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1006                 i40e_dev_interrupt_handler, (void *)dev);
1007
1008         return 0;
1009 }
1010
1011 static int
1012 i40e_dev_configure(struct rte_eth_dev *dev)
1013 {
1014         struct i40e_adapter *ad =
1015                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1016         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1017         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1018         int i, ret;
1019
1020         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1021          * bulk allocation or vector Rx preconditions we will reset it.
1022          */
1023         ad->rx_bulk_alloc_allowed = true;
1024         ad->rx_vec_allowed = true;
1025         ad->tx_simple_allowed = true;
1026         ad->tx_vec_allowed = true;
1027
1028         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1029                 ret = i40e_fdir_setup(pf);
1030                 if (ret != I40E_SUCCESS) {
1031                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1032                         return -ENOTSUP;
1033                 }
1034                 ret = i40e_fdir_configure(dev);
1035                 if (ret < 0) {
1036                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1037                         goto err;
1038                 }
1039         } else
1040                 i40e_fdir_teardown(pf);
1041
1042         ret = i40e_dev_init_vlan(dev);
1043         if (ret < 0)
1044                 goto err;
1045
1046         /* VMDQ setup.
1047          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1048          *  RSS setting have different requirements.
1049          *  General PMD driver call sequence are NIC init, configure,
1050          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1051          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1052          *  applicable. So, VMDQ setting has to be done before
1053          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1054          *  For RSS setting, it will try to calculate actual configured RX queue
1055          *  number, which will be available after rx_queue_setup(). dev_start()
1056          *  function is good to place RSS setup.
1057          */
1058         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1059                 ret = i40e_vmdq_setup(dev);
1060                 if (ret)
1061                         goto err;
1062         }
1063
1064         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1065                 ret = i40e_dcb_setup(dev);
1066                 if (ret) {
1067                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1068                         goto err_dcb;
1069                 }
1070         }
1071
1072         return 0;
1073
1074 err_dcb:
1075         /* need to release vmdq resource if exists */
1076         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1077                 i40e_vsi_release(pf->vmdq[i].vsi);
1078                 pf->vmdq[i].vsi = NULL;
1079         }
1080         rte_free(pf->vmdq);
1081         pf->vmdq = NULL;
1082 err:
1083         /* need to release fdir resource if exists */
1084         i40e_fdir_teardown(pf);
1085         return ret;
1086 }
1087
1088 void
1089 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1090 {
1091         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1092         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1093         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1094         uint16_t msix_vect = vsi->msix_intr;
1095         uint16_t i;
1096
1097         for (i = 0; i < vsi->nb_qps; i++) {
1098                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1099                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1100                 rte_wmb();
1101         }
1102
1103         if (vsi->type != I40E_VSI_SRIOV) {
1104                 if (!rte_intr_allow_others(intr_handle)) {
1105                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1106                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1107                         I40E_WRITE_REG(hw,
1108                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1109                                        0);
1110                 } else {
1111                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1112                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1113                         I40E_WRITE_REG(hw,
1114                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1115                                                        msix_vect - 1), 0);
1116                 }
1117         } else {
1118                 uint32_t reg;
1119                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1120                         vsi->user_param + (msix_vect - 1);
1121
1122                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1123                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1124         }
1125         I40E_WRITE_FLUSH(hw);
1126 }
1127
1128 static void
1129 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1130                        int base_queue, int nb_queue)
1131 {
1132         int i;
1133         uint32_t val;
1134         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1135
1136         /* Bind all RX queues to allocated MSIX interrupt */
1137         for (i = 0; i < nb_queue; i++) {
1138                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1139                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1140                         ((base_queue + i + 1) <<
1141                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1142                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1143                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1144
1145                 if (i == nb_queue - 1)
1146                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1147                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1148         }
1149
1150         /* Write first RX queue to Link list register as the head element */
1151         if (vsi->type != I40E_VSI_SRIOV) {
1152                 uint16_t interval =
1153                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1154
1155                 if (msix_vect == I40E_MISC_VEC_ID) {
1156                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1157                                        (base_queue <<
1158                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1159                                        (0x0 <<
1160                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1161                         I40E_WRITE_REG(hw,
1162                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1163                                        interval);
1164                 } else {
1165                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1166                                        (base_queue <<
1167                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1168                                        (0x0 <<
1169                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1170                         I40E_WRITE_REG(hw,
1171                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1172                                                        msix_vect - 1),
1173                                        interval);
1174                 }
1175         } else {
1176                 uint32_t reg;
1177
1178                 if (msix_vect == I40E_MISC_VEC_ID) {
1179                         I40E_WRITE_REG(hw,
1180                                        I40E_VPINT_LNKLST0(vsi->user_param),
1181                                        (base_queue <<
1182                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1183                                        (0x0 <<
1184                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1185                 } else {
1186                         /* num_msix_vectors_vf needs to minus irq0 */
1187                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1188                                 vsi->user_param + (msix_vect - 1);
1189
1190                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1191                                        (base_queue <<
1192                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1193                                        (0x0 <<
1194                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1195                 }
1196         }
1197
1198         I40E_WRITE_FLUSH(hw);
1199 }
1200
1201 void
1202 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1203 {
1204         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1205         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1206         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1207         uint16_t msix_vect = vsi->msix_intr;
1208         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1209         uint16_t queue_idx = 0;
1210         int record = 0;
1211         uint32_t val;
1212         int i;
1213
1214         for (i = 0; i < vsi->nb_qps; i++) {
1215                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1216                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1217         }
1218
1219         /* INTENA flag is not auto-cleared for interrupt */
1220         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1221         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1222                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1223                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1224         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1225
1226         /* VF bind interrupt */
1227         if (vsi->type == I40E_VSI_SRIOV) {
1228                 __vsi_queues_bind_intr(vsi, msix_vect,
1229                                        vsi->base_queue, vsi->nb_qps);
1230                 return;
1231         }
1232
1233         /* PF & VMDq bind interrupt */
1234         if (rte_intr_dp_is_en(intr_handle)) {
1235                 if (vsi->type == I40E_VSI_MAIN) {
1236                         queue_idx = 0;
1237                         record = 1;
1238                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1239                         struct i40e_vsi *main_vsi =
1240                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1241                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1242                         record = 1;
1243                 }
1244         }
1245
1246         for (i = 0; i < vsi->nb_used_qps; i++) {
1247                 if (nb_msix <= 1) {
1248                         if (!rte_intr_allow_others(intr_handle))
1249                                 /* allow to share MISC_VEC_ID */
1250                                 msix_vect = I40E_MISC_VEC_ID;
1251
1252                         /* no enough msix_vect, map all to one */
1253                         __vsi_queues_bind_intr(vsi, msix_vect,
1254                                                vsi->base_queue + i,
1255                                                vsi->nb_used_qps - i);
1256                         for (; !!record && i < vsi->nb_used_qps; i++)
1257                                 intr_handle->intr_vec[queue_idx + i] =
1258                                         msix_vect;
1259                         break;
1260                 }
1261                 /* 1:1 queue/msix_vect mapping */
1262                 __vsi_queues_bind_intr(vsi, msix_vect,
1263                                        vsi->base_queue + i, 1);
1264                 if (!!record)
1265                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1266
1267                 msix_vect++;
1268                 nb_msix--;
1269         }
1270 }
1271
1272 static void
1273 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1274 {
1275         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1276         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1277         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1278         uint16_t interval = i40e_calc_itr_interval(\
1279                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1280         uint16_t msix_intr, i;
1281
1282         if (rte_intr_allow_others(intr_handle))
1283                 for (i = 0; i < vsi->nb_msix; i++) {
1284                         msix_intr = vsi->msix_intr + i;
1285                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1286                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1287                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1288                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1289                                 (interval <<
1290                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1291                 }
1292         else
1293                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1294                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1295                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1296                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1297                                (interval <<
1298                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1299
1300         I40E_WRITE_FLUSH(hw);
1301 }
1302
1303 static void
1304 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1305 {
1306         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1307         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1308         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1309         uint16_t msix_intr, i;
1310
1311         if (rte_intr_allow_others(intr_handle))
1312                 for (i = 0; i < vsi->nb_msix; i++) {
1313                         msix_intr = vsi->msix_intr + i;
1314                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1315                                        0);
1316                 }
1317         else
1318                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1319
1320         I40E_WRITE_FLUSH(hw);
1321 }
1322
1323 static inline uint8_t
1324 i40e_parse_link_speed(uint16_t eth_link_speed)
1325 {
1326         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1327
1328         switch (eth_link_speed) {
1329         case ETH_LINK_SPEED_40G:
1330                 link_speed = I40E_LINK_SPEED_40GB;
1331                 break;
1332         case ETH_LINK_SPEED_20G:
1333                 link_speed = I40E_LINK_SPEED_20GB;
1334                 break;
1335         case ETH_LINK_SPEED_10G:
1336                 link_speed = I40E_LINK_SPEED_10GB;
1337                 break;
1338         case ETH_LINK_SPEED_1000:
1339                 link_speed = I40E_LINK_SPEED_1GB;
1340                 break;
1341         case ETH_LINK_SPEED_100:
1342                 link_speed = I40E_LINK_SPEED_100MB;
1343                 break;
1344         }
1345
1346         return link_speed;
1347 }
1348
1349 static int
1350 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1351                    __rte_unused uint8_t abilities,
1352                    __rte_unused uint8_t force_speed)
1353 {
1354         /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1355          * for the link control limitation of that all link control should be
1356          * handled by firmware. It should follow up if link control will be
1357          * opened to software driver in future firmware versions.
1358          */
1359         return I40E_SUCCESS;
1360 }
1361
1362 static int
1363 i40e_apply_link_speed(struct rte_eth_dev *dev)
1364 {
1365         uint8_t speed;
1366         uint8_t abilities = 0;
1367         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1368         struct rte_eth_conf *conf = &dev->data->dev_conf;
1369
1370         speed = i40e_parse_link_speed(conf->link_speed);
1371         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1372         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1373                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1374         else
1375                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1376
1377         return i40e_phy_conf_link(hw, abilities, speed);
1378 }
1379
1380 static int
1381 i40e_dev_start(struct rte_eth_dev *dev)
1382 {
1383         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1384         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1385         struct i40e_vsi *main_vsi = pf->main_vsi;
1386         int ret, i;
1387         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1388         uint32_t intr_vector = 0;
1389
1390         hw->adapter_stopped = 0;
1391
1392         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1393                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1394                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1395                              dev->data->dev_conf.link_duplex,
1396                              dev->data->port_id);
1397                 return -EINVAL;
1398         }
1399
1400         rte_intr_disable(intr_handle);
1401
1402         if ((rte_intr_cap_multiple(intr_handle) ||
1403              !RTE_ETH_DEV_SRIOV(dev).active) &&
1404             dev->data->dev_conf.intr_conf.rxq != 0) {
1405                 intr_vector = dev->data->nb_rx_queues;
1406                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1407                         return -1;
1408         }
1409
1410         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1411                 intr_handle->intr_vec =
1412                         rte_zmalloc("intr_vec",
1413                                     dev->data->nb_rx_queues * sizeof(int),
1414                                     0);
1415                 if (!intr_handle->intr_vec) {
1416                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1417                                      " intr_vec\n", dev->data->nb_rx_queues);
1418                         return -ENOMEM;
1419                 }
1420         }
1421
1422         /* Initialize VSI */
1423         ret = i40e_dev_rxtx_init(pf);
1424         if (ret != I40E_SUCCESS) {
1425                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1426                 goto err_up;
1427         }
1428
1429         /* Map queues with MSIX interrupt */
1430         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1431                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1432         i40e_vsi_queues_bind_intr(main_vsi);
1433         i40e_vsi_enable_queues_intr(main_vsi);
1434
1435         /* Map VMDQ VSI queues with MSIX interrupt */
1436         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1437                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1438                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1439                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1440         }
1441
1442         /* enable FDIR MSIX interrupt */
1443         if (pf->fdir.fdir_vsi) {
1444                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1445                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1446         }
1447
1448         /* Enable all queues which have been configured */
1449         ret = i40e_dev_switch_queues(pf, TRUE);
1450         if (ret != I40E_SUCCESS) {
1451                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1452                 goto err_up;
1453         }
1454
1455         /* Enable receiving broadcast packets */
1456         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1457         if (ret != I40E_SUCCESS)
1458                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1459
1460         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1461                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1462                                                 true, NULL);
1463                 if (ret != I40E_SUCCESS)
1464                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1465         }
1466
1467         /* Apply link configure */
1468         ret = i40e_apply_link_speed(dev);
1469         if (I40E_SUCCESS != ret) {
1470                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1471                 goto err_up;
1472         }
1473
1474         if (!rte_intr_allow_others(intr_handle)) {
1475                 rte_intr_callback_unregister(intr_handle,
1476                                              i40e_dev_interrupt_handler,
1477                                              (void *)dev);
1478                 /* configure and enable device interrupt */
1479                 i40e_pf_config_irq0(hw, FALSE);
1480                 i40e_pf_enable_irq0(hw);
1481
1482                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1483                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1484                                      " no intr multiplex\n");
1485         }
1486
1487         /* enable uio intr after callback register */
1488         rte_intr_enable(intr_handle);
1489
1490         return I40E_SUCCESS;
1491
1492 err_up:
1493         i40e_dev_switch_queues(pf, FALSE);
1494         i40e_dev_clear_queues(dev);
1495
1496         return ret;
1497 }
1498
1499 static void
1500 i40e_dev_stop(struct rte_eth_dev *dev)
1501 {
1502         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1503         struct i40e_vsi *main_vsi = pf->main_vsi;
1504         struct i40e_mirror_rule *p_mirror;
1505         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1506         int i;
1507
1508         /* Disable all queues */
1509         i40e_dev_switch_queues(pf, FALSE);
1510
1511         /* un-map queues with interrupt registers */
1512         i40e_vsi_disable_queues_intr(main_vsi);
1513         i40e_vsi_queues_unbind_intr(main_vsi);
1514
1515         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1516                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1517                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1518         }
1519
1520         if (pf->fdir.fdir_vsi) {
1521                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1522                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1523         }
1524         /* Clear all queues and release memory */
1525         i40e_dev_clear_queues(dev);
1526
1527         /* Set link down */
1528         i40e_dev_set_link_down(dev);
1529
1530         /* Remove all mirror rules */
1531         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1532                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1533                 rte_free(p_mirror);
1534         }
1535         pf->nb_mirror_rule = 0;
1536
1537         if (!rte_intr_allow_others(intr_handle))
1538                 /* resume to the default handler */
1539                 rte_intr_callback_register(intr_handle,
1540                                            i40e_dev_interrupt_handler,
1541                                            (void *)dev);
1542
1543         /* Clean datapath event and queue/vec mapping */
1544         rte_intr_efd_disable(intr_handle);
1545         if (intr_handle->intr_vec) {
1546                 rte_free(intr_handle->intr_vec);
1547                 intr_handle->intr_vec = NULL;
1548         }
1549 }
1550
1551 static void
1552 i40e_dev_close(struct rte_eth_dev *dev)
1553 {
1554         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1555         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1556         uint32_t reg;
1557         int i;
1558
1559         PMD_INIT_FUNC_TRACE();
1560
1561         i40e_dev_stop(dev);
1562         hw->adapter_stopped = 1;
1563         i40e_dev_free_queues(dev);
1564
1565         /* Disable interrupt */
1566         i40e_pf_disable_irq0(hw);
1567         rte_intr_disable(&(dev->pci_dev->intr_handle));
1568
1569         /* shutdown and destroy the HMC */
1570         i40e_shutdown_lan_hmc(hw);
1571
1572         /* release all the existing VSIs and VEBs */
1573         i40e_fdir_teardown(pf);
1574         i40e_vsi_release(pf->main_vsi);
1575
1576         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1577                 i40e_vsi_release(pf->vmdq[i].vsi);
1578                 pf->vmdq[i].vsi = NULL;
1579         }
1580
1581         rte_free(pf->vmdq);
1582         pf->vmdq = NULL;
1583
1584         /* shutdown the adminq */
1585         i40e_aq_queue_shutdown(hw, true);
1586         i40e_shutdown_adminq(hw);
1587
1588         i40e_res_pool_destroy(&pf->qp_pool);
1589         i40e_res_pool_destroy(&pf->msix_pool);
1590
1591         /* force a PF reset to clean anything leftover */
1592         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1593         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1594                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1595         I40E_WRITE_FLUSH(hw);
1596 }
1597
1598 static void
1599 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1600 {
1601         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1602         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1603         struct i40e_vsi *vsi = pf->main_vsi;
1604         int status;
1605
1606         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1607                                                         true, NULL);
1608         if (status != I40E_SUCCESS)
1609                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1610
1611         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1612                                                         TRUE, NULL);
1613         if (status != I40E_SUCCESS)
1614                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1615
1616 }
1617
1618 static void
1619 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1620 {
1621         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1622         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1623         struct i40e_vsi *vsi = pf->main_vsi;
1624         int status;
1625
1626         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1627                                                         false, NULL);
1628         if (status != I40E_SUCCESS)
1629                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1630
1631         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1632                                                         false, NULL);
1633         if (status != I40E_SUCCESS)
1634                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1635 }
1636
1637 static void
1638 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1639 {
1640         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1641         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1642         struct i40e_vsi *vsi = pf->main_vsi;
1643         int ret;
1644
1645         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1646         if (ret != I40E_SUCCESS)
1647                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1648 }
1649
1650 static void
1651 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1652 {
1653         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655         struct i40e_vsi *vsi = pf->main_vsi;
1656         int ret;
1657
1658         if (dev->data->promiscuous == 1)
1659                 return; /* must remain in all_multicast mode */
1660
1661         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1662                                 vsi->seid, FALSE, NULL);
1663         if (ret != I40E_SUCCESS)
1664                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1665 }
1666
1667 /*
1668  * Set device link up.
1669  */
1670 static int
1671 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1672 {
1673         /* re-apply link speed setting */
1674         return i40e_apply_link_speed(dev);
1675 }
1676
1677 /*
1678  * Set device link down.
1679  */
1680 static int
1681 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1682 {
1683         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1684         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1685         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1686
1687         return i40e_phy_conf_link(hw, abilities, speed);
1688 }
1689
1690 int
1691 i40e_dev_link_update(struct rte_eth_dev *dev,
1692                      int wait_to_complete)
1693 {
1694 #define CHECK_INTERVAL 100  /* 100ms */
1695 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1696         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1697         struct i40e_link_status link_status;
1698         struct rte_eth_link link, old;
1699         int status;
1700         unsigned rep_cnt = MAX_REPEAT_TIME;
1701
1702         memset(&link, 0, sizeof(link));
1703         memset(&old, 0, sizeof(old));
1704         memset(&link_status, 0, sizeof(link_status));
1705         rte_i40e_dev_atomic_read_link_status(dev, &old);
1706
1707         do {
1708                 /* Get link status information from hardware */
1709                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1710                 if (status != I40E_SUCCESS) {
1711                         link.link_speed = ETH_LINK_SPEED_100;
1712                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1713                         PMD_DRV_LOG(ERR, "Failed to get link info");
1714                         goto out;
1715                 }
1716
1717                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1718                 if (!wait_to_complete)
1719                         break;
1720
1721                 rte_delay_ms(CHECK_INTERVAL);
1722         } while (!link.link_status && rep_cnt--);
1723
1724         if (!link.link_status)
1725                 goto out;
1726
1727         /* i40e uses full duplex only */
1728         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1729
1730         /* Parse the link status */
1731         switch (link_status.link_speed) {
1732         case I40E_LINK_SPEED_100MB:
1733                 link.link_speed = ETH_LINK_SPEED_100;
1734                 break;
1735         case I40E_LINK_SPEED_1GB:
1736                 link.link_speed = ETH_LINK_SPEED_1000;
1737                 break;
1738         case I40E_LINK_SPEED_10GB:
1739                 link.link_speed = ETH_LINK_SPEED_10G;
1740                 break;
1741         case I40E_LINK_SPEED_20GB:
1742                 link.link_speed = ETH_LINK_SPEED_20G;
1743                 break;
1744         case I40E_LINK_SPEED_40GB:
1745                 link.link_speed = ETH_LINK_SPEED_40G;
1746                 break;
1747         default:
1748                 link.link_speed = ETH_LINK_SPEED_100;
1749                 break;
1750         }
1751
1752 out:
1753         rte_i40e_dev_atomic_write_link_status(dev, &link);
1754         if (link.link_status == old.link_status)
1755                 return -1;
1756
1757         return 0;
1758 }
1759
1760 /* Get all the statistics of a VSI */
1761 void
1762 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1763 {
1764         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1765         struct i40e_eth_stats *nes = &vsi->eth_stats;
1766         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1767         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1768
1769         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1770                             vsi->offset_loaded, &oes->rx_bytes,
1771                             &nes->rx_bytes);
1772         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1773                             vsi->offset_loaded, &oes->rx_unicast,
1774                             &nes->rx_unicast);
1775         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1776                             vsi->offset_loaded, &oes->rx_multicast,
1777                             &nes->rx_multicast);
1778         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1779                             vsi->offset_loaded, &oes->rx_broadcast,
1780                             &nes->rx_broadcast);
1781         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1782                             &oes->rx_discards, &nes->rx_discards);
1783         /* GLV_REPC not supported */
1784         /* GLV_RMPC not supported */
1785         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1786                             &oes->rx_unknown_protocol,
1787                             &nes->rx_unknown_protocol);
1788         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1789                             vsi->offset_loaded, &oes->tx_bytes,
1790                             &nes->tx_bytes);
1791         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1792                             vsi->offset_loaded, &oes->tx_unicast,
1793                             &nes->tx_unicast);
1794         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1795                             vsi->offset_loaded, &oes->tx_multicast,
1796                             &nes->tx_multicast);
1797         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1798                             vsi->offset_loaded,  &oes->tx_broadcast,
1799                             &nes->tx_broadcast);
1800         /* GLV_TDPC not supported */
1801         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1802                             &oes->tx_errors, &nes->tx_errors);
1803         vsi->offset_loaded = true;
1804
1805         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1806                     vsi->vsi_id);
1807         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1808         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1809         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1810         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1811         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1812         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1813                     nes->rx_unknown_protocol);
1814         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1815         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1816         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1817         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1818         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1819         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1820         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1821                     vsi->vsi_id);
1822 }
1823
1824 static void
1825 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1826 {
1827         unsigned int i;
1828         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1829         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1830
1831         /* Get statistics of struct i40e_eth_stats */
1832         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1833                             I40E_GLPRT_GORCL(hw->port),
1834                             pf->offset_loaded, &os->eth.rx_bytes,
1835                             &ns->eth.rx_bytes);
1836         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1837                             I40E_GLPRT_UPRCL(hw->port),
1838                             pf->offset_loaded, &os->eth.rx_unicast,
1839                             &ns->eth.rx_unicast);
1840         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1841                             I40E_GLPRT_MPRCL(hw->port),
1842                             pf->offset_loaded, &os->eth.rx_multicast,
1843                             &ns->eth.rx_multicast);
1844         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1845                             I40E_GLPRT_BPRCL(hw->port),
1846                             pf->offset_loaded, &os->eth.rx_broadcast,
1847                             &ns->eth.rx_broadcast);
1848         /* Workaround: CRC size should not be included in byte statistics,
1849          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1850          */
1851         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1852                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1853
1854         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1855                             pf->offset_loaded, &os->eth.rx_discards,
1856                             &ns->eth.rx_discards);
1857         /* GLPRT_REPC not supported */
1858         /* GLPRT_RMPC not supported */
1859         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1860                             pf->offset_loaded,
1861                             &os->eth.rx_unknown_protocol,
1862                             &ns->eth.rx_unknown_protocol);
1863         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1864                             I40E_GLPRT_GOTCL(hw->port),
1865                             pf->offset_loaded, &os->eth.tx_bytes,
1866                             &ns->eth.tx_bytes);
1867         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1868                             I40E_GLPRT_UPTCL(hw->port),
1869                             pf->offset_loaded, &os->eth.tx_unicast,
1870                             &ns->eth.tx_unicast);
1871         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1872                             I40E_GLPRT_MPTCL(hw->port),
1873                             pf->offset_loaded, &os->eth.tx_multicast,
1874                             &ns->eth.tx_multicast);
1875         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1876                             I40E_GLPRT_BPTCL(hw->port),
1877                             pf->offset_loaded, &os->eth.tx_broadcast,
1878                             &ns->eth.tx_broadcast);
1879         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1880                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1881         /* GLPRT_TEPC not supported */
1882
1883         /* additional port specific stats */
1884         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1885                             pf->offset_loaded, &os->tx_dropped_link_down,
1886                             &ns->tx_dropped_link_down);
1887         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1888                             pf->offset_loaded, &os->crc_errors,
1889                             &ns->crc_errors);
1890         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1891                             pf->offset_loaded, &os->illegal_bytes,
1892                             &ns->illegal_bytes);
1893         /* GLPRT_ERRBC not supported */
1894         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1895                             pf->offset_loaded, &os->mac_local_faults,
1896                             &ns->mac_local_faults);
1897         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1898                             pf->offset_loaded, &os->mac_remote_faults,
1899                             &ns->mac_remote_faults);
1900         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1901                             pf->offset_loaded, &os->rx_length_errors,
1902                             &ns->rx_length_errors);
1903         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1904                             pf->offset_loaded, &os->link_xon_rx,
1905                             &ns->link_xon_rx);
1906         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1907                             pf->offset_loaded, &os->link_xoff_rx,
1908                             &ns->link_xoff_rx);
1909         for (i = 0; i < 8; i++) {
1910                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1911                                     pf->offset_loaded,
1912                                     &os->priority_xon_rx[i],
1913                                     &ns->priority_xon_rx[i]);
1914                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1915                                     pf->offset_loaded,
1916                                     &os->priority_xoff_rx[i],
1917                                     &ns->priority_xoff_rx[i]);
1918         }
1919         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1920                             pf->offset_loaded, &os->link_xon_tx,
1921                             &ns->link_xon_tx);
1922         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1923                             pf->offset_loaded, &os->link_xoff_tx,
1924                             &ns->link_xoff_tx);
1925         for (i = 0; i < 8; i++) {
1926                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1927                                     pf->offset_loaded,
1928                                     &os->priority_xon_tx[i],
1929                                     &ns->priority_xon_tx[i]);
1930                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1931                                     pf->offset_loaded,
1932                                     &os->priority_xoff_tx[i],
1933                                     &ns->priority_xoff_tx[i]);
1934                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1935                                     pf->offset_loaded,
1936                                     &os->priority_xon_2_xoff[i],
1937                                     &ns->priority_xon_2_xoff[i]);
1938         }
1939         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1940                             I40E_GLPRT_PRC64L(hw->port),
1941                             pf->offset_loaded, &os->rx_size_64,
1942                             &ns->rx_size_64);
1943         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1944                             I40E_GLPRT_PRC127L(hw->port),
1945                             pf->offset_loaded, &os->rx_size_127,
1946                             &ns->rx_size_127);
1947         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1948                             I40E_GLPRT_PRC255L(hw->port),
1949                             pf->offset_loaded, &os->rx_size_255,
1950                             &ns->rx_size_255);
1951         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1952                             I40E_GLPRT_PRC511L(hw->port),
1953                             pf->offset_loaded, &os->rx_size_511,
1954                             &ns->rx_size_511);
1955         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1956                             I40E_GLPRT_PRC1023L(hw->port),
1957                             pf->offset_loaded, &os->rx_size_1023,
1958                             &ns->rx_size_1023);
1959         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1960                             I40E_GLPRT_PRC1522L(hw->port),
1961                             pf->offset_loaded, &os->rx_size_1522,
1962                             &ns->rx_size_1522);
1963         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1964                             I40E_GLPRT_PRC9522L(hw->port),
1965                             pf->offset_loaded, &os->rx_size_big,
1966                             &ns->rx_size_big);
1967         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1968                             pf->offset_loaded, &os->rx_undersize,
1969                             &ns->rx_undersize);
1970         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1971                             pf->offset_loaded, &os->rx_fragments,
1972                             &ns->rx_fragments);
1973         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1974                             pf->offset_loaded, &os->rx_oversize,
1975                             &ns->rx_oversize);
1976         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1977                             pf->offset_loaded, &os->rx_jabber,
1978                             &ns->rx_jabber);
1979         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1980                             I40E_GLPRT_PTC64L(hw->port),
1981                             pf->offset_loaded, &os->tx_size_64,
1982                             &ns->tx_size_64);
1983         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1984                             I40E_GLPRT_PTC127L(hw->port),
1985                             pf->offset_loaded, &os->tx_size_127,
1986                             &ns->tx_size_127);
1987         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1988                             I40E_GLPRT_PTC255L(hw->port),
1989                             pf->offset_loaded, &os->tx_size_255,
1990                             &ns->tx_size_255);
1991         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1992                             I40E_GLPRT_PTC511L(hw->port),
1993                             pf->offset_loaded, &os->tx_size_511,
1994                             &ns->tx_size_511);
1995         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1996                             I40E_GLPRT_PTC1023L(hw->port),
1997                             pf->offset_loaded, &os->tx_size_1023,
1998                             &ns->tx_size_1023);
1999         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2000                             I40E_GLPRT_PTC1522L(hw->port),
2001                             pf->offset_loaded, &os->tx_size_1522,
2002                             &ns->tx_size_1522);
2003         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2004                             I40E_GLPRT_PTC9522L(hw->port),
2005                             pf->offset_loaded, &os->tx_size_big,
2006                             &ns->tx_size_big);
2007         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2008                            pf->offset_loaded,
2009                            &os->fd_sb_match, &ns->fd_sb_match);
2010         /* GLPRT_MSPDC not supported */
2011         /* GLPRT_XEC not supported */
2012
2013         pf->offset_loaded = true;
2014
2015         if (pf->main_vsi)
2016                 i40e_update_vsi_stats(pf->main_vsi);
2017 }
2018
2019 /* Get all statistics of a port */
2020 static void
2021 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2022 {
2023         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2024         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2026         unsigned i;
2027
2028         /* call read registers - updates values, now write them to struct */
2029         i40e_read_stats_registers(pf, hw);
2030
2031         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2032                         pf->main_vsi->eth_stats.rx_multicast +
2033                         pf->main_vsi->eth_stats.rx_broadcast -
2034                         pf->main_vsi->eth_stats.rx_discards;
2035         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2036                         pf->main_vsi->eth_stats.tx_multicast +
2037                         pf->main_vsi->eth_stats.tx_broadcast;
2038         stats->ibytes   = ns->eth.rx_bytes;
2039         stats->obytes   = ns->eth.tx_bytes;
2040         stats->oerrors  = ns->eth.tx_errors +
2041                         pf->main_vsi->eth_stats.tx_errors;
2042         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2043
2044         /* Rx Errors */
2045         stats->imissed  = ns->eth.rx_discards +
2046                         pf->main_vsi->eth_stats.rx_discards;
2047         stats->ierrors  = ns->crc_errors +
2048                         ns->rx_length_errors + ns->rx_undersize +
2049                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
2050                         stats->imissed;
2051
2052         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2053         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2054         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2055         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2056         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2057         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2058         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2059                     ns->eth.rx_unknown_protocol);
2060         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2061         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2062         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2063         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2064         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2065         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2066
2067         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2068                     ns->tx_dropped_link_down);
2069         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2070         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2071                     ns->illegal_bytes);
2072         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2073         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2074                     ns->mac_local_faults);
2075         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2076                     ns->mac_remote_faults);
2077         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2078                     ns->rx_length_errors);
2079         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2080         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2081         for (i = 0; i < 8; i++) {
2082                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2083                                 i, ns->priority_xon_rx[i]);
2084                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2085                                 i, ns->priority_xoff_rx[i]);
2086         }
2087         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2088         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2089         for (i = 0; i < 8; i++) {
2090                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2091                                 i, ns->priority_xon_tx[i]);
2092                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2093                                 i, ns->priority_xoff_tx[i]);
2094                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2095                                 i, ns->priority_xon_2_xoff[i]);
2096         }
2097         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2098         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2099         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2100         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2101         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2102         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2103         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2104         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2105         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2106         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2107         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2108         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2109         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2110         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2111         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2112         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2113         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2114         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2115         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2116                         ns->mac_short_packet_dropped);
2117         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2118                     ns->checksum_error);
2119         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2120         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2121 }
2122
2123 /* Reset the statistics */
2124 static void
2125 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2126 {
2127         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2128         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2129
2130         /* Mark PF and VSI stats to update the offset, aka "reset" */
2131         pf->offset_loaded = false;
2132         if (pf->main_vsi)
2133                 pf->main_vsi->offset_loaded = false;
2134
2135         /* read the stats, reading current register values into offset */
2136         i40e_read_stats_registers(pf, hw);
2137 }
2138
2139 static uint32_t
2140 i40e_xstats_calc_num(void)
2141 {
2142         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2143                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2144                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2145 }
2146
2147 static int
2148 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2149                     unsigned n)
2150 {
2151         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2152         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2153         unsigned i, count, prio;
2154         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2155
2156         count = i40e_xstats_calc_num();
2157         if (n < count)
2158                 return count;
2159
2160         i40e_read_stats_registers(pf, hw);
2161
2162         if (xstats == NULL)
2163                 return 0;
2164
2165         count = 0;
2166
2167         /* Get stats from i40e_eth_stats struct */
2168         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2169                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2170                          "%s", rte_i40e_stats_strings[i].name);
2171                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2172                         rte_i40e_stats_strings[i].offset);
2173                 count++;
2174         }
2175
2176         /* Get individiual stats from i40e_hw_port struct */
2177         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2178                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2179                          "%s", rte_i40e_hw_port_strings[i].name);
2180                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2181                                 rte_i40e_hw_port_strings[i].offset);
2182                 count++;
2183         }
2184
2185         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2186                 for (prio = 0; prio < 8; prio++) {
2187                         snprintf(xstats[count].name,
2188                                  sizeof(xstats[count].name),
2189                                  "rx_priority%u_%s", prio,
2190                                  rte_i40e_rxq_prio_strings[i].name);
2191                         xstats[count].value =
2192                                 *(uint64_t *)(((char *)hw_stats) +
2193                                 rte_i40e_rxq_prio_strings[i].offset +
2194                                 (sizeof(uint64_t) * prio));
2195                         count++;
2196                 }
2197         }
2198
2199         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2200                 for (prio = 0; prio < 8; prio++) {
2201                         snprintf(xstats[count].name,
2202                                  sizeof(xstats[count].name),
2203                                  "tx_priority%u_%s", prio,
2204                                  rte_i40e_txq_prio_strings[i].name);
2205                         xstats[count].value =
2206                                 *(uint64_t *)(((char *)hw_stats) +
2207                                 rte_i40e_txq_prio_strings[i].offset +
2208                                 (sizeof(uint64_t) * prio));
2209                         count++;
2210                 }
2211         }
2212
2213         return count;
2214 }
2215
2216 static int
2217 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2218                                  __rte_unused uint16_t queue_id,
2219                                  __rte_unused uint8_t stat_idx,
2220                                  __rte_unused uint8_t is_rx)
2221 {
2222         PMD_INIT_FUNC_TRACE();
2223
2224         return -ENOSYS;
2225 }
2226
2227 static void
2228 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2229 {
2230         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2231         struct i40e_vsi *vsi = pf->main_vsi;
2232
2233         dev_info->max_rx_queues = vsi->nb_qps;
2234         dev_info->max_tx_queues = vsi->nb_qps;
2235         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2236         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2237         dev_info->max_mac_addrs = vsi->max_macaddrs;
2238         dev_info->max_vfs = dev->pci_dev->max_vfs;
2239         dev_info->rx_offload_capa =
2240                 DEV_RX_OFFLOAD_VLAN_STRIP |
2241                 DEV_RX_OFFLOAD_QINQ_STRIP |
2242                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2243                 DEV_RX_OFFLOAD_UDP_CKSUM |
2244                 DEV_RX_OFFLOAD_TCP_CKSUM;
2245         dev_info->tx_offload_capa =
2246                 DEV_TX_OFFLOAD_VLAN_INSERT |
2247                 DEV_TX_OFFLOAD_QINQ_INSERT |
2248                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2249                 DEV_TX_OFFLOAD_UDP_CKSUM |
2250                 DEV_TX_OFFLOAD_TCP_CKSUM |
2251                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2252                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2253                 DEV_TX_OFFLOAD_TCP_TSO;
2254         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2255                                                 sizeof(uint32_t);
2256         dev_info->reta_size = pf->hash_lut_size;
2257         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2258
2259         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2260                 .rx_thresh = {
2261                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2262                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2263                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2264                 },
2265                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2266                 .rx_drop_en = 0,
2267         };
2268
2269         dev_info->default_txconf = (struct rte_eth_txconf) {
2270                 .tx_thresh = {
2271                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2272                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2273                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2274                 },
2275                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2276                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2277                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2278                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2279         };
2280
2281         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2282                 .nb_max = I40E_MAX_RING_DESC,
2283                 .nb_min = I40E_MIN_RING_DESC,
2284                 .nb_align = I40E_ALIGN_RING_DESC,
2285         };
2286
2287         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2288                 .nb_max = I40E_MAX_RING_DESC,
2289                 .nb_min = I40E_MIN_RING_DESC,
2290                 .nb_align = I40E_ALIGN_RING_DESC,
2291         };
2292
2293         if (pf->flags & I40E_FLAG_VMDQ) {
2294                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2295                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2296                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2297                                                 pf->max_nb_vmdq_vsi;
2298                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2299                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2300                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2301         }
2302 }
2303
2304 static int
2305 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2306 {
2307         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2308         struct i40e_vsi *vsi = pf->main_vsi;
2309         PMD_INIT_FUNC_TRACE();
2310
2311         if (on)
2312                 return i40e_vsi_add_vlan(vsi, vlan_id);
2313         else
2314                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2315 }
2316
2317 static void
2318 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2319                    __rte_unused uint16_t tpid)
2320 {
2321         PMD_INIT_FUNC_TRACE();
2322 }
2323
2324 static void
2325 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2326 {
2327         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2328         struct i40e_vsi *vsi = pf->main_vsi;
2329
2330         if (mask & ETH_VLAN_STRIP_MASK) {
2331                 /* Enable or disable VLAN stripping */
2332                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2333                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2334                 else
2335                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2336         }
2337
2338         if (mask & ETH_VLAN_EXTEND_MASK) {
2339                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2340                         i40e_vsi_config_double_vlan(vsi, TRUE);
2341                 else
2342                         i40e_vsi_config_double_vlan(vsi, FALSE);
2343         }
2344 }
2345
2346 static void
2347 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2348                           __rte_unused uint16_t queue,
2349                           __rte_unused int on)
2350 {
2351         PMD_INIT_FUNC_TRACE();
2352 }
2353
2354 static int
2355 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2356 {
2357         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2358         struct i40e_vsi *vsi = pf->main_vsi;
2359         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2360         struct i40e_vsi_vlan_pvid_info info;
2361
2362         memset(&info, 0, sizeof(info));
2363         info.on = on;
2364         if (info.on)
2365                 info.config.pvid = pvid;
2366         else {
2367                 info.config.reject.tagged =
2368                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2369                 info.config.reject.untagged =
2370                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2371         }
2372
2373         return i40e_vsi_vlan_pvid_set(vsi, &info);
2374 }
2375
2376 static int
2377 i40e_dev_led_on(struct rte_eth_dev *dev)
2378 {
2379         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2380         uint32_t mode = i40e_led_get(hw);
2381
2382         if (mode == 0)
2383                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2384
2385         return 0;
2386 }
2387
2388 static int
2389 i40e_dev_led_off(struct rte_eth_dev *dev)
2390 {
2391         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392         uint32_t mode = i40e_led_get(hw);
2393
2394         if (mode != 0)
2395                 i40e_led_set(hw, 0, false);
2396
2397         return 0;
2398 }
2399
2400 static int
2401 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2402 {
2403         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2405
2406         fc_conf->pause_time = pf->fc_conf.pause_time;
2407         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2408         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2409
2410          /* Return current mode according to actual setting*/
2411         switch (hw->fc.current_mode) {
2412         case I40E_FC_FULL:
2413                 fc_conf->mode = RTE_FC_FULL;
2414                 break;
2415         case I40E_FC_TX_PAUSE:
2416                 fc_conf->mode = RTE_FC_TX_PAUSE;
2417                 break;
2418         case I40E_FC_RX_PAUSE:
2419                 fc_conf->mode = RTE_FC_RX_PAUSE;
2420                 break;
2421         case I40E_FC_NONE:
2422         default:
2423                 fc_conf->mode = RTE_FC_NONE;
2424         };
2425
2426         return 0;
2427 }
2428
2429 static int
2430 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2431 {
2432         uint32_t mflcn_reg, fctrl_reg, reg;
2433         uint32_t max_high_water;
2434         uint8_t i, aq_failure;
2435         int err;
2436         struct i40e_hw *hw;
2437         struct i40e_pf *pf;
2438         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2439                 [RTE_FC_NONE] = I40E_FC_NONE,
2440                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2441                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2442                 [RTE_FC_FULL] = I40E_FC_FULL
2443         };
2444
2445         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2446
2447         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2448         if ((fc_conf->high_water > max_high_water) ||
2449                         (fc_conf->high_water < fc_conf->low_water)) {
2450                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2451                         "High_water must <= %d.", max_high_water);
2452                 return -EINVAL;
2453         }
2454
2455         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2457         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2458
2459         pf->fc_conf.pause_time = fc_conf->pause_time;
2460         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2461         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2462
2463         PMD_INIT_FUNC_TRACE();
2464
2465         /* All the link flow control related enable/disable register
2466          * configuration is handle by the F/W
2467          */
2468         err = i40e_set_fc(hw, &aq_failure, true);
2469         if (err < 0)
2470                 return -ENOSYS;
2471
2472         if (i40e_is_40G_device(hw->device_id)) {
2473                 /* Configure flow control refresh threshold,
2474                  * the value for stat_tx_pause_refresh_timer[8]
2475                  * is used for global pause operation.
2476                  */
2477
2478                 I40E_WRITE_REG(hw,
2479                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2480                                pf->fc_conf.pause_time);
2481
2482                 /* configure the timer value included in transmitted pause
2483                  * frame,
2484                  * the value for stat_tx_pause_quanta[8] is used for global
2485                  * pause operation
2486                  */
2487                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2488                                pf->fc_conf.pause_time);
2489
2490                 fctrl_reg = I40E_READ_REG(hw,
2491                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2492
2493                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2494                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2495                 else
2496                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2497
2498                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2499                                fctrl_reg);
2500         } else {
2501                 /* Configure pause time (2 TCs per register) */
2502                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2503                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2504                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2505
2506                 /* Configure flow control refresh threshold value */
2507                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2508                                pf->fc_conf.pause_time / 2);
2509
2510                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2511
2512                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2513                  *depending on configuration
2514                  */
2515                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2516                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2517                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2518                 } else {
2519                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2520                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2521                 }
2522
2523                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2524         }
2525
2526         /* config the water marker both based on the packets and bytes */
2527         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2528                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2529                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2530         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2531                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2532                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2533         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2534                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2535                        << I40E_KILOSHIFT);
2536         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2537                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2538                        << I40E_KILOSHIFT);
2539
2540         I40E_WRITE_FLUSH(hw);
2541
2542         return 0;
2543 }
2544
2545 static int
2546 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2547                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2548 {
2549         PMD_INIT_FUNC_TRACE();
2550
2551         return -ENOSYS;
2552 }
2553
2554 /* Add a MAC address, and update filters */
2555 static void
2556 i40e_macaddr_add(struct rte_eth_dev *dev,
2557                  struct ether_addr *mac_addr,
2558                  __rte_unused uint32_t index,
2559                  uint32_t pool)
2560 {
2561         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2562         struct i40e_mac_filter_info mac_filter;
2563         struct i40e_vsi *vsi;
2564         int ret;
2565
2566         /* If VMDQ not enabled or configured, return */
2567         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2568                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2569                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2570                         pool);
2571                 return;
2572         }
2573
2574         if (pool > pf->nb_cfg_vmdq_vsi) {
2575                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2576                                 pool, pf->nb_cfg_vmdq_vsi);
2577                 return;
2578         }
2579
2580         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2581         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2582
2583         if (pool == 0)
2584                 vsi = pf->main_vsi;
2585         else
2586                 vsi = pf->vmdq[pool - 1].vsi;
2587
2588         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2589         if (ret != I40E_SUCCESS) {
2590                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2591                 return;
2592         }
2593 }
2594
2595 /* Remove a MAC address, and update filters */
2596 static void
2597 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2598 {
2599         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2600         struct i40e_vsi *vsi;
2601         struct rte_eth_dev_data *data = dev->data;
2602         struct ether_addr *macaddr;
2603         int ret;
2604         uint32_t i;
2605         uint64_t pool_sel;
2606
2607         macaddr = &(data->mac_addrs[index]);
2608
2609         pool_sel = dev->data->mac_pool_sel[index];
2610
2611         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2612                 if (pool_sel & (1ULL << i)) {
2613                         if (i == 0)
2614                                 vsi = pf->main_vsi;
2615                         else {
2616                                 /* No VMDQ pool enabled or configured */
2617                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2618                                         (i > pf->nb_cfg_vmdq_vsi)) {
2619                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2620                                                         "/configured");
2621                                         return;
2622                                 }
2623                                 vsi = pf->vmdq[i - 1].vsi;
2624                         }
2625                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2626
2627                         if (ret) {
2628                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2629                                 return;
2630                         }
2631                 }
2632         }
2633 }
2634
2635 /* Set perfect match or hash match of MAC and VLAN for a VF */
2636 static int
2637 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2638                  struct rte_eth_mac_filter *filter,
2639                  bool add)
2640 {
2641         struct i40e_hw *hw;
2642         struct i40e_mac_filter_info mac_filter;
2643         struct ether_addr old_mac;
2644         struct ether_addr *new_mac;
2645         struct i40e_pf_vf *vf = NULL;
2646         uint16_t vf_id;
2647         int ret;
2648
2649         if (pf == NULL) {
2650                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2651                 return -EINVAL;
2652         }
2653         hw = I40E_PF_TO_HW(pf);
2654
2655         if (filter == NULL) {
2656                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2657                 return -EINVAL;
2658         }
2659
2660         new_mac = &filter->mac_addr;
2661
2662         if (is_zero_ether_addr(new_mac)) {
2663                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2664                 return -EINVAL;
2665         }
2666
2667         vf_id = filter->dst_id;
2668
2669         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2670                 PMD_DRV_LOG(ERR, "Invalid argument.");
2671                 return -EINVAL;
2672         }
2673         vf = &pf->vfs[vf_id];
2674
2675         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2676                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2677                 return -EINVAL;
2678         }
2679
2680         if (add) {
2681                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2682                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2683                                 ETHER_ADDR_LEN);
2684                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2685                                  ETHER_ADDR_LEN);
2686
2687                 mac_filter.filter_type = filter->filter_type;
2688                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2689                 if (ret != I40E_SUCCESS) {
2690                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2691                         return -1;
2692                 }
2693                 ether_addr_copy(new_mac, &pf->dev_addr);
2694         } else {
2695                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2696                                 ETHER_ADDR_LEN);
2697                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2698                 if (ret != I40E_SUCCESS) {
2699                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2700                         return -1;
2701                 }
2702
2703                 /* Clear device address as it has been removed */
2704                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2705                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2706         }
2707
2708         return 0;
2709 }
2710
2711 /* MAC filter handle */
2712 static int
2713 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2714                 void *arg)
2715 {
2716         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2717         struct rte_eth_mac_filter *filter;
2718         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2719         int ret = I40E_NOT_SUPPORTED;
2720
2721         filter = (struct rte_eth_mac_filter *)(arg);
2722
2723         switch (filter_op) {
2724         case RTE_ETH_FILTER_NOP:
2725                 ret = I40E_SUCCESS;
2726                 break;
2727         case RTE_ETH_FILTER_ADD:
2728                 i40e_pf_disable_irq0(hw);
2729                 if (filter->is_vf)
2730                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2731                 i40e_pf_enable_irq0(hw);
2732                 break;
2733         case RTE_ETH_FILTER_DELETE:
2734                 i40e_pf_disable_irq0(hw);
2735                 if (filter->is_vf)
2736                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2737                 i40e_pf_enable_irq0(hw);
2738                 break;
2739         default:
2740                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2741                 ret = I40E_ERR_PARAM;
2742                 break;
2743         }
2744
2745         return ret;
2746 }
2747
2748 static int
2749 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2750 {
2751         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2752         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2753         int ret;
2754
2755         if (!lut)
2756                 return -EINVAL;
2757
2758         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2759                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2760                                           lut, lut_size);
2761                 if (ret) {
2762                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2763                         return ret;
2764                 }
2765         } else {
2766                 uint32_t *lut_dw = (uint32_t *)lut;
2767                 uint16_t i, lut_size_dw = lut_size / 4;
2768
2769                 for (i = 0; i < lut_size_dw; i++)
2770                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2771         }
2772
2773         return 0;
2774 }
2775
2776 static int
2777 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2778 {
2779         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2780         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2781         int ret;
2782
2783         if (!vsi || !lut)
2784                 return -EINVAL;
2785
2786         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2787                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2788                                           lut, lut_size);
2789                 if (ret) {
2790                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2791                         return ret;
2792                 }
2793         } else {
2794                 uint32_t *lut_dw = (uint32_t *)lut;
2795                 uint16_t i, lut_size_dw = lut_size / 4;
2796
2797                 for (i = 0; i < lut_size_dw; i++)
2798                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2799                 I40E_WRITE_FLUSH(hw);
2800         }
2801
2802         return 0;
2803 }
2804
2805 static int
2806 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2807                          struct rte_eth_rss_reta_entry64 *reta_conf,
2808                          uint16_t reta_size)
2809 {
2810         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2811         uint16_t i, lut_size = pf->hash_lut_size;
2812         uint16_t idx, shift;
2813         uint8_t *lut;
2814         int ret;
2815
2816         if (reta_size != lut_size ||
2817                 reta_size > ETH_RSS_RETA_SIZE_512) {
2818                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2819                         "(%d) doesn't match the number hardware can supported "
2820                                         "(%d)\n", reta_size, lut_size);
2821                 return -EINVAL;
2822         }
2823
2824         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2825         if (!lut) {
2826                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2827                 return -ENOMEM;
2828         }
2829         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2830         if (ret)
2831                 goto out;
2832         for (i = 0; i < reta_size; i++) {
2833                 idx = i / RTE_RETA_GROUP_SIZE;
2834                 shift = i % RTE_RETA_GROUP_SIZE;
2835                 if (reta_conf[idx].mask & (1ULL << shift))
2836                         lut[i] = reta_conf[idx].reta[shift];
2837         }
2838         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2839
2840 out:
2841         rte_free(lut);
2842
2843         return ret;
2844 }
2845
2846 static int
2847 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2848                         struct rte_eth_rss_reta_entry64 *reta_conf,
2849                         uint16_t reta_size)
2850 {
2851         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2852         uint16_t i, lut_size = pf->hash_lut_size;
2853         uint16_t idx, shift;
2854         uint8_t *lut;
2855         int ret;
2856
2857         if (reta_size != lut_size ||
2858                 reta_size > ETH_RSS_RETA_SIZE_512) {
2859                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2860                         "(%d) doesn't match the number hardware can supported "
2861                                         "(%d)\n", reta_size, lut_size);
2862                 return -EINVAL;
2863         }
2864
2865         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2866         if (!lut) {
2867                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2868                 return -ENOMEM;
2869         }
2870
2871         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2872         if (ret)
2873                 goto out;
2874         for (i = 0; i < reta_size; i++) {
2875                 idx = i / RTE_RETA_GROUP_SIZE;
2876                 shift = i % RTE_RETA_GROUP_SIZE;
2877                 if (reta_conf[idx].mask & (1ULL << shift))
2878                         reta_conf[idx].reta[shift] = lut[i];
2879         }
2880
2881 out:
2882         rte_free(lut);
2883
2884         return ret;
2885 }
2886
2887 /**
2888  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2889  * @hw:   pointer to the HW structure
2890  * @mem:  pointer to mem struct to fill out
2891  * @size: size of memory requested
2892  * @alignment: what to align the allocation to
2893  **/
2894 enum i40e_status_code
2895 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2896                         struct i40e_dma_mem *mem,
2897                         u64 size,
2898                         u32 alignment)
2899 {
2900         const struct rte_memzone *mz = NULL;
2901         char z_name[RTE_MEMZONE_NAMESIZE];
2902
2903         if (!mem)
2904                 return I40E_ERR_PARAM;
2905
2906         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
2907         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2908                                          alignment, RTE_PGSIZE_2M);
2909         if (!mz)
2910                 return I40E_ERR_NO_MEMORY;
2911
2912         mem->size = size;
2913         mem->va = mz->addr;
2914         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2915         mem->zone = (const void *)mz;
2916         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
2917                     "%"PRIu64, mz->name, mem->pa);
2918
2919         return I40E_SUCCESS;
2920 }
2921
2922 /**
2923  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2924  * @hw:   pointer to the HW structure
2925  * @mem:  ptr to mem struct to free
2926  **/
2927 enum i40e_status_code
2928 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2929                     struct i40e_dma_mem *mem)
2930 {
2931         if (!mem)
2932                 return I40E_ERR_PARAM;
2933
2934         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
2935                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
2936                     mem->pa);
2937         rte_memzone_free((const struct rte_memzone *)mem->zone);
2938         mem->zone = NULL;
2939         mem->va = NULL;
2940         mem->pa = (u64)0;
2941
2942         return I40E_SUCCESS;
2943 }
2944
2945 /**
2946  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2947  * @hw:   pointer to the HW structure
2948  * @mem:  pointer to mem struct to fill out
2949  * @size: size of memory requested
2950  **/
2951 enum i40e_status_code
2952 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2953                          struct i40e_virt_mem *mem,
2954                          u32 size)
2955 {
2956         if (!mem)
2957                 return I40E_ERR_PARAM;
2958
2959         mem->size = size;
2960         mem->va = rte_zmalloc("i40e", size, 0);
2961
2962         if (mem->va)
2963                 return I40E_SUCCESS;
2964         else
2965                 return I40E_ERR_NO_MEMORY;
2966 }
2967
2968 /**
2969  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2970  * @hw:   pointer to the HW structure
2971  * @mem:  pointer to mem struct to free
2972  **/
2973 enum i40e_status_code
2974 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2975                      struct i40e_virt_mem *mem)
2976 {
2977         if (!mem)
2978                 return I40E_ERR_PARAM;
2979
2980         rte_free(mem->va);
2981         mem->va = NULL;
2982
2983         return I40E_SUCCESS;
2984 }
2985
2986 void
2987 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2988 {
2989         rte_spinlock_init(&sp->spinlock);
2990 }
2991
2992 void
2993 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2994 {
2995         rte_spinlock_lock(&sp->spinlock);
2996 }
2997
2998 void
2999 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3000 {
3001         rte_spinlock_unlock(&sp->spinlock);
3002 }
3003
3004 void
3005 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3006 {
3007         return;
3008 }
3009
3010 /**
3011  * Get the hardware capabilities, which will be parsed
3012  * and saved into struct i40e_hw.
3013  */
3014 static int
3015 i40e_get_cap(struct i40e_hw *hw)
3016 {
3017         struct i40e_aqc_list_capabilities_element_resp *buf;
3018         uint16_t len, size = 0;
3019         int ret;
3020
3021         /* Calculate a huge enough buff for saving response data temporarily */
3022         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3023                                                 I40E_MAX_CAP_ELE_NUM;
3024         buf = rte_zmalloc("i40e", len, 0);
3025         if (!buf) {
3026                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3027                 return I40E_ERR_NO_MEMORY;
3028         }
3029
3030         /* Get, parse the capabilities and save it to hw */
3031         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3032                         i40e_aqc_opc_list_func_capabilities, NULL);
3033         if (ret != I40E_SUCCESS)
3034                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3035
3036         /* Free the temporary buffer after being used */
3037         rte_free(buf);
3038
3039         return ret;
3040 }
3041
3042 static int
3043 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3044 {
3045         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3046         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3047         uint16_t qp_count = 0, vsi_count = 0;
3048
3049         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3050                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3051                 return -EINVAL;
3052         }
3053         /* Add the parameter init for LFC */
3054         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3055         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3056         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3057
3058         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3059         pf->max_num_vsi = hw->func_caps.num_vsis;
3060         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3061         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3062         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3063
3064         /* FDir queue/VSI allocation */
3065         pf->fdir_qp_offset = 0;
3066         if (hw->func_caps.fd) {
3067                 pf->flags |= I40E_FLAG_FDIR;
3068                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3069         } else {
3070                 pf->fdir_nb_qps = 0;
3071         }
3072         qp_count += pf->fdir_nb_qps;
3073         vsi_count += 1;
3074
3075         /* LAN queue/VSI allocation */
3076         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3077         if (!hw->func_caps.rss) {
3078                 pf->lan_nb_qps = 1;
3079         } else {
3080                 pf->flags |= I40E_FLAG_RSS;
3081                 if (hw->mac.type == I40E_MAC_X722)
3082                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3083                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3084         }
3085         qp_count += pf->lan_nb_qps;
3086         vsi_count += 1;
3087
3088         /* VF queue/VSI allocation */
3089         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3090         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3091                 pf->flags |= I40E_FLAG_SRIOV;
3092                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3093                 pf->vf_num = dev->pci_dev->max_vfs;
3094                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3095                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3096                             pf->vf_nb_qps * pf->vf_num);
3097         } else {
3098                 pf->vf_nb_qps = 0;
3099                 pf->vf_num = 0;
3100         }
3101         qp_count += pf->vf_nb_qps * pf->vf_num;
3102         vsi_count += pf->vf_num;
3103
3104         /* VMDq queue/VSI allocation */
3105         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3106         pf->vmdq_nb_qps = 0;
3107         pf->max_nb_vmdq_vsi = 0;
3108         if (hw->func_caps.vmdq) {
3109                 if (qp_count < hw->func_caps.num_tx_qp &&
3110                         vsi_count < hw->func_caps.num_vsis) {
3111                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3112                                 qp_count) / pf->vmdq_nb_qp_max;
3113
3114                         /* Limit the maximum number of VMDq vsi to the maximum
3115                          * ethdev can support
3116                          */
3117                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3118                                 hw->func_caps.num_vsis - vsi_count);
3119                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3120                                 ETH_64_POOLS);
3121                         if (pf->max_nb_vmdq_vsi) {
3122                                 pf->flags |= I40E_FLAG_VMDQ;
3123                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3124                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3125                                             "per VMDQ VSI, in total %u queues",
3126                                             pf->max_nb_vmdq_vsi,
3127                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3128                                             pf->max_nb_vmdq_vsi);
3129                         } else {
3130                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3131                                             "VMDq");
3132                         }
3133                 } else {
3134                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3135                 }
3136         }
3137         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3138         vsi_count += pf->max_nb_vmdq_vsi;
3139
3140         if (hw->func_caps.dcb)
3141                 pf->flags |= I40E_FLAG_DCB;
3142
3143         if (qp_count > hw->func_caps.num_tx_qp) {
3144                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3145                             "the hardware maximum %u", qp_count,
3146                             hw->func_caps.num_tx_qp);
3147                 return -EINVAL;
3148         }
3149         if (vsi_count > hw->func_caps.num_vsis) {
3150                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3151                             "the hardware maximum %u", vsi_count,
3152                             hw->func_caps.num_vsis);
3153                 return -EINVAL;
3154         }
3155
3156         return 0;
3157 }
3158
3159 static int
3160 i40e_pf_get_switch_config(struct i40e_pf *pf)
3161 {
3162         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3163         struct i40e_aqc_get_switch_config_resp *switch_config;
3164         struct i40e_aqc_switch_config_element_resp *element;
3165         uint16_t start_seid = 0, num_reported;
3166         int ret;
3167
3168         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3169                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3170         if (!switch_config) {
3171                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3172                 return -ENOMEM;
3173         }
3174
3175         /* Get the switch configurations */
3176         ret = i40e_aq_get_switch_config(hw, switch_config,
3177                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3178         if (ret != I40E_SUCCESS) {
3179                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3180                 goto fail;
3181         }
3182         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3183         if (num_reported != 1) { /* The number should be 1 */
3184                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3185                 goto fail;
3186         }
3187
3188         /* Parse the switch configuration elements */
3189         element = &(switch_config->element[0]);
3190         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3191                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3192                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3193         } else
3194                 PMD_DRV_LOG(INFO, "Unknown element type");
3195
3196 fail:
3197         rte_free(switch_config);
3198
3199         return ret;
3200 }
3201
3202 static int
3203 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3204                         uint32_t num)
3205 {
3206         struct pool_entry *entry;
3207
3208         if (pool == NULL || num == 0)
3209                 return -EINVAL;
3210
3211         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3212         if (entry == NULL) {
3213                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3214                 return -ENOMEM;
3215         }
3216
3217         /* queue heap initialize */
3218         pool->num_free = num;
3219         pool->num_alloc = 0;
3220         pool->base = base;
3221         LIST_INIT(&pool->alloc_list);
3222         LIST_INIT(&pool->free_list);
3223
3224         /* Initialize element  */
3225         entry->base = 0;
3226         entry->len = num;
3227
3228         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3229         return 0;
3230 }
3231
3232 static void
3233 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3234 {
3235         struct pool_entry *entry;
3236
3237         if (pool == NULL)
3238                 return;
3239
3240         LIST_FOREACH(entry, &pool->alloc_list, next) {
3241                 LIST_REMOVE(entry, next);
3242                 rte_free(entry);
3243         }
3244
3245         LIST_FOREACH(entry, &pool->free_list, next) {
3246                 LIST_REMOVE(entry, next);
3247                 rte_free(entry);
3248         }
3249
3250         pool->num_free = 0;
3251         pool->num_alloc = 0;
3252         pool->base = 0;
3253         LIST_INIT(&pool->alloc_list);
3254         LIST_INIT(&pool->free_list);
3255 }
3256
3257 static int
3258 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3259                        uint32_t base)
3260 {
3261         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3262         uint32_t pool_offset;
3263         int insert;
3264
3265         if (pool == NULL) {
3266                 PMD_DRV_LOG(ERR, "Invalid parameter");
3267                 return -EINVAL;
3268         }
3269
3270         pool_offset = base - pool->base;
3271         /* Lookup in alloc list */
3272         LIST_FOREACH(entry, &pool->alloc_list, next) {
3273                 if (entry->base == pool_offset) {
3274                         valid_entry = entry;
3275                         LIST_REMOVE(entry, next);
3276                         break;
3277                 }
3278         }
3279
3280         /* Not find, return */
3281         if (valid_entry == NULL) {
3282                 PMD_DRV_LOG(ERR, "Failed to find entry");
3283                 return -EINVAL;
3284         }
3285
3286         /**
3287          * Found it, move it to free list  and try to merge.
3288          * In order to make merge easier, always sort it by qbase.
3289          * Find adjacent prev and last entries.
3290          */
3291         prev = next = NULL;
3292         LIST_FOREACH(entry, &pool->free_list, next) {
3293                 if (entry->base > valid_entry->base) {
3294                         next = entry;
3295                         break;
3296                 }
3297                 prev = entry;
3298         }
3299
3300         insert = 0;
3301         /* Try to merge with next one*/
3302         if (next != NULL) {
3303                 /* Merge with next one */
3304                 if (valid_entry->base + valid_entry->len == next->base) {
3305                         next->base = valid_entry->base;
3306                         next->len += valid_entry->len;
3307                         rte_free(valid_entry);
3308                         valid_entry = next;
3309                         insert = 1;
3310                 }
3311         }
3312
3313         if (prev != NULL) {
3314                 /* Merge with previous one */
3315                 if (prev->base + prev->len == valid_entry->base) {
3316                         prev->len += valid_entry->len;
3317                         /* If it merge with next one, remove next node */
3318                         if (insert == 1) {
3319                                 LIST_REMOVE(valid_entry, next);
3320                                 rte_free(valid_entry);
3321                         } else {
3322                                 rte_free(valid_entry);
3323                                 insert = 1;
3324                         }
3325                 }
3326         }
3327
3328         /* Not find any entry to merge, insert */
3329         if (insert == 0) {
3330                 if (prev != NULL)
3331                         LIST_INSERT_AFTER(prev, valid_entry, next);
3332                 else if (next != NULL)
3333                         LIST_INSERT_BEFORE(next, valid_entry, next);
3334                 else /* It's empty list, insert to head */
3335                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3336         }
3337
3338         pool->num_free += valid_entry->len;
3339         pool->num_alloc -= valid_entry->len;
3340
3341         return 0;
3342 }
3343
3344 static int
3345 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3346                        uint16_t num)
3347 {
3348         struct pool_entry *entry, *valid_entry;
3349
3350         if (pool == NULL || num == 0) {
3351                 PMD_DRV_LOG(ERR, "Invalid parameter");
3352                 return -EINVAL;
3353         }
3354
3355         if (pool->num_free < num) {
3356                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3357                             num, pool->num_free);
3358                 return -ENOMEM;
3359         }
3360
3361         valid_entry = NULL;
3362         /* Lookup  in free list and find most fit one */
3363         LIST_FOREACH(entry, &pool->free_list, next) {
3364                 if (entry->len >= num) {
3365                         /* Find best one */
3366                         if (entry->len == num) {
3367                                 valid_entry = entry;
3368                                 break;
3369                         }
3370                         if (valid_entry == NULL || valid_entry->len > entry->len)
3371                                 valid_entry = entry;
3372                 }
3373         }
3374
3375         /* Not find one to satisfy the request, return */
3376         if (valid_entry == NULL) {
3377                 PMD_DRV_LOG(ERR, "No valid entry found");
3378                 return -ENOMEM;
3379         }
3380         /**
3381          * The entry have equal queue number as requested,
3382          * remove it from alloc_list.
3383          */
3384         if (valid_entry->len == num) {
3385                 LIST_REMOVE(valid_entry, next);
3386         } else {
3387                 /**
3388                  * The entry have more numbers than requested,
3389                  * create a new entry for alloc_list and minus its
3390                  * queue base and number in free_list.
3391                  */
3392                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3393                 if (entry == NULL) {
3394                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3395                                     "resource pool");
3396                         return -ENOMEM;
3397                 }
3398                 entry->base = valid_entry->base;
3399                 entry->len = num;
3400                 valid_entry->base += num;
3401                 valid_entry->len -= num;
3402                 valid_entry = entry;
3403         }
3404
3405         /* Insert it into alloc list, not sorted */
3406         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3407
3408         pool->num_free -= valid_entry->len;
3409         pool->num_alloc += valid_entry->len;
3410
3411         return (valid_entry->base + pool->base);
3412 }
3413
3414 /**
3415  * bitmap_is_subset - Check whether src2 is subset of src1
3416  **/
3417 static inline int
3418 bitmap_is_subset(uint8_t src1, uint8_t src2)
3419 {
3420         return !((src1 ^ src2) & src2);
3421 }
3422
3423 static enum i40e_status_code
3424 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3425 {
3426         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3427
3428         /* If DCB is not supported, only default TC is supported */
3429         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3430                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3431                 return I40E_NOT_SUPPORTED;
3432         }
3433
3434         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3435                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3436                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3437                             enabled_tcmap);
3438                 return I40E_NOT_SUPPORTED;
3439         }
3440         return I40E_SUCCESS;
3441 }
3442
3443 int
3444 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3445                                 struct i40e_vsi_vlan_pvid_info *info)
3446 {
3447         struct i40e_hw *hw;
3448         struct i40e_vsi_context ctxt;
3449         uint8_t vlan_flags = 0;
3450         int ret;
3451
3452         if (vsi == NULL || info == NULL) {
3453                 PMD_DRV_LOG(ERR, "invalid parameters");
3454                 return I40E_ERR_PARAM;
3455         }
3456
3457         if (info->on) {
3458                 vsi->info.pvid = info->config.pvid;
3459                 /**
3460                  * If insert pvid is enabled, only tagged pkts are
3461                  * allowed to be sent out.
3462                  */
3463                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3464                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3465         } else {
3466                 vsi->info.pvid = 0;
3467                 if (info->config.reject.tagged == 0)
3468                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3469
3470                 if (info->config.reject.untagged == 0)
3471                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3472         }
3473         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3474                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3475         vsi->info.port_vlan_flags |= vlan_flags;
3476         vsi->info.valid_sections =
3477                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3478         memset(&ctxt, 0, sizeof(ctxt));
3479         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3480         ctxt.seid = vsi->seid;
3481
3482         hw = I40E_VSI_TO_HW(vsi);
3483         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3484         if (ret != I40E_SUCCESS)
3485                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3486
3487         return ret;
3488 }
3489
3490 static int
3491 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3492 {
3493         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3494         int i, ret;
3495         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3496
3497         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3498         if (ret != I40E_SUCCESS)
3499                 return ret;
3500
3501         if (!vsi->seid) {
3502                 PMD_DRV_LOG(ERR, "seid not valid");
3503                 return -EINVAL;
3504         }
3505
3506         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3507         tc_bw_data.tc_valid_bits = enabled_tcmap;
3508         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3509                 tc_bw_data.tc_bw_credits[i] =
3510                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3511
3512         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3513         if (ret != I40E_SUCCESS) {
3514                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3515                 return ret;
3516         }
3517
3518         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3519                                         sizeof(vsi->info.qs_handle));
3520         return I40E_SUCCESS;
3521 }
3522
3523 static enum i40e_status_code
3524 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3525                                  struct i40e_aqc_vsi_properties_data *info,
3526                                  uint8_t enabled_tcmap)
3527 {
3528         enum i40e_status_code ret;
3529         int i, total_tc = 0;
3530         uint16_t qpnum_per_tc, bsf, qp_idx;
3531
3532         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3533         if (ret != I40E_SUCCESS)
3534                 return ret;
3535
3536         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3537                 if (enabled_tcmap & (1 << i))
3538                         total_tc++;
3539         vsi->enabled_tc = enabled_tcmap;
3540
3541         /* Number of queues per enabled TC */
3542         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3543         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3544         bsf = rte_bsf32(qpnum_per_tc);
3545
3546         /* Adjust the queue number to actual queues that can be applied */
3547         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3548                 vsi->nb_qps = qpnum_per_tc * total_tc;
3549
3550         /**
3551          * Configure TC and queue mapping parameters, for enabled TC,
3552          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3553          * default queue will serve it.
3554          */
3555         qp_idx = 0;
3556         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3557                 if (vsi->enabled_tc & (1 << i)) {
3558                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3559                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3560                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3561                         qp_idx += qpnum_per_tc;
3562                 } else
3563                         info->tc_mapping[i] = 0;
3564         }
3565
3566         /* Associate queue number with VSI */
3567         if (vsi->type == I40E_VSI_SRIOV) {
3568                 info->mapping_flags |=
3569                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3570                 for (i = 0; i < vsi->nb_qps; i++)
3571                         info->queue_mapping[i] =
3572                                 rte_cpu_to_le_16(vsi->base_queue + i);
3573         } else {
3574                 info->mapping_flags |=
3575                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3576                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3577         }
3578         info->valid_sections |=
3579                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3580
3581         return I40E_SUCCESS;
3582 }
3583
3584 static int
3585 i40e_veb_release(struct i40e_veb *veb)
3586 {
3587         struct i40e_vsi *vsi;
3588         struct i40e_hw *hw;
3589
3590         if (veb == NULL || veb->associate_vsi == NULL)
3591                 return -EINVAL;
3592
3593         if (!TAILQ_EMPTY(&veb->head)) {
3594                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3595                 return -EACCES;
3596         }
3597
3598         vsi = veb->associate_vsi;
3599         hw = I40E_VSI_TO_HW(vsi);
3600
3601         vsi->uplink_seid = veb->uplink_seid;
3602         i40e_aq_delete_element(hw, veb->seid, NULL);
3603         rte_free(veb);
3604         vsi->veb = NULL;
3605         return I40E_SUCCESS;
3606 }
3607
3608 /* Setup a veb */
3609 static struct i40e_veb *
3610 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3611 {
3612         struct i40e_veb *veb;
3613         int ret;
3614         struct i40e_hw *hw;
3615
3616         if (NULL == pf || vsi == NULL) {
3617                 PMD_DRV_LOG(ERR, "veb setup failed, "
3618                             "associated VSI shouldn't null");
3619                 return NULL;
3620         }
3621         hw = I40E_PF_TO_HW(pf);
3622
3623         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3624         if (!veb) {
3625                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3626                 goto fail;
3627         }
3628
3629         veb->associate_vsi = vsi;
3630         TAILQ_INIT(&veb->head);
3631         veb->uplink_seid = vsi->uplink_seid;
3632
3633         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3634                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3635
3636         if (ret != I40E_SUCCESS) {
3637                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3638                             hw->aq.asq_last_status);
3639                 goto fail;
3640         }
3641
3642         /* get statistics index */
3643         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3644                                 &veb->stats_idx, NULL, NULL, NULL);
3645         if (ret != I40E_SUCCESS) {
3646                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3647                             hw->aq.asq_last_status);
3648                 goto fail;
3649         }
3650
3651         /* Get VEB bandwidth, to be implemented */
3652         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3653         vsi->uplink_seid = veb->seid;
3654
3655         return veb;
3656 fail:
3657         rte_free(veb);
3658         return NULL;
3659 }
3660
3661 int
3662 i40e_vsi_release(struct i40e_vsi *vsi)
3663 {
3664         struct i40e_pf *pf;
3665         struct i40e_hw *hw;
3666         struct i40e_vsi_list *vsi_list;
3667         int ret;
3668         struct i40e_mac_filter *f;
3669
3670         if (!vsi)
3671                 return I40E_SUCCESS;
3672
3673         pf = I40E_VSI_TO_PF(vsi);
3674         hw = I40E_VSI_TO_HW(vsi);
3675
3676         /* VSI has child to attach, release child first */
3677         if (vsi->veb) {
3678                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3679                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3680                                 return -1;
3681                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3682                 }
3683                 i40e_veb_release(vsi->veb);
3684         }
3685
3686         /* Remove all macvlan filters of the VSI */
3687         i40e_vsi_remove_all_macvlan_filter(vsi);
3688         TAILQ_FOREACH(f, &vsi->mac_list, next)
3689                 rte_free(f);
3690
3691         if (vsi->type != I40E_VSI_MAIN) {
3692                 /* Remove vsi from parent's sibling list */
3693                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3694                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3695                         return I40E_ERR_PARAM;
3696                 }
3697                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3698                                 &vsi->sib_vsi_list, list);
3699
3700                 /* Remove all switch element of the VSI */
3701                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3702                 if (ret != I40E_SUCCESS)
3703                         PMD_DRV_LOG(ERR, "Failed to delete element");
3704         }
3705         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3706
3707         if (vsi->type != I40E_VSI_SRIOV)
3708                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3709         rte_free(vsi);
3710
3711         return I40E_SUCCESS;
3712 }
3713
3714 static int
3715 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3716 {
3717         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3718         struct i40e_aqc_remove_macvlan_element_data def_filter;
3719         struct i40e_mac_filter_info filter;
3720         int ret;
3721
3722         if (vsi->type != I40E_VSI_MAIN)
3723                 return I40E_ERR_CONFIG;
3724         memset(&def_filter, 0, sizeof(def_filter));
3725         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3726                                         ETH_ADDR_LEN);
3727         def_filter.vlan_tag = 0;
3728         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3729                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3730         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3731         if (ret != I40E_SUCCESS) {
3732                 struct i40e_mac_filter *f;
3733                 struct ether_addr *mac;
3734
3735                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3736                             "macvlan filter");
3737                 /* It needs to add the permanent mac into mac list */
3738                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3739                 if (f == NULL) {
3740                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3741                         return I40E_ERR_NO_MEMORY;
3742                 }
3743                 mac = &f->mac_info.mac_addr;
3744                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3745                                 ETH_ADDR_LEN);
3746                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3747                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3748                 vsi->mac_num++;
3749
3750                 return ret;
3751         }
3752         (void)rte_memcpy(&filter.mac_addr,
3753                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3754         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3755         return i40e_vsi_add_mac(vsi, &filter);
3756 }
3757
3758 #define I40E_3_BIT_MASK     0x7
3759 /*
3760  * i40e_vsi_get_bw_config - Query VSI BW Information
3761  * @vsi: the VSI to be queried
3762  *
3763  * Returns 0 on success, negative value on failure
3764  */
3765 static enum i40e_status_code
3766 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3767 {
3768         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3769         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3770         struct i40e_hw *hw = &vsi->adapter->hw;
3771         i40e_status ret;
3772         int i;
3773         uint32_t bw_max;
3774
3775         memset(&bw_config, 0, sizeof(bw_config));
3776         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3777         if (ret != I40E_SUCCESS) {
3778                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3779                             hw->aq.asq_last_status);
3780                 return ret;
3781         }
3782
3783         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3784         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3785                                         &ets_sla_config, NULL);
3786         if (ret != I40E_SUCCESS) {
3787                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3788                             "configuration %u", hw->aq.asq_last_status);
3789                 return ret;
3790         }
3791
3792         /* store and print out BW info */
3793         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3794         vsi->bw_info.bw_max = bw_config.max_bw;
3795         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3796         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3797         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3798                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3799                      I40E_16_BIT_WIDTH);
3800         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3801                 vsi->bw_info.bw_ets_share_credits[i] =
3802                                 ets_sla_config.share_credits[i];
3803                 vsi->bw_info.bw_ets_credits[i] =
3804                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3805                 /* 4 bits per TC, 4th bit is reserved */
3806                 vsi->bw_info.bw_ets_max[i] =
3807                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3808                                   I40E_3_BIT_MASK);
3809                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3810                             vsi->bw_info.bw_ets_share_credits[i]);
3811                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3812                             vsi->bw_info.bw_ets_credits[i]);
3813                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3814                             vsi->bw_info.bw_ets_max[i]);
3815         }
3816
3817         return I40E_SUCCESS;
3818 }
3819
3820 /* Setup a VSI */
3821 struct i40e_vsi *
3822 i40e_vsi_setup(struct i40e_pf *pf,
3823                enum i40e_vsi_type type,
3824                struct i40e_vsi *uplink_vsi,
3825                uint16_t user_param)
3826 {
3827         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3828         struct i40e_vsi *vsi;
3829         struct i40e_mac_filter_info filter;
3830         int ret;
3831         struct i40e_vsi_context ctxt;
3832         struct ether_addr broadcast =
3833                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3834
3835         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3836                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3837                             "VSI link shouldn't be NULL");
3838                 return NULL;
3839         }
3840
3841         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3842                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3843                             "uplink VSI should be NULL");
3844                 return NULL;
3845         }
3846
3847         /* If uplink vsi didn't setup VEB, create one first */
3848         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3849                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3850
3851                 if (NULL == uplink_vsi->veb) {
3852                         PMD_DRV_LOG(ERR, "VEB setup failed");
3853                         return NULL;
3854                 }
3855         }
3856
3857         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3858         if (!vsi) {
3859                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3860                 return NULL;
3861         }
3862         TAILQ_INIT(&vsi->mac_list);
3863         vsi->type = type;
3864         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3865         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3866         vsi->parent_vsi = uplink_vsi;
3867         vsi->user_param = user_param;
3868         /* Allocate queues */
3869         switch (vsi->type) {
3870         case I40E_VSI_MAIN  :
3871                 vsi->nb_qps = pf->lan_nb_qps;
3872                 break;
3873         case I40E_VSI_SRIOV :
3874                 vsi->nb_qps = pf->vf_nb_qps;
3875                 break;
3876         case I40E_VSI_VMDQ2:
3877                 vsi->nb_qps = pf->vmdq_nb_qps;
3878                 break;
3879         case I40E_VSI_FDIR:
3880                 vsi->nb_qps = pf->fdir_nb_qps;
3881                 break;
3882         default:
3883                 goto fail_mem;
3884         }
3885         /*
3886          * The filter status descriptor is reported in rx queue 0,
3887          * while the tx queue for fdir filter programming has no
3888          * such constraints, can be non-zero queues.
3889          * To simplify it, choose FDIR vsi use queue 0 pair.
3890          * To make sure it will use queue 0 pair, queue allocation
3891          * need be done before this function is called
3892          */
3893         if (type != I40E_VSI_FDIR) {
3894                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3895                         if (ret < 0) {
3896                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3897                                                 vsi->seid, ret);
3898                                 goto fail_mem;
3899                         }
3900                         vsi->base_queue = ret;
3901         } else
3902                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3903
3904         /* VF has MSIX interrupt in VF range, don't allocate here */
3905         if (type == I40E_VSI_MAIN) {
3906                 ret = i40e_res_pool_alloc(&pf->msix_pool,
3907                                           RTE_MIN(vsi->nb_qps,
3908                                                   RTE_MAX_RXTX_INTR_VEC_ID));
3909                 if (ret < 0) {
3910                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
3911                                     vsi->seid, ret);
3912                         goto fail_queue_alloc;
3913                 }
3914                 vsi->msix_intr = ret;
3915                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
3916         } else if (type != I40E_VSI_SRIOV) {
3917                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3918                 if (ret < 0) {
3919                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3920                         goto fail_queue_alloc;
3921                 }
3922                 vsi->msix_intr = ret;
3923                 vsi->nb_msix = 1;
3924         } else {
3925                 vsi->msix_intr = 0;
3926                 vsi->nb_msix = 0;
3927         }
3928
3929         /* Add VSI */
3930         if (type == I40E_VSI_MAIN) {
3931                 /* For main VSI, no need to add since it's default one */
3932                 vsi->uplink_seid = pf->mac_seid;
3933                 vsi->seid = pf->main_vsi_seid;
3934                 /* Bind queues with specific MSIX interrupt */
3935                 /**
3936                  * Needs 2 interrupt at least, one for misc cause which will
3937                  * enabled from OS side, Another for queues binding the
3938                  * interrupt from device side only.
3939                  */
3940
3941                 /* Get default VSI parameters from hardware */
3942                 memset(&ctxt, 0, sizeof(ctxt));
3943                 ctxt.seid = vsi->seid;
3944                 ctxt.pf_num = hw->pf_id;
3945                 ctxt.uplink_seid = vsi->uplink_seid;
3946                 ctxt.vf_num = 0;
3947                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3948                 if (ret != I40E_SUCCESS) {
3949                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3950                         goto fail_msix_alloc;
3951                 }
3952                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3953                         sizeof(struct i40e_aqc_vsi_properties_data));
3954                 vsi->vsi_id = ctxt.vsi_number;
3955                 vsi->info.valid_sections = 0;
3956
3957                 /* Configure tc, enabled TC0 only */
3958                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3959                         I40E_SUCCESS) {
3960                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3961                         goto fail_msix_alloc;
3962                 }
3963
3964                 /* TC, queue mapping */
3965                 memset(&ctxt, 0, sizeof(ctxt));
3966                 vsi->info.valid_sections |=
3967                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3968                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3969                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3970                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3971                         sizeof(struct i40e_aqc_vsi_properties_data));
3972                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3973                                                 I40E_DEFAULT_TCMAP);
3974                 if (ret != I40E_SUCCESS) {
3975                         PMD_DRV_LOG(ERR, "Failed to configure "
3976                                     "TC queue mapping");
3977                         goto fail_msix_alloc;
3978                 }
3979                 ctxt.seid = vsi->seid;
3980                 ctxt.pf_num = hw->pf_id;
3981                 ctxt.uplink_seid = vsi->uplink_seid;
3982                 ctxt.vf_num = 0;
3983
3984                 /* Update VSI parameters */
3985                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3986                 if (ret != I40E_SUCCESS) {
3987                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3988                         goto fail_msix_alloc;
3989                 }
3990
3991                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3992                                                 sizeof(vsi->info.tc_mapping));
3993                 (void)rte_memcpy(&vsi->info.queue_mapping,
3994                                 &ctxt.info.queue_mapping,
3995                         sizeof(vsi->info.queue_mapping));
3996                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3997                 vsi->info.valid_sections = 0;
3998
3999                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4000                                 ETH_ADDR_LEN);
4001
4002                 /**
4003                  * Updating default filter settings are necessary to prevent
4004                  * reception of tagged packets.
4005                  * Some old firmware configurations load a default macvlan
4006                  * filter which accepts both tagged and untagged packets.
4007                  * The updating is to use a normal filter instead if needed.
4008                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4009                  * The firmware with correct configurations load the default
4010                  * macvlan filter which is expected and cannot be removed.
4011                  */
4012                 i40e_update_default_filter_setting(vsi);
4013                 i40e_config_qinq(hw, vsi);
4014         } else if (type == I40E_VSI_SRIOV) {
4015                 memset(&ctxt, 0, sizeof(ctxt));
4016                 /**
4017                  * For other VSI, the uplink_seid equals to uplink VSI's
4018                  * uplink_seid since they share same VEB
4019                  */
4020                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4021                 ctxt.pf_num = hw->pf_id;
4022                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4023                 ctxt.uplink_seid = vsi->uplink_seid;
4024                 ctxt.connection_type = 0x1;
4025                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4026
4027                 /**
4028                  * Do not configure switch ID to enable VEB switch by
4029                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
4030                  * if the source mac address of packet sent from VF is not
4031                  * listed in the VEB's mac table, the VEB will switch the
4032                  * packet back to the VF. Need to enable it when HW issue
4033                  * is fixed.
4034                  */
4035
4036                 /* Configure port/vlan */
4037                 ctxt.info.valid_sections |=
4038                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4039                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4040                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4041                                                 I40E_DEFAULT_TCMAP);
4042                 if (ret != I40E_SUCCESS) {
4043                         PMD_DRV_LOG(ERR, "Failed to configure "
4044                                     "TC queue mapping");
4045                         goto fail_msix_alloc;
4046                 }
4047                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4048                 ctxt.info.valid_sections |=
4049                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4050                 /**
4051                  * Since VSI is not created yet, only configure parameter,
4052                  * will add vsi below.
4053                  */
4054
4055                 i40e_config_qinq(hw, vsi);
4056         } else if (type == I40E_VSI_VMDQ2) {
4057                 memset(&ctxt, 0, sizeof(ctxt));
4058                 /*
4059                  * For other VSI, the uplink_seid equals to uplink VSI's
4060                  * uplink_seid since they share same VEB
4061                  */
4062                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4063                 ctxt.pf_num = hw->pf_id;
4064                 ctxt.vf_num = 0;
4065                 ctxt.uplink_seid = vsi->uplink_seid;
4066                 ctxt.connection_type = 0x1;
4067                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4068
4069                 ctxt.info.valid_sections |=
4070                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4071                 /* user_param carries flag to enable loop back */
4072                 if (user_param) {
4073                         ctxt.info.switch_id =
4074                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4075                         ctxt.info.switch_id |=
4076                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4077                 }
4078
4079                 /* Configure port/vlan */
4080                 ctxt.info.valid_sections |=
4081                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4082                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4083                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4084                                                 I40E_DEFAULT_TCMAP);
4085                 if (ret != I40E_SUCCESS) {
4086                         PMD_DRV_LOG(ERR, "Failed to configure "
4087                                         "TC queue mapping");
4088                         goto fail_msix_alloc;
4089                 }
4090                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4091                 ctxt.info.valid_sections |=
4092                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4093         } else if (type == I40E_VSI_FDIR) {
4094                 memset(&ctxt, 0, sizeof(ctxt));
4095                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4096                 ctxt.pf_num = hw->pf_id;
4097                 ctxt.vf_num = 0;
4098                 ctxt.uplink_seid = vsi->uplink_seid;
4099                 ctxt.connection_type = 0x1;     /* regular data port */
4100                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4101                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4102                                                 I40E_DEFAULT_TCMAP);
4103                 if (ret != I40E_SUCCESS) {
4104                         PMD_DRV_LOG(ERR, "Failed to configure "
4105                                         "TC queue mapping.");
4106                         goto fail_msix_alloc;
4107                 }
4108                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4109                 ctxt.info.valid_sections |=
4110                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4111         } else {
4112                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4113                 goto fail_msix_alloc;
4114         }
4115
4116         if (vsi->type != I40E_VSI_MAIN) {
4117                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4118                 if (ret != I40E_SUCCESS) {
4119                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4120                                     hw->aq.asq_last_status);
4121                         goto fail_msix_alloc;
4122                 }
4123                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4124                 vsi->info.valid_sections = 0;
4125                 vsi->seid = ctxt.seid;
4126                 vsi->vsi_id = ctxt.vsi_number;
4127                 vsi->sib_vsi_list.vsi = vsi;
4128                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4129                                 &vsi->sib_vsi_list, list);
4130         }
4131
4132         /* MAC/VLAN configuration */
4133         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4134         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4135
4136         ret = i40e_vsi_add_mac(vsi, &filter);
4137         if (ret != I40E_SUCCESS) {
4138                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4139                 goto fail_msix_alloc;
4140         }
4141
4142         /* Get VSI BW information */
4143         i40e_vsi_get_bw_config(vsi);
4144         return vsi;
4145 fail_msix_alloc:
4146         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4147 fail_queue_alloc:
4148         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4149 fail_mem:
4150         rte_free(vsi);
4151         return NULL;
4152 }
4153
4154 /* Configure vlan stripping on or off */
4155 int
4156 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4157 {
4158         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4159         struct i40e_vsi_context ctxt;
4160         uint8_t vlan_flags;
4161         int ret = I40E_SUCCESS;
4162
4163         /* Check if it has been already on or off */
4164         if (vsi->info.valid_sections &
4165                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4166                 if (on) {
4167                         if ((vsi->info.port_vlan_flags &
4168                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4169                                 return 0; /* already on */
4170                 } else {
4171                         if ((vsi->info.port_vlan_flags &
4172                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4173                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4174                                 return 0; /* already off */
4175                 }
4176         }
4177
4178         if (on)
4179                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4180         else
4181                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4182         vsi->info.valid_sections =
4183                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4184         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4185         vsi->info.port_vlan_flags |= vlan_flags;
4186         ctxt.seid = vsi->seid;
4187         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4188         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4189         if (ret)
4190                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4191                             on ? "enable" : "disable");
4192
4193         return ret;
4194 }
4195
4196 static int
4197 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4198 {
4199         struct rte_eth_dev_data *data = dev->data;
4200         int ret;
4201
4202         /* Apply vlan offload setting */
4203         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
4204
4205         /* Apply double-vlan setting, not implemented yet */
4206
4207         /* Apply pvid setting */
4208         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4209                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4210         if (ret)
4211                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4212
4213         return ret;
4214 }
4215
4216 static int
4217 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4218 {
4219         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4220
4221         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4222 }
4223
4224 static int
4225 i40e_update_flow_control(struct i40e_hw *hw)
4226 {
4227 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4228         struct i40e_link_status link_status;
4229         uint32_t rxfc = 0, txfc = 0, reg;
4230         uint8_t an_info;
4231         int ret;
4232
4233         memset(&link_status, 0, sizeof(link_status));
4234         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4235         if (ret != I40E_SUCCESS) {
4236                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4237                 goto write_reg; /* Disable flow control */
4238         }
4239
4240         an_info = hw->phy.link_info.an_info;
4241         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4242                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4243                 ret = I40E_ERR_NOT_READY;
4244                 goto write_reg; /* Disable flow control */
4245         }
4246         /**
4247          * If link auto negotiation is enabled, flow control needs to
4248          * be configured according to it
4249          */
4250         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4251         case I40E_LINK_PAUSE_RXTX:
4252                 rxfc = 1;
4253                 txfc = 1;
4254                 hw->fc.current_mode = I40E_FC_FULL;
4255                 break;
4256         case I40E_AQ_LINK_PAUSE_RX:
4257                 rxfc = 1;
4258                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4259                 break;
4260         case I40E_AQ_LINK_PAUSE_TX:
4261                 txfc = 1;
4262                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4263                 break;
4264         default:
4265                 hw->fc.current_mode = I40E_FC_NONE;
4266                 break;
4267         }
4268
4269 write_reg:
4270         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4271                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4272         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4273         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4274         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4275         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4276
4277         return ret;
4278 }
4279
4280 /* PF setup */
4281 static int
4282 i40e_pf_setup(struct i40e_pf *pf)
4283 {
4284         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4285         struct i40e_filter_control_settings settings;
4286         struct i40e_vsi *vsi;
4287         int ret;
4288
4289         /* Clear all stats counters */
4290         pf->offset_loaded = FALSE;
4291         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4292         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4293
4294         ret = i40e_pf_get_switch_config(pf);
4295         if (ret != I40E_SUCCESS) {
4296                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4297                 return ret;
4298         }
4299         if (pf->flags & I40E_FLAG_FDIR) {
4300                 /* make queue allocated first, let FDIR use queue pair 0*/
4301                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4302                 if (ret != I40E_FDIR_QUEUE_ID) {
4303                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4304                                     " ret =%d", ret);
4305                         pf->flags &= ~I40E_FLAG_FDIR;
4306                 }
4307         }
4308         /*  main VSI setup */
4309         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4310         if (!vsi) {
4311                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4312                 return I40E_ERR_NOT_READY;
4313         }
4314         pf->main_vsi = vsi;
4315
4316         /* Configure filter control */
4317         memset(&settings, 0, sizeof(settings));
4318         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4319                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4320         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4321                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4322         else {
4323                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4324                                                 hw->func_caps.rss_table_size);
4325                 return I40E_ERR_PARAM;
4326         }
4327         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4328                         "size: %u\n", hw->func_caps.rss_table_size);
4329         pf->hash_lut_size = hw->func_caps.rss_table_size;
4330
4331         /* Enable ethtype and macvlan filters */
4332         settings.enable_ethtype = TRUE;
4333         settings.enable_macvlan = TRUE;
4334         ret = i40e_set_filter_control(hw, &settings);
4335         if (ret)
4336                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4337                                                                 ret);
4338
4339         /* Update flow control according to the auto negotiation */
4340         i40e_update_flow_control(hw);
4341
4342         return I40E_SUCCESS;
4343 }
4344
4345 int
4346 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4347 {
4348         uint32_t reg;
4349         uint16_t j;
4350
4351         /**
4352          * Set or clear TX Queue Disable flags,
4353          * which is required by hardware.
4354          */
4355         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4356         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4357
4358         /* Wait until the request is finished */
4359         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4360                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4361                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4362                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4363                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4364                                                         & 0x1))) {
4365                         break;
4366                 }
4367         }
4368         if (on) {
4369                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4370                         return I40E_SUCCESS; /* already on, skip next steps */
4371
4372                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4373                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4374         } else {
4375                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4376                         return I40E_SUCCESS; /* already off, skip next steps */
4377                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4378         }
4379         /* Write the register */
4380         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4381         /* Check the result */
4382         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4383                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4384                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4385                 if (on) {
4386                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4387                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4388                                 break;
4389                 } else {
4390                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4391                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4392                                 break;
4393                 }
4394         }
4395         /* Check if it is timeout */
4396         if (j >= I40E_CHK_Q_ENA_COUNT) {
4397                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4398                             (on ? "enable" : "disable"), q_idx);
4399                 return I40E_ERR_TIMEOUT;
4400         }
4401
4402         return I40E_SUCCESS;
4403 }
4404
4405 /* Swith on or off the tx queues */
4406 static int
4407 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4408 {
4409         struct rte_eth_dev_data *dev_data = pf->dev_data;
4410         struct i40e_tx_queue *txq;
4411         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4412         uint16_t i;
4413         int ret;
4414
4415         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4416                 txq = dev_data->tx_queues[i];
4417                 /* Don't operate the queue if not configured or
4418                  * if starting only per queue */
4419                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4420                         continue;
4421                 if (on)
4422                         ret = i40e_dev_tx_queue_start(dev, i);
4423                 else
4424                         ret = i40e_dev_tx_queue_stop(dev, i);
4425                 if ( ret != I40E_SUCCESS)
4426                         return ret;
4427         }
4428
4429         return I40E_SUCCESS;
4430 }
4431
4432 int
4433 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4434 {
4435         uint32_t reg;
4436         uint16_t j;
4437
4438         /* Wait until the request is finished */
4439         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4440                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4441                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4442                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4443                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4444                         break;
4445         }
4446
4447         if (on) {
4448                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4449                         return I40E_SUCCESS; /* Already on, skip next steps */
4450                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4451         } else {
4452                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4453                         return I40E_SUCCESS; /* Already off, skip next steps */
4454                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4455         }
4456
4457         /* Write the register */
4458         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4459         /* Check the result */
4460         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4461                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4462                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4463                 if (on) {
4464                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4465                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4466                                 break;
4467                 } else {
4468                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4469                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4470                                 break;
4471                 }
4472         }
4473
4474         /* Check if it is timeout */
4475         if (j >= I40E_CHK_Q_ENA_COUNT) {
4476                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4477                             (on ? "enable" : "disable"), q_idx);
4478                 return I40E_ERR_TIMEOUT;
4479         }
4480
4481         return I40E_SUCCESS;
4482 }
4483 /* Switch on or off the rx queues */
4484 static int
4485 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4486 {
4487         struct rte_eth_dev_data *dev_data = pf->dev_data;
4488         struct i40e_rx_queue *rxq;
4489         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4490         uint16_t i;
4491         int ret;
4492
4493         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4494                 rxq = dev_data->rx_queues[i];
4495                 /* Don't operate the queue if not configured or
4496                  * if starting only per queue */
4497                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4498                         continue;
4499                 if (on)
4500                         ret = i40e_dev_rx_queue_start(dev, i);
4501                 else
4502                         ret = i40e_dev_rx_queue_stop(dev, i);
4503                 if (ret != I40E_SUCCESS)
4504                         return ret;
4505         }
4506
4507         return I40E_SUCCESS;
4508 }
4509
4510 /* Switch on or off all the rx/tx queues */
4511 int
4512 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4513 {
4514         int ret;
4515
4516         if (on) {
4517                 /* enable rx queues before enabling tx queues */
4518                 ret = i40e_dev_switch_rx_queues(pf, on);
4519                 if (ret) {
4520                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4521                         return ret;
4522                 }
4523                 ret = i40e_dev_switch_tx_queues(pf, on);
4524         } else {
4525                 /* Stop tx queues before stopping rx queues */
4526                 ret = i40e_dev_switch_tx_queues(pf, on);
4527                 if (ret) {
4528                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4529                         return ret;
4530                 }
4531                 ret = i40e_dev_switch_rx_queues(pf, on);
4532         }
4533
4534         return ret;
4535 }
4536
4537 /* Initialize VSI for TX */
4538 static int
4539 i40e_dev_tx_init(struct i40e_pf *pf)
4540 {
4541         struct rte_eth_dev_data *data = pf->dev_data;
4542         uint16_t i;
4543         uint32_t ret = I40E_SUCCESS;
4544         struct i40e_tx_queue *txq;
4545
4546         for (i = 0; i < data->nb_tx_queues; i++) {
4547                 txq = data->tx_queues[i];
4548                 if (!txq || !txq->q_set)
4549                         continue;
4550                 ret = i40e_tx_queue_init(txq);
4551                 if (ret != I40E_SUCCESS)
4552                         break;
4553         }
4554         if (ret == I40E_SUCCESS)
4555                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4556                                      ->eth_dev);
4557
4558         return ret;
4559 }
4560
4561 /* Initialize VSI for RX */
4562 static int
4563 i40e_dev_rx_init(struct i40e_pf *pf)
4564 {
4565         struct rte_eth_dev_data *data = pf->dev_data;
4566         int ret = I40E_SUCCESS;
4567         uint16_t i;
4568         struct i40e_rx_queue *rxq;
4569
4570         i40e_pf_config_mq_rx(pf);
4571         for (i = 0; i < data->nb_rx_queues; i++) {
4572                 rxq = data->rx_queues[i];
4573                 if (!rxq || !rxq->q_set)
4574                         continue;
4575
4576                 ret = i40e_rx_queue_init(rxq);
4577                 if (ret != I40E_SUCCESS) {
4578                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4579                                     "initialization");
4580                         break;
4581                 }
4582         }
4583         if (ret == I40E_SUCCESS)
4584                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4585                                      ->eth_dev);
4586
4587         return ret;
4588 }
4589
4590 static int
4591 i40e_dev_rxtx_init(struct i40e_pf *pf)
4592 {
4593         int err;
4594
4595         err = i40e_dev_tx_init(pf);
4596         if (err) {
4597                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4598                 return err;
4599         }
4600         err = i40e_dev_rx_init(pf);
4601         if (err) {
4602                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4603                 return err;
4604         }
4605
4606         return err;
4607 }
4608
4609 static int
4610 i40e_vmdq_setup(struct rte_eth_dev *dev)
4611 {
4612         struct rte_eth_conf *conf = &dev->data->dev_conf;
4613         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4614         int i, err, conf_vsis, j, loop;
4615         struct i40e_vsi *vsi;
4616         struct i40e_vmdq_info *vmdq_info;
4617         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4618         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4619
4620         /*
4621          * Disable interrupt to avoid message from VF. Furthermore, it will
4622          * avoid race condition in VSI creation/destroy.
4623          */
4624         i40e_pf_disable_irq0(hw);
4625
4626         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4627                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4628                 return -ENOTSUP;
4629         }
4630
4631         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4632         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4633                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4634                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4635                         pf->max_nb_vmdq_vsi);
4636                 return -ENOTSUP;
4637         }
4638
4639         if (pf->vmdq != NULL) {
4640                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4641                 return 0;
4642         }
4643
4644         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4645                                 sizeof(*vmdq_info) * conf_vsis, 0);
4646
4647         if (pf->vmdq == NULL) {
4648                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4649                 return -ENOMEM;
4650         }
4651
4652         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4653
4654         /* Create VMDQ VSI */
4655         for (i = 0; i < conf_vsis; i++) {
4656                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4657                                 vmdq_conf->enable_loop_back);
4658                 if (vsi == NULL) {
4659                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4660                         err = -1;
4661                         goto err_vsi_setup;
4662                 }
4663                 vmdq_info = &pf->vmdq[i];
4664                 vmdq_info->pf = pf;
4665                 vmdq_info->vsi = vsi;
4666         }
4667         pf->nb_cfg_vmdq_vsi = conf_vsis;
4668
4669         /* Configure Vlan */
4670         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4671         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4672                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4673                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4674                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4675                                         vmdq_conf->pool_map[i].vlan_id, j);
4676
4677                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4678                                                 vmdq_conf->pool_map[i].vlan_id);
4679                                 if (err) {
4680                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4681                                         err = -1;
4682                                         goto err_vsi_setup;
4683                                 }
4684                         }
4685                 }
4686         }
4687
4688         i40e_pf_enable_irq0(hw);
4689
4690         return 0;
4691
4692 err_vsi_setup:
4693         for (i = 0; i < conf_vsis; i++)
4694                 if (pf->vmdq[i].vsi == NULL)
4695                         break;
4696                 else
4697                         i40e_vsi_release(pf->vmdq[i].vsi);
4698
4699         rte_free(pf->vmdq);
4700         pf->vmdq = NULL;
4701         i40e_pf_enable_irq0(hw);
4702         return err;
4703 }
4704
4705 static void
4706 i40e_stat_update_32(struct i40e_hw *hw,
4707                    uint32_t reg,
4708                    bool offset_loaded,
4709                    uint64_t *offset,
4710                    uint64_t *stat)
4711 {
4712         uint64_t new_data;
4713
4714         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4715         if (!offset_loaded)
4716                 *offset = new_data;
4717
4718         if (new_data >= *offset)
4719                 *stat = (uint64_t)(new_data - *offset);
4720         else
4721                 *stat = (uint64_t)((new_data +
4722                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4723 }
4724
4725 static void
4726 i40e_stat_update_48(struct i40e_hw *hw,
4727                    uint32_t hireg,
4728                    uint32_t loreg,
4729                    bool offset_loaded,
4730                    uint64_t *offset,
4731                    uint64_t *stat)
4732 {
4733         uint64_t new_data;
4734
4735         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4736         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4737                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4738
4739         if (!offset_loaded)
4740                 *offset = new_data;
4741
4742         if (new_data >= *offset)
4743                 *stat = new_data - *offset;
4744         else
4745                 *stat = (uint64_t)((new_data +
4746                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4747
4748         *stat &= I40E_48_BIT_MASK;
4749 }
4750
4751 /* Disable IRQ0 */
4752 void
4753 i40e_pf_disable_irq0(struct i40e_hw *hw)
4754 {
4755         /* Disable all interrupt types */
4756         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4757         I40E_WRITE_FLUSH(hw);
4758 }
4759
4760 /* Enable IRQ0 */
4761 void
4762 i40e_pf_enable_irq0(struct i40e_hw *hw)
4763 {
4764         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4765                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4766                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4767                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4768         I40E_WRITE_FLUSH(hw);
4769 }
4770
4771 static void
4772 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4773 {
4774         /* read pending request and disable first */
4775         i40e_pf_disable_irq0(hw);
4776         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4777         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4778                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4779
4780         if (no_queue)
4781                 /* Link no queues with irq0 */
4782                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4783                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4784 }
4785
4786 static void
4787 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4788 {
4789         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4790         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4791         int i;
4792         uint16_t abs_vf_id;
4793         uint32_t index, offset, val;
4794
4795         if (!pf->vfs)
4796                 return;
4797         /**
4798          * Try to find which VF trigger a reset, use absolute VF id to access
4799          * since the reg is global register.
4800          */
4801         for (i = 0; i < pf->vf_num; i++) {
4802                 abs_vf_id = hw->func_caps.vf_base_id + i;
4803                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4804                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4805                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4806                 /* VFR event occured */
4807                 if (val & (0x1 << offset)) {
4808                         int ret;
4809
4810                         /* Clear the event first */
4811                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4812                                                         (0x1 << offset));
4813                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4814                         /**
4815                          * Only notify a VF reset event occured,
4816                          * don't trigger another SW reset
4817                          */
4818                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4819                         if (ret != I40E_SUCCESS)
4820                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4821                 }
4822         }
4823 }
4824
4825 static void
4826 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4827 {
4828         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4829         struct i40e_arq_event_info info;
4830         uint16_t pending, opcode;
4831         int ret;
4832
4833         info.buf_len = I40E_AQ_BUF_SZ;
4834         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4835         if (!info.msg_buf) {
4836                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4837                 return;
4838         }
4839
4840         pending = 1;
4841         while (pending) {
4842                 ret = i40e_clean_arq_element(hw, &info, &pending);
4843
4844                 if (ret != I40E_SUCCESS) {
4845                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4846                                     "aq_err: %u", hw->aq.asq_last_status);
4847                         break;
4848                 }
4849                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4850
4851                 switch (opcode) {
4852                 case i40e_aqc_opc_send_msg_to_pf:
4853                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4854                         i40e_pf_host_handle_vf_msg(dev,
4855                                         rte_le_to_cpu_16(info.desc.retval),
4856                                         rte_le_to_cpu_32(info.desc.cookie_high),
4857                                         rte_le_to_cpu_32(info.desc.cookie_low),
4858                                         info.msg_buf,
4859                                         info.msg_len);
4860                         break;
4861                 default:
4862                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4863                                     opcode);
4864                         break;
4865                 }
4866         }
4867         rte_free(info.msg_buf);
4868 }
4869
4870 /*
4871  * Interrupt handler is registered as the alarm callback for handling LSC
4872  * interrupt in a definite of time, in order to wait the NIC into a stable
4873  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4874  * no need for link down interrupt.
4875  */
4876 static void
4877 i40e_dev_interrupt_delayed_handler(void *param)
4878 {
4879         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4880         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4881         uint32_t icr0;
4882
4883         /* read interrupt causes again */
4884         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4885
4886 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4887         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4888                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4889         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4890                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4891         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4892                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4893         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4894                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4895         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4896                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4897                                                                 "state\n");
4898         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4899                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4900         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4901                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4902 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4903
4904         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4905                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4906                 i40e_dev_handle_vfr_event(dev);
4907         }
4908         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4909                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4910                 i40e_dev_handle_aq_msg(dev);
4911         }
4912
4913         /* handle the link up interrupt in an alarm callback */
4914         i40e_dev_link_update(dev, 0);
4915         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4916
4917         i40e_pf_enable_irq0(hw);
4918         rte_intr_enable(&(dev->pci_dev->intr_handle));
4919 }
4920
4921 /**
4922  * Interrupt handler triggered by NIC  for handling
4923  * specific interrupt.
4924  *
4925  * @param handle
4926  *  Pointer to interrupt handle.
4927  * @param param
4928  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4929  *
4930  * @return
4931  *  void
4932  */
4933 static void
4934 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4935                            void *param)
4936 {
4937         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4938         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4939         uint32_t icr0;
4940
4941         /* Disable interrupt */
4942         i40e_pf_disable_irq0(hw);
4943
4944         /* read out interrupt causes */
4945         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4946
4947         /* No interrupt event indicated */
4948         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4949                 PMD_DRV_LOG(INFO, "No interrupt event");
4950                 goto done;
4951         }
4952 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4953         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4954                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4955         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4956                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4957         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4958                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4959         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4960                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4961         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4962                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4963         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4964                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4965         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4966                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4967 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4968
4969         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4970                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4971                 i40e_dev_handle_vfr_event(dev);
4972         }
4973         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4974                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4975                 i40e_dev_handle_aq_msg(dev);
4976         }
4977
4978         /* Link Status Change interrupt */
4979         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4980 #define I40E_US_PER_SECOND 1000000
4981                 struct rte_eth_link link;
4982
4983                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4984                 memset(&link, 0, sizeof(link));
4985                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4986                 i40e_dev_link_update(dev, 0);
4987
4988                 /*
4989                  * For link up interrupt, it needs to wait 1 second to let the
4990                  * hardware be a stable state. Otherwise several consecutive
4991                  * interrupts can be observed.
4992                  * For link down interrupt, no need to wait.
4993                  */
4994                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4995                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4996                         return;
4997                 else
4998                         _rte_eth_dev_callback_process(dev,
4999                                 RTE_ETH_EVENT_INTR_LSC);
5000         }
5001
5002 done:
5003         /* Enable interrupt */
5004         i40e_pf_enable_irq0(hw);
5005         rte_intr_enable(&(dev->pci_dev->intr_handle));
5006 }
5007
5008 static int
5009 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5010                          struct i40e_macvlan_filter *filter,
5011                          int total)
5012 {
5013         int ele_num, ele_buff_size;
5014         int num, actual_num, i;
5015         uint16_t flags;
5016         int ret = I40E_SUCCESS;
5017         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5018         struct i40e_aqc_add_macvlan_element_data *req_list;
5019
5020         if (filter == NULL  || total == 0)
5021                 return I40E_ERR_PARAM;
5022         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5023         ele_buff_size = hw->aq.asq_buf_size;
5024
5025         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5026         if (req_list == NULL) {
5027                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5028                 return I40E_ERR_NO_MEMORY;
5029         }
5030
5031         num = 0;
5032         do {
5033                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5034                 memset(req_list, 0, ele_buff_size);
5035
5036                 for (i = 0; i < actual_num; i++) {
5037                         (void)rte_memcpy(req_list[i].mac_addr,
5038                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5039                         req_list[i].vlan_tag =
5040                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5041
5042                         switch (filter[num + i].filter_type) {
5043                         case RTE_MAC_PERFECT_MATCH:
5044                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5045                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5046                                 break;
5047                         case RTE_MACVLAN_PERFECT_MATCH:
5048                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5049                                 break;
5050                         case RTE_MAC_HASH_MATCH:
5051                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5052                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5053                                 break;
5054                         case RTE_MACVLAN_HASH_MATCH:
5055                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5056                                 break;
5057                         default:
5058                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5059                                 ret = I40E_ERR_PARAM;
5060                                 goto DONE;
5061                         }
5062
5063                         req_list[i].queue_number = 0;
5064
5065                         req_list[i].flags = rte_cpu_to_le_16(flags);
5066                 }
5067
5068                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5069                                                 actual_num, NULL);
5070                 if (ret != I40E_SUCCESS) {
5071                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5072                         goto DONE;
5073                 }
5074                 num += actual_num;
5075         } while (num < total);
5076
5077 DONE:
5078         rte_free(req_list);
5079         return ret;
5080 }
5081
5082 static int
5083 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5084                             struct i40e_macvlan_filter *filter,
5085                             int total)
5086 {
5087         int ele_num, ele_buff_size;
5088         int num, actual_num, i;
5089         uint16_t flags;
5090         int ret = I40E_SUCCESS;
5091         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5092         struct i40e_aqc_remove_macvlan_element_data *req_list;
5093
5094         if (filter == NULL  || total == 0)
5095                 return I40E_ERR_PARAM;
5096
5097         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5098         ele_buff_size = hw->aq.asq_buf_size;
5099
5100         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5101         if (req_list == NULL) {
5102                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5103                 return I40E_ERR_NO_MEMORY;
5104         }
5105
5106         num = 0;
5107         do {
5108                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5109                 memset(req_list, 0, ele_buff_size);
5110
5111                 for (i = 0; i < actual_num; i++) {
5112                         (void)rte_memcpy(req_list[i].mac_addr,
5113                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5114                         req_list[i].vlan_tag =
5115                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5116
5117                         switch (filter[num + i].filter_type) {
5118                         case RTE_MAC_PERFECT_MATCH:
5119                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5120                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5121                                 break;
5122                         case RTE_MACVLAN_PERFECT_MATCH:
5123                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5124                                 break;
5125                         case RTE_MAC_HASH_MATCH:
5126                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5127                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5128                                 break;
5129                         case RTE_MACVLAN_HASH_MATCH:
5130                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5131                                 break;
5132                         default:
5133                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5134                                 ret = I40E_ERR_PARAM;
5135                                 goto DONE;
5136                         }
5137                         req_list[i].flags = rte_cpu_to_le_16(flags);
5138                 }
5139
5140                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5141                                                 actual_num, NULL);
5142                 if (ret != I40E_SUCCESS) {
5143                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5144                         goto DONE;
5145                 }
5146                 num += actual_num;
5147         } while (num < total);
5148
5149 DONE:
5150         rte_free(req_list);
5151         return ret;
5152 }
5153
5154 /* Find out specific MAC filter */
5155 static struct i40e_mac_filter *
5156 i40e_find_mac_filter(struct i40e_vsi *vsi,
5157                          struct ether_addr *macaddr)
5158 {
5159         struct i40e_mac_filter *f;
5160
5161         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5162                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5163                         return f;
5164         }
5165
5166         return NULL;
5167 }
5168
5169 static bool
5170 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5171                          uint16_t vlan_id)
5172 {
5173         uint32_t vid_idx, vid_bit;
5174
5175         if (vlan_id > ETH_VLAN_ID_MAX)
5176                 return 0;
5177
5178         vid_idx = I40E_VFTA_IDX(vlan_id);
5179         vid_bit = I40E_VFTA_BIT(vlan_id);
5180
5181         if (vsi->vfta[vid_idx] & vid_bit)
5182                 return 1;
5183         else
5184                 return 0;
5185 }
5186
5187 static void
5188 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5189                          uint16_t vlan_id, bool on)
5190 {
5191         uint32_t vid_idx, vid_bit;
5192
5193         if (vlan_id > ETH_VLAN_ID_MAX)
5194                 return;
5195
5196         vid_idx = I40E_VFTA_IDX(vlan_id);
5197         vid_bit = I40E_VFTA_BIT(vlan_id);
5198
5199         if (on)
5200                 vsi->vfta[vid_idx] |= vid_bit;
5201         else
5202                 vsi->vfta[vid_idx] &= ~vid_bit;
5203 }
5204
5205 /**
5206  * Find all vlan options for specific mac addr,
5207  * return with actual vlan found.
5208  */
5209 static inline int
5210 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5211                            struct i40e_macvlan_filter *mv_f,
5212                            int num, struct ether_addr *addr)
5213 {
5214         int i;
5215         uint32_t j, k;
5216
5217         /**
5218          * Not to use i40e_find_vlan_filter to decrease the loop time,
5219          * although the code looks complex.
5220           */
5221         if (num < vsi->vlan_num)
5222                 return I40E_ERR_PARAM;
5223
5224         i = 0;
5225         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5226                 if (vsi->vfta[j]) {
5227                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5228                                 if (vsi->vfta[j] & (1 << k)) {
5229                                         if (i > num - 1) {
5230                                                 PMD_DRV_LOG(ERR, "vlan number "
5231                                                             "not match");
5232                                                 return I40E_ERR_PARAM;
5233                                         }
5234                                         (void)rte_memcpy(&mv_f[i].macaddr,
5235                                                         addr, ETH_ADDR_LEN);
5236                                         mv_f[i].vlan_id =
5237                                                 j * I40E_UINT32_BIT_SIZE + k;
5238                                         i++;
5239                                 }
5240                         }
5241                 }
5242         }
5243         return I40E_SUCCESS;
5244 }
5245
5246 static inline int
5247 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5248                            struct i40e_macvlan_filter *mv_f,
5249                            int num,
5250                            uint16_t vlan)
5251 {
5252         int i = 0;
5253         struct i40e_mac_filter *f;
5254
5255         if (num < vsi->mac_num)
5256                 return I40E_ERR_PARAM;
5257
5258         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5259                 if (i > num - 1) {
5260                         PMD_DRV_LOG(ERR, "buffer number not match");
5261                         return I40E_ERR_PARAM;
5262                 }
5263                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5264                                 ETH_ADDR_LEN);
5265                 mv_f[i].vlan_id = vlan;
5266                 mv_f[i].filter_type = f->mac_info.filter_type;
5267                 i++;
5268         }
5269
5270         return I40E_SUCCESS;
5271 }
5272
5273 static int
5274 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5275 {
5276         int i, num;
5277         struct i40e_mac_filter *f;
5278         struct i40e_macvlan_filter *mv_f;
5279         int ret = I40E_SUCCESS;
5280
5281         if (vsi == NULL || vsi->mac_num == 0)
5282                 return I40E_ERR_PARAM;
5283
5284         /* Case that no vlan is set */
5285         if (vsi->vlan_num == 0)
5286                 num = vsi->mac_num;
5287         else
5288                 num = vsi->mac_num * vsi->vlan_num;
5289
5290         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5291         if (mv_f == NULL) {
5292                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5293                 return I40E_ERR_NO_MEMORY;
5294         }
5295
5296         i = 0;
5297         if (vsi->vlan_num == 0) {
5298                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5299                         (void)rte_memcpy(&mv_f[i].macaddr,
5300                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5301                         mv_f[i].vlan_id = 0;
5302                         i++;
5303                 }
5304         } else {
5305                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5306                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5307                                         vsi->vlan_num, &f->mac_info.mac_addr);
5308                         if (ret != I40E_SUCCESS)
5309                                 goto DONE;
5310                         i += vsi->vlan_num;
5311                 }
5312         }
5313
5314         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5315 DONE:
5316         rte_free(mv_f);
5317
5318         return ret;
5319 }
5320
5321 int
5322 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5323 {
5324         struct i40e_macvlan_filter *mv_f;
5325         int mac_num;
5326         int ret = I40E_SUCCESS;
5327
5328         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5329                 return I40E_ERR_PARAM;
5330
5331         /* If it's already set, just return */
5332         if (i40e_find_vlan_filter(vsi,vlan))
5333                 return I40E_SUCCESS;
5334
5335         mac_num = vsi->mac_num;
5336
5337         if (mac_num == 0) {
5338                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5339                 return I40E_ERR_PARAM;
5340         }
5341
5342         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5343
5344         if (mv_f == NULL) {
5345                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5346                 return I40E_ERR_NO_MEMORY;
5347         }
5348
5349         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5350
5351         if (ret != I40E_SUCCESS)
5352                 goto DONE;
5353
5354         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5355
5356         if (ret != I40E_SUCCESS)
5357                 goto DONE;
5358
5359         i40e_set_vlan_filter(vsi, vlan, 1);
5360
5361         vsi->vlan_num++;
5362         ret = I40E_SUCCESS;
5363 DONE:
5364         rte_free(mv_f);
5365         return ret;
5366 }
5367
5368 int
5369 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5370 {
5371         struct i40e_macvlan_filter *mv_f;
5372         int mac_num;
5373         int ret = I40E_SUCCESS;
5374
5375         /**
5376          * Vlan 0 is the generic filter for untagged packets
5377          * and can't be removed.
5378          */
5379         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5380                 return I40E_ERR_PARAM;
5381
5382         /* If can't find it, just return */
5383         if (!i40e_find_vlan_filter(vsi, vlan))
5384                 return I40E_ERR_PARAM;
5385
5386         mac_num = vsi->mac_num;
5387
5388         if (mac_num == 0) {
5389                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5390                 return I40E_ERR_PARAM;
5391         }
5392
5393         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5394
5395         if (mv_f == NULL) {
5396                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5397                 return I40E_ERR_NO_MEMORY;
5398         }
5399
5400         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5401
5402         if (ret != I40E_SUCCESS)
5403                 goto DONE;
5404
5405         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5406
5407         if (ret != I40E_SUCCESS)
5408                 goto DONE;
5409
5410         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5411         if (vsi->vlan_num == 1) {
5412                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5413                 if (ret != I40E_SUCCESS)
5414                         goto DONE;
5415
5416                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5417                 if (ret != I40E_SUCCESS)
5418                         goto DONE;
5419         }
5420
5421         i40e_set_vlan_filter(vsi, vlan, 0);
5422
5423         vsi->vlan_num--;
5424         ret = I40E_SUCCESS;
5425 DONE:
5426         rte_free(mv_f);
5427         return ret;
5428 }
5429
5430 int
5431 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5432 {
5433         struct i40e_mac_filter *f;
5434         struct i40e_macvlan_filter *mv_f;
5435         int i, vlan_num = 0;
5436         int ret = I40E_SUCCESS;
5437
5438         /* If it's add and we've config it, return */
5439         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5440         if (f != NULL)
5441                 return I40E_SUCCESS;
5442         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5443                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5444
5445                 /**
5446                  * If vlan_num is 0, that's the first time to add mac,
5447                  * set mask for vlan_id 0.
5448                  */
5449                 if (vsi->vlan_num == 0) {
5450                         i40e_set_vlan_filter(vsi, 0, 1);
5451                         vsi->vlan_num = 1;
5452                 }
5453                 vlan_num = vsi->vlan_num;
5454         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5455                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5456                 vlan_num = 1;
5457
5458         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5459         if (mv_f == NULL) {
5460                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5461                 return I40E_ERR_NO_MEMORY;
5462         }
5463
5464         for (i = 0; i < vlan_num; i++) {
5465                 mv_f[i].filter_type = mac_filter->filter_type;
5466                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5467                                 ETH_ADDR_LEN);
5468         }
5469
5470         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5471                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5472                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5473                                         &mac_filter->mac_addr);
5474                 if (ret != I40E_SUCCESS)
5475                         goto DONE;
5476         }
5477
5478         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5479         if (ret != I40E_SUCCESS)
5480                 goto DONE;
5481
5482         /* Add the mac addr into mac list */
5483         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5484         if (f == NULL) {
5485                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5486                 ret = I40E_ERR_NO_MEMORY;
5487                 goto DONE;
5488         }
5489         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5490                         ETH_ADDR_LEN);
5491         f->mac_info.filter_type = mac_filter->filter_type;
5492         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5493         vsi->mac_num++;
5494
5495         ret = I40E_SUCCESS;
5496 DONE:
5497         rte_free(mv_f);
5498
5499         return ret;
5500 }
5501
5502 int
5503 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5504 {
5505         struct i40e_mac_filter *f;
5506         struct i40e_macvlan_filter *mv_f;
5507         int i, vlan_num;
5508         enum rte_mac_filter_type filter_type;
5509         int ret = I40E_SUCCESS;
5510
5511         /* Can't find it, return an error */
5512         f = i40e_find_mac_filter(vsi, addr);
5513         if (f == NULL)
5514                 return I40E_ERR_PARAM;
5515
5516         vlan_num = vsi->vlan_num;
5517         filter_type = f->mac_info.filter_type;
5518         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5519                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5520                 if (vlan_num == 0) {
5521                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5522                         return I40E_ERR_PARAM;
5523                 }
5524         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5525                         filter_type == RTE_MAC_HASH_MATCH)
5526                 vlan_num = 1;
5527
5528         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5529         if (mv_f == NULL) {
5530                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5531                 return I40E_ERR_NO_MEMORY;
5532         }
5533
5534         for (i = 0; i < vlan_num; i++) {
5535                 mv_f[i].filter_type = filter_type;
5536                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5537                                 ETH_ADDR_LEN);
5538         }
5539         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5540                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5541                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5542                 if (ret != I40E_SUCCESS)
5543                         goto DONE;
5544         }
5545
5546         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5547         if (ret != I40E_SUCCESS)
5548                 goto DONE;
5549
5550         /* Remove the mac addr into mac list */
5551         TAILQ_REMOVE(&vsi->mac_list, f, next);
5552         rte_free(f);
5553         vsi->mac_num--;
5554
5555         ret = I40E_SUCCESS;
5556 DONE:
5557         rte_free(mv_f);
5558         return ret;
5559 }
5560
5561 /* Configure hash enable flags for RSS */
5562 uint64_t
5563 i40e_config_hena(uint64_t flags)
5564 {
5565         uint64_t hena = 0;
5566
5567         if (!flags)
5568                 return hena;
5569
5570         if (flags & ETH_RSS_FRAG_IPV4)
5571                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5572         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5573                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5574         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5575                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5576         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5577                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5578         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5579                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5580         if (flags & ETH_RSS_FRAG_IPV6)
5581                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5582         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5583                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5584         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5585                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5586         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5587                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5588         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5589                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5590         if (flags & ETH_RSS_L2_PAYLOAD)
5591                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5592
5593         return hena;
5594 }
5595
5596 /* Parse the hash enable flags */
5597 uint64_t
5598 i40e_parse_hena(uint64_t flags)
5599 {
5600         uint64_t rss_hf = 0;
5601
5602         if (!flags)
5603                 return rss_hf;
5604         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5605                 rss_hf |= ETH_RSS_FRAG_IPV4;
5606         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5607                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5608         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5609                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5610         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5611                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5612         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5613                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5614         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5615                 rss_hf |= ETH_RSS_FRAG_IPV6;
5616         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5617                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5618         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5619                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5620         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5621                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5622         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5623                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5624         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5625                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5626
5627         return rss_hf;
5628 }
5629
5630 /* Disable RSS */
5631 static void
5632 i40e_pf_disable_rss(struct i40e_pf *pf)
5633 {
5634         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5635         uint64_t hena;
5636
5637         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5638         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5639         hena &= ~I40E_RSS_HENA_ALL;
5640         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5641         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5642         I40E_WRITE_FLUSH(hw);
5643 }
5644
5645 static int
5646 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5647 {
5648         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5649         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5650         int ret = 0;
5651
5652         if (!key || key_len == 0) {
5653                 PMD_DRV_LOG(DEBUG, "No key to be configured");
5654                 return 0;
5655         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5656                 sizeof(uint32_t)) {
5657                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5658                 return -EINVAL;
5659         }
5660
5661         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5662                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5663                         (struct i40e_aqc_get_set_rss_key_data *)key;
5664
5665                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5666                 if (ret)
5667                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5668                                      "via AQ");
5669         } else {
5670                 uint32_t *hash_key = (uint32_t *)key;
5671                 uint16_t i;
5672
5673                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5674                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5675                 I40E_WRITE_FLUSH(hw);
5676         }
5677
5678         return ret;
5679 }
5680
5681 static int
5682 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5683 {
5684         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5685         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5686         int ret;
5687
5688         if (!key || !key_len)
5689                 return -EINVAL;
5690
5691         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5692                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5693                         (struct i40e_aqc_get_set_rss_key_data *)key);
5694                 if (ret) {
5695                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5696                         return ret;
5697                 }
5698         } else {
5699                 uint32_t *key_dw = (uint32_t *)key;
5700                 uint16_t i;
5701
5702                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5703                         key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5704         }
5705         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5706
5707         return 0;
5708 }
5709
5710 static int
5711 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5712 {
5713         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5714         uint64_t rss_hf;
5715         uint64_t hena;
5716         int ret;
5717
5718         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5719                                rss_conf->rss_key_len);
5720         if (ret)
5721                 return ret;
5722
5723         rss_hf = rss_conf->rss_hf;
5724         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5725         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5726         hena &= ~I40E_RSS_HENA_ALL;
5727         hena |= i40e_config_hena(rss_hf);
5728         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5729         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5730         I40E_WRITE_FLUSH(hw);
5731
5732         return 0;
5733 }
5734
5735 static int
5736 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5737                          struct rte_eth_rss_conf *rss_conf)
5738 {
5739         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5740         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5741         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5742         uint64_t hena;
5743
5744         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5745         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5746         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5747                 if (rss_hf != 0) /* Enable RSS */
5748                         return -EINVAL;
5749                 return 0; /* Nothing to do */
5750         }
5751         /* RSS enabled */
5752         if (rss_hf == 0) /* Disable RSS */
5753                 return -EINVAL;
5754
5755         return i40e_hw_rss_hash_set(pf, rss_conf);
5756 }
5757
5758 static int
5759 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5760                            struct rte_eth_rss_conf *rss_conf)
5761 {
5762         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5763         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5764         uint64_t hena;
5765
5766         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5767                          &rss_conf->rss_key_len);
5768
5769         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5770         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5771         rss_conf->rss_hf = i40e_parse_hena(hena);
5772
5773         return 0;
5774 }
5775
5776 static int
5777 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5778 {
5779         switch (filter_type) {
5780         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5781                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5782                 break;
5783         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5784                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5785                 break;
5786         case RTE_TUNNEL_FILTER_IMAC_TENID:
5787                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5788                 break;
5789         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5790                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5791                 break;
5792         case ETH_TUNNEL_FILTER_IMAC:
5793                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5794                 break;
5795         default:
5796                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5797                 return -EINVAL;
5798         }
5799
5800         return 0;
5801 }
5802
5803 static int
5804 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5805                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5806                         uint8_t add)
5807 {
5808         uint16_t ip_type;
5809         uint8_t tun_type = 0;
5810         int val, ret = 0;
5811         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5812         struct i40e_vsi *vsi = pf->main_vsi;
5813         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5814         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5815
5816         cld_filter = rte_zmalloc("tunnel_filter",
5817                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5818                 0);
5819
5820         if (NULL == cld_filter) {
5821                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5822                 return -EINVAL;
5823         }
5824         pfilter = cld_filter;
5825
5826         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5827                         sizeof(struct ether_addr));
5828         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5829                         sizeof(struct ether_addr));
5830
5831         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5832         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5833                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5834                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5835                                 &tunnel_filter->ip_addr,
5836                                 sizeof(pfilter->ipaddr.v4.data));
5837         } else {
5838                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5839                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5840                                 &tunnel_filter->ip_addr,
5841                                 sizeof(pfilter->ipaddr.v6.data));
5842         }
5843
5844         /* check tunneled type */
5845         switch (tunnel_filter->tunnel_type) {
5846         case RTE_TUNNEL_TYPE_VXLAN:
5847                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5848                 break;
5849         case RTE_TUNNEL_TYPE_NVGRE:
5850                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5851                 break;
5852         default:
5853                 /* Other tunnel types is not supported. */
5854                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5855                 rte_free(cld_filter);
5856                 return -EINVAL;
5857         }
5858
5859         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5860                                                 &pfilter->flags);
5861         if (val < 0) {
5862                 rte_free(cld_filter);
5863                 return -EINVAL;
5864         }
5865
5866         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5867                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5868         pfilter->tenant_id = tunnel_filter->tenant_id;
5869         pfilter->queue_number = tunnel_filter->queue_id;
5870
5871         if (add)
5872                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5873         else
5874                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5875                                                 cld_filter, 1);
5876
5877         rte_free(cld_filter);
5878         return ret;
5879 }
5880
5881 static int
5882 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5883 {
5884         uint8_t i;
5885
5886         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5887                 if (pf->vxlan_ports[i] == port)
5888                         return i;
5889         }
5890
5891         return -1;
5892 }
5893
5894 static int
5895 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5896 {
5897         int  idx, ret;
5898         uint8_t filter_idx;
5899         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5900
5901         idx = i40e_get_vxlan_port_idx(pf, port);
5902
5903         /* Check if port already exists */
5904         if (idx >= 0) {
5905                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5906                 return -EINVAL;
5907         }
5908
5909         /* Now check if there is space to add the new port */
5910         idx = i40e_get_vxlan_port_idx(pf, 0);
5911         if (idx < 0) {
5912                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5913                         "not adding port %d", port);
5914                 return -ENOSPC;
5915         }
5916
5917         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5918                                         &filter_idx, NULL);
5919         if (ret < 0) {
5920                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5921                 return -1;
5922         }
5923
5924         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5925                          port,  filter_idx);
5926
5927         /* New port: add it and mark its index in the bitmap */
5928         pf->vxlan_ports[idx] = port;
5929         pf->vxlan_bitmap |= (1 << idx);
5930
5931         if (!(pf->flags & I40E_FLAG_VXLAN))
5932                 pf->flags |= I40E_FLAG_VXLAN;
5933
5934         return 0;
5935 }
5936
5937 static int
5938 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5939 {
5940         int idx;
5941         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5942
5943         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5944                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5945                 return -EINVAL;
5946         }
5947
5948         idx = i40e_get_vxlan_port_idx(pf, port);
5949
5950         if (idx < 0) {
5951                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5952                 return -EINVAL;
5953         }
5954
5955         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5956                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5957                 return -1;
5958         }
5959
5960         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5961                         port, idx);
5962
5963         pf->vxlan_ports[idx] = 0;
5964         pf->vxlan_bitmap &= ~(1 << idx);
5965
5966         if (!pf->vxlan_bitmap)
5967                 pf->flags &= ~I40E_FLAG_VXLAN;
5968
5969         return 0;
5970 }
5971
5972 /* Add UDP tunneling port */
5973 static int
5974 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5975                         struct rte_eth_udp_tunnel *udp_tunnel)
5976 {
5977         int ret = 0;
5978         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5979
5980         if (udp_tunnel == NULL)
5981                 return -EINVAL;
5982
5983         switch (udp_tunnel->prot_type) {
5984         case RTE_TUNNEL_TYPE_VXLAN:
5985                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5986                 break;
5987
5988         case RTE_TUNNEL_TYPE_GENEVE:
5989         case RTE_TUNNEL_TYPE_TEREDO:
5990                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5991                 ret = -1;
5992                 break;
5993
5994         default:
5995                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5996                 ret = -1;
5997                 break;
5998         }
5999
6000         return ret;
6001 }
6002
6003 /* Remove UDP tunneling port */
6004 static int
6005 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
6006                         struct rte_eth_udp_tunnel *udp_tunnel)
6007 {
6008         int ret = 0;
6009         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6010
6011         if (udp_tunnel == NULL)
6012                 return -EINVAL;
6013
6014         switch (udp_tunnel->prot_type) {
6015         case RTE_TUNNEL_TYPE_VXLAN:
6016                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6017                 break;
6018         case RTE_TUNNEL_TYPE_GENEVE:
6019         case RTE_TUNNEL_TYPE_TEREDO:
6020                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6021                 ret = -1;
6022                 break;
6023         default:
6024                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6025                 ret = -1;
6026                 break;
6027         }
6028
6029         return ret;
6030 }
6031
6032 /* Calculate the maximum number of contiguous PF queues that are configured */
6033 static int
6034 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6035 {
6036         struct rte_eth_dev_data *data = pf->dev_data;
6037         int i, num;
6038         struct i40e_rx_queue *rxq;
6039
6040         num = 0;
6041         for (i = 0; i < pf->lan_nb_qps; i++) {
6042                 rxq = data->rx_queues[i];
6043                 if (rxq && rxq->q_set)
6044                         num++;
6045                 else
6046                         break;
6047         }
6048
6049         return num;
6050 }
6051
6052 /* Configure RSS */
6053 static int
6054 i40e_pf_config_rss(struct i40e_pf *pf)
6055 {
6056         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6057         struct rte_eth_rss_conf rss_conf;
6058         uint32_t i, lut = 0;
6059         uint16_t j, num;
6060
6061         /*
6062          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6063          * It's necessary to calulate the actual PF queues that are configured.
6064          */
6065         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6066                 num = i40e_pf_calc_configured_queues_num(pf);
6067         else
6068                 num = pf->dev_data->nb_rx_queues;
6069
6070         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6071         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6072                         num);
6073
6074         if (num == 0) {
6075                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6076                 return -ENOTSUP;
6077         }
6078
6079         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6080                 if (j == num)
6081                         j = 0;
6082                 lut = (lut << 8) | (j & ((0x1 <<
6083                         hw->func_caps.rss_table_entry_width) - 1));
6084                 if ((i & 3) == 3)
6085                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6086         }
6087
6088         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6089         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6090                 i40e_pf_disable_rss(pf);
6091                 return 0;
6092         }
6093         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6094                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6095                 /* Random default keys */
6096                 static uint32_t rss_key_default[] = {0x6b793944,
6097                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6098                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6099                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6100
6101                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6102                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6103                                                         sizeof(uint32_t);
6104         }
6105
6106         return i40e_hw_rss_hash_set(pf, &rss_conf);
6107 }
6108
6109 static int
6110 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6111                                struct rte_eth_tunnel_filter_conf *filter)
6112 {
6113         if (pf == NULL || filter == NULL) {
6114                 PMD_DRV_LOG(ERR, "Invalid parameter");
6115                 return -EINVAL;
6116         }
6117
6118         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6119                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6120                 return -EINVAL;
6121         }
6122
6123         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6124                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6125                 return -EINVAL;
6126         }
6127
6128         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6129                 (is_zero_ether_addr(filter->outer_mac))) {
6130                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6131                 return -EINVAL;
6132         }
6133
6134         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6135                 (is_zero_ether_addr(filter->inner_mac))) {
6136                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6137                 return -EINVAL;
6138         }
6139
6140         return 0;
6141 }
6142
6143 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6144 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6145 static int
6146 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6147 {
6148         uint32_t val, reg;
6149         int ret = -EINVAL;
6150
6151         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6152         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6153
6154         if (len == 3) {
6155                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6156         } else if (len == 4) {
6157                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6158         } else {
6159                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6160                 return ret;
6161         }
6162
6163         if (reg != val) {
6164                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6165                                                    reg, NULL);
6166                 if (ret != 0)
6167                         return ret;
6168         } else {
6169                 ret = 0;
6170         }
6171         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6172                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6173
6174         return ret;
6175 }
6176
6177 static int
6178 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6179 {
6180         int ret = -EINVAL;
6181
6182         if (!hw || !cfg)
6183                 return -EINVAL;
6184
6185         switch (cfg->cfg_type) {
6186         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6187                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6188                 break;
6189         default:
6190                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6191                 break;
6192         }
6193
6194         return ret;
6195 }
6196
6197 static int
6198 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6199                                enum rte_filter_op filter_op,
6200                                void *arg)
6201 {
6202         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6203         int ret = I40E_ERR_PARAM;
6204
6205         switch (filter_op) {
6206         case RTE_ETH_FILTER_SET:
6207                 ret = i40e_dev_global_config_set(hw,
6208                         (struct rte_eth_global_cfg *)arg);
6209                 break;
6210         default:
6211                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6212                 break;
6213         }
6214
6215         return ret;
6216 }
6217
6218 static int
6219 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6220                           enum rte_filter_op filter_op,
6221                           void *arg)
6222 {
6223         struct rte_eth_tunnel_filter_conf *filter;
6224         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6225         int ret = I40E_SUCCESS;
6226
6227         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6228
6229         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6230                 return I40E_ERR_PARAM;
6231
6232         switch (filter_op) {
6233         case RTE_ETH_FILTER_NOP:
6234                 if (!(pf->flags & I40E_FLAG_VXLAN))
6235                         ret = I40E_NOT_SUPPORTED;
6236                 break;
6237         case RTE_ETH_FILTER_ADD:
6238                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6239                 break;
6240         case RTE_ETH_FILTER_DELETE:
6241                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6242                 break;
6243         default:
6244                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6245                 ret = I40E_ERR_PARAM;
6246                 break;
6247         }
6248
6249         return ret;
6250 }
6251
6252 static int
6253 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6254 {
6255         int ret = 0;
6256         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6257
6258         /* RSS setup */
6259         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6260                 ret = i40e_pf_config_rss(pf);
6261         else
6262                 i40e_pf_disable_rss(pf);
6263
6264         return ret;
6265 }
6266
6267 /* Get the symmetric hash enable configurations per port */
6268 static void
6269 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6270 {
6271         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6272
6273         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6274 }
6275
6276 /* Set the symmetric hash enable configurations per port */
6277 static void
6278 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6279 {
6280         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6281
6282         if (enable > 0) {
6283                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6284                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6285                                                         "been enabled");
6286                         return;
6287                 }
6288                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6289         } else {
6290                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6291                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6292                                                         "been disabled");
6293                         return;
6294                 }
6295                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6296         }
6297         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
6298         I40E_WRITE_FLUSH(hw);
6299 }
6300
6301 /*
6302  * Get global configurations of hash function type and symmetric hash enable
6303  * per flow type (pctype). Note that global configuration means it affects all
6304  * the ports on the same NIC.
6305  */
6306 static int
6307 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6308                                    struct rte_eth_hash_global_conf *g_cfg)
6309 {
6310         uint32_t reg, mask = I40E_FLOW_TYPES;
6311         uint16_t i;
6312         enum i40e_filter_pctype pctype;
6313
6314         memset(g_cfg, 0, sizeof(*g_cfg));
6315         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6316         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6317                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6318         else
6319                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6320         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6321                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6322
6323         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6324                 if (!(mask & (1UL << i)))
6325                         continue;
6326                 mask &= ~(1UL << i);
6327                 /* Bit set indicats the coresponding flow type is supported */
6328                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6329                 pctype = i40e_flowtype_to_pctype(i);
6330                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
6331                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6332                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6333         }
6334
6335         return 0;
6336 }
6337
6338 static int
6339 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6340 {
6341         uint32_t i;
6342         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6343
6344         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6345                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6346                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6347                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6348                                                 g_cfg->hash_func);
6349                 return -EINVAL;
6350         }
6351
6352         /*
6353          * As i40e supports less than 32 flow types, only first 32 bits need to
6354          * be checked.
6355          */
6356         mask0 = g_cfg->valid_bit_mask[0];
6357         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6358                 if (i == 0) {
6359                         /* Check if any unsupported flow type configured */
6360                         if ((mask0 | i40e_mask) ^ i40e_mask)
6361                                 goto mask_err;
6362                 } else {
6363                         if (g_cfg->valid_bit_mask[i])
6364                                 goto mask_err;
6365                 }
6366         }
6367
6368         return 0;
6369
6370 mask_err:
6371         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6372
6373         return -EINVAL;
6374 }
6375
6376 /*
6377  * Set global configurations of hash function type and symmetric hash enable
6378  * per flow type (pctype). Note any modifying global configuration will affect
6379  * all the ports on the same NIC.
6380  */
6381 static int
6382 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6383                                    struct rte_eth_hash_global_conf *g_cfg)
6384 {
6385         int ret;
6386         uint16_t i;
6387         uint32_t reg;
6388         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6389         enum i40e_filter_pctype pctype;
6390
6391         /* Check the input parameters */
6392         ret = i40e_hash_global_config_check(g_cfg);
6393         if (ret < 0)
6394                 return ret;
6395
6396         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6397                 if (!(mask0 & (1UL << i)))
6398                         continue;
6399                 mask0 &= ~(1UL << i);
6400                 pctype = i40e_flowtype_to_pctype(i);
6401                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6402                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6403                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
6404         }
6405
6406         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6407         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6408                 /* Toeplitz */
6409                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6410                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6411                                                                 "Toeplitz");
6412                         goto out;
6413                 }
6414                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6415         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6416                 /* Simple XOR */
6417                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6418                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6419                                                         "Simple XOR");
6420                         goto out;
6421                 }
6422                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6423         } else
6424                 /* Use the default, and keep it as it is */
6425                 goto out;
6426
6427         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6428
6429 out:
6430         I40E_WRITE_FLUSH(hw);
6431
6432         return 0;
6433 }
6434
6435 /**
6436  * Valid input sets for hash and flow director filters per PCTYPE
6437  */
6438 static uint64_t
6439 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6440                 enum rte_filter_type filter)
6441 {
6442         uint64_t valid;
6443
6444         static const uint64_t valid_hash_inset_table[] = {
6445                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6446                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6447                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6448                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6449                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6450                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6451                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6452                         I40E_INSET_FLEX_PAYLOAD,
6453                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6454                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6455                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6456                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6457                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6458                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6459                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6460                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6461                         I40E_INSET_FLEX_PAYLOAD,
6462                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6463                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6464                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6465                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6466                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6467                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6468                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6469                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6470                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6471                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6472                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6473                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6474                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6475                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6476                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6477                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6478                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6479                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6480                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6481                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6482                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6483                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6484                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6485                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6486                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6487                         I40E_INSET_FLEX_PAYLOAD,
6488                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6489                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6490                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6491                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6492                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6493                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6494                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6495                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6496                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6497                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6498                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6499                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6500                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6501                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6502                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6503                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6504                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6505                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6506                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6507                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6508                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6509                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6510                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6511                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6512                         I40E_INSET_FLEX_PAYLOAD,
6513                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6514                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6515                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6516                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6517                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6518                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6519                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6520                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6521                         I40E_INSET_FLEX_PAYLOAD,
6522                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6523                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6524                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6525                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6526                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6527                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6528                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6529                         I40E_INSET_FLEX_PAYLOAD,
6530                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6531                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6532                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6533                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6534                         I40E_INSET_FLEX_PAYLOAD,
6535         };
6536
6537         /**
6538          * Flow director supports only fields defined in
6539          * union rte_eth_fdir_flow.
6540          */
6541         static const uint64_t valid_fdir_inset_table[] = {
6542                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6543                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6544                 I40E_INSET_FLEX_PAYLOAD,
6545                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6546                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6547                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6548                 I40E_INSET_FLEX_PAYLOAD,
6549                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6550                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6551                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6552                 I40E_INSET_FLEX_PAYLOAD,
6553                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6554                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6555                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6556                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6557                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6558                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6559                 I40E_INSET_FLEX_PAYLOAD,
6560                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6561                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6562                 I40E_INSET_FLEX_PAYLOAD,
6563                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6564                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6565                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6566                 I40E_INSET_FLEX_PAYLOAD,
6567                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6568                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6569                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6570                 I40E_INSET_FLEX_PAYLOAD,
6571                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6572                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6573                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6574                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6575                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6576                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6577                 I40E_INSET_FLEX_PAYLOAD,
6578                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6579                 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6580         };
6581
6582         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6583                 return 0;
6584         if (filter == RTE_ETH_FILTER_HASH)
6585                 valid = valid_hash_inset_table[pctype];
6586         else
6587                 valid = valid_fdir_inset_table[pctype];
6588
6589         return valid;
6590 }
6591
6592 /**
6593  * Validate if the input set is allowed for a specific PCTYPE
6594  */
6595 static int
6596 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6597                 enum rte_filter_type filter, uint64_t inset)
6598 {
6599         uint64_t valid;
6600
6601         valid = i40e_get_valid_input_set(pctype, filter);
6602         if (inset & (~valid))
6603                 return -EINVAL;
6604
6605         return 0;
6606 }
6607
6608 /* default input set fields combination per pctype */
6609 static uint64_t
6610 i40e_get_default_input_set(uint16_t pctype)
6611 {
6612         static const uint64_t default_inset_table[] = {
6613                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6614                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6615                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6616                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6617                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6618                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6619                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6620                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6621                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6622                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6623                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6624                         I40E_INSET_SCTP_VT,
6625                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6626                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6627                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6628                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6629                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6630                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6631                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6632                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6633                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6634                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6635                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6636                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6637                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6638                         I40E_INSET_SCTP_VT,
6639                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6640                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6641                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6642                         I40E_INSET_LAST_ETHER_TYPE,
6643         };
6644
6645         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6646                 return 0;
6647
6648         return default_inset_table[pctype];
6649 }
6650
6651 /**
6652  * Parse the input set from index to logical bit masks
6653  */
6654 static int
6655 i40e_parse_input_set(uint64_t *inset,
6656                      enum i40e_filter_pctype pctype,
6657                      enum rte_eth_input_set_field *field,
6658                      uint16_t size)
6659 {
6660         uint16_t i, j;
6661         int ret = -EINVAL;
6662
6663         static const struct {
6664                 enum rte_eth_input_set_field field;
6665                 uint64_t inset;
6666         } inset_convert_table[] = {
6667                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6668                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6669                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6670                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6671                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6672                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6673                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6674                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6675                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6676                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6677                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6678                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6679                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6680                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6681                         I40E_INSET_IPV6_NEXT_HDR},
6682                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6683                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6684                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6685                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6686                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6687                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6688                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6689                         I40E_INSET_SCTP_VT},
6690                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6691                         I40E_INSET_TUNNEL_DMAC},
6692                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6693                         I40E_INSET_VLAN_TUNNEL},
6694                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6695                         I40E_INSET_TUNNEL_ID},
6696                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6697                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6698                         I40E_INSET_FLEX_PAYLOAD_W1},
6699                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6700                         I40E_INSET_FLEX_PAYLOAD_W2},
6701                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6702                         I40E_INSET_FLEX_PAYLOAD_W3},
6703                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6704                         I40E_INSET_FLEX_PAYLOAD_W4},
6705                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6706                         I40E_INSET_FLEX_PAYLOAD_W5},
6707                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6708                         I40E_INSET_FLEX_PAYLOAD_W6},
6709                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6710                         I40E_INSET_FLEX_PAYLOAD_W7},
6711                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6712                         I40E_INSET_FLEX_PAYLOAD_W8},
6713         };
6714
6715         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6716                 return ret;
6717
6718         /* Only one item allowed for default or all */
6719         if (size == 1) {
6720                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6721                         *inset = i40e_get_default_input_set(pctype);
6722                         return 0;
6723                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6724                         *inset = I40E_INSET_NONE;
6725                         return 0;
6726                 }
6727         }
6728
6729         for (i = 0, *inset = 0; i < size; i++) {
6730                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6731                         if (field[i] == inset_convert_table[j].field) {
6732                                 *inset |= inset_convert_table[j].inset;
6733                                 break;
6734                         }
6735                 }
6736
6737                 /* It contains unsupported input set, return immediately */
6738                 if (j == RTE_DIM(inset_convert_table))
6739                         return ret;
6740         }
6741
6742         return 0;
6743 }
6744
6745 /**
6746  * Translate the input set from bit masks to register aware bit masks
6747  * and vice versa
6748  */
6749 static uint64_t
6750 i40e_translate_input_set_reg(uint64_t input)
6751 {
6752         uint64_t val = 0;
6753         uint16_t i;
6754
6755         static const struct {
6756                 uint64_t inset;
6757                 uint64_t inset_reg;
6758         } inset_map[] = {
6759                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6760                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6761                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6762                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6763                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6764                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6765                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6766                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6767                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6768                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6769                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6770                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6771                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6772                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6773                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6774                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6775                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6776                 {I40E_INSET_TUNNEL_DMAC,
6777                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6778                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6779                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6780                 {I40E_INSET_TUNNEL_SRC_PORT,
6781                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6782                 {I40E_INSET_TUNNEL_DST_PORT,
6783                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6784                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6785                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6786                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6787                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6788                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6789                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6790                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6791                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6792                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6793         };
6794
6795         if (input == 0)
6796                 return val;
6797
6798         /* Translate input set to register aware inset */
6799         for (i = 0; i < RTE_DIM(inset_map); i++) {
6800                 if (input & inset_map[i].inset)
6801                         val |= inset_map[i].inset_reg;
6802         }
6803
6804         return val;
6805 }
6806
6807 static uint8_t
6808 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6809 {
6810         uint8_t i, idx = 0;
6811
6812         static const struct {
6813                 uint64_t inset;
6814                 uint32_t mask;
6815         } inset_mask_map[] = {
6816                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6817                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6818                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6819                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6820         };
6821
6822         if (!inset || !mask || !nb_elem)
6823                 return 0;
6824
6825         if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6826                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6827                         mask[i] = 0;
6828                 return I40E_INSET_MASK_NUM_REG;
6829         }
6830
6831         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6832                 if (idx >= nb_elem)
6833                         break;
6834                 if (inset & inset_mask_map[i].inset) {
6835                         mask[idx] = inset_mask_map[i].mask;
6836                         idx++;
6837                 }
6838         }
6839
6840         return idx;
6841 }
6842
6843 static uint64_t
6844 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
6845                             enum i40e_filter_pctype pctype)
6846 {
6847         uint64_t reg = 0;
6848
6849         if (filter == RTE_ETH_FILTER_HASH) {
6850                 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
6851                 reg <<= I40E_32_BIT_WIDTH;
6852                 reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
6853         } else if (filter == RTE_ETH_FILTER_FDIR) {
6854                 reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
6855                 reg <<= I40E_32_BIT_WIDTH;
6856                 reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
6857         }
6858
6859         return reg;
6860 }
6861
6862 static void
6863 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
6864 {
6865         uint32_t reg = I40E_READ_REG(hw, addr);
6866
6867         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
6868         if (reg != val)
6869                 I40E_WRITE_REG(hw, addr, val);
6870         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
6871                     (uint32_t)I40E_READ_REG(hw, addr));
6872 }
6873
6874 static int
6875 i40e_set_hash_inset_mask(struct i40e_hw *hw,
6876                          enum i40e_filter_pctype pctype,
6877                          enum rte_filter_input_set_op op,
6878                          uint32_t *mask_reg,
6879                          uint8_t num)
6880 {
6881         uint32_t reg;
6882         uint8_t i;
6883
6884         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6885                 return -EINVAL;
6886
6887         if (op == RTE_ETH_INPUT_SET_SELECT) {
6888                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6889                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6890                                              0);
6891                         if (i >= num)
6892                                 continue;
6893                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6894                                              mask_reg[i]);
6895                 }
6896         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6897                 uint8_t j, count = 0;
6898
6899                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6900                         reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
6901                         if (reg & I40E_GLQF_HASH_MSK_FIELD)
6902                                 count++;
6903                 }
6904                 if (count + num > I40E_INSET_MASK_NUM_REG)
6905                         return -EINVAL;
6906
6907                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6908                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6909                                              mask_reg[j]);
6910         }
6911
6912         return 0;
6913 }
6914
6915 static int
6916 i40e_set_fd_inset_mask(struct i40e_hw *hw,
6917                        enum i40e_filter_pctype pctype,
6918                        enum rte_filter_input_set_op op,
6919                        uint32_t *mask_reg,
6920                        uint8_t num)
6921 {
6922         uint32_t reg;
6923         uint8_t i;
6924
6925         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6926                 return -EINVAL;
6927
6928         if (op == RTE_ETH_INPUT_SET_SELECT) {
6929                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6930                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6931                                              0);
6932                         if (i >= num)
6933                                 continue;
6934                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6935                                              mask_reg[i]);
6936                 }
6937         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6938                 uint8_t j, count = 0;
6939
6940                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6941                         reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
6942                         if (reg & I40E_GLQF_FD_MSK_FIELD)
6943                                 count++;
6944                 }
6945                 if (count + num > I40E_INSET_MASK_NUM_REG)
6946                         return -EINVAL;
6947
6948                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6949                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6950                                              mask_reg[j]);
6951         }
6952
6953         return 0;
6954 }
6955
6956 int
6957 i40e_filter_inset_select(struct i40e_hw *hw,
6958                          struct rte_eth_input_set_conf *conf,
6959                          enum rte_filter_type filter)
6960 {
6961         enum i40e_filter_pctype pctype;
6962         uint64_t inset_reg = 0, input_set;
6963         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
6964         uint8_t num;
6965         int ret;
6966
6967         if (!hw || !conf) {
6968                 PMD_DRV_LOG(ERR, "Invalid pointer");
6969                 return -EFAULT;
6970         }
6971
6972         pctype = i40e_flowtype_to_pctype(conf->flow_type);
6973         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
6974                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
6975                             conf->flow_type);
6976                 return -EINVAL;
6977         }
6978         if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
6979                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6980                 return -EINVAL;
6981         }
6982
6983         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
6984                                    conf->inset_size);
6985         if (ret) {
6986                 PMD_DRV_LOG(ERR, "Failed to parse input set");
6987                 return -EINVAL;
6988         }
6989         if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
6990                 PMD_DRV_LOG(ERR, "Invalid input set");
6991                 return -EINVAL;
6992         }
6993
6994         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
6995                 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
6996         } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
6997                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
6998                 return -EINVAL;
6999         }
7000         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7001                                            I40E_INSET_MASK_NUM_REG);
7002         inset_reg |= i40e_translate_input_set_reg(input_set);
7003
7004         if (filter == RTE_ETH_FILTER_HASH) {
7005                 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
7006                                                num);
7007                 if (ret)
7008                         return -EINVAL;
7009
7010                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7011                                       (uint32_t)(inset_reg & UINT32_MAX));
7012                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7013                                      (uint32_t)((inset_reg >>
7014                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7015         } else if (filter == RTE_ETH_FILTER_FDIR) {
7016                 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
7017                                              num);
7018                 if (ret)
7019                         return -EINVAL;
7020
7021                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7022                                       (uint32_t)(inset_reg & UINT32_MAX));
7023                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7024                                      (uint32_t)((inset_reg >>
7025                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7026         } else {
7027                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7028                 return -EINVAL;
7029         }
7030         I40E_WRITE_FLUSH(hw);
7031
7032         return 0;
7033 }
7034
7035 static int
7036 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7037 {
7038         int ret = 0;
7039
7040         if (!hw || !info) {
7041                 PMD_DRV_LOG(ERR, "Invalid pointer");
7042                 return -EFAULT;
7043         }
7044
7045         switch (info->info_type) {
7046         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7047                 i40e_get_symmetric_hash_enable_per_port(hw,
7048                                         &(info->info.enable));
7049                 break;
7050         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7051                 ret = i40e_get_hash_filter_global_config(hw,
7052                                 &(info->info.global_conf));
7053                 break;
7054         default:
7055                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7056                                                         info->info_type);
7057                 ret = -EINVAL;
7058                 break;
7059         }
7060
7061         return ret;
7062 }
7063
7064 static int
7065 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7066 {
7067         int ret = 0;
7068
7069         if (!hw || !info) {
7070                 PMD_DRV_LOG(ERR, "Invalid pointer");
7071                 return -EFAULT;
7072         }
7073
7074         switch (info->info_type) {
7075         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7076                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7077                 break;
7078         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7079                 ret = i40e_set_hash_filter_global_config(hw,
7080                                 &(info->info.global_conf));
7081                 break;
7082         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7083                 ret = i40e_filter_inset_select(hw,
7084                                                &(info->info.input_set_conf),
7085                                                RTE_ETH_FILTER_HASH);
7086                 break;
7087
7088         default:
7089                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7090                                                         info->info_type);
7091                 ret = -EINVAL;
7092                 break;
7093         }
7094
7095         return ret;
7096 }
7097
7098 /* Operations for hash function */
7099 static int
7100 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7101                       enum rte_filter_op filter_op,
7102                       void *arg)
7103 {
7104         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7105         int ret = 0;
7106
7107         switch (filter_op) {
7108         case RTE_ETH_FILTER_NOP:
7109                 break;
7110         case RTE_ETH_FILTER_GET:
7111                 ret = i40e_hash_filter_get(hw,
7112                         (struct rte_eth_hash_filter_info *)arg);
7113                 break;
7114         case RTE_ETH_FILTER_SET:
7115                 ret = i40e_hash_filter_set(hw,
7116                         (struct rte_eth_hash_filter_info *)arg);
7117                 break;
7118         default:
7119                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7120                                                                 filter_op);
7121                 ret = -ENOTSUP;
7122                 break;
7123         }
7124
7125         return ret;
7126 }
7127
7128 /*
7129  * Configure ethertype filter, which can director packet by filtering
7130  * with mac address and ether_type or only ether_type
7131  */
7132 static int
7133 i40e_ethertype_filter_set(struct i40e_pf *pf,
7134                         struct rte_eth_ethertype_filter *filter,
7135                         bool add)
7136 {
7137         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7138         struct i40e_control_filter_stats stats;
7139         uint16_t flags = 0;
7140         int ret;
7141
7142         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7143                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7144                 return -EINVAL;
7145         }
7146         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7147                 filter->ether_type == ETHER_TYPE_IPv6) {
7148                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7149                         " control packet filter.", filter->ether_type);
7150                 return -EINVAL;
7151         }
7152         if (filter->ether_type == ETHER_TYPE_VLAN)
7153                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7154                         " not supported.");
7155
7156         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7157                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7158         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7159                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7160         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7161
7162         memset(&stats, 0, sizeof(stats));
7163         ret = i40e_aq_add_rem_control_packet_filter(hw,
7164                         filter->mac_addr.addr_bytes,
7165                         filter->ether_type, flags,
7166                         pf->main_vsi->seid,
7167                         filter->queue, add, &stats, NULL);
7168
7169         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7170                          " mac_etype_used = %u, etype_used = %u,"
7171                          " mac_etype_free = %u, etype_free = %u\n",
7172                          ret, stats.mac_etype_used, stats.etype_used,
7173                          stats.mac_etype_free, stats.etype_free);
7174         if (ret < 0)
7175                 return -ENOSYS;
7176         return 0;
7177 }
7178
7179 /*
7180  * Handle operations for ethertype filter.
7181  */
7182 static int
7183 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7184                                 enum rte_filter_op filter_op,
7185                                 void *arg)
7186 {
7187         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7188         int ret = 0;
7189
7190         if (filter_op == RTE_ETH_FILTER_NOP)
7191                 return ret;
7192
7193         if (arg == NULL) {
7194                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7195                             filter_op);
7196                 return -EINVAL;
7197         }
7198
7199         switch (filter_op) {
7200         case RTE_ETH_FILTER_ADD:
7201                 ret = i40e_ethertype_filter_set(pf,
7202                         (struct rte_eth_ethertype_filter *)arg,
7203                         TRUE);
7204                 break;
7205         case RTE_ETH_FILTER_DELETE:
7206                 ret = i40e_ethertype_filter_set(pf,
7207                         (struct rte_eth_ethertype_filter *)arg,
7208                         FALSE);
7209                 break;
7210         default:
7211                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7212                 ret = -ENOSYS;
7213                 break;
7214         }
7215         return ret;
7216 }
7217
7218 static int
7219 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7220                      enum rte_filter_type filter_type,
7221                      enum rte_filter_op filter_op,
7222                      void *arg)
7223 {
7224         int ret = 0;
7225
7226         if (dev == NULL)
7227                 return -EINVAL;
7228
7229         switch (filter_type) {
7230         case RTE_ETH_FILTER_NONE:
7231                 /* For global configuration */
7232                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7233                 break;
7234         case RTE_ETH_FILTER_HASH:
7235                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7236                 break;
7237         case RTE_ETH_FILTER_MACVLAN:
7238                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7239                 break;
7240         case RTE_ETH_FILTER_ETHERTYPE:
7241                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7242                 break;
7243         case RTE_ETH_FILTER_TUNNEL:
7244                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7245                 break;
7246         case RTE_ETH_FILTER_FDIR:
7247                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7248                 break;
7249         default:
7250                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7251                                                         filter_type);
7252                 ret = -EINVAL;
7253                 break;
7254         }
7255
7256         return ret;
7257 }
7258
7259 /*
7260  * As some registers wouldn't be reset unless a global hardware reset,
7261  * hardware initialization is needed to put those registers into an
7262  * expected initial state.
7263  */
7264 static void
7265 i40e_hw_init(struct i40e_hw *hw)
7266 {
7267         /* clear the PF Queue Filter control register */
7268         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
7269
7270         /* Disable symmetric hash per port */
7271         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7272 }
7273
7274 enum i40e_filter_pctype
7275 i40e_flowtype_to_pctype(uint16_t flow_type)
7276 {
7277         static const enum i40e_filter_pctype pctype_table[] = {
7278                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7279                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7280                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7281                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7282                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7283                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7284                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7285                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7286                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7287                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7288                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7289                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7290                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7291                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7292                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7293                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7294                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7295                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7296                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7297         };
7298
7299         return pctype_table[flow_type];
7300 }
7301
7302 uint16_t
7303 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7304 {
7305         static const uint16_t flowtype_table[] = {
7306                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7307                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7308                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7309                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7310                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7311                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7312                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7313                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7314                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7315                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7316                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7317                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7318                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7319                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7320                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7321                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7322                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7323                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7324                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7325         };
7326
7327         return flowtype_table[pctype];
7328 }
7329
7330 /*
7331  * On X710, performance number is far from the expectation on recent firmware
7332  * versions; on XL710, performance number is also far from the expectation on
7333  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7334  * mode is enabled and port MAC address is equal to the packet destination MAC
7335  * address. The fix for this issue may not be integrated in the following
7336  * firmware version. So the workaround in software driver is needed. It needs
7337  * to modify the initial values of 3 internal only registers for both X710 and
7338  * XL710. Note that the values for X710 or XL710 could be different, and the
7339  * workaround can be removed when it is fixed in firmware in the future.
7340  */
7341
7342 /* For both X710 and XL710 */
7343 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7344 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7345
7346 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7347 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7348
7349 /* For X710 */
7350 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7351 /* For XL710 */
7352 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7353 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7354
7355 static void
7356 i40e_configure_registers(struct i40e_hw *hw)
7357 {
7358         static struct {
7359                 uint32_t addr;
7360                 uint64_t val;
7361         } reg_table[] = {
7362                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7363                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7364                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7365         };
7366         uint64_t reg;
7367         uint32_t i;
7368         int ret;
7369
7370         for (i = 0; i < RTE_DIM(reg_table); i++) {
7371                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7372                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7373                                 reg_table[i].val =
7374                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7375                         else /* For X710 */
7376                                 reg_table[i].val =
7377                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7378                 }
7379
7380                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7381                                                         &reg, NULL);
7382                 if (ret < 0) {
7383                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7384                                                         reg_table[i].addr);
7385                         break;
7386                 }
7387                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7388                                                 reg_table[i].addr, reg);
7389                 if (reg == reg_table[i].val)
7390                         continue;
7391
7392                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7393                                                 reg_table[i].val, NULL);
7394                 if (ret < 0) {
7395                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7396                                 "address of 0x%"PRIx32, reg_table[i].val,
7397                                                         reg_table[i].addr);
7398                         break;
7399                 }
7400                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7401                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7402         }
7403 }
7404
7405 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7406 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7407 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7408 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7409 static int
7410 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7411 {
7412         uint32_t reg;
7413         int ret;
7414
7415         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7416                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7417                 return -EINVAL;
7418         }
7419
7420         /* Configure for double VLAN RX stripping */
7421         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7422         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7423                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7424                 ret = i40e_aq_debug_write_register(hw,
7425                                                    I40E_VSI_TSR(vsi->vsi_id),
7426                                                    reg, NULL);
7427                 if (ret < 0) {
7428                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7429                                     vsi->vsi_id);
7430                         return I40E_ERR_CONFIG;
7431                 }
7432         }
7433
7434         /* Configure for double VLAN TX insertion */
7435         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7436         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7437                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7438                 ret = i40e_aq_debug_write_register(hw,
7439                                                    I40E_VSI_L2TAGSTXVALID(
7440                                                    vsi->vsi_id), reg, NULL);
7441                 if (ret < 0) {
7442                         PMD_DRV_LOG(ERR, "Failed to update "
7443                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7444                         return I40E_ERR_CONFIG;
7445                 }
7446         }
7447
7448         return 0;
7449 }
7450
7451 /**
7452  * i40e_aq_add_mirror_rule
7453  * @hw: pointer to the hardware structure
7454  * @seid: VEB seid to add mirror rule to
7455  * @dst_id: destination vsi seid
7456  * @entries: Buffer which contains the entities to be mirrored
7457  * @count: number of entities contained in the buffer
7458  * @rule_id:the rule_id of the rule to be added
7459  *
7460  * Add a mirror rule for a given veb.
7461  *
7462  **/
7463 static enum i40e_status_code
7464 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7465                         uint16_t seid, uint16_t dst_id,
7466                         uint16_t rule_type, uint16_t *entries,
7467                         uint16_t count, uint16_t *rule_id)
7468 {
7469         struct i40e_aq_desc desc;
7470         struct i40e_aqc_add_delete_mirror_rule cmd;
7471         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7472                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7473                 &desc.params.raw;
7474         uint16_t buff_len;
7475         enum i40e_status_code status;
7476
7477         i40e_fill_default_direct_cmd_desc(&desc,
7478                                           i40e_aqc_opc_add_mirror_rule);
7479         memset(&cmd, 0, sizeof(cmd));
7480
7481         buff_len = sizeof(uint16_t) * count;
7482         desc.datalen = rte_cpu_to_le_16(buff_len);
7483         if (buff_len > 0)
7484                 desc.flags |= rte_cpu_to_le_16(
7485                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7486         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7487                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7488         cmd.num_entries = rte_cpu_to_le_16(count);
7489         cmd.seid = rte_cpu_to_le_16(seid);
7490         cmd.destination = rte_cpu_to_le_16(dst_id);
7491
7492         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7493         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7494         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7495                          "rule_id = %u"
7496                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7497                          hw->aq.asq_last_status, resp->rule_id,
7498                          resp->mirror_rules_used, resp->mirror_rules_free);
7499         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7500
7501         return status;
7502 }
7503
7504 /**
7505  * i40e_aq_del_mirror_rule
7506  * @hw: pointer to the hardware structure
7507  * @seid: VEB seid to add mirror rule to
7508  * @entries: Buffer which contains the entities to be mirrored
7509  * @count: number of entities contained in the buffer
7510  * @rule_id:the rule_id of the rule to be delete
7511  *
7512  * Delete a mirror rule for a given veb.
7513  *
7514  **/
7515 static enum i40e_status_code
7516 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7517                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7518                 uint16_t count, uint16_t rule_id)
7519 {
7520         struct i40e_aq_desc desc;
7521         struct i40e_aqc_add_delete_mirror_rule cmd;
7522         uint16_t buff_len = 0;
7523         enum i40e_status_code status;
7524         void *buff = NULL;
7525
7526         i40e_fill_default_direct_cmd_desc(&desc,
7527                                           i40e_aqc_opc_delete_mirror_rule);
7528         memset(&cmd, 0, sizeof(cmd));
7529         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7530                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7531                                                           I40E_AQ_FLAG_RD));
7532                 cmd.num_entries = count;
7533                 buff_len = sizeof(uint16_t) * count;
7534                 desc.datalen = rte_cpu_to_le_16(buff_len);
7535                 buff = (void *)entries;
7536         } else
7537                 /* rule id is filled in destination field for deleting mirror rule */
7538                 cmd.destination = rte_cpu_to_le_16(rule_id);
7539
7540         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7541                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7542         cmd.seid = rte_cpu_to_le_16(seid);
7543
7544         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7545         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7546
7547         return status;
7548 }
7549
7550 /**
7551  * i40e_mirror_rule_set
7552  * @dev: pointer to the hardware structure
7553  * @mirror_conf: mirror rule info
7554  * @sw_id: mirror rule's sw_id
7555  * @on: enable/disable
7556  *
7557  * set a mirror rule.
7558  *
7559  **/
7560 static int
7561 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7562                         struct rte_eth_mirror_conf *mirror_conf,
7563                         uint8_t sw_id, uint8_t on)
7564 {
7565         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7566         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7567         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7568         struct i40e_mirror_rule *parent = NULL;
7569         uint16_t seid, dst_seid, rule_id;
7570         uint16_t i, j = 0;
7571         int ret;
7572
7573         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7574
7575         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7576                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7577                         " without veb or vfs.");
7578                 return -ENOSYS;
7579         }
7580         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7581                 PMD_DRV_LOG(ERR, "mirror table is full.");
7582                 return -ENOSPC;
7583         }
7584         if (mirror_conf->dst_pool > pf->vf_num) {
7585                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7586                                  mirror_conf->dst_pool);
7587                 return -EINVAL;
7588         }
7589
7590         seid = pf->main_vsi->veb->seid;
7591
7592         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7593                 if (sw_id <= it->index) {
7594                         mirr_rule = it;
7595                         break;
7596                 }
7597                 parent = it;
7598         }
7599         if (mirr_rule && sw_id == mirr_rule->index) {
7600                 if (on) {
7601                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7602                         return -EEXIST;
7603                 } else {
7604                         ret = i40e_aq_del_mirror_rule(hw, seid,
7605                                         mirr_rule->rule_type,
7606                                         mirr_rule->entries,
7607                                         mirr_rule->num_entries, mirr_rule->id);
7608                         if (ret < 0) {
7609                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7610                                                    " ret = %d, aq_err = %d.",
7611                                                    ret, hw->aq.asq_last_status);
7612                                 return -ENOSYS;
7613                         }
7614                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7615                         rte_free(mirr_rule);
7616                         pf->nb_mirror_rule--;
7617                         return 0;
7618                 }
7619         } else if (!on) {
7620                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7621                 return -ENOENT;
7622         }
7623
7624         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7625                                 sizeof(struct i40e_mirror_rule) , 0);
7626         if (!mirr_rule) {
7627                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7628                 return I40E_ERR_NO_MEMORY;
7629         }
7630         switch (mirror_conf->rule_type) {
7631         case ETH_MIRROR_VLAN:
7632                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7633                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7634                                 mirr_rule->entries[j] =
7635                                         mirror_conf->vlan.vlan_id[i];
7636                                 j++;
7637                         }
7638                 }
7639                 if (j == 0) {
7640                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7641                         rte_free(mirr_rule);
7642                         return -EINVAL;
7643                 }
7644                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7645                 break;
7646         case ETH_MIRROR_VIRTUAL_POOL_UP:
7647         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7648                 /* check if the specified pool bit is out of range */
7649                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7650                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7651                         rte_free(mirr_rule);
7652                         return -EINVAL;
7653                 }
7654                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7655                         if (mirror_conf->pool_mask & (1ULL << i)) {
7656                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7657                                 j++;
7658                         }
7659                 }
7660                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7661                         /* add pf vsi to entries */
7662                         mirr_rule->entries[j] = pf->main_vsi_seid;
7663                         j++;
7664                 }
7665                 if (j == 0) {
7666                         PMD_DRV_LOG(ERR, "pool is not specified.");
7667                         rte_free(mirr_rule);
7668                         return -EINVAL;
7669                 }
7670                 /* egress and ingress in aq commands means from switch but not port */
7671                 mirr_rule->rule_type =
7672                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7673                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7674                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7675                 break;
7676         case ETH_MIRROR_UPLINK_PORT:
7677                 /* egress and ingress in aq commands means from switch but not port*/
7678                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7679                 break;
7680         case ETH_MIRROR_DOWNLINK_PORT:
7681                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7682                 break;
7683         default:
7684                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7685                         mirror_conf->rule_type);
7686                 rte_free(mirr_rule);
7687                 return -EINVAL;
7688         }
7689
7690         /* If the dst_pool is equal to vf_num, consider it as PF */
7691         if (mirror_conf->dst_pool == pf->vf_num)
7692                 dst_seid = pf->main_vsi_seid;
7693         else
7694                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7695
7696         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7697                                       mirr_rule->rule_type, mirr_rule->entries,
7698                                       j, &rule_id);
7699         if (ret < 0) {
7700                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7701                                    " ret = %d, aq_err = %d.",
7702                                    ret, hw->aq.asq_last_status);
7703                 rte_free(mirr_rule);
7704                 return -ENOSYS;
7705         }
7706
7707         mirr_rule->index = sw_id;
7708         mirr_rule->num_entries = j;
7709         mirr_rule->id = rule_id;
7710         mirr_rule->dst_vsi_seid = dst_seid;
7711
7712         if (parent)
7713                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7714         else
7715                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7716
7717         pf->nb_mirror_rule++;
7718         return 0;
7719 }
7720
7721 /**
7722  * i40e_mirror_rule_reset
7723  * @dev: pointer to the device
7724  * @sw_id: mirror rule's sw_id
7725  *
7726  * reset a mirror rule.
7727  *
7728  **/
7729 static int
7730 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7731 {
7732         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7733         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7734         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7735         uint16_t seid;
7736         int ret;
7737
7738         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7739
7740         seid = pf->main_vsi->veb->seid;
7741
7742         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7743                 if (sw_id == it->index) {
7744                         mirr_rule = it;
7745                         break;
7746                 }
7747         }
7748         if (mirr_rule) {
7749                 ret = i40e_aq_del_mirror_rule(hw, seid,
7750                                 mirr_rule->rule_type,
7751                                 mirr_rule->entries,
7752                                 mirr_rule->num_entries, mirr_rule->id);
7753                 if (ret < 0) {
7754                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7755                                            " status = %d, aq_err = %d.",
7756                                            ret, hw->aq.asq_last_status);
7757                         return -ENOSYS;
7758                 }
7759                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7760                 rte_free(mirr_rule);
7761                 pf->nb_mirror_rule--;
7762         } else {
7763                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7764                 return -ENOENT;
7765         }
7766         return 0;
7767 }
7768
7769 static uint64_t
7770 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
7771 {
7772         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7773         uint64_t systim_cycles;
7774
7775         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
7776         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
7777                         << 32;
7778
7779         return systim_cycles;
7780 }
7781
7782 static uint64_t
7783 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
7784 {
7785         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7786         uint64_t rx_tstamp;
7787
7788         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7789         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
7790                         << 32;
7791
7792         return rx_tstamp;
7793 }
7794
7795 static uint64_t
7796 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7797 {
7798         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7799         uint64_t tx_tstamp;
7800
7801         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
7802         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
7803                         << 32;
7804
7805         return tx_tstamp;
7806 }
7807
7808 static void
7809 i40e_start_timecounters(struct rte_eth_dev *dev)
7810 {
7811         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7812         struct i40e_adapter *adapter =
7813                         (struct i40e_adapter *)dev->data->dev_private;
7814         struct rte_eth_link link;
7815         uint32_t tsync_inc_l;
7816         uint32_t tsync_inc_h;
7817
7818         /* Get current link speed. */
7819         memset(&link, 0, sizeof(link));
7820         i40e_dev_link_update(dev, 1);
7821         rte_i40e_dev_atomic_read_link_status(dev, &link);
7822
7823         switch (link.link_speed) {
7824         case ETH_LINK_SPEED_40G:
7825                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
7826                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
7827                 break;
7828         case ETH_LINK_SPEED_10G:
7829                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
7830                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
7831                 break;
7832         case ETH_LINK_SPEED_1000:
7833                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
7834                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
7835                 break;
7836         default:
7837                 tsync_inc_l = 0x0;
7838                 tsync_inc_h = 0x0;
7839         }
7840
7841         /* Set the timesync increment value. */
7842         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
7843         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
7844
7845         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7846         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7847         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7848
7849         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7850         adapter->systime_tc.cc_shift = 0;
7851         adapter->systime_tc.nsec_mask = 0;
7852
7853         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7854         adapter->rx_tstamp_tc.cc_shift = 0;
7855         adapter->rx_tstamp_tc.nsec_mask = 0;
7856
7857         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7858         adapter->tx_tstamp_tc.cc_shift = 0;
7859         adapter->tx_tstamp_tc.nsec_mask = 0;
7860 }
7861
7862 static int
7863 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7864 {
7865         struct i40e_adapter *adapter =
7866                         (struct i40e_adapter *)dev->data->dev_private;
7867
7868         adapter->systime_tc.nsec += delta;
7869         adapter->rx_tstamp_tc.nsec += delta;
7870         adapter->tx_tstamp_tc.nsec += delta;
7871
7872         return 0;
7873 }
7874
7875 static int
7876 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7877 {
7878         uint64_t ns;
7879         struct i40e_adapter *adapter =
7880                         (struct i40e_adapter *)dev->data->dev_private;
7881
7882         ns = rte_timespec_to_ns(ts);
7883
7884         /* Set the timecounters to a new value. */
7885         adapter->systime_tc.nsec = ns;
7886         adapter->rx_tstamp_tc.nsec = ns;
7887         adapter->tx_tstamp_tc.nsec = ns;
7888
7889         return 0;
7890 }
7891
7892 static int
7893 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7894 {
7895         uint64_t ns, systime_cycles;
7896         struct i40e_adapter *adapter =
7897                         (struct i40e_adapter *)dev->data->dev_private;
7898
7899         systime_cycles = i40e_read_systime_cyclecounter(dev);
7900         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7901         *ts = rte_ns_to_timespec(ns);
7902
7903         return 0;
7904 }
7905
7906 static int
7907 i40e_timesync_enable(struct rte_eth_dev *dev)
7908 {
7909         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7910         uint32_t tsync_ctl_l;
7911         uint32_t tsync_ctl_h;
7912
7913         /* Stop the timesync system time. */
7914         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7915         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7916         /* Reset the timesync system time value. */
7917         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
7918         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
7919
7920         i40e_start_timecounters(dev);
7921
7922         /* Clear timesync registers. */
7923         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7924         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7925         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
7926         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
7927         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
7928         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
7929
7930         /* Enable timestamping of PTP packets. */
7931         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7932         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
7933
7934         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7935         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
7936         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
7937
7938         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7939         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7940
7941         return 0;
7942 }
7943
7944 static int
7945 i40e_timesync_disable(struct rte_eth_dev *dev)
7946 {
7947         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7948         uint32_t tsync_ctl_l;
7949         uint32_t tsync_ctl_h;
7950
7951         /* Disable timestamping of transmitted PTP packets. */
7952         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7953         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
7954
7955         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7956         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
7957
7958         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7959         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7960
7961         /* Reset the timesync increment value. */
7962         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7963         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7964
7965         return 0;
7966 }
7967
7968 static int
7969 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7970                                 struct timespec *timestamp, uint32_t flags)
7971 {
7972         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7973         struct i40e_adapter *adapter =
7974                 (struct i40e_adapter *)dev->data->dev_private;
7975
7976         uint32_t sync_status;
7977         uint32_t index = flags & 0x03;
7978         uint64_t rx_tstamp_cycles;
7979         uint64_t ns;
7980
7981         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
7982         if ((sync_status & (1 << index)) == 0)
7983                 return -EINVAL;
7984
7985         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
7986         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7987         *timestamp = rte_ns_to_timespec(ns);
7988
7989         return 0;
7990 }
7991
7992 static int
7993 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7994                                 struct timespec *timestamp)
7995 {
7996         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7997         struct i40e_adapter *adapter =
7998                 (struct i40e_adapter *)dev->data->dev_private;
7999
8000         uint32_t sync_status;
8001         uint64_t tx_tstamp_cycles;
8002         uint64_t ns;
8003
8004         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8005         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8006                 return -EINVAL;
8007
8008         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8009         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8010         *timestamp = rte_ns_to_timespec(ns);
8011
8012         return 0;
8013 }
8014
8015 /*
8016  * i40e_parse_dcb_configure - parse dcb configure from user
8017  * @dev: the device being configured
8018  * @dcb_cfg: pointer of the result of parse
8019  * @*tc_map: bit map of enabled traffic classes
8020  *
8021  * Returns 0 on success, negative value on failure
8022  */
8023 static int
8024 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8025                          struct i40e_dcbx_config *dcb_cfg,
8026                          uint8_t *tc_map)
8027 {
8028         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8029         uint8_t i, tc_bw, bw_lf;
8030
8031         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8032
8033         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8034         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8035                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8036                 return -EINVAL;
8037         }
8038
8039         /* assume each tc has the same bw */
8040         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8041         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8042                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8043         /* to ensure the sum of tcbw is equal to 100 */
8044         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8045         for (i = 0; i < bw_lf; i++)
8046                 dcb_cfg->etscfg.tcbwtable[i]++;
8047
8048         /* assume each tc has the same Transmission Selection Algorithm */
8049         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8050                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8051
8052         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8053                 dcb_cfg->etscfg.prioritytable[i] =
8054                                 dcb_rx_conf->dcb_tc[i];
8055
8056         /* FW needs one App to configure HW */
8057         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8058         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8059         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8060         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8061
8062         if (dcb_rx_conf->nb_tcs == 0)
8063                 *tc_map = 1; /* tc0 only */
8064         else
8065                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8066
8067         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8068                 dcb_cfg->pfc.willing = 0;
8069                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8070                 dcb_cfg->pfc.pfcenable = *tc_map;
8071         }
8072         return 0;
8073 }
8074
8075
8076 static enum i40e_status_code
8077 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8078                               struct i40e_aqc_vsi_properties_data *info,
8079                               uint8_t enabled_tcmap)
8080 {
8081         enum i40e_status_code ret;
8082         int i, total_tc = 0;
8083         uint16_t qpnum_per_tc, bsf, qp_idx;
8084         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8085
8086         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8087         if (ret != I40E_SUCCESS)
8088                 return ret;
8089
8090         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8091                 if (enabled_tcmap & (1 << i))
8092                         total_tc++;
8093         }
8094         if (total_tc == 0)
8095                 total_tc = 1;
8096         vsi->enabled_tc = enabled_tcmap;
8097
8098         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
8099         /* Number of queues per enabled TC */
8100         if (qpnum_per_tc == 0) {
8101                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8102                 return I40E_ERR_INVALID_QP_ID;
8103         }
8104         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8105                                 I40E_MAX_Q_PER_TC);
8106         bsf = rte_bsf32(qpnum_per_tc);
8107
8108         /**
8109          * Configure TC and queue mapping parameters, for enabled TC,
8110          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8111          * default queue will serve it.
8112          */
8113         qp_idx = 0;
8114         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8115                 if (vsi->enabled_tc & (1 << i)) {
8116                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8117                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8118                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8119                         qp_idx += qpnum_per_tc;
8120                 } else
8121                         info->tc_mapping[i] = 0;
8122         }
8123
8124         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8125         if (vsi->type == I40E_VSI_SRIOV) {
8126                 info->mapping_flags |=
8127                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8128                 for (i = 0; i < vsi->nb_qps; i++)
8129                         info->queue_mapping[i] =
8130                                 rte_cpu_to_le_16(vsi->base_queue + i);
8131         } else {
8132                 info->mapping_flags |=
8133                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8134                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8135         }
8136         info->valid_sections |=
8137                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8138
8139         return I40E_SUCCESS;
8140 }
8141
8142 /*
8143  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8144  * @vsi: VSI to be configured
8145  * @tc_map: enabled TC bitmap
8146  *
8147  * Returns 0 on success, negative value on failure
8148  */
8149 static enum i40e_status_code
8150 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
8151 {
8152         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8153         struct i40e_vsi_context ctxt;
8154         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8155         enum i40e_status_code ret = I40E_SUCCESS;
8156         int i;
8157
8158         /* Check if enabled_tc is same as existing or new TCs */
8159         if (vsi->enabled_tc == tc_map)
8160                 return ret;
8161
8162         /* configure tc bandwidth */
8163         memset(&bw_data, 0, sizeof(bw_data));
8164         bw_data.tc_valid_bits = tc_map;
8165         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8166         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8167                 if (tc_map & BIT_ULL(i))
8168                         bw_data.tc_bw_credits[i] = 1;
8169         }
8170         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8171         if (ret) {
8172                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8173                         " per TC failed = %d",
8174                         hw->aq.asq_last_status);
8175                 goto out;
8176         }
8177         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8178                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8179
8180         /* Update Queue Pairs Mapping for currently enabled UPs */
8181         ctxt.seid = vsi->seid;
8182         ctxt.pf_num = hw->pf_id;
8183         ctxt.vf_num = 0;
8184         ctxt.uplink_seid = vsi->uplink_seid;
8185         ctxt.info = vsi->info;
8186         i40e_get_cap(hw);
8187         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8188         if (ret)
8189                 goto out;
8190
8191         /* Update the VSI after updating the VSI queue-mapping information */
8192         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8193         if (ret) {
8194                 PMD_INIT_LOG(ERR, "Failed to configure "
8195                             "TC queue mapping = %d",
8196                             hw->aq.asq_last_status);
8197                 goto out;
8198         }
8199         /* update the local VSI info with updated queue map */
8200         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8201                                         sizeof(vsi->info.tc_mapping));
8202         (void)rte_memcpy(&vsi->info.queue_mapping,
8203                         &ctxt.info.queue_mapping,
8204                 sizeof(vsi->info.queue_mapping));
8205         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8206         vsi->info.valid_sections = 0;
8207
8208         /* query and update current VSI BW information */
8209         ret = i40e_vsi_get_bw_config(vsi);
8210         if (ret) {
8211                 PMD_INIT_LOG(ERR,
8212                          "Failed updating vsi bw info, err %s aq_err %s",
8213                          i40e_stat_str(hw, ret),
8214                          i40e_aq_str(hw, hw->aq.asq_last_status));
8215                 goto out;
8216         }
8217
8218         vsi->enabled_tc = tc_map;
8219
8220 out:
8221         return ret;
8222 }
8223
8224 /*
8225  * i40e_dcb_hw_configure - program the dcb setting to hw
8226  * @pf: pf the configuration is taken on
8227  * @new_cfg: new configuration
8228  * @tc_map: enabled TC bitmap
8229  *
8230  * Returns 0 on success, negative value on failure
8231  */
8232 static enum i40e_status_code
8233 i40e_dcb_hw_configure(struct i40e_pf *pf,
8234                       struct i40e_dcbx_config *new_cfg,
8235                       uint8_t tc_map)
8236 {
8237         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8238         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8239         struct i40e_vsi *main_vsi = pf->main_vsi;
8240         struct i40e_vsi_list *vsi_list;
8241         enum i40e_status_code ret;
8242         int i;
8243         uint32_t val;
8244
8245         /* Use the FW API if FW > v4.4*/
8246         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8247               (hw->aq.fw_maj_ver >= 5))) {
8248                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8249                                   " to configure DCB");
8250                 return I40E_ERR_FIRMWARE_API_VERSION;
8251         }
8252
8253         /* Check if need reconfiguration */
8254         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8255                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8256                 return I40E_SUCCESS;
8257         }
8258
8259         /* Copy the new config to the current config */
8260         *old_cfg = *new_cfg;
8261         old_cfg->etsrec = old_cfg->etscfg;
8262         ret = i40e_set_dcb_config(hw);
8263         if (ret) {
8264                 PMD_INIT_LOG(ERR,
8265                          "Set DCB Config failed, err %s aq_err %s\n",
8266                          i40e_stat_str(hw, ret),
8267                          i40e_aq_str(hw, hw->aq.asq_last_status));
8268                 return ret;
8269         }
8270         /* set receive Arbiter to RR mode and ETS scheme by default */
8271         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8272                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8273                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8274                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8275                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8276                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8277                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8278                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8279                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8280                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8281                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8282                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8283                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8284         }
8285         /* get local mib to check whether it is configured correctly */
8286         /* IEEE mode */
8287         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8288         /* Get Local DCB Config */
8289         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8290                                      &hw->local_dcbx_config);
8291
8292         /* Update each VSI */
8293         i40e_vsi_config_tc(main_vsi, tc_map);
8294         if (main_vsi->veb) {
8295                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8296                         /* Beside main VSI, only enable default
8297                          * TC for other VSIs
8298                          */
8299                         ret = i40e_vsi_config_tc(vsi_list->vsi,
8300                                                 I40E_DEFAULT_TCMAP);
8301                         if (ret)
8302                                 PMD_INIT_LOG(WARNING,
8303                                          "Failed configuring TC for VSI seid=%d\n",
8304                                          vsi_list->vsi->seid);
8305                         /* continue */
8306                 }
8307         }
8308         return I40E_SUCCESS;
8309 }
8310
8311 /*
8312  * i40e_dcb_init_configure - initial dcb config
8313  * @dev: device being configured
8314  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8315  *
8316  * Returns 0 on success, negative value on failure
8317  */
8318 static int
8319 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8320 {
8321         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8322         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8323         int ret = 0;
8324
8325         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8326                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8327                 return -ENOTSUP;
8328         }
8329
8330         /* DCB initialization:
8331          * Update DCB configuration from the Firmware and configure
8332          * LLDP MIB change event.
8333          */
8334         if (sw_dcb == TRUE) {
8335                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8336                 if (ret != I40E_SUCCESS)
8337                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8338
8339                 ret = i40e_init_dcb(hw);
8340                 /* if sw_dcb, lldp agent is stopped, the return from
8341                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8342                  * adminq status.
8343                  */
8344                 if (ret != I40E_SUCCESS &&
8345                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8346                         memset(&hw->local_dcbx_config, 0,
8347                                 sizeof(struct i40e_dcbx_config));
8348                         /* set dcb default configuration */
8349                         hw->local_dcbx_config.etscfg.willing = 0;
8350                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8351                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8352                         hw->local_dcbx_config.etscfg.tsatable[0] =
8353                                                 I40E_IEEE_TSA_ETS;
8354                         hw->local_dcbx_config.etsrec =
8355                                 hw->local_dcbx_config.etscfg;
8356                         hw->local_dcbx_config.pfc.willing = 0;
8357                         hw->local_dcbx_config.pfc.pfccap =
8358                                                 I40E_MAX_TRAFFIC_CLASS;
8359                         /* FW needs one App to configure HW */
8360                         hw->local_dcbx_config.numapps = 1;
8361                         hw->local_dcbx_config.app[0].selector =
8362                                                 I40E_APP_SEL_ETHTYPE;
8363                         hw->local_dcbx_config.app[0].priority = 3;
8364                         hw->local_dcbx_config.app[0].protocolid =
8365                                                 I40E_APP_PROTOID_FCOE;
8366                         ret = i40e_set_dcb_config(hw);
8367                         if (ret) {
8368                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8369                                         " err = %d, aq_err = %d.", ret,
8370                                           hw->aq.asq_last_status);
8371                                 return -ENOSYS;
8372                         }
8373                 } else {
8374                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8375                                           " aq_err = %d.", ret,
8376                                           hw->aq.asq_last_status);
8377                         return -ENOTSUP;
8378                 }
8379         } else {
8380                 ret = i40e_aq_start_lldp(hw, NULL);
8381                 if (ret != I40E_SUCCESS)
8382                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8383
8384                 ret = i40e_init_dcb(hw);
8385                 if (!ret) {
8386                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8387                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8388                                                   " DCBX offload.");
8389                                 return -ENOTSUP;
8390                         }
8391                 } else {
8392                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8393                                           " aq_err = %d.", ret,
8394                                           hw->aq.asq_last_status);
8395                         return -ENOTSUP;
8396                 }
8397         }
8398         return 0;
8399 }
8400
8401 /*
8402  * i40e_dcb_setup - setup dcb related config
8403  * @dev: device being configured
8404  *
8405  * Returns 0 on success, negative value on failure
8406  */
8407 static int
8408 i40e_dcb_setup(struct rte_eth_dev *dev)
8409 {
8410         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8411         struct i40e_dcbx_config dcb_cfg;
8412         uint8_t tc_map = 0;
8413         int ret = 0;
8414
8415         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8416                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8417                 return -ENOTSUP;
8418         }
8419
8420         if (pf->vf_num != 0 ||
8421             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8422                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8423
8424         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8425         if (ret) {
8426                 PMD_INIT_LOG(ERR, "invalid dcb config");
8427                 return -EINVAL;
8428         }
8429         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8430         if (ret) {
8431                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8432                 return -ENOSYS;
8433         }
8434
8435         return 0;
8436 }
8437
8438 static int
8439 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8440                       struct rte_eth_dcb_info *dcb_info)
8441 {
8442         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8443         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8444         struct i40e_vsi *vsi = pf->main_vsi;
8445         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8446         uint16_t bsf, tc_mapping;
8447         int i;
8448
8449         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8450                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8451         else
8452                 dcb_info->nb_tcs = 1;
8453         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8454                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8455         for (i = 0; i < dcb_info->nb_tcs; i++)
8456                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8457
8458         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8459                 if (vsi->enabled_tc & (1 << i)) {
8460                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8461                         /* only main vsi support multi TCs */
8462                         dcb_info->tc_queue.tc_rxq[0][i].base =
8463                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8464                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8465                         dcb_info->tc_queue.tc_txq[0][i].base =
8466                                 dcb_info->tc_queue.tc_rxq[0][i].base;
8467                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8468                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8469                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8470                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8471                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
8472                 }
8473         }
8474
8475         return 0;
8476 }
8477
8478 static int
8479 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8480 {
8481         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8482         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8483         uint16_t interval =
8484                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8485         uint16_t msix_intr;
8486
8487         msix_intr = intr_handle->intr_vec[queue_id];
8488         if (msix_intr == I40E_MISC_VEC_ID)
8489                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8490                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8491                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8492                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8493                                (interval <<
8494                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8495         else
8496                 I40E_WRITE_REG(hw,
8497                                I40E_PFINT_DYN_CTLN(msix_intr -
8498                                                    I40E_RX_VEC_START),
8499                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8500                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8501                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8502                                (interval <<
8503                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8504
8505         I40E_WRITE_FLUSH(hw);
8506         rte_intr_enable(&dev->pci_dev->intr_handle);
8507
8508         return 0;
8509 }
8510
8511 static int
8512 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8513 {
8514         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8515         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8516         uint16_t msix_intr;
8517
8518         msix_intr = intr_handle->intr_vec[queue_id];
8519         if (msix_intr == I40E_MISC_VEC_ID)
8520                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8521         else
8522                 I40E_WRITE_REG(hw,
8523                                I40E_PFINT_DYN_CTLN(msix_intr -
8524                                                    I40E_RX_VEC_START),
8525                                0);
8526         I40E_WRITE_FLUSH(hw);
8527
8528         return 0;
8529 }