drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  47 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  48
  49 #define I40E_CLEAR_PXE_WAIT_MS     200
  50
  51 /* Maximun number of capability elements */
  52 #define I40E_MAX_CAP_ELE_NUM       128
  53
  54 /* Wait count and interval */
  55 #define I40E_CHK_Q_ENA_COUNT       1000
  56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  57
  58 /* Maximun number of VSI */
  59 #define I40E_MAX_NUM_VSIS          (384UL)
  60
  61 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  62
  63 /* Flow control default timer */
  64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  65
  66 /* Flow control enable fwd bit */
  67 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  68
  69 /* Receive Packet Buffer size */
  70 #define I40E_RXPBSIZE (968 * 1024)
  71
  72 /* Kilobytes shift */
  73 #define I40E_KILOSHIFT 10
  74
  75 /* Flow control default high water */
  76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Flow control default low water */
  79 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  80
  81 /* Receive Average Packet Size in Byte*/
  82 #define I40E_PACKET_AVERAGE_SIZE 128
  83
  84 /* Mask of PF interrupt causes */
  85 #define I40E_PFINT_ICR0_ENA_MASK ( \
  86                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  87                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  90                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 /* Additional timesync values. */
 110 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 111 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 112 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 113 #define I40E_PRTTSYN_TSYNENA     0x80000000
 114 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 115 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 116
 117 /**
 118  * Below are values for writing un-exposed registers suggested
 119  * by silicon experts
 120  */
 121 /* Destination MAC address */
 122 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 123 /* Source MAC address */
 124 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 126 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 128 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 129 /* Single VLAN tag in the inner L2 header */
 130 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 131 /* Source IPv4 address */
 132 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 133 /* Destination IPv4 address */
 134 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 135 /* Source IPv4 address for X722 */
 136 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 137 /* Destination IPv4 address for X722 */
 138 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 139 /* IPv4 Protocol for X722 */
 140 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 141 /* IPv4 Time to Live for X722 */
 142 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 143 /* IPv4 Type of Service (TOS) */
 144 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 145 /* IPv4 Protocol */
 146 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 147 /* IPv4 Time to Live */
 148 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 149 /* Source IPv6 address */
 150 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 151 /* Destination IPv6 address */
 152 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 153 /* IPv6 Traffic Class (TC) */
 154 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 155 /* IPv6 Next Header */
 156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 157 /* IPv6 Hop Limit */
 158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 159 /* Source L4 port */
 160 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 161 /* Destination L4 port */
 162 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 163 /* SCTP verification tag */
 164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 167 /* Source port of tunneling UDP */
 168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 169 /* Destination port of tunneling UDP */
 170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 171 /* UDP Tunneling ID, NVGRE/GRE key */
 172 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 173 /* Last ether type */
 174 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 175 /* Tunneling outer destination IPv4 address */
 176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 177 /* Tunneling outer destination IPv6 address */
 178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 179 /* 1st word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 181 /* 2nd word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 183 /* 3rd word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 185 /* 4th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 187 /* 5th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 189 /* 6th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 191 /* 7th word of flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 193 /* 8th word of flex payload */
 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 195 /* all 8 words flex payload */
 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 197 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 198
 199 #define I40E_TRANSLATE_INSET 0
 200 #define I40E_TRANSLATE_REG   1
 201
 202 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 203 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 204 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 205 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 207 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 208
 209 /* PCI offset for querying capability */
 210 #define PCI_DEV_CAP_REG            0xA4
 211 /* PCI offset for enabling/disabling Extended Tag */
 212 #define PCI_DEV_CTRL_REG           0xA8
 213 /* Bit mask of Extended Tag capability */
 214 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 215 /* Bit shift of Extended Tag enable/disable */
 216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 217 /* Bit mask of Extended Tag enable/disable */
 218 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 219
 220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 222 static int i40e_dev_configure(struct rte_eth_dev *dev);
 223 static int i40e_dev_start(struct rte_eth_dev *dev);
 224 static void i40e_dev_stop(struct rte_eth_dev *dev);
 225 static void i40e_dev_close(struct rte_eth_dev *dev);
 226 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 227 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 228 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 229 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 230 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 234                                struct rte_eth_stats *stats);
 235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 236                                struct rte_eth_xstat *xstats, unsigned n);
 237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 238                                      struct rte_eth_xstat_name *xstats_names,
 239                                      unsigned limit);
 240 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 244                              struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct rte_ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static void i40e_dev_alarm_handler(void *param);
 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 294                                 uint32_t base, uint32_t num);
 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 297                         uint32_t base);
 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 299                         uint16_t num);
 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 301 static int i40e_veb_release(struct i40e_veb *veb);
 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 303                                                 struct i40e_vsi *vsi);
 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static int i40e_get_module_info(struct rte_eth_dev *dev,
 374                                 struct rte_eth_dev_module_info *modinfo);
 375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 376                                   struct rte_dev_eeprom_info *info);
 377
 378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 379                                       struct rte_ether_addr *mac_addr);
 380
 381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 382
 383 static int i40e_ethertype_filter_convert(
 384         const struct rte_eth_ethertype_filter *input,
 385         struct i40e_ethertype_filter *filter);
 386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 387                                    struct i40e_ethertype_filter *filter);
 388
 389 static int i40e_tunnel_filter_convert(
 390         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 391         struct i40e_tunnel_filter *tunnel_filter);
 392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 393                                 struct i40e_tunnel_filter *tunnel_filter);
 394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 395
 396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 398 static void i40e_filter_restore(struct i40e_pf *pf);
 399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 400
 401 int i40e_logtype_init;
 402 int i40e_logtype_driver;
 403 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
 404 int i40e_logtype_rx;
 405 #endif
 406 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
 407 int i40e_logtype_tx;
 408 #endif
 409 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
 410 int i40e_logtype_tx_free;
 411 #endif
 412
 413 static const char *const valid_keys[] = {
 414         ETH_I40E_FLOATING_VEB_ARG,
 415         ETH_I40E_FLOATING_VEB_LIST_ARG,
 416         ETH_I40E_SUPPORT_MULTI_DRIVER,
 417         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 418         ETH_I40E_USE_LATEST_VEC,
 419         ETH_I40E_VF_MSG_CFG,
 420         NULL};
 421
 422 static const struct rte_pci_id pci_id_i40e_map[] = {
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
 447         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
 448         { .vendor_id = 0, /* sentinel */ },
 449 };
 450
 451 static const struct eth_dev_ops i40e_eth_dev_ops = {
 452         .dev_configure                = i40e_dev_configure,
 453         .dev_start                    = i40e_dev_start,
 454         .dev_stop                     = i40e_dev_stop,
 455         .dev_close                    = i40e_dev_close,
 456         .dev_reset                    = i40e_dev_reset,
 457         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 458         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 459         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 460         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 461         .dev_set_link_up              = i40e_dev_set_link_up,
 462         .dev_set_link_down            = i40e_dev_set_link_down,
 463         .link_update                  = i40e_dev_link_update,
 464         .stats_get                    = i40e_dev_stats_get,
 465         .xstats_get                   = i40e_dev_xstats_get,
 466         .xstats_get_names             = i40e_dev_xstats_get_names,
 467         .stats_reset                  = i40e_dev_stats_reset,
 468         .xstats_reset                 = i40e_dev_stats_reset,
 469         .fw_version_get               = i40e_fw_version_get,
 470         .dev_infos_get                = i40e_dev_info_get,
 471         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 472         .vlan_filter_set              = i40e_vlan_filter_set,
 473         .vlan_tpid_set                = i40e_vlan_tpid_set,
 474         .vlan_offload_set             = i40e_vlan_offload_set,
 475         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 476         .vlan_pvid_set                = i40e_vlan_pvid_set,
 477         .rx_queue_start               = i40e_dev_rx_queue_start,
 478         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 479         .tx_queue_start               = i40e_dev_tx_queue_start,
 480         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 481         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 482         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 483         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 484         .rx_queue_release             = i40e_dev_rx_queue_release,
 485         .rx_queue_count               = i40e_dev_rx_queue_count,
 486         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 487         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 488         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 489         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 490         .tx_queue_release             = i40e_dev_tx_queue_release,
 491         .dev_led_on                   = i40e_dev_led_on,
 492         .dev_led_off                  = i40e_dev_led_off,
 493         .flow_ctrl_get                = i40e_flow_ctrl_get,
 494         .flow_ctrl_set                = i40e_flow_ctrl_set,
 495         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 496         .mac_addr_add                 = i40e_macaddr_add,
 497         .mac_addr_remove              = i40e_macaddr_remove,
 498         .reta_update                  = i40e_dev_rss_reta_update,
 499         .reta_query                   = i40e_dev_rss_reta_query,
 500         .rss_hash_update              = i40e_dev_rss_hash_update,
 501         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 502         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 503         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 504         .filter_ctrl                  = i40e_dev_filter_ctrl,
 505         .rxq_info_get                 = i40e_rxq_info_get,
 506         .txq_info_get                 = i40e_txq_info_get,
 507         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 508         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 509         .mirror_rule_set              = i40e_mirror_rule_set,
 510         .mirror_rule_reset            = i40e_mirror_rule_reset,
 511         .timesync_enable              = i40e_timesync_enable,
 512         .timesync_disable             = i40e_timesync_disable,
 513         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 514         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 515         .get_dcb_info                 = i40e_dev_get_dcb_info,
 516         .timesync_adjust_time         = i40e_timesync_adjust_time,
 517         .timesync_read_time           = i40e_timesync_read_time,
 518         .timesync_write_time          = i40e_timesync_write_time,
 519         .get_reg                      = i40e_get_regs,
 520         .get_eeprom_length            = i40e_get_eeprom_length,
 521         .get_eeprom                   = i40e_get_eeprom,
 522         .get_module_info              = i40e_get_module_info,
 523         .get_module_eeprom            = i40e_get_module_eeprom,
 524         .mac_addr_set                 = i40e_set_default_mac_addr,
 525         .mtu_set                      = i40e_dev_mtu_set,
 526         .tm_ops_get                   = i40e_tm_ops_get,
 527         .tx_done_cleanup              = i40e_tx_done_cleanup,
 528 };
 529
 530 /* store statistics names and its offset in stats structure */
 531 struct rte_i40e_xstats_name_off {
 532         char name[RTE_ETH_XSTATS_NAME_SIZE];
 533         unsigned offset;
 534 };
 535
 536 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 537         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 538         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 539         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 540         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 541         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 542                 rx_unknown_protocol)},
 543         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 544         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 545         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 546         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 547 };
 548
 549 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 550                 sizeof(rte_i40e_stats_strings[0]))
 551
 552 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 553         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 554                 tx_dropped_link_down)},
 555         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 556         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 557                 illegal_bytes)},
 558         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 559         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 560                 mac_local_faults)},
 561         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 562                 mac_remote_faults)},
 563         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 564                 rx_length_errors)},
 565         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 566         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 567         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 568         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 569         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 570         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 571                 rx_size_127)},
 572         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 573                 rx_size_255)},
 574         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 575                 rx_size_511)},
 576         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 577                 rx_size_1023)},
 578         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 579                 rx_size_1522)},
 580         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 581                 rx_size_big)},
 582         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 583                 rx_undersize)},
 584         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_oversize)},
 586         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 587                 mac_short_packet_dropped)},
 588         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 589                 rx_fragments)},
 590         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 591         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 592         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 593                 tx_size_127)},
 594         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 595                 tx_size_255)},
 596         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 597                 tx_size_511)},
 598         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 599                 tx_size_1023)},
 600         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 601                 tx_size_1522)},
 602         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 603                 tx_size_big)},
 604         {"rx_flow_director_atr_match_packets",
 605                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 606         {"rx_flow_director_sb_match_packets",
 607                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 608         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 609                 tx_lpi_status)},
 610         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 611                 rx_lpi_status)},
 612         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 613                 tx_lpi_count)},
 614         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 615                 rx_lpi_count)},
 616 };
 617
 618 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 619                 sizeof(rte_i40e_hw_port_strings[0]))
 620
 621 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 622         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xon_rx)},
 624         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xoff_rx)},
 626 };
 627
 628 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 629                 sizeof(rte_i40e_rxq_prio_strings[0]))
 630
 631 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 632         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 633                 priority_xon_tx)},
 634         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 635                 priority_xoff_tx)},
 636         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 637                 priority_xon_2_xoff)},
 638 };
 639
 640 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 641                 sizeof(rte_i40e_txq_prio_strings[0]))
 642
 643 static int
 644 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 645         struct rte_pci_device *pci_dev)
 646 {
 647         char name[RTE_ETH_NAME_MAX_LEN];
 648         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 649         int i, retval;
 650
 651         if (pci_dev->device.devargs) {
 652                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 653                                 &eth_da);
 654                 if (retval)
 655                         return retval;
 656         }
 657
 658         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 659                 sizeof(struct i40e_adapter),
 660                 eth_dev_pci_specific_init, pci_dev,
 661                 eth_i40e_dev_init, NULL);
 662
 663         if (retval || eth_da.nb_representor_ports < 1)
 664                 return retval;
 665
 666         /* probe VF representor ports */
 667         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 668                 pci_dev->device.name);
 669
 670         if (pf_ethdev == NULL)
 671                 return -ENODEV;
 672
 673         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 674                 struct i40e_vf_representor representor = {
 675                         .vf_id = eth_da.representor_ports[i],
 676                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 677                                 pf_ethdev->data->dev_private)->switch_domain_id,
 678                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 679                                 pf_ethdev->data->dev_private)
 680                 };
 681
 682                 /* representor port net_bdf_port */
 683                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 684                         pci_dev->device.name, eth_da.representor_ports[i]);
 685
 686                 retval = rte_eth_dev_create(&pci_dev->device, name,
 687                         sizeof(struct i40e_vf_representor), NULL, NULL,
 688                         i40e_vf_representor_init, &representor);
 689
 690                 if (retval)
 691                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 692                                 "representor %s.", name);
 693         }
 694
 695         return 0;
 696 }
 697
 698 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 699 {
 700         struct rte_eth_dev *ethdev;
 701
 702         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 703         if (!ethdev)
 704                 return 0;
 705
 706         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 707                 return rte_eth_dev_pci_generic_remove(pci_dev,
 708                                         i40e_vf_representor_uninit);
 709         else
 710                 return rte_eth_dev_pci_generic_remove(pci_dev,
 711                                                 eth_i40e_dev_uninit);
 712 }
 713
 714 static struct rte_pci_driver rte_i40e_pmd = {
 715         .id_table = pci_id_i40e_map,
 716         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 717         .probe = eth_i40e_pci_probe,
 718         .remove = eth_i40e_pci_remove,
 719 };
 720
 721 static inline void
 722 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 723                          uint32_t reg_val)
 724 {
 725         uint32_t ori_reg_val;
 726         struct rte_eth_dev *dev;
 727
 728         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 729         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 730         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 731         if (ori_reg_val != reg_val)
 732                 PMD_DRV_LOG(WARNING,
 733                             "i40e device %s changed global register [0x%08x]."
 734                             " original: 0x%08x, new: 0x%08x",
 735                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 736 }
 737
 738 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 739 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 740 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 741
 742 #ifndef I40E_GLQF_ORT
 743 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 744 #endif
 745 #ifndef I40E_GLQF_PIT
 746 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 747 #endif
 748 #ifndef I40E_GLQF_L3_MAP
 749 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 750 #endif
 751
 752 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 753 {
 754         /*
 755          * Initialize registers for parsing packet type of QinQ
 756          * This should be removed from code once proper
 757          * configuration API is added to avoid configuration conflicts
 758          * between ports of the same device.
 759          */
 760         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 761         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 762 }
 763
 764 static inline void i40e_config_automask(struct i40e_pf *pf)
 765 {
 766         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 767         uint32_t val;
 768
 769         /* INTENA flag is not auto-cleared for interrupt */
 770         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 771         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 772                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 773
 774         /* If support multi-driver, PF will use INT0. */
 775         if (!pf->support_multi_driver)
 776                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 777
 778         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 779 }
 780
 781 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 782
 783 /*
 784  * Add a ethertype filter to drop all flow control frames transmitted
 785  * from VSIs.
 786 */
 787 static void
 788 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 789 {
 790         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 791         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 792                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 793                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 794         int ret;
 795
 796         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 797                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 798                                 pf->main_vsi_seid, 0,
 799                                 TRUE, NULL, NULL);
 800         if (ret)
 801                 PMD_INIT_LOG(ERR,
 802                         "Failed to add filter to drop flow control frames from VSIs.");
 803 }
 804
 805 static int
 806 floating_veb_list_handler(__rte_unused const char *key,
 807                           const char *floating_veb_value,
 808                           void *opaque)
 809 {
 810         int idx = 0;
 811         unsigned int count = 0;
 812         char *end = NULL;
 813         int min, max;
 814         bool *vf_floating_veb = opaque;
 815
 816         while (isblank(*floating_veb_value))
 817                 floating_veb_value++;
 818
 819         /* Reset floating VEB configuration for VFs */
 820         for (idx = 0; idx < I40E_MAX_VF; idx++)
 821                 vf_floating_veb[idx] = false;
 822
 823         min = I40E_MAX_VF;
 824         do {
 825                 while (isblank(*floating_veb_value))
 826                         floating_veb_value++;
 827                 if (*floating_veb_value == '\0')
 828                         return -1;
 829                 errno = 0;
 830                 idx = strtoul(floating_veb_value, &end, 10);
 831                 if (errno || end == NULL)
 832                         return -1;
 833                 while (isblank(*end))
 834                         end++;
 835                 if (*end == '-') {
 836                         min = idx;
 837                 } else if ((*end == ';') || (*end == '\0')) {
 838                         max = idx;
 839                         if (min == I40E_MAX_VF)
 840                                 min = idx;
 841                         if (max >= I40E_MAX_VF)
 842                                 max = I40E_MAX_VF - 1;
 843                         for (idx = min; idx <= max; idx++) {
 844                                 vf_floating_veb[idx] = true;
 845                                 count++;
 846                         }
 847                         min = I40E_MAX_VF;
 848                 } else {
 849                         return -1;
 850                 }
 851                 floating_veb_value = end + 1;
 852         } while (*end != '\0');
 853
 854         if (count == 0)
 855                 return -1;
 856
 857         return 0;
 858 }
 859
 860 static void
 861 config_vf_floating_veb(struct rte_devargs *devargs,
 862                        uint16_t floating_veb,
 863                        bool *vf_floating_veb)
 864 {
 865         struct rte_kvargs *kvlist;
 866         int i;
 867         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 868
 869         if (!floating_veb)
 870                 return;
 871         /* All the VFs attach to the floating VEB by default
 872          * when the floating VEB is enabled.
 873          */
 874         for (i = 0; i < I40E_MAX_VF; i++)
 875                 vf_floating_veb[i] = true;
 876
 877         if (devargs == NULL)
 878                 return;
 879
 880         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 881         if (kvlist == NULL)
 882                 return;
 883
 884         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 885                 rte_kvargs_free(kvlist);
 886                 return;
 887         }
 888         /* When the floating_veb_list parameter exists, all the VFs
 889          * will attach to the legacy VEB firstly, then configure VFs
 890          * to the floating VEB according to the floating_veb_list.
 891          */
 892         if (rte_kvargs_process(kvlist, floating_veb_list,
 893                                floating_veb_list_handler,
 894                                vf_floating_veb) < 0) {
 895                 rte_kvargs_free(kvlist);
 896                 return;
 897         }
 898         rte_kvargs_free(kvlist);
 899 }
 900
 901 static int
 902 i40e_check_floating_handler(__rte_unused const char *key,
 903                             const char *value,
 904                             __rte_unused void *opaque)
 905 {
 906         if (strcmp(value, "1"))
 907                 return -1;
 908
 909         return 0;
 910 }
 911
 912 static int
 913 is_floating_veb_supported(struct rte_devargs *devargs)
 914 {
 915         struct rte_kvargs *kvlist;
 916         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 917
 918         if (devargs == NULL)
 919                 return 0;
 920
 921         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 922         if (kvlist == NULL)
 923                 return 0;
 924
 925         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 926                 rte_kvargs_free(kvlist);
 927                 return 0;
 928         }
 929         /* Floating VEB is enabled when there's key-value:
 930          * enable_floating_veb=1
 931          */
 932         if (rte_kvargs_process(kvlist, floating_veb_key,
 933                                i40e_check_floating_handler, NULL) < 0) {
 934                 rte_kvargs_free(kvlist);
 935                 return 0;
 936         }
 937         rte_kvargs_free(kvlist);
 938
 939         return 1;
 940 }
 941
 942 static void
 943 config_floating_veb(struct rte_eth_dev *dev)
 944 {
 945         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 946         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 947         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 948
 949         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 950
 951         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 952                 pf->floating_veb =
 953                         is_floating_veb_supported(pci_dev->device.devargs);
 954                 config_vf_floating_veb(pci_dev->device.devargs,
 955                                        pf->floating_veb,
 956                                        pf->floating_veb_list);
 957         } else {
 958                 pf->floating_veb = false;
 959         }
 960 }
 961
 962 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 963 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 964
 965 static int
 966 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 967 {
 968         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 969         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 970         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 971         int ret;
 972
 973         struct rte_hash_parameters ethertype_hash_params = {
 974                 .name = ethertype_hash_name,
 975                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 976                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 977                 .hash_func = rte_hash_crc,
 978                 .hash_func_init_val = 0,
 979                 .socket_id = rte_socket_id(),
 980         };
 981
 982         /* Initialize ethertype filter rule list and hash */
 983         TAILQ_INIT(&ethertype_rule->ethertype_list);
 984         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 985                  "ethertype_%s", dev->device->name);
 986         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 987         if (!ethertype_rule->hash_table) {
 988                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 989                 return -EINVAL;
 990         }
 991         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 992                                        sizeof(struct i40e_ethertype_filter *) *
 993                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 994                                        0);
 995         if (!ethertype_rule->hash_map) {
 996                 PMD_INIT_LOG(ERR,
 997                              "Failed to allocate memory for ethertype hash map!");
 998                 ret = -ENOMEM;
 999                 goto err_ethertype_hash_map_alloc;
1000         }
1001
1002         return 0;
1003
1004 err_ethertype_hash_map_alloc:
1005         rte_hash_free(ethertype_rule->hash_table);
1006
1007         return ret;
1008 }
1009
1010 static int
1011 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1012 {
1013         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1014         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1015         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1016         int ret;
1017
1018         struct rte_hash_parameters tunnel_hash_params = {
1019                 .name = tunnel_hash_name,
1020                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1021                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1022                 .hash_func = rte_hash_crc,
1023                 .hash_func_init_val = 0,
1024                 .socket_id = rte_socket_id(),
1025         };
1026
1027         /* Initialize tunnel filter rule list and hash */
1028         TAILQ_INIT(&tunnel_rule->tunnel_list);
1029         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1030                  "tunnel_%s", dev->device->name);
1031         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1032         if (!tunnel_rule->hash_table) {
1033                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1034                 return -EINVAL;
1035         }
1036         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1037                                     sizeof(struct i40e_tunnel_filter *) *
1038                                     I40E_MAX_TUNNEL_FILTER_NUM,
1039                                     0);
1040         if (!tunnel_rule->hash_map) {
1041                 PMD_INIT_LOG(ERR,
1042                              "Failed to allocate memory for tunnel hash map!");
1043                 ret = -ENOMEM;
1044                 goto err_tunnel_hash_map_alloc;
1045         }
1046
1047         return 0;
1048
1049 err_tunnel_hash_map_alloc:
1050         rte_hash_free(tunnel_rule->hash_table);
1051
1052         return ret;
1053 }
1054
1055 static int
1056 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1057 {
1058         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1059         struct i40e_fdir_info *fdir_info = &pf->fdir;
1060         char fdir_hash_name[RTE_HASH_NAMESIZE];
1061         int ret;
1062
1063         struct rte_hash_parameters fdir_hash_params = {
1064                 .name = fdir_hash_name,
1065                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1066                 .key_len = sizeof(struct i40e_fdir_input),
1067                 .hash_func = rte_hash_crc,
1068                 .hash_func_init_val = 0,
1069                 .socket_id = rte_socket_id(),
1070         };
1071
1072         /* Initialize flow director filter rule list and hash */
1073         TAILQ_INIT(&fdir_info->fdir_list);
1074         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1075                  "fdir_%s", dev->device->name);
1076         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1077         if (!fdir_info->hash_table) {
1078                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1079                 return -EINVAL;
1080         }
1081         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1082                                           sizeof(struct i40e_fdir_filter *) *
1083                                           I40E_MAX_FDIR_FILTER_NUM,
1084                                           0);
1085         if (!fdir_info->hash_map) {
1086                 PMD_INIT_LOG(ERR,
1087                              "Failed to allocate memory for fdir hash map!");
1088                 ret = -ENOMEM;
1089                 goto err_fdir_hash_map_alloc;
1090         }
1091         return 0;
1092
1093 err_fdir_hash_map_alloc:
1094         rte_hash_free(fdir_info->hash_table);
1095
1096         return ret;
1097 }
1098
1099 static void
1100 i40e_init_customized_info(struct i40e_pf *pf)
1101 {
1102         int i;
1103
1104         /* Initialize customized pctype */
1105         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1106                 pf->customized_pctype[i].index = i;
1107                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1108                 pf->customized_pctype[i].valid = false;
1109         }
1110
1111         pf->gtp_support = false;
1112 }
1113
1114 void
1115 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1116 {
1117         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1118         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1119         struct i40e_queue_regions *info = &pf->queue_region;
1120         uint16_t i;
1121
1122         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1123                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1124
1125         memset(info, 0, sizeof(struct i40e_queue_regions));
1126 }
1127
1128 static int
1129 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1130                                const char *value,
1131                                void *opaque)
1132 {
1133         struct i40e_pf *pf;
1134         unsigned long support_multi_driver;
1135         char *end;
1136
1137         pf = (struct i40e_pf *)opaque;
1138
1139         errno = 0;
1140         support_multi_driver = strtoul(value, &end, 10);
1141         if (errno != 0 || end == value || *end != 0) {
1142                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1143                 return -(EINVAL);
1144         }
1145
1146         if (support_multi_driver == 1 || support_multi_driver == 0)
1147                 pf->support_multi_driver = (bool)support_multi_driver;
1148         else
1149                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1150                             "enable global configuration by default."
1151                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1152         return 0;
1153 }
1154
1155 static int
1156 i40e_support_multi_driver(struct rte_eth_dev *dev)
1157 {
1158         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1159         struct rte_kvargs *kvlist;
1160         int kvargs_count;
1161
1162         /* Enable global configuration by default */
1163         pf->support_multi_driver = false;
1164
1165         if (!dev->device->devargs)
1166                 return 0;
1167
1168         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1169         if (!kvlist)
1170                 return -EINVAL;
1171
1172         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1173         if (!kvargs_count) {
1174                 rte_kvargs_free(kvlist);
1175                 return 0;
1176         }
1177
1178         if (kvargs_count > 1)
1179                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1180                             "the first invalid or last valid one is used !",
1181                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1182
1183         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1184                                i40e_parse_multi_drv_handler, pf) < 0) {
1185                 rte_kvargs_free(kvlist);
1186                 return -EINVAL;
1187         }
1188
1189         rte_kvargs_free(kvlist);
1190         return 0;
1191 }
1192
1193 static int
1194 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1195                                     uint32_t reg_addr, uint64_t reg_val,
1196                                     struct i40e_asq_cmd_details *cmd_details)
1197 {
1198         uint64_t ori_reg_val;
1199         struct rte_eth_dev *dev;
1200         int ret;
1201
1202         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1203         if (ret != I40E_SUCCESS) {
1204                 PMD_DRV_LOG(ERR,
1205                             "Fail to debug read from 0x%08x",
1206                             reg_addr);
1207                 return -EIO;
1208         }
1209         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1210
1211         if (ori_reg_val != reg_val)
1212                 PMD_DRV_LOG(WARNING,
1213                             "i40e device %s changed global register [0x%08x]."
1214                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1215                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1216
1217         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1218 }
1219
1220 static int
1221 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1222                                 const char *value,
1223                                 void *opaque)
1224 {
1225         struct i40e_adapter *ad = opaque;
1226         int use_latest_vec;
1227
1228         use_latest_vec = atoi(value);
1229
1230         if (use_latest_vec != 0 && use_latest_vec != 1)
1231                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1232
1233         ad->use_latest_vec = (uint8_t)use_latest_vec;
1234
1235         return 0;
1236 }
1237
1238 static int
1239 i40e_use_latest_vec(struct rte_eth_dev *dev)
1240 {
1241         struct i40e_adapter *ad =
1242                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1243         struct rte_kvargs *kvlist;
1244         int kvargs_count;
1245
1246         ad->use_latest_vec = false;
1247
1248         if (!dev->device->devargs)
1249                 return 0;
1250
1251         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1252         if (!kvlist)
1253                 return -EINVAL;
1254
1255         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1256         if (!kvargs_count) {
1257                 rte_kvargs_free(kvlist);
1258                 return 0;
1259         }
1260
1261         if (kvargs_count > 1)
1262                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1263                             "the first invalid or last valid one is used !",
1264                             ETH_I40E_USE_LATEST_VEC);
1265
1266         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1267                                 i40e_parse_latest_vec_handler, ad) < 0) {
1268                 rte_kvargs_free(kvlist);
1269                 return -EINVAL;
1270         }
1271
1272         rte_kvargs_free(kvlist);
1273         return 0;
1274 }
1275
1276 static int
1277 read_vf_msg_config(__rte_unused const char *key,
1278                                const char *value,
1279                                void *opaque)
1280 {
1281         struct i40e_vf_msg_cfg *cfg = opaque;
1282
1283         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1284                         &cfg->ignore_second) != 3) {
1285                 memset(cfg, 0, sizeof(*cfg));
1286                 PMD_DRV_LOG(ERR, "format error! example: "
1287                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1288                 return -EINVAL;
1289         }
1290
1291         /*
1292          * If the message validation function been enabled, the 'period'
1293          * and 'ignore_second' must greater than 0.
1294          */
1295         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1296                 memset(cfg, 0, sizeof(*cfg));
1297                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1298                                 " number must be greater than 0!",
1299                                 ETH_I40E_VF_MSG_CFG);
1300                 return -EINVAL;
1301         }
1302
1303         return 0;
1304 }
1305
1306 static int
1307 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1308                 struct i40e_vf_msg_cfg *msg_cfg)
1309 {
1310         struct rte_kvargs *kvlist;
1311         int kvargs_count;
1312         int ret = 0;
1313
1314         memset(msg_cfg, 0, sizeof(*msg_cfg));
1315
1316         if (!dev->device->devargs)
1317                 return ret;
1318
1319         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1320         if (!kvlist)
1321                 return -EINVAL;
1322
1323         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1324         if (!kvargs_count)
1325                 goto free_end;
1326
1327         if (kvargs_count > 1) {
1328                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1329                                 ETH_I40E_VF_MSG_CFG);
1330                 ret = -EINVAL;
1331                 goto free_end;
1332         }
1333
1334         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1335                         read_vf_msg_config, msg_cfg) < 0)
1336                 ret = -EINVAL;
1337
1338 free_end:
1339         rte_kvargs_free(kvlist);
1340         return ret;
1341 }
1342
1343 #define I40E_ALARM_INTERVAL 50000 /* us */
1344
1345 static int
1346 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1347 {
1348         struct rte_pci_device *pci_dev;
1349         struct rte_intr_handle *intr_handle;
1350         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1351         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352         struct i40e_vsi *vsi;
1353         int ret;
1354         uint32_t len, val;
1355         uint8_t aq_fail = 0;
1356
1357         PMD_INIT_FUNC_TRACE();
1358
1359         dev->dev_ops = &i40e_eth_dev_ops;
1360         dev->rx_pkt_burst = i40e_recv_pkts;
1361         dev->tx_pkt_burst = i40e_xmit_pkts;
1362         dev->tx_pkt_prepare = i40e_prep_pkts;
1363
1364         /* for secondary processes, we don't initialise any further as primary
1365          * has already done this work. Only check we don't need a different
1366          * RX function */
1367         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1368                 i40e_set_rx_function(dev);
1369                 i40e_set_tx_function(dev);
1370                 return 0;
1371         }
1372         i40e_set_default_ptype_table(dev);
1373         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1374         intr_handle = &pci_dev->intr_handle;
1375
1376         rte_eth_copy_pci_info(dev, pci_dev);
1377
1378         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1379         pf->adapter->eth_dev = dev;
1380         pf->dev_data = dev->data;
1381
1382         hw->back = I40E_PF_TO_ADAPTER(pf);
1383         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1384         if (!hw->hw_addr) {
1385                 PMD_INIT_LOG(ERR,
1386                         "Hardware is not available, as address is NULL");
1387                 return -ENODEV;
1388         }
1389
1390         hw->vendor_id = pci_dev->id.vendor_id;
1391         hw->device_id = pci_dev->id.device_id;
1392         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1393         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1394         hw->bus.device = pci_dev->addr.devid;
1395         hw->bus.func = pci_dev->addr.function;
1396         hw->adapter_stopped = 0;
1397         hw->adapter_closed = 0;
1398
1399         /* Init switch device pointer */
1400         hw->switch_dev = NULL;
1401
1402         /*
1403          * Switch Tag value should not be identical to either the First Tag
1404          * or Second Tag values. So set something other than common Ethertype
1405          * for internal switching.
1406          */
1407         hw->switch_tag = 0xffff;
1408
1409         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1410         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1411                 PMD_INIT_LOG(ERR, "\nERROR: "
1412                         "Firmware recovery mode detected. Limiting functionality.\n"
1413                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1414                         "User Guide for details on firmware recovery mode.");
1415                 return -EIO;
1416         }
1417
1418         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1419         /* Check if need to support multi-driver */
1420         i40e_support_multi_driver(dev);
1421         /* Check if users want the latest supported vec path */
1422         i40e_use_latest_vec(dev);
1423
1424         /* Make sure all is clean before doing PF reset */
1425         i40e_clear_hw(hw);
1426
1427         /* Reset here to make sure all is clean for each PF */
1428         ret = i40e_pf_reset(hw);
1429         if (ret) {
1430                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1431                 return ret;
1432         }
1433
1434         /* Initialize the shared code (base driver) */
1435         ret = i40e_init_shared_code(hw);
1436         if (ret) {
1437                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1438                 return ret;
1439         }
1440
1441         /* Initialize the parameters for adminq */
1442         i40e_init_adminq_parameter(hw);
1443         ret = i40e_init_adminq(hw);
1444         if (ret != I40E_SUCCESS) {
1445                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1446                 return -EIO;
1447         }
1448         /* Firmware of SFP x722 does not support adminq option */
1449         if (hw->device_id == I40E_DEV_ID_SFP_X722)
1450                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1451
1452         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1453                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1454                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1455                      ((hw->nvm.version >> 12) & 0xf),
1456                      ((hw->nvm.version >> 4) & 0xff),
1457                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1458
1459         /* Initialize the hardware */
1460         i40e_hw_init(dev);
1461
1462         i40e_config_automask(pf);
1463
1464         i40e_set_default_pctype_table(dev);
1465
1466         /*
1467          * To work around the NVM issue, initialize registers
1468          * for packet type of QinQ by software.
1469          * It should be removed once issues are fixed in NVM.
1470          */
1471         if (!pf->support_multi_driver)
1472                 i40e_GLQF_reg_init(hw);
1473
1474         /* Initialize the input set for filters (hash and fd) to default value */
1475         i40e_filter_input_set_init(pf);
1476
1477         /* initialise the L3_MAP register */
1478         if (!pf->support_multi_driver) {
1479                 ret = i40e_aq_debug_write_global_register(hw,
1480                                                    I40E_GLQF_L3_MAP(40),
1481                                                    0x00000028,  NULL);
1482                 if (ret)
1483                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1484                                      ret);
1485                 PMD_INIT_LOG(DEBUG,
1486                              "Global register 0x%08x is changed with 0x28",
1487                              I40E_GLQF_L3_MAP(40));
1488         }
1489
1490         /* Need the special FW version to support floating VEB */
1491         config_floating_veb(dev);
1492         /* Clear PXE mode */
1493         i40e_clear_pxe_mode(hw);
1494         i40e_dev_sync_phy_type(hw);
1495
1496         /*
1497          * On X710, performance number is far from the expectation on recent
1498          * firmware versions. The fix for this issue may not be integrated in
1499          * the following firmware version. So the workaround in software driver
1500          * is needed. It needs to modify the initial values of 3 internal only
1501          * registers. Note that the workaround can be removed when it is fixed
1502          * in firmware in the future.
1503          */
1504         i40e_configure_registers(hw);
1505
1506         /* Get hw capabilities */
1507         ret = i40e_get_cap(hw);
1508         if (ret != I40E_SUCCESS) {
1509                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1510                 goto err_get_capabilities;
1511         }
1512
1513         /* Initialize parameters for PF */
1514         ret = i40e_pf_parameter_init(dev);
1515         if (ret != 0) {
1516                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1517                 goto err_parameter_init;
1518         }
1519
1520         /* Initialize the queue management */
1521         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1522         if (ret < 0) {
1523                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1524                 goto err_qp_pool_init;
1525         }
1526         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1527                                 hw->func_caps.num_msix_vectors - 1);
1528         if (ret < 0) {
1529                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1530                 goto err_msix_pool_init;
1531         }
1532
1533         /* Initialize lan hmc */
1534         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1535                                 hw->func_caps.num_rx_qp, 0, 0);
1536         if (ret != I40E_SUCCESS) {
1537                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1538                 goto err_init_lan_hmc;
1539         }
1540
1541         /* Configure lan hmc */
1542         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1543         if (ret != I40E_SUCCESS) {
1544                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1545                 goto err_configure_lan_hmc;
1546         }
1547
1548         /* Get and check the mac address */
1549         i40e_get_mac_addr(hw, hw->mac.addr);
1550         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1551                 PMD_INIT_LOG(ERR, "mac address is not valid");
1552                 ret = -EIO;
1553                 goto err_get_mac_addr;
1554         }
1555         /* Copy the permanent MAC address */
1556         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1557                         (struct rte_ether_addr *)hw->mac.perm_addr);
1558
1559         /* Disable flow control */
1560         hw->fc.requested_mode = I40E_FC_NONE;
1561         i40e_set_fc(hw, &aq_fail, TRUE);
1562
1563         /* Set the global registers with default ether type value */
1564         if (!pf->support_multi_driver) {
1565                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1566                                          RTE_ETHER_TYPE_VLAN);
1567                 if (ret != I40E_SUCCESS) {
1568                         PMD_INIT_LOG(ERR,
1569                                      "Failed to set the default outer "
1570                                      "VLAN ether type");
1571                         goto err_setup_pf_switch;
1572                 }
1573         }
1574
1575         /* PF setup, which includes VSI setup */
1576         ret = i40e_pf_setup(pf);
1577         if (ret) {
1578                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1579                 goto err_setup_pf_switch;
1580         }
1581
1582         vsi = pf->main_vsi;
1583
1584         /* Disable double vlan by default */
1585         i40e_vsi_config_double_vlan(vsi, FALSE);
1586
1587         /* Disable S-TAG identification when floating_veb is disabled */
1588         if (!pf->floating_veb) {
1589                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1590                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1591                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1592                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1593                 }
1594         }
1595
1596         if (!vsi->max_macaddrs)
1597                 len = RTE_ETHER_ADDR_LEN;
1598         else
1599                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1600
1601         /* Should be after VSI initialized */
1602         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1603         if (!dev->data->mac_addrs) {
1604                 PMD_INIT_LOG(ERR,
1605                         "Failed to allocated memory for storing mac address");
1606                 goto err_mac_alloc;
1607         }
1608         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1609                                         &dev->data->mac_addrs[0]);
1610
1611         /* Pass the information to the rte_eth_dev_close() that it should also
1612          * release the private port resources.
1613          */
1614         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1615
1616         /* Init dcb to sw mode by default */
1617         ret = i40e_dcb_init_configure(dev, TRUE);
1618         if (ret != I40E_SUCCESS) {
1619                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1620                 pf->flags &= ~I40E_FLAG_DCB;
1621         }
1622         /* Update HW struct after DCB configuration */
1623         i40e_get_cap(hw);
1624
1625         /* initialize pf host driver to setup SRIOV resource if applicable */
1626         i40e_pf_host_init(dev);
1627
1628         /* register callback func to eal lib */
1629         rte_intr_callback_register(intr_handle,
1630                                    i40e_dev_interrupt_handler, dev);
1631
1632         /* configure and enable device interrupt */
1633         i40e_pf_config_irq0(hw, TRUE);
1634         i40e_pf_enable_irq0(hw);
1635
1636         /* enable uio intr after callback register */
1637         rte_intr_enable(intr_handle);
1638
1639         /* By default disable flexible payload in global configuration */
1640         if (!pf->support_multi_driver)
1641                 i40e_flex_payload_reg_set_default(hw);
1642
1643         /*
1644          * Add an ethertype filter to drop all flow control frames transmitted
1645          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1646          * frames to wire.
1647          */
1648         i40e_add_tx_flow_control_drop_filter(pf);
1649
1650         /* Set the max frame size to 0x2600 by default,
1651          * in case other drivers changed the default value.
1652          */
1653         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1654
1655         /* initialize mirror rule list */
1656         TAILQ_INIT(&pf->mirror_list);
1657
1658         /* initialize Traffic Manager configuration */
1659         i40e_tm_conf_init(dev);
1660
1661         /* Initialize customized information */
1662         i40e_init_customized_info(pf);
1663
1664         ret = i40e_init_ethtype_filter_list(dev);
1665         if (ret < 0)
1666                 goto err_init_ethtype_filter_list;
1667         ret = i40e_init_tunnel_filter_list(dev);
1668         if (ret < 0)
1669                 goto err_init_tunnel_filter_list;
1670         ret = i40e_init_fdir_filter_list(dev);
1671         if (ret < 0)
1672                 goto err_init_fdir_filter_list;
1673
1674         /* initialize queue region configuration */
1675         i40e_init_queue_region_conf(dev);
1676
1677         /* initialize rss configuration from rte_flow */
1678         memset(&pf->rss_info, 0,
1679                 sizeof(struct i40e_rte_flow_rss_conf));
1680
1681         /* reset all stats of the device, including pf and main vsi */
1682         i40e_dev_stats_reset(dev);
1683
1684         return 0;
1685
1686 err_init_fdir_filter_list:
1687         rte_free(pf->tunnel.hash_table);
1688         rte_free(pf->tunnel.hash_map);
1689 err_init_tunnel_filter_list:
1690         rte_free(pf->ethertype.hash_table);
1691         rte_free(pf->ethertype.hash_map);
1692 err_init_ethtype_filter_list:
1693         rte_free(dev->data->mac_addrs);
1694         dev->data->mac_addrs = NULL;
1695 err_mac_alloc:
1696         i40e_vsi_release(pf->main_vsi);
1697 err_setup_pf_switch:
1698 err_get_mac_addr:
1699 err_configure_lan_hmc:
1700         (void)i40e_shutdown_lan_hmc(hw);
1701 err_init_lan_hmc:
1702         i40e_res_pool_destroy(&pf->msix_pool);
1703 err_msix_pool_init:
1704         i40e_res_pool_destroy(&pf->qp_pool);
1705 err_qp_pool_init:
1706 err_parameter_init:
1707 err_get_capabilities:
1708         (void)i40e_shutdown_adminq(hw);
1709
1710         return ret;
1711 }
1712
1713 static void
1714 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1715 {
1716         struct i40e_ethertype_filter *p_ethertype;
1717         struct i40e_ethertype_rule *ethertype_rule;
1718
1719         ethertype_rule = &pf->ethertype;
1720         /* Remove all ethertype filter rules and hash */
1721         if (ethertype_rule->hash_map)
1722                 rte_free(ethertype_rule->hash_map);
1723         if (ethertype_rule->hash_table)
1724                 rte_hash_free(ethertype_rule->hash_table);
1725
1726         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1727                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1728                              p_ethertype, rules);
1729                 rte_free(p_ethertype);
1730         }
1731 }
1732
1733 static void
1734 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1735 {
1736         struct i40e_tunnel_filter *p_tunnel;
1737         struct i40e_tunnel_rule *tunnel_rule;
1738
1739         tunnel_rule = &pf->tunnel;
1740         /* Remove all tunnel director rules and hash */
1741         if (tunnel_rule->hash_map)
1742                 rte_free(tunnel_rule->hash_map);
1743         if (tunnel_rule->hash_table)
1744                 rte_hash_free(tunnel_rule->hash_table);
1745
1746         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1747                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1748                 rte_free(p_tunnel);
1749         }
1750 }
1751
1752 static void
1753 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1754 {
1755         struct i40e_fdir_filter *p_fdir;
1756         struct i40e_fdir_info *fdir_info;
1757
1758         fdir_info = &pf->fdir;
1759         /* Remove all flow director rules and hash */
1760         if (fdir_info->hash_map)
1761                 rte_free(fdir_info->hash_map);
1762         if (fdir_info->hash_table)
1763                 rte_hash_free(fdir_info->hash_table);
1764
1765         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1766                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1767                 rte_free(p_fdir);
1768         }
1769 }
1770
1771 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1772 {
1773         /*
1774          * Disable by default flexible payload
1775          * for corresponding L2/L3/L4 layers.
1776          */
1777         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1778         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1779         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1780 }
1781
1782 static int
1783 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1784 {
1785         struct i40e_hw *hw;
1786
1787         PMD_INIT_FUNC_TRACE();
1788
1789         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1790                 return 0;
1791
1792         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1793
1794         if (hw->adapter_closed == 0)
1795                 i40e_dev_close(dev);
1796
1797         return 0;
1798 }
1799
1800 static int
1801 i40e_dev_configure(struct rte_eth_dev *dev)
1802 {
1803         struct i40e_adapter *ad =
1804                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1805         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1806         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1807         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1808         int i, ret;
1809
1810         ret = i40e_dev_sync_phy_type(hw);
1811         if (ret)
1812                 return ret;
1813
1814         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1815          * bulk allocation or vector Rx preconditions we will reset it.
1816          */
1817         ad->rx_bulk_alloc_allowed = true;
1818         ad->rx_vec_allowed = true;
1819         ad->tx_simple_allowed = true;
1820         ad->tx_vec_allowed = true;
1821
1822         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1823                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1824
1825         /* Only legacy filter API needs the following fdir config. So when the
1826          * legacy filter API is deprecated, the following codes should also be
1827          * removed.
1828          */
1829         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1830                 ret = i40e_fdir_setup(pf);
1831                 if (ret != I40E_SUCCESS) {
1832                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1833                         return -ENOTSUP;
1834                 }
1835                 ret = i40e_fdir_configure(dev);
1836                 if (ret < 0) {
1837                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1838                         goto err;
1839                 }
1840         } else
1841                 i40e_fdir_teardown(pf);
1842
1843         ret = i40e_dev_init_vlan(dev);
1844         if (ret < 0)
1845                 goto err;
1846
1847         /* VMDQ setup.
1848          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1849          *  RSS setting have different requirements.
1850          *  General PMD driver call sequence are NIC init, configure,
1851          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1852          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1853          *  applicable. So, VMDQ setting has to be done before
1854          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1855          *  For RSS setting, it will try to calculate actual configured RX queue
1856          *  number, which will be available after rx_queue_setup(). dev_start()
1857          *  function is good to place RSS setup.
1858          */
1859         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1860                 ret = i40e_vmdq_setup(dev);
1861                 if (ret)
1862                         goto err;
1863         }
1864
1865         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1866                 ret = i40e_dcb_setup(dev);
1867                 if (ret) {
1868                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1869                         goto err_dcb;
1870                 }
1871         }
1872
1873         TAILQ_INIT(&pf->flow_list);
1874
1875         return 0;
1876
1877 err_dcb:
1878         /* need to release vmdq resource if exists */
1879         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1880                 i40e_vsi_release(pf->vmdq[i].vsi);
1881                 pf->vmdq[i].vsi = NULL;
1882         }
1883         rte_free(pf->vmdq);
1884         pf->vmdq = NULL;
1885 err:
1886         /* Need to release fdir resource if exists.
1887          * Only legacy filter API needs the following fdir config. So when the
1888          * legacy filter API is deprecated, the following code should also be
1889          * removed.
1890          */
1891         i40e_fdir_teardown(pf);
1892         return ret;
1893 }
1894
1895 void
1896 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1897 {
1898         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1899         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1900         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1901         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1902         uint16_t msix_vect = vsi->msix_intr;
1903         uint16_t i;
1904
1905         for (i = 0; i < vsi->nb_qps; i++) {
1906                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1907                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1908                 rte_wmb();
1909         }
1910
1911         if (vsi->type != I40E_VSI_SRIOV) {
1912                 if (!rte_intr_allow_others(intr_handle)) {
1913                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1914                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1915                         I40E_WRITE_REG(hw,
1916                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1917                                        0);
1918                 } else {
1919                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1920                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1921                         I40E_WRITE_REG(hw,
1922                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1923                                                        msix_vect - 1), 0);
1924                 }
1925         } else {
1926                 uint32_t reg;
1927                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1928                         vsi->user_param + (msix_vect - 1);
1929
1930                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1931                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1932         }
1933         I40E_WRITE_FLUSH(hw);
1934 }
1935
1936 static void
1937 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1938                        int base_queue, int nb_queue,
1939                        uint16_t itr_idx)
1940 {
1941         int i;
1942         uint32_t val;
1943         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1944         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1945
1946         /* Bind all RX queues to allocated MSIX interrupt */
1947         for (i = 0; i < nb_queue; i++) {
1948                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1949                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1950                         ((base_queue + i + 1) <<
1951                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1952                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1953                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1954
1955                 if (i == nb_queue - 1)
1956                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1957                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1958         }
1959
1960         /* Write first RX queue to Link list register as the head element */
1961         if (vsi->type != I40E_VSI_SRIOV) {
1962                 uint16_t interval =
1963                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1964
1965                 if (msix_vect == I40E_MISC_VEC_ID) {
1966                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1967                                        (base_queue <<
1968                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1969                                        (0x0 <<
1970                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1971                         I40E_WRITE_REG(hw,
1972                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1973                                        interval);
1974                 } else {
1975                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1976                                        (base_queue <<
1977                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1978                                        (0x0 <<
1979                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1980                         I40E_WRITE_REG(hw,
1981                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1982                                                        msix_vect - 1),
1983                                        interval);
1984                 }
1985         } else {
1986                 uint32_t reg;
1987
1988                 if (msix_vect == I40E_MISC_VEC_ID) {
1989                         I40E_WRITE_REG(hw,
1990                                        I40E_VPINT_LNKLST0(vsi->user_param),
1991                                        (base_queue <<
1992                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1993                                        (0x0 <<
1994                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1995                 } else {
1996                         /* num_msix_vectors_vf needs to minus irq0 */
1997                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1998                                 vsi->user_param + (msix_vect - 1);
1999
2000                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2001                                        (base_queue <<
2002                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2003                                        (0x0 <<
2004                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2005                 }
2006         }
2007
2008         I40E_WRITE_FLUSH(hw);
2009 }
2010
2011 void
2012 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2013 {
2014         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2015         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2016         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2017         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2018         uint16_t msix_vect = vsi->msix_intr;
2019         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2020         uint16_t queue_idx = 0;
2021         int record = 0;
2022         int i;
2023
2024         for (i = 0; i < vsi->nb_qps; i++) {
2025                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2026                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2027         }
2028
2029         /* VF bind interrupt */
2030         if (vsi->type == I40E_VSI_SRIOV) {
2031                 __vsi_queues_bind_intr(vsi, msix_vect,
2032                                        vsi->base_queue, vsi->nb_qps,
2033                                        itr_idx);
2034                 return;
2035         }
2036
2037         /* PF & VMDq bind interrupt */
2038         if (rte_intr_dp_is_en(intr_handle)) {
2039                 if (vsi->type == I40E_VSI_MAIN) {
2040                         queue_idx = 0;
2041                         record = 1;
2042                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2043                         struct i40e_vsi *main_vsi =
2044                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2045                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2046                         record = 1;
2047                 }
2048         }
2049
2050         for (i = 0; i < vsi->nb_used_qps; i++) {
2051                 if (nb_msix <= 1) {
2052                         if (!rte_intr_allow_others(intr_handle))
2053                                 /* allow to share MISC_VEC_ID */
2054                                 msix_vect = I40E_MISC_VEC_ID;
2055
2056                         /* no enough msix_vect, map all to one */
2057                         __vsi_queues_bind_intr(vsi, msix_vect,
2058                                                vsi->base_queue + i,
2059                                                vsi->nb_used_qps - i,
2060                                                itr_idx);
2061                         for (; !!record && i < vsi->nb_used_qps; i++)
2062                                 intr_handle->intr_vec[queue_idx + i] =
2063                                         msix_vect;
2064                         break;
2065                 }
2066                 /* 1:1 queue/msix_vect mapping */
2067                 __vsi_queues_bind_intr(vsi, msix_vect,
2068                                        vsi->base_queue + i, 1,
2069                                        itr_idx);
2070                 if (!!record)
2071                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2072
2073                 msix_vect++;
2074                 nb_msix--;
2075         }
2076 }
2077
2078 static void
2079 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2080 {
2081         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2082         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2083         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2084         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2085         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2086         uint16_t msix_intr, i;
2087
2088         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2089                 for (i = 0; i < vsi->nb_msix; i++) {
2090                         msix_intr = vsi->msix_intr + i;
2091                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2092                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2093                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2094                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2095                 }
2096         else
2097                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2098                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2099                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2100                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2101
2102         I40E_WRITE_FLUSH(hw);
2103 }
2104
2105 static void
2106 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2107 {
2108         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2109         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2110         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2111         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2112         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2113         uint16_t msix_intr, i;
2114
2115         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2116                 for (i = 0; i < vsi->nb_msix; i++) {
2117                         msix_intr = vsi->msix_intr + i;
2118                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2119                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2120                 }
2121         else
2122                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2123                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2124
2125         I40E_WRITE_FLUSH(hw);
2126 }
2127
2128 static inline uint8_t
2129 i40e_parse_link_speeds(uint16_t link_speeds)
2130 {
2131         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2132
2133         if (link_speeds & ETH_LINK_SPEED_40G)
2134                 link_speed |= I40E_LINK_SPEED_40GB;
2135         if (link_speeds & ETH_LINK_SPEED_25G)
2136                 link_speed |= I40E_LINK_SPEED_25GB;
2137         if (link_speeds & ETH_LINK_SPEED_20G)
2138                 link_speed |= I40E_LINK_SPEED_20GB;
2139         if (link_speeds & ETH_LINK_SPEED_10G)
2140                 link_speed |= I40E_LINK_SPEED_10GB;
2141         if (link_speeds & ETH_LINK_SPEED_1G)
2142                 link_speed |= I40E_LINK_SPEED_1GB;
2143         if (link_speeds & ETH_LINK_SPEED_100M)
2144                 link_speed |= I40E_LINK_SPEED_100MB;
2145
2146         return link_speed;
2147 }
2148
2149 static int
2150 i40e_phy_conf_link(struct i40e_hw *hw,
2151                    uint8_t abilities,
2152                    uint8_t force_speed,
2153                    bool is_up)
2154 {
2155         enum i40e_status_code status;
2156         struct i40e_aq_get_phy_abilities_resp phy_ab;
2157         struct i40e_aq_set_phy_config phy_conf;
2158         enum i40e_aq_phy_type cnt;
2159         uint8_t avail_speed;
2160         uint32_t phy_type_mask = 0;
2161
2162         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2163                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2164                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2165                         I40E_AQ_PHY_FLAG_LOW_POWER;
2166         int ret = -ENOTSUP;
2167
2168         /* To get phy capabilities of available speeds. */
2169         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2170                                               NULL);
2171         if (status) {
2172                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2173                                 status);
2174                 return ret;
2175         }
2176         avail_speed = phy_ab.link_speed;
2177
2178         /* To get the current phy config. */
2179         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2180                                               NULL);
2181         if (status) {
2182                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2183                                 status);
2184                 return ret;
2185         }
2186
2187         /* If link needs to go up and it is in autoneg mode the speed is OK,
2188          * no need to set up again.
2189          */
2190         if (is_up && phy_ab.phy_type != 0 &&
2191                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2192                      phy_ab.link_speed != 0)
2193                 return I40E_SUCCESS;
2194
2195         memset(&phy_conf, 0, sizeof(phy_conf));
2196
2197         /* bits 0-2 use the values from get_phy_abilities_resp */
2198         abilities &= ~mask;
2199         abilities |= phy_ab.abilities & mask;
2200
2201         phy_conf.abilities = abilities;
2202
2203         /* If link needs to go up, but the force speed is not supported,
2204          * Warn users and config the default available speeds.
2205          */
2206         if (is_up && !(force_speed & avail_speed)) {
2207                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2208                 phy_conf.link_speed = avail_speed;
2209         } else {
2210                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2211         }
2212
2213         /* PHY type mask needs to include each type except PHY type extension */
2214         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2215                 phy_type_mask |= 1 << cnt;
2216
2217         /* use get_phy_abilities_resp value for the rest */
2218         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2219         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2220                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2221                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2222         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2223         phy_conf.eee_capability = phy_ab.eee_capability;
2224         phy_conf.eeer = phy_ab.eeer_val;
2225         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2226
2227         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2228                     phy_ab.abilities, phy_ab.link_speed);
2229         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2230                     phy_conf.abilities, phy_conf.link_speed);
2231
2232         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2233         if (status)
2234                 return ret;
2235
2236         return I40E_SUCCESS;
2237 }
2238
2239 static int
2240 i40e_apply_link_speed(struct rte_eth_dev *dev)
2241 {
2242         uint8_t speed;
2243         uint8_t abilities = 0;
2244         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2245         struct rte_eth_conf *conf = &dev->data->dev_conf;
2246
2247         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2248                      I40E_AQ_PHY_LINK_ENABLED;
2249
2250         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2251                 conf->link_speeds = ETH_LINK_SPEED_40G |
2252                                     ETH_LINK_SPEED_25G |
2253                                     ETH_LINK_SPEED_20G |
2254                                     ETH_LINK_SPEED_10G |
2255                                     ETH_LINK_SPEED_1G |
2256                                     ETH_LINK_SPEED_100M;
2257
2258                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2259         } else {
2260                 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2261         }
2262         speed = i40e_parse_link_speeds(conf->link_speeds);
2263
2264         return i40e_phy_conf_link(hw, abilities, speed, true);
2265 }
2266
2267 static int
2268 i40e_dev_start(struct rte_eth_dev *dev)
2269 {
2270         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2271         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2272         struct i40e_vsi *main_vsi = pf->main_vsi;
2273         int ret, i;
2274         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2275         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2276         uint32_t intr_vector = 0;
2277         struct i40e_vsi *vsi;
2278
2279         hw->adapter_stopped = 0;
2280
2281         rte_intr_disable(intr_handle);
2282
2283         if ((rte_intr_cap_multiple(intr_handle) ||
2284              !RTE_ETH_DEV_SRIOV(dev).active) &&
2285             dev->data->dev_conf.intr_conf.rxq != 0) {
2286                 intr_vector = dev->data->nb_rx_queues;
2287                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2288                 if (ret)
2289                         return ret;
2290         }
2291
2292         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2293                 intr_handle->intr_vec =
2294                         rte_zmalloc("intr_vec",
2295                                     dev->data->nb_rx_queues * sizeof(int),
2296                                     0);
2297                 if (!intr_handle->intr_vec) {
2298                         PMD_INIT_LOG(ERR,
2299                                 "Failed to allocate %d rx_queues intr_vec",
2300                                 dev->data->nb_rx_queues);
2301                         return -ENOMEM;
2302                 }
2303         }
2304
2305         /* Initialize VSI */
2306         ret = i40e_dev_rxtx_init(pf);
2307         if (ret != I40E_SUCCESS) {
2308                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2309                 goto err_up;
2310         }
2311
2312         /* Map queues with MSIX interrupt */
2313         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2314                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2315         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2316         i40e_vsi_enable_queues_intr(main_vsi);
2317
2318         /* Map VMDQ VSI queues with MSIX interrupt */
2319         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2320                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2321                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2322                                           I40E_ITR_INDEX_DEFAULT);
2323                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2324         }
2325
2326         /* enable FDIR MSIX interrupt */
2327         if (pf->fdir.fdir_vsi) {
2328                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2329                                           I40E_ITR_INDEX_NONE);
2330                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2331         }
2332
2333         /* Enable all queues which have been configured */
2334         ret = i40e_dev_switch_queues(pf, TRUE);
2335         if (ret != I40E_SUCCESS) {
2336                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2337                 goto err_up;
2338         }
2339
2340         /* Enable receiving broadcast packets */
2341         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2342         if (ret != I40E_SUCCESS)
2343                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2344
2345         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2346                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2347                                                 true, NULL);
2348                 if (ret != I40E_SUCCESS)
2349                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2350         }
2351
2352         /* Enable the VLAN promiscuous mode. */
2353         if (pf->vfs) {
2354                 for (i = 0; i < pf->vf_num; i++) {
2355                         vsi = pf->vfs[i].vsi;
2356                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2357                                                      true, NULL);
2358                 }
2359         }
2360
2361         /* Enable mac loopback mode */
2362         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2363             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2364                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2365                 if (ret != I40E_SUCCESS) {
2366                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2367                         goto err_up;
2368                 }
2369         }
2370
2371         /* Apply link configure */
2372         ret = i40e_apply_link_speed(dev);
2373         if (I40E_SUCCESS != ret) {
2374                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2375                 goto err_up;
2376         }
2377
2378         if (!rte_intr_allow_others(intr_handle)) {
2379                 rte_intr_callback_unregister(intr_handle,
2380                                              i40e_dev_interrupt_handler,
2381                                              (void *)dev);
2382                 /* configure and enable device interrupt */
2383                 i40e_pf_config_irq0(hw, FALSE);
2384                 i40e_pf_enable_irq0(hw);
2385
2386                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2387                         PMD_INIT_LOG(INFO,
2388                                 "lsc won't enable because of no intr multiplex");
2389         } else {
2390                 ret = i40e_aq_set_phy_int_mask(hw,
2391                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2392                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2393                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2394                 if (ret != I40E_SUCCESS)
2395                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2396
2397                 /* Call get_link_info aq commond to enable/disable LSE */
2398                 i40e_dev_link_update(dev, 0);
2399         }
2400
2401         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2402                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2403                                   i40e_dev_alarm_handler, dev);
2404         } else {
2405                 /* enable uio intr after callback register */
2406                 rte_intr_enable(intr_handle);
2407         }
2408
2409         i40e_filter_restore(pf);
2410
2411         if (pf->tm_conf.root && !pf->tm_conf.committed)
2412                 PMD_DRV_LOG(WARNING,
2413                             "please call hierarchy_commit() "
2414                             "before starting the port");
2415
2416         return I40E_SUCCESS;
2417
2418 err_up:
2419         i40e_dev_switch_queues(pf, FALSE);
2420         i40e_dev_clear_queues(dev);
2421
2422         return ret;
2423 }
2424
2425 static void
2426 i40e_dev_stop(struct rte_eth_dev *dev)
2427 {
2428         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2429         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2430         struct i40e_vsi *main_vsi = pf->main_vsi;
2431         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2432         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2433         int i;
2434
2435         if (hw->adapter_stopped == 1)
2436                 return;
2437
2438         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2439                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2440                 rte_intr_enable(intr_handle);
2441         }
2442
2443         /* Disable all queues */
2444         i40e_dev_switch_queues(pf, FALSE);
2445
2446         /* un-map queues with interrupt registers */
2447         i40e_vsi_disable_queues_intr(main_vsi);
2448         i40e_vsi_queues_unbind_intr(main_vsi);
2449
2450         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2451                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2452                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2453         }
2454
2455         if (pf->fdir.fdir_vsi) {
2456                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2457                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2458         }
2459         /* Clear all queues and release memory */
2460         i40e_dev_clear_queues(dev);
2461
2462         /* Set link down */
2463         i40e_dev_set_link_down(dev);
2464
2465         if (!rte_intr_allow_others(intr_handle))
2466                 /* resume to the default handler */
2467                 rte_intr_callback_register(intr_handle,
2468                                            i40e_dev_interrupt_handler,
2469                                            (void *)dev);
2470
2471         /* Clean datapath event and queue/vec mapping */
2472         rte_intr_efd_disable(intr_handle);
2473         if (intr_handle->intr_vec) {
2474                 rte_free(intr_handle->intr_vec);
2475                 intr_handle->intr_vec = NULL;
2476         }
2477
2478         /* reset hierarchy commit */
2479         pf->tm_conf.committed = false;
2480
2481         hw->adapter_stopped = 1;
2482
2483         pf->adapter->rss_reta_updated = 0;
2484 }
2485
2486 static void
2487 i40e_dev_close(struct rte_eth_dev *dev)
2488 {
2489         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2490         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2491         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2492         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2493         struct i40e_mirror_rule *p_mirror;
2494         struct i40e_filter_control_settings settings;
2495         struct rte_flow *p_flow;
2496         uint32_t reg;
2497         int i;
2498         int ret;
2499         uint8_t aq_fail = 0;
2500         int retries = 0;
2501
2502         PMD_INIT_FUNC_TRACE();
2503
2504         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2505         if (ret)
2506                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2507
2508
2509         i40e_dev_stop(dev);
2510
2511         /* Remove all mirror rules */
2512         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2513                 ret = i40e_aq_del_mirror_rule(hw,
2514                                               pf->main_vsi->veb->seid,
2515                                               p_mirror->rule_type,
2516                                               p_mirror->entries,
2517                                               p_mirror->num_entries,
2518                                               p_mirror->id);
2519                 if (ret < 0)
2520                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2521                                     "status = %d, aq_err = %d.", ret,
2522                                     hw->aq.asq_last_status);
2523
2524                 /* remove mirror software resource anyway */
2525                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2526                 rte_free(p_mirror);
2527                 pf->nb_mirror_rule--;
2528         }
2529
2530         i40e_dev_free_queues(dev);
2531
2532         /* Disable interrupt */
2533         i40e_pf_disable_irq0(hw);
2534         rte_intr_disable(intr_handle);
2535
2536         /*
2537          * Only legacy filter API needs the following fdir config. So when the
2538          * legacy filter API is deprecated, the following code should also be
2539          * removed.
2540          */
2541         i40e_fdir_teardown(pf);
2542
2543         /* shutdown and destroy the HMC */
2544         i40e_shutdown_lan_hmc(hw);
2545
2546         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2547                 i40e_vsi_release(pf->vmdq[i].vsi);
2548                 pf->vmdq[i].vsi = NULL;
2549         }
2550         rte_free(pf->vmdq);
2551         pf->vmdq = NULL;
2552
2553         /* release all the existing VSIs and VEBs */
2554         i40e_vsi_release(pf->main_vsi);
2555
2556         /* shutdown the adminq */
2557         i40e_aq_queue_shutdown(hw, true);
2558         i40e_shutdown_adminq(hw);
2559
2560         i40e_res_pool_destroy(&pf->qp_pool);
2561         i40e_res_pool_destroy(&pf->msix_pool);
2562
2563         /* Disable flexible payload in global configuration */
2564         if (!pf->support_multi_driver)
2565                 i40e_flex_payload_reg_set_default(hw);
2566
2567         /* force a PF reset to clean anything leftover */
2568         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2569         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2570                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2571         I40E_WRITE_FLUSH(hw);
2572
2573         dev->dev_ops = NULL;
2574         dev->rx_pkt_burst = NULL;
2575         dev->tx_pkt_burst = NULL;
2576
2577         /* Clear PXE mode */
2578         i40e_clear_pxe_mode(hw);
2579
2580         /* Unconfigure filter control */
2581         memset(&settings, 0, sizeof(settings));
2582         ret = i40e_set_filter_control(hw, &settings);
2583         if (ret)
2584                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2585                                         ret);
2586
2587         /* Disable flow control */
2588         hw->fc.requested_mode = I40E_FC_NONE;
2589         i40e_set_fc(hw, &aq_fail, TRUE);
2590
2591         /* uninitialize pf host driver */
2592         i40e_pf_host_uninit(dev);
2593
2594         do {
2595                 ret = rte_intr_callback_unregister(intr_handle,
2596                                 i40e_dev_interrupt_handler, dev);
2597                 if (ret >= 0 || ret == -ENOENT) {
2598                         break;
2599                 } else if (ret != -EAGAIN) {
2600                         PMD_INIT_LOG(ERR,
2601                                  "intr callback unregister failed: %d",
2602                                  ret);
2603                 }
2604                 i40e_msec_delay(500);
2605         } while (retries++ < 5);
2606
2607         i40e_rm_ethtype_filter_list(pf);
2608         i40e_rm_tunnel_filter_list(pf);
2609         i40e_rm_fdir_filter_list(pf);
2610
2611         /* Remove all flows */
2612         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2613                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2614                 rte_free(p_flow);
2615         }
2616
2617         /* Remove all Traffic Manager configuration */
2618         i40e_tm_conf_uninit(dev);
2619
2620         hw->adapter_closed = 1;
2621 }
2622
2623 /*
2624  * Reset PF device only to re-initialize resources in PMD layer
2625  */
2626 static int
2627 i40e_dev_reset(struct rte_eth_dev *dev)
2628 {
2629         int ret;
2630
2631         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2632          * its VF to make them align with it. The detailed notification
2633          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2634          * To avoid unexpected behavior in VF, currently reset of PF with
2635          * SR-IOV activation is not supported. It might be supported later.
2636          */
2637         if (dev->data->sriov.active)
2638                 return -ENOTSUP;
2639
2640         ret = eth_i40e_dev_uninit(dev);
2641         if (ret)
2642                 return ret;
2643
2644         ret = eth_i40e_dev_init(dev, NULL);
2645
2646         return ret;
2647 }
2648
2649 static int
2650 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2651 {
2652         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2653         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2654         struct i40e_vsi *vsi = pf->main_vsi;
2655         int status;
2656
2657         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2658                                                      true, NULL, true);
2659         if (status != I40E_SUCCESS) {
2660                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2661                 return -EAGAIN;
2662         }
2663
2664         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2665                                                         TRUE, NULL);
2666         if (status != I40E_SUCCESS) {
2667                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2668                 /* Rollback unicast promiscuous mode */
2669                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2670                                                     false, NULL, true);
2671                 return -EAGAIN;
2672         }
2673
2674         return 0;
2675 }
2676
2677 static int
2678 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2679 {
2680         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2681         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2682         struct i40e_vsi *vsi = pf->main_vsi;
2683         int status;
2684
2685         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2686                                                      false, NULL, true);
2687         if (status != I40E_SUCCESS) {
2688                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2689                 return -EAGAIN;
2690         }
2691
2692         /* must remain in all_multicast mode */
2693         if (dev->data->all_multicast == 1)
2694                 return 0;
2695
2696         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2697                                                         false, NULL);
2698         if (status != I40E_SUCCESS) {
2699                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2700                 /* Rollback unicast promiscuous mode */
2701                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2702                                                     true, NULL, true);
2703                 return -EAGAIN;
2704         }
2705
2706         return 0;
2707 }
2708
2709 static int
2710 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2711 {
2712         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2714         struct i40e_vsi *vsi = pf->main_vsi;
2715         int ret;
2716
2717         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2718         if (ret != I40E_SUCCESS) {
2719                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2720                 return -EAGAIN;
2721         }
2722
2723         return 0;
2724 }
2725
2726 static int
2727 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2728 {
2729         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2730         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2731         struct i40e_vsi *vsi = pf->main_vsi;
2732         int ret;
2733
2734         if (dev->data->promiscuous == 1)
2735                 return 0; /* must remain in all_multicast mode */
2736
2737         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2738                                 vsi->seid, FALSE, NULL);
2739         if (ret != I40E_SUCCESS) {
2740                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2741                 return -EAGAIN;
2742         }
2743
2744         return 0;
2745 }
2746
2747 /*
2748  * Set device link up.
2749  */
2750 static int
2751 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2752 {
2753         /* re-apply link speed setting */
2754         return i40e_apply_link_speed(dev);
2755 }
2756
2757 /*
2758  * Set device link down.
2759  */
2760 static int
2761 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2762 {
2763         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2764         uint8_t abilities = 0;
2765         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2766
2767         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2768         return i40e_phy_conf_link(hw, abilities, speed, false);
2769 }
2770
2771 static __rte_always_inline void
2772 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2773 {
2774 /* Link status registers and values*/
2775 #define I40E_PRTMAC_LINKSTA             0x001E2420
2776 #define I40E_REG_LINK_UP                0x40000080
2777 #define I40E_PRTMAC_MACC                0x001E24E0
2778 #define I40E_REG_MACC_25GB              0x00020000
2779 #define I40E_REG_SPEED_MASK             0x38000000
2780 #define I40E_REG_SPEED_0                0x00000000
2781 #define I40E_REG_SPEED_1                0x08000000
2782 #define I40E_REG_SPEED_2                0x10000000
2783 #define I40E_REG_SPEED_3                0x18000000
2784 #define I40E_REG_SPEED_4                0x20000000
2785         uint32_t link_speed;
2786         uint32_t reg_val;
2787
2788         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2789         link_speed = reg_val & I40E_REG_SPEED_MASK;
2790         reg_val &= I40E_REG_LINK_UP;
2791         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2792
2793         if (unlikely(link->link_status == 0))
2794                 return;
2795
2796         /* Parse the link status */
2797         switch (link_speed) {
2798         case I40E_REG_SPEED_0:
2799                 link->link_speed = ETH_SPEED_NUM_100M;
2800                 break;
2801         case I40E_REG_SPEED_1:
2802                 link->link_speed = ETH_SPEED_NUM_1G;
2803                 break;
2804         case I40E_REG_SPEED_2:
2805                 if (hw->mac.type == I40E_MAC_X722)
2806                         link->link_speed = ETH_SPEED_NUM_2_5G;
2807                 else
2808                         link->link_speed = ETH_SPEED_NUM_10G;
2809                 break;
2810         case I40E_REG_SPEED_3:
2811                 if (hw->mac.type == I40E_MAC_X722) {
2812                         link->link_speed = ETH_SPEED_NUM_5G;
2813                 } else {
2814                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2815
2816                         if (reg_val & I40E_REG_MACC_25GB)
2817                                 link->link_speed = ETH_SPEED_NUM_25G;
2818                         else
2819                                 link->link_speed = ETH_SPEED_NUM_40G;
2820                 }
2821                 break;
2822         case I40E_REG_SPEED_4:
2823                 if (hw->mac.type == I40E_MAC_X722)
2824                         link->link_speed = ETH_SPEED_NUM_10G;
2825                 else
2826                         link->link_speed = ETH_SPEED_NUM_20G;
2827                 break;
2828         default:
2829                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2830                 break;
2831         }
2832 }
2833
2834 static __rte_always_inline void
2835 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2836         bool enable_lse, int wait_to_complete)
2837 {
2838 #define CHECK_INTERVAL             100  /* 100ms */
2839 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2840         uint32_t rep_cnt = MAX_REPEAT_TIME;
2841         struct i40e_link_status link_status;
2842         int status;
2843
2844         memset(&link_status, 0, sizeof(link_status));
2845
2846         do {
2847                 memset(&link_status, 0, sizeof(link_status));
2848
2849                 /* Get link status information from hardware */
2850                 status = i40e_aq_get_link_info(hw, enable_lse,
2851                                                 &link_status, NULL);
2852                 if (unlikely(status != I40E_SUCCESS)) {
2853                         link->link_speed = ETH_SPEED_NUM_NONE;
2854                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2855                         PMD_DRV_LOG(ERR, "Failed to get link info");
2856                         return;
2857                 }
2858
2859                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2860                 if (!wait_to_complete || link->link_status)
2861                         break;
2862
2863                 rte_delay_ms(CHECK_INTERVAL);
2864         } while (--rep_cnt);
2865
2866         /* Parse the link status */
2867         switch (link_status.link_speed) {
2868         case I40E_LINK_SPEED_100MB:
2869                 link->link_speed = ETH_SPEED_NUM_100M;
2870                 break;
2871         case I40E_LINK_SPEED_1GB:
2872                 link->link_speed = ETH_SPEED_NUM_1G;
2873                 break;
2874         case I40E_LINK_SPEED_10GB:
2875                 link->link_speed = ETH_SPEED_NUM_10G;
2876                 break;
2877         case I40E_LINK_SPEED_20GB:
2878                 link->link_speed = ETH_SPEED_NUM_20G;
2879                 break;
2880         case I40E_LINK_SPEED_25GB:
2881                 link->link_speed = ETH_SPEED_NUM_25G;
2882                 break;
2883         case I40E_LINK_SPEED_40GB:
2884                 link->link_speed = ETH_SPEED_NUM_40G;
2885                 break;
2886         default:
2887                 link->link_speed = ETH_SPEED_NUM_NONE;
2888                 break;
2889         }
2890 }
2891
2892 int
2893 i40e_dev_link_update(struct rte_eth_dev *dev,
2894                      int wait_to_complete)
2895 {
2896         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2897         struct rte_eth_link link;
2898         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2899         int ret;
2900
2901         memset(&link, 0, sizeof(link));
2902
2903         /* i40e uses full duplex only */
2904         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2905         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2906                         ETH_LINK_SPEED_FIXED);
2907
2908         if (!wait_to_complete && !enable_lse)
2909                 update_link_reg(hw, &link);
2910         else
2911                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2912
2913         if (hw->switch_dev)
2914                 rte_eth_linkstatus_get(hw->switch_dev, &link);
2915
2916         ret = rte_eth_linkstatus_set(dev, &link);
2917         i40e_notify_all_vfs_link_status(dev);
2918
2919         return ret;
2920 }
2921
2922 /* Get all the statistics of a VSI */
2923 void
2924 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2925 {
2926         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2927         struct i40e_eth_stats *nes = &vsi->eth_stats;
2928         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2929         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2930
2931         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2932                             vsi->offset_loaded, &oes->rx_bytes,
2933                             &nes->rx_bytes);
2934         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2935                             vsi->offset_loaded, &oes->rx_unicast,
2936                             &nes->rx_unicast);
2937         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2938                             vsi->offset_loaded, &oes->rx_multicast,
2939                             &nes->rx_multicast);
2940         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2941                             vsi->offset_loaded, &oes->rx_broadcast,
2942                             &nes->rx_broadcast);
2943         /* exclude CRC bytes */
2944         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2945                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2946
2947         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2948                             &oes->rx_discards, &nes->rx_discards);
2949         /* GLV_REPC not supported */
2950         /* GLV_RMPC not supported */
2951         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2952                             &oes->rx_unknown_protocol,
2953                             &nes->rx_unknown_protocol);
2954         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2955                             vsi->offset_loaded, &oes->tx_bytes,
2956                             &nes->tx_bytes);
2957         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2958                             vsi->offset_loaded, &oes->tx_unicast,
2959                             &nes->tx_unicast);
2960         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2961                             vsi->offset_loaded, &oes->tx_multicast,
2962                             &nes->tx_multicast);
2963         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2964                             vsi->offset_loaded,  &oes->tx_broadcast,
2965                             &nes->tx_broadcast);
2966         /* GLV_TDPC not supported */
2967         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2968                             &oes->tx_errors, &nes->tx_errors);
2969         vsi->offset_loaded = true;
2970
2971         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2972                     vsi->vsi_id);
2973         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2974         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2975         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2976         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2977         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2978         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2979                     nes->rx_unknown_protocol);
2980         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2981         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2982         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2983         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2984         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2985         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2986         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2987                     vsi->vsi_id);
2988 }
2989
2990 static void
2991 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2992 {
2993         unsigned int i;
2994         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2995         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2996
2997         /* Get rx/tx bytes of internal transfer packets */
2998         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2999                         I40E_GLV_GORCL(hw->port),
3000                         pf->offset_loaded,
3001                         &pf->internal_stats_offset.rx_bytes,
3002                         &pf->internal_stats.rx_bytes);
3003
3004         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
3005                         I40E_GLV_GOTCL(hw->port),
3006                         pf->offset_loaded,
3007                         &pf->internal_stats_offset.tx_bytes,
3008                         &pf->internal_stats.tx_bytes);
3009         /* Get total internal rx packet count */
3010         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3011                             I40E_GLV_UPRCL(hw->port),
3012                             pf->offset_loaded,
3013                             &pf->internal_stats_offset.rx_unicast,
3014                             &pf->internal_stats.rx_unicast);
3015         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3016                             I40E_GLV_MPRCL(hw->port),
3017                             pf->offset_loaded,
3018                             &pf->internal_stats_offset.rx_multicast,
3019                             &pf->internal_stats.rx_multicast);
3020         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3021                             I40E_GLV_BPRCL(hw->port),
3022                             pf->offset_loaded,
3023                             &pf->internal_stats_offset.rx_broadcast,
3024                             &pf->internal_stats.rx_broadcast);
3025         /* Get total internal tx packet count */
3026         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3027                             I40E_GLV_UPTCL(hw->port),
3028                             pf->offset_loaded,
3029                             &pf->internal_stats_offset.tx_unicast,
3030                             &pf->internal_stats.tx_unicast);
3031         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3032                             I40E_GLV_MPTCL(hw->port),
3033                             pf->offset_loaded,
3034                             &pf->internal_stats_offset.tx_multicast,
3035                             &pf->internal_stats.tx_multicast);
3036         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3037                             I40E_GLV_BPTCL(hw->port),
3038                             pf->offset_loaded,
3039                             &pf->internal_stats_offset.tx_broadcast,
3040                             &pf->internal_stats.tx_broadcast);
3041
3042         /* exclude CRC size */
3043         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3044                 pf->internal_stats.rx_multicast +
3045                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3046
3047         /* Get statistics of struct i40e_eth_stats */
3048         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3049                             I40E_GLPRT_GORCL(hw->port),
3050                             pf->offset_loaded, &os->eth.rx_bytes,
3051                             &ns->eth.rx_bytes);
3052         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3053                             I40E_GLPRT_UPRCL(hw->port),
3054                             pf->offset_loaded, &os->eth.rx_unicast,
3055                             &ns->eth.rx_unicast);
3056         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3057                             I40E_GLPRT_MPRCL(hw->port),
3058                             pf->offset_loaded, &os->eth.rx_multicast,
3059                             &ns->eth.rx_multicast);
3060         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3061                             I40E_GLPRT_BPRCL(hw->port),
3062                             pf->offset_loaded, &os->eth.rx_broadcast,
3063                             &ns->eth.rx_broadcast);
3064         /* Workaround: CRC size should not be included in byte statistics,
3065          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3066          * packet.
3067          */
3068         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3069                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3070
3071         /* exclude internal rx bytes
3072          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3073          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3074          * value.
3075          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3076          */
3077         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3078                 ns->eth.rx_bytes = 0;
3079         else
3080                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3081
3082         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3083                 ns->eth.rx_unicast = 0;
3084         else
3085                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3086
3087         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3088                 ns->eth.rx_multicast = 0;
3089         else
3090                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3091
3092         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3093                 ns->eth.rx_broadcast = 0;
3094         else
3095                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3096
3097         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3098                             pf->offset_loaded, &os->eth.rx_discards,
3099                             &ns->eth.rx_discards);
3100         /* GLPRT_REPC not supported */
3101         /* GLPRT_RMPC not supported */
3102         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3103                             pf->offset_loaded,
3104                             &os->eth.rx_unknown_protocol,
3105                             &ns->eth.rx_unknown_protocol);
3106         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3107                             I40E_GLPRT_GOTCL(hw->port),
3108                             pf->offset_loaded, &os->eth.tx_bytes,
3109                             &ns->eth.tx_bytes);
3110         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3111                             I40E_GLPRT_UPTCL(hw->port),
3112                             pf->offset_loaded, &os->eth.tx_unicast,
3113                             &ns->eth.tx_unicast);
3114         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3115                             I40E_GLPRT_MPTCL(hw->port),
3116                             pf->offset_loaded, &os->eth.tx_multicast,
3117                             &ns->eth.tx_multicast);
3118         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3119                             I40E_GLPRT_BPTCL(hw->port),
3120                             pf->offset_loaded, &os->eth.tx_broadcast,
3121                             &ns->eth.tx_broadcast);
3122         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3123                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3124
3125         /* exclude internal tx bytes
3126          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3127          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3128          * value.
3129          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3130          */
3131         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3132                 ns->eth.tx_bytes = 0;
3133         else
3134                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3135
3136         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3137                 ns->eth.tx_unicast = 0;
3138         else
3139                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3140
3141         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3142                 ns->eth.tx_multicast = 0;
3143         else
3144                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3145
3146         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3147                 ns->eth.tx_broadcast = 0;
3148         else
3149                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3150
3151         /* GLPRT_TEPC not supported */
3152
3153         /* additional port specific stats */
3154         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3155                             pf->offset_loaded, &os->tx_dropped_link_down,
3156                             &ns->tx_dropped_link_down);
3157         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3158                             pf->offset_loaded, &os->crc_errors,
3159                             &ns->crc_errors);
3160         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3161                             pf->offset_loaded, &os->illegal_bytes,
3162                             &ns->illegal_bytes);
3163         /* GLPRT_ERRBC not supported */
3164         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3165                             pf->offset_loaded, &os->mac_local_faults,
3166                             &ns->mac_local_faults);
3167         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3168                             pf->offset_loaded, &os->mac_remote_faults,
3169                             &ns->mac_remote_faults);
3170         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3171                             pf->offset_loaded, &os->rx_length_errors,
3172                             &ns->rx_length_errors);
3173         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3174                             pf->offset_loaded, &os->link_xon_rx,
3175                             &ns->link_xon_rx);
3176         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3177                             pf->offset_loaded, &os->link_xoff_rx,
3178                             &ns->link_xoff_rx);
3179         for (i = 0; i < 8; i++) {
3180                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3181                                     pf->offset_loaded,
3182                                     &os->priority_xon_rx[i],
3183                                     &ns->priority_xon_rx[i]);
3184                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3185                                     pf->offset_loaded,
3186                                     &os->priority_xoff_rx[i],
3187                                     &ns->priority_xoff_rx[i]);
3188         }
3189         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3190                             pf->offset_loaded, &os->link_xon_tx,
3191                             &ns->link_xon_tx);
3192         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3193                             pf->offset_loaded, &os->link_xoff_tx,
3194                             &ns->link_xoff_tx);
3195         for (i = 0; i < 8; i++) {
3196                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3197                                     pf->offset_loaded,
3198                                     &os->priority_xon_tx[i],
3199                                     &ns->priority_xon_tx[i]);
3200                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3201                                     pf->offset_loaded,
3202                                     &os->priority_xoff_tx[i],
3203                                     &ns->priority_xoff_tx[i]);
3204                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3205                                     pf->offset_loaded,
3206                                     &os->priority_xon_2_xoff[i],
3207                                     &ns->priority_xon_2_xoff[i]);
3208         }
3209         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3210                             I40E_GLPRT_PRC64L(hw->port),
3211                             pf->offset_loaded, &os->rx_size_64,
3212                             &ns->rx_size_64);
3213         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3214                             I40E_GLPRT_PRC127L(hw->port),
3215                             pf->offset_loaded, &os->rx_size_127,
3216                             &ns->rx_size_127);
3217         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3218                             I40E_GLPRT_PRC255L(hw->port),
3219                             pf->offset_loaded, &os->rx_size_255,
3220                             &ns->rx_size_255);
3221         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3222                             I40E_GLPRT_PRC511L(hw->port),
3223                             pf->offset_loaded, &os->rx_size_511,
3224                             &ns->rx_size_511);
3225         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3226                             I40E_GLPRT_PRC1023L(hw->port),
3227                             pf->offset_loaded, &os->rx_size_1023,
3228                             &ns->rx_size_1023);
3229         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3230                             I40E_GLPRT_PRC1522L(hw->port),
3231                             pf->offset_loaded, &os->rx_size_1522,
3232                             &ns->rx_size_1522);
3233         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3234                             I40E_GLPRT_PRC9522L(hw->port),
3235                             pf->offset_loaded, &os->rx_size_big,
3236                             &ns->rx_size_big);
3237         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3238                             pf->offset_loaded, &os->rx_undersize,
3239                             &ns->rx_undersize);
3240         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3241                             pf->offset_loaded, &os->rx_fragments,
3242                             &ns->rx_fragments);
3243         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3244                             pf->offset_loaded, &os->rx_oversize,
3245                             &ns->rx_oversize);
3246         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3247                             pf->offset_loaded, &os->rx_jabber,
3248                             &ns->rx_jabber);
3249         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3250                             I40E_GLPRT_PTC64L(hw->port),
3251                             pf->offset_loaded, &os->tx_size_64,
3252                             &ns->tx_size_64);
3253         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3254                             I40E_GLPRT_PTC127L(hw->port),
3255                             pf->offset_loaded, &os->tx_size_127,
3256                             &ns->tx_size_127);
3257         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3258                             I40E_GLPRT_PTC255L(hw->port),
3259                             pf->offset_loaded, &os->tx_size_255,
3260                             &ns->tx_size_255);
3261         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3262                             I40E_GLPRT_PTC511L(hw->port),
3263                             pf->offset_loaded, &os->tx_size_511,
3264                             &ns->tx_size_511);
3265         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3266                             I40E_GLPRT_PTC1023L(hw->port),
3267                             pf->offset_loaded, &os->tx_size_1023,
3268                             &ns->tx_size_1023);
3269         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3270                             I40E_GLPRT_PTC1522L(hw->port),
3271                             pf->offset_loaded, &os->tx_size_1522,
3272                             &ns->tx_size_1522);
3273         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3274                             I40E_GLPRT_PTC9522L(hw->port),
3275                             pf->offset_loaded, &os->tx_size_big,
3276                             &ns->tx_size_big);
3277         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3278                            pf->offset_loaded,
3279                            &os->fd_sb_match, &ns->fd_sb_match);
3280         /* GLPRT_MSPDC not supported */
3281         /* GLPRT_XEC not supported */
3282
3283         pf->offset_loaded = true;
3284
3285         if (pf->main_vsi)
3286                 i40e_update_vsi_stats(pf->main_vsi);
3287 }
3288
3289 /* Get all statistics of a port */
3290 static int
3291 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3292 {
3293         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3294         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3295         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3296         struct i40e_vsi *vsi;
3297         unsigned i;
3298
3299         /* call read registers - updates values, now write them to struct */
3300         i40e_read_stats_registers(pf, hw);
3301
3302         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3303                         pf->main_vsi->eth_stats.rx_multicast +
3304                         pf->main_vsi->eth_stats.rx_broadcast -
3305                         pf->main_vsi->eth_stats.rx_discards;
3306         stats->opackets = ns->eth.tx_unicast +
3307                         ns->eth.tx_multicast +
3308                         ns->eth.tx_broadcast;
3309         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3310         stats->obytes   = ns->eth.tx_bytes;
3311         stats->oerrors  = ns->eth.tx_errors +
3312                         pf->main_vsi->eth_stats.tx_errors;
3313
3314         /* Rx Errors */
3315         stats->imissed  = ns->eth.rx_discards +
3316                         pf->main_vsi->eth_stats.rx_discards;
3317         stats->ierrors  = ns->crc_errors +
3318                         ns->rx_length_errors + ns->rx_undersize +
3319                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3320
3321         if (pf->vfs) {
3322                 for (i = 0; i < pf->vf_num; i++) {
3323                         vsi = pf->vfs[i].vsi;
3324                         i40e_update_vsi_stats(vsi);
3325
3326                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3327                                         vsi->eth_stats.rx_multicast +
3328                                         vsi->eth_stats.rx_broadcast -
3329                                         vsi->eth_stats.rx_discards);
3330                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3331                         stats->oerrors  += vsi->eth_stats.tx_errors;
3332                         stats->imissed  += vsi->eth_stats.rx_discards;
3333                 }
3334         }
3335
3336         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3337         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3338         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3339         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3340         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3341         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3342         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3343                     ns->eth.rx_unknown_protocol);
3344         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3345         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3346         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3347         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3348         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3349         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3350
3351         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3352                     ns->tx_dropped_link_down);
3353         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3354         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3355                     ns->illegal_bytes);
3356         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3357         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3358                     ns->mac_local_faults);
3359         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3360                     ns->mac_remote_faults);
3361         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3362                     ns->rx_length_errors);
3363         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3364         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3365         for (i = 0; i < 8; i++) {
3366                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3367                                 i, ns->priority_xon_rx[i]);
3368                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3369                                 i, ns->priority_xoff_rx[i]);
3370         }
3371         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3372         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3373         for (i = 0; i < 8; i++) {
3374                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3375                                 i, ns->priority_xon_tx[i]);
3376                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3377                                 i, ns->priority_xoff_tx[i]);
3378                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3379                                 i, ns->priority_xon_2_xoff[i]);
3380         }
3381         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3382         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3383         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3384         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3385         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3386         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3387         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3388         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3389         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3390         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3391         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3392         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3393         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3394         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3395         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3396         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3397         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3398         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3399         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3400                         ns->mac_short_packet_dropped);
3401         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3402                     ns->checksum_error);
3403         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3404         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3405         return 0;
3406 }
3407
3408 /* Reset the statistics */
3409 static int
3410 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3411 {
3412         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3413         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3414
3415         /* Mark PF and VSI stats to update the offset, aka "reset" */
3416         pf->offset_loaded = false;
3417         if (pf->main_vsi)
3418                 pf->main_vsi->offset_loaded = false;
3419
3420         /* read the stats, reading current register values into offset */
3421         i40e_read_stats_registers(pf, hw);
3422
3423         return 0;
3424 }
3425
3426 static uint32_t
3427 i40e_xstats_calc_num(void)
3428 {
3429         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3430                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3431                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3432 }
3433
3434 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3435                                      struct rte_eth_xstat_name *xstats_names,
3436                                      __rte_unused unsigned limit)
3437 {
3438         unsigned count = 0;
3439         unsigned i, prio;
3440
3441         if (xstats_names == NULL)
3442                 return i40e_xstats_calc_num();
3443
3444         /* Note: limit checked in rte_eth_xstats_names() */
3445
3446         /* Get stats from i40e_eth_stats struct */
3447         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3448                 strlcpy(xstats_names[count].name,
3449                         rte_i40e_stats_strings[i].name,
3450                         sizeof(xstats_names[count].name));
3451                 count++;
3452         }
3453
3454         /* Get individiual stats from i40e_hw_port struct */
3455         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3456                 strlcpy(xstats_names[count].name,
3457                         rte_i40e_hw_port_strings[i].name,
3458                         sizeof(xstats_names[count].name));
3459                 count++;
3460         }
3461
3462         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3463                 for (prio = 0; prio < 8; prio++) {
3464                         snprintf(xstats_names[count].name,
3465                                  sizeof(xstats_names[count].name),
3466                                  "rx_priority%u_%s", prio,
3467                                  rte_i40e_rxq_prio_strings[i].name);
3468                         count++;
3469                 }
3470         }
3471
3472         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3473                 for (prio = 0; prio < 8; prio++) {
3474                         snprintf(xstats_names[count].name,
3475                                  sizeof(xstats_names[count].name),
3476                                  "tx_priority%u_%s", prio,
3477                                  rte_i40e_txq_prio_strings[i].name);
3478                         count++;
3479                 }
3480         }
3481         return count;
3482 }
3483
3484 static int
3485 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3486                     unsigned n)
3487 {
3488         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3489         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3490         unsigned i, count, prio;
3491         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3492
3493         count = i40e_xstats_calc_num();
3494         if (n < count)
3495                 return count;
3496
3497         i40e_read_stats_registers(pf, hw);
3498
3499         if (xstats == NULL)
3500                 return 0;
3501
3502         count = 0;
3503
3504         /* Get stats from i40e_eth_stats struct */
3505         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3506                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3507                         rte_i40e_stats_strings[i].offset);
3508                 xstats[count].id = count;
3509                 count++;
3510         }
3511
3512         /* Get individiual stats from i40e_hw_port struct */
3513         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3514                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3515                         rte_i40e_hw_port_strings[i].offset);
3516                 xstats[count].id = count;
3517                 count++;
3518         }
3519
3520         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3521                 for (prio = 0; prio < 8; prio++) {
3522                         xstats[count].value =
3523                                 *(uint64_t *)(((char *)hw_stats) +
3524                                 rte_i40e_rxq_prio_strings[i].offset +
3525                                 (sizeof(uint64_t) * prio));
3526                         xstats[count].id = count;
3527                         count++;
3528                 }
3529         }
3530
3531         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3532                 for (prio = 0; prio < 8; prio++) {
3533                         xstats[count].value =
3534                                 *(uint64_t *)(((char *)hw_stats) +
3535                                 rte_i40e_txq_prio_strings[i].offset +
3536                                 (sizeof(uint64_t) * prio));
3537                         xstats[count].id = count;
3538                         count++;
3539                 }
3540         }
3541
3542         return count;
3543 }
3544
3545 static int
3546 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3547 {
3548         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3549         u32 full_ver;
3550         u8 ver, patch;
3551         u16 build;
3552         int ret;
3553
3554         full_ver = hw->nvm.oem_ver;
3555         ver = (u8)(full_ver >> 24);
3556         build = (u16)((full_ver >> 8) & 0xffff);
3557         patch = (u8)(full_ver & 0xff);
3558
3559         ret = snprintf(fw_version, fw_size,
3560                  "%d.%d%d 0x%08x %d.%d.%d",
3561                  ((hw->nvm.version >> 12) & 0xf),
3562                  ((hw->nvm.version >> 4) & 0xff),
3563                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3564                  ver, build, patch);
3565
3566         ret += 1; /* add the size of '\0' */
3567         if (fw_size < (u32)ret)
3568                 return ret;
3569         else
3570                 return 0;
3571 }
3572
3573 /*
3574  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3575  * the Rx data path does not hang if the FW LLDP is stopped.
3576  * return true if lldp need to stop
3577  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3578  */
3579 static bool
3580 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3581 {
3582         double nvm_ver;
3583         char ver_str[64] = {0};
3584         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3585
3586         i40e_fw_version_get(dev, ver_str, 64);
3587         nvm_ver = atof(ver_str);
3588         if ((hw->mac.type == I40E_MAC_X722 ||
3589              hw->mac.type == I40E_MAC_X722_VF) &&
3590              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3591                 return true;
3592         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3593                 return true;
3594
3595         return false;
3596 }
3597
3598 static int
3599 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3600 {
3601         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3602         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3603         struct i40e_vsi *vsi = pf->main_vsi;
3604         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3605
3606         dev_info->max_rx_queues = vsi->nb_qps;
3607         dev_info->max_tx_queues = vsi->nb_qps;
3608         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3609         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3610         dev_info->max_mac_addrs = vsi->max_macaddrs;
3611         dev_info->max_vfs = pci_dev->max_vfs;
3612         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3613         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3614         dev_info->rx_queue_offload_capa = 0;
3615         dev_info->rx_offload_capa =
3616                 DEV_RX_OFFLOAD_VLAN_STRIP |
3617                 DEV_RX_OFFLOAD_QINQ_STRIP |
3618                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3619                 DEV_RX_OFFLOAD_UDP_CKSUM |
3620                 DEV_RX_OFFLOAD_TCP_CKSUM |
3621                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3622                 DEV_RX_OFFLOAD_KEEP_CRC |
3623                 DEV_RX_OFFLOAD_SCATTER |
3624                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3625                 DEV_RX_OFFLOAD_VLAN_FILTER |
3626                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3627                 DEV_RX_OFFLOAD_RSS_HASH;
3628
3629         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3630         dev_info->tx_offload_capa =
3631                 DEV_TX_OFFLOAD_VLAN_INSERT |
3632                 DEV_TX_OFFLOAD_QINQ_INSERT |
3633                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3634                 DEV_TX_OFFLOAD_UDP_CKSUM |
3635                 DEV_TX_OFFLOAD_TCP_CKSUM |
3636                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3637                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3638                 DEV_TX_OFFLOAD_TCP_TSO |
3639                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3640                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3641                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3642                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3643                 DEV_TX_OFFLOAD_MULTI_SEGS |
3644                 dev_info->tx_queue_offload_capa;
3645         dev_info->dev_capa =
3646                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3647                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3648
3649         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3650                                                 sizeof(uint32_t);
3651         dev_info->reta_size = pf->hash_lut_size;
3652         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3653
3654         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3655                 .rx_thresh = {
3656                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3657                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3658                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3659                 },
3660                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3661                 .rx_drop_en = 0,
3662                 .offloads = 0,
3663         };
3664
3665         dev_info->default_txconf = (struct rte_eth_txconf) {
3666                 .tx_thresh = {
3667                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3668                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3669                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3670                 },
3671                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3672                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3673                 .offloads = 0,
3674         };
3675
3676         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3677                 .nb_max = I40E_MAX_RING_DESC,
3678                 .nb_min = I40E_MIN_RING_DESC,
3679                 .nb_align = I40E_ALIGN_RING_DESC,
3680         };
3681
3682         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3683                 .nb_max = I40E_MAX_RING_DESC,
3684                 .nb_min = I40E_MIN_RING_DESC,
3685                 .nb_align = I40E_ALIGN_RING_DESC,
3686                 .nb_seg_max = I40E_TX_MAX_SEG,
3687                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3688         };
3689
3690         if (pf->flags & I40E_FLAG_VMDQ) {
3691                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3692                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3693                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3694                                                 pf->max_nb_vmdq_vsi;
3695                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3696                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3697                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3698         }
3699
3700         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3701                 /* For XL710 */
3702                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3703                 dev_info->default_rxportconf.nb_queues = 2;
3704                 dev_info->default_txportconf.nb_queues = 2;
3705                 if (dev->data->nb_rx_queues == 1)
3706                         dev_info->default_rxportconf.ring_size = 2048;
3707                 else
3708                         dev_info->default_rxportconf.ring_size = 1024;
3709                 if (dev->data->nb_tx_queues == 1)
3710                         dev_info->default_txportconf.ring_size = 1024;
3711                 else
3712                         dev_info->default_txportconf.ring_size = 512;
3713
3714         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3715                 /* For XXV710 */
3716                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3717                 dev_info->default_rxportconf.nb_queues = 1;
3718                 dev_info->default_txportconf.nb_queues = 1;
3719                 dev_info->default_rxportconf.ring_size = 256;
3720                 dev_info->default_txportconf.ring_size = 256;
3721         } else {
3722                 /* For X710 */
3723                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3724                 dev_info->default_rxportconf.nb_queues = 1;
3725                 dev_info->default_txportconf.nb_queues = 1;
3726                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3727                         dev_info->default_rxportconf.ring_size = 512;
3728                         dev_info->default_txportconf.ring_size = 256;
3729                 } else {
3730                         dev_info->default_rxportconf.ring_size = 256;
3731                         dev_info->default_txportconf.ring_size = 256;
3732                 }
3733         }
3734         dev_info->default_rxportconf.burst_size = 32;
3735         dev_info->default_txportconf.burst_size = 32;
3736
3737         return 0;
3738 }
3739
3740 static int
3741 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3742 {
3743         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3744         struct i40e_vsi *vsi = pf->main_vsi;
3745         PMD_INIT_FUNC_TRACE();
3746
3747         if (on)
3748                 return i40e_vsi_add_vlan(vsi, vlan_id);
3749         else
3750                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3751 }
3752
3753 static int
3754 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3755                                 enum rte_vlan_type vlan_type,
3756                                 uint16_t tpid, int qinq)
3757 {
3758         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3759         uint64_t reg_r = 0;
3760         uint64_t reg_w = 0;
3761         uint16_t reg_id = 3;
3762         int ret;
3763
3764         if (qinq) {
3765                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3766                         reg_id = 2;
3767         }
3768
3769         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3770                                           &reg_r, NULL);
3771         if (ret != I40E_SUCCESS) {
3772                 PMD_DRV_LOG(ERR,
3773                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3774                            reg_id);
3775                 return -EIO;
3776         }
3777         PMD_DRV_LOG(DEBUG,
3778                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3779                     reg_id, reg_r);
3780
3781         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3782         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3783         if (reg_r == reg_w) {
3784                 PMD_DRV_LOG(DEBUG, "No need to write");
3785                 return 0;
3786         }
3787
3788         ret = i40e_aq_debug_write_global_register(hw,
3789                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3790                                            reg_w, NULL);
3791         if (ret != I40E_SUCCESS) {
3792                 PMD_DRV_LOG(ERR,
3793                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3794                             reg_id);
3795                 return -EIO;
3796         }
3797         PMD_DRV_LOG(DEBUG,
3798                     "Global register 0x%08x is changed with value 0x%08x",
3799                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3800
3801         return 0;
3802 }
3803
3804 static int
3805 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3806                    enum rte_vlan_type vlan_type,
3807                    uint16_t tpid)
3808 {
3809         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3810         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3811         int qinq = dev->data->dev_conf.rxmode.offloads &
3812                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3813         int ret = 0;
3814
3815         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3816              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3817             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3818                 PMD_DRV_LOG(ERR,
3819                             "Unsupported vlan type.");
3820                 return -EINVAL;
3821         }
3822
3823         if (pf->support_multi_driver) {
3824                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3825                 return -ENOTSUP;
3826         }
3827
3828         /* 802.1ad frames ability is added in NVM API 1.7*/
3829         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3830                 if (qinq) {
3831                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3832                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3833                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3834                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3835                 } else {
3836                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3837                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3838                 }
3839                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3840                 if (ret != I40E_SUCCESS) {
3841                         PMD_DRV_LOG(ERR,
3842                                     "Set switch config failed aq_err: %d",
3843                                     hw->aq.asq_last_status);
3844                         ret = -EIO;
3845                 }
3846         } else
3847                 /* If NVM API < 1.7, keep the register setting */
3848                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3849                                                       tpid, qinq);
3850
3851         return ret;
3852 }
3853
3854 static int
3855 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3856 {
3857         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3858         struct i40e_vsi *vsi = pf->main_vsi;
3859         struct rte_eth_rxmode *rxmode;
3860
3861         if (mask & ETH_QINQ_STRIP_MASK) {
3862                 PMD_DRV_LOG(ERR, "Strip qinq is not supported.");
3863                 return -ENOTSUP;
3864         }
3865
3866         rxmode = &dev->data->dev_conf.rxmode;
3867         if (mask & ETH_VLAN_FILTER_MASK) {
3868                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3869                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3870                 else
3871                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3872         }
3873
3874         if (mask & ETH_VLAN_STRIP_MASK) {
3875                 /* Enable or disable VLAN stripping */
3876                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3877                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3878                 else
3879                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3880         }
3881
3882         if (mask & ETH_VLAN_EXTEND_MASK) {
3883                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3884                         i40e_vsi_config_double_vlan(vsi, TRUE);
3885                         /* Set global registers with default ethertype. */
3886                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3887                                            RTE_ETHER_TYPE_VLAN);
3888                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3889                                            RTE_ETHER_TYPE_VLAN);
3890                 }
3891                 else
3892                         i40e_vsi_config_double_vlan(vsi, FALSE);
3893         }
3894
3895         return 0;
3896 }
3897
3898 static void
3899 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3900                           __rte_unused uint16_t queue,
3901                           __rte_unused int on)
3902 {
3903         PMD_INIT_FUNC_TRACE();
3904 }
3905
3906 static int
3907 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3908 {
3909         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3910         struct i40e_vsi *vsi = pf->main_vsi;
3911         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3912         struct i40e_vsi_vlan_pvid_info info;
3913
3914         memset(&info, 0, sizeof(info));
3915         info.on = on;
3916         if (info.on)
3917                 info.config.pvid = pvid;
3918         else {
3919                 info.config.reject.tagged =
3920                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3921                 info.config.reject.untagged =
3922                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3923         }
3924
3925         return i40e_vsi_vlan_pvid_set(vsi, &info);
3926 }
3927
3928 static int
3929 i40e_dev_led_on(struct rte_eth_dev *dev)
3930 {
3931         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3932         uint32_t mode = i40e_led_get(hw);
3933
3934         if (mode == 0)
3935                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3936
3937         return 0;
3938 }
3939
3940 static int
3941 i40e_dev_led_off(struct rte_eth_dev *dev)
3942 {
3943         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3944         uint32_t mode = i40e_led_get(hw);
3945
3946         if (mode != 0)
3947                 i40e_led_set(hw, 0, false);
3948
3949         return 0;
3950 }
3951
3952 static int
3953 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3954 {
3955         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3956         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3957
3958         fc_conf->pause_time = pf->fc_conf.pause_time;
3959
3960         /* read out from register, in case they are modified by other port */
3961         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3962                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3963         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3964                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3965
3966         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3967         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3968
3969          /* Return current mode according to actual setting*/
3970         switch (hw->fc.current_mode) {
3971         case I40E_FC_FULL:
3972                 fc_conf->mode = RTE_FC_FULL;
3973                 break;
3974         case I40E_FC_TX_PAUSE:
3975                 fc_conf->mode = RTE_FC_TX_PAUSE;
3976                 break;
3977         case I40E_FC_RX_PAUSE:
3978                 fc_conf->mode = RTE_FC_RX_PAUSE;
3979                 break;
3980         case I40E_FC_NONE:
3981         default:
3982                 fc_conf->mode = RTE_FC_NONE;
3983         };
3984
3985         return 0;
3986 }
3987
3988 static int
3989 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3990 {
3991         uint32_t mflcn_reg, fctrl_reg, reg;
3992         uint32_t max_high_water;
3993         uint8_t i, aq_failure;
3994         int err;
3995         struct i40e_hw *hw;
3996         struct i40e_pf *pf;
3997         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3998                 [RTE_FC_NONE] = I40E_FC_NONE,
3999                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4000                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4001                 [RTE_FC_FULL] = I40E_FC_FULL
4002         };
4003
4004         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4005
4006         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4007         if ((fc_conf->high_water > max_high_water) ||
4008                         (fc_conf->high_water < fc_conf->low_water)) {
4009                 PMD_INIT_LOG(ERR,
4010                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4011                         max_high_water);
4012                 return -EINVAL;
4013         }
4014
4015         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4016         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4017         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4018
4019         pf->fc_conf.pause_time = fc_conf->pause_time;
4020         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4021         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4022
4023         PMD_INIT_FUNC_TRACE();
4024
4025         /* All the link flow control related enable/disable register
4026          * configuration is handle by the F/W
4027          */
4028         err = i40e_set_fc(hw, &aq_failure, true);
4029         if (err < 0)
4030                 return -ENOSYS;
4031
4032         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4033                 /* Configure flow control refresh threshold,
4034                  * the value for stat_tx_pause_refresh_timer[8]
4035                  * is used for global pause operation.
4036                  */
4037
4038                 I40E_WRITE_REG(hw,
4039                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4040                                pf->fc_conf.pause_time);
4041
4042                 /* configure the timer value included in transmitted pause
4043                  * frame,
4044                  * the value for stat_tx_pause_quanta[8] is used for global
4045                  * pause operation
4046                  */
4047                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4048                                pf->fc_conf.pause_time);
4049
4050                 fctrl_reg = I40E_READ_REG(hw,
4051                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4052
4053                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4054                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4055                 else
4056                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4057
4058                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4059                                fctrl_reg);
4060         } else {
4061                 /* Configure pause time (2 TCs per register) */
4062                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4063                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4064                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4065
4066                 /* Configure flow control refresh threshold value */
4067                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4068                                pf->fc_conf.pause_time / 2);
4069
4070                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4071
4072                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4073                  *depending on configuration
4074                  */
4075                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4076                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4077                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4078                 } else {
4079                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4080                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4081                 }
4082
4083                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4084         }
4085
4086         if (!pf->support_multi_driver) {
4087                 /* config water marker both based on the packets and bytes */
4088                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4089                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4090                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4091                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4092                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4093                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4094                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4095                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4096                                   << I40E_KILOSHIFT);
4097                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4098                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4099                                    << I40E_KILOSHIFT);
4100         } else {
4101                 PMD_DRV_LOG(ERR,
4102                             "Water marker configuration is not supported.");
4103         }
4104
4105         I40E_WRITE_FLUSH(hw);
4106
4107         return 0;
4108 }
4109
4110 static int
4111 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4112                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4113 {
4114         PMD_INIT_FUNC_TRACE();
4115
4116         return -ENOSYS;
4117 }
4118
4119 /* Add a MAC address, and update filters */
4120 static int
4121 i40e_macaddr_add(struct rte_eth_dev *dev,
4122                  struct rte_ether_addr *mac_addr,
4123                  __rte_unused uint32_t index,
4124                  uint32_t pool)
4125 {
4126         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4127         struct i40e_mac_filter_info mac_filter;
4128         struct i40e_vsi *vsi;
4129         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4130         int ret;
4131
4132         /* If VMDQ not enabled or configured, return */
4133         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4134                           !pf->nb_cfg_vmdq_vsi)) {
4135                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4136                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4137                         pool);
4138                 return -ENOTSUP;
4139         }
4140
4141         if (pool > pf->nb_cfg_vmdq_vsi) {
4142                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4143                                 pool, pf->nb_cfg_vmdq_vsi);
4144                 return -EINVAL;
4145         }
4146
4147         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4148         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4149                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4150         else
4151                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4152
4153         if (pool == 0)
4154                 vsi = pf->main_vsi;
4155         else
4156                 vsi = pf->vmdq[pool - 1].vsi;
4157
4158         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4159         if (ret != I40E_SUCCESS) {
4160                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4161                 return -ENODEV;
4162         }
4163         return 0;
4164 }
4165
4166 /* Remove a MAC address, and update filters */
4167 static void
4168 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4169 {
4170         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4171         struct i40e_vsi *vsi;
4172         struct rte_eth_dev_data *data = dev->data;
4173         struct rte_ether_addr *macaddr;
4174         int ret;
4175         uint32_t i;
4176         uint64_t pool_sel;
4177
4178         macaddr = &(data->mac_addrs[index]);
4179
4180         pool_sel = dev->data->mac_pool_sel[index];
4181
4182         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4183                 if (pool_sel & (1ULL << i)) {
4184                         if (i == 0)
4185                                 vsi = pf->main_vsi;
4186                         else {
4187                                 /* No VMDQ pool enabled or configured */
4188                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4189                                         (i > pf->nb_cfg_vmdq_vsi)) {
4190                                         PMD_DRV_LOG(ERR,
4191                                                 "No VMDQ pool enabled/configured");
4192                                         return;
4193                                 }
4194                                 vsi = pf->vmdq[i - 1].vsi;
4195                         }
4196                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4197
4198                         if (ret) {
4199                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4200                                 return;
4201                         }
4202                 }
4203         }
4204 }
4205
4206 /* Set perfect match or hash match of MAC and VLAN for a VF */
4207 static int
4208 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4209                  struct rte_eth_mac_filter *filter,
4210                  bool add)
4211 {
4212         struct i40e_hw *hw;
4213         struct i40e_mac_filter_info mac_filter;
4214         struct rte_ether_addr old_mac;
4215         struct rte_ether_addr *new_mac;
4216         struct i40e_pf_vf *vf = NULL;
4217         uint16_t vf_id;
4218         int ret;
4219
4220         if (pf == NULL) {
4221                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4222                 return -EINVAL;
4223         }
4224         hw = I40E_PF_TO_HW(pf);
4225
4226         if (filter == NULL) {
4227                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4228                 return -EINVAL;
4229         }
4230
4231         new_mac = &filter->mac_addr;
4232
4233         if (rte_is_zero_ether_addr(new_mac)) {
4234                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4235                 return -EINVAL;
4236         }
4237
4238         vf_id = filter->dst_id;
4239
4240         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4241                 PMD_DRV_LOG(ERR, "Invalid argument.");
4242                 return -EINVAL;
4243         }
4244         vf = &pf->vfs[vf_id];
4245
4246         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4247                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4248                 return -EINVAL;
4249         }
4250
4251         if (add) {
4252                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4253                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4254                                 RTE_ETHER_ADDR_LEN);
4255                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4256                                  RTE_ETHER_ADDR_LEN);
4257
4258                 mac_filter.filter_type = filter->filter_type;
4259                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4260                 if (ret != I40E_SUCCESS) {
4261                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4262                         return -1;
4263                 }
4264                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4265         } else {
4266                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4267                                 RTE_ETHER_ADDR_LEN);
4268                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4269                 if (ret != I40E_SUCCESS) {
4270                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4271                         return -1;
4272                 }
4273
4274                 /* Clear device address as it has been removed */
4275                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4276                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4277         }
4278
4279         return 0;
4280 }
4281
4282 /* MAC filter handle */
4283 static int
4284 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4285                 void *arg)
4286 {
4287         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4288         struct rte_eth_mac_filter *filter;
4289         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4290         int ret = I40E_NOT_SUPPORTED;
4291
4292         filter = (struct rte_eth_mac_filter *)(arg);
4293
4294         switch (filter_op) {
4295         case RTE_ETH_FILTER_NOP:
4296                 ret = I40E_SUCCESS;
4297                 break;
4298         case RTE_ETH_FILTER_ADD:
4299                 i40e_pf_disable_irq0(hw);
4300                 if (filter->is_vf)
4301                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4302                 i40e_pf_enable_irq0(hw);
4303                 break;
4304         case RTE_ETH_FILTER_DELETE:
4305                 i40e_pf_disable_irq0(hw);
4306                 if (filter->is_vf)
4307                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4308                 i40e_pf_enable_irq0(hw);
4309                 break;
4310         default:
4311                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4312                 ret = I40E_ERR_PARAM;
4313                 break;
4314         }
4315
4316         return ret;
4317 }
4318
4319 static int
4320 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4321 {
4322         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4323         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4324         uint32_t reg;
4325         int ret;
4326
4327         if (!lut)
4328                 return -EINVAL;
4329
4330         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4331                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4332                                           vsi->type != I40E_VSI_SRIOV,
4333                                           lut, lut_size);
4334                 if (ret) {
4335                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4336                         return ret;
4337                 }
4338         } else {
4339                 uint32_t *lut_dw = (uint32_t *)lut;
4340                 uint16_t i, lut_size_dw = lut_size / 4;
4341
4342                 if (vsi->type == I40E_VSI_SRIOV) {
4343                         for (i = 0; i <= lut_size_dw; i++) {
4344                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4345                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4346                         }
4347                 } else {
4348                         for (i = 0; i < lut_size_dw; i++)
4349                                 lut_dw[i] = I40E_READ_REG(hw,
4350                                                           I40E_PFQF_HLUT(i));
4351                 }
4352         }
4353
4354         return 0;
4355 }
4356
4357 int
4358 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4359 {
4360         struct i40e_pf *pf;
4361         struct i40e_hw *hw;
4362         int ret;
4363
4364         if (!vsi || !lut)
4365                 return -EINVAL;
4366
4367         pf = I40E_VSI_TO_PF(vsi);
4368         hw = I40E_VSI_TO_HW(vsi);
4369
4370         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4371                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4372                                           vsi->type != I40E_VSI_SRIOV,
4373                                           lut, lut_size);
4374                 if (ret) {
4375                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4376                         return ret;
4377                 }
4378         } else {
4379                 uint32_t *lut_dw = (uint32_t *)lut;
4380                 uint16_t i, lut_size_dw = lut_size / 4;
4381
4382                 if (vsi->type == I40E_VSI_SRIOV) {
4383                         for (i = 0; i < lut_size_dw; i++)
4384                                 I40E_WRITE_REG(
4385                                         hw,
4386                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4387                                         lut_dw[i]);
4388                 } else {
4389                         for (i = 0; i < lut_size_dw; i++)
4390                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4391                                                lut_dw[i]);
4392                 }
4393                 I40E_WRITE_FLUSH(hw);
4394         }
4395
4396         return 0;
4397 }
4398
4399 static int
4400 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4401                          struct rte_eth_rss_reta_entry64 *reta_conf,
4402                          uint16_t reta_size)
4403 {
4404         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4405         uint16_t i, lut_size = pf->hash_lut_size;
4406         uint16_t idx, shift;
4407         uint8_t *lut;
4408         int ret;
4409
4410         if (reta_size != lut_size ||
4411                 reta_size > ETH_RSS_RETA_SIZE_512) {
4412                 PMD_DRV_LOG(ERR,
4413                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4414                         reta_size, lut_size);
4415                 return -EINVAL;
4416         }
4417
4418         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4419         if (!lut) {
4420                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4421                 return -ENOMEM;
4422         }
4423         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4424         if (ret)
4425                 goto out;
4426         for (i = 0; i < reta_size; i++) {
4427                 idx = i / RTE_RETA_GROUP_SIZE;
4428                 shift = i % RTE_RETA_GROUP_SIZE;
4429                 if (reta_conf[idx].mask & (1ULL << shift))
4430                         lut[i] = reta_conf[idx].reta[shift];
4431         }
4432         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4433
4434         pf->adapter->rss_reta_updated = 1;
4435
4436 out:
4437         rte_free(lut);
4438
4439         return ret;
4440 }
4441
4442 static int
4443 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4444                         struct rte_eth_rss_reta_entry64 *reta_conf,
4445                         uint16_t reta_size)
4446 {
4447         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4448         uint16_t i, lut_size = pf->hash_lut_size;
4449         uint16_t idx, shift;
4450         uint8_t *lut;
4451         int ret;
4452
4453         if (reta_size != lut_size ||
4454                 reta_size > ETH_RSS_RETA_SIZE_512) {
4455                 PMD_DRV_LOG(ERR,
4456                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4457                         reta_size, lut_size);
4458                 return -EINVAL;
4459         }
4460
4461         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4462         if (!lut) {
4463                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4464                 return -ENOMEM;
4465         }
4466
4467         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4468         if (ret)
4469                 goto out;
4470         for (i = 0; i < reta_size; i++) {
4471                 idx = i / RTE_RETA_GROUP_SIZE;
4472                 shift = i % RTE_RETA_GROUP_SIZE;
4473                 if (reta_conf[idx].mask & (1ULL << shift))
4474                         reta_conf[idx].reta[shift] = lut[i];
4475         }
4476
4477 out:
4478         rte_free(lut);
4479
4480         return ret;
4481 }
4482
4483 /**
4484  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4485  * @hw:   pointer to the HW structure
4486  * @mem:  pointer to mem struct to fill out
4487  * @size: size of memory requested
4488  * @alignment: what to align the allocation to
4489  **/
4490 enum i40e_status_code
4491 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4492                         struct i40e_dma_mem *mem,
4493                         u64 size,
4494                         u32 alignment)
4495 {
4496         const struct rte_memzone *mz = NULL;
4497         char z_name[RTE_MEMZONE_NAMESIZE];
4498
4499         if (!mem)
4500                 return I40E_ERR_PARAM;
4501
4502         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4503         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4504                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4505         if (!mz)
4506                 return I40E_ERR_NO_MEMORY;
4507
4508         mem->size = size;
4509         mem->va = mz->addr;
4510         mem->pa = mz->iova;
4511         mem->zone = (const void *)mz;
4512         PMD_DRV_LOG(DEBUG,
4513                 "memzone %s allocated with physical address: %"PRIu64,
4514                 mz->name, mem->pa);
4515
4516         return I40E_SUCCESS;
4517 }
4518
4519 /**
4520  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4521  * @hw:   pointer to the HW structure
4522  * @mem:  ptr to mem struct to free
4523  **/
4524 enum i40e_status_code
4525 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4526                     struct i40e_dma_mem *mem)
4527 {
4528         if (!mem)
4529                 return I40E_ERR_PARAM;
4530
4531         PMD_DRV_LOG(DEBUG,
4532                 "memzone %s to be freed with physical address: %"PRIu64,
4533                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4534         rte_memzone_free((const struct rte_memzone *)mem->zone);
4535         mem->zone = NULL;
4536         mem->va = NULL;
4537         mem->pa = (u64)0;
4538
4539         return I40E_SUCCESS;
4540 }
4541
4542 /**
4543  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4544  * @hw:   pointer to the HW structure
4545  * @mem:  pointer to mem struct to fill out
4546  * @size: size of memory requested
4547  **/
4548 enum i40e_status_code
4549 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4550                          struct i40e_virt_mem *mem,
4551                          u32 size)
4552 {
4553         if (!mem)
4554                 return I40E_ERR_PARAM;
4555
4556         mem->size = size;
4557         mem->va = rte_zmalloc("i40e", size, 0);
4558
4559         if (mem->va)
4560                 return I40E_SUCCESS;
4561         else
4562                 return I40E_ERR_NO_MEMORY;
4563 }
4564
4565 /**
4566  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4567  * @hw:   pointer to the HW structure
4568  * @mem:  pointer to mem struct to free
4569  **/
4570 enum i40e_status_code
4571 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4572                      struct i40e_virt_mem *mem)
4573 {
4574         if (!mem)
4575                 return I40E_ERR_PARAM;
4576
4577         rte_free(mem->va);
4578         mem->va = NULL;
4579
4580         return I40E_SUCCESS;
4581 }
4582
4583 void
4584 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4585 {
4586         rte_spinlock_init(&sp->spinlock);
4587 }
4588
4589 void
4590 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4591 {
4592         rte_spinlock_lock(&sp->spinlock);
4593 }
4594
4595 void
4596 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4597 {
4598         rte_spinlock_unlock(&sp->spinlock);
4599 }
4600
4601 void
4602 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4603 {
4604         return;
4605 }
4606
4607 /**
4608  * Get the hardware capabilities, which will be parsed
4609  * and saved into struct i40e_hw.
4610  */
4611 static int
4612 i40e_get_cap(struct i40e_hw *hw)
4613 {
4614         struct i40e_aqc_list_capabilities_element_resp *buf;
4615         uint16_t len, size = 0;
4616         int ret;
4617
4618         /* Calculate a huge enough buff for saving response data temporarily */
4619         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4620                                                 I40E_MAX_CAP_ELE_NUM;
4621         buf = rte_zmalloc("i40e", len, 0);
4622         if (!buf) {
4623                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4624                 return I40E_ERR_NO_MEMORY;
4625         }
4626
4627         /* Get, parse the capabilities and save it to hw */
4628         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4629                         i40e_aqc_opc_list_func_capabilities, NULL);
4630         if (ret != I40E_SUCCESS)
4631                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4632
4633         /* Free the temporary buffer after being used */
4634         rte_free(buf);
4635
4636         return ret;
4637 }
4638
4639 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4640
4641 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4642                 const char *value,
4643                 void *opaque)
4644 {
4645         struct i40e_pf *pf;
4646         unsigned long num;
4647         char *end;
4648
4649         pf = (struct i40e_pf *)opaque;
4650         RTE_SET_USED(key);
4651
4652         errno = 0;
4653         num = strtoul(value, &end, 0);
4654         if (errno != 0 || end == value || *end != 0) {
4655                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4656                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4657                 return -(EINVAL);
4658         }
4659
4660         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4661                 pf->vf_nb_qp_max = (uint16_t)num;
4662         else
4663                 /* here return 0 to make next valid same argument work */
4664                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4665                             "power of 2 and equal or less than 16 !, Now it is "
4666                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4667
4668         return 0;
4669 }
4670
4671 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4672 {
4673         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4674         struct rte_kvargs *kvlist;
4675         int kvargs_count;
4676
4677         /* set default queue number per VF as 4 */
4678         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4679
4680         if (dev->device->devargs == NULL)
4681                 return 0;
4682
4683         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4684         if (kvlist == NULL)
4685                 return -(EINVAL);
4686
4687         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4688         if (!kvargs_count) {
4689                 rte_kvargs_free(kvlist);
4690                 return 0;
4691         }
4692
4693         if (kvargs_count > 1)
4694                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4695                             "the first invalid or last valid one is used !",
4696                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4697
4698         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4699                            i40e_pf_parse_vf_queue_number_handler, pf);
4700
4701         rte_kvargs_free(kvlist);
4702
4703         return 0;
4704 }
4705
4706 static int
4707 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4708 {
4709         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4710         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4711         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4712         uint16_t qp_count = 0, vsi_count = 0;
4713
4714         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4715                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4716                 return -EINVAL;
4717         }
4718
4719         i40e_pf_config_vf_rxq_number(dev);
4720
4721         /* Add the parameter init for LFC */
4722         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4723         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4724         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4725
4726         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4727         pf->max_num_vsi = hw->func_caps.num_vsis;
4728         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4729         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4730
4731         /* FDir queue/VSI allocation */
4732         pf->fdir_qp_offset = 0;
4733         if (hw->func_caps.fd) {
4734                 pf->flags |= I40E_FLAG_FDIR;
4735                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4736         } else {
4737                 pf->fdir_nb_qps = 0;
4738         }
4739         qp_count += pf->fdir_nb_qps;
4740         vsi_count += 1;
4741
4742         /* LAN queue/VSI allocation */
4743         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4744         if (!hw->func_caps.rss) {
4745                 pf->lan_nb_qps = 1;
4746         } else {
4747                 pf->flags |= I40E_FLAG_RSS;
4748                 if (hw->mac.type == I40E_MAC_X722)
4749                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4750                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4751         }
4752         qp_count += pf->lan_nb_qps;
4753         vsi_count += 1;
4754
4755         /* VF queue/VSI allocation */
4756         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4757         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4758                 pf->flags |= I40E_FLAG_SRIOV;
4759                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4760                 pf->vf_num = pci_dev->max_vfs;
4761                 PMD_DRV_LOG(DEBUG,
4762                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4763                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4764         } else {
4765                 pf->vf_nb_qps = 0;
4766                 pf->vf_num = 0;
4767         }
4768         qp_count += pf->vf_nb_qps * pf->vf_num;
4769         vsi_count += pf->vf_num;
4770
4771         /* VMDq queue/VSI allocation */
4772         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4773         pf->vmdq_nb_qps = 0;
4774         pf->max_nb_vmdq_vsi = 0;
4775         if (hw->func_caps.vmdq) {
4776                 if (qp_count < hw->func_caps.num_tx_qp &&
4777                         vsi_count < hw->func_caps.num_vsis) {
4778                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4779                                 qp_count) / pf->vmdq_nb_qp_max;
4780
4781                         /* Limit the maximum number of VMDq vsi to the maximum
4782                          * ethdev can support
4783                          */
4784                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4785                                 hw->func_caps.num_vsis - vsi_count);
4786                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4787                                 ETH_64_POOLS);
4788                         if (pf->max_nb_vmdq_vsi) {
4789                                 pf->flags |= I40E_FLAG_VMDQ;
4790                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4791                                 PMD_DRV_LOG(DEBUG,
4792                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4793                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4794                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4795                         } else {
4796                                 PMD_DRV_LOG(INFO,
4797                                         "No enough queues left for VMDq");
4798                         }
4799                 } else {
4800                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4801                 }
4802         }
4803         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4804         vsi_count += pf->max_nb_vmdq_vsi;
4805
4806         if (hw->func_caps.dcb)
4807                 pf->flags |= I40E_FLAG_DCB;
4808
4809         if (qp_count > hw->func_caps.num_tx_qp) {
4810                 PMD_DRV_LOG(ERR,
4811                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4812                         qp_count, hw->func_caps.num_tx_qp);
4813                 return -EINVAL;
4814         }
4815         if (vsi_count > hw->func_caps.num_vsis) {
4816                 PMD_DRV_LOG(ERR,
4817                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4818                         vsi_count, hw->func_caps.num_vsis);
4819                 return -EINVAL;
4820         }
4821
4822         return 0;
4823 }
4824
4825 static int
4826 i40e_pf_get_switch_config(struct i40e_pf *pf)
4827 {
4828         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4829         struct i40e_aqc_get_switch_config_resp *switch_config;
4830         struct i40e_aqc_switch_config_element_resp *element;
4831         uint16_t start_seid = 0, num_reported;
4832         int ret;
4833
4834         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4835                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4836         if (!switch_config) {
4837                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4838                 return -ENOMEM;
4839         }
4840
4841         /* Get the switch configurations */
4842         ret = i40e_aq_get_switch_config(hw, switch_config,
4843                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4844         if (ret != I40E_SUCCESS) {
4845                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4846                 goto fail;
4847         }
4848         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4849         if (num_reported != 1) { /* The number should be 1 */
4850                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4851                 goto fail;
4852         }
4853
4854         /* Parse the switch configuration elements */
4855         element = &(switch_config->element[0]);
4856         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4857                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4858                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4859         } else
4860                 PMD_DRV_LOG(INFO, "Unknown element type");
4861
4862 fail:
4863         rte_free(switch_config);
4864
4865         return ret;
4866 }
4867
4868 static int
4869 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4870                         uint32_t num)
4871 {
4872         struct pool_entry *entry;
4873
4874         if (pool == NULL || num == 0)
4875                 return -EINVAL;
4876
4877         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4878         if (entry == NULL) {
4879                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4880                 return -ENOMEM;
4881         }
4882
4883         /* queue heap initialize */
4884         pool->num_free = num;
4885         pool->num_alloc = 0;
4886         pool->base = base;
4887         LIST_INIT(&pool->alloc_list);
4888         LIST_INIT(&pool->free_list);
4889
4890         /* Initialize element  */
4891         entry->base = 0;
4892         entry->len = num;
4893
4894         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4895         return 0;
4896 }
4897
4898 static void
4899 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4900 {
4901         struct pool_entry *entry, *next_entry;
4902
4903         if (pool == NULL)
4904                 return;
4905
4906         for (entry = LIST_FIRST(&pool->alloc_list);
4907                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4908                         entry = next_entry) {
4909                 LIST_REMOVE(entry, next);
4910                 rte_free(entry);
4911         }
4912
4913         for (entry = LIST_FIRST(&pool->free_list);
4914                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4915                         entry = next_entry) {
4916                 LIST_REMOVE(entry, next);
4917                 rte_free(entry);
4918         }
4919
4920         pool->num_free = 0;
4921         pool->num_alloc = 0;
4922         pool->base = 0;
4923         LIST_INIT(&pool->alloc_list);
4924         LIST_INIT(&pool->free_list);
4925 }
4926
4927 static int
4928 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4929                        uint32_t base)
4930 {
4931         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4932         uint32_t pool_offset;
4933         int insert;
4934
4935         if (pool == NULL) {
4936                 PMD_DRV_LOG(ERR, "Invalid parameter");
4937                 return -EINVAL;
4938         }
4939
4940         pool_offset = base - pool->base;
4941         /* Lookup in alloc list */
4942         LIST_FOREACH(entry, &pool->alloc_list, next) {
4943                 if (entry->base == pool_offset) {
4944                         valid_entry = entry;
4945                         LIST_REMOVE(entry, next);
4946                         break;
4947                 }
4948         }
4949
4950         /* Not find, return */
4951         if (valid_entry == NULL) {
4952                 PMD_DRV_LOG(ERR, "Failed to find entry");
4953                 return -EINVAL;
4954         }
4955
4956         /**
4957          * Found it, move it to free list  and try to merge.
4958          * In order to make merge easier, always sort it by qbase.
4959          * Find adjacent prev and last entries.
4960          */
4961         prev = next = NULL;
4962         LIST_FOREACH(entry, &pool->free_list, next) {
4963                 if (entry->base > valid_entry->base) {
4964                         next = entry;
4965                         break;
4966                 }
4967                 prev = entry;
4968         }
4969
4970         insert = 0;
4971         /* Try to merge with next one*/
4972         if (next != NULL) {
4973                 /* Merge with next one */
4974                 if (valid_entry->base + valid_entry->len == next->base) {
4975                         next->base = valid_entry->base;
4976                         next->len += valid_entry->len;
4977                         rte_free(valid_entry);
4978                         valid_entry = next;
4979                         insert = 1;
4980                 }
4981         }
4982
4983         if (prev != NULL) {
4984                 /* Merge with previous one */
4985                 if (prev->base + prev->len == valid_entry->base) {
4986                         prev->len += valid_entry->len;
4987                         /* If it merge with next one, remove next node */
4988                         if (insert == 1) {
4989                                 LIST_REMOVE(valid_entry, next);
4990                                 rte_free(valid_entry);
4991                         } else {
4992                                 rte_free(valid_entry);
4993                                 insert = 1;
4994                         }
4995                 }
4996         }
4997
4998         /* Not find any entry to merge, insert */
4999         if (insert == 0) {
5000                 if (prev != NULL)
5001                         LIST_INSERT_AFTER(prev, valid_entry, next);
5002                 else if (next != NULL)
5003                         LIST_INSERT_BEFORE(next, valid_entry, next);
5004                 else /* It's empty list, insert to head */
5005                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5006         }
5007
5008         pool->num_free += valid_entry->len;
5009         pool->num_alloc -= valid_entry->len;
5010
5011         return 0;
5012 }
5013
5014 static int
5015 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5016                        uint16_t num)
5017 {
5018         struct pool_entry *entry, *valid_entry;
5019
5020         if (pool == NULL || num == 0) {
5021                 PMD_DRV_LOG(ERR, "Invalid parameter");
5022                 return -EINVAL;
5023         }
5024
5025         if (pool->num_free < num) {
5026                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5027                             num, pool->num_free);
5028                 return -ENOMEM;
5029         }
5030
5031         valid_entry = NULL;
5032         /* Lookup  in free list and find most fit one */
5033         LIST_FOREACH(entry, &pool->free_list, next) {
5034                 if (entry->len >= num) {
5035                         /* Find best one */
5036                         if (entry->len == num) {
5037                                 valid_entry = entry;
5038                                 break;
5039                         }
5040                         if (valid_entry == NULL || valid_entry->len > entry->len)
5041                                 valid_entry = entry;
5042                 }
5043         }
5044
5045         /* Not find one to satisfy the request, return */
5046         if (valid_entry == NULL) {
5047                 PMD_DRV_LOG(ERR, "No valid entry found");
5048                 return -ENOMEM;
5049         }
5050         /**
5051          * The entry have equal queue number as requested,
5052          * remove it from alloc_list.
5053          */
5054         if (valid_entry->len == num) {
5055                 LIST_REMOVE(valid_entry, next);
5056         } else {
5057                 /**
5058                  * The entry have more numbers than requested,
5059                  * create a new entry for alloc_list and minus its
5060                  * queue base and number in free_list.
5061                  */
5062                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5063                 if (entry == NULL) {
5064                         PMD_DRV_LOG(ERR,
5065                                 "Failed to allocate memory for resource pool");
5066                         return -ENOMEM;
5067                 }
5068                 entry->base = valid_entry->base;
5069                 entry->len = num;
5070                 valid_entry->base += num;
5071                 valid_entry->len -= num;
5072                 valid_entry = entry;
5073         }
5074
5075         /* Insert it into alloc list, not sorted */
5076         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5077
5078         pool->num_free -= valid_entry->len;
5079         pool->num_alloc += valid_entry->len;
5080
5081         return valid_entry->base + pool->base;
5082 }
5083
5084 /**
5085  * bitmap_is_subset - Check whether src2 is subset of src1
5086  **/
5087 static inline int
5088 bitmap_is_subset(uint8_t src1, uint8_t src2)
5089 {
5090         return !((src1 ^ src2) & src2);
5091 }
5092
5093 static enum i40e_status_code
5094 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5095 {
5096         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5097
5098         /* If DCB is not supported, only default TC is supported */
5099         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5100                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5101                 return I40E_NOT_SUPPORTED;
5102         }
5103
5104         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5105                 PMD_DRV_LOG(ERR,
5106                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5107                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5108                 return I40E_NOT_SUPPORTED;
5109         }
5110         return I40E_SUCCESS;
5111 }
5112
5113 int
5114 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5115                                 struct i40e_vsi_vlan_pvid_info *info)
5116 {
5117         struct i40e_hw *hw;
5118         struct i40e_vsi_context ctxt;
5119         uint8_t vlan_flags = 0;
5120         int ret;
5121
5122         if (vsi == NULL || info == NULL) {
5123                 PMD_DRV_LOG(ERR, "invalid parameters");
5124                 return I40E_ERR_PARAM;
5125         }
5126
5127         if (info->on) {
5128                 vsi->info.pvid = info->config.pvid;
5129                 /**
5130                  * If insert pvid is enabled, only tagged pkts are
5131                  * allowed to be sent out.
5132                  */
5133                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5134                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5135         } else {
5136                 vsi->info.pvid = 0;
5137                 if (info->config.reject.tagged == 0)
5138                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5139
5140                 if (info->config.reject.untagged == 0)
5141                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5142         }
5143         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5144                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5145         vsi->info.port_vlan_flags |= vlan_flags;
5146         vsi->info.valid_sections =
5147                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5148         memset(&ctxt, 0, sizeof(ctxt));
5149         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5150         ctxt.seid = vsi->seid;
5151
5152         hw = I40E_VSI_TO_HW(vsi);
5153         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5154         if (ret != I40E_SUCCESS)
5155                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5156
5157         return ret;
5158 }
5159
5160 static int
5161 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5162 {
5163         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5164         int i, ret;
5165         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5166
5167         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5168         if (ret != I40E_SUCCESS)
5169                 return ret;
5170
5171         if (!vsi->seid) {
5172                 PMD_DRV_LOG(ERR, "seid not valid");
5173                 return -EINVAL;
5174         }
5175
5176         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5177         tc_bw_data.tc_valid_bits = enabled_tcmap;
5178         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5179                 tc_bw_data.tc_bw_credits[i] =
5180                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5181
5182         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5183         if (ret != I40E_SUCCESS) {
5184                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5185                 return ret;
5186         }
5187
5188         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5189                                         sizeof(vsi->info.qs_handle));
5190         return I40E_SUCCESS;
5191 }
5192
5193 static enum i40e_status_code
5194 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5195                                  struct i40e_aqc_vsi_properties_data *info,
5196                                  uint8_t enabled_tcmap)
5197 {
5198         enum i40e_status_code ret;
5199         int i, total_tc = 0;
5200         uint16_t qpnum_per_tc, bsf, qp_idx;
5201
5202         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5203         if (ret != I40E_SUCCESS)
5204                 return ret;
5205
5206         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5207                 if (enabled_tcmap & (1 << i))
5208                         total_tc++;
5209         if (total_tc == 0)
5210                 total_tc = 1;
5211         vsi->enabled_tc = enabled_tcmap;
5212
5213         /* Number of queues per enabled TC */
5214         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5215         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5216         bsf = rte_bsf32(qpnum_per_tc);
5217
5218         /* Adjust the queue number to actual queues that can be applied */
5219         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5220                 vsi->nb_qps = qpnum_per_tc * total_tc;
5221
5222         /**
5223          * Configure TC and queue mapping parameters, for enabled TC,
5224          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5225          * default queue will serve it.
5226          */
5227         qp_idx = 0;
5228         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5229                 if (vsi->enabled_tc & (1 << i)) {
5230                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5231                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5232                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5233                         qp_idx += qpnum_per_tc;
5234                 } else
5235                         info->tc_mapping[i] = 0;
5236         }
5237
5238         /* Associate queue number with VSI */
5239         if (vsi->type == I40E_VSI_SRIOV) {
5240                 info->mapping_flags |=
5241                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5242                 for (i = 0; i < vsi->nb_qps; i++)
5243                         info->queue_mapping[i] =
5244                                 rte_cpu_to_le_16(vsi->base_queue + i);
5245         } else {
5246                 info->mapping_flags |=
5247                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5248                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5249         }
5250         info->valid_sections |=
5251                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5252
5253         return I40E_SUCCESS;
5254 }
5255
5256 static int
5257 i40e_veb_release(struct i40e_veb *veb)
5258 {
5259         struct i40e_vsi *vsi;
5260         struct i40e_hw *hw;
5261
5262         if (veb == NULL)
5263                 return -EINVAL;
5264
5265         if (!TAILQ_EMPTY(&veb->head)) {
5266                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5267                 return -EACCES;
5268         }
5269         /* associate_vsi field is NULL for floating VEB */
5270         if (veb->associate_vsi != NULL) {
5271                 vsi = veb->associate_vsi;
5272                 hw = I40E_VSI_TO_HW(vsi);
5273
5274                 vsi->uplink_seid = veb->uplink_seid;
5275                 vsi->veb = NULL;
5276         } else {
5277                 veb->associate_pf->main_vsi->floating_veb = NULL;
5278                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5279         }
5280
5281         i40e_aq_delete_element(hw, veb->seid, NULL);
5282         rte_free(veb);
5283         return I40E_SUCCESS;
5284 }
5285
5286 /* Setup a veb */
5287 static struct i40e_veb *
5288 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5289 {
5290         struct i40e_veb *veb;
5291         int ret;
5292         struct i40e_hw *hw;
5293
5294         if (pf == NULL) {
5295                 PMD_DRV_LOG(ERR,
5296                             "veb setup failed, associated PF shouldn't null");
5297                 return NULL;
5298         }
5299         hw = I40E_PF_TO_HW(pf);
5300
5301         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5302         if (!veb) {
5303                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5304                 goto fail;
5305         }
5306
5307         veb->associate_vsi = vsi;
5308         veb->associate_pf = pf;
5309         TAILQ_INIT(&veb->head);
5310         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5311
5312         /* create floating veb if vsi is NULL */
5313         if (vsi != NULL) {
5314                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5315                                       I40E_DEFAULT_TCMAP, false,
5316                                       &veb->seid, false, NULL);
5317         } else {
5318                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5319                                       true, &veb->seid, false, NULL);
5320         }
5321
5322         if (ret != I40E_SUCCESS) {
5323                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5324                             hw->aq.asq_last_status);
5325                 goto fail;
5326         }
5327         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5328
5329         /* get statistics index */
5330         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5331                                 &veb->stats_idx, NULL, NULL, NULL);
5332         if (ret != I40E_SUCCESS) {
5333                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5334                             hw->aq.asq_last_status);
5335                 goto fail;
5336         }
5337         /* Get VEB bandwidth, to be implemented */
5338         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5339         if (vsi)
5340                 vsi->uplink_seid = veb->seid;
5341
5342         return veb;
5343 fail:
5344         rte_free(veb);
5345         return NULL;
5346 }
5347
5348 int
5349 i40e_vsi_release(struct i40e_vsi *vsi)
5350 {
5351         struct i40e_pf *pf;
5352         struct i40e_hw *hw;
5353         struct i40e_vsi_list *vsi_list;
5354         void *temp;
5355         int ret;
5356         struct i40e_mac_filter *f;
5357         uint16_t user_param;
5358
5359         if (!vsi)
5360                 return I40E_SUCCESS;
5361
5362         if (!vsi->adapter)
5363                 return -EFAULT;
5364
5365         user_param = vsi->user_param;
5366
5367         pf = I40E_VSI_TO_PF(vsi);
5368         hw = I40E_VSI_TO_HW(vsi);
5369
5370         /* VSI has child to attach, release child first */
5371         if (vsi->veb) {
5372                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5373                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5374                                 return -1;
5375                 }
5376                 i40e_veb_release(vsi->veb);
5377         }
5378
5379         if (vsi->floating_veb) {
5380                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5381                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5382                                 return -1;
5383                 }
5384         }
5385
5386         /* Remove all macvlan filters of the VSI */
5387         i40e_vsi_remove_all_macvlan_filter(vsi);
5388         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5389                 rte_free(f);
5390
5391         if (vsi->type != I40E_VSI_MAIN &&
5392             ((vsi->type != I40E_VSI_SRIOV) ||
5393             !pf->floating_veb_list[user_param])) {
5394                 /* Remove vsi from parent's sibling list */
5395                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5396                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5397                         return I40E_ERR_PARAM;
5398                 }
5399                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5400                                 &vsi->sib_vsi_list, list);
5401
5402                 /* Remove all switch element of the VSI */
5403                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5404                 if (ret != I40E_SUCCESS)
5405                         PMD_DRV_LOG(ERR, "Failed to delete element");
5406         }
5407
5408         if ((vsi->type == I40E_VSI_SRIOV) &&
5409             pf->floating_veb_list[user_param]) {
5410                 /* Remove vsi from parent's sibling list */
5411                 if (vsi->parent_vsi == NULL ||
5412                     vsi->parent_vsi->floating_veb == NULL) {
5413                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5414                         return I40E_ERR_PARAM;
5415                 }
5416                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5417                              &vsi->sib_vsi_list, list);
5418
5419                 /* Remove all switch element of the VSI */
5420                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5421                 if (ret != I40E_SUCCESS)
5422                         PMD_DRV_LOG(ERR, "Failed to delete element");
5423         }
5424
5425         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5426
5427         if (vsi->type != I40E_VSI_SRIOV)
5428                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5429         rte_free(vsi);
5430
5431         return I40E_SUCCESS;
5432 }
5433
5434 static int
5435 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5436 {
5437         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5438         struct i40e_aqc_remove_macvlan_element_data def_filter;
5439         struct i40e_mac_filter_info filter;
5440         int ret;
5441
5442         if (vsi->type != I40E_VSI_MAIN)
5443                 return I40E_ERR_CONFIG;
5444         memset(&def_filter, 0, sizeof(def_filter));
5445         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5446                                         ETH_ADDR_LEN);
5447         def_filter.vlan_tag = 0;
5448         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5449                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5450         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5451         if (ret != I40E_SUCCESS) {
5452                 struct i40e_mac_filter *f;
5453                 struct rte_ether_addr *mac;
5454
5455                 PMD_DRV_LOG(DEBUG,
5456                             "Cannot remove the default macvlan filter");
5457                 /* It needs to add the permanent mac into mac list */
5458                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5459                 if (f == NULL) {
5460                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5461                         return I40E_ERR_NO_MEMORY;
5462                 }
5463                 mac = &f->mac_info.mac_addr;
5464                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5465                                 ETH_ADDR_LEN);
5466                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5467                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5468                 vsi->mac_num++;
5469
5470                 return ret;
5471         }
5472         rte_memcpy(&filter.mac_addr,
5473                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5474         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5475         return i40e_vsi_add_mac(vsi, &filter);
5476 }
5477
5478 /*
5479  * i40e_vsi_get_bw_config - Query VSI BW Information
5480  * @vsi: the VSI to be queried
5481  *
5482  * Returns 0 on success, negative value on failure
5483  */
5484 static enum i40e_status_code
5485 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5486 {
5487         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5488         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5489         struct i40e_hw *hw = &vsi->adapter->hw;
5490         i40e_status ret;
5491         int i;
5492         uint32_t bw_max;
5493
5494         memset(&bw_config, 0, sizeof(bw_config));
5495         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5496         if (ret != I40E_SUCCESS) {
5497                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5498                             hw->aq.asq_last_status);
5499                 return ret;
5500         }
5501
5502         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5503         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5504                                         &ets_sla_config, NULL);
5505         if (ret != I40E_SUCCESS) {
5506                 PMD_DRV_LOG(ERR,
5507                         "VSI failed to get TC bandwdith configuration %u",
5508                         hw->aq.asq_last_status);
5509                 return ret;
5510         }
5511
5512         /* store and print out BW info */
5513         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5514         vsi->bw_info.bw_max = bw_config.max_bw;
5515         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5516         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5517         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5518                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5519                      I40E_16_BIT_WIDTH);
5520         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5521                 vsi->bw_info.bw_ets_share_credits[i] =
5522                                 ets_sla_config.share_credits[i];
5523                 vsi->bw_info.bw_ets_credits[i] =
5524                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5525                 /* 4 bits per TC, 4th bit is reserved */
5526                 vsi->bw_info.bw_ets_max[i] =
5527                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5528                                   RTE_LEN2MASK(3, uint8_t));
5529                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5530                             vsi->bw_info.bw_ets_share_credits[i]);
5531                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5532                             vsi->bw_info.bw_ets_credits[i]);
5533                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5534                             vsi->bw_info.bw_ets_max[i]);
5535         }
5536
5537         return I40E_SUCCESS;
5538 }
5539
5540 /* i40e_enable_pf_lb
5541  * @pf: pointer to the pf structure
5542  *
5543  * allow loopback on pf
5544  */
5545 static inline void
5546 i40e_enable_pf_lb(struct i40e_pf *pf)
5547 {
5548         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5549         struct i40e_vsi_context ctxt;
5550         int ret;
5551
5552         /* Use the FW API if FW >= v5.0 */
5553         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5554                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5555                 return;
5556         }
5557
5558         memset(&ctxt, 0, sizeof(ctxt));
5559         ctxt.seid = pf->main_vsi_seid;
5560         ctxt.pf_num = hw->pf_id;
5561         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5562         if (ret) {
5563                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5564                             ret, hw->aq.asq_last_status);
5565                 return;
5566         }
5567         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5568         ctxt.info.valid_sections =
5569                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5570         ctxt.info.switch_id |=
5571                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5572
5573         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5574         if (ret)
5575                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5576                             hw->aq.asq_last_status);
5577 }
5578
5579 /* Setup a VSI */
5580 struct i40e_vsi *
5581 i40e_vsi_setup(struct i40e_pf *pf,
5582                enum i40e_vsi_type type,
5583                struct i40e_vsi *uplink_vsi,
5584                uint16_t user_param)
5585 {
5586         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5587         struct i40e_vsi *vsi;
5588         struct i40e_mac_filter_info filter;
5589         int ret;
5590         struct i40e_vsi_context ctxt;
5591         struct rte_ether_addr broadcast =
5592                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5593
5594         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5595             uplink_vsi == NULL) {
5596                 PMD_DRV_LOG(ERR,
5597                         "VSI setup failed, VSI link shouldn't be NULL");
5598                 return NULL;
5599         }
5600
5601         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5602                 PMD_DRV_LOG(ERR,
5603                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5604                 return NULL;
5605         }
5606
5607         /* two situations
5608          * 1.type is not MAIN and uplink vsi is not NULL
5609          * If uplink vsi didn't setup VEB, create one first under veb field
5610          * 2.type is SRIOV and the uplink is NULL
5611          * If floating VEB is NULL, create one veb under floating veb field
5612          */
5613
5614         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5615             uplink_vsi->veb == NULL) {
5616                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5617
5618                 if (uplink_vsi->veb == NULL) {
5619                         PMD_DRV_LOG(ERR, "VEB setup failed");
5620                         return NULL;
5621                 }
5622                 /* set ALLOWLOOPBACk on pf, when veb is created */
5623                 i40e_enable_pf_lb(pf);
5624         }
5625
5626         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5627             pf->main_vsi->floating_veb == NULL) {
5628                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5629
5630                 if (pf->main_vsi->floating_veb == NULL) {
5631                         PMD_DRV_LOG(ERR, "VEB setup failed");
5632                         return NULL;
5633                 }
5634         }
5635
5636         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5637         if (!vsi) {
5638                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5639                 return NULL;
5640         }
5641         TAILQ_INIT(&vsi->mac_list);
5642         vsi->type = type;
5643         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5644         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5645         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5646         vsi->user_param = user_param;
5647         vsi->vlan_anti_spoof_on = 0;
5648         vsi->vlan_filter_on = 0;
5649         /* Allocate queues */
5650         switch (vsi->type) {
5651         case I40E_VSI_MAIN  :
5652                 vsi->nb_qps = pf->lan_nb_qps;
5653                 break;
5654         case I40E_VSI_SRIOV :
5655                 vsi->nb_qps = pf->vf_nb_qps;
5656                 break;
5657         case I40E_VSI_VMDQ2:
5658                 vsi->nb_qps = pf->vmdq_nb_qps;
5659                 break;
5660         case I40E_VSI_FDIR:
5661                 vsi->nb_qps = pf->fdir_nb_qps;
5662                 break;
5663         default:
5664                 goto fail_mem;
5665         }
5666         /*
5667          * The filter status descriptor is reported in rx queue 0,
5668          * while the tx queue for fdir filter programming has no
5669          * such constraints, can be non-zero queues.
5670          * To simplify it, choose FDIR vsi use queue 0 pair.
5671          * To make sure it will use queue 0 pair, queue allocation
5672          * need be done before this function is called
5673          */
5674         if (type != I40E_VSI_FDIR) {
5675                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5676                         if (ret < 0) {
5677                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5678                                                 vsi->seid, ret);
5679                                 goto fail_mem;
5680                         }
5681                         vsi->base_queue = ret;
5682         } else
5683                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5684
5685         /* VF has MSIX interrupt in VF range, don't allocate here */
5686         if (type == I40E_VSI_MAIN) {
5687                 if (pf->support_multi_driver) {
5688                         /* If support multi-driver, need to use INT0 instead of
5689                          * allocating from msix pool. The Msix pool is init from
5690                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5691                          * to 1 without calling i40e_res_pool_alloc.
5692                          */
5693                         vsi->msix_intr = 0;
5694                         vsi->nb_msix = 1;
5695                 } else {
5696                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5697                                                   RTE_MIN(vsi->nb_qps,
5698                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5699                         if (ret < 0) {
5700                                 PMD_DRV_LOG(ERR,
5701                                             "VSI MAIN %d get heap failed %d",
5702                                             vsi->seid, ret);
5703                                 goto fail_queue_alloc;
5704                         }
5705                         vsi->msix_intr = ret;
5706                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5707                                                RTE_MAX_RXTX_INTR_VEC_ID);
5708                 }
5709         } else if (type != I40E_VSI_SRIOV) {
5710                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5711                 if (ret < 0) {
5712                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5713                         goto fail_queue_alloc;
5714                 }
5715                 vsi->msix_intr = ret;
5716                 vsi->nb_msix = 1;
5717         } else {
5718                 vsi->msix_intr = 0;
5719                 vsi->nb_msix = 0;
5720         }
5721
5722         /* Add VSI */
5723         if (type == I40E_VSI_MAIN) {
5724                 /* For main VSI, no need to add since it's default one */
5725                 vsi->uplink_seid = pf->mac_seid;
5726                 vsi->seid = pf->main_vsi_seid;
5727                 /* Bind queues with specific MSIX interrupt */
5728                 /**
5729                  * Needs 2 interrupt at least, one for misc cause which will
5730                  * enabled from OS side, Another for queues binding the
5731                  * interrupt from device side only.
5732                  */
5733
5734                 /* Get default VSI parameters from hardware */
5735                 memset(&ctxt, 0, sizeof(ctxt));
5736                 ctxt.seid = vsi->seid;
5737                 ctxt.pf_num = hw->pf_id;
5738                 ctxt.uplink_seid = vsi->uplink_seid;
5739                 ctxt.vf_num = 0;
5740                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5741                 if (ret != I40E_SUCCESS) {
5742                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5743                         goto fail_msix_alloc;
5744                 }
5745                 rte_memcpy(&vsi->info, &ctxt.info,
5746                         sizeof(struct i40e_aqc_vsi_properties_data));
5747                 vsi->vsi_id = ctxt.vsi_number;
5748                 vsi->info.valid_sections = 0;
5749
5750                 /* Configure tc, enabled TC0 only */
5751                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5752                         I40E_SUCCESS) {
5753                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5754                         goto fail_msix_alloc;
5755                 }
5756
5757                 /* TC, queue mapping */
5758                 memset(&ctxt, 0, sizeof(ctxt));
5759                 vsi->info.valid_sections |=
5760                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5761                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5762                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5763                 rte_memcpy(&ctxt.info, &vsi->info,
5764                         sizeof(struct i40e_aqc_vsi_properties_data));
5765                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5766                                                 I40E_DEFAULT_TCMAP);
5767                 if (ret != I40E_SUCCESS) {
5768                         PMD_DRV_LOG(ERR,
5769                                 "Failed to configure TC queue mapping");
5770                         goto fail_msix_alloc;
5771                 }
5772                 ctxt.seid = vsi->seid;
5773                 ctxt.pf_num = hw->pf_id;
5774                 ctxt.uplink_seid = vsi->uplink_seid;
5775                 ctxt.vf_num = 0;
5776
5777                 /* Update VSI parameters */
5778                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5779                 if (ret != I40E_SUCCESS) {
5780                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5781                         goto fail_msix_alloc;
5782                 }
5783
5784                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5785                                                 sizeof(vsi->info.tc_mapping));
5786                 rte_memcpy(&vsi->info.queue_mapping,
5787                                 &ctxt.info.queue_mapping,
5788                         sizeof(vsi->info.queue_mapping));
5789                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5790                 vsi->info.valid_sections = 0;
5791
5792                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5793                                 ETH_ADDR_LEN);
5794
5795                 /**
5796                  * Updating default filter settings are necessary to prevent
5797                  * reception of tagged packets.
5798                  * Some old firmware configurations load a default macvlan
5799                  * filter which accepts both tagged and untagged packets.
5800                  * The updating is to use a normal filter instead if needed.
5801                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5802                  * The firmware with correct configurations load the default
5803                  * macvlan filter which is expected and cannot be removed.
5804                  */
5805                 i40e_update_default_filter_setting(vsi);
5806                 i40e_config_qinq(hw, vsi);
5807         } else if (type == I40E_VSI_SRIOV) {
5808                 memset(&ctxt, 0, sizeof(ctxt));
5809                 /**
5810                  * For other VSI, the uplink_seid equals to uplink VSI's
5811                  * uplink_seid since they share same VEB
5812                  */
5813                 if (uplink_vsi == NULL)
5814                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5815                 else
5816                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5817                 ctxt.pf_num = hw->pf_id;
5818                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5819                 ctxt.uplink_seid = vsi->uplink_seid;
5820                 ctxt.connection_type = 0x1;
5821                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5822
5823                 /* Use the VEB configuration if FW >= v5.0 */
5824                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5825                         /* Configure switch ID */
5826                         ctxt.info.valid_sections |=
5827                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5828                         ctxt.info.switch_id =
5829                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5830                 }
5831
5832                 /* Configure port/vlan */
5833                 ctxt.info.valid_sections |=
5834                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5835                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5836                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5837                                                 hw->func_caps.enabled_tcmap);
5838                 if (ret != I40E_SUCCESS) {
5839                         PMD_DRV_LOG(ERR,
5840                                 "Failed to configure TC queue mapping");
5841                         goto fail_msix_alloc;
5842                 }
5843
5844                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5845                 ctxt.info.valid_sections |=
5846                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5847                 /**
5848                  * Since VSI is not created yet, only configure parameter,
5849                  * will add vsi below.
5850                  */
5851
5852                 i40e_config_qinq(hw, vsi);
5853         } else if (type == I40E_VSI_VMDQ2) {
5854                 memset(&ctxt, 0, sizeof(ctxt));
5855                 /*
5856                  * For other VSI, the uplink_seid equals to uplink VSI's
5857                  * uplink_seid since they share same VEB
5858                  */
5859                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5860                 ctxt.pf_num = hw->pf_id;
5861                 ctxt.vf_num = 0;
5862                 ctxt.uplink_seid = vsi->uplink_seid;
5863                 ctxt.connection_type = 0x1;
5864                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5865
5866                 ctxt.info.valid_sections |=
5867                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5868                 /* user_param carries flag to enable loop back */
5869                 if (user_param) {
5870                         ctxt.info.switch_id =
5871                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5872                         ctxt.info.switch_id |=
5873                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5874                 }
5875
5876                 /* Configure port/vlan */
5877                 ctxt.info.valid_sections |=
5878                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5879                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5880                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5881                                                 I40E_DEFAULT_TCMAP);
5882                 if (ret != I40E_SUCCESS) {
5883                         PMD_DRV_LOG(ERR,
5884                                 "Failed to configure TC queue mapping");
5885                         goto fail_msix_alloc;
5886                 }
5887                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5888                 ctxt.info.valid_sections |=
5889                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5890         } else if (type == I40E_VSI_FDIR) {
5891                 memset(&ctxt, 0, sizeof(ctxt));
5892                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5893                 ctxt.pf_num = hw->pf_id;
5894                 ctxt.vf_num = 0;
5895                 ctxt.uplink_seid = vsi->uplink_seid;
5896                 ctxt.connection_type = 0x1;     /* regular data port */
5897                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5898                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5899                                                 I40E_DEFAULT_TCMAP);
5900                 if (ret != I40E_SUCCESS) {
5901                         PMD_DRV_LOG(ERR,
5902                                 "Failed to configure TC queue mapping.");
5903                         goto fail_msix_alloc;
5904                 }
5905                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5906                 ctxt.info.valid_sections |=
5907                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5908         } else {
5909                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5910                 goto fail_msix_alloc;
5911         }
5912
5913         if (vsi->type != I40E_VSI_MAIN) {
5914                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5915                 if (ret != I40E_SUCCESS) {
5916                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5917                                     hw->aq.asq_last_status);
5918                         goto fail_msix_alloc;
5919                 }
5920                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5921                 vsi->info.valid_sections = 0;
5922                 vsi->seid = ctxt.seid;
5923                 vsi->vsi_id = ctxt.vsi_number;
5924                 vsi->sib_vsi_list.vsi = vsi;
5925                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5926                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5927                                           &vsi->sib_vsi_list, list);
5928                 } else {
5929                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5930                                           &vsi->sib_vsi_list, list);
5931                 }
5932         }
5933
5934         /* MAC/VLAN configuration */
5935         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5936         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5937
5938         ret = i40e_vsi_add_mac(vsi, &filter);
5939         if (ret != I40E_SUCCESS) {
5940                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5941                 goto fail_msix_alloc;
5942         }
5943
5944         /* Get VSI BW information */
5945         i40e_vsi_get_bw_config(vsi);
5946         return vsi;
5947 fail_msix_alloc:
5948         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5949 fail_queue_alloc:
5950         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5951 fail_mem:
5952         rte_free(vsi);
5953         return NULL;
5954 }
5955
5956 /* Configure vlan filter on or off */
5957 int
5958 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5959 {
5960         int i, num;
5961         struct i40e_mac_filter *f;
5962         void *temp;
5963         struct i40e_mac_filter_info *mac_filter;
5964         enum rte_mac_filter_type desired_filter;
5965         int ret = I40E_SUCCESS;
5966
5967         if (on) {
5968                 /* Filter to match MAC and VLAN */
5969                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5970         } else {
5971                 /* Filter to match only MAC */
5972                 desired_filter = RTE_MAC_PERFECT_MATCH;
5973         }
5974
5975         num = vsi->mac_num;
5976
5977         mac_filter = rte_zmalloc("mac_filter_info_data",
5978                                  num * sizeof(*mac_filter), 0);
5979         if (mac_filter == NULL) {
5980                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5981                 return I40E_ERR_NO_MEMORY;
5982         }
5983
5984         i = 0;
5985
5986         /* Remove all existing mac */
5987         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5988                 mac_filter[i] = f->mac_info;
5989                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5990                 if (ret) {
5991                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5992                                     on ? "enable" : "disable");
5993                         goto DONE;
5994                 }
5995                 i++;
5996         }
5997
5998         /* Override with new filter */
5999         for (i = 0; i < num; i++) {
6000                 mac_filter[i].filter_type = desired_filter;
6001                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6002                 if (ret) {
6003                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6004                                     on ? "enable" : "disable");
6005                         goto DONE;
6006                 }
6007         }
6008
6009 DONE:
6010         rte_free(mac_filter);
6011         return ret;
6012 }
6013
6014 /* Configure vlan stripping on or off */
6015 int
6016 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6017 {
6018         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6019         struct i40e_vsi_context ctxt;
6020         uint8_t vlan_flags;
6021         int ret = I40E_SUCCESS;
6022
6023         /* Check if it has been already on or off */
6024         if (vsi->info.valid_sections &
6025                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6026                 if (on) {
6027                         if ((vsi->info.port_vlan_flags &
6028                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6029                                 return 0; /* already on */
6030                 } else {
6031                         if ((vsi->info.port_vlan_flags &
6032                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6033                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6034                                 return 0; /* already off */
6035                 }
6036         }
6037
6038         if (on)
6039                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6040         else
6041                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6042         vsi->info.valid_sections =
6043                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6044         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6045         vsi->info.port_vlan_flags |= vlan_flags;
6046         ctxt.seid = vsi->seid;
6047         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6048         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6049         if (ret)
6050                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6051                             on ? "enable" : "disable");
6052
6053         return ret;
6054 }
6055
6056 static int
6057 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6058 {
6059         struct rte_eth_dev_data *data = dev->data;
6060         int ret;
6061         int mask = 0;
6062
6063         /* Apply vlan offload setting */
6064         mask = ETH_VLAN_STRIP_MASK |
6065                ETH_VLAN_FILTER_MASK |
6066                ETH_VLAN_EXTEND_MASK;
6067         ret = i40e_vlan_offload_set(dev, mask);
6068         if (ret) {
6069                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6070                 return ret;
6071         }
6072
6073         /* Apply pvid setting */
6074         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6075                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6076         if (ret)
6077                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6078
6079         return ret;
6080 }
6081
6082 static int
6083 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6084 {
6085         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6086
6087         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6088 }
6089
6090 static int
6091 i40e_update_flow_control(struct i40e_hw *hw)
6092 {
6093 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6094         struct i40e_link_status link_status;
6095         uint32_t rxfc = 0, txfc = 0, reg;
6096         uint8_t an_info;
6097         int ret;
6098
6099         memset(&link_status, 0, sizeof(link_status));
6100         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6101         if (ret != I40E_SUCCESS) {
6102                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6103                 goto write_reg; /* Disable flow control */
6104         }
6105
6106         an_info = hw->phy.link_info.an_info;
6107         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6108                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6109                 ret = I40E_ERR_NOT_READY;
6110                 goto write_reg; /* Disable flow control */
6111         }
6112         /**
6113          * If link auto negotiation is enabled, flow control needs to
6114          * be configured according to it
6115          */
6116         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6117         case I40E_LINK_PAUSE_RXTX:
6118                 rxfc = 1;
6119                 txfc = 1;
6120                 hw->fc.current_mode = I40E_FC_FULL;
6121                 break;
6122         case I40E_AQ_LINK_PAUSE_RX:
6123                 rxfc = 1;
6124                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6125                 break;
6126         case I40E_AQ_LINK_PAUSE_TX:
6127                 txfc = 1;
6128                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6129                 break;
6130         default:
6131                 hw->fc.current_mode = I40E_FC_NONE;
6132                 break;
6133         }
6134
6135 write_reg:
6136         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6137                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6138         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6139         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6140         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6141         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6142
6143         return ret;
6144 }
6145
6146 /* PF setup */
6147 static int
6148 i40e_pf_setup(struct i40e_pf *pf)
6149 {
6150         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6151         struct i40e_filter_control_settings settings;
6152         struct i40e_vsi *vsi;
6153         int ret;
6154
6155         /* Clear all stats counters */
6156         pf->offset_loaded = FALSE;
6157         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6158         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6159         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6160         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6161
6162         ret = i40e_pf_get_switch_config(pf);
6163         if (ret != I40E_SUCCESS) {
6164                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6165                 return ret;
6166         }
6167
6168         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6169         if (ret)
6170                 PMD_INIT_LOG(WARNING,
6171                         "failed to allocate switch domain for device %d", ret);
6172
6173         if (pf->flags & I40E_FLAG_FDIR) {
6174                 /* make queue allocated first, let FDIR use queue pair 0*/
6175                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6176                 if (ret != I40E_FDIR_QUEUE_ID) {
6177                         PMD_DRV_LOG(ERR,
6178                                 "queue allocation fails for FDIR: ret =%d",
6179                                 ret);
6180                         pf->flags &= ~I40E_FLAG_FDIR;
6181                 }
6182         }
6183         /*  main VSI setup */
6184         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6185         if (!vsi) {
6186                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6187                 return I40E_ERR_NOT_READY;
6188         }
6189         pf->main_vsi = vsi;
6190
6191         /* Configure filter control */
6192         memset(&settings, 0, sizeof(settings));
6193         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6194                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6195         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6196                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6197         else {
6198                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6199                         hw->func_caps.rss_table_size);
6200                 return I40E_ERR_PARAM;
6201         }
6202         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6203                 hw->func_caps.rss_table_size);
6204         pf->hash_lut_size = hw->func_caps.rss_table_size;
6205
6206         /* Enable ethtype and macvlan filters */
6207         settings.enable_ethtype = TRUE;
6208         settings.enable_macvlan = TRUE;
6209         ret = i40e_set_filter_control(hw, &settings);
6210         if (ret)
6211                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6212                                                                 ret);
6213
6214         /* Update flow control according to the auto negotiation */
6215         i40e_update_flow_control(hw);
6216
6217         return I40E_SUCCESS;
6218 }
6219
6220 int
6221 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6222 {
6223         uint32_t reg;
6224         uint16_t j;
6225
6226         /**
6227          * Set or clear TX Queue Disable flags,
6228          * which is required by hardware.
6229          */
6230         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6231         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6232
6233         /* Wait until the request is finished */
6234         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6235                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6236                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6237                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6238                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6239                                                         & 0x1))) {
6240                         break;
6241                 }
6242         }
6243         if (on) {
6244                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6245                         return I40E_SUCCESS; /* already on, skip next steps */
6246
6247                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6248                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6249         } else {
6250                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6251                         return I40E_SUCCESS; /* already off, skip next steps */
6252                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6253         }
6254         /* Write the register */
6255         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6256         /* Check the result */
6257         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6258                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6259                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6260                 if (on) {
6261                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6262                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6263                                 break;
6264                 } else {
6265                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6266                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6267                                 break;
6268                 }
6269         }
6270         /* Check if it is timeout */
6271         if (j >= I40E_CHK_Q_ENA_COUNT) {
6272                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6273                             (on ? "enable" : "disable"), q_idx);
6274                 return I40E_ERR_TIMEOUT;
6275         }
6276
6277         return I40E_SUCCESS;
6278 }
6279
6280 /* Swith on or off the tx queues */
6281 static int
6282 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6283 {
6284         struct rte_eth_dev_data *dev_data = pf->dev_data;
6285         struct i40e_tx_queue *txq;
6286         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6287         uint16_t i;
6288         int ret;
6289
6290         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6291                 txq = dev_data->tx_queues[i];
6292                 /* Don't operate the queue if not configured or
6293                  * if starting only per queue */
6294                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6295                         continue;
6296                 if (on)
6297                         ret = i40e_dev_tx_queue_start(dev, i);
6298                 else
6299                         ret = i40e_dev_tx_queue_stop(dev, i);
6300                 if ( ret != I40E_SUCCESS)
6301                         return ret;
6302         }
6303
6304         return I40E_SUCCESS;
6305 }
6306
6307 int
6308 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6309 {
6310         uint32_t reg;
6311         uint16_t j;
6312
6313         /* Wait until the request is finished */
6314         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6315                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6316                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6317                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6318                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6319                         break;
6320         }
6321
6322         if (on) {
6323                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6324                         return I40E_SUCCESS; /* Already on, skip next steps */
6325                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6326         } else {
6327                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6328                         return I40E_SUCCESS; /* Already off, skip next steps */
6329                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6330         }
6331
6332         /* Write the register */
6333         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6334         /* Check the result */
6335         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6336                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6337                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6338                 if (on) {
6339                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6340                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6341                                 break;
6342                 } else {
6343                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6344                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6345                                 break;
6346                 }
6347         }
6348
6349         /* Check if it is timeout */
6350         if (j >= I40E_CHK_Q_ENA_COUNT) {
6351                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6352                             (on ? "enable" : "disable"), q_idx);
6353                 return I40E_ERR_TIMEOUT;
6354         }
6355
6356         return I40E_SUCCESS;
6357 }
6358 /* Switch on or off the rx queues */
6359 static int
6360 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6361 {
6362         struct rte_eth_dev_data *dev_data = pf->dev_data;
6363         struct i40e_rx_queue *rxq;
6364         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6365         uint16_t i;
6366         int ret;
6367
6368         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6369                 rxq = dev_data->rx_queues[i];
6370                 /* Don't operate the queue if not configured or
6371                  * if starting only per queue */
6372                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6373                         continue;
6374                 if (on)
6375                         ret = i40e_dev_rx_queue_start(dev, i);
6376                 else
6377                         ret = i40e_dev_rx_queue_stop(dev, i);
6378                 if (ret != I40E_SUCCESS)
6379                         return ret;
6380         }
6381
6382         return I40E_SUCCESS;
6383 }
6384
6385 /* Switch on or off all the rx/tx queues */
6386 int
6387 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6388 {
6389         int ret;
6390
6391         if (on) {
6392                 /* enable rx queues before enabling tx queues */
6393                 ret = i40e_dev_switch_rx_queues(pf, on);
6394                 if (ret) {
6395                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6396                         return ret;
6397                 }
6398                 ret = i40e_dev_switch_tx_queues(pf, on);
6399         } else {
6400                 /* Stop tx queues before stopping rx queues */
6401                 ret = i40e_dev_switch_tx_queues(pf, on);
6402                 if (ret) {
6403                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6404                         return ret;
6405                 }
6406                 ret = i40e_dev_switch_rx_queues(pf, on);
6407         }
6408
6409         return ret;
6410 }
6411
6412 /* Initialize VSI for TX */
6413 static int
6414 i40e_dev_tx_init(struct i40e_pf *pf)
6415 {
6416         struct rte_eth_dev_data *data = pf->dev_data;
6417         uint16_t i;
6418         uint32_t ret = I40E_SUCCESS;
6419         struct i40e_tx_queue *txq;
6420
6421         for (i = 0; i < data->nb_tx_queues; i++) {
6422                 txq = data->tx_queues[i];
6423                 if (!txq || !txq->q_set)
6424                         continue;
6425                 ret = i40e_tx_queue_init(txq);
6426                 if (ret != I40E_SUCCESS)
6427                         break;
6428         }
6429         if (ret == I40E_SUCCESS)
6430                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6431                                      ->eth_dev);
6432
6433         return ret;
6434 }
6435
6436 /* Initialize VSI for RX */
6437 static int
6438 i40e_dev_rx_init(struct i40e_pf *pf)
6439 {
6440         struct rte_eth_dev_data *data = pf->dev_data;
6441         int ret = I40E_SUCCESS;
6442         uint16_t i;
6443         struct i40e_rx_queue *rxq;
6444
6445         i40e_pf_config_mq_rx(pf);
6446         for (i = 0; i < data->nb_rx_queues; i++) {
6447                 rxq = data->rx_queues[i];
6448                 if (!rxq || !rxq->q_set)
6449                         continue;
6450
6451                 ret = i40e_rx_queue_init(rxq);
6452                 if (ret != I40E_SUCCESS) {
6453                         PMD_DRV_LOG(ERR,
6454                                 "Failed to do RX queue initialization");
6455                         break;
6456                 }
6457         }
6458         if (ret == I40E_SUCCESS)
6459                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6460                                      ->eth_dev);
6461
6462         return ret;
6463 }
6464
6465 static int
6466 i40e_dev_rxtx_init(struct i40e_pf *pf)
6467 {
6468         int err;
6469
6470         err = i40e_dev_tx_init(pf);
6471         if (err) {
6472                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6473                 return err;
6474         }
6475         err = i40e_dev_rx_init(pf);
6476         if (err) {
6477                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6478                 return err;
6479         }
6480
6481         return err;
6482 }
6483
6484 static int
6485 i40e_vmdq_setup(struct rte_eth_dev *dev)
6486 {
6487         struct rte_eth_conf *conf = &dev->data->dev_conf;
6488         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6489         int i, err, conf_vsis, j, loop;
6490         struct i40e_vsi *vsi;
6491         struct i40e_vmdq_info *vmdq_info;
6492         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6493         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6494
6495         /*
6496          * Disable interrupt to avoid message from VF. Furthermore, it will
6497          * avoid race condition in VSI creation/destroy.
6498          */
6499         i40e_pf_disable_irq0(hw);
6500
6501         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6502                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6503                 return -ENOTSUP;
6504         }
6505
6506         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6507         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6508                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6509                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6510                         pf->max_nb_vmdq_vsi);
6511                 return -ENOTSUP;
6512         }
6513
6514         if (pf->vmdq != NULL) {
6515                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6516                 return 0;
6517         }
6518
6519         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6520                                 sizeof(*vmdq_info) * conf_vsis, 0);
6521
6522         if (pf->vmdq == NULL) {
6523                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6524                 return -ENOMEM;
6525         }
6526
6527         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6528
6529         /* Create VMDQ VSI */
6530         for (i = 0; i < conf_vsis; i++) {
6531                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6532                                 vmdq_conf->enable_loop_back);
6533                 if (vsi == NULL) {
6534                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6535                         err = -1;
6536                         goto err_vsi_setup;
6537                 }
6538                 vmdq_info = &pf->vmdq[i];
6539                 vmdq_info->pf = pf;
6540                 vmdq_info->vsi = vsi;
6541         }
6542         pf->nb_cfg_vmdq_vsi = conf_vsis;
6543
6544         /* Configure Vlan */
6545         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6546         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6547                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6548                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6549                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6550                                         vmdq_conf->pool_map[i].vlan_id, j);
6551
6552                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6553                                                 vmdq_conf->pool_map[i].vlan_id);
6554                                 if (err) {
6555                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6556                                         err = -1;
6557                                         goto err_vsi_setup;
6558                                 }
6559                         }
6560                 }
6561         }
6562
6563         i40e_pf_enable_irq0(hw);
6564
6565         return 0;
6566
6567 err_vsi_setup:
6568         for (i = 0; i < conf_vsis; i++)
6569                 if (pf->vmdq[i].vsi == NULL)
6570                         break;
6571                 else
6572                         i40e_vsi_release(pf->vmdq[i].vsi);
6573
6574         rte_free(pf->vmdq);
6575         pf->vmdq = NULL;
6576         i40e_pf_enable_irq0(hw);
6577         return err;
6578 }
6579
6580 static void
6581 i40e_stat_update_32(struct i40e_hw *hw,
6582                    uint32_t reg,
6583                    bool offset_loaded,
6584                    uint64_t *offset,
6585                    uint64_t *stat)
6586 {
6587         uint64_t new_data;
6588
6589         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6590         if (!offset_loaded)
6591                 *offset = new_data;
6592
6593         if (new_data >= *offset)
6594                 *stat = (uint64_t)(new_data - *offset);
6595         else
6596                 *stat = (uint64_t)((new_data +
6597                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6598 }
6599
6600 static void
6601 i40e_stat_update_48(struct i40e_hw *hw,
6602                    uint32_t hireg,
6603                    uint32_t loreg,
6604                    bool offset_loaded,
6605                    uint64_t *offset,
6606                    uint64_t *stat)
6607 {
6608         uint64_t new_data;
6609
6610         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6611         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6612                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6613
6614         if (!offset_loaded)
6615                 *offset = new_data;
6616
6617         if (new_data >= *offset)
6618                 *stat = new_data - *offset;
6619         else
6620                 *stat = (uint64_t)((new_data +
6621                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6622
6623         *stat &= I40E_48_BIT_MASK;
6624 }
6625
6626 /* Disable IRQ0 */
6627 void
6628 i40e_pf_disable_irq0(struct i40e_hw *hw)
6629 {
6630         /* Disable all interrupt types */
6631         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6632                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6633         I40E_WRITE_FLUSH(hw);
6634 }
6635
6636 /* Enable IRQ0 */
6637 void
6638 i40e_pf_enable_irq0(struct i40e_hw *hw)
6639 {
6640         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6641                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6642                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6643                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6644         I40E_WRITE_FLUSH(hw);
6645 }
6646
6647 static void
6648 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6649 {
6650         /* read pending request and disable first */
6651         i40e_pf_disable_irq0(hw);
6652         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6653         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6654                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6655
6656         if (no_queue)
6657                 /* Link no queues with irq0 */
6658                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6659                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6660 }
6661
6662 static void
6663 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6664 {
6665         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6666         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6667         int i;
6668         uint16_t abs_vf_id;
6669         uint32_t index, offset, val;
6670
6671         if (!pf->vfs)
6672                 return;
6673         /**
6674          * Try to find which VF trigger a reset, use absolute VF id to access
6675          * since the reg is global register.
6676          */
6677         for (i = 0; i < pf->vf_num; i++) {
6678                 abs_vf_id = hw->func_caps.vf_base_id + i;
6679                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6680                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6681                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6682                 /* VFR event occurred */
6683                 if (val & (0x1 << offset)) {
6684                         int ret;
6685
6686                         /* Clear the event first */
6687                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6688                                                         (0x1 << offset));
6689                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6690                         /**
6691                          * Only notify a VF reset event occurred,
6692                          * don't trigger another SW reset
6693                          */
6694                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6695                         if (ret != I40E_SUCCESS)
6696                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6697                 }
6698         }
6699 }
6700
6701 static void
6702 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6703 {
6704         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6705         int i;
6706
6707         for (i = 0; i < pf->vf_num; i++)
6708                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6709 }
6710
6711 static void
6712 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6713 {
6714         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6715         struct i40e_arq_event_info info;
6716         uint16_t pending, opcode;
6717         int ret;
6718
6719         info.buf_len = I40E_AQ_BUF_SZ;
6720         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6721         if (!info.msg_buf) {
6722                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6723                 return;
6724         }
6725
6726         pending = 1;
6727         while (pending) {
6728                 ret = i40e_clean_arq_element(hw, &info, &pending);
6729
6730                 if (ret != I40E_SUCCESS) {
6731                         PMD_DRV_LOG(INFO,
6732                                 "Failed to read msg from AdminQ, aq_err: %u",
6733                                 hw->aq.asq_last_status);
6734                         break;
6735                 }
6736                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6737
6738                 switch (opcode) {
6739                 case i40e_aqc_opc_send_msg_to_pf:
6740                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6741                         i40e_pf_host_handle_vf_msg(dev,
6742                                         rte_le_to_cpu_16(info.desc.retval),
6743                                         rte_le_to_cpu_32(info.desc.cookie_high),
6744                                         rte_le_to_cpu_32(info.desc.cookie_low),
6745                                         info.msg_buf,
6746                                         info.msg_len);
6747                         break;
6748                 case i40e_aqc_opc_get_link_status:
6749                         ret = i40e_dev_link_update(dev, 0);
6750                         if (!ret)
6751                                 _rte_eth_dev_callback_process(dev,
6752                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6753                         break;
6754                 default:
6755                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6756                                     opcode);
6757                         break;
6758                 }
6759         }
6760         rte_free(info.msg_buf);
6761 }
6762
6763 /**
6764  * Interrupt handler triggered by NIC  for handling
6765  * specific interrupt.
6766  *
6767  * @param handle
6768  *  Pointer to interrupt handle.
6769  * @param param
6770  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6771  *
6772  * @return
6773  *  void
6774  */
6775 static void
6776 i40e_dev_interrupt_handler(void *param)
6777 {
6778         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6779         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6780         uint32_t icr0;
6781
6782         /* Disable interrupt */
6783         i40e_pf_disable_irq0(hw);
6784
6785         /* read out interrupt causes */
6786         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6787
6788         /* No interrupt event indicated */
6789         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6790                 PMD_DRV_LOG(INFO, "No interrupt event");
6791                 goto done;
6792         }
6793         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6794                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6795         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6796                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6797         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6798                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6799         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6800                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6801         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6802                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6803         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6804                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6805         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6806                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6807
6808         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6809                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6810                 i40e_dev_handle_vfr_event(dev);
6811         }
6812         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6813                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6814                 i40e_dev_handle_aq_msg(dev);
6815         }
6816
6817 done:
6818         /* Enable interrupt */
6819         i40e_pf_enable_irq0(hw);
6820 }
6821
6822 static void
6823 i40e_dev_alarm_handler(void *param)
6824 {
6825         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6826         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6827         uint32_t icr0;
6828
6829         /* Disable interrupt */
6830         i40e_pf_disable_irq0(hw);
6831
6832         /* read out interrupt causes */
6833         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6834
6835         /* No interrupt event indicated */
6836         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6837                 goto done;
6838         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6839                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6840         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6841                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6842         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6843                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6844         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6845                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6846         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6847                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6848         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6849                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6850         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6851                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6852
6853         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6854                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6855                 i40e_dev_handle_vfr_event(dev);
6856         }
6857         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6858                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6859                 i40e_dev_handle_aq_msg(dev);
6860         }
6861
6862 done:
6863         /* Enable interrupt */
6864         i40e_pf_enable_irq0(hw);
6865         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6866                           i40e_dev_alarm_handler, dev);
6867 }
6868
6869 int
6870 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6871                          struct i40e_macvlan_filter *filter,
6872                          int total)
6873 {
6874         int ele_num, ele_buff_size;
6875         int num, actual_num, i;
6876         uint16_t flags;
6877         int ret = I40E_SUCCESS;
6878         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6879         struct i40e_aqc_add_macvlan_element_data *req_list;
6880
6881         if (filter == NULL  || total == 0)
6882                 return I40E_ERR_PARAM;
6883         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6884         ele_buff_size = hw->aq.asq_buf_size;
6885
6886         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6887         if (req_list == NULL) {
6888                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6889                 return I40E_ERR_NO_MEMORY;
6890         }
6891
6892         num = 0;
6893         do {
6894                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6895                 memset(req_list, 0, ele_buff_size);
6896
6897                 for (i = 0; i < actual_num; i++) {
6898                         rte_memcpy(req_list[i].mac_addr,
6899                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6900                         req_list[i].vlan_tag =
6901                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6902
6903                         switch (filter[num + i].filter_type) {
6904                         case RTE_MAC_PERFECT_MATCH:
6905                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6906                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6907                                 break;
6908                         case RTE_MACVLAN_PERFECT_MATCH:
6909                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6910                                 break;
6911                         case RTE_MAC_HASH_MATCH:
6912                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6913                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6914                                 break;
6915                         case RTE_MACVLAN_HASH_MATCH:
6916                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6917                                 break;
6918                         default:
6919                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6920                                 ret = I40E_ERR_PARAM;
6921                                 goto DONE;
6922                         }
6923
6924                         req_list[i].queue_number = 0;
6925
6926                         req_list[i].flags = rte_cpu_to_le_16(flags);
6927                 }
6928
6929                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6930                                                 actual_num, NULL);
6931                 if (ret != I40E_SUCCESS) {
6932                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6933                         goto DONE;
6934                 }
6935                 num += actual_num;
6936         } while (num < total);
6937
6938 DONE:
6939         rte_free(req_list);
6940         return ret;
6941 }
6942
6943 int
6944 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6945                             struct i40e_macvlan_filter *filter,
6946                             int total)
6947 {
6948         int ele_num, ele_buff_size;
6949         int num, actual_num, i;
6950         uint16_t flags;
6951         int ret = I40E_SUCCESS;
6952         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6953         struct i40e_aqc_remove_macvlan_element_data *req_list;
6954
6955         if (filter == NULL  || total == 0)
6956                 return I40E_ERR_PARAM;
6957
6958         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6959         ele_buff_size = hw->aq.asq_buf_size;
6960
6961         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6962         if (req_list == NULL) {
6963                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6964                 return I40E_ERR_NO_MEMORY;
6965         }
6966
6967         num = 0;
6968         do {
6969                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6970                 memset(req_list, 0, ele_buff_size);
6971
6972                 for (i = 0; i < actual_num; i++) {
6973                         rte_memcpy(req_list[i].mac_addr,
6974                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6975                         req_list[i].vlan_tag =
6976                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6977
6978                         switch (filter[num + i].filter_type) {
6979                         case RTE_MAC_PERFECT_MATCH:
6980                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6981                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6982                                 break;
6983                         case RTE_MACVLAN_PERFECT_MATCH:
6984                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6985                                 break;
6986                         case RTE_MAC_HASH_MATCH:
6987                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6988                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6989                                 break;
6990                         case RTE_MACVLAN_HASH_MATCH:
6991                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6992                                 break;
6993                         default:
6994                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6995                                 ret = I40E_ERR_PARAM;
6996                                 goto DONE;
6997                         }
6998                         req_list[i].flags = rte_cpu_to_le_16(flags);
6999                 }
7000
7001                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7002                                                 actual_num, NULL);
7003                 if (ret != I40E_SUCCESS) {
7004                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7005                         goto DONE;
7006                 }
7007                 num += actual_num;
7008         } while (num < total);
7009
7010 DONE:
7011         rte_free(req_list);
7012         return ret;
7013 }
7014
7015 /* Find out specific MAC filter */
7016 static struct i40e_mac_filter *
7017 i40e_find_mac_filter(struct i40e_vsi *vsi,
7018                          struct rte_ether_addr *macaddr)
7019 {
7020         struct i40e_mac_filter *f;
7021
7022         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7023                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7024                         return f;
7025         }
7026
7027         return NULL;
7028 }
7029
7030 static bool
7031 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7032                          uint16_t vlan_id)
7033 {
7034         uint32_t vid_idx, vid_bit;
7035
7036         if (vlan_id > ETH_VLAN_ID_MAX)
7037                 return 0;
7038
7039         vid_idx = I40E_VFTA_IDX(vlan_id);
7040         vid_bit = I40E_VFTA_BIT(vlan_id);
7041
7042         if (vsi->vfta[vid_idx] & vid_bit)
7043                 return 1;
7044         else
7045                 return 0;
7046 }
7047
7048 static void
7049 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7050                        uint16_t vlan_id, bool on)
7051 {
7052         uint32_t vid_idx, vid_bit;
7053
7054         vid_idx = I40E_VFTA_IDX(vlan_id);
7055         vid_bit = I40E_VFTA_BIT(vlan_id);
7056
7057         if (on)
7058                 vsi->vfta[vid_idx] |= vid_bit;
7059         else
7060                 vsi->vfta[vid_idx] &= ~vid_bit;
7061 }
7062
7063 void
7064 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7065                      uint16_t vlan_id, bool on)
7066 {
7067         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7068         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7069         int ret;
7070
7071         if (vlan_id > ETH_VLAN_ID_MAX)
7072                 return;
7073
7074         i40e_store_vlan_filter(vsi, vlan_id, on);
7075
7076         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7077                 return;
7078
7079         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7080
7081         if (on) {
7082                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7083                                        &vlan_data, 1, NULL);
7084                 if (ret != I40E_SUCCESS)
7085                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7086         } else {
7087                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7088                                           &vlan_data, 1, NULL);
7089                 if (ret != I40E_SUCCESS)
7090                         PMD_DRV_LOG(ERR,
7091                                     "Failed to remove vlan filter");
7092         }
7093 }
7094
7095 /**
7096  * Find all vlan options for specific mac addr,
7097  * return with actual vlan found.
7098  */
7099 int
7100 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7101                            struct i40e_macvlan_filter *mv_f,
7102                            int num, struct rte_ether_addr *addr)
7103 {
7104         int i;
7105         uint32_t j, k;
7106
7107         /**
7108          * Not to use i40e_find_vlan_filter to decrease the loop time,
7109          * although the code looks complex.
7110           */
7111         if (num < vsi->vlan_num)
7112                 return I40E_ERR_PARAM;
7113
7114         i = 0;
7115         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7116                 if (vsi->vfta[j]) {
7117                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7118                                 if (vsi->vfta[j] & (1 << k)) {
7119                                         if (i > num - 1) {
7120                                                 PMD_DRV_LOG(ERR,
7121                                                         "vlan number doesn't match");
7122                                                 return I40E_ERR_PARAM;
7123                                         }
7124                                         rte_memcpy(&mv_f[i].macaddr,
7125                                                         addr, ETH_ADDR_LEN);
7126                                         mv_f[i].vlan_id =
7127                                                 j * I40E_UINT32_BIT_SIZE + k;
7128                                         i++;
7129                                 }
7130                         }
7131                 }
7132         }
7133         return I40E_SUCCESS;
7134 }
7135
7136 static inline int
7137 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7138                            struct i40e_macvlan_filter *mv_f,
7139                            int num,
7140                            uint16_t vlan)
7141 {
7142         int i = 0;
7143         struct i40e_mac_filter *f;
7144
7145         if (num < vsi->mac_num)
7146                 return I40E_ERR_PARAM;
7147
7148         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7149                 if (i > num - 1) {
7150                         PMD_DRV_LOG(ERR, "buffer number not match");
7151                         return I40E_ERR_PARAM;
7152                 }
7153                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7154                                 ETH_ADDR_LEN);
7155                 mv_f[i].vlan_id = vlan;
7156                 mv_f[i].filter_type = f->mac_info.filter_type;
7157                 i++;
7158         }
7159
7160         return I40E_SUCCESS;
7161 }
7162
7163 static int
7164 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7165 {
7166         int i, j, num;
7167         struct i40e_mac_filter *f;
7168         struct i40e_macvlan_filter *mv_f;
7169         int ret = I40E_SUCCESS;
7170
7171         if (vsi == NULL || vsi->mac_num == 0)
7172                 return I40E_ERR_PARAM;
7173
7174         /* Case that no vlan is set */
7175         if (vsi->vlan_num == 0)
7176                 num = vsi->mac_num;
7177         else
7178                 num = vsi->mac_num * vsi->vlan_num;
7179
7180         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7181         if (mv_f == NULL) {
7182                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7183                 return I40E_ERR_NO_MEMORY;
7184         }
7185
7186         i = 0;
7187         if (vsi->vlan_num == 0) {
7188                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7189                         rte_memcpy(&mv_f[i].macaddr,
7190                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7191                         mv_f[i].filter_type = f->mac_info.filter_type;
7192                         mv_f[i].vlan_id = 0;
7193                         i++;
7194                 }
7195         } else {
7196                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7197                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7198                                         vsi->vlan_num, &f->mac_info.mac_addr);
7199                         if (ret != I40E_SUCCESS)
7200                                 goto DONE;
7201                         for (j = i; j < i + vsi->vlan_num; j++)
7202                                 mv_f[j].filter_type = f->mac_info.filter_type;
7203                         i += vsi->vlan_num;
7204                 }
7205         }
7206
7207         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7208 DONE:
7209         rte_free(mv_f);
7210
7211         return ret;
7212 }
7213
7214 int
7215 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7216 {
7217         struct i40e_macvlan_filter *mv_f;
7218         int mac_num;
7219         int ret = I40E_SUCCESS;
7220
7221         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7222                 return I40E_ERR_PARAM;
7223
7224         /* If it's already set, just return */
7225         if (i40e_find_vlan_filter(vsi,vlan))
7226                 return I40E_SUCCESS;
7227
7228         mac_num = vsi->mac_num;
7229
7230         if (mac_num == 0) {
7231                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7232                 return I40E_ERR_PARAM;
7233         }
7234
7235         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7236
7237         if (mv_f == NULL) {
7238                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7239                 return I40E_ERR_NO_MEMORY;
7240         }
7241
7242         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7243
7244         if (ret != I40E_SUCCESS)
7245                 goto DONE;
7246
7247         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7248
7249         if (ret != I40E_SUCCESS)
7250                 goto DONE;
7251
7252         i40e_set_vlan_filter(vsi, vlan, 1);
7253
7254         vsi->vlan_num++;
7255         ret = I40E_SUCCESS;
7256 DONE:
7257         rte_free(mv_f);
7258         return ret;
7259 }
7260
7261 int
7262 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7263 {
7264         struct i40e_macvlan_filter *mv_f;
7265         int mac_num;
7266         int ret = I40E_SUCCESS;
7267
7268         /**
7269          * Vlan 0 is the generic filter for untagged packets
7270          * and can't be removed.
7271          */
7272         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7273                 return I40E_ERR_PARAM;
7274
7275         /* If can't find it, just return */
7276         if (!i40e_find_vlan_filter(vsi, vlan))
7277                 return I40E_ERR_PARAM;
7278
7279         mac_num = vsi->mac_num;
7280
7281         if (mac_num == 0) {
7282                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7283                 return I40E_ERR_PARAM;
7284         }
7285
7286         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7287
7288         if (mv_f == NULL) {
7289                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7290                 return I40E_ERR_NO_MEMORY;
7291         }
7292
7293         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7294
7295         if (ret != I40E_SUCCESS)
7296                 goto DONE;
7297
7298         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7299
7300         if (ret != I40E_SUCCESS)
7301                 goto DONE;
7302
7303         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7304         if (vsi->vlan_num == 1) {
7305                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7306                 if (ret != I40E_SUCCESS)
7307                         goto DONE;
7308
7309                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7310                 if (ret != I40E_SUCCESS)
7311                         goto DONE;
7312         }
7313
7314         i40e_set_vlan_filter(vsi, vlan, 0);
7315
7316         vsi->vlan_num--;
7317         ret = I40E_SUCCESS;
7318 DONE:
7319         rte_free(mv_f);
7320         return ret;
7321 }
7322
7323 int
7324 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7325 {
7326         struct i40e_mac_filter *f;
7327         struct i40e_macvlan_filter *mv_f;
7328         int i, vlan_num = 0;
7329         int ret = I40E_SUCCESS;
7330
7331         /* If it's add and we've config it, return */
7332         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7333         if (f != NULL)
7334                 return I40E_SUCCESS;
7335         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7336                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7337
7338                 /**
7339                  * If vlan_num is 0, that's the first time to add mac,
7340                  * set mask for vlan_id 0.
7341                  */
7342                 if (vsi->vlan_num == 0) {
7343                         i40e_set_vlan_filter(vsi, 0, 1);
7344                         vsi->vlan_num = 1;
7345                 }
7346                 vlan_num = vsi->vlan_num;
7347         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7348                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7349                 vlan_num = 1;
7350
7351         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7352         if (mv_f == NULL) {
7353                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7354                 return I40E_ERR_NO_MEMORY;
7355         }
7356
7357         for (i = 0; i < vlan_num; i++) {
7358                 mv_f[i].filter_type = mac_filter->filter_type;
7359                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7360                                 ETH_ADDR_LEN);
7361         }
7362
7363         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7364                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7365                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7366                                         &mac_filter->mac_addr);
7367                 if (ret != I40E_SUCCESS)
7368                         goto DONE;
7369         }
7370
7371         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7372         if (ret != I40E_SUCCESS)
7373                 goto DONE;
7374
7375         /* Add the mac addr into mac list */
7376         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7377         if (f == NULL) {
7378                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7379                 ret = I40E_ERR_NO_MEMORY;
7380                 goto DONE;
7381         }
7382         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7383                         ETH_ADDR_LEN);
7384         f->mac_info.filter_type = mac_filter->filter_type;
7385         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7386         vsi->mac_num++;
7387
7388         ret = I40E_SUCCESS;
7389 DONE:
7390         rte_free(mv_f);
7391
7392         return ret;
7393 }
7394
7395 int
7396 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7397 {
7398         struct i40e_mac_filter *f;
7399         struct i40e_macvlan_filter *mv_f;
7400         int i, vlan_num;
7401         enum rte_mac_filter_type filter_type;
7402         int ret = I40E_SUCCESS;
7403
7404         /* Can't find it, return an error */
7405         f = i40e_find_mac_filter(vsi, addr);
7406         if (f == NULL)
7407                 return I40E_ERR_PARAM;
7408
7409         vlan_num = vsi->vlan_num;
7410         filter_type = f->mac_info.filter_type;
7411         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7412                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7413                 if (vlan_num == 0) {
7414                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7415                         return I40E_ERR_PARAM;
7416                 }
7417         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7418                         filter_type == RTE_MAC_HASH_MATCH)
7419                 vlan_num = 1;
7420
7421         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7422         if (mv_f == NULL) {
7423                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7424                 return I40E_ERR_NO_MEMORY;
7425         }
7426
7427         for (i = 0; i < vlan_num; i++) {
7428                 mv_f[i].filter_type = filter_type;
7429                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7430                                 ETH_ADDR_LEN);
7431         }
7432         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7433                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7434                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7435                 if (ret != I40E_SUCCESS)
7436                         goto DONE;
7437         }
7438
7439         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7440         if (ret != I40E_SUCCESS)
7441                 goto DONE;
7442
7443         /* Remove the mac addr into mac list */
7444         TAILQ_REMOVE(&vsi->mac_list, f, next);
7445         rte_free(f);
7446         vsi->mac_num--;
7447
7448         ret = I40E_SUCCESS;
7449 DONE:
7450         rte_free(mv_f);
7451         return ret;
7452 }
7453
7454 /* Configure hash enable flags for RSS */
7455 uint64_t
7456 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7457 {
7458         uint64_t hena = 0;
7459         int i;
7460
7461         if (!flags)
7462                 return hena;
7463
7464         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7465                 if (flags & (1ULL << i))
7466                         hena |= adapter->pctypes_tbl[i];
7467         }
7468
7469         return hena;
7470 }
7471
7472 /* Parse the hash enable flags */
7473 uint64_t
7474 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7475 {
7476         uint64_t rss_hf = 0;
7477
7478         if (!flags)
7479                 return rss_hf;
7480         int i;
7481
7482         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7483                 if (flags & adapter->pctypes_tbl[i])
7484                         rss_hf |= (1ULL << i);
7485         }
7486         return rss_hf;
7487 }
7488
7489 /* Disable RSS */
7490 static void
7491 i40e_pf_disable_rss(struct i40e_pf *pf)
7492 {
7493         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7494
7495         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7496         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7497         I40E_WRITE_FLUSH(hw);
7498 }
7499
7500 int
7501 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7502 {
7503         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7504         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7505         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7506                            I40E_VFQF_HKEY_MAX_INDEX :
7507                            I40E_PFQF_HKEY_MAX_INDEX;
7508         int ret = 0;
7509
7510         if (!key || key_len == 0) {
7511                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7512                 return 0;
7513         } else if (key_len != (key_idx + 1) *
7514                 sizeof(uint32_t)) {
7515                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7516                 return -EINVAL;
7517         }
7518
7519         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7520                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7521                         (struct i40e_aqc_get_set_rss_key_data *)key;
7522
7523                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7524                 if (ret)
7525                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7526         } else {
7527                 uint32_t *hash_key = (uint32_t *)key;
7528                 uint16_t i;
7529
7530                 if (vsi->type == I40E_VSI_SRIOV) {
7531                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7532                                 I40E_WRITE_REG(
7533                                         hw,
7534                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7535                                         hash_key[i]);
7536
7537                 } else {
7538                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7539                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7540                                                hash_key[i]);
7541                 }
7542                 I40E_WRITE_FLUSH(hw);
7543         }
7544
7545         return ret;
7546 }
7547
7548 static int
7549 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7550 {
7551         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7552         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7553         uint32_t reg;
7554         int ret;
7555
7556         if (!key || !key_len)
7557                 return 0;
7558
7559         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7560                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7561                         (struct i40e_aqc_get_set_rss_key_data *)key);
7562                 if (ret) {
7563                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7564                         return ret;
7565                 }
7566         } else {
7567                 uint32_t *key_dw = (uint32_t *)key;
7568                 uint16_t i;
7569
7570                 if (vsi->type == I40E_VSI_SRIOV) {
7571                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7572                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7573                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7574                         }
7575                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7576                                    sizeof(uint32_t);
7577                 } else {
7578                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7579                                 reg = I40E_PFQF_HKEY(i);
7580                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7581                         }
7582                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7583                                    sizeof(uint32_t);
7584                 }
7585         }
7586         return 0;
7587 }
7588
7589 static int
7590 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7591 {
7592         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7593         uint64_t hena;
7594         int ret;
7595
7596         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7597                                rss_conf->rss_key_len);
7598         if (ret)
7599                 return ret;
7600
7601         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7602         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7603         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7604         I40E_WRITE_FLUSH(hw);
7605
7606         return 0;
7607 }
7608
7609 static int
7610 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7611                          struct rte_eth_rss_conf *rss_conf)
7612 {
7613         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7614         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7615         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7616         uint64_t hena;
7617
7618         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7619         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7620
7621         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7622                 if (rss_hf != 0) /* Enable RSS */
7623                         return -EINVAL;
7624                 return 0; /* Nothing to do */
7625         }
7626         /* RSS enabled */
7627         if (rss_hf == 0) /* Disable RSS */
7628                 return -EINVAL;
7629
7630         return i40e_hw_rss_hash_set(pf, rss_conf);
7631 }
7632
7633 static int
7634 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7635                            struct rte_eth_rss_conf *rss_conf)
7636 {
7637         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7638         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7639         uint64_t hena;
7640         int ret;
7641
7642         if (!rss_conf)
7643                 return -EINVAL;
7644
7645         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7646                          &rss_conf->rss_key_len);
7647         if (ret)
7648                 return ret;
7649
7650         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7651         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7652         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7653
7654         return 0;
7655 }
7656
7657 static int
7658 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7659 {
7660         switch (filter_type) {
7661         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7662                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7663                 break;
7664         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7665                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7666                 break;
7667         case RTE_TUNNEL_FILTER_IMAC_TENID:
7668                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7669                 break;
7670         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7671                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7672                 break;
7673         case ETH_TUNNEL_FILTER_IMAC:
7674                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7675                 break;
7676         case ETH_TUNNEL_FILTER_OIP:
7677                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7678                 break;
7679         case ETH_TUNNEL_FILTER_IIP:
7680                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7681                 break;
7682         default:
7683                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7684                 return -EINVAL;
7685         }
7686
7687         return 0;
7688 }
7689
7690 /* Convert tunnel filter structure */
7691 static int
7692 i40e_tunnel_filter_convert(
7693         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7694         struct i40e_tunnel_filter *tunnel_filter)
7695 {
7696         rte_ether_addr_copy((struct rte_ether_addr *)
7697                         &cld_filter->element.outer_mac,
7698                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7699         rte_ether_addr_copy((struct rte_ether_addr *)
7700                         &cld_filter->element.inner_mac,
7701                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7702         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7703         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7704              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7705             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7706                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7707         else
7708                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7709         tunnel_filter->input.flags = cld_filter->element.flags;
7710         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7711         tunnel_filter->queue = cld_filter->element.queue_number;
7712         rte_memcpy(tunnel_filter->input.general_fields,
7713                    cld_filter->general_fields,
7714                    sizeof(cld_filter->general_fields));
7715
7716         return 0;
7717 }
7718
7719 /* Check if there exists the tunnel filter */
7720 struct i40e_tunnel_filter *
7721 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7722                              const struct i40e_tunnel_filter_input *input)
7723 {
7724         int ret;
7725
7726         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7727         if (ret < 0)
7728                 return NULL;
7729
7730         return tunnel_rule->hash_map[ret];
7731 }
7732
7733 /* Add a tunnel filter into the SW list */
7734 static int
7735 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7736                              struct i40e_tunnel_filter *tunnel_filter)
7737 {
7738         struct i40e_tunnel_rule *rule = &pf->tunnel;
7739         int ret;
7740
7741         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7742         if (ret < 0) {
7743                 PMD_DRV_LOG(ERR,
7744                             "Failed to insert tunnel filter to hash table %d!",
7745                             ret);
7746                 return ret;
7747         }
7748         rule->hash_map[ret] = tunnel_filter;
7749
7750         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7751
7752         return 0;
7753 }
7754
7755 /* Delete a tunnel filter from the SW list */
7756 int
7757 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7758                           struct i40e_tunnel_filter_input *input)
7759 {
7760         struct i40e_tunnel_rule *rule = &pf->tunnel;
7761         struct i40e_tunnel_filter *tunnel_filter;
7762         int ret;
7763
7764         ret = rte_hash_del_key(rule->hash_table, input);
7765         if (ret < 0) {
7766                 PMD_DRV_LOG(ERR,
7767                             "Failed to delete tunnel filter to hash table %d!",
7768                             ret);
7769                 return ret;
7770         }
7771         tunnel_filter = rule->hash_map[ret];
7772         rule->hash_map[ret] = NULL;
7773
7774         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7775         rte_free(tunnel_filter);
7776
7777         return 0;
7778 }
7779
7780 int
7781 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7782                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7783                         uint8_t add)
7784 {
7785         uint16_t ip_type;
7786         uint32_t ipv4_addr, ipv4_addr_le;
7787         uint8_t i, tun_type = 0;
7788         /* internal varialbe to convert ipv6 byte order */
7789         uint32_t convert_ipv6[4];
7790         int val, ret = 0;
7791         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7792         struct i40e_vsi *vsi = pf->main_vsi;
7793         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7794         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7795         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7796         struct i40e_tunnel_filter *tunnel, *node;
7797         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7798
7799         cld_filter = rte_zmalloc("tunnel_filter",
7800                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7801         0);
7802
7803         if (NULL == cld_filter) {
7804                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7805                 return -ENOMEM;
7806         }
7807         pfilter = cld_filter;
7808
7809         rte_ether_addr_copy(&tunnel_filter->outer_mac,
7810                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7811         rte_ether_addr_copy(&tunnel_filter->inner_mac,
7812                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
7813
7814         pfilter->element.inner_vlan =
7815                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7816         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7817                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7818                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7819                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7820                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7821                                 &ipv4_addr_le,
7822                                 sizeof(pfilter->element.ipaddr.v4.data));
7823         } else {
7824                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7825                 for (i = 0; i < 4; i++) {
7826                         convert_ipv6[i] =
7827                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7828                 }
7829                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7830                            &convert_ipv6,
7831                            sizeof(pfilter->element.ipaddr.v6.data));
7832         }
7833
7834         /* check tunneled type */
7835         switch (tunnel_filter->tunnel_type) {
7836         case RTE_TUNNEL_TYPE_VXLAN:
7837                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7838                 break;
7839         case RTE_TUNNEL_TYPE_NVGRE:
7840                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7841                 break;
7842         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7843                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7844                 break;
7845         case RTE_TUNNEL_TYPE_VXLAN_GPE:
7846                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7847                 break;
7848         default:
7849                 /* Other tunnel types is not supported. */
7850                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7851                 rte_free(cld_filter);
7852                 return -EINVAL;
7853         }
7854
7855         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7856                                        &pfilter->element.flags);
7857         if (val < 0) {
7858                 rte_free(cld_filter);
7859                 return -EINVAL;
7860         }
7861
7862         pfilter->element.flags |= rte_cpu_to_le_16(
7863                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7864                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7865         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7866         pfilter->element.queue_number =
7867                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7868
7869         /* Check if there is the filter in SW list */
7870         memset(&check_filter, 0, sizeof(check_filter));
7871         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7872         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7873         if (add && node) {
7874                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7875                 rte_free(cld_filter);
7876                 return -EINVAL;
7877         }
7878
7879         if (!add && !node) {
7880                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7881                 rte_free(cld_filter);
7882                 return -EINVAL;
7883         }
7884
7885         if (add) {
7886                 ret = i40e_aq_add_cloud_filters(hw,
7887                                         vsi->seid, &cld_filter->element, 1);
7888                 if (ret < 0) {
7889                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7890                         rte_free(cld_filter);
7891                         return -ENOTSUP;
7892                 }
7893                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7894                 if (tunnel == NULL) {
7895                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7896                         rte_free(cld_filter);
7897                         return -ENOMEM;
7898                 }
7899
7900                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7901                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7902                 if (ret < 0)
7903                         rte_free(tunnel);
7904         } else {
7905                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7906                                                    &cld_filter->element, 1);
7907                 if (ret < 0) {
7908                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7909                         rte_free(cld_filter);
7910                         return -ENOTSUP;
7911                 }
7912                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7913         }
7914
7915         rte_free(cld_filter);
7916         return ret;
7917 }
7918
7919 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7920 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7921 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7922 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7923 #define I40E_TR_GRE_KEY_MASK                    0x400
7924 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7925 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7926
7927 static enum
7928 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7929 {
7930         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7931         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7932         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7933         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7934         enum i40e_status_code status = I40E_SUCCESS;
7935
7936         if (pf->support_multi_driver) {
7937                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7938                 return I40E_NOT_SUPPORTED;
7939         }
7940
7941         memset(&filter_replace, 0,
7942                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7943         memset(&filter_replace_buf, 0,
7944                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7945
7946         /* create L1 filter */
7947         filter_replace.old_filter_type =
7948                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7949         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7950         filter_replace.tr_bit = 0;
7951
7952         /* Prepare the buffer, 3 entries */
7953         filter_replace_buf.data[0] =
7954                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7955         filter_replace_buf.data[0] |=
7956                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7957         filter_replace_buf.data[2] = 0xFF;
7958         filter_replace_buf.data[3] = 0xFF;
7959         filter_replace_buf.data[4] =
7960                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7961         filter_replace_buf.data[4] |=
7962                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7963         filter_replace_buf.data[7] = 0xF0;
7964         filter_replace_buf.data[8]
7965                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7966         filter_replace_buf.data[8] |=
7967                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7968         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7969                 I40E_TR_GENEVE_KEY_MASK |
7970                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7971         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7972                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7973                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7974
7975         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7976                                                &filter_replace_buf);
7977         if (!status && (filter_replace.old_filter_type !=
7978                         filter_replace.new_filter_type))
7979                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7980                             " original: 0x%x, new: 0x%x",
7981                             dev->device->name,
7982                             filter_replace.old_filter_type,
7983                             filter_replace.new_filter_type);
7984
7985         return status;
7986 }
7987
7988 static enum
7989 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7990 {
7991         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7992         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7993         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7994         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7995         enum i40e_status_code status = I40E_SUCCESS;
7996
7997         if (pf->support_multi_driver) {
7998                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7999                 return I40E_NOT_SUPPORTED;
8000         }
8001
8002         /* For MPLSoUDP */
8003         memset(&filter_replace, 0,
8004                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8005         memset(&filter_replace_buf, 0,
8006                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8007         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8008                 I40E_AQC_MIRROR_CLOUD_FILTER;
8009         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8010         filter_replace.new_filter_type =
8011                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8012         /* Prepare the buffer, 2 entries */
8013         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8014         filter_replace_buf.data[0] |=
8015                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8016         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8017         filter_replace_buf.data[4] |=
8018                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8019         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8020                                                &filter_replace_buf);
8021         if (status < 0)
8022                 return status;
8023         if (filter_replace.old_filter_type !=
8024             filter_replace.new_filter_type)
8025                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8026                             " original: 0x%x, new: 0x%x",
8027                             dev->device->name,
8028                             filter_replace.old_filter_type,
8029                             filter_replace.new_filter_type);
8030
8031         /* For MPLSoGRE */
8032         memset(&filter_replace, 0,
8033                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8034         memset(&filter_replace_buf, 0,
8035                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8036
8037         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8038                 I40E_AQC_MIRROR_CLOUD_FILTER;
8039         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8040         filter_replace.new_filter_type =
8041                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8042         /* Prepare the buffer, 2 entries */
8043         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8044         filter_replace_buf.data[0] |=
8045                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8046         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8047         filter_replace_buf.data[4] |=
8048                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8049
8050         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8051                                                &filter_replace_buf);
8052         if (!status && (filter_replace.old_filter_type !=
8053                         filter_replace.new_filter_type))
8054                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8055                             " original: 0x%x, new: 0x%x",
8056                             dev->device->name,
8057                             filter_replace.old_filter_type,
8058                             filter_replace.new_filter_type);
8059
8060         return status;
8061 }
8062
8063 static enum i40e_status_code
8064 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8065 {
8066         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8067         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8068         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8069         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8070         enum i40e_status_code status = I40E_SUCCESS;
8071
8072         if (pf->support_multi_driver) {
8073                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8074                 return I40E_NOT_SUPPORTED;
8075         }
8076
8077         /* For GTP-C */
8078         memset(&filter_replace, 0,
8079                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8080         memset(&filter_replace_buf, 0,
8081                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8082         /* create L1 filter */
8083         filter_replace.old_filter_type =
8084                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8085         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8086         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8087                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8088         /* Prepare the buffer, 2 entries */
8089         filter_replace_buf.data[0] =
8090                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8091         filter_replace_buf.data[0] |=
8092                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8093         filter_replace_buf.data[2] = 0xFF;
8094         filter_replace_buf.data[3] = 0xFF;
8095         filter_replace_buf.data[4] =
8096                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8097         filter_replace_buf.data[4] |=
8098                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8099         filter_replace_buf.data[6] = 0xFF;
8100         filter_replace_buf.data[7] = 0xFF;
8101         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8102                                                &filter_replace_buf);
8103         if (status < 0)
8104                 return status;
8105         if (filter_replace.old_filter_type !=
8106             filter_replace.new_filter_type)
8107                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8108                             " original: 0x%x, new: 0x%x",
8109                             dev->device->name,
8110                             filter_replace.old_filter_type,
8111                             filter_replace.new_filter_type);
8112
8113         /* for GTP-U */
8114         memset(&filter_replace, 0,
8115                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8116         memset(&filter_replace_buf, 0,
8117                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8118         /* create L1 filter */
8119         filter_replace.old_filter_type =
8120                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8121         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8122         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8123                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8124         /* Prepare the buffer, 2 entries */
8125         filter_replace_buf.data[0] =
8126                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8127         filter_replace_buf.data[0] |=
8128                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8129         filter_replace_buf.data[2] = 0xFF;
8130         filter_replace_buf.data[3] = 0xFF;
8131         filter_replace_buf.data[4] =
8132                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8133         filter_replace_buf.data[4] |=
8134                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8135         filter_replace_buf.data[6] = 0xFF;
8136         filter_replace_buf.data[7] = 0xFF;
8137
8138         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8139                                                &filter_replace_buf);
8140         if (!status && (filter_replace.old_filter_type !=
8141                         filter_replace.new_filter_type))
8142                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8143                             " original: 0x%x, new: 0x%x",
8144                             dev->device->name,
8145                             filter_replace.old_filter_type,
8146                             filter_replace.new_filter_type);
8147
8148         return status;
8149 }
8150
8151 static enum
8152 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8153 {
8154         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8155         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8156         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8157         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8158         enum i40e_status_code status = I40E_SUCCESS;
8159
8160         if (pf->support_multi_driver) {
8161                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8162                 return I40E_NOT_SUPPORTED;
8163         }
8164
8165         /* for GTP-C */
8166         memset(&filter_replace, 0,
8167                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8168         memset(&filter_replace_buf, 0,
8169                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8170         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8171         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8172         filter_replace.new_filter_type =
8173                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8174         /* Prepare the buffer, 2 entries */
8175         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8176         filter_replace_buf.data[0] |=
8177                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8178         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8179         filter_replace_buf.data[4] |=
8180                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8181         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8182                                                &filter_replace_buf);
8183         if (status < 0)
8184                 return status;
8185         if (filter_replace.old_filter_type !=
8186             filter_replace.new_filter_type)
8187                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8188                             " original: 0x%x, new: 0x%x",
8189                             dev->device->name,
8190                             filter_replace.old_filter_type,
8191                             filter_replace.new_filter_type);
8192
8193         /* for GTP-U */
8194         memset(&filter_replace, 0,
8195                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8196         memset(&filter_replace_buf, 0,
8197                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8198         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8199         filter_replace.old_filter_type =
8200                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8201         filter_replace.new_filter_type =
8202                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8203         /* Prepare the buffer, 2 entries */
8204         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8205         filter_replace_buf.data[0] |=
8206                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8207         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8208         filter_replace_buf.data[4] |=
8209                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8210
8211         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8212                                                &filter_replace_buf);
8213         if (!status && (filter_replace.old_filter_type !=
8214                         filter_replace.new_filter_type))
8215                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8216                             " original: 0x%x, new: 0x%x",
8217                             dev->device->name,
8218                             filter_replace.old_filter_type,
8219                             filter_replace.new_filter_type);
8220
8221         return status;
8222 }
8223
8224 int
8225 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8226                       struct i40e_tunnel_filter_conf *tunnel_filter,
8227                       uint8_t add)
8228 {
8229         uint16_t ip_type;
8230         uint32_t ipv4_addr, ipv4_addr_le;
8231         uint8_t i, tun_type = 0;
8232         /* internal variable to convert ipv6 byte order */
8233         uint32_t convert_ipv6[4];
8234         int val, ret = 0;
8235         struct i40e_pf_vf *vf = NULL;
8236         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8237         struct i40e_vsi *vsi;
8238         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8239         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8240         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8241         struct i40e_tunnel_filter *tunnel, *node;
8242         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8243         uint32_t teid_le;
8244         bool big_buffer = 0;
8245
8246         cld_filter = rte_zmalloc("tunnel_filter",
8247                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8248                          0);
8249
8250         if (cld_filter == NULL) {
8251                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8252                 return -ENOMEM;
8253         }
8254         pfilter = cld_filter;
8255
8256         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8257                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8258         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8259                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8260
8261         pfilter->element.inner_vlan =
8262                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8263         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8264                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8265                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8266                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8267                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8268                                 &ipv4_addr_le,
8269                                 sizeof(pfilter->element.ipaddr.v4.data));
8270         } else {
8271                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8272                 for (i = 0; i < 4; i++) {
8273                         convert_ipv6[i] =
8274                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8275                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8276                 }
8277                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8278                            &convert_ipv6,
8279                            sizeof(pfilter->element.ipaddr.v6.data));
8280         }
8281
8282         /* check tunneled type */
8283         switch (tunnel_filter->tunnel_type) {
8284         case I40E_TUNNEL_TYPE_VXLAN:
8285                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8286                 break;
8287         case I40E_TUNNEL_TYPE_NVGRE:
8288                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8289                 break;
8290         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8291                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8292                 break;
8293         case I40E_TUNNEL_TYPE_MPLSoUDP:
8294                 if (!pf->mpls_replace_flag) {
8295                         i40e_replace_mpls_l1_filter(pf);
8296                         i40e_replace_mpls_cloud_filter(pf);
8297                         pf->mpls_replace_flag = 1;
8298                 }
8299                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8300                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8301                         teid_le >> 4;
8302                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8303                         (teid_le & 0xF) << 12;
8304                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8305                         0x40;
8306                 big_buffer = 1;
8307                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8308                 break;
8309         case I40E_TUNNEL_TYPE_MPLSoGRE:
8310                 if (!pf->mpls_replace_flag) {
8311                         i40e_replace_mpls_l1_filter(pf);
8312                         i40e_replace_mpls_cloud_filter(pf);
8313                         pf->mpls_replace_flag = 1;
8314                 }
8315                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8316                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8317                         teid_le >> 4;
8318                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8319                         (teid_le & 0xF) << 12;
8320                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8321                         0x0;
8322                 big_buffer = 1;
8323                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8324                 break;
8325         case I40E_TUNNEL_TYPE_GTPC:
8326                 if (!pf->gtp_replace_flag) {
8327                         i40e_replace_gtp_l1_filter(pf);
8328                         i40e_replace_gtp_cloud_filter(pf);
8329                         pf->gtp_replace_flag = 1;
8330                 }
8331                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8332                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8333                         (teid_le >> 16) & 0xFFFF;
8334                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8335                         teid_le & 0xFFFF;
8336                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8337                         0x0;
8338                 big_buffer = 1;
8339                 break;
8340         case I40E_TUNNEL_TYPE_GTPU:
8341                 if (!pf->gtp_replace_flag) {
8342                         i40e_replace_gtp_l1_filter(pf);
8343                         i40e_replace_gtp_cloud_filter(pf);
8344                         pf->gtp_replace_flag = 1;
8345                 }
8346                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8347                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8348                         (teid_le >> 16) & 0xFFFF;
8349                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8350                         teid_le & 0xFFFF;
8351                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8352                         0x0;
8353                 big_buffer = 1;
8354                 break;
8355         case I40E_TUNNEL_TYPE_QINQ:
8356                 if (!pf->qinq_replace_flag) {
8357                         ret = i40e_cloud_filter_qinq_create(pf);
8358                         if (ret < 0)
8359                                 PMD_DRV_LOG(DEBUG,
8360                                             "QinQ tunnel filter already created.");
8361                         pf->qinq_replace_flag = 1;
8362                 }
8363                 /*      Add in the General fields the values of
8364                  *      the Outer and Inner VLAN
8365                  *      Big Buffer should be set, see changes in
8366                  *      i40e_aq_add_cloud_filters
8367                  */
8368                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8369                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8370                 big_buffer = 1;
8371                 break;
8372         default:
8373                 /* Other tunnel types is not supported. */
8374                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8375                 rte_free(cld_filter);
8376                 return -EINVAL;
8377         }
8378
8379         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8380                 pfilter->element.flags =
8381                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8382         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8383                 pfilter->element.flags =
8384                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8385         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8386                 pfilter->element.flags =
8387                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8388         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8389                 pfilter->element.flags =
8390                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8391         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8392                 pfilter->element.flags |=
8393                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8394         else {
8395                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8396                                                 &pfilter->element.flags);
8397                 if (val < 0) {
8398                         rte_free(cld_filter);
8399                         return -EINVAL;
8400                 }
8401         }
8402
8403         pfilter->element.flags |= rte_cpu_to_le_16(
8404                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8405                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8406         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8407         pfilter->element.queue_number =
8408                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8409
8410         if (!tunnel_filter->is_to_vf)
8411                 vsi = pf->main_vsi;
8412         else {
8413                 if (tunnel_filter->vf_id >= pf->vf_num) {
8414                         PMD_DRV_LOG(ERR, "Invalid argument.");
8415                         rte_free(cld_filter);
8416                         return -EINVAL;
8417                 }
8418                 vf = &pf->vfs[tunnel_filter->vf_id];
8419                 vsi = vf->vsi;
8420         }
8421
8422         /* Check if there is the filter in SW list */
8423         memset(&check_filter, 0, sizeof(check_filter));
8424         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8425         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8426         check_filter.vf_id = tunnel_filter->vf_id;
8427         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8428         if (add && node) {
8429                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8430                 rte_free(cld_filter);
8431                 return -EINVAL;
8432         }
8433
8434         if (!add && !node) {
8435                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8436                 rte_free(cld_filter);
8437                 return -EINVAL;
8438         }
8439
8440         if (add) {
8441                 if (big_buffer)
8442                         ret = i40e_aq_add_cloud_filters_bb(hw,
8443                                                    vsi->seid, cld_filter, 1);
8444                 else
8445                         ret = i40e_aq_add_cloud_filters(hw,
8446                                         vsi->seid, &cld_filter->element, 1);
8447                 if (ret < 0) {
8448                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8449                         rte_free(cld_filter);
8450                         return -ENOTSUP;
8451                 }
8452                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8453                 if (tunnel == NULL) {
8454                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8455                         rte_free(cld_filter);
8456                         return -ENOMEM;
8457                 }
8458
8459                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8460                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8461                 if (ret < 0)
8462                         rte_free(tunnel);
8463         } else {
8464                 if (big_buffer)
8465                         ret = i40e_aq_rem_cloud_filters_bb(
8466                                 hw, vsi->seid, cld_filter, 1);
8467                 else
8468                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8469                                                 &cld_filter->element, 1);
8470                 if (ret < 0) {
8471                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8472                         rte_free(cld_filter);
8473                         return -ENOTSUP;
8474                 }
8475                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8476         }
8477
8478         rte_free(cld_filter);
8479         return ret;
8480 }
8481
8482 static int
8483 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8484 {
8485         uint8_t i;
8486
8487         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8488                 if (pf->vxlan_ports[i] == port)
8489                         return i;
8490         }
8491
8492         return -1;
8493 }
8494
8495 static int
8496 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8497 {
8498         int  idx, ret;
8499         uint8_t filter_idx = 0;
8500         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8501
8502         idx = i40e_get_vxlan_port_idx(pf, port);
8503
8504         /* Check if port already exists */
8505         if (idx >= 0) {
8506                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8507                 return -EINVAL;
8508         }
8509
8510         /* Now check if there is space to add the new port */
8511         idx = i40e_get_vxlan_port_idx(pf, 0);
8512         if (idx < 0) {
8513                 PMD_DRV_LOG(ERR,
8514                         "Maximum number of UDP ports reached, not adding port %d",
8515                         port);
8516                 return -ENOSPC;
8517         }
8518
8519         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8520                                         &filter_idx, NULL);
8521         if (ret < 0) {
8522                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8523                 return -1;
8524         }
8525
8526         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8527                          port,  filter_idx);
8528
8529         /* New port: add it and mark its index in the bitmap */
8530         pf->vxlan_ports[idx] = port;
8531         pf->vxlan_bitmap |= (1 << idx);
8532
8533         if (!(pf->flags & I40E_FLAG_VXLAN))
8534                 pf->flags |= I40E_FLAG_VXLAN;
8535
8536         return 0;
8537 }
8538
8539 static int
8540 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8541 {
8542         int idx;
8543         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8544
8545         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8546                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8547                 return -EINVAL;
8548         }
8549
8550         idx = i40e_get_vxlan_port_idx(pf, port);
8551
8552         if (idx < 0) {
8553                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8554                 return -EINVAL;
8555         }
8556
8557         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8558                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8559                 return -1;
8560         }
8561
8562         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8563                         port, idx);
8564
8565         pf->vxlan_ports[idx] = 0;
8566         pf->vxlan_bitmap &= ~(1 << idx);
8567
8568         if (!pf->vxlan_bitmap)
8569                 pf->flags &= ~I40E_FLAG_VXLAN;
8570
8571         return 0;
8572 }
8573
8574 /* Add UDP tunneling port */
8575 static int
8576 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8577                              struct rte_eth_udp_tunnel *udp_tunnel)
8578 {
8579         int ret = 0;
8580         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8581
8582         if (udp_tunnel == NULL)
8583                 return -EINVAL;
8584
8585         switch (udp_tunnel->prot_type) {
8586         case RTE_TUNNEL_TYPE_VXLAN:
8587                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8588                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8589                 break;
8590         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8591                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8592                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8593                 break;
8594         case RTE_TUNNEL_TYPE_GENEVE:
8595         case RTE_TUNNEL_TYPE_TEREDO:
8596                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8597                 ret = -1;
8598                 break;
8599
8600         default:
8601                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8602                 ret = -1;
8603                 break;
8604         }
8605
8606         return ret;
8607 }
8608
8609 /* Remove UDP tunneling port */
8610 static int
8611 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8612                              struct rte_eth_udp_tunnel *udp_tunnel)
8613 {
8614         int ret = 0;
8615         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8616
8617         if (udp_tunnel == NULL)
8618                 return -EINVAL;
8619
8620         switch (udp_tunnel->prot_type) {
8621         case RTE_TUNNEL_TYPE_VXLAN:
8622         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8623                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8624                 break;
8625         case RTE_TUNNEL_TYPE_GENEVE:
8626         case RTE_TUNNEL_TYPE_TEREDO:
8627                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8628                 ret = -1;
8629                 break;
8630         default:
8631                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8632                 ret = -1;
8633                 break;
8634         }
8635
8636         return ret;
8637 }
8638
8639 /* Calculate the maximum number of contiguous PF queues that are configured */
8640 static int
8641 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8642 {
8643         struct rte_eth_dev_data *data = pf->dev_data;
8644         int i, num;
8645         struct i40e_rx_queue *rxq;
8646
8647         num = 0;
8648         for (i = 0; i < pf->lan_nb_qps; i++) {
8649                 rxq = data->rx_queues[i];
8650                 if (rxq && rxq->q_set)
8651                         num++;
8652                 else
8653                         break;
8654         }
8655
8656         return num;
8657 }
8658
8659 /* Configure RSS */
8660 static int
8661 i40e_pf_config_rss(struct i40e_pf *pf)
8662 {
8663         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8664         struct rte_eth_rss_conf rss_conf;
8665         uint32_t i, lut = 0;
8666         uint16_t j, num;
8667
8668         /*
8669          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8670          * It's necessary to calculate the actual PF queues that are configured.
8671          */
8672         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8673                 num = i40e_pf_calc_configured_queues_num(pf);
8674         else
8675                 num = pf->dev_data->nb_rx_queues;
8676
8677         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8678         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8679                         num);
8680
8681         if (num == 0) {
8682                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8683                 return -ENOTSUP;
8684         }
8685
8686         if (pf->adapter->rss_reta_updated == 0) {
8687                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8688                         if (j == num)
8689                                 j = 0;
8690                         lut = (lut << 8) | (j & ((0x1 <<
8691                                 hw->func_caps.rss_table_entry_width) - 1));
8692                         if ((i & 3) == 3)
8693                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8694                                                rte_bswap32(lut));
8695                 }
8696         }
8697
8698         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8699         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8700                 i40e_pf_disable_rss(pf);
8701                 return 0;
8702         }
8703         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8704                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8705                 /* Random default keys */
8706                 static uint32_t rss_key_default[] = {0x6b793944,
8707                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8708                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8709                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8710
8711                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8712                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8713                                                         sizeof(uint32_t);
8714         }
8715
8716         return i40e_hw_rss_hash_set(pf, &rss_conf);
8717 }
8718
8719 static int
8720 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8721                                struct rte_eth_tunnel_filter_conf *filter)
8722 {
8723         if (pf == NULL || filter == NULL) {
8724                 PMD_DRV_LOG(ERR, "Invalid parameter");
8725                 return -EINVAL;
8726         }
8727
8728         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8729                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8730                 return -EINVAL;
8731         }
8732
8733         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8734                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8735                 return -EINVAL;
8736         }
8737
8738         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8739                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8740                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8741                 return -EINVAL;
8742         }
8743
8744         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8745                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8746                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8747                 return -EINVAL;
8748         }
8749
8750         return 0;
8751 }
8752
8753 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8754 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8755 static int
8756 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8757 {
8758         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8759         uint32_t val, reg;
8760         int ret = -EINVAL;
8761
8762         if (pf->support_multi_driver) {
8763                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8764                 return -ENOTSUP;
8765         }
8766
8767         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8768         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8769
8770         if (len == 3) {
8771                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8772         } else if (len == 4) {
8773                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8774         } else {
8775                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8776                 return ret;
8777         }
8778
8779         if (reg != val) {
8780                 ret = i40e_aq_debug_write_global_register(hw,
8781                                                    I40E_GL_PRS_FVBM(2),
8782                                                    reg, NULL);
8783                 if (ret != 0)
8784                         return ret;
8785                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8786                             "with value 0x%08x",
8787                             I40E_GL_PRS_FVBM(2), reg);
8788         } else {
8789                 ret = 0;
8790         }
8791         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8792                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8793
8794         return ret;
8795 }
8796
8797 static int
8798 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8799 {
8800         int ret = -EINVAL;
8801
8802         if (!hw || !cfg)
8803                 return -EINVAL;
8804
8805         switch (cfg->cfg_type) {
8806         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8807                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8808                 break;
8809         default:
8810                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8811                 break;
8812         }
8813
8814         return ret;
8815 }
8816
8817 static int
8818 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8819                                enum rte_filter_op filter_op,
8820                                void *arg)
8821 {
8822         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8823         int ret = I40E_ERR_PARAM;
8824
8825         switch (filter_op) {
8826         case RTE_ETH_FILTER_SET:
8827                 ret = i40e_dev_global_config_set(hw,
8828                         (struct rte_eth_global_cfg *)arg);
8829                 break;
8830         default:
8831                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8832                 break;
8833         }
8834
8835         return ret;
8836 }
8837
8838 static int
8839 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8840                           enum rte_filter_op filter_op,
8841                           void *arg)
8842 {
8843         struct rte_eth_tunnel_filter_conf *filter;
8844         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8845         int ret = I40E_SUCCESS;
8846
8847         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8848
8849         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8850                 return I40E_ERR_PARAM;
8851
8852         switch (filter_op) {
8853         case RTE_ETH_FILTER_NOP:
8854                 if (!(pf->flags & I40E_FLAG_VXLAN))
8855                         ret = I40E_NOT_SUPPORTED;
8856                 break;
8857         case RTE_ETH_FILTER_ADD:
8858                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8859                 break;
8860         case RTE_ETH_FILTER_DELETE:
8861                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8862                 break;
8863         default:
8864                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8865                 ret = I40E_ERR_PARAM;
8866                 break;
8867         }
8868
8869         return ret;
8870 }
8871
8872 static int
8873 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8874 {
8875         int ret = 0;
8876         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8877
8878         /* RSS setup */
8879         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8880                 ret = i40e_pf_config_rss(pf);
8881         else
8882                 i40e_pf_disable_rss(pf);
8883
8884         return ret;
8885 }
8886
8887 /* Get the symmetric hash enable configurations per port */
8888 static void
8889 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8890 {
8891         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8892
8893         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8894 }
8895
8896 /* Set the symmetric hash enable configurations per port */
8897 static void
8898 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8899 {
8900         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8901
8902         if (enable > 0) {
8903                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8904                         PMD_DRV_LOG(INFO,
8905                                 "Symmetric hash has already been enabled");
8906                         return;
8907                 }
8908                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8909         } else {
8910                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8911                         PMD_DRV_LOG(INFO,
8912                                 "Symmetric hash has already been disabled");
8913                         return;
8914                 }
8915                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8916         }
8917         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8918         I40E_WRITE_FLUSH(hw);
8919 }
8920
8921 /*
8922  * Get global configurations of hash function type and symmetric hash enable
8923  * per flow type (pctype). Note that global configuration means it affects all
8924  * the ports on the same NIC.
8925  */
8926 static int
8927 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8928                                    struct rte_eth_hash_global_conf *g_cfg)
8929 {
8930         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8931         uint32_t reg;
8932         uint16_t i, j;
8933
8934         memset(g_cfg, 0, sizeof(*g_cfg));
8935         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8936         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8937                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8938         else
8939                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8940         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8941                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8942
8943         /*
8944          * As i40e supports less than 64 flow types, only first 64 bits need to
8945          * be checked.
8946          */
8947         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8948                 g_cfg->valid_bit_mask[i] = 0ULL;
8949                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8950         }
8951
8952         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8953
8954         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8955                 if (!adapter->pctypes_tbl[i])
8956                         continue;
8957                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8958                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8959                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8960                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8961                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8962                                         g_cfg->sym_hash_enable_mask[0] |=
8963                                                                 (1ULL << i);
8964                                 }
8965                         }
8966                 }
8967         }
8968
8969         return 0;
8970 }
8971
8972 static int
8973 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8974                               const struct rte_eth_hash_global_conf *g_cfg)
8975 {
8976         uint32_t i;
8977         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8978
8979         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8980                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8981                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8982                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8983                                                 g_cfg->hash_func);
8984                 return -EINVAL;
8985         }
8986
8987         /*
8988          * As i40e supports less than 64 flow types, only first 64 bits need to
8989          * be checked.
8990          */
8991         mask0 = g_cfg->valid_bit_mask[0];
8992         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8993                 if (i == 0) {
8994                         /* Check if any unsupported flow type configured */
8995                         if ((mask0 | i40e_mask) ^ i40e_mask)
8996                                 goto mask_err;
8997                 } else {
8998                         if (g_cfg->valid_bit_mask[i])
8999                                 goto mask_err;
9000                 }
9001         }
9002
9003         return 0;
9004
9005 mask_err:
9006         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9007
9008         return -EINVAL;
9009 }
9010
9011 /*
9012  * Set global configurations of hash function type and symmetric hash enable
9013  * per flow type (pctype). Note any modifying global configuration will affect
9014  * all the ports on the same NIC.
9015  */
9016 static int
9017 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9018                                    struct rte_eth_hash_global_conf *g_cfg)
9019 {
9020         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9021         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9022         int ret;
9023         uint16_t i, j;
9024         uint32_t reg;
9025         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9026
9027         if (pf->support_multi_driver) {
9028                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9029                 return -ENOTSUP;
9030         }
9031
9032         /* Check the input parameters */
9033         ret = i40e_hash_global_config_check(adapter, g_cfg);
9034         if (ret < 0)
9035                 return ret;
9036
9037         /*
9038          * As i40e supports less than 64 flow types, only first 64 bits need to
9039          * be configured.
9040          */
9041         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9042                 if (mask0 & (1UL << i)) {
9043                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9044                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9045
9046                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9047                              j < I40E_FILTER_PCTYPE_MAX; j++) {
9048                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
9049                                         i40e_write_global_rx_ctl(hw,
9050                                                           I40E_GLQF_HSYM(j),
9051                                                           reg);
9052                         }
9053                 }
9054         }
9055
9056         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9057         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9058                 /* Toeplitz */
9059                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9060                         PMD_DRV_LOG(DEBUG,
9061                                 "Hash function already set to Toeplitz");
9062                         goto out;
9063                 }
9064                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9065         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9066                 /* Simple XOR */
9067                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9068                         PMD_DRV_LOG(DEBUG,
9069                                 "Hash function already set to Simple XOR");
9070                         goto out;
9071                 }
9072                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9073         } else
9074                 /* Use the default, and keep it as it is */
9075                 goto out;
9076
9077         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9078
9079 out:
9080         I40E_WRITE_FLUSH(hw);
9081
9082         return 0;
9083 }
9084
9085 /**
9086  * Valid input sets for hash and flow director filters per PCTYPE
9087  */
9088 static uint64_t
9089 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9090                 enum rte_filter_type filter)
9091 {
9092         uint64_t valid;
9093
9094         static const uint64_t valid_hash_inset_table[] = {
9095                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9096                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9097                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9098                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9099                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9100                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9101                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9102                         I40E_INSET_FLEX_PAYLOAD,
9103                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9104                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9105                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9106                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9107                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9108                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9109                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9110                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9111                         I40E_INSET_FLEX_PAYLOAD,
9112                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9113                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9114                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9115                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9116                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9117                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9118                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9119                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9120                         I40E_INSET_FLEX_PAYLOAD,
9121                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9122                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9123                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9124                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9125                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9126                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9127                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9128                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9129                         I40E_INSET_FLEX_PAYLOAD,
9130                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9131                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9132                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9133                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9134                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9135                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9136                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9137                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9138                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9139                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9140                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9141                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9142                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9143                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9144                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9145                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9146                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9147                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9148                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9149                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9150                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9151                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9152                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9153                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9154                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9155                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9156                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9157                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9158                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9159                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9160                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9161                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9162                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9163                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9164                         I40E_INSET_FLEX_PAYLOAD,
9165                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9166                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9167                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9168                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9169                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9170                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9171                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9172                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9173                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9174                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9175                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9176                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9177                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9178                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9179                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9180                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9181                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9182                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9183                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9184                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9185                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9186                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9187                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9188                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9189                         I40E_INSET_FLEX_PAYLOAD,
9190                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9191                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9192                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9193                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9194                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9195                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9196                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9197                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9198                         I40E_INSET_FLEX_PAYLOAD,
9199                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9200                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9201                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9202                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9203                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9204                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9205                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9206                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9207                         I40E_INSET_FLEX_PAYLOAD,
9208                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9209                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9210                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9211                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9212                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9213                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9214                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9215                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9216                         I40E_INSET_FLEX_PAYLOAD,
9217                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9218                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9219                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9220                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9221                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9222                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9223                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9224                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9225                         I40E_INSET_FLEX_PAYLOAD,
9226                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9227                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9228                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9229                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9230                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9231                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9232                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9233                         I40E_INSET_FLEX_PAYLOAD,
9234                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9235                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9236                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9237                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9238                         I40E_INSET_FLEX_PAYLOAD,
9239         };
9240
9241         /**
9242          * Flow director supports only fields defined in
9243          * union rte_eth_fdir_flow.
9244          */
9245         static const uint64_t valid_fdir_inset_table[] = {
9246                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9247                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9248                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9249                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9250                 I40E_INSET_IPV4_TTL,
9251                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9252                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9253                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9254                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9255                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9256                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9257                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9258                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9259                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9260                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9261                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9262                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9263                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9264                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9265                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9266                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9267                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9268                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9269                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9270                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9271                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9272                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9273                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9274                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9275                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9276                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9277                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9278                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9279                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9280                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9281                 I40E_INSET_SCTP_VT,
9282                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9283                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9284                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9285                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9286                 I40E_INSET_IPV4_TTL,
9287                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9288                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9289                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9290                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9291                 I40E_INSET_IPV6_HOP_LIMIT,
9292                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9293                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9294                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9295                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9296                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9297                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9298                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9299                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9300                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9301                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9302                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9303                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9304                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9305                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9306                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9307                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9308                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9309                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9310                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9311                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9312                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9313                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9314                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9315                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9316                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9317                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9318                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9319                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9320                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9321                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9322                 I40E_INSET_SCTP_VT,
9323                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9324                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9325                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9326                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9327                 I40E_INSET_IPV6_HOP_LIMIT,
9328                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9329                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9330                 I40E_INSET_LAST_ETHER_TYPE,
9331         };
9332
9333         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9334                 return 0;
9335         if (filter == RTE_ETH_FILTER_HASH)
9336                 valid = valid_hash_inset_table[pctype];
9337         else
9338                 valid = valid_fdir_inset_table[pctype];
9339
9340         return valid;
9341 }
9342
9343 /**
9344  * Validate if the input set is allowed for a specific PCTYPE
9345  */
9346 int
9347 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9348                 enum rte_filter_type filter, uint64_t inset)
9349 {
9350         uint64_t valid;
9351
9352         valid = i40e_get_valid_input_set(pctype, filter);
9353         if (inset & (~valid))
9354                 return -EINVAL;
9355
9356         return 0;
9357 }
9358
9359 /* default input set fields combination per pctype */
9360 uint64_t
9361 i40e_get_default_input_set(uint16_t pctype)
9362 {
9363         static const uint64_t default_inset_table[] = {
9364                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9365                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9366                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9367                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9368                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9369                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9370                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9371                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9372                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9373                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9374                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9375                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9376                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9377                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9378                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9379                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9380                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9381                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9382                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9383                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9384                         I40E_INSET_SCTP_VT,
9385                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9386                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9387                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9388                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9389                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9390                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9391                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9392                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9393                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9394                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9395                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9396                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9397                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9398                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9399                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9400                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9401                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9402                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9403                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9404                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9405                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9406                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9407                         I40E_INSET_SCTP_VT,
9408                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9409                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9410                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9411                         I40E_INSET_LAST_ETHER_TYPE,
9412         };
9413
9414         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9415                 return 0;
9416
9417         return default_inset_table[pctype];
9418 }
9419
9420 /**
9421  * Parse the input set from index to logical bit masks
9422  */
9423 static int
9424 i40e_parse_input_set(uint64_t *inset,
9425                      enum i40e_filter_pctype pctype,
9426                      enum rte_eth_input_set_field *field,
9427                      uint16_t size)
9428 {
9429         uint16_t i, j;
9430         int ret = -EINVAL;
9431
9432         static const struct {
9433                 enum rte_eth_input_set_field field;
9434                 uint64_t inset;
9435         } inset_convert_table[] = {
9436                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9437                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9438                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9439                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9440                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9441                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9442                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9443                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9444                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9445                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9446                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9447                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9448                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9449                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9450                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9451                         I40E_INSET_IPV6_NEXT_HDR},
9452                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9453                         I40E_INSET_IPV6_HOP_LIMIT},
9454                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9455                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9456                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9457                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9458                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9459                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9460                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9461                         I40E_INSET_SCTP_VT},
9462                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9463                         I40E_INSET_TUNNEL_DMAC},
9464                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9465                         I40E_INSET_VLAN_TUNNEL},
9466                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9467                         I40E_INSET_TUNNEL_ID},
9468                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9469                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9470                         I40E_INSET_FLEX_PAYLOAD_W1},
9471                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9472                         I40E_INSET_FLEX_PAYLOAD_W2},
9473                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9474                         I40E_INSET_FLEX_PAYLOAD_W3},
9475                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9476                         I40E_INSET_FLEX_PAYLOAD_W4},
9477                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9478                         I40E_INSET_FLEX_PAYLOAD_W5},
9479                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9480                         I40E_INSET_FLEX_PAYLOAD_W6},
9481                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9482                         I40E_INSET_FLEX_PAYLOAD_W7},
9483                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9484                         I40E_INSET_FLEX_PAYLOAD_W8},
9485         };
9486
9487         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9488                 return ret;
9489
9490         /* Only one item allowed for default or all */
9491         if (size == 1) {
9492                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9493                         *inset = i40e_get_default_input_set(pctype);
9494                         return 0;
9495                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9496                         *inset = I40E_INSET_NONE;
9497                         return 0;
9498                 }
9499         }
9500
9501         for (i = 0, *inset = 0; i < size; i++) {
9502                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9503                         if (field[i] == inset_convert_table[j].field) {
9504                                 *inset |= inset_convert_table[j].inset;
9505                                 break;
9506                         }
9507                 }
9508
9509                 /* It contains unsupported input set, return immediately */
9510                 if (j == RTE_DIM(inset_convert_table))
9511                         return ret;
9512         }
9513
9514         return 0;
9515 }
9516
9517 /**
9518  * Translate the input set from bit masks to register aware bit masks
9519  * and vice versa
9520  */
9521 uint64_t
9522 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9523 {
9524         uint64_t val = 0;
9525         uint16_t i;
9526
9527         struct inset_map {
9528                 uint64_t inset;
9529                 uint64_t inset_reg;
9530         };
9531
9532         static const struct inset_map inset_map_common[] = {
9533                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9534                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9535                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9536                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9537                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9538                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9539                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9540                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9541                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9542                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9543                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9544                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9545                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9546                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9547                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9548                 {I40E_INSET_TUNNEL_DMAC,
9549                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9550                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9551                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9552                 {I40E_INSET_TUNNEL_SRC_PORT,
9553                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9554                 {I40E_INSET_TUNNEL_DST_PORT,
9555                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9556                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9557                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9558                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9559                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9560                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9561                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9562                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9563                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9564                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9565         };
9566
9567     /* some different registers map in x722*/
9568         static const struct inset_map inset_map_diff_x722[] = {
9569                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9570                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9571                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9572                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9573         };
9574
9575         static const struct inset_map inset_map_diff_not_x722[] = {
9576                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9577                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9578                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9579                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9580         };
9581
9582         if (input == 0)
9583                 return val;
9584
9585         /* Translate input set to register aware inset */
9586         if (type == I40E_MAC_X722) {
9587                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9588                         if (input & inset_map_diff_x722[i].inset)
9589                                 val |= inset_map_diff_x722[i].inset_reg;
9590                 }
9591         } else {
9592                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9593                         if (input & inset_map_diff_not_x722[i].inset)
9594                                 val |= inset_map_diff_not_x722[i].inset_reg;
9595                 }
9596         }
9597
9598         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9599                 if (input & inset_map_common[i].inset)
9600                         val |= inset_map_common[i].inset_reg;
9601         }
9602
9603         return val;
9604 }
9605
9606 int
9607 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9608 {
9609         uint8_t i, idx = 0;
9610         uint64_t inset_need_mask = inset;
9611
9612         static const struct {
9613                 uint64_t inset;
9614                 uint32_t mask;
9615         } inset_mask_map[] = {
9616                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9617                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9618                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9619                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9620                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9621                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9622                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9623                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9624         };
9625
9626         if (!inset || !mask || !nb_elem)
9627                 return 0;
9628
9629         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9630                 /* Clear the inset bit, if no MASK is required,
9631                  * for example proto + ttl
9632                  */
9633                 if ((inset & inset_mask_map[i].inset) ==
9634                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9635                         inset_need_mask &= ~inset_mask_map[i].inset;
9636                 if (!inset_need_mask)
9637                         return 0;
9638         }
9639         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9640                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9641                     inset_mask_map[i].inset) {
9642                         if (idx >= nb_elem) {
9643                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9644                                 return -EINVAL;
9645                         }
9646                         mask[idx] = inset_mask_map[i].mask;
9647                         idx++;
9648                 }
9649         }
9650
9651         return idx;
9652 }
9653
9654 void
9655 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9656 {
9657         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9658
9659         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9660         if (reg != val)
9661                 i40e_write_rx_ctl(hw, addr, val);
9662         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9663                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9664 }
9665
9666 void
9667 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9668 {
9669         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9670         struct rte_eth_dev *dev;
9671
9672         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9673         if (reg != val) {
9674                 i40e_write_rx_ctl(hw, addr, val);
9675                 PMD_DRV_LOG(WARNING,
9676                             "i40e device %s changed global register [0x%08x]."
9677                             " original: 0x%08x, new: 0x%08x",
9678                             dev->device->name, addr, reg,
9679                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9680         }
9681 }
9682
9683 static void
9684 i40e_filter_input_set_init(struct i40e_pf *pf)
9685 {
9686         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9687         enum i40e_filter_pctype pctype;
9688         uint64_t input_set, inset_reg;
9689         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9690         int num, i;
9691         uint16_t flow_type;
9692
9693         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9694              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9695                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9696
9697                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9698                         continue;
9699
9700                 input_set = i40e_get_default_input_set(pctype);
9701
9702                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9703                                                    I40E_INSET_MASK_NUM_REG);
9704                 if (num < 0)
9705                         return;
9706                 if (pf->support_multi_driver && num > 0) {
9707                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9708                         return;
9709                 }
9710                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9711                                         input_set);
9712
9713                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9714                                       (uint32_t)(inset_reg & UINT32_MAX));
9715                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9716                                      (uint32_t)((inset_reg >>
9717                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9718                 if (!pf->support_multi_driver) {
9719                         i40e_check_write_global_reg(hw,
9720                                             I40E_GLQF_HASH_INSET(0, pctype),
9721                                             (uint32_t)(inset_reg & UINT32_MAX));
9722                         i40e_check_write_global_reg(hw,
9723                                              I40E_GLQF_HASH_INSET(1, pctype),
9724                                              (uint32_t)((inset_reg >>
9725                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9726
9727                         for (i = 0; i < num; i++) {
9728                                 i40e_check_write_global_reg(hw,
9729                                                     I40E_GLQF_FD_MSK(i, pctype),
9730                                                     mask_reg[i]);
9731                                 i40e_check_write_global_reg(hw,
9732                                                   I40E_GLQF_HASH_MSK(i, pctype),
9733                                                   mask_reg[i]);
9734                         }
9735                         /*clear unused mask registers of the pctype */
9736                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9737                                 i40e_check_write_global_reg(hw,
9738                                                     I40E_GLQF_FD_MSK(i, pctype),
9739                                                     0);
9740                                 i40e_check_write_global_reg(hw,
9741                                                   I40E_GLQF_HASH_MSK(i, pctype),
9742                                                   0);
9743                         }
9744                 } else {
9745                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9746                 }
9747                 I40E_WRITE_FLUSH(hw);
9748
9749                 /* store the default input set */
9750                 if (!pf->support_multi_driver)
9751                         pf->hash_input_set[pctype] = input_set;
9752                 pf->fdir.input_set[pctype] = input_set;
9753         }
9754 }
9755
9756 int
9757 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9758                          struct rte_eth_input_set_conf *conf)
9759 {
9760         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9761         enum i40e_filter_pctype pctype;
9762         uint64_t input_set, inset_reg = 0;
9763         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9764         int ret, i, num;
9765
9766         if (!conf) {
9767                 PMD_DRV_LOG(ERR, "Invalid pointer");
9768                 return -EFAULT;
9769         }
9770         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9771             conf->op != RTE_ETH_INPUT_SET_ADD) {
9772                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9773                 return -EINVAL;
9774         }
9775
9776         if (pf->support_multi_driver) {
9777                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9778                 return -ENOTSUP;
9779         }
9780
9781         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9782         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9783                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9784                 return -EINVAL;
9785         }
9786
9787         if (hw->mac.type == I40E_MAC_X722) {
9788                 /* get translated pctype value in fd pctype register */
9789                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9790                         I40E_GLQF_FD_PCTYPES((int)pctype));
9791         }
9792
9793         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9794                                    conf->inset_size);
9795         if (ret) {
9796                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9797                 return -EINVAL;
9798         }
9799
9800         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9801                 /* get inset value in register */
9802                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9803                 inset_reg <<= I40E_32_BIT_WIDTH;
9804                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9805                 input_set |= pf->hash_input_set[pctype];
9806         }
9807         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9808                                            I40E_INSET_MASK_NUM_REG);
9809         if (num < 0)
9810                 return -EINVAL;
9811
9812         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9813
9814         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9815                                     (uint32_t)(inset_reg & UINT32_MAX));
9816         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9817                                     (uint32_t)((inset_reg >>
9818                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9819
9820         for (i = 0; i < num; i++)
9821                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9822                                             mask_reg[i]);
9823         /*clear unused mask registers of the pctype */
9824         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9825                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9826                                             0);
9827         I40E_WRITE_FLUSH(hw);
9828
9829         pf->hash_input_set[pctype] = input_set;
9830         return 0;
9831 }
9832
9833 int
9834 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9835                          struct rte_eth_input_set_conf *conf)
9836 {
9837         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9838         enum i40e_filter_pctype pctype;
9839         uint64_t input_set, inset_reg = 0;
9840         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9841         int ret, i, num;
9842
9843         if (!hw || !conf) {
9844                 PMD_DRV_LOG(ERR, "Invalid pointer");
9845                 return -EFAULT;
9846         }
9847         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9848             conf->op != RTE_ETH_INPUT_SET_ADD) {
9849                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9850                 return -EINVAL;
9851         }
9852
9853         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9854
9855         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9856                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9857                 return -EINVAL;
9858         }
9859
9860         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9861                                    conf->inset_size);
9862         if (ret) {
9863                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9864                 return -EINVAL;
9865         }
9866
9867         /* get inset value in register */
9868         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9869         inset_reg <<= I40E_32_BIT_WIDTH;
9870         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9871
9872         /* Can not change the inset reg for flex payload for fdir,
9873          * it is done by writing I40E_PRTQF_FD_FLXINSET
9874          * in i40e_set_flex_mask_on_pctype.
9875          */
9876         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9877                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9878         else
9879                 input_set |= pf->fdir.input_set[pctype];
9880         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9881                                            I40E_INSET_MASK_NUM_REG);
9882         if (num < 0)
9883                 return -EINVAL;
9884         if (pf->support_multi_driver && num > 0) {
9885                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9886                 return -ENOTSUP;
9887         }
9888
9889         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9890
9891         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9892                               (uint32_t)(inset_reg & UINT32_MAX));
9893         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9894                              (uint32_t)((inset_reg >>
9895                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9896
9897         if (!pf->support_multi_driver) {
9898                 for (i = 0; i < num; i++)
9899                         i40e_check_write_global_reg(hw,
9900                                                     I40E_GLQF_FD_MSK(i, pctype),
9901                                                     mask_reg[i]);
9902                 /*clear unused mask registers of the pctype */
9903                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9904                         i40e_check_write_global_reg(hw,
9905                                                     I40E_GLQF_FD_MSK(i, pctype),
9906                                                     0);
9907         } else {
9908                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9909         }
9910         I40E_WRITE_FLUSH(hw);
9911
9912         pf->fdir.input_set[pctype] = input_set;
9913         return 0;
9914 }
9915
9916 static int
9917 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9918 {
9919         int ret = 0;
9920
9921         if (!hw || !info) {
9922                 PMD_DRV_LOG(ERR, "Invalid pointer");
9923                 return -EFAULT;
9924         }
9925
9926         switch (info->info_type) {
9927         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9928                 i40e_get_symmetric_hash_enable_per_port(hw,
9929                                         &(info->info.enable));
9930                 break;
9931         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9932                 ret = i40e_get_hash_filter_global_config(hw,
9933                                 &(info->info.global_conf));
9934                 break;
9935         default:
9936                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9937                                                         info->info_type);
9938                 ret = -EINVAL;
9939                 break;
9940         }
9941
9942         return ret;
9943 }
9944
9945 static int
9946 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9947 {
9948         int ret = 0;
9949
9950         if (!hw || !info) {
9951                 PMD_DRV_LOG(ERR, "Invalid pointer");
9952                 return -EFAULT;
9953         }
9954
9955         switch (info->info_type) {
9956         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9957                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9958                 break;
9959         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9960                 ret = i40e_set_hash_filter_global_config(hw,
9961                                 &(info->info.global_conf));
9962                 break;
9963         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9964                 ret = i40e_hash_filter_inset_select(hw,
9965                                                &(info->info.input_set_conf));
9966                 break;
9967
9968         default:
9969                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9970                                                         info->info_type);
9971                 ret = -EINVAL;
9972                 break;
9973         }
9974
9975         return ret;
9976 }
9977
9978 /* Operations for hash function */
9979 static int
9980 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9981                       enum rte_filter_op filter_op,
9982                       void *arg)
9983 {
9984         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9985         int ret = 0;
9986
9987         switch (filter_op) {
9988         case RTE_ETH_FILTER_NOP:
9989                 break;
9990         case RTE_ETH_FILTER_GET:
9991                 ret = i40e_hash_filter_get(hw,
9992                         (struct rte_eth_hash_filter_info *)arg);
9993                 break;
9994         case RTE_ETH_FILTER_SET:
9995                 ret = i40e_hash_filter_set(hw,
9996                         (struct rte_eth_hash_filter_info *)arg);
9997                 break;
9998         default:
9999                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10000                                                                 filter_op);
10001                 ret = -ENOTSUP;
10002                 break;
10003         }
10004
10005         return ret;
10006 }
10007
10008 /* Convert ethertype filter structure */
10009 static int
10010 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10011                               struct i40e_ethertype_filter *filter)
10012 {
10013         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10014                 RTE_ETHER_ADDR_LEN);
10015         filter->input.ether_type = input->ether_type;
10016         filter->flags = input->flags;
10017         filter->queue = input->queue;
10018
10019         return 0;
10020 }
10021
10022 /* Check if there exists the ehtertype filter */
10023 struct i40e_ethertype_filter *
10024 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10025                                 const struct i40e_ethertype_filter_input *input)
10026 {
10027         int ret;
10028
10029         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10030         if (ret < 0)
10031                 return NULL;
10032
10033         return ethertype_rule->hash_map[ret];
10034 }
10035
10036 /* Add ethertype filter in SW list */
10037 static int
10038 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10039                                 struct i40e_ethertype_filter *filter)
10040 {
10041         struct i40e_ethertype_rule *rule = &pf->ethertype;
10042         int ret;
10043
10044         ret = rte_hash_add_key(rule->hash_table, &filter->input);
10045         if (ret < 0) {
10046                 PMD_DRV_LOG(ERR,
10047                             "Failed to insert ethertype filter"
10048                             " to hash table %d!",
10049                             ret);
10050                 return ret;
10051         }
10052         rule->hash_map[ret] = filter;
10053
10054         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10055
10056         return 0;
10057 }
10058
10059 /* Delete ethertype filter in SW list */
10060 int
10061 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10062                              struct i40e_ethertype_filter_input *input)
10063 {
10064         struct i40e_ethertype_rule *rule = &pf->ethertype;
10065         struct i40e_ethertype_filter *filter;
10066         int ret;
10067
10068         ret = rte_hash_del_key(rule->hash_table, input);
10069         if (ret < 0) {
10070                 PMD_DRV_LOG(ERR,
10071                             "Failed to delete ethertype filter"
10072                             " to hash table %d!",
10073                             ret);
10074                 return ret;
10075         }
10076         filter = rule->hash_map[ret];
10077         rule->hash_map[ret] = NULL;
10078
10079         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10080         rte_free(filter);
10081
10082         return 0;
10083 }
10084
10085 /*
10086  * Configure ethertype filter, which can director packet by filtering
10087  * with mac address and ether_type or only ether_type
10088  */
10089 int
10090 i40e_ethertype_filter_set(struct i40e_pf *pf,
10091                         struct rte_eth_ethertype_filter *filter,
10092                         bool add)
10093 {
10094         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10095         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10096         struct i40e_ethertype_filter *ethertype_filter, *node;
10097         struct i40e_ethertype_filter check_filter;
10098         struct i40e_control_filter_stats stats;
10099         uint16_t flags = 0;
10100         int ret;
10101
10102         if (filter->queue >= pf->dev_data->nb_rx_queues) {
10103                 PMD_DRV_LOG(ERR, "Invalid queue ID");
10104                 return -EINVAL;
10105         }
10106         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10107                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10108                 PMD_DRV_LOG(ERR,
10109                         "unsupported ether_type(0x%04x) in control packet filter.",
10110                         filter->ether_type);
10111                 return -EINVAL;
10112         }
10113         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10114                 PMD_DRV_LOG(WARNING,
10115                         "filter vlan ether_type in first tag is not supported.");
10116
10117         /* Check if there is the filter in SW list */
10118         memset(&check_filter, 0, sizeof(check_filter));
10119         i40e_ethertype_filter_convert(filter, &check_filter);
10120         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10121                                                &check_filter.input);
10122         if (add && node) {
10123                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10124                 return -EINVAL;
10125         }
10126
10127         if (!add && !node) {
10128                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10129                 return -EINVAL;
10130         }
10131
10132         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10133                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10134         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10135                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10136         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10137
10138         memset(&stats, 0, sizeof(stats));
10139         ret = i40e_aq_add_rem_control_packet_filter(hw,
10140                         filter->mac_addr.addr_bytes,
10141                         filter->ether_type, flags,
10142                         pf->main_vsi->seid,
10143                         filter->queue, add, &stats, NULL);
10144
10145         PMD_DRV_LOG(INFO,
10146                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10147                 ret, stats.mac_etype_used, stats.etype_used,
10148                 stats.mac_etype_free, stats.etype_free);
10149         if (ret < 0)
10150                 return -ENOSYS;
10151
10152         /* Add or delete a filter in SW list */
10153         if (add) {
10154                 ethertype_filter = rte_zmalloc("ethertype_filter",
10155                                        sizeof(*ethertype_filter), 0);
10156                 if (ethertype_filter == NULL) {
10157                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10158                         return -ENOMEM;
10159                 }
10160
10161                 rte_memcpy(ethertype_filter, &check_filter,
10162                            sizeof(check_filter));
10163                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10164                 if (ret < 0)
10165                         rte_free(ethertype_filter);
10166         } else {
10167                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10168         }
10169
10170         return ret;
10171 }
10172
10173 /*
10174  * Handle operations for ethertype filter.
10175  */
10176 static int
10177 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10178                                 enum rte_filter_op filter_op,
10179                                 void *arg)
10180 {
10181         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10182         int ret = 0;
10183
10184         if (filter_op == RTE_ETH_FILTER_NOP)
10185                 return ret;
10186
10187         if (arg == NULL) {
10188                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10189                             filter_op);
10190                 return -EINVAL;
10191         }
10192
10193         switch (filter_op) {
10194         case RTE_ETH_FILTER_ADD:
10195                 ret = i40e_ethertype_filter_set(pf,
10196                         (struct rte_eth_ethertype_filter *)arg,
10197                         TRUE);
10198                 break;
10199         case RTE_ETH_FILTER_DELETE:
10200                 ret = i40e_ethertype_filter_set(pf,
10201                         (struct rte_eth_ethertype_filter *)arg,
10202                         FALSE);
10203                 break;
10204         default:
10205                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10206                 ret = -ENOSYS;
10207                 break;
10208         }
10209         return ret;
10210 }
10211
10212 static int
10213 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10214                      enum rte_filter_type filter_type,
10215                      enum rte_filter_op filter_op,
10216                      void *arg)
10217 {
10218         int ret = 0;
10219
10220         if (dev == NULL)
10221                 return -EINVAL;
10222
10223         switch (filter_type) {
10224         case RTE_ETH_FILTER_NONE:
10225                 /* For global configuration */
10226                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10227                 break;
10228         case RTE_ETH_FILTER_HASH:
10229                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10230                 break;
10231         case RTE_ETH_FILTER_MACVLAN:
10232                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10233                 break;
10234         case RTE_ETH_FILTER_ETHERTYPE:
10235                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10236                 break;
10237         case RTE_ETH_FILTER_TUNNEL:
10238                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10239                 break;
10240         case RTE_ETH_FILTER_FDIR:
10241                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10242                 break;
10243         case RTE_ETH_FILTER_GENERIC:
10244                 if (filter_op != RTE_ETH_FILTER_GET)
10245                         return -EINVAL;
10246                 *(const void **)arg = &i40e_flow_ops;
10247                 break;
10248         default:
10249                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10250                                                         filter_type);
10251                 ret = -EINVAL;
10252                 break;
10253         }
10254
10255         return ret;
10256 }
10257
10258 /*
10259  * Check and enable Extended Tag.
10260  * Enabling Extended Tag is important for 40G performance.
10261  */
10262 static void
10263 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10264 {
10265         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10266         uint32_t buf = 0;
10267         int ret;
10268
10269         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10270                                       PCI_DEV_CAP_REG);
10271         if (ret < 0) {
10272                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10273                             PCI_DEV_CAP_REG);
10274                 return;
10275         }
10276         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10277                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10278                 return;
10279         }
10280
10281         buf = 0;
10282         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10283                                       PCI_DEV_CTRL_REG);
10284         if (ret < 0) {
10285                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10286                             PCI_DEV_CTRL_REG);
10287                 return;
10288         }
10289         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10290                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10291                 return;
10292         }
10293         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10294         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10295                                        PCI_DEV_CTRL_REG);
10296         if (ret < 0) {
10297                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10298                             PCI_DEV_CTRL_REG);
10299                 return;
10300         }
10301 }
10302
10303 /*
10304  * As some registers wouldn't be reset unless a global hardware reset,
10305  * hardware initialization is needed to put those registers into an
10306  * expected initial state.
10307  */
10308 static void
10309 i40e_hw_init(struct rte_eth_dev *dev)
10310 {
10311         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10312
10313         i40e_enable_extended_tag(dev);
10314
10315         /* clear the PF Queue Filter control register */
10316         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10317
10318         /* Disable symmetric hash per port */
10319         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10320 }
10321
10322 /*
10323  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10324  * however this function will return only one highest pctype index,
10325  * which is not quite correct. This is known problem of i40e driver
10326  * and needs to be fixed later.
10327  */
10328 enum i40e_filter_pctype
10329 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10330 {
10331         int i;
10332         uint64_t pctype_mask;
10333
10334         if (flow_type < I40E_FLOW_TYPE_MAX) {
10335                 pctype_mask = adapter->pctypes_tbl[flow_type];
10336                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10337                         if (pctype_mask & (1ULL << i))
10338                                 return (enum i40e_filter_pctype)i;
10339                 }
10340         }
10341         return I40E_FILTER_PCTYPE_INVALID;
10342 }
10343
10344 uint16_t
10345 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10346                         enum i40e_filter_pctype pctype)
10347 {
10348         uint16_t flowtype;
10349         uint64_t pctype_mask = 1ULL << pctype;
10350
10351         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10352              flowtype++) {
10353                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10354                         return flowtype;
10355         }
10356
10357         return RTE_ETH_FLOW_UNKNOWN;
10358 }
10359
10360 /*
10361  * On X710, performance number is far from the expectation on recent firmware
10362  * versions; on XL710, performance number is also far from the expectation on
10363  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10364  * mode is enabled and port MAC address is equal to the packet destination MAC
10365  * address. The fix for this issue may not be integrated in the following
10366  * firmware version. So the workaround in software driver is needed. It needs
10367  * to modify the initial values of 3 internal only registers for both X710 and
10368  * XL710. Note that the values for X710 or XL710 could be different, and the
10369  * workaround can be removed when it is fixed in firmware in the future.
10370  */
10371
10372 /* For both X710 and XL710 */
10373 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10374 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10375 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10376
10377 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10378 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10379
10380 /* For X722 */
10381 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10382 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10383
10384 /* For X710 */
10385 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10386 /* For XL710 */
10387 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10388 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10389
10390 /*
10391  * GL_SWR_PM_UP_THR:
10392  * The value is not impacted from the link speed, its value is set according
10393  * to the total number of ports for a better pipe-monitor configuration.
10394  */
10395 static bool
10396 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10397 {
10398 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10399                 .device_id = (dev),   \
10400                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10401
10402 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10403                 .device_id = (dev),   \
10404                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10405
10406         static const struct {
10407                 uint16_t device_id;
10408                 uint32_t val;
10409         } swr_pm_table[] = {
10410                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10411                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10412                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10413                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10414
10415                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10416                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10417                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10418                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10419                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10420                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10421                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10422         };
10423         uint32_t i;
10424
10425         if (value == NULL) {
10426                 PMD_DRV_LOG(ERR, "value is NULL");
10427                 return false;
10428         }
10429
10430         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10431                 if (hw->device_id == swr_pm_table[i].device_id) {
10432                         *value = swr_pm_table[i].val;
10433
10434                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10435                                     "value - 0x%08x",
10436                                     hw->device_id, *value);
10437                         return true;
10438                 }
10439         }
10440
10441         return false;
10442 }
10443
10444 static int
10445 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10446 {
10447         enum i40e_status_code status;
10448         struct i40e_aq_get_phy_abilities_resp phy_ab;
10449         int ret = -ENOTSUP;
10450         int retries = 0;
10451
10452         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10453                                               NULL);
10454
10455         while (status) {
10456                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10457                         status);
10458                 retries++;
10459                 rte_delay_us(100000);
10460                 if  (retries < 5)
10461                         status = i40e_aq_get_phy_capabilities(hw, false,
10462                                         true, &phy_ab, NULL);
10463                 else
10464                         return ret;
10465         }
10466         return 0;
10467 }
10468
10469 static void
10470 i40e_configure_registers(struct i40e_hw *hw)
10471 {
10472         static struct {
10473                 uint32_t addr;
10474                 uint64_t val;
10475         } reg_table[] = {
10476                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10477                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10478                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10479         };
10480         uint64_t reg;
10481         uint32_t i;
10482         int ret;
10483
10484         for (i = 0; i < RTE_DIM(reg_table); i++) {
10485                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10486                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10487                                 reg_table[i].val =
10488                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10489                         else /* For X710/XL710/XXV710 */
10490                                 if (hw->aq.fw_maj_ver < 6)
10491                                         reg_table[i].val =
10492                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10493                                 else
10494                                         reg_table[i].val =
10495                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10496                 }
10497
10498                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10499                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10500                                 reg_table[i].val =
10501                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10502                         else /* For X710/XL710/XXV710 */
10503                                 reg_table[i].val =
10504                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10505                 }
10506
10507                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10508                         uint32_t cfg_val;
10509
10510                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10511                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10512                                             "GL_SWR_PM_UP_THR value fixup",
10513                                             hw->device_id);
10514                                 continue;
10515                         }
10516
10517                         reg_table[i].val = cfg_val;
10518                 }
10519
10520                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10521                                                         &reg, NULL);
10522                 if (ret < 0) {
10523                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10524                                                         reg_table[i].addr);
10525                         break;
10526                 }
10527                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10528                                                 reg_table[i].addr, reg);
10529                 if (reg == reg_table[i].val)
10530                         continue;
10531
10532                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10533                                                 reg_table[i].val, NULL);
10534                 if (ret < 0) {
10535                         PMD_DRV_LOG(ERR,
10536                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10537                                 reg_table[i].val, reg_table[i].addr);
10538                         break;
10539                 }
10540                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10541                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10542         }
10543 }
10544
10545 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10546 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10547 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10548 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10549 static int
10550 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10551 {
10552         uint32_t reg;
10553         int ret;
10554
10555         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10556                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10557                 return -EINVAL;
10558         }
10559
10560         /* Configure for double VLAN RX stripping */
10561         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10562         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10563                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10564                 ret = i40e_aq_debug_write_register(hw,
10565                                                    I40E_VSI_TSR(vsi->vsi_id),
10566                                                    reg, NULL);
10567                 if (ret < 0) {
10568                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10569                                     vsi->vsi_id);
10570                         return I40E_ERR_CONFIG;
10571                 }
10572         }
10573
10574         /* Configure for double VLAN TX insertion */
10575         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10576         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10577                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10578                 ret = i40e_aq_debug_write_register(hw,
10579                                                    I40E_VSI_L2TAGSTXVALID(
10580                                                    vsi->vsi_id), reg, NULL);
10581                 if (ret < 0) {
10582                         PMD_DRV_LOG(ERR,
10583                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10584                                 vsi->vsi_id);
10585                         return I40E_ERR_CONFIG;
10586                 }
10587         }
10588
10589         return 0;
10590 }
10591
10592 /**
10593  * i40e_aq_add_mirror_rule
10594  * @hw: pointer to the hardware structure
10595  * @seid: VEB seid to add mirror rule to
10596  * @dst_id: destination vsi seid
10597  * @entries: Buffer which contains the entities to be mirrored
10598  * @count: number of entities contained in the buffer
10599  * @rule_id:the rule_id of the rule to be added
10600  *
10601  * Add a mirror rule for a given veb.
10602  *
10603  **/
10604 static enum i40e_status_code
10605 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10606                         uint16_t seid, uint16_t dst_id,
10607                         uint16_t rule_type, uint16_t *entries,
10608                         uint16_t count, uint16_t *rule_id)
10609 {
10610         struct i40e_aq_desc desc;
10611         struct i40e_aqc_add_delete_mirror_rule cmd;
10612         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10613                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10614                 &desc.params.raw;
10615         uint16_t buff_len;
10616         enum i40e_status_code status;
10617
10618         i40e_fill_default_direct_cmd_desc(&desc,
10619                                           i40e_aqc_opc_add_mirror_rule);
10620         memset(&cmd, 0, sizeof(cmd));
10621
10622         buff_len = sizeof(uint16_t) * count;
10623         desc.datalen = rte_cpu_to_le_16(buff_len);
10624         if (buff_len > 0)
10625                 desc.flags |= rte_cpu_to_le_16(
10626                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10627         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10628                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10629         cmd.num_entries = rte_cpu_to_le_16(count);
10630         cmd.seid = rte_cpu_to_le_16(seid);
10631         cmd.destination = rte_cpu_to_le_16(dst_id);
10632
10633         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10634         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10635         PMD_DRV_LOG(INFO,
10636                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10637                 hw->aq.asq_last_status, resp->rule_id,
10638                 resp->mirror_rules_used, resp->mirror_rules_free);
10639         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10640
10641         return status;
10642 }
10643
10644 /**
10645  * i40e_aq_del_mirror_rule
10646  * @hw: pointer to the hardware structure
10647  * @seid: VEB seid to add mirror rule to
10648  * @entries: Buffer which contains the entities to be mirrored
10649  * @count: number of entities contained in the buffer
10650  * @rule_id:the rule_id of the rule to be delete
10651  *
10652  * Delete a mirror rule for a given veb.
10653  *
10654  **/
10655 static enum i40e_status_code
10656 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10657                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10658                 uint16_t count, uint16_t rule_id)
10659 {
10660         struct i40e_aq_desc desc;
10661         struct i40e_aqc_add_delete_mirror_rule cmd;
10662         uint16_t buff_len = 0;
10663         enum i40e_status_code status;
10664         void *buff = NULL;
10665
10666         i40e_fill_default_direct_cmd_desc(&desc,
10667                                           i40e_aqc_opc_delete_mirror_rule);
10668         memset(&cmd, 0, sizeof(cmd));
10669         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10670                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10671                                                           I40E_AQ_FLAG_RD));
10672                 cmd.num_entries = count;
10673                 buff_len = sizeof(uint16_t) * count;
10674                 desc.datalen = rte_cpu_to_le_16(buff_len);
10675                 buff = (void *)entries;
10676         } else
10677                 /* rule id is filled in destination field for deleting mirror rule */
10678                 cmd.destination = rte_cpu_to_le_16(rule_id);
10679
10680         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10681                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10682         cmd.seid = rte_cpu_to_le_16(seid);
10683
10684         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10685         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10686
10687         return status;
10688 }
10689
10690 /**
10691  * i40e_mirror_rule_set
10692  * @dev: pointer to the hardware structure
10693  * @mirror_conf: mirror rule info
10694  * @sw_id: mirror rule's sw_id
10695  * @on: enable/disable
10696  *
10697  * set a mirror rule.
10698  *
10699  **/
10700 static int
10701 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10702                         struct rte_eth_mirror_conf *mirror_conf,
10703                         uint8_t sw_id, uint8_t on)
10704 {
10705         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10706         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10707         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10708         struct i40e_mirror_rule *parent = NULL;
10709         uint16_t seid, dst_seid, rule_id;
10710         uint16_t i, j = 0;
10711         int ret;
10712
10713         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10714
10715         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10716                 PMD_DRV_LOG(ERR,
10717                         "mirror rule can not be configured without veb or vfs.");
10718                 return -ENOSYS;
10719         }
10720         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10721                 PMD_DRV_LOG(ERR, "mirror table is full.");
10722                 return -ENOSPC;
10723         }
10724         if (mirror_conf->dst_pool > pf->vf_num) {
10725                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10726                                  mirror_conf->dst_pool);
10727                 return -EINVAL;
10728         }
10729
10730         seid = pf->main_vsi->veb->seid;
10731
10732         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10733                 if (sw_id <= it->index) {
10734                         mirr_rule = it;
10735                         break;
10736                 }
10737                 parent = it;
10738         }
10739         if (mirr_rule && sw_id == mirr_rule->index) {
10740                 if (on) {
10741                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10742                         return -EEXIST;
10743                 } else {
10744                         ret = i40e_aq_del_mirror_rule(hw, seid,
10745                                         mirr_rule->rule_type,
10746                                         mirr_rule->entries,
10747                                         mirr_rule->num_entries, mirr_rule->id);
10748                         if (ret < 0) {
10749                                 PMD_DRV_LOG(ERR,
10750                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10751                                         ret, hw->aq.asq_last_status);
10752                                 return -ENOSYS;
10753                         }
10754                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10755                         rte_free(mirr_rule);
10756                         pf->nb_mirror_rule--;
10757                         return 0;
10758                 }
10759         } else if (!on) {
10760                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10761                 return -ENOENT;
10762         }
10763
10764         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10765                                 sizeof(struct i40e_mirror_rule) , 0);
10766         if (!mirr_rule) {
10767                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10768                 return I40E_ERR_NO_MEMORY;
10769         }
10770         switch (mirror_conf->rule_type) {
10771         case ETH_MIRROR_VLAN:
10772                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10773                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10774                                 mirr_rule->entries[j] =
10775                                         mirror_conf->vlan.vlan_id[i];
10776                                 j++;
10777                         }
10778                 }
10779                 if (j == 0) {
10780                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10781                         rte_free(mirr_rule);
10782                         return -EINVAL;
10783                 }
10784                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10785                 break;
10786         case ETH_MIRROR_VIRTUAL_POOL_UP:
10787         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10788                 /* check if the specified pool bit is out of range */
10789                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10790                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10791                         rte_free(mirr_rule);
10792                         return -EINVAL;
10793                 }
10794                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10795                         if (mirror_conf->pool_mask & (1ULL << i)) {
10796                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10797                                 j++;
10798                         }
10799                 }
10800                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10801                         /* add pf vsi to entries */
10802                         mirr_rule->entries[j] = pf->main_vsi_seid;
10803                         j++;
10804                 }
10805                 if (j == 0) {
10806                         PMD_DRV_LOG(ERR, "pool is not specified.");
10807                         rte_free(mirr_rule);
10808                         return -EINVAL;
10809                 }
10810                 /* egress and ingress in aq commands means from switch but not port */
10811                 mirr_rule->rule_type =
10812                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10813                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10814                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10815                 break;
10816         case ETH_MIRROR_UPLINK_PORT:
10817                 /* egress and ingress in aq commands means from switch but not port*/
10818                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10819                 break;
10820         case ETH_MIRROR_DOWNLINK_PORT:
10821                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10822                 break;
10823         default:
10824                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10825                         mirror_conf->rule_type);
10826                 rte_free(mirr_rule);
10827                 return -EINVAL;
10828         }
10829
10830         /* If the dst_pool is equal to vf_num, consider it as PF */
10831         if (mirror_conf->dst_pool == pf->vf_num)
10832                 dst_seid = pf->main_vsi_seid;
10833         else
10834                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10835
10836         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10837                                       mirr_rule->rule_type, mirr_rule->entries,
10838                                       j, &rule_id);
10839         if (ret < 0) {
10840                 PMD_DRV_LOG(ERR,
10841                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10842                         ret, hw->aq.asq_last_status);
10843                 rte_free(mirr_rule);
10844                 return -ENOSYS;
10845         }
10846
10847         mirr_rule->index = sw_id;
10848         mirr_rule->num_entries = j;
10849         mirr_rule->id = rule_id;
10850         mirr_rule->dst_vsi_seid = dst_seid;
10851
10852         if (parent)
10853                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10854         else
10855                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10856
10857         pf->nb_mirror_rule++;
10858         return 0;
10859 }
10860
10861 /**
10862  * i40e_mirror_rule_reset
10863  * @dev: pointer to the device
10864  * @sw_id: mirror rule's sw_id
10865  *
10866  * reset a mirror rule.
10867  *
10868  **/
10869 static int
10870 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10871 {
10872         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10873         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10874         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10875         uint16_t seid;
10876         int ret;
10877
10878         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10879
10880         seid = pf->main_vsi->veb->seid;
10881
10882         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10883                 if (sw_id == it->index) {
10884                         mirr_rule = it;
10885                         break;
10886                 }
10887         }
10888         if (mirr_rule) {
10889                 ret = i40e_aq_del_mirror_rule(hw, seid,
10890                                 mirr_rule->rule_type,
10891                                 mirr_rule->entries,
10892                                 mirr_rule->num_entries, mirr_rule->id);
10893                 if (ret < 0) {
10894                         PMD_DRV_LOG(ERR,
10895                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10896                                 ret, hw->aq.asq_last_status);
10897                         return -ENOSYS;
10898                 }
10899                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10900                 rte_free(mirr_rule);
10901                 pf->nb_mirror_rule--;
10902         } else {
10903                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10904                 return -ENOENT;
10905         }
10906         return 0;
10907 }
10908
10909 static uint64_t
10910 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10911 {
10912         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10913         uint64_t systim_cycles;
10914
10915         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10916         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10917                         << 32;
10918
10919         return systim_cycles;
10920 }
10921
10922 static uint64_t
10923 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10924 {
10925         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10926         uint64_t rx_tstamp;
10927
10928         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10929         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10930                         << 32;
10931
10932         return rx_tstamp;
10933 }
10934
10935 static uint64_t
10936 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10937 {
10938         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10939         uint64_t tx_tstamp;
10940
10941         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10942         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10943                         << 32;
10944
10945         return tx_tstamp;
10946 }
10947
10948 static void
10949 i40e_start_timecounters(struct rte_eth_dev *dev)
10950 {
10951         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10952         struct i40e_adapter *adapter = dev->data->dev_private;
10953         struct rte_eth_link link;
10954         uint32_t tsync_inc_l;
10955         uint32_t tsync_inc_h;
10956
10957         /* Get current link speed. */
10958         i40e_dev_link_update(dev, 1);
10959         rte_eth_linkstatus_get(dev, &link);
10960
10961         switch (link.link_speed) {
10962         case ETH_SPEED_NUM_40G:
10963         case ETH_SPEED_NUM_25G:
10964                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10965                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10966                 break;
10967         case ETH_SPEED_NUM_10G:
10968                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10969                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10970                 break;
10971         case ETH_SPEED_NUM_1G:
10972                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10973                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10974                 break;
10975         default:
10976                 tsync_inc_l = 0x0;
10977                 tsync_inc_h = 0x0;
10978         }
10979
10980         /* Set the timesync increment value. */
10981         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10982         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10983
10984         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10985         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10986         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10987
10988         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10989         adapter->systime_tc.cc_shift = 0;
10990         adapter->systime_tc.nsec_mask = 0;
10991
10992         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10993         adapter->rx_tstamp_tc.cc_shift = 0;
10994         adapter->rx_tstamp_tc.nsec_mask = 0;
10995
10996         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10997         adapter->tx_tstamp_tc.cc_shift = 0;
10998         adapter->tx_tstamp_tc.nsec_mask = 0;
10999 }
11000
11001 static int
11002 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11003 {
11004         struct i40e_adapter *adapter = dev->data->dev_private;
11005
11006         adapter->systime_tc.nsec += delta;
11007         adapter->rx_tstamp_tc.nsec += delta;
11008         adapter->tx_tstamp_tc.nsec += delta;
11009
11010         return 0;
11011 }
11012
11013 static int
11014 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11015 {
11016         uint64_t ns;
11017         struct i40e_adapter *adapter = dev->data->dev_private;
11018
11019         ns = rte_timespec_to_ns(ts);
11020
11021         /* Set the timecounters to a new value. */
11022         adapter->systime_tc.nsec = ns;
11023         adapter->rx_tstamp_tc.nsec = ns;
11024         adapter->tx_tstamp_tc.nsec = ns;
11025
11026         return 0;
11027 }
11028
11029 static int
11030 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11031 {
11032         uint64_t ns, systime_cycles;
11033         struct i40e_adapter *adapter = dev->data->dev_private;
11034
11035         systime_cycles = i40e_read_systime_cyclecounter(dev);
11036         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11037         *ts = rte_ns_to_timespec(ns);
11038
11039         return 0;
11040 }
11041
11042 static int
11043 i40e_timesync_enable(struct rte_eth_dev *dev)
11044 {
11045         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11046         uint32_t tsync_ctl_l;
11047         uint32_t tsync_ctl_h;
11048
11049         /* Stop the timesync system time. */
11050         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11051         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11052         /* Reset the timesync system time value. */
11053         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11054         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11055
11056         i40e_start_timecounters(dev);
11057
11058         /* Clear timesync registers. */
11059         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11060         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11061         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11062         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11063         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11064         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11065
11066         /* Enable timestamping of PTP packets. */
11067         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11068         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11069
11070         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11071         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11072         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11073
11074         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11075         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11076
11077         return 0;
11078 }
11079
11080 static int
11081 i40e_timesync_disable(struct rte_eth_dev *dev)
11082 {
11083         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11084         uint32_t tsync_ctl_l;
11085         uint32_t tsync_ctl_h;
11086
11087         /* Disable timestamping of transmitted PTP packets. */
11088         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11089         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11090
11091         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11092         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11093
11094         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11095         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11096
11097         /* Reset the timesync increment value. */
11098         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11099         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11100
11101         return 0;
11102 }
11103
11104 static int
11105 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11106                                 struct timespec *timestamp, uint32_t flags)
11107 {
11108         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11109         struct i40e_adapter *adapter = dev->data->dev_private;
11110         uint32_t sync_status;
11111         uint32_t index = flags & 0x03;
11112         uint64_t rx_tstamp_cycles;
11113         uint64_t ns;
11114
11115         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11116         if ((sync_status & (1 << index)) == 0)
11117                 return -EINVAL;
11118
11119         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11120         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11121         *timestamp = rte_ns_to_timespec(ns);
11122
11123         return 0;
11124 }
11125
11126 static int
11127 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11128                                 struct timespec *timestamp)
11129 {
11130         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11131         struct i40e_adapter *adapter = dev->data->dev_private;
11132         uint32_t sync_status;
11133         uint64_t tx_tstamp_cycles;
11134         uint64_t ns;
11135
11136         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11137         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11138                 return -EINVAL;
11139
11140         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11141         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11142         *timestamp = rte_ns_to_timespec(ns);
11143
11144         return 0;
11145 }
11146
11147 /*
11148  * i40e_parse_dcb_configure - parse dcb configure from user
11149  * @dev: the device being configured
11150  * @dcb_cfg: pointer of the result of parse
11151  * @*tc_map: bit map of enabled traffic classes
11152  *
11153  * Returns 0 on success, negative value on failure
11154  */
11155 static int
11156 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11157                          struct i40e_dcbx_config *dcb_cfg,
11158                          uint8_t *tc_map)
11159 {
11160         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11161         uint8_t i, tc_bw, bw_lf;
11162
11163         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11164
11165         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11166         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11167                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11168                 return -EINVAL;
11169         }
11170
11171         /* assume each tc has the same bw */
11172         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11173         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11174                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11175         /* to ensure the sum of tcbw is equal to 100 */
11176         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11177         for (i = 0; i < bw_lf; i++)
11178                 dcb_cfg->etscfg.tcbwtable[i]++;
11179
11180         /* assume each tc has the same Transmission Selection Algorithm */
11181         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11182                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11183
11184         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11185                 dcb_cfg->etscfg.prioritytable[i] =
11186                                 dcb_rx_conf->dcb_tc[i];
11187
11188         /* FW needs one App to configure HW */
11189         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11190         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11191         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11192         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11193
11194         if (dcb_rx_conf->nb_tcs == 0)
11195                 *tc_map = 1; /* tc0 only */
11196         else
11197                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11198
11199         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11200                 dcb_cfg->pfc.willing = 0;
11201                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11202                 dcb_cfg->pfc.pfcenable = *tc_map;
11203         }
11204         return 0;
11205 }
11206
11207
11208 static enum i40e_status_code
11209 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11210                               struct i40e_aqc_vsi_properties_data *info,
11211                               uint8_t enabled_tcmap)
11212 {
11213         enum i40e_status_code ret;
11214         int i, total_tc = 0;
11215         uint16_t qpnum_per_tc, bsf, qp_idx;
11216         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11217         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11218         uint16_t used_queues;
11219
11220         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11221         if (ret != I40E_SUCCESS)
11222                 return ret;
11223
11224         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11225                 if (enabled_tcmap & (1 << i))
11226                         total_tc++;
11227         }
11228         if (total_tc == 0)
11229                 total_tc = 1;
11230         vsi->enabled_tc = enabled_tcmap;
11231
11232         /* different VSI has different queues assigned */
11233         if (vsi->type == I40E_VSI_MAIN)
11234                 used_queues = dev_data->nb_rx_queues -
11235                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11236         else if (vsi->type == I40E_VSI_VMDQ2)
11237                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11238         else {
11239                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11240                 return I40E_ERR_NO_AVAILABLE_VSI;
11241         }
11242
11243         qpnum_per_tc = used_queues / total_tc;
11244         /* Number of queues per enabled TC */
11245         if (qpnum_per_tc == 0) {
11246                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11247                 return I40E_ERR_INVALID_QP_ID;
11248         }
11249         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11250                                 I40E_MAX_Q_PER_TC);
11251         bsf = rte_bsf32(qpnum_per_tc);
11252
11253         /**
11254          * Configure TC and queue mapping parameters, for enabled TC,
11255          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11256          * default queue will serve it.
11257          */
11258         qp_idx = 0;
11259         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11260                 if (vsi->enabled_tc & (1 << i)) {
11261                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11262                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11263                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11264                         qp_idx += qpnum_per_tc;
11265                 } else
11266                         info->tc_mapping[i] = 0;
11267         }
11268
11269         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11270         if (vsi->type == I40E_VSI_SRIOV) {
11271                 info->mapping_flags |=
11272                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11273                 for (i = 0; i < vsi->nb_qps; i++)
11274                         info->queue_mapping[i] =
11275                                 rte_cpu_to_le_16(vsi->base_queue + i);
11276         } else {
11277                 info->mapping_flags |=
11278                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11279                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11280         }
11281         info->valid_sections |=
11282                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11283
11284         return I40E_SUCCESS;
11285 }
11286
11287 /*
11288  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11289  * @veb: VEB to be configured
11290  * @tc_map: enabled TC bitmap
11291  *
11292  * Returns 0 on success, negative value on failure
11293  */
11294 static enum i40e_status_code
11295 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11296 {
11297         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11298         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11299         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11300         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11301         enum i40e_status_code ret = I40E_SUCCESS;
11302         int i;
11303         uint32_t bw_max;
11304
11305         /* Check if enabled_tc is same as existing or new TCs */
11306         if (veb->enabled_tc == tc_map)
11307                 return ret;
11308
11309         /* configure tc bandwidth */
11310         memset(&veb_bw, 0, sizeof(veb_bw));
11311         veb_bw.tc_valid_bits = tc_map;
11312         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11313         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11314                 if (tc_map & BIT_ULL(i))
11315                         veb_bw.tc_bw_share_credits[i] = 1;
11316         }
11317         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11318                                                    &veb_bw, NULL);
11319         if (ret) {
11320                 PMD_INIT_LOG(ERR,
11321                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11322                         hw->aq.asq_last_status);
11323                 return ret;
11324         }
11325
11326         memset(&ets_query, 0, sizeof(ets_query));
11327         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11328                                                    &ets_query, NULL);
11329         if (ret != I40E_SUCCESS) {
11330                 PMD_DRV_LOG(ERR,
11331                         "Failed to get switch_comp ETS configuration %u",
11332                         hw->aq.asq_last_status);
11333                 return ret;
11334         }
11335         memset(&bw_query, 0, sizeof(bw_query));
11336         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11337                                                   &bw_query, NULL);
11338         if (ret != I40E_SUCCESS) {
11339                 PMD_DRV_LOG(ERR,
11340                         "Failed to get switch_comp bandwidth configuration %u",
11341                         hw->aq.asq_last_status);
11342                 return ret;
11343         }
11344
11345         /* store and print out BW info */
11346         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11347         veb->bw_info.bw_max = ets_query.tc_bw_max;
11348         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11349         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11350         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11351                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11352                      I40E_16_BIT_WIDTH);
11353         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11354                 veb->bw_info.bw_ets_share_credits[i] =
11355                                 bw_query.tc_bw_share_credits[i];
11356                 veb->bw_info.bw_ets_credits[i] =
11357                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11358                 /* 4 bits per TC, 4th bit is reserved */
11359                 veb->bw_info.bw_ets_max[i] =
11360                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11361                                   RTE_LEN2MASK(3, uint8_t));
11362                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11363                             veb->bw_info.bw_ets_share_credits[i]);
11364                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11365                             veb->bw_info.bw_ets_credits[i]);
11366                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11367                             veb->bw_info.bw_ets_max[i]);
11368         }
11369
11370         veb->enabled_tc = tc_map;
11371
11372         return ret;
11373 }
11374
11375
11376 /*
11377  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11378  * @vsi: VSI to be configured
11379  * @tc_map: enabled TC bitmap
11380  *
11381  * Returns 0 on success, negative value on failure
11382  */
11383 static enum i40e_status_code
11384 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11385 {
11386         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11387         struct i40e_vsi_context ctxt;
11388         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11389         enum i40e_status_code ret = I40E_SUCCESS;
11390         int i;
11391
11392         /* Check if enabled_tc is same as existing or new TCs */
11393         if (vsi->enabled_tc == tc_map)
11394                 return ret;
11395
11396         /* configure tc bandwidth */
11397         memset(&bw_data, 0, sizeof(bw_data));
11398         bw_data.tc_valid_bits = tc_map;
11399         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11400         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11401                 if (tc_map & BIT_ULL(i))
11402                         bw_data.tc_bw_credits[i] = 1;
11403         }
11404         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11405         if (ret) {
11406                 PMD_INIT_LOG(ERR,
11407                         "AQ command Config VSI BW allocation per TC failed = %d",
11408                         hw->aq.asq_last_status);
11409                 goto out;
11410         }
11411         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11412                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11413
11414         /* Update Queue Pairs Mapping for currently enabled UPs */
11415         ctxt.seid = vsi->seid;
11416         ctxt.pf_num = hw->pf_id;
11417         ctxt.vf_num = 0;
11418         ctxt.uplink_seid = vsi->uplink_seid;
11419         ctxt.info = vsi->info;
11420         i40e_get_cap(hw);
11421         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11422         if (ret)
11423                 goto out;
11424
11425         /* Update the VSI after updating the VSI queue-mapping information */
11426         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11427         if (ret) {
11428                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11429                         hw->aq.asq_last_status);
11430                 goto out;
11431         }
11432         /* update the local VSI info with updated queue map */
11433         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11434                                         sizeof(vsi->info.tc_mapping));
11435         rte_memcpy(&vsi->info.queue_mapping,
11436                         &ctxt.info.queue_mapping,
11437                 sizeof(vsi->info.queue_mapping));
11438         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11439         vsi->info.valid_sections = 0;
11440
11441         /* query and update current VSI BW information */
11442         ret = i40e_vsi_get_bw_config(vsi);
11443         if (ret) {
11444                 PMD_INIT_LOG(ERR,
11445                          "Failed updating vsi bw info, err %s aq_err %s",
11446                          i40e_stat_str(hw, ret),
11447                          i40e_aq_str(hw, hw->aq.asq_last_status));
11448                 goto out;
11449         }
11450
11451         vsi->enabled_tc = tc_map;
11452
11453 out:
11454         return ret;
11455 }
11456
11457 /*
11458  * i40e_dcb_hw_configure - program the dcb setting to hw
11459  * @pf: pf the configuration is taken on
11460  * @new_cfg: new configuration
11461  * @tc_map: enabled TC bitmap
11462  *
11463  * Returns 0 on success, negative value on failure
11464  */
11465 static enum i40e_status_code
11466 i40e_dcb_hw_configure(struct i40e_pf *pf,
11467                       struct i40e_dcbx_config *new_cfg,
11468                       uint8_t tc_map)
11469 {
11470         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11471         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11472         struct i40e_vsi *main_vsi = pf->main_vsi;
11473         struct i40e_vsi_list *vsi_list;
11474         enum i40e_status_code ret;
11475         int i;
11476         uint32_t val;
11477
11478         /* Use the FW API if FW > v4.4*/
11479         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11480               (hw->aq.fw_maj_ver >= 5))) {
11481                 PMD_INIT_LOG(ERR,
11482                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11483                 return I40E_ERR_FIRMWARE_API_VERSION;
11484         }
11485
11486         /* Check if need reconfiguration */
11487         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11488                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11489                 return I40E_SUCCESS;
11490         }
11491
11492         /* Copy the new config to the current config */
11493         *old_cfg = *new_cfg;
11494         old_cfg->etsrec = old_cfg->etscfg;
11495         ret = i40e_set_dcb_config(hw);
11496         if (ret) {
11497                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11498                          i40e_stat_str(hw, ret),
11499                          i40e_aq_str(hw, hw->aq.asq_last_status));
11500                 return ret;
11501         }
11502         /* set receive Arbiter to RR mode and ETS scheme by default */
11503         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11504                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11505                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11506                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11507                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11508                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11509                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11510                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11511                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11512                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11513                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11514                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11515                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11516         }
11517         /* get local mib to check whether it is configured correctly */
11518         /* IEEE mode */
11519         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11520         /* Get Local DCB Config */
11521         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11522                                      &hw->local_dcbx_config);
11523
11524         /* if Veb is created, need to update TC of it at first */
11525         if (main_vsi->veb) {
11526                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11527                 if (ret)
11528                         PMD_INIT_LOG(WARNING,
11529                                  "Failed configuring TC for VEB seid=%d",
11530                                  main_vsi->veb->seid);
11531         }
11532         /* Update each VSI */
11533         i40e_vsi_config_tc(main_vsi, tc_map);
11534         if (main_vsi->veb) {
11535                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11536                         /* Beside main VSI and VMDQ VSIs, only enable default
11537                          * TC for other VSIs
11538                          */
11539                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11540                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11541                                                          tc_map);
11542                         else
11543                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11544                                                          I40E_DEFAULT_TCMAP);
11545                         if (ret)
11546                                 PMD_INIT_LOG(WARNING,
11547                                         "Failed configuring TC for VSI seid=%d",
11548                                         vsi_list->vsi->seid);
11549                         /* continue */
11550                 }
11551         }
11552         return I40E_SUCCESS;
11553 }
11554
11555 /*
11556  * i40e_dcb_init_configure - initial dcb config
11557  * @dev: device being configured
11558  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11559  *
11560  * Returns 0 on success, negative value on failure
11561  */
11562 int
11563 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11564 {
11565         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11566         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11567         int i, ret = 0;
11568
11569         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11570                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11571                 return -ENOTSUP;
11572         }
11573
11574         /* DCB initialization:
11575          * Update DCB configuration from the Firmware and configure
11576          * LLDP MIB change event.
11577          */
11578         if (sw_dcb == TRUE) {
11579                 if (i40e_need_stop_lldp(dev)) {
11580                         ret = i40e_aq_stop_lldp(hw, TRUE, TRUE, NULL);
11581                         if (ret != I40E_SUCCESS)
11582                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11583                 }
11584
11585                 ret = i40e_init_dcb(hw, true);
11586                 /* If lldp agent is stopped, the return value from
11587                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11588                  * adminq status. Otherwise, it should return success.
11589                  */
11590                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11591                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11592                         memset(&hw->local_dcbx_config, 0,
11593                                 sizeof(struct i40e_dcbx_config));
11594                         /* set dcb default configuration */
11595                         hw->local_dcbx_config.etscfg.willing = 0;
11596                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11597                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11598                         hw->local_dcbx_config.etscfg.tsatable[0] =
11599                                                 I40E_IEEE_TSA_ETS;
11600                         /* all UPs mapping to TC0 */
11601                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11602                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11603                         hw->local_dcbx_config.etsrec =
11604                                 hw->local_dcbx_config.etscfg;
11605                         hw->local_dcbx_config.pfc.willing = 0;
11606                         hw->local_dcbx_config.pfc.pfccap =
11607                                                 I40E_MAX_TRAFFIC_CLASS;
11608                         /* FW needs one App to configure HW */
11609                         hw->local_dcbx_config.numapps = 1;
11610                         hw->local_dcbx_config.app[0].selector =
11611                                                 I40E_APP_SEL_ETHTYPE;
11612                         hw->local_dcbx_config.app[0].priority = 3;
11613                         hw->local_dcbx_config.app[0].protocolid =
11614                                                 I40E_APP_PROTOID_FCOE;
11615                         ret = i40e_set_dcb_config(hw);
11616                         if (ret) {
11617                                 PMD_INIT_LOG(ERR,
11618                                         "default dcb config fails. err = %d, aq_err = %d.",
11619                                         ret, hw->aq.asq_last_status);
11620                                 return -ENOSYS;
11621                         }
11622                 } else {
11623                         PMD_INIT_LOG(ERR,
11624                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11625                                 ret, hw->aq.asq_last_status);
11626                         return -ENOTSUP;
11627                 }
11628         } else {
11629                 ret = i40e_aq_start_lldp(hw, true, NULL);
11630                 if (ret != I40E_SUCCESS)
11631                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11632
11633                 ret = i40e_init_dcb(hw, true);
11634                 if (!ret) {
11635                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11636                                 PMD_INIT_LOG(ERR,
11637                                         "HW doesn't support DCBX offload.");
11638                                 return -ENOTSUP;
11639                         }
11640                 } else {
11641                         PMD_INIT_LOG(ERR,
11642                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11643                                 ret, hw->aq.asq_last_status);
11644                         return -ENOTSUP;
11645                 }
11646         }
11647         return 0;
11648 }
11649
11650 /*
11651  * i40e_dcb_setup - setup dcb related config
11652  * @dev: device being configured
11653  *
11654  * Returns 0 on success, negative value on failure
11655  */
11656 static int
11657 i40e_dcb_setup(struct rte_eth_dev *dev)
11658 {
11659         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11660         struct i40e_dcbx_config dcb_cfg;
11661         uint8_t tc_map = 0;
11662         int ret = 0;
11663
11664         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11665                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11666                 return -ENOTSUP;
11667         }
11668
11669         if (pf->vf_num != 0)
11670                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11671
11672         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11673         if (ret) {
11674                 PMD_INIT_LOG(ERR, "invalid dcb config");
11675                 return -EINVAL;
11676         }
11677         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11678         if (ret) {
11679                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11680                 return -ENOSYS;
11681         }
11682
11683         return 0;
11684 }
11685
11686 static int
11687 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11688                       struct rte_eth_dcb_info *dcb_info)
11689 {
11690         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11691         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11692         struct i40e_vsi *vsi = pf->main_vsi;
11693         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11694         uint16_t bsf, tc_mapping;
11695         int i, j = 0;
11696
11697         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11698                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11699         else
11700                 dcb_info->nb_tcs = 1;
11701         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11702                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11703         for (i = 0; i < dcb_info->nb_tcs; i++)
11704                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11705
11706         /* get queue mapping if vmdq is disabled */
11707         if (!pf->nb_cfg_vmdq_vsi) {
11708                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11709                         if (!(vsi->enabled_tc & (1 << i)))
11710                                 continue;
11711                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11712                         dcb_info->tc_queue.tc_rxq[j][i].base =
11713                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11714                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11715                         dcb_info->tc_queue.tc_txq[j][i].base =
11716                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11717                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11718                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11719                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11720                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11721                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11722                 }
11723                 return 0;
11724         }
11725
11726         /* get queue mapping if vmdq is enabled */
11727         do {
11728                 vsi = pf->vmdq[j].vsi;
11729                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11730                         if (!(vsi->enabled_tc & (1 << i)))
11731                                 continue;
11732                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11733                         dcb_info->tc_queue.tc_rxq[j][i].base =
11734                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11735                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11736                         dcb_info->tc_queue.tc_txq[j][i].base =
11737                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11738                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11739                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11740                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11741                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11742                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11743                 }
11744                 j++;
11745         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11746         return 0;
11747 }
11748
11749 static int
11750 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11751 {
11752         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11753         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11754         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11755         uint16_t msix_intr;
11756
11757         msix_intr = intr_handle->intr_vec[queue_id];
11758         if (msix_intr == I40E_MISC_VEC_ID)
11759                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11760                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11761                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11762                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11763         else
11764                 I40E_WRITE_REG(hw,
11765                                I40E_PFINT_DYN_CTLN(msix_intr -
11766                                                    I40E_RX_VEC_START),
11767                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11768                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11769                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11770
11771         I40E_WRITE_FLUSH(hw);
11772         rte_intr_ack(&pci_dev->intr_handle);
11773
11774         return 0;
11775 }
11776
11777 static int
11778 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11779 {
11780         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11781         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11782         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11783         uint16_t msix_intr;
11784
11785         msix_intr = intr_handle->intr_vec[queue_id];
11786         if (msix_intr == I40E_MISC_VEC_ID)
11787                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11788                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11789         else
11790                 I40E_WRITE_REG(hw,
11791                                I40E_PFINT_DYN_CTLN(msix_intr -
11792                                                    I40E_RX_VEC_START),
11793                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11794         I40E_WRITE_FLUSH(hw);
11795
11796         return 0;
11797 }
11798
11799 /**
11800  * This function is used to check if the register is valid.
11801  * Below is the valid registers list for X722 only:
11802  * 0x2b800--0x2bb00
11803  * 0x38700--0x38a00
11804  * 0x3d800--0x3db00
11805  * 0x208e00--0x209000
11806  * 0x20be00--0x20c000
11807  * 0x263c00--0x264000
11808  * 0x265c00--0x266000
11809  */
11810 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11811 {
11812         if ((type != I40E_MAC_X722) &&
11813             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11814              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11815              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11816              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11817              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11818              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11819              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11820                 return 0;
11821         else
11822                 return 1;
11823 }
11824
11825 static int i40e_get_regs(struct rte_eth_dev *dev,
11826                          struct rte_dev_reg_info *regs)
11827 {
11828         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11829         uint32_t *ptr_data = regs->data;
11830         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11831         const struct i40e_reg_info *reg_info;
11832
11833         if (ptr_data == NULL) {
11834                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11835                 regs->width = sizeof(uint32_t);
11836                 return 0;
11837         }
11838
11839         /* The first few registers have to be read using AQ operations */
11840         reg_idx = 0;
11841         while (i40e_regs_adminq[reg_idx].name) {
11842                 reg_info = &i40e_regs_adminq[reg_idx++];
11843                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11844                         for (arr_idx2 = 0;
11845                                         arr_idx2 <= reg_info->count2;
11846                                         arr_idx2++) {
11847                                 reg_offset = arr_idx * reg_info->stride1 +
11848                                         arr_idx2 * reg_info->stride2;
11849                                 reg_offset += reg_info->base_addr;
11850                                 ptr_data[reg_offset >> 2] =
11851                                         i40e_read_rx_ctl(hw, reg_offset);
11852                         }
11853         }
11854
11855         /* The remaining registers can be read using primitives */
11856         reg_idx = 0;
11857         while (i40e_regs_others[reg_idx].name) {
11858                 reg_info = &i40e_regs_others[reg_idx++];
11859                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11860                         for (arr_idx2 = 0;
11861                                         arr_idx2 <= reg_info->count2;
11862                                         arr_idx2++) {
11863                                 reg_offset = arr_idx * reg_info->stride1 +
11864                                         arr_idx2 * reg_info->stride2;
11865                                 reg_offset += reg_info->base_addr;
11866                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11867                                         ptr_data[reg_offset >> 2] = 0;
11868                                 else
11869                                         ptr_data[reg_offset >> 2] =
11870                                                 I40E_READ_REG(hw, reg_offset);
11871                         }
11872         }
11873
11874         return 0;
11875 }
11876
11877 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11878 {
11879         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11880
11881         /* Convert word count to byte count */
11882         return hw->nvm.sr_size << 1;
11883 }
11884
11885 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11886                            struct rte_dev_eeprom_info *eeprom)
11887 {
11888         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11889         uint16_t *data = eeprom->data;
11890         uint16_t offset, length, cnt_words;
11891         int ret_code;
11892
11893         offset = eeprom->offset >> 1;
11894         length = eeprom->length >> 1;
11895         cnt_words = length;
11896
11897         if (offset > hw->nvm.sr_size ||
11898                 offset + length > hw->nvm.sr_size) {
11899                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11900                 return -EINVAL;
11901         }
11902
11903         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11904
11905         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11906         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11907                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11908                 return -EIO;
11909         }
11910
11911         return 0;
11912 }
11913
11914 static int i40e_get_module_info(struct rte_eth_dev *dev,
11915                                 struct rte_eth_dev_module_info *modinfo)
11916 {
11917         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11918         uint32_t sff8472_comp = 0;
11919         uint32_t sff8472_swap = 0;
11920         uint32_t sff8636_rev = 0;
11921         i40e_status status;
11922         uint32_t type = 0;
11923
11924         /* Check if firmware supports reading module EEPROM. */
11925         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11926                 PMD_DRV_LOG(ERR,
11927                             "Module EEPROM memory read not supported. "
11928                             "Please update the NVM image.\n");
11929                 return -EINVAL;
11930         }
11931
11932         status = i40e_update_link_info(hw);
11933         if (status)
11934                 return -EIO;
11935
11936         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11937                 PMD_DRV_LOG(ERR,
11938                             "Cannot read module EEPROM memory. "
11939                             "No module connected.\n");
11940                 return -EINVAL;
11941         }
11942
11943         type = hw->phy.link_info.module_type[0];
11944
11945         switch (type) {
11946         case I40E_MODULE_TYPE_SFP:
11947                 status = i40e_aq_get_phy_register(hw,
11948                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11949                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11950                                 I40E_MODULE_SFF_8472_COMP,
11951                                 &sff8472_comp, NULL);
11952                 if (status)
11953                         return -EIO;
11954
11955                 status = i40e_aq_get_phy_register(hw,
11956                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11957                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11958                                 I40E_MODULE_SFF_8472_SWAP,
11959                                 &sff8472_swap, NULL);
11960                 if (status)
11961                         return -EIO;
11962
11963                 /* Check if the module requires address swap to access
11964                  * the other EEPROM memory page.
11965                  */
11966                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11967                         PMD_DRV_LOG(WARNING,
11968                                     "Module address swap to access "
11969                                     "page 0xA2 is not supported.\n");
11970                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11971                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11972                 } else if (sff8472_comp == 0x00) {
11973                         /* Module is not SFF-8472 compliant */
11974                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11975                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11976                 } else {
11977                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11978                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11979                 }
11980                 break;
11981         case I40E_MODULE_TYPE_QSFP_PLUS:
11982                 /* Read from memory page 0. */
11983                 status = i40e_aq_get_phy_register(hw,
11984                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11985                                 0, 1,
11986                                 I40E_MODULE_REVISION_ADDR,
11987                                 &sff8636_rev, NULL);
11988                 if (status)
11989                         return -EIO;
11990                 /* Determine revision compliance byte */
11991                 if (sff8636_rev > 0x02) {
11992                         /* Module is SFF-8636 compliant */
11993                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11994                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11995                 } else {
11996                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11997                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11998                 }
11999                 break;
12000         case I40E_MODULE_TYPE_QSFP28:
12001                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12002                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12003                 break;
12004         default:
12005                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12006                 return -EINVAL;
12007         }
12008         return 0;
12009 }
12010
12011 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12012                                   struct rte_dev_eeprom_info *info)
12013 {
12014         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12015         bool is_sfp = false;
12016         i40e_status status;
12017         uint8_t *data;
12018         uint32_t value = 0;
12019         uint32_t i;
12020
12021         if (!info || !info->length || !info->data)
12022                 return -EINVAL;
12023
12024         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12025                 is_sfp = true;
12026
12027         data = info->data;
12028         for (i = 0; i < info->length; i++) {
12029                 u32 offset = i + info->offset;
12030                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12031
12032                 /* Check if we need to access the other memory page */
12033                 if (is_sfp) {
12034                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12035                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12036                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12037                         }
12038                 } else {
12039                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12040                                 /* Compute memory page number and offset. */
12041                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12042                                 addr++;
12043                         }
12044                 }
12045                 status = i40e_aq_get_phy_register(hw,
12046                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12047                                 addr, offset, 1, &value, NULL);
12048                 if (status)
12049                         return -EIO;
12050                 data[i] = (uint8_t)value;
12051         }
12052         return 0;
12053 }
12054
12055 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12056                                      struct rte_ether_addr *mac_addr)
12057 {
12058         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12059         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12060         struct i40e_vsi *vsi = pf->main_vsi;
12061         struct i40e_mac_filter_info mac_filter;
12062         struct i40e_mac_filter *f;
12063         int ret;
12064
12065         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12066                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12067                 return -EINVAL;
12068         }
12069
12070         TAILQ_FOREACH(f, &vsi->mac_list, next) {
12071                 if (rte_is_same_ether_addr(&pf->dev_addr,
12072                                                 &f->mac_info.mac_addr))
12073                         break;
12074         }
12075
12076         if (f == NULL) {
12077                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12078                 return -EIO;
12079         }
12080
12081         mac_filter = f->mac_info;
12082         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12083         if (ret != I40E_SUCCESS) {
12084                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12085                 return -EIO;
12086         }
12087         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12088         ret = i40e_vsi_add_mac(vsi, &mac_filter);
12089         if (ret != I40E_SUCCESS) {
12090                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12091                 return -EIO;
12092         }
12093         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12094
12095         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12096                                         mac_addr->addr_bytes, NULL);
12097         if (ret != I40E_SUCCESS) {
12098                 PMD_DRV_LOG(ERR, "Failed to change mac");
12099                 return -EIO;
12100         }
12101
12102         return 0;
12103 }
12104
12105 static int
12106 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12107 {
12108         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12109         struct rte_eth_dev_data *dev_data = pf->dev_data;
12110         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12111         int ret = 0;
12112
12113         /* check if mtu is within the allowed range */
12114         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12115                 return -EINVAL;
12116
12117         /* mtu setting is forbidden if port is start */
12118         if (dev_data->dev_started) {
12119                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12120                             dev_data->port_id);
12121                 return -EBUSY;
12122         }
12123
12124         if (frame_size > RTE_ETHER_MAX_LEN)
12125                 dev_data->dev_conf.rxmode.offloads |=
12126                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12127         else
12128                 dev_data->dev_conf.rxmode.offloads &=
12129                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12130
12131         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12132
12133         return ret;
12134 }
12135
12136 /* Restore ethertype filter */
12137 static void
12138 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12139 {
12140         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12141         struct i40e_ethertype_filter_list
12142                 *ethertype_list = &pf->ethertype.ethertype_list;
12143         struct i40e_ethertype_filter *f;
12144         struct i40e_control_filter_stats stats;
12145         uint16_t flags;
12146
12147         TAILQ_FOREACH(f, ethertype_list, rules) {
12148                 flags = 0;
12149                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12150                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12151                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12152                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12153                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12154
12155                 memset(&stats, 0, sizeof(stats));
12156                 i40e_aq_add_rem_control_packet_filter(hw,
12157                                             f->input.mac_addr.addr_bytes,
12158                                             f->input.ether_type,
12159                                             flags, pf->main_vsi->seid,
12160                                             f->queue, 1, &stats, NULL);
12161         }
12162         PMD_DRV_LOG(INFO, "Ethertype filter:"
12163                     " mac_etype_used = %u, etype_used = %u,"
12164                     " mac_etype_free = %u, etype_free = %u",
12165                     stats.mac_etype_used, stats.etype_used,
12166                     stats.mac_etype_free, stats.etype_free);
12167 }
12168
12169 /* Restore tunnel filter */
12170 static void
12171 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12172 {
12173         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12174         struct i40e_vsi *vsi;
12175         struct i40e_pf_vf *vf;
12176         struct i40e_tunnel_filter_list
12177                 *tunnel_list = &pf->tunnel.tunnel_list;
12178         struct i40e_tunnel_filter *f;
12179         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12180         bool big_buffer = 0;
12181
12182         TAILQ_FOREACH(f, tunnel_list, rules) {
12183                 if (!f->is_to_vf)
12184                         vsi = pf->main_vsi;
12185                 else {
12186                         vf = &pf->vfs[f->vf_id];
12187                         vsi = vf->vsi;
12188                 }
12189                 memset(&cld_filter, 0, sizeof(cld_filter));
12190                 rte_ether_addr_copy((struct rte_ether_addr *)
12191                                 &f->input.outer_mac,
12192                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12193                 rte_ether_addr_copy((struct rte_ether_addr *)
12194                                 &f->input.inner_mac,
12195                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12196                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12197                 cld_filter.element.flags = f->input.flags;
12198                 cld_filter.element.tenant_id = f->input.tenant_id;
12199                 cld_filter.element.queue_number = f->queue;
12200                 rte_memcpy(cld_filter.general_fields,
12201                            f->input.general_fields,
12202                            sizeof(f->input.general_fields));
12203
12204                 if (((f->input.flags &
12205                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12206                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12207                     ((f->input.flags &
12208                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12209                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12210                     ((f->input.flags &
12211                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12212                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12213                         big_buffer = 1;
12214
12215                 if (big_buffer)
12216                         i40e_aq_add_cloud_filters_bb(hw,
12217                                         vsi->seid, &cld_filter, 1);
12218                 else
12219                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12220                                                   &cld_filter.element, 1);
12221         }
12222 }
12223
12224 /* Restore rss filter */
12225 static inline void
12226 i40e_rss_filter_restore(struct i40e_pf *pf)
12227 {
12228         struct i40e_rte_flow_rss_conf *conf =
12229                                         &pf->rss_info;
12230         if (conf->conf.queue_num)
12231                 i40e_config_rss_filter(pf, conf, TRUE);
12232 }
12233
12234 static void
12235 i40e_filter_restore(struct i40e_pf *pf)
12236 {
12237         i40e_ethertype_filter_restore(pf);
12238         i40e_tunnel_filter_restore(pf);
12239         i40e_fdir_filter_restore(pf);
12240         i40e_rss_filter_restore(pf);
12241 }
12242
12243 bool
12244 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12245 {
12246         if (strcmp(dev->device->driver->name, drv->driver.name))
12247                 return false;
12248
12249         return true;
12250 }
12251
12252 bool
12253 is_i40e_supported(struct rte_eth_dev *dev)
12254 {
12255         return is_device_supported(dev, &rte_i40e_pmd);
12256 }
12257
12258 struct i40e_customized_pctype*
12259 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12260 {
12261         int i;
12262
12263         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12264                 if (pf->customized_pctype[i].index == index)
12265                         return &pf->customized_pctype[i];
12266         }
12267         return NULL;
12268 }
12269
12270 static int
12271 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12272                               uint32_t pkg_size, uint32_t proto_num,
12273                               struct rte_pmd_i40e_proto_info *proto,
12274                               enum rte_pmd_i40e_package_op op)
12275 {
12276         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12277         uint32_t pctype_num;
12278         struct rte_pmd_i40e_ptype_info *pctype;
12279         uint32_t buff_size;
12280         struct i40e_customized_pctype *new_pctype = NULL;
12281         uint8_t proto_id;
12282         uint8_t pctype_value;
12283         char name[64];
12284         uint32_t i, j, n;
12285         int ret;
12286
12287         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12288             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12289                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12290                 return -1;
12291         }
12292
12293         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12294                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12295                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12296         if (ret) {
12297                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12298                 return -1;
12299         }
12300         if (!pctype_num) {
12301                 PMD_DRV_LOG(INFO, "No new pctype added");
12302                 return -1;
12303         }
12304
12305         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12306         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12307         if (!pctype) {
12308                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12309                 return -1;
12310         }
12311         /* get information about new pctype list */
12312         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12313                                         (uint8_t *)pctype, buff_size,
12314                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12315         if (ret) {
12316                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12317                 rte_free(pctype);
12318                 return -1;
12319         }
12320
12321         /* Update customized pctype. */
12322         for (i = 0; i < pctype_num; i++) {
12323                 pctype_value = pctype[i].ptype_id;
12324                 memset(name, 0, sizeof(name));
12325                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12326                         proto_id = pctype[i].protocols[j];
12327                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12328                                 continue;
12329                         for (n = 0; n < proto_num; n++) {
12330                                 if (proto[n].proto_id != proto_id)
12331                                         continue;
12332                                 strlcat(name, proto[n].name, sizeof(name));
12333                                 strlcat(name, "_", sizeof(name));
12334                                 break;
12335                         }
12336                 }
12337                 name[strlen(name) - 1] = '\0';
12338                 if (!strcmp(name, "GTPC"))
12339                         new_pctype =
12340                                 i40e_find_customized_pctype(pf,
12341                                                       I40E_CUSTOMIZED_GTPC);
12342                 else if (!strcmp(name, "GTPU_IPV4"))
12343                         new_pctype =
12344                                 i40e_find_customized_pctype(pf,
12345                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12346                 else if (!strcmp(name, "GTPU_IPV6"))
12347                         new_pctype =
12348                                 i40e_find_customized_pctype(pf,
12349                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12350                 else if (!strcmp(name, "GTPU"))
12351                         new_pctype =
12352                                 i40e_find_customized_pctype(pf,
12353                                                       I40E_CUSTOMIZED_GTPU);
12354                 else if (!strcmp(name, "IPV4_L2TPV3"))
12355                         new_pctype =
12356                                 i40e_find_customized_pctype(pf,
12357                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
12358                 else if (!strcmp(name, "IPV6_L2TPV3"))
12359                         new_pctype =
12360                                 i40e_find_customized_pctype(pf,
12361                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
12362                 if (new_pctype) {
12363                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12364                                 new_pctype->pctype = pctype_value;
12365                                 new_pctype->valid = true;
12366                         } else {
12367                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12368                                 new_pctype->valid = false;
12369                         }
12370                 }
12371         }
12372
12373         rte_free(pctype);
12374         return 0;
12375 }
12376
12377 static int
12378 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12379                              uint32_t pkg_size, uint32_t proto_num,
12380                              struct rte_pmd_i40e_proto_info *proto,
12381                              enum rte_pmd_i40e_package_op op)
12382 {
12383         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12384         uint16_t port_id = dev->data->port_id;
12385         uint32_t ptype_num;
12386         struct rte_pmd_i40e_ptype_info *ptype;
12387         uint32_t buff_size;
12388         uint8_t proto_id;
12389         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12390         uint32_t i, j, n;
12391         bool in_tunnel;
12392         int ret;
12393
12394         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12395             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12396                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12397                 return -1;
12398         }
12399
12400         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12401                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12402                 return 0;
12403         }
12404
12405         /* get information about new ptype num */
12406         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12407                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12408                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12409         if (ret) {
12410                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12411                 return ret;
12412         }
12413         if (!ptype_num) {
12414                 PMD_DRV_LOG(INFO, "No new ptype added");
12415                 return -1;
12416         }
12417
12418         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12419         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12420         if (!ptype) {
12421                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12422                 return -1;
12423         }
12424
12425         /* get information about new ptype list */
12426         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12427                                         (uint8_t *)ptype, buff_size,
12428                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12429         if (ret) {
12430                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12431                 rte_free(ptype);
12432                 return ret;
12433         }
12434
12435         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12436         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12437         if (!ptype_mapping) {
12438                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12439                 rte_free(ptype);
12440                 return -1;
12441         }
12442
12443         /* Update ptype mapping table. */
12444         for (i = 0; i < ptype_num; i++) {
12445                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12446                 ptype_mapping[i].sw_ptype = 0;
12447                 in_tunnel = false;
12448                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12449                         proto_id = ptype[i].protocols[j];
12450                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12451                                 continue;
12452                         for (n = 0; n < proto_num; n++) {
12453                                 if (proto[n].proto_id != proto_id)
12454                                         continue;
12455                                 memset(name, 0, sizeof(name));
12456                                 strcpy(name, proto[n].name);
12457                                 if (!strncasecmp(name, "PPPOE", 5))
12458                                         ptype_mapping[i].sw_ptype |=
12459                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12460                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12461                                          !in_tunnel) {
12462                                         ptype_mapping[i].sw_ptype |=
12463                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12464                                         ptype_mapping[i].sw_ptype |=
12465                                                 RTE_PTYPE_L4_FRAG;
12466                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12467                                            in_tunnel) {
12468                                         ptype_mapping[i].sw_ptype |=
12469                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12470                                         ptype_mapping[i].sw_ptype |=
12471                                                 RTE_PTYPE_INNER_L4_FRAG;
12472                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12473                                         ptype_mapping[i].sw_ptype |=
12474                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12475                                         in_tunnel = true;
12476                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12477                                            !in_tunnel)
12478                                         ptype_mapping[i].sw_ptype |=
12479                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12480                                 else if (!strncasecmp(name, "IPV4", 4) &&
12481                                          in_tunnel)
12482                                         ptype_mapping[i].sw_ptype |=
12483                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12484                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12485                                          !in_tunnel) {
12486                                         ptype_mapping[i].sw_ptype |=
12487                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12488                                         ptype_mapping[i].sw_ptype |=
12489                                                 RTE_PTYPE_L4_FRAG;
12490                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12491                                            in_tunnel) {
12492                                         ptype_mapping[i].sw_ptype |=
12493                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12494                                         ptype_mapping[i].sw_ptype |=
12495                                                 RTE_PTYPE_INNER_L4_FRAG;
12496                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12497                                         ptype_mapping[i].sw_ptype |=
12498                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12499                                         in_tunnel = true;
12500                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12501                                            !in_tunnel)
12502                                         ptype_mapping[i].sw_ptype |=
12503                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12504                                 else if (!strncasecmp(name, "IPV6", 4) &&
12505                                          in_tunnel)
12506                                         ptype_mapping[i].sw_ptype |=
12507                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12508                                 else if (!strncasecmp(name, "UDP", 3) &&
12509                                          !in_tunnel)
12510                                         ptype_mapping[i].sw_ptype |=
12511                                                 RTE_PTYPE_L4_UDP;
12512                                 else if (!strncasecmp(name, "UDP", 3) &&
12513                                          in_tunnel)
12514                                         ptype_mapping[i].sw_ptype |=
12515                                                 RTE_PTYPE_INNER_L4_UDP;
12516                                 else if (!strncasecmp(name, "TCP", 3) &&
12517                                          !in_tunnel)
12518                                         ptype_mapping[i].sw_ptype |=
12519                                                 RTE_PTYPE_L4_TCP;
12520                                 else if (!strncasecmp(name, "TCP", 3) &&
12521                                          in_tunnel)
12522                                         ptype_mapping[i].sw_ptype |=
12523                                                 RTE_PTYPE_INNER_L4_TCP;
12524                                 else if (!strncasecmp(name, "SCTP", 4) &&
12525                                          !in_tunnel)
12526                                         ptype_mapping[i].sw_ptype |=
12527                                                 RTE_PTYPE_L4_SCTP;
12528                                 else if (!strncasecmp(name, "SCTP", 4) &&
12529                                          in_tunnel)
12530                                         ptype_mapping[i].sw_ptype |=
12531                                                 RTE_PTYPE_INNER_L4_SCTP;
12532                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12533                                           !strncasecmp(name, "ICMPV6", 6)) &&
12534                                          !in_tunnel)
12535                                         ptype_mapping[i].sw_ptype |=
12536                                                 RTE_PTYPE_L4_ICMP;
12537                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12538                                           !strncasecmp(name, "ICMPV6", 6)) &&
12539                                          in_tunnel)
12540                                         ptype_mapping[i].sw_ptype |=
12541                                                 RTE_PTYPE_INNER_L4_ICMP;
12542                                 else if (!strncasecmp(name, "GTPC", 4)) {
12543                                         ptype_mapping[i].sw_ptype |=
12544                                                 RTE_PTYPE_TUNNEL_GTPC;
12545                                         in_tunnel = true;
12546                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12547                                         ptype_mapping[i].sw_ptype |=
12548                                                 RTE_PTYPE_TUNNEL_GTPU;
12549                                         in_tunnel = true;
12550                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12551                                         ptype_mapping[i].sw_ptype |=
12552                                                 RTE_PTYPE_TUNNEL_GRENAT;
12553                                         in_tunnel = true;
12554                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12555                                            !strncasecmp(name, "L2TPV2", 6) ||
12556                                            !strncasecmp(name, "L2TPV3", 6)) {
12557                                         ptype_mapping[i].sw_ptype |=
12558                                                 RTE_PTYPE_TUNNEL_L2TP;
12559                                         in_tunnel = true;
12560                                 }
12561
12562                                 break;
12563                         }
12564                 }
12565         }
12566
12567         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12568                                                 ptype_num, 0);
12569         if (ret)
12570                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12571
12572         rte_free(ptype_mapping);
12573         rte_free(ptype);
12574         return ret;
12575 }
12576
12577 void
12578 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12579                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12580 {
12581         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12582         uint32_t proto_num;
12583         struct rte_pmd_i40e_proto_info *proto;
12584         uint32_t buff_size;
12585         uint32_t i;
12586         int ret;
12587
12588         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12589             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12590                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12591                 return;
12592         }
12593
12594         /* get information about protocol number */
12595         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12596                                        (uint8_t *)&proto_num, sizeof(proto_num),
12597                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12598         if (ret) {
12599                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12600                 return;
12601         }
12602         if (!proto_num) {
12603                 PMD_DRV_LOG(INFO, "No new protocol added");
12604                 return;
12605         }
12606
12607         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12608         proto = rte_zmalloc("new_proto", buff_size, 0);
12609         if (!proto) {
12610                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12611                 return;
12612         }
12613
12614         /* get information about protocol list */
12615         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12616                                         (uint8_t *)proto, buff_size,
12617                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12618         if (ret) {
12619                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12620                 rte_free(proto);
12621                 return;
12622         }
12623
12624         /* Check if GTP is supported. */
12625         for (i = 0; i < proto_num; i++) {
12626                 if (!strncmp(proto[i].name, "GTP", 3)) {
12627                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12628                                 pf->gtp_support = true;
12629                         else
12630                                 pf->gtp_support = false;
12631                         break;
12632                 }
12633         }
12634
12635         /* Update customized pctype info */
12636         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12637                                             proto_num, proto, op);
12638         if (ret)
12639                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12640
12641         /* Update customized ptype info */
12642         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12643                                            proto_num, proto, op);
12644         if (ret)
12645                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12646
12647         rte_free(proto);
12648 }
12649
12650 /* Create a QinQ cloud filter
12651  *
12652  * The Fortville NIC has limited resources for tunnel filters,
12653  * so we can only reuse existing filters.
12654  *
12655  * In step 1 we define which Field Vector fields can be used for
12656  * filter types.
12657  * As we do not have the inner tag defined as a field,
12658  * we have to define it first, by reusing one of L1 entries.
12659  *
12660  * In step 2 we are replacing one of existing filter types with
12661  * a new one for QinQ.
12662  * As we reusing L1 and replacing L2, some of the default filter
12663  * types will disappear,which depends on L1 and L2 entries we reuse.
12664  *
12665  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12666  *
12667  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12668  *              later when we define the cloud filter.
12669  *      a.      Valid_flags.replace_cloud = 0
12670  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12671  *      c.      New_filter = 0x10
12672  *      d.      TR bit = 0xff (optional, not used here)
12673  *      e.      Buffer – 2 entries:
12674  *              i.      Byte 0 = 8 (outer vlan FV index).
12675  *                      Byte 1 = 0 (rsv)
12676  *                      Byte 2-3 = 0x0fff
12677  *              ii.     Byte 0 = 37 (inner vlan FV index).
12678  *                      Byte 1 =0 (rsv)
12679  *                      Byte 2-3 = 0x0fff
12680  *
12681  * Step 2:
12682  * 2.   Create cloud filter using two L1 filters entries: stag and
12683  *              new filter(outer vlan+ inner vlan)
12684  *      a.      Valid_flags.replace_cloud = 1
12685  *      b.      Old_filter = 1 (instead of outer IP)
12686  *      c.      New_filter = 0x10
12687  *      d.      Buffer – 2 entries:
12688  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12689  *                      Byte 1-3 = 0 (rsv)
12690  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12691  *                      Byte 9-11 = 0 (rsv)
12692  */
12693 static int
12694 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12695 {
12696         int ret = -ENOTSUP;
12697         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12698         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12699         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12700         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12701
12702         if (pf->support_multi_driver) {
12703                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12704                 return ret;
12705         }
12706
12707         /* Init */
12708         memset(&filter_replace, 0,
12709                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12710         memset(&filter_replace_buf, 0,
12711                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12712
12713         /* create L1 filter */
12714         filter_replace.old_filter_type =
12715                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12716         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12717         filter_replace.tr_bit = 0;
12718
12719         /* Prepare the buffer, 2 entries */
12720         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12721         filter_replace_buf.data[0] |=
12722                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12723         /* Field Vector 12b mask */
12724         filter_replace_buf.data[2] = 0xff;
12725         filter_replace_buf.data[3] = 0x0f;
12726         filter_replace_buf.data[4] =
12727                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12728         filter_replace_buf.data[4] |=
12729                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12730         /* Field Vector 12b mask */
12731         filter_replace_buf.data[6] = 0xff;
12732         filter_replace_buf.data[7] = 0x0f;
12733         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12734                         &filter_replace_buf);
12735         if (ret != I40E_SUCCESS)
12736                 return ret;
12737
12738         if (filter_replace.old_filter_type !=
12739             filter_replace.new_filter_type)
12740                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12741                             " original: 0x%x, new: 0x%x",
12742                             dev->device->name,
12743                             filter_replace.old_filter_type,
12744                             filter_replace.new_filter_type);
12745
12746         /* Apply the second L2 cloud filter */
12747         memset(&filter_replace, 0,
12748                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12749         memset(&filter_replace_buf, 0,
12750                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12751
12752         /* create L2 filter, input for L2 filter will be L1 filter  */
12753         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12754         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12755         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12756
12757         /* Prepare the buffer, 2 entries */
12758         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12759         filter_replace_buf.data[0] |=
12760                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12761         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12762         filter_replace_buf.data[4] |=
12763                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12764         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12765                         &filter_replace_buf);
12766         if (!ret && (filter_replace.old_filter_type !=
12767                      filter_replace.new_filter_type))
12768                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12769                             " original: 0x%x, new: 0x%x",
12770                             dev->device->name,
12771                             filter_replace.old_filter_type,
12772                             filter_replace.new_filter_type);
12773
12774         return ret;
12775 }
12776
12777 int
12778 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12779                    const struct rte_flow_action_rss *in)
12780 {
12781         if (in->key_len > RTE_DIM(out->key) ||
12782             in->queue_num > RTE_DIM(out->queue))
12783                 return -EINVAL;
12784         if (!in->key && in->key_len)
12785                 return -EINVAL;
12786         out->conf = (struct rte_flow_action_rss){
12787                 .func = in->func,
12788                 .level = in->level,
12789                 .types = in->types,
12790                 .key_len = in->key_len,
12791                 .queue_num = in->queue_num,
12792                 .queue = memcpy(out->queue, in->queue,
12793                                 sizeof(*in->queue) * in->queue_num),
12794         };
12795         if (in->key)
12796                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12797         return 0;
12798 }
12799
12800 int
12801 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12802                      const struct rte_flow_action_rss *with)
12803 {
12804         return (comp->func == with->func &&
12805                 comp->level == with->level &&
12806                 comp->types == with->types &&
12807                 comp->key_len == with->key_len &&
12808                 comp->queue_num == with->queue_num &&
12809                 !memcmp(comp->key, with->key, with->key_len) &&
12810                 !memcmp(comp->queue, with->queue,
12811                         sizeof(*with->queue) * with->queue_num));
12812 }
12813
12814 int
12815 i40e_config_rss_filter(struct i40e_pf *pf,
12816                 struct i40e_rte_flow_rss_conf *conf, bool add)
12817 {
12818         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12819         uint32_t i, lut = 0;
12820         uint16_t j, num;
12821         struct rte_eth_rss_conf rss_conf = {
12822                 .rss_key = conf->conf.key_len ?
12823                         (void *)(uintptr_t)conf->conf.key : NULL,
12824                 .rss_key_len = conf->conf.key_len,
12825                 .rss_hf = conf->conf.types,
12826         };
12827         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12828
12829         if (!add) {
12830                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12831                         i40e_pf_disable_rss(pf);
12832                         memset(rss_info, 0,
12833                                 sizeof(struct i40e_rte_flow_rss_conf));
12834                         return 0;
12835                 }
12836                 return -EINVAL;
12837         }
12838
12839         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12840          * It's necessary to calculate the actual PF queues that are configured.
12841          */
12842         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12843                 num = i40e_pf_calc_configured_queues_num(pf);
12844         else
12845                 num = pf->dev_data->nb_rx_queues;
12846
12847         num = RTE_MIN(num, conf->conf.queue_num);
12848         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12849                         num);
12850
12851         if (num == 0) {
12852                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12853                 return -ENOTSUP;
12854         }
12855
12856         /* Fill in redirection table */
12857         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12858                 if (j == num)
12859                         j = 0;
12860                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12861                         hw->func_caps.rss_table_entry_width) - 1));
12862                 if ((i & 3) == 3)
12863                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12864         }
12865
12866         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12867                 i40e_pf_disable_rss(pf);
12868                 return 0;
12869         }
12870         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12871                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12872                 /* Random default keys */
12873                 static uint32_t rss_key_default[] = {0x6b793944,
12874                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12875                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12876                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12877
12878                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12879                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12880                                                         sizeof(uint32_t);
12881                 PMD_DRV_LOG(INFO,
12882                         "No valid RSS key config for i40e, using default\n");
12883         }
12884
12885         i40e_hw_rss_hash_set(pf, &rss_conf);
12886
12887         if (i40e_rss_conf_init(rss_info, &conf->conf))
12888                 return -EINVAL;
12889
12890         return 0;
12891 }
12892
12893 RTE_INIT(i40e_init_log)
12894 {
12895         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12896         if (i40e_logtype_init >= 0)
12897                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12898         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12899         if (i40e_logtype_driver >= 0)
12900                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12901
12902 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
12903         i40e_logtype_rx = rte_log_register("pmd.net.i40e.rx");
12904         if (i40e_logtype_rx >= 0)
12905                 rte_log_set_level(i40e_logtype_rx, RTE_LOG_DEBUG);
12906 #endif
12907
12908 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
12909         i40e_logtype_tx = rte_log_register("pmd.net.i40e.tx");
12910         if (i40e_logtype_tx >= 0)
12911                 rte_log_set_level(i40e_logtype_tx, RTE_LOG_DEBUG);
12912 #endif
12913
12914 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
12915         i40e_logtype_tx_free = rte_log_register("pmd.net.i40e.tx_free");
12916         if (i40e_logtype_tx_free >= 0)
12917                 rte_log_set_level(i40e_logtype_tx_free, RTE_LOG_DEBUG);
12918 #endif
12919 }
12920
12921 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12922                               ETH_I40E_FLOATING_VEB_ARG "=1"
12923                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12924                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12925                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12926                               ETH_I40E_USE_LATEST_VEC "=0|1");